93394f15ba
mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
115 lines
3.2 KiB
C
115 lines
3.2 KiB
C
/*-
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* Copyright (c) 2007 Bruce M. Simpson.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Child driver for SDRAM/DDR controller core.
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* Generally the OS should not need to access this device unless the
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* firmware has not configured the SDRAM controller.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/malloc.h>
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#include <machine/bus.h>
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#include <dev/siba/sibavar.h>
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#include <dev/siba/sibareg.h>
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#include <dev/siba/siba_ids.h>
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static int siba_sdram_attach(device_t);
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static int siba_sdram_probe(device_t);
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static int
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siba_sdram_probe(device_t dev)
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{
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if (siba_get_vendor(dev) == SIBA_VID_BROADCOM &&
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siba_get_device(dev) == SIBA_DEVID_SDRAMDDR) {
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device_set_desc(dev, "SDRAM/DDR core");
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return (BUS_PROBE_DEFAULT);
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}
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return (ENXIO);
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}
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struct siba_sdram_softc {
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void *notused;
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};
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static int
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siba_sdram_attach(device_t dev)
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{
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//struct siba_sdram_softc *sc = device_get_softc(dev);
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struct resource *mem;
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int rid;
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/*
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* Allocate the resources which the parent bus has already
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* determined for us.
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* TODO: interrupt routing
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*/
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#define MIPS_MEM_RID 0x20
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rid = MIPS_MEM_RID;
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mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (mem == NULL) {
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device_printf(dev, "unable to allocate memory\n");
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return (ENXIO);
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}
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#if 0
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device_printf(dev, "start %08lx size %04lx\n",
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rman_get_start(mem), rman_get_size(mem));
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#endif
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return (0);
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}
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static device_method_t siba_sdram_methods[] = {
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/* Device interface */
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DEVMETHOD(device_attach, siba_sdram_attach),
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DEVMETHOD(device_probe, siba_sdram_probe),
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{0, 0},
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};
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static driver_t siba_sdram_driver = {
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"siba_sdram",
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siba_sdram_methods,
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sizeof(struct siba_softc),
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};
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static devclass_t siba_sdram_devclass;
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DRIVER_MODULE(siba_sdram, siba, siba_sdram_driver, siba_sdram_devclass, 0, 0);
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