157 lines
4.7 KiB
Groff
157 lines
4.7 KiB
Groff
.\" Copyright (c) 2009, 2010 Rui Paulo. All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" This software is provided by Rui Paulo ``as is'' and
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.\" any express or implied warranties, including, but not limited to, the
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.\" implied warranties of merchantability and fitness for a particular purpose
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.\" are disclaimed. in no event shall Joseph Koshy be liable
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.\" for any direct, indirect, incidental, special, exemplary, or consequential
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.\" damages (including, but not limited to, procurement of substitute goods
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.\" or services; loss of use, data, or profits; or business interruption)
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.\" however caused and on any theory of liability, whether in contract, strict
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.\" liability, or tort (including negligence or otherwise) arising in any way
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.\" out of the use of this software, even if advised of the possibility of
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.\" such damage.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd December 23, 2009
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.Dt PMC.XSCALE 3
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.Os
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.Sh NAME
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.Nm pmc.xscale
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.Nd measurement events for
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.Tn Intel
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.Tn XScale
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family CPUs
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.Sh LIBRARY
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.Lb libpmc
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.Sh SYNOPSIS
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.In pmc.h
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.Sh DESCRIPTION
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.Tn Intel XScale
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CPUs are ARM CPUs based on the ARMv5e core.
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.Pp
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Second generation cores have 2 counters, while third generation cores
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have 4 counters.
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Third generation cores also have an increased number of PMC events.
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.Pp
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.Tn Intel XScale
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PMCs are documented in
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.Rs
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.%B "3rd Generation Intel XScale Microarchitecture Developer's Manual"
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.%D May 2007
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.Re
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.Ss Event Specifiers (Programmable PMCs)
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.Tn Intel XScale
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programmable PMCs support the following events:
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.Bl -tag -width indent
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.It Li IC_FETCH
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External memory fetch due to L1 instruction cache miss.
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.It Li IC_MISS
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Instruction cache or TLB miss.
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.It Li DATA_DEPENDENCY_STALLED
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A data dependency stalled
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.It Li ITLB_MISS
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Instruction TLB miss.
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.It Li DTLB_MISS
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Data TLB miss.
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.It Li BRANCH_RETIRED
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Branch instruction retired (executed).
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.It Li BRANCH_MISPRED
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Branch mispredicted.
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.It Li INSTR_RETIRED
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Instructions retired (executed).
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.It Li DC_FULL_CYCLE
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L1 data cache buffer full stall.
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Event occurs on every cycle the
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condition is present.
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.It Li DC_FULL_CONTIG
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L1 data cache buffer full stall.
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Event occurs once for each contiguous sequence of this type of stall.
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.It Li DC_ACCESS
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L1 data cache access, not including cache operations.
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.It Li DC_MISS
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L1 data cache miss, not including cache operations.
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.It Li DC_WRITEBACK
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L1 data cache write-back.
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Occurs for each cache line that's written back from the cache.
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.It Li PC_CHANGE
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Software changed the program counter.
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.It Li BRANCH_RETIRED_ALL
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Branch instruction retired (executed).
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This event counts all branch instructions, indirect or direct.
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.It Li INSTR_CYCLE
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Count the number of microarchitecture cycles each instruction requires
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to issue.
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.It Li CP_STALL
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Coprocessor stalled the instruction pipeline.
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.It Li PC_CHANGE_ALL
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Software changed the program counter (includes exceptions).
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.It Li PIPELINE_FLUSH
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Pipeline flushes due to mispredictions or exceptions.
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.It Li BACKEND_STALL
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Backend stalled the instruction pipeline.
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.It Li MULTIPLIER_USE
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Multiplier used.
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.It Li MULTIPLIER_STALLED
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Multiplier stalled the instruction pipeline.
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.It Li DATA_CACHE_STALLED
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Data cache stalled the instruction pipeline.
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.It Li L2_CACHE_REQ
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L2 cache request, not including cache operations.
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.It Li L2_CACHE_MISS
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L2 cache miss, not including cache operations.
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.It Li ADDRESS_BUS_TRANS
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Address bus transaction.
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.It Li SELF_ADDRESS_BUS_TRANS
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Self initiated address bus transaction.
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.It Li DATA_BUS_TRANS
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Data bus transaction.
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.El
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.Ss Event Name Aliases
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The following table shows the mapping between the PMC-independent
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aliases supported by
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.Lb libpmc
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and the underlying hardware events used.
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.Bl -column "branch-mispredicts" "BRANCH_MISPRED"
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.It Em Alias Ta Em Event Ta
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.It Li branches Ta Li BRANCH_RETIRED Ta
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.It Li branch-mispredicts Ta Li BRANCH_MISPRED Ta
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.It Li dc-misses Ta Li DC_MISS Ta
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.It Li ic-misses Ta Li IC_MISS Ta
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.It Li instructions Ta Li INSTR_RETIRED Ta
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.El
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.Sh SEE ALSO
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.Xr pmc 3 ,
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.Xr pmc_cpuinfo 3 ,
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.Xr pmclog 3 ,
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.Xr hwpmc 4
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.Sh HISTORY
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The
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.Nm pmc
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library first appeared in
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.Fx 6.0 .
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Intel XScale support first appeared in
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.Fx 9.0 .
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.Sh AUTHORS
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The
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.Lb libpmc
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library was written by
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.An "Joseph Koshy"
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.Aq jkoshy@FreeBSD.org .
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.Pp
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Intel XScale support was added by
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.An "Rui Paulo"
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.Aq rpaulo@FreeBSD.org .
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.Sh CAVEATS
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The Intel XScale code does not yet support sampling.
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