dc4ee6ca91
make use of it where possible. This primarily brings in support for newer hardware, and FreeBSD is not yet able to support the abundance of IRQs on new hardware and many features in the Ethernet driver. Because of the changes to IRQs in the Simple Executive, we have to maintain our own list of Octeon IRQs now, which probably can be pared-down and be specific to the CIU interrupt unit soon, and when other interrupt mechanisms are added they can maintain their own definitions. Remove unmasking of interrupts from within the UART device now that the function used is no longer present in the Simple Executive. The unmasking seems to have been gratuitous as this is more properly handled by the buses above the UART device, and seems to work on that basis.
320 lines
8.1 KiB
C
320 lines
8.1 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Inc. nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* @file
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*
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* Module to support operations on bitmap of cores. Coremask can be used to
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* select a specific core, a group of cores, or all available cores, for
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* initialization and differentiation of roles within a single shared binary
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* executable image.
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*
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* <hr>$Revision: 70030 $<hr>
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*
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*/
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#ifndef __CVMX_COREMASK_H__
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#define __CVMX_COREMASK_H__
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#include "cvmx-asm.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef uint64_t cvmx_coremask_holder_t; /* basic type to hold the
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coremask bits */
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#define CVMX_COREMASK_HLDRSZ ((int)(sizeof(cvmx_coremask_holder_t) * 8))
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/* bits per holder */
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#define CVMX_COREMASK_BMPSZ ((int)(CVMX_MAX_CORES / CVMX_COREMASK_HLDRSZ + 1))
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/* bit map size */
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/*
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* The macro pair implement a way to iterate active cores in the mask.
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* @param fec_pcm points to the coremask.
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* @param fec_ppid is the active core's id.
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*/
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#define CVMX_COREMASK_FOR_EACH_CORE_BEGIN(fec_pcm, fec_ppid) \
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do { \
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int fec_i, fec_j; \
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\
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for (fec_i = 0; fec_i < CVMX_COREMASK_BMPSZ; fec_i++) \
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{ \
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for (fec_j = 0; fec_j < CVMX_COREMASK_HLDRSZ; fec_j++) \
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{ \
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if (((cvmx_coremask_holder_t)1 << fec_j) & \
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(fec_pcm)->coremask_bitmap[fec_i]) \
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{ \
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fec_ppid = fec_i * CVMX_COREMASK_HLDRSZ + fec_j;
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#define CVMX_COREMASK_FOR_EACH_CORE_END \
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} \
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} \
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} \
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} while (0)
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struct cvmx_coremask {
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/*
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* Big-endian. Array elems of larger indices represent cores of
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* bigger ids. So do MSBs within a cvmx_coremask_holder_t. Ditto
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* MSbs within a byte.
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*/
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cvmx_coremask_holder_t coremask_bitmap[CVMX_COREMASK_BMPSZ];
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};
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/*
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* Is ``core'' set in the coremask?
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*
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* @param pcm is the pointer to the coremask.
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* @param core
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* @return 1 if core is set and 0 if not.
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*/
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static inline int cvmx_coremask_is_set_core(struct cvmx_coremask *pcm,
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int core)
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{
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int n, i;
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n = core % CVMX_COREMASK_HLDRSZ;
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i = core / CVMX_COREMASK_HLDRSZ;
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return (int)((pcm->coremask_bitmap[i] & (1ull << n)) != 0);
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}
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/*
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* Set ``core'' in the coremask.
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*
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* @param pcm is the pointer to the coremask.
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* @param core
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* @return 0.
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*/
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static inline int cvmx_coremask_set_core(struct cvmx_coremask *pcm,
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int core)
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{
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int n, i;
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n = core % CVMX_COREMASK_HLDRSZ;
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i = core / CVMX_COREMASK_HLDRSZ;
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pcm->coremask_bitmap[i] |= (1ull << n);
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return 0;
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}
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/*
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* Clear ``core'' from the coremask.
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*
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* @param pcm is the pointer to the coremask.
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* @param core
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* @return 0.
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*/
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static inline int cvmx_coremask_clear_core(struct cvmx_coremask *pcm,
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int core)
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{
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int n, i;
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n = core % CVMX_COREMASK_HLDRSZ;
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i = core / CVMX_COREMASK_HLDRSZ;
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pcm->coremask_bitmap[i] &= ~(1ull << n);
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return 0;
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}
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/*
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* Clear the coremask.
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*
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* @param pcm is the pointer to the coremask.
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* @return 0.
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*/
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static inline int cvmx_coremask_clear_all(struct cvmx_coremask *pcm)
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{
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int i;
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for (i = 0; i < CVMX_COREMASK_BMPSZ; i++)
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pcm->coremask_bitmap[i] = 0;
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return 0;
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}
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/*
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* Is the current core the first in the coremask?
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*
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* @param pcm is the pointer to the coremask.
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* @return 1 for yes and 0 for no.
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*/
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static inline int cvmx_coremask_first_core_bmp(struct cvmx_coremask *pcm)
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{
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int n, i;
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n = (int) cvmx_get_core_num();
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for (i = 0; i < CVMX_COREMASK_BMPSZ; i++)
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{
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if (pcm->coremask_bitmap[i])
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{
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if (n == 0 && pcm->coremask_bitmap[i] & 1)
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return 1;
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if (n >= CVMX_COREMASK_HLDRSZ)
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return 0;
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return ((((1ull << n) - 1) & pcm->coremask_bitmap[i]) == 0);
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}
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else
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n -= CVMX_COREMASK_HLDRSZ;
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}
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return 0;
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}
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/*
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* Is the current core a member of the coremask?
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*
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* @param pcm is the pointer to the coremask.
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* @return 1 for yes and 0 for no.
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*/
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static inline int cvmx_coremask_is_member_bmp(struct cvmx_coremask *pcm)
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{
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return cvmx_coremask_is_set_core(pcm, (int)cvmx_get_core_num());
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}
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/*
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* coremask is simply unsigned int (32 bits).
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*
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* NOTE: supports up to 32 cores maximum.
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*
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* union of coremasks is simply bitwise-or.
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* intersection of coremasks is simply bitwise-and.
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*
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*/
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#define CVMX_COREMASK_MAX 0xFFFFFFFFu /* maximum supported mask */
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/**
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* Compute coremask for a specific core.
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*
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* @param core_id The core ID
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*
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* @return coremask for a specific core
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*
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*/
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static inline unsigned int cvmx_coremask_core(unsigned int core_id)
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{
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return (1u << core_id);
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}
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/**
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* Compute coremask for num_cores cores starting with core 0.
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*
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* @param num_cores number of cores
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*
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* @return coremask for num_cores cores
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*
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*/
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static inline unsigned int cvmx_coremask_numcores(unsigned int num_cores)
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{
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return (CVMX_COREMASK_MAX >> (CVMX_MAX_CORES - num_cores));
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}
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/**
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* Compute coremask for a range of cores from core low to core high.
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*
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* @param low first core in the range
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* @param high last core in the range
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*
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* @return coremask for the range of cores
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*
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*/
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static inline unsigned int cvmx_coremask_range(unsigned int low, unsigned int high)
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{
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return ((CVMX_COREMASK_MAX >> (CVMX_MAX_CORES - 1 - high + low)) << low);
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}
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/**
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* Test to see if current core is a member of coremask.
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*
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* @param coremask the coremask to test against
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*
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* @return 1 if current core is a member of coremask, 0 otherwise
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*
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*/
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static inline int cvmx_coremask_is_member(unsigned int coremask)
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{
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return ((cvmx_coremask_core(cvmx_get_core_num()) & coremask) != 0);
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}
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/**
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* Test to see if current core is first core in coremask.
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*
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* @param coremask the coremask to test against
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*
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* @return 1 if current core is first core in the coremask, 0 otherwise
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*
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*/
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static inline int cvmx_coremask_first_core(unsigned int coremask)
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{
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return cvmx_coremask_is_member(coremask)
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&& ((cvmx_get_core_num() == 0) ||
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((cvmx_coremask_numcores(cvmx_get_core_num()) & coremask) == 0));
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}
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/**
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* Wait (stall) until all cores in the given coremask has reached this point
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* in the program execution before proceeding.
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*
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* @param coremask the group of cores performing the barrier sync
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*
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*/
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extern void cvmx_coremask_barrier_sync(unsigned int coremask);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CVMX_COREMASK_H__ */
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