a66dc0c52b
have ACLE support built in. The ACLE (ARM C Language Extensions) defines a set of standardized symbols which indicate the architecture version and features available. ACLE support is built in to modern compilers (both clang and gcc), but absent from gcc prior to 4.4. ARM (the company) provides the acle-compat.h header file to define the right symbols for older versions of gcc. Basically, acle-compat.h does for arm about the same thing cdefs.h does for freebsd: defines standardized macros that work no matter which compiler you use. If ARM hadn't provided this file we would have ended up with a big #ifdef __arm__ section in cdefs.h with our own compatibility shims. Remove #include <machine/acle-compat.h> from the zillion other places (an ever-growing list) that it appears. Since style(9) requires sys/types.h or sys/param.h early in the include list, and both of those lead to including cdefs.h, only a couple special cases still need to include acle-compat.h directly. Loves it: imp
94 lines
2.4 KiB
C
94 lines
2.4 KiB
C
/* $NetBSD: cpu.h,v 1.2 2001/02/23 21:23:52 reinoud Exp $ */
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/* $FreeBSD$ */
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#ifndef MACHINE_CPU_H
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#define MACHINE_CPU_H
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#include <machine/armreg.h>
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#include <machine/frame.h>
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void cpu_halt(void);
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void swi_vm(void *);
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#ifdef _KERNEL
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#if __ARM_ARCH >= 6
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#include <machine/cpu-v6.h>
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#else
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#include <machine/cpu-v4.h>
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#endif /* __ARM_ARCH >= 6 */
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static __inline uint64_t
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get_cyclecount(void)
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{
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#if __ARM_ARCH >= 6
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#if (__ARM_ARCH > 6) && defined(DEV_PMU)
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if (pmu_attched) {
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u_int cpu;
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uint64_t h, h2;
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uint32_t l, r;
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cpu = PCPU_GET(cpuid);
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h = (uint64_t)atomic_load_acq_32(&ccnt_hi[cpu]);
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l = cp15_pmccntr_get();
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/* In case interrupts are disabled we need to check for overflow. */
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r = cp15_pmovsr_get();
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if (r & PMU_OVSR_C) {
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atomic_add_32(&ccnt_hi[cpu], 1);
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/* Clear the event. */
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cp15_pmovsr_set(PMU_OVSR_C);
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}
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/* Make sure there was no wrap-around while we read the lo half. */
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h2 = (uint64_t)atomic_load_acq_32(&ccnt_hi[cpu]);
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if (h != h2)
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l = cp15_pmccntr_get();
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return (h2 << 32 | l);
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} else
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#endif
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return cp15_pmccntr_get();
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#else /* No performance counters, so use binuptime(9). This is slooooow */
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struct bintime bt;
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binuptime(&bt);
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return ((uint64_t)bt.sec << 56 | bt.frac >> 8);
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#endif
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}
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#endif
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#define TRAPF_USERMODE(frame) ((frame->tf_spsr & PSR_MODE) == PSR_USR32_MODE)
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#define TRAPF_PC(tfp) ((tfp)->tf_pc)
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#define cpu_getstack(td) ((td)->td_frame->tf_usr_sp)
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#define cpu_setstack(td, sp) ((td)->td_frame->tf_usr_sp = (sp))
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#define cpu_spinwait() /* nothing */
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#define ARM_NVEC 8
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#define ARM_VEC_ALL 0xffffffff
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extern vm_offset_t vector_page;
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/*
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* Params passed into initarm. If you change the size of this you will
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* need to update locore.S to allocate more memory on the stack before
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* it calls initarm.
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*/
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struct arm_boot_params {
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register_t abp_size; /* Size of this structure */
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register_t abp_r0; /* r0 from the boot loader */
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register_t abp_r1; /* r1 from the boot loader */
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register_t abp_r2; /* r2 from the boot loader */
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register_t abp_r3; /* r3 from the boot loader */
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vm_offset_t abp_physaddr; /* The kernel physical address */
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vm_offset_t abp_pagetable; /* The early page table */
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};
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void arm_vector_init(vm_offset_t, int);
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void fork_trampoline(void);
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void identify_arm_cpu(void);
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void *initarm(struct arm_boot_params *);
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extern char btext[];
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extern char etext[];
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int badaddr_read(void *, size_t, void *);
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#endif /* !MACHINE_CPU_H */
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