61a1eed0b4
# Note: Cavium provided a port that has atomics similar to these, but # that does a syncw; sync; atomic; sync; syncw where we just do the classic # mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why # the extra is needed. Since my initial target is one core, I'll defer # investigation until I bring up multiple cores. syncw is an octeon specific # instruction. |
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| .. | ||
| adm5120 | ||
| alchemy | ||
| atheros | ||
| compile | ||
| conf | ||
| idt | ||
| include | ||
| malta | ||
| mips | ||
| octeon1 | ||
| sentry5 | ||
| sibyte | ||