244af1d4db
Defining INTRNG remove some necessary registers and declarations of pic_init_secondary, pic_ipi_send, pic_ipi_read and pic_ipi_clear. Because Marvell ArmadaXP and Armada38X always use INTRNG, include all INTRNG code and remove code that does not use it. Separate pic registers declarations for Armada38X are unnecessary, it works properly with ArmadaXP config. Submitted by: Rafal Kozik <rk@semihalf.com> Reviewed by: andrew Obtained from: Semihalf Sponsored by: Stormshield Differential Revision: https://reviews.freebsd.org/D14734
114 lines
3.5 KiB
C
114 lines
3.5 KiB
C
/* $NetBSD: intr.h,v 1.7 2003/06/16 20:01:00 thorpej Exp $ */
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/*-
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* SPDX-License-Identifier: BSD-4-Clause
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*
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* Copyright (c) 1997 Mark Brinicombe.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe
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* for the NetBSD Project.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef _MACHINE_INTR_H_
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#define _MACHINE_INTR_H_
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#ifdef FDT
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#include <dev/ofw/openfirm.h>
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#endif
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#ifdef INTRNG
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#ifndef NIRQ
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#define NIRQ 1024 /* XXX - It should be an option. */
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#endif
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#include <sys/intr.h>
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#ifdef SMP
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typedef void intr_ipi_send_t(void *, cpuset_t, u_int);
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typedef void intr_ipi_handler_t(void *);
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void intr_ipi_dispatch(u_int, struct trapframe *);
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void intr_ipi_send(cpuset_t, u_int);
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void intr_ipi_setup(u_int, const char *, intr_ipi_handler_t *, void *,
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intr_ipi_send_t *, void *);
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int intr_pic_ipi_setup(u_int, const char *, intr_ipi_handler_t *, void *);
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#endif
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#else /* INTRNG */
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/* XXX move to std.* files? */
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#ifdef CPU_XSCALE_81342
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#define NIRQ 128
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#elif defined(CPU_XSCALE_PXA2X0)
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#include <arm/xscale/pxa/pxareg.h>
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#define NIRQ IRQ_GPIO_MAX
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#elif defined(SOC_MV_DISCOVERY)
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#define NIRQ 96
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#elif defined(CPU_ARM9) || defined(SOC_MV_KIRKWOOD) || \
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defined(CPU_XSCALE_IXP435)
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#define NIRQ 64
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#elif defined(CPU_CORTEXA)
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#define NIRQ 1020
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#elif defined(CPU_KRAIT)
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#define NIRQ 288
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#elif defined(CPU_ARM1176)
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#define NIRQ 128
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#else
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#define NIRQ 32
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#endif
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int arm_get_next_irq(int);
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void arm_mask_irq(uintptr_t);
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void arm_unmask_irq(uintptr_t);
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void arm_intrnames_init(void);
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void arm_setup_irqhandler(const char *, int (*)(void*), void (*)(void*),
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void *, int, int, void **);
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int arm_remove_irqhandler(int, void *);
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extern void (*arm_post_filter)(void *);
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extern int (*arm_config_irq)(int irq, enum intr_trigger trig,
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enum intr_polarity pol);
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void intr_pic_init_secondary(void);
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#ifdef FDT
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int gic_decode_fdt(phandle_t, pcell_t *, int *, int *, int *);
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int intr_fdt_map_irq(phandle_t, pcell_t *, int);
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#endif
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#endif /* INTRNG */
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void arm_irq_memory_barrier(uintptr_t);
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#endif /* _MACHINE_INTR_H */
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