caeff9a3c2
On BHND MIPS SoCs, this replaces the use of hard-coded MIPS IRQ#s in the common bhnd(4) core drivers; we now register an INTRNG child PIC that handles routing of backplane interrupt vectors via the MIPS core. On BHND PCI devices, backplane interrupt vectors are now routed to the PCI/PCIe host bridge core when bus_setup_intr() is called, where they are dispatched by the PCI core via a host interrupt (e.g. INTx/MSI). The bhndb(4) bridge driver tracks registered interrupt handlers for the bridged bhnd(4) devices and manages backplane interrupt routing, while delegating actual bus interrupt setup/teardown to the parent bus on behalf of the bridged cores. Approved by: adrian (mentor, implicit) Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D12518
33 lines
1.1 KiB
Plaintext
33 lines
1.1 KiB
Plaintext
# $FreeBSD$
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# TODO: Add attachment elsewhere in the tree
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# for USB 1.1 OHCI, Ethernet and IPSEC cores
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# which are believed to be devices we have drivers for
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# which just need to be tweaked for attachment to an BHND system bus.
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mips/broadcom/bcm_machdep.c standard
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mips/broadcom/bcm_bmips.c optional siba_nexus siba
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mips/broadcom/bcm_mips74k.c optional bcma_nexus bcma
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mips/broadcom/bcm_mips.c optional siba_nexus siba | \
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bcma_nexus bcma
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mips/broadcom/bcm_nvram_cfe.c optional bhnd siba_nexus cfe | \
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bhnd bcma_nexus cfe
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mips/broadcom/bcm_pmu.c standard
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mips/broadcom/bhnd_nexus.c optional bhnd siba_nexus | \
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bhnd bcma_nexus
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mips/broadcom/bcma_nexus.c optional bcma_nexus bcma bhnd
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mips/broadcom/siba_nexus.c optional siba_nexus siba bhnd
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mips/mips/tick.c standard
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mips/broadcom/uart_cpu_chipc.c optional uart
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mips/broadcom/uart_bus_chipc.c optional uart
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# TODO: Replace with BCM47xx/57xx/etc-aware geom_map
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geom/geom_flashmap.c standard
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# USB bits
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dev/bhnd/cores/usb/bhnd_usb.c optional usb
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dev/bhnd/cores/usb/bhnd_ehci.c optional ehci
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dev/bhnd/cores/usb/bhnd_ohci.c optional ohci
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