9fc0d68aeb
Switch the cache line size during invalidations/flushes to be read from CP15 cache type register. Submitted by: Wojciech Macek <wma@semihalf.com> Reviewed by: ian, imp Obtained from: Semihalf
446 lines
18 KiB
C
446 lines
18 KiB
C
/* $NetBSD: armreg.h,v 1.37 2007/01/06 00:50:54 christos Exp $ */
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/*-
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* Copyright (c) 1998, 2001 Ben Harris
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* Copyright (c) 1994-1996 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef MACHINE_ARMREG_H
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#define MACHINE_ARMREG_H
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#include <machine/acle-compat.h>
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#define INSN_SIZE 4
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#define INSN_COND_MASK 0xf0000000 /* Condition mask */
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#define PSR_MODE 0x0000001f /* mode mask */
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#define PSR_USR32_MODE 0x00000010
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#define PSR_FIQ32_MODE 0x00000011
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#define PSR_IRQ32_MODE 0x00000012
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#define PSR_SVC32_MODE 0x00000013
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#define PSR_MON32_MODE 0x00000016
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#define PSR_ABT32_MODE 0x00000017
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#define PSR_HYP32_MODE 0x0000001a
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#define PSR_UND32_MODE 0x0000001b
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#define PSR_SYS32_MODE 0x0000001f
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#define PSR_32_MODE 0x00000010
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#define PSR_T 0x00000020 /* Instruction set bit */
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#define PSR_F 0x00000040 /* FIQ disable bit */
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#define PSR_I 0x00000080 /* IRQ disable bit */
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#define PSR_A 0x00000100 /* Imprecise abort bit */
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#define PSR_E 0x00000200 /* Data endianess bit */
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#define PSR_GE 0x000f0000 /* Greater than or equal to bits */
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#define PSR_J 0x01000000 /* Java bit */
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#define PSR_Q 0x08000000 /* Sticky overflow bit */
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#define PSR_V 0x10000000 /* Overflow bit */
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#define PSR_C 0x20000000 /* Carry bit */
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#define PSR_Z 0x40000000 /* Zero bit */
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#define PSR_N 0x80000000 /* Negative bit */
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#define PSR_FLAGS 0xf0000000 /* Flags mask. */
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/* The high-order byte is always the implementor */
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#define CPU_ID_IMPLEMENTOR_MASK 0xff000000
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#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */
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#define CPU_ID_DEC 0x44000000 /* 'D' */
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#define CPU_ID_INTEL 0x69000000 /* 'i' */
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#define CPU_ID_TI 0x54000000 /* 'T' */
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#define CPU_ID_FARADAY 0x66000000 /* 'f' */
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/* How to decide what format the CPUID is in. */
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#define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000)
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#define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000)
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#define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x))
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/* On recent ARMs this byte holds the architecture and variant (sub-model) */
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#define CPU_ID_ARCH_MASK 0x000f0000
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#define CPU_ID_ARCH_V3 0x00000000
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#define CPU_ID_ARCH_V4 0x00010000
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#define CPU_ID_ARCH_V4T 0x00020000
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#define CPU_ID_ARCH_V5 0x00030000
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#define CPU_ID_ARCH_V5T 0x00040000
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#define CPU_ID_ARCH_V5TE 0x00050000
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#define CPU_ID_ARCH_V5TEJ 0x00060000
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#define CPU_ID_ARCH_V6 0x00070000
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#define CPU_ID_CPUID_SCHEME 0x000f0000
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#define CPU_ID_VARIANT_MASK 0x00f00000
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/* Next three nybbles are part number */
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#define CPU_ID_PARTNO_MASK 0x0000fff0
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/* Intel XScale has sub fields in part number */
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#define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */
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#define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */
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#define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */
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/* And finally, the revision number. */
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#define CPU_ID_REVISION_MASK 0x0000000f
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/* Individual CPUs are probably best IDed by everything but the revision. */
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#define CPU_ID_CPU_MASK 0xfffffff0
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/* ARM9 and later CPUs */
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#define CPU_ID_ARM920T 0x41129200
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#define CPU_ID_ARM920T_ALT 0x41009200
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#define CPU_ID_ARM922T 0x41029220
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#define CPU_ID_ARM926EJS 0x41069260
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#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */
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#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */
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#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */
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#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */
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#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */
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#define CPU_ID_ARM1022ES 0x4105a220
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#define CPU_ID_ARM1026EJS 0x4106a260
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#define CPU_ID_ARM1136JS 0x4107b360
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#define CPU_ID_ARM1136JSR1 0x4117b360
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#define CPU_ID_ARM1176JZS 0x410fb760
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#define CPU_ID_CORTEXA5 0x410fc050
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#define CPU_ID_CORTEXA7 0x410fc070
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#define CPU_ID_CORTEXA8R1 0x411fc080
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#define CPU_ID_CORTEXA8R2 0x412fc080
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#define CPU_ID_CORTEXA8R3 0x413fc080
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#define CPU_ID_CORTEXA9R1 0x411fc090
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#define CPU_ID_CORTEXA9R2 0x412fc090
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#define CPU_ID_CORTEXA9R3 0x413fc090
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#define CPU_ID_CORTEXA12R0 0x410fc0d0
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#define CPU_ID_CORTEXA15R0 0x410fc0f0
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#define CPU_ID_CORTEXA15R1 0x411fc0f0
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#define CPU_ID_CORTEXA15R2 0x412fc0f0
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#define CPU_ID_CORTEXA15R3 0x413fc0f0
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#define CPU_ID_KRAIT 0x510f06f0 /* Snapdragon S4 Pro/APQ8064 */
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#define CPU_ID_TI925T 0x54029250
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#define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */
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#define CPU_ID_MV88FR331 0x56153310 /* Marvell Feroceon 88FR331 Core */
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#define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */
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/*
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* LokiPlus core has also ID set to 0x41159260 and this define cause execution of unsupported
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* L2-cache instructions so need to disable it. 0x41159260 is a generic ARM926E-S ID.
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*/
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#ifdef SOC_MV_LOKIPLUS
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#define CPU_ID_MV88FR571_41 0x00000000
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#else
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#define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */
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#endif
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#define CPU_ID_MV88SV581X_V7 0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */
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#define CPU_ID_MV88SV584X_V7 0x562F5840 /* Marvell Sheeva 88SV584x v7 Core */
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/* Marvell's CPUIDs with ARM ID in implementor field */
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#define CPU_ID_ARM_88SV581X_V7 0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */
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#define CPU_ID_FA526 0x66015260
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#define CPU_ID_FA626TE 0x66056260
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#define CPU_ID_80200 0x69052000
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#define CPU_ID_PXA250 0x69052100 /* sans core revision */
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#define CPU_ID_PXA210 0x69052120
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#define CPU_ID_PXA250A 0x69052100 /* 1st version Core */
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#define CPU_ID_PXA210A 0x69052120 /* 1st version Core */
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#define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */
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#define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */
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#define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */
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#define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */
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#define CPU_ID_PXA27X 0x69054110
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#define CPU_ID_80321_400 0x69052420
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#define CPU_ID_80321_600 0x69052430
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#define CPU_ID_80321_400_B0 0x69052c20
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#define CPU_ID_80321_600_B0 0x69052c30
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#define CPU_ID_80219_400 0x69052e20 /* A0 stepping/revision. */
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#define CPU_ID_80219_600 0x69052e30 /* A0 stepping/revision. */
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#define CPU_ID_81342 0x69056810
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#define CPU_ID_IXP425 0x690541c0
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#define CPU_ID_IXP425_533 0x690541c0
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#define CPU_ID_IXP425_400 0x690541d0
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#define CPU_ID_IXP425_266 0x690541f0
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#define CPU_ID_IXP435 0x69054040
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#define CPU_ID_IXP465 0x69054200
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/* CPUID registers */
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#define ARM_PFR0_ARM_ISA_MASK 0x0000000f
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#define ARM_PFR0_THUMB_MASK 0x000000f0
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#define ARM_PFR0_THUMB 0x10
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#define ARM_PFR0_THUMB2 0x30
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#define ARM_PFR0_JAZELLE_MASK 0x00000f00
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#define ARM_PFR0_THUMBEE_MASK 0x0000f000
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#define ARM_PFR1_ARMV4_MASK 0x0000000f
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#define ARM_PFR1_SEC_EXT_MASK 0x000000f0
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#define ARM_PFR1_MICROCTRL_MASK 0x00000f00
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/*
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* Post-ARM3 CP15 registers:
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*
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* 1 Control register
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*
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* 2 Translation Table Base
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*
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* 3 Domain Access Control
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*
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* 4 Reserved
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*
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* 5 Fault Status
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*
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* 6 Fault Address
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*
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* 7 Cache/write-buffer Control
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*
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* 8 TLB Control
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*
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* 9 Cache Lockdown
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*
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* 10 TLB Lockdown
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*
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* 11 Reserved
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*
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* 12 Reserved
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*
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* 13 Process ID (for FCSE)
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*
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* 14 Reserved
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*
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* 15 Implementation Dependent
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*/
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/* Some of the definitions below need cleaning up for V3/V4 architectures */
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/* CPU control register (CP15 register 1) */
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#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */
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#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */
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#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */
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#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */
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#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
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#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
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#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */
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#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
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#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */
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#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */
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#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */
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#define CPU_CONTROL_SW_ENABLE 0x00000400 /* SW: SWP instruction enable */
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#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */
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#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */
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#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */
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#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */
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#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */
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#define CPU_CONTROL_HAF_ENABLE 0x00020000 /* HA: Hardware Access Flag Enable */
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#define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */
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#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */
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#define CPU_CONTROL_V6_EXTPAGE 0x00800000 /* XP: ARMv6 extended page tables */
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#define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */
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#define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */
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#define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */
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#define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */
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#define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: TEX Remap*/
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#define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access Flag enable */
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#define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */
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#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
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/* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */
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#define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */
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#define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */
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#define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */
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#define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */
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#define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */
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#define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */
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#define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */
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#define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */
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/* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */
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#define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */
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/* This is an undocumented flag
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* used to work around a cache bug
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* in r0 steppings. See errata
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* 364296.
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*/
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/* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */
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#define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */
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#define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */
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#define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */
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#define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */
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/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */
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#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */
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#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */
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/* Note: XSCale core 3 uses those for LLR DCcahce attributes */
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#define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */
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#define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */
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#define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */
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#define XSCALE_AUXCTL_MD_MASK 0x00000030
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/* Xscale Core 3 only */
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#define XSCALE_AUXCTL_LLR 0x00000400 /* Enable L2 for LLR Cache */
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/* Marvell Extra Features Register (CP15 register 1, opcode2 0) */
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#define MV_DC_REPLACE_LOCK 0x80000000 /* Replace DCache Lock */
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#define MV_DC_STREAM_ENABLE 0x20000000 /* DCache Streaming Switch */
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#define MV_WA_ENABLE 0x10000000 /* Enable Write Allocate */
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#define MV_L2_PREFETCH_DISABLE 0x01000000 /* L2 Cache Prefetch Disable */
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#define MV_L2_INV_EVICT_ERR 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */
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#define MV_L2_ENABLE 0x00400000 /* L2 Cache enable */
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#define MV_IC_REPLACE_LOCK 0x00080000 /* Replace ICache Lock */
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#define MV_BGH_ENABLE 0x00040000 /* Branch Global History Register Enable */
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#define MV_BTB_DISABLE 0x00020000 /* Branch Target Buffer Disable */
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#define MV_L1_PARERR_ENABLE 0x00010000 /* L1 Parity Error Enable */
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/* Cache type register definitions */
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#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */
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#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */
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#define CPU_CT_S (1U << 24) /* split cache */
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#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */
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#define CPU_CT_FORMAT(x) ((x) >> 29)
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/* Cache type register definitions for ARM v7 */
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#define CPU_CT_IMINLINE(x) ((x) & 0xf) /* I$ min line size */
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#define CPU_CT_DMINLINE(x) (((x) >> 16) & 0xf) /* D$ min line size */
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#define CPU_CT_CTYPE_WT 0 /* write-through */
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#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */
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#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */
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#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */
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#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */
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#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */
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#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */
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#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */
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#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */
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#define CPU_CT_ARMV7 0x4
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/* ARM v7 Cache type definitions */
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#define CPUV7_CT_CTYPE_WT (1U << 31)
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#define CPUV7_CT_CTYPE_WB (1 << 30)
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#define CPUV7_CT_CTYPE_RA (1 << 29)
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#define CPUV7_CT_CTYPE_WA (1 << 28)
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#define CPUV7_CT_xSIZE_LEN(x) ((x) & 0x7) /* line size */
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#define CPUV7_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x3ff) /* associativity */
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#define CPUV7_CT_xSIZE_SET(x) (((x) >> 13) & 0x7fff) /* num sets */
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#define CPU_CLIDR_CTYPE(reg,x) (((reg) >> ((x) * 3)) & 0x7)
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#define CPU_CLIDR_LOUIS(reg) (((reg) >> 21) & 0x7)
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#define CPU_CLIDR_LOC(reg) (((reg) >> 24) & 0x7)
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#define CPU_CLIDR_LOUU(reg) (((reg) >> 27) & 0x7)
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#define CACHE_ICACHE 1
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#define CACHE_DCACHE 2
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#define CACHE_SEP_CACHE 3
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#define CACHE_UNI_CACHE 4
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/* Fault status register definitions */
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#define FAULT_USER 0x10
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#if __ARM_ARCH < 6
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#define FAULT_TYPE_MASK 0x0f
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#define FAULT_WRTBUF_0 0x00 /* Vector Exception */
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#define FAULT_WRTBUF_1 0x02 /* Terminal Exception */
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#define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */
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#define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */
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#define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */
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#define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */
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#define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */
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#define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */
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#define FAULT_ALIGN_0 0x01 /* Alignment */
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#define FAULT_ALIGN_1 0x03 /* Alignment */
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#define FAULT_TRANS_S 0x05 /* Translation -- Section */
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#define FAULT_TRANS_F 0x06 /* Translation -- Flag */
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#define FAULT_TRANS_P 0x07 /* Translation -- Page */
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#define FAULT_DOMAIN_S 0x09 /* Domain -- Section */
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#define FAULT_DOMAIN_P 0x0b /* Domain -- Page */
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#define FAULT_PERM_S 0x0d /* Permission -- Section */
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#define FAULT_PERM_P 0x0f /* Permission -- Page */
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#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */
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#define FAULT_EXTERNAL 0x400 /* External abort (armv6+) */
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#define FAULT_WNR 0x800 /* Write-not-Read access (armv6+) */
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#else /* __ARM_ARCH < 6 */
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#define FAULT_ALIGN 0x001 /* Alignment Fault */
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#define FAULT_DEBUG 0x002 /* Debug Event */
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#define FAULT_ACCESS_L1 0x003 /* Access Bit (L1) */
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#define FAULT_ICACHE 0x004 /* Instruction cache maintenance */
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#define FAULT_TRAN_L1 0x005 /* Translation Fault (L1) */
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#define FAULT_ACCESS_L2 0x006 /* Access Bit (L2) */
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#define FAULT_TRAN_L2 0x007 /* Translation Fault (L2) */
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#define FAULT_EA_PREC 0x008 /* External Abort */
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#define FAULT_DOMAIN_L1 0x009 /* Domain Fault (L1) */
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#define FAULT_DOMAIN_L2 0x00B /* Domain Fault (L2) */
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#define FAULT_EA_TRAN_L1 0x00C /* External Translation Abort (L1) */
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#define FAULT_PERM_L1 0x00D /* Permission Fault (L1) */
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#define FAULT_EA_TRAN_L2 0x00E /* External Translation Abort (L2) */
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#define FAULT_PERM_L2 0x00F /* Permission Fault (L2) */
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#define FAULT_TLB_CONFLICT 0x010 /* Permission Fault (L2) */
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#define FAULT_EA_IMPREC 0x016 /* Asynchronous External Abort */
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#define FAULT_PE_IMPREC 0x018 /* Asynchronous Parity Error */
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#define FAULT_PARITY 0x019 /* Parity Error */
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#define FAULT_PE_TRAN_L1 0x01C /* Parity Error on Translation (L1) */
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#define FAULT_PE_TRAN_L2 0x01E /* Parity Error on Translation (L2) */
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#define FSR_TO_FAULT(fsr) (((fsr) & 0xF) | \
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((((fsr) & (1 << 10)) >> (10 - 4))))
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#define FSR_LPAE (1 << 9) /* LPAE indicator */
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#define FSR_WNR (1 << 11) /* Write-not-Read access */
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#define FSR_EXT (1 << 12) /* DECERR/SLVERR for external*/
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#define FSR_CM (1 << 13) /* Cache maintenance fault */
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#endif /* !__ARM_ARCH < 6 */
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/*
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* Address of the vector page, low and high versions.
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*/
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#ifndef __ASSEMBLER__
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#define ARM_VECTORS_LOW 0x00000000U
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#define ARM_VECTORS_HIGH 0xffff0000U
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#else
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#define ARM_VECTORS_LOW 0
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#define ARM_VECTORS_HIGH 0xffff0000
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#endif
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/*
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* ARM Instructions
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|
*
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* 3 3 2 2 2
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|
* 1 0 9 8 7 0
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|
* +-------+-------------------------------------------------------+
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* | cond | instruction dependant |
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* |c c c c| |
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* +-------+-------------------------------------------------------+
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*/
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#define INSN_SIZE 4 /* Always 4 bytes */
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#define INSN_COND_MASK 0xf0000000 /* Condition mask */
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|
#define INSN_COND_AL 0xe0000000 /* Always condition */
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#define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */
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#endif /* !MACHINE_ARMREG_H */
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