986 lines
25 KiB
C
986 lines
25 KiB
C
/*-
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* Copyright (c) 2011
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* Ben Gray <ben.r.gray@gmail.com>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/**
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* Very simple GPIO (general purpose IO) driver module for TI OMAP SoC's.
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*
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* Currently this driver only does the basics, get a value on a pin & set a
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* value on a pin. Hopefully over time I'll expand this to be a bit more generic
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* and support interrupts and other various bits on the SoC can do ... in the
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* meantime this is all you get.
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*
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* Beware the OMA datasheet(s) lists GPIO banks 1-6, whereas I've used 0-5 here
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* in the code.
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*
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/gpio.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <arm/ti/ti_cpuid.h>
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#include <arm/ti/ti_scm.h>
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#include <arm/ti/ti_prcm.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "gpio_if.h"
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/* Register definitions */
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#define TI_GPIO_REVISION 0x0000
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#define TI_GPIO_SYSCONFIG 0x0010
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#if defined(SOC_OMAP3)
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#define TI_GPIO_SYSSTATUS 0x0014
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#define TI_GPIO_IRQSTATUS1 0x0018
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#define TI_GPIO_IRQENABLE1 0x001C
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#define TI_GPIO_WAKEUPENABLE 0x0020
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#define TI_GPIO_IRQSTATUS2 0x0028
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#define TI_GPIO_IRQENABLE2 0x002C
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#define TI_GPIO_CTRL 0x0030
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#define TI_GPIO_OE 0x0034
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#define TI_GPIO_DATAIN 0x0038
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#define TI_GPIO_DATAOUT 0x003C
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#define TI_GPIO_LEVELDETECT0 0x0040
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#define TI_GPIO_LEVELDETECT1 0x0044
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#define TI_GPIO_RISINGDETECT 0x0048
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#define TI_GPIO_FALLINGDETECT 0x004C
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#define TI_GPIO_DEBOUNCENABLE 0x0050
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#define TI_GPIO_DEBOUNCINGTIME 0x0054
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#define TI_GPIO_CLEARIRQENABLE1 0x0060
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#define TI_GPIO_SETIRQENABLE1 0x0064
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#define TI_GPIO_CLEARIRQENABLE2 0x0070
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#define TI_GPIO_SETIRQENABLE2 0x0074
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#define TI_GPIO_CLEARWKUENA 0x0080
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#define TI_GPIO_SETWKUENA 0x0084
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#define TI_GPIO_CLEARDATAOUT 0x0090
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#define TI_GPIO_SETDATAOUT 0x0094
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#elif defined(SOC_OMAP4) || defined(SOC_TI_AM335X)
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#define TI_GPIO_IRQSTATUS_RAW_0 0x0024
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#define TI_GPIO_IRQSTATUS_RAW_1 0x0028
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#define TI_GPIO_IRQSTATUS_0 0x002C
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#define TI_GPIO_IRQSTATUS_1 0x0030
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#define TI_GPIO_IRQSTATUS_SET_0 0x0034
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#define TI_GPIO_IRQSTATUS_SET_1 0x0038
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#define TI_GPIO_IRQSTATUS_CLR_0 0x003C
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#define TI_GPIO_IRQSTATUS_CLR_1 0x0040
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#define TI_GPIO_IRQWAKEN_0 0x0044
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#define TI_GPIO_IRQWAKEN_1 0x0048
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#define TI_GPIO_SYSSTATUS 0x0114
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#define TI_GPIO_IRQSTATUS1 0x0118
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#define TI_GPIO_IRQENABLE1 0x011C
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#define TI_GPIO_WAKEUPENABLE 0x0120
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#define TI_GPIO_IRQSTATUS2 0x0128
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#define TI_GPIO_IRQENABLE2 0x012C
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#define TI_GPIO_CTRL 0x0130
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#define TI_GPIO_OE 0x0134
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#define TI_GPIO_DATAIN 0x0138
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#define TI_GPIO_DATAOUT 0x013C
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#define TI_GPIO_LEVELDETECT0 0x0140
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#define TI_GPIO_LEVELDETECT1 0x0144
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#define TI_GPIO_RISINGDETECT 0x0148
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#define TI_GPIO_FALLINGDETECT 0x014C
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#define TI_GPIO_DEBOUNCENABLE 0x0150
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#define TI_GPIO_DEBOUNCINGTIME 0x0154
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#define TI_GPIO_CLEARWKUPENA 0x0180
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#define TI_GPIO_SETWKUENA 0x0184
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#define TI_GPIO_CLEARDATAOUT 0x0190
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#define TI_GPIO_SETDATAOUT 0x0194
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#else
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#error "Unknown SoC"
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#endif
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/* Other SoC Specific definitions */
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#define OMAP3_MAX_GPIO_BANKS 6
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#define OMAP3_FIRST_GPIO_BANK 1
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#define OMAP3_INTR_PER_BANK 1
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#define OMAP3_GPIO_REV 0x00000025
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#define OMAP4_MAX_GPIO_BANKS 6
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#define OMAP4_FIRST_GPIO_BANK 1
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#define OMAP4_INTR_PER_BANK 1
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#define OMAP4_GPIO_REV 0x50600801
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#define AM335X_MAX_GPIO_BANKS 4
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#define AM335X_FIRST_GPIO_BANK 0
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#define AM335X_INTR_PER_BANK 2
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#define AM335X_GPIO_REV 0x50600801
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#define PINS_PER_BANK 32
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#define MAX_GPIO_BANKS 6
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/* Maximum GPIOS possible, max of *_MAX_GPIO_BANKS * *_INTR_PER_BANK */
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#define MAX_GPIO_INTRS 8
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static u_int
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ti_max_gpio_banks(void)
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{
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switch(ti_chip()) {
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#ifdef SOC_OMAP3
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case CHIP_OMAP_3:
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return (OMAP3_MAX_GPIO_BANKS);
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#endif
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#ifdef SOC_OMAP4
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case CHIP_OMAP_4:
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return (OMAP4_MAX_GPIO_BANKS);
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#endif
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#ifdef SOC_TI_AM335X
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case CHIP_AM335X:
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return (AM335X_MAX_GPIO_BANKS);
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#endif
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}
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return (0);
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}
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static u_int
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ti_max_gpio_intrs(void)
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{
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switch(ti_chip()) {
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#ifdef SOC_OMAP3
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case CHIP_OMAP_3:
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return (OMAP3_MAX_GPIO_BANKS * OMAP3_INTR_PER_BANK);
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#endif
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#ifdef SOC_OMAP4
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case CHIP_OMAP_4:
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return (OMAP4_MAX_GPIO_BANKS * OMAP4_INTR_PER_BANK);
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#endif
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#ifdef SOC_TI_AM335X
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case CHIP_AM335X:
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return (AM335X_MAX_GPIO_BANKS * AM335X_INTR_PER_BANK);
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#endif
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}
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return (0);
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}
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static u_int
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ti_first_gpio_bank(void)
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{
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switch(ti_chip()) {
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#ifdef SOC_OMAP3
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case CHIP_OMAP_3:
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return (OMAP3_FIRST_GPIO_BANK);
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#endif
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#ifdef SOC_OMAP4
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case CHIP_OMAP_4:
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return (OMAP4_FIRST_GPIO_BANK);
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#endif
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#ifdef SOC_TI_AM335X
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case CHIP_AM335X:
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return (AM335X_FIRST_GPIO_BANK);
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#endif
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}
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return (0);
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}
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static uint32_t
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ti_gpio_rev(void)
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{
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switch(ti_chip()) {
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#ifdef SOC_OMAP3
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case CHIP_OMAP_3:
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return (OMAP3_GPIO_REV);
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#endif
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#ifdef SOC_OMAP4
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case CHIP_OMAP_4:
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return (OMAP4_GPIO_REV);
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#endif
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#ifdef SOC_TI_AM335X
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case CHIP_AM335X:
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return (AM335X_GPIO_REV);
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#endif
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}
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return (0);
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}
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/**
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* ti_gpio_mem_spec - Resource specification used when allocating resources
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* ti_gpio_irq_spec - Resource specification used when allocating resources
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*
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* This driver module can have up to six independent memory regions, each
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* region typically controls 32 GPIO pins.
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*
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* On OMAP3 and OMAP4 there is only one physical interrupt line per bank,
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* but there are two set of registers which control the interrupt delivery
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* to internal subsystems. The first set of registers control the
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* interrupts delivery to the MPU and the second set control the
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* interrupts delivery to the DSP.
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*
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* On AM335x there are two physical interrupt lines for each GPIO module.
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* Each interrupt line is controlled by a set of registers.
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*/
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static struct resource_spec ti_gpio_mem_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL },
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{ SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL },
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{ SYS_RES_MEMORY, 3, RF_ACTIVE | RF_OPTIONAL },
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#if !defined(SOC_TI_AM335X)
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{ SYS_RES_MEMORY, 4, RF_ACTIVE | RF_OPTIONAL },
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{ SYS_RES_MEMORY, 5, RF_ACTIVE | RF_OPTIONAL },
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#endif
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{ -1, 0, 0 }
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};
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static struct resource_spec ti_gpio_irq_spec[] = {
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL },
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{ SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL },
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{ SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL },
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{ SYS_RES_IRQ, 4, RF_ACTIVE | RF_OPTIONAL },
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{ SYS_RES_IRQ, 5, RF_ACTIVE | RF_OPTIONAL },
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#if defined(SOC_TI_AM335X)
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{ SYS_RES_IRQ, 6, RF_ACTIVE | RF_OPTIONAL },
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{ SYS_RES_IRQ, 7, RF_ACTIVE | RF_OPTIONAL },
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#endif
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{ -1, 0, 0 }
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};
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/**
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* Structure that stores the driver context.
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*
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* This structure is allocated during driver attach.
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*/
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struct ti_gpio_softc {
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device_t sc_dev;
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/*
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* The memory resource(s) for the PRCM register set, when the device is
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* created the caller can assign up to 6 memory regions depending on
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* the SoC type.
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*/
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struct resource *sc_mem_res[MAX_GPIO_BANKS];
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struct resource *sc_irq_res[MAX_GPIO_INTRS];
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/* The handle for the register IRQ handlers. */
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void *sc_irq_hdl[MAX_GPIO_INTRS];
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/*
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* The following describes the H/W revision of each of the GPIO banks.
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*/
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uint32_t sc_revision[MAX_GPIO_BANKS];
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struct mtx sc_mtx;
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};
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/**
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* Macros for driver mutex locking
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*/
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#define TI_GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define TI_GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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#define TI_GPIO_LOCK_INIT(_sc) \
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mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
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"ti_gpio", MTX_DEF)
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#define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx)
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#define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED)
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#define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED)
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/**
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* ti_gpio_read_4 - reads a 16-bit value from one of the PADCONFS registers
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* @sc: GPIO device context
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* @bank: The bank to read from
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* @off: The offset of a register from the GPIO register address range
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*
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*
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* RETURNS:
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* 32-bit value read from the register.
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*/
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static inline uint32_t
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ti_gpio_read_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off)
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{
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return (bus_read_4(sc->sc_mem_res[bank], off));
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}
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/**
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* ti_gpio_write_4 - writes a 32-bit value to one of the PADCONFS registers
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* @sc: GPIO device context
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* @bank: The bank to write to
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* @off: The offset of a register from the GPIO register address range
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* @val: The value to write into the register
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*
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* RETURNS:
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* nothing
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*/
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static inline void
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ti_gpio_write_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off,
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uint32_t val)
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{
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bus_write_4(sc->sc_mem_res[bank], off, val);
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}
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static inline void
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ti_gpio_intr_clr(struct ti_gpio_softc *sc, unsigned int bank, uint32_t mask)
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{
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/* We clear both set of registers. */
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#if defined(SOC_OMAP4) || defined(SOC_TI_AM335X)
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ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_0, mask);
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ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_1, mask);
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#else
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ti_gpio_write_4(sc, bank, TI_GPIO_CLEARIRQENABLE1, mask);
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ti_gpio_write_4(sc, bank, TI_GPIO_CLEARIRQENABLE2, mask);
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#endif
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}
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/**
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* ti_gpio_pin_max - Returns the maximum number of GPIO pins
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* @dev: gpio device handle
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* @maxpin: pointer to a value that upon return will contain the maximum number
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* of pins in the device.
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*
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*
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* LOCKING:
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* Internally locks the context
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*
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* RETURNS:
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* Returns 0 on success otherwise an error code
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*/
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static int
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ti_gpio_pin_max(device_t dev, int *maxpin)
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{
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struct ti_gpio_softc *sc = device_get_softc(dev);
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unsigned int i;
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unsigned int banks = 0;
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TI_GPIO_LOCK(sc);
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/* Calculate how many valid banks we have and then multiply that by 32 to
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* give use the total number of pins.
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*/
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for (i = 0; i < ti_max_gpio_banks(); i++) {
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if (sc->sc_mem_res[i] != NULL)
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banks++;
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}
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*maxpin = (banks * PINS_PER_BANK) - 1;
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TI_GPIO_UNLOCK(sc);
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return (0);
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}
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/**
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* ti_gpio_pin_getcaps - Gets the capabilties of a given pin
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* @dev: gpio device handle
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* @pin: the number of the pin
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* @caps: pointer to a value that upon return will contain the capabilities
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*
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* Currently all pins have the same capability, notably:
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* - GPIO_PIN_INPUT
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* - GPIO_PIN_OUTPUT
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* - GPIO_PIN_PULLUP
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* - GPIO_PIN_PULLDOWN
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*
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* LOCKING:
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* Internally locks the context
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*
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* RETURNS:
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* Returns 0 on success otherwise an error code
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*/
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static int
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ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
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{
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struct ti_gpio_softc *sc = device_get_softc(dev);
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uint32_t bank = (pin / PINS_PER_BANK);
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TI_GPIO_LOCK(sc);
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/* Sanity check the pin number is valid */
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if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) {
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TI_GPIO_UNLOCK(sc);
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return (EINVAL);
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}
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*caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |GPIO_PIN_PULLUP |
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GPIO_PIN_PULLDOWN);
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TI_GPIO_UNLOCK(sc);
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return (0);
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}
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/**
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* ti_gpio_pin_getflags - Gets the current flags of a given pin
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* @dev: gpio device handle
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* @pin: the number of the pin
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* @flags: upon return will contain the current flags of the pin
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*
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* Reads the current flags of a given pin, here we actually read the H/W
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* registers to determine the flags, rather than storing the value in the
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* setflags call.
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*
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* LOCKING:
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* Internally locks the context
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*
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* RETURNS:
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* Returns 0 on success otherwise an error code
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*/
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static int
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ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
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{
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struct ti_gpio_softc *sc = device_get_softc(dev);
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uint32_t bank = (pin / PINS_PER_BANK);
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TI_GPIO_LOCK(sc);
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/* Sanity check the pin number is valid */
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if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) {
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TI_GPIO_UNLOCK(sc);
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return (EINVAL);
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}
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/* Get the current pin state */
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ti_scm_padconf_get_gpioflags(pin, flags);
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TI_GPIO_UNLOCK(sc);
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return (0);
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}
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/**
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* ti_gpio_pin_getname - Gets the name of a given pin
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* @dev: gpio device handle
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* @pin: the number of the pin
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* @name: buffer to put the name in
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*
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* The driver simply calls the pins gpio_n, where 'n' is obviously the number
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* of the pin.
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*
|
|
* LOCKING:
|
|
* Internally locks the context
|
|
*
|
|
* RETURNS:
|
|
* Returns 0 on success otherwise an error code
|
|
*/
|
|
static int
|
|
ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
|
|
{
|
|
struct ti_gpio_softc *sc = device_get_softc(dev);
|
|
uint32_t bank = (pin / PINS_PER_BANK);
|
|
|
|
TI_GPIO_LOCK(sc);
|
|
|
|
/* Sanity check the pin number is valid */
|
|
if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) {
|
|
TI_GPIO_UNLOCK(sc);
|
|
return (EINVAL);
|
|
}
|
|
|
|
/* Set a very simple name */
|
|
snprintf(name, GPIOMAXNAME, "gpio_%u", pin);
|
|
name[GPIOMAXNAME - 1] = '\0';
|
|
|
|
TI_GPIO_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
/**
|
|
* ti_gpio_pin_setflags - Sets the flags for a given pin
|
|
* @dev: gpio device handle
|
|
* @pin: the number of the pin
|
|
* @flags: the flags to set
|
|
*
|
|
* The flags of the pin correspond to things like input/output mode, pull-ups,
|
|
* pull-downs, etc. This driver doesn't support all flags, only the following:
|
|
* - GPIO_PIN_INPUT
|
|
* - GPIO_PIN_OUTPUT
|
|
* - GPIO_PIN_PULLUP
|
|
* - GPIO_PIN_PULLDOWN
|
|
*
|
|
* LOCKING:
|
|
* Internally locks the context
|
|
*
|
|
* RETURNS:
|
|
* Returns 0 on success otherwise an error code
|
|
*/
|
|
static int
|
|
ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
|
|
{
|
|
struct ti_gpio_softc *sc = device_get_softc(dev);
|
|
uint32_t bank = (pin / PINS_PER_BANK);
|
|
uint32_t mask = (1UL << (pin % PINS_PER_BANK));
|
|
uint32_t reg_val;
|
|
|
|
/* Sanity check the flags supplied are valid, i.e. not input and output */
|
|
if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) == 0x0000)
|
|
return (EINVAL);
|
|
if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) ==
|
|
(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT))
|
|
return (EINVAL);
|
|
if ((flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) ==
|
|
(GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN))
|
|
return (EINVAL);
|
|
|
|
TI_GPIO_LOCK(sc);
|
|
|
|
/* Sanity check the pin number is valid */
|
|
if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) {
|
|
TI_GPIO_UNLOCK(sc);
|
|
return (EINVAL);
|
|
}
|
|
|
|
/* Set the GPIO mode and state */
|
|
if (ti_scm_padconf_set_gpioflags(pin, flags) != 0) {
|
|
TI_GPIO_UNLOCK(sc);
|
|
return (EINVAL);
|
|
}
|
|
|
|
/* If configuring as an output set the "output enable" bit */
|
|
reg_val = ti_gpio_read_4(sc, bank, TI_GPIO_OE);
|
|
if (flags & GPIO_PIN_INPUT)
|
|
reg_val |= mask;
|
|
else
|
|
reg_val &= ~mask;
|
|
ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_val);
|
|
|
|
TI_GPIO_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
/**
|
|
* ti_gpio_pin_set - Sets the current level on a GPIO pin
|
|
* @dev: gpio device handle
|
|
* @pin: the number of the pin
|
|
* @value: non-zero value will drive the pin high, otherwise the pin is
|
|
* driven low.
|
|
*
|
|
*
|
|
* LOCKING:
|
|
* Internally locks the context
|
|
*
|
|
* RETURNS:
|
|
* Returns 0 on success otherwise a error code
|
|
*/
|
|
static int
|
|
ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
|
|
{
|
|
struct ti_gpio_softc *sc = device_get_softc(dev);
|
|
uint32_t bank = (pin / PINS_PER_BANK);
|
|
uint32_t mask = (1UL << (pin % PINS_PER_BANK));
|
|
|
|
TI_GPIO_LOCK(sc);
|
|
|
|
/* Sanity check the pin number is valid */
|
|
if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) {
|
|
TI_GPIO_UNLOCK(sc);
|
|
return (EINVAL);
|
|
}
|
|
|
|
ti_gpio_write_4(sc, bank, (value == GPIO_PIN_LOW) ? TI_GPIO_CLEARDATAOUT
|
|
: TI_GPIO_SETDATAOUT, mask);
|
|
|
|
TI_GPIO_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
/**
|
|
* ti_gpio_pin_get - Gets the current level on a GPIO pin
|
|
* @dev: gpio device handle
|
|
* @pin: the number of the pin
|
|
* @value: pointer to a value that upond return will contain the pin value
|
|
*
|
|
* The pin must be configured as an input pin beforehand, otherwise this
|
|
* function will fail.
|
|
*
|
|
* LOCKING:
|
|
* Internally locks the context
|
|
*
|
|
* RETURNS:
|
|
* Returns 0 on success otherwise a error code
|
|
*/
|
|
static int
|
|
ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
|
|
{
|
|
struct ti_gpio_softc *sc = device_get_softc(dev);
|
|
uint32_t bank = (pin / PINS_PER_BANK);
|
|
uint32_t mask = (1UL << (pin % PINS_PER_BANK));
|
|
uint32_t val = 0;
|
|
|
|
TI_GPIO_LOCK(sc);
|
|
|
|
/* Sanity check the pin number is valid */
|
|
if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) {
|
|
TI_GPIO_UNLOCK(sc);
|
|
return (EINVAL);
|
|
}
|
|
|
|
/* Sanity check the pin is not configured as an output */
|
|
val = ti_gpio_read_4(sc, bank, TI_GPIO_OE);
|
|
|
|
/* Read the value on the pin */
|
|
if (val & mask)
|
|
*value = (ti_gpio_read_4(sc, bank, TI_GPIO_DATAIN) & mask) ? 1 : 0;
|
|
else
|
|
*value = (ti_gpio_read_4(sc, bank, TI_GPIO_DATAOUT) & mask) ? 1 : 0;
|
|
|
|
TI_GPIO_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
/**
|
|
* ti_gpio_pin_toggle - Toggles a given GPIO pin
|
|
* @dev: gpio device handle
|
|
* @pin: the number of the pin
|
|
*
|
|
*
|
|
* LOCKING:
|
|
* Internally locks the context
|
|
*
|
|
* RETURNS:
|
|
* Returns 0 on success otherwise a error code
|
|
*/
|
|
static int
|
|
ti_gpio_pin_toggle(device_t dev, uint32_t pin)
|
|
{
|
|
struct ti_gpio_softc *sc = device_get_softc(dev);
|
|
uint32_t bank = (pin / PINS_PER_BANK);
|
|
uint32_t mask = (1UL << (pin % PINS_PER_BANK));
|
|
uint32_t val;
|
|
|
|
TI_GPIO_LOCK(sc);
|
|
|
|
/* Sanity check the pin number is valid */
|
|
if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) {
|
|
TI_GPIO_UNLOCK(sc);
|
|
return (EINVAL);
|
|
}
|
|
|
|
/* Toggle the pin */
|
|
val = ti_gpio_read_4(sc, bank, TI_GPIO_DATAOUT);
|
|
if (val & mask)
|
|
ti_gpio_write_4(sc, bank, TI_GPIO_CLEARDATAOUT, mask);
|
|
else
|
|
ti_gpio_write_4(sc, bank, TI_GPIO_SETDATAOUT, mask);
|
|
|
|
TI_GPIO_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
/**
|
|
* ti_gpio_intr - ISR for all GPIO modules
|
|
* @arg: the soft context pointer
|
|
*
|
|
* Unsused
|
|
*
|
|
* LOCKING:
|
|
* Internally locks the context
|
|
*
|
|
*/
|
|
static void
|
|
ti_gpio_intr(void *arg)
|
|
{
|
|
struct ti_gpio_softc *sc = arg;
|
|
|
|
TI_GPIO_LOCK(sc);
|
|
/* TODO: something useful */
|
|
TI_GPIO_UNLOCK(sc);
|
|
}
|
|
|
|
/**
|
|
* ti_gpio_probe - probe function for the driver
|
|
* @dev: gpio device handle
|
|
*
|
|
* Simply sets the name of the driver
|
|
*
|
|
* LOCKING:
|
|
* None
|
|
*
|
|
* RETURNS:
|
|
* Always returns 0
|
|
*/
|
|
static int
|
|
ti_gpio_probe(device_t dev)
|
|
{
|
|
|
|
if (!ofw_bus_status_okay(dev))
|
|
return (ENXIO);
|
|
|
|
if (!ofw_bus_is_compatible(dev, "ti,gpio"))
|
|
return (ENXIO);
|
|
|
|
device_set_desc(dev, "TI General Purpose I/O (GPIO)");
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ti_gpio_attach_intr(device_t dev)
|
|
{
|
|
int i;
|
|
struct ti_gpio_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
for (i = 0; i < ti_max_gpio_intrs(); i++) {
|
|
if (sc->sc_irq_res[i] == NULL)
|
|
break;
|
|
|
|
/*
|
|
* Register our interrupt handler for each of the IRQ resources.
|
|
*/
|
|
if (bus_setup_intr(dev, sc->sc_irq_res[i],
|
|
INTR_TYPE_MISC | INTR_MPSAFE, NULL, ti_gpio_intr, sc,
|
|
&sc->sc_irq_hdl[i]) != 0) {
|
|
device_printf(dev,
|
|
"WARNING: unable to register interrupt handler\n");
|
|
return (-1);
|
|
}
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ti_gpio_detach_intr(device_t dev)
|
|
{
|
|
int i;
|
|
struct ti_gpio_softc *sc;
|
|
|
|
/* Teardown our interrupt handlers. */
|
|
sc = device_get_softc(dev);
|
|
for (i = 0; i < ti_max_gpio_intrs(); i++) {
|
|
if (sc->sc_irq_res[i] == NULL)
|
|
break;
|
|
|
|
if (sc->sc_irq_hdl[i]) {
|
|
bus_teardown_intr(dev, sc->sc_irq_res[i],
|
|
sc->sc_irq_hdl[i]);
|
|
}
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ti_gpio_bank_init(device_t dev, int bank)
|
|
{
|
|
int pin;
|
|
struct ti_gpio_softc *sc;
|
|
uint32_t flags, reg_oe;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
/* Enable the interface and functional clocks for the module. */
|
|
ti_prcm_clk_enable(GPIO0_CLK + ti_first_gpio_bank() + bank);
|
|
|
|
/*
|
|
* Read the revision number of the module. TI don't publish the
|
|
* actual revision numbers, so instead the values have been
|
|
* determined by experimentation.
|
|
*/
|
|
sc->sc_revision[bank] = ti_gpio_read_4(sc, bank, TI_GPIO_REVISION);
|
|
|
|
/* Check the revision. */
|
|
if (sc->sc_revision[bank] != ti_gpio_rev()) {
|
|
device_printf(dev, "Warning: could not determine the revision "
|
|
"of %u GPIO module (revision:0x%08x)\n",
|
|
bank, sc->sc_revision[bank]);
|
|
return (EINVAL);
|
|
}
|
|
|
|
/* Disable interrupts for all pins. */
|
|
ti_gpio_intr_clr(sc, bank, 0xffffffff);
|
|
|
|
/* Init OE register based on pads configuration. */
|
|
reg_oe = 0xffffffff;
|
|
for (pin = 0; pin < PINS_PER_BANK; pin++) {
|
|
ti_scm_padconf_get_gpioflags(PINS_PER_BANK * bank + pin,
|
|
&flags);
|
|
if (flags & GPIO_PIN_OUTPUT)
|
|
reg_oe &= ~(1UL << pin);
|
|
}
|
|
ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_oe);
|
|
|
|
return (0);
|
|
}
|
|
|
|
/**
|
|
* ti_gpio_attach - attach function for the driver
|
|
* @dev: gpio device handle
|
|
*
|
|
* Allocates and sets up the driver context for all GPIO banks. This function
|
|
* expects the memory ranges and IRQs to already be allocated to the driver.
|
|
*
|
|
* LOCKING:
|
|
* None
|
|
*
|
|
* RETURNS:
|
|
* Always returns 0
|
|
*/
|
|
static int
|
|
ti_gpio_attach(device_t dev)
|
|
{
|
|
struct ti_gpio_softc *sc;
|
|
unsigned int i;
|
|
int err;
|
|
|
|
sc = device_get_softc(dev);
|
|
sc->sc_dev = dev;
|
|
|
|
TI_GPIO_LOCK_INIT(sc);
|
|
|
|
/* There are up to 6 different GPIO register sets located in different
|
|
* memory areas on the chip. The memory range should have been set for
|
|
* the driver when it was added as a child.
|
|
*/
|
|
if (bus_alloc_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res) != 0) {
|
|
device_printf(dev, "Error: could not allocate mem resources\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* Request the IRQ resources */
|
|
if (bus_alloc_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res) != 0) {
|
|
bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
|
|
device_printf(dev, "Error: could not allocate irq resources\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* Setup the IRQ resources */
|
|
if (ti_gpio_attach_intr(dev) != 0) {
|
|
ti_gpio_detach_intr(dev);
|
|
bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res);
|
|
bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* We need to go through each block and ensure the clocks are running and
|
|
* the module is enabled. It might be better to do this only when the
|
|
* pins are configured which would result in less power used if the GPIO
|
|
* pins weren't used ...
|
|
*/
|
|
for (i = 0; i < ti_max_gpio_banks(); i++) {
|
|
if (sc->sc_mem_res[i] != NULL) {
|
|
/* Initialize the GPIO module. */
|
|
err = ti_gpio_bank_init(dev, i);
|
|
if (err != 0) {
|
|
ti_gpio_detach_intr(dev);
|
|
bus_release_resources(dev, ti_gpio_irq_spec,
|
|
sc->sc_irq_res);
|
|
bus_release_resources(dev, ti_gpio_mem_spec,
|
|
sc->sc_mem_res);
|
|
return (err);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Finish of the probe call */
|
|
device_add_child(dev, "gpioc", device_get_unit(dev));
|
|
device_add_child(dev, "gpiobus", device_get_unit(dev));
|
|
|
|
return (bus_generic_attach(dev));
|
|
}
|
|
|
|
/**
|
|
* ti_gpio_detach - detach function for the driver
|
|
* @dev: scm device handle
|
|
*
|
|
* Allocates and sets up the driver context, this simply entails creating a
|
|
* bus mappings for the SCM register set.
|
|
*
|
|
* LOCKING:
|
|
* None
|
|
*
|
|
* RETURNS:
|
|
* Always returns 0
|
|
*/
|
|
static int
|
|
ti_gpio_detach(device_t dev)
|
|
{
|
|
struct ti_gpio_softc *sc = device_get_softc(dev);
|
|
unsigned int i;
|
|
|
|
KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
|
|
|
|
/* Disable all interrupts */
|
|
for (i = 0; i < ti_max_gpio_banks(); i++) {
|
|
if (sc->sc_mem_res[i] != NULL)
|
|
ti_gpio_intr_clr(sc, i, 0xffffffff);
|
|
}
|
|
|
|
bus_generic_detach(dev);
|
|
|
|
/* Release the memory and IRQ resources. */
|
|
ti_gpio_detach_intr(dev);
|
|
bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res);
|
|
bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
|
|
|
|
TI_GPIO_LOCK_DESTROY(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static phandle_t
|
|
ti_gpio_get_node(device_t bus, device_t dev)
|
|
{
|
|
|
|
/* We only have one child, the GPIO bus, which needs our own node. */
|
|
return (ofw_bus_get_node(bus));
|
|
}
|
|
|
|
static device_method_t ti_gpio_methods[] = {
|
|
DEVMETHOD(device_probe, ti_gpio_probe),
|
|
DEVMETHOD(device_attach, ti_gpio_attach),
|
|
DEVMETHOD(device_detach, ti_gpio_detach),
|
|
|
|
/* GPIO protocol */
|
|
DEVMETHOD(gpio_pin_max, ti_gpio_pin_max),
|
|
DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname),
|
|
DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags),
|
|
DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps),
|
|
DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags),
|
|
DEVMETHOD(gpio_pin_get, ti_gpio_pin_get),
|
|
DEVMETHOD(gpio_pin_set, ti_gpio_pin_set),
|
|
DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle),
|
|
|
|
/* ofw_bus interface */
|
|
DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node),
|
|
|
|
{0, 0},
|
|
};
|
|
|
|
static driver_t ti_gpio_driver = {
|
|
"gpio",
|
|
ti_gpio_methods,
|
|
sizeof(struct ti_gpio_softc),
|
|
};
|
|
static devclass_t ti_gpio_devclass;
|
|
|
|
DRIVER_MODULE(ti_gpio, simplebus, ti_gpio_driver, ti_gpio_devclass, 0, 0);
|