ee270bbca3
drive strength, pull mode, mux mode, speed, etc. - Add i2c devices to the tree - Add IPG clock
502 lines
11 KiB
C
502 lines
11 KiB
C
/*-
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* Copyright (c) 2013-2014 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Vybrid Family Clock Controller Module (CCM)
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* Chapter 10, Vybrid Reference Manual, Rev. 5, 07/2013
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <sys/watchdog.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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#include <machine/fdt.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <arm/freescale/vybrid/vf_common.h>
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#define CCM_CCR 0x00 /* Control Register */
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#define CCM_CSR 0x04 /* Status Register */
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#define CCM_CCSR 0x08 /* Clock Switcher Register */
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#define CCM_CACRR 0x0C /* ARM Clock Root Register */
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#define CCM_CSCMR1 0x10 /* Serial Clock Multiplexer Register 1 */
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#define CCM_CSCDR1 0x14 /* Serial Clock Divider Register 1 */
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#define CCM_CSCDR2 0x18 /* Serial Clock Divider Register 2 */
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#define CCM_CSCDR3 0x1C /* Serial Clock Divider Register 3 */
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#define CCM_CSCMR2 0x20 /* Serial Clock Multiplexer Register 2 */
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#define CCM_CTOR 0x28 /* Testing Observability Register */
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#define CCM_CLPCR 0x2C /* Low Power Control Register */
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#define CCM_CISR 0x30 /* Interrupt Status Register */
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#define CCM_CIMR 0x34 /* Interrupt Mask Register */
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#define CCM_CCOSR 0x38 /* Clock Output Source Register */
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#define CCM_CGPR 0x3C /* General Purpose Register */
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#define CCM_CCGRN 12
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#define CCM_CCGR(n) (0x40 + (n * 0x04)) /* Clock Gating Register */
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#define CCM_CMEOR(n) (0x70 + (n * 0x70)) /* Module Enable Override */
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#define CCM_CCPGR(n) (0x90 + (n * 0x04)) /* Platform Clock Gating */
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#define CCM_CPPDSR 0x88 /* PLL PFD Disable Status Register */
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#define CCM_CCOWR 0x8C /* CORE Wakeup Register */
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#define PLL3_PFD4_EN (1U << 31)
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#define PLL3_PFD3_EN (1 << 30)
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#define PLL3_PFD2_EN (1 << 29)
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#define PLL3_PFD1_EN (1 << 28)
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#define PLL2_PFD4_EN (1 << 15)
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#define PLL2_PFD3_EN (1 << 14)
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#define PLL2_PFD2_EN (1 << 13)
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#define PLL2_PFD1_EN (1 << 12)
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#define PLL1_PFD4_EN (1 << 11)
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#define PLL1_PFD3_EN (1 << 10)
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#define PLL1_PFD2_EN (1 << 9)
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#define PLL1_PFD1_EN (1 << 8)
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/* CCM_CCR */
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#define FIRC_EN (1 << 16)
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#define FXOSC_EN (1 << 12)
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#define FXOSC_RDY (1 << 5)
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/* CCM_CSCDR1 */
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#define ENET_TS_EN (1 << 23)
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#define RMII_CLK_EN (1 << 24)
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#define SAI3_EN (1 << 19)
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/* CCM_CSCDR2 */
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#define ESAI_EN (1 << 30)
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#define ESDHC1_EN (1 << 29)
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#define ESDHC0_EN (1 << 28)
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#define NFC_EN (1 << 9)
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#define ESDHC1_DIV_S 20
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#define ESDHC1_DIV_M 0xf
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#define ESDHC0_DIV_S 16
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#define ESDHC0_DIV_M 0xf
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/* CCM_CSCDR3 */
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#define DCU0_EN (1 << 19)
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#define QSPI1_EN (1 << 12)
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#define QSPI1_DIV (1 << 11)
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#define QSPI1_X2_DIV (1 << 10)
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#define QSPI1_X4_DIV_M 0x3
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#define QSPI1_X4_DIV_S 8
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#define QSPI0_EN (1 << 4)
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#define QSPI0_DIV (1 << 3)
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#define QSPI0_X2_DIV (1 << 2)
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#define QSPI0_X4_DIV_M 0x3
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#define QSPI0_X4_DIV_S 0
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#define SAI3_DIV_SHIFT 12
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#define SAI3_DIV_MASK 0xf
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#define ESAI_DIV_SHIFT 24
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#define ESAI_DIV_MASK 0xf
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#define PLL4_CLK_DIV_SHIFT 6
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#define PLL4_CLK_DIV_MASK 0x7
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#define IPG_CLK_DIV_SHIFT 11
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#define IPG_CLK_DIV_MASK 0x3
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#define ESAI_CLK_SEL_SHIFT 20
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#define ESAI_CLK_SEL_MASK 0x3
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#define SAI3_CLK_SEL_SHIFT 6
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#define SAI3_CLK_SEL_MASK 0x3
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#define CKO1_EN (1 << 10)
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#define CKO1_DIV_MASK 0xf
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#define CKO1_DIV_SHIFT 6
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#define CKO1_SEL_MASK 0x3f
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#define CKO1_SEL_SHIFT 0
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#define CKO1_PLL4_MAIN 0x6
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#define CKO1_PLL4_DIVD 0x7
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struct clk {
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uint32_t reg;
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uint32_t enable_reg;
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uint32_t div_mask;
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uint32_t div_shift;
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uint32_t div_val;
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uint32_t sel_reg;
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uint32_t sel_mask;
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uint32_t sel_shift;
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uint32_t sel_val;
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};
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static struct clk ipg_clk = {
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.reg = CCM_CACRR,
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.enable_reg = 0,
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.div_mask = IPG_CLK_DIV_MASK,
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.div_shift = IPG_CLK_DIV_SHIFT,
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.div_val = 1, /* Divide by 2 */
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.sel_reg = 0,
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.sel_mask = 0,
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.sel_shift = 0,
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.sel_val = 0,
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};
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/*
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PLL4 clock divider (before switching the clocks should be gated)
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000 Divide by 1 (only if PLL frequency less than or equal to 650 MHz)
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001 Divide by 4
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010 Divide by 6
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011 Divide by 8
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100 Divide by 10
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101 Divide by 12
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110 Divide by 14
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111 Divide by 16
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*/
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static struct clk pll4_clk = {
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.reg = CCM_CACRR,
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.enable_reg = 0,
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.div_mask = PLL4_CLK_DIV_MASK,
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.div_shift = PLL4_CLK_DIV_SHIFT,
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.div_val = 5, /* Divide by 12 */
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.sel_reg = 0,
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.sel_mask = 0,
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.sel_shift = 0,
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.sel_val = 0,
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};
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static struct clk sai3_clk = {
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.reg = CCM_CSCDR1,
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.enable_reg = SAI3_EN,
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.div_mask = SAI3_DIV_MASK,
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.div_shift = SAI3_DIV_SHIFT,
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.div_val = 1,
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.sel_reg = CCM_CSCMR1,
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.sel_mask = SAI3_CLK_SEL_MASK,
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.sel_shift = SAI3_CLK_SEL_SHIFT,
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.sel_val = 0x3, /* Divided PLL4 main clock */
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};
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static struct clk cko1_clk = {
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.reg = CCM_CCOSR,
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.enable_reg = CKO1_EN,
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.div_mask = CKO1_DIV_MASK,
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.div_shift = CKO1_DIV_SHIFT,
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.div_val = 1,
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.sel_reg = CCM_CCOSR,
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.sel_mask = CKO1_SEL_MASK,
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.sel_shift = CKO1_SEL_SHIFT,
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.sel_val = CKO1_PLL4_DIVD,
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};
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static struct clk esdhc0_clk = {
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.reg = CCM_CSCDR2,
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.enable_reg = ESDHC0_EN,
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.div_mask = ESDHC0_DIV_M,
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.div_shift = ESDHC0_DIV_S,
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.div_val = 0x9,
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.sel_reg = 0,
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.sel_mask = 0,
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.sel_shift = 0,
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.sel_val = 0,
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};
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static struct clk esdhc1_clk = {
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.reg = CCM_CSCDR2,
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.enable_reg = ESDHC1_EN,
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.div_mask = ESDHC1_DIV_M,
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.div_shift = ESDHC1_DIV_S,
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.div_val = 0x9,
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.sel_reg = 0,
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.sel_mask = 0,
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.sel_shift = 0,
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.sel_val = 0,
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};
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static struct clk qspi0_clk = {
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.reg = CCM_CSCDR3,
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.enable_reg = QSPI0_EN,
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.div_mask = 0,
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.div_shift = 0,
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.div_val = 0,
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.sel_reg = 0,
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.sel_mask = 0,
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.sel_shift = 0,
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.sel_val = 0,
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};
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static struct clk dcu0_clk = {
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.reg = CCM_CSCDR3,
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.enable_reg = DCU0_EN,
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.div_mask = 0x7,
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.div_shift = 16, /* DCU0_DIV */
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.div_val = 0, /* divide by 1 */
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.sel_reg = 0,
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.sel_mask = 0,
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.sel_shift = 0,
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.sel_val = 0,
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};
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static struct clk enet_clk = {
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.reg = CCM_CSCDR1,
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.enable_reg = (ENET_TS_EN | RMII_CLK_EN),
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.div_mask = 0,
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.div_shift = 0,
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.div_val = 0,
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.sel_reg = 0,
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.sel_mask = 0,
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.sel_shift = 0,
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.sel_val = 0,
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};
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static struct clk nand_clk = {
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.reg = CCM_CSCDR2,
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.enable_reg = NFC_EN,
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.div_mask = 0,
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.div_shift = 0,
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.div_val = 0,
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.sel_reg = 0,
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.sel_mask = 0,
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.sel_shift = 0,
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.sel_val = 0,
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};
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/*
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Divider to generate ESAI clock
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0000 Divide by 1
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0001 Divide by 2
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... ...
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1111 Divide by 16
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*/
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static struct clk esai_clk = {
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.reg = CCM_CSCDR2,
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.enable_reg = ESAI_EN,
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.div_mask = ESAI_DIV_MASK,
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.div_shift = ESAI_DIV_SHIFT,
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.div_val = 3, /* Divide by 4 */
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.sel_reg = CCM_CSCMR1,
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.sel_mask = ESAI_CLK_SEL_MASK,
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.sel_shift = ESAI_CLK_SEL_SHIFT,
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.sel_val = 0x3, /* Divided PLL4 main clock */
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};
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struct clock_entry {
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char *name;
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struct clk *clk;
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};
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static struct clock_entry clock_map[] = {
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{"ipg", &ipg_clk},
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{"pll4", &pll4_clk},
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{"sai3", &sai3_clk},
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{"cko1", &cko1_clk},
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{"esdhc0", &esdhc0_clk},
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{"esdhc1", &esdhc1_clk},
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{"qspi0", &qspi0_clk},
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{"dcu0", &dcu0_clk},
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{"enet", &enet_clk},
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{"nand", &nand_clk},
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{"esai", &esai_clk},
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{NULL, NULL}
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};
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struct ccm_softc {
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struct resource *res[1];
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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device_t dev;
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};
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static struct resource_spec ccm_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static int
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ccm_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "fsl,mvf600-ccm"))
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return (ENXIO);
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device_set_desc(dev, "Vybrid Family CCM Unit");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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set_clock(struct ccm_softc *sc, char *name)
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{
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struct clk *clk;
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int reg;
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int i;
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for (i = 0; clock_map[i].name != NULL; i++) {
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if (strcmp(clock_map[i].name, name) == 0) {
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#if 0
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device_printf(sc->dev, "Configuring %s clk\n", name);
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#endif
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clk = clock_map[i].clk;
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if (clk->sel_reg != 0) {
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reg = READ4(sc, clk->sel_reg);
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reg &= ~(clk->sel_mask << clk->sel_shift);
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reg |= (clk->sel_val << clk->sel_shift);
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WRITE4(sc, clk->sel_reg, reg);
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};
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reg = READ4(sc, clk->reg);
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reg |= clk->enable_reg;
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reg &= ~(clk->div_mask << clk->div_shift);
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reg |= (clk->div_val << clk->div_shift);
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WRITE4(sc, clk->reg, reg);
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};
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};
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return (0);
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}
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static int
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ccm_fdt_set(struct ccm_softc *sc)
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{
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phandle_t child, parent, root;
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int len;
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char *fdt_config, *name;
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root = OF_finddevice("/");
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len = 0;
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parent = root;
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/* Find 'clock_names' prop in the tree */
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for (child = OF_child(parent); child != 0; child = OF_peer(child)) {
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/* Find a 'leaf'. Start the search from this node. */
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while (OF_child(child)) {
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parent = child;
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child = OF_child(child);
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}
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if (!fdt_is_enabled(child))
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continue;
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if ((len = OF_getproplen(child, "clock_names")) > 0) {
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len = OF_getproplen(child, "clock_names");
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OF_getprop_alloc(child, "clock_names", 1,
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(void **)&fdt_config);
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while (len > 0) {
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name = fdt_config;
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fdt_config += strlen(name) + 1;
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len -= strlen(name) + 1;
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set_clock(sc, name);
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};
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};
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if (OF_peer(child) == 0) {
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/* No more siblings. */
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child = parent;
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parent = OF_parent(child);
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}
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}
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return (0);
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}
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static int
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ccm_attach(device_t dev)
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{
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struct ccm_softc *sc;
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int reg;
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int i;
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sc = device_get_softc(dev);
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sc->dev = dev;
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if (bus_alloc_resources(dev, ccm_spec, sc->res)) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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/* Memory interface */
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sc->bst = rman_get_bustag(sc->res[0]);
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sc->bsh = rman_get_bushandle(sc->res[0]);
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/* Enable oscillator */
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reg = READ4(sc, CCM_CCR);
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reg |= (FIRC_EN | FXOSC_EN);
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WRITE4(sc, CCM_CCR, reg);
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/* Wait 10 times */
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for (i = 0; i < 10; i++) {
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if (READ4(sc, CCM_CSR) & FXOSC_RDY) {
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device_printf(sc->dev, "On board oscillator is ready.\n");
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break;
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}
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cpufunc_nullop();
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}
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/* Clock is on during all modes, except stop mode. */
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for (i = 0; i < CCM_CCGRN; i++) {
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WRITE4(sc, CCM_CCGR(i), 0xffffffff);
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}
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/* Take and apply FDT clocks */
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ccm_fdt_set(sc);
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return (0);
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}
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static device_method_t ccm_methods[] = {
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DEVMETHOD(device_probe, ccm_probe),
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DEVMETHOD(device_attach, ccm_attach),
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{ 0, 0 }
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};
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static driver_t ccm_driver = {
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"ccm",
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ccm_methods,
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sizeof(struct ccm_softc),
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};
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static devclass_t ccm_devclass;
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DRIVER_MODULE(ccm, simplebus, ccm_driver, ccm_devclass, 0, 0);
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