66f61b8256
with one of the following (I486_CPU,I586_CPU,I686_CPU) so it can take advantage of the very quick bswap insn. This keeps LKMs from being built to take advantage of the insn, but also makes sure that the LKMs can be run on all CPUs. (The LKMs don't pick up the CPU options :-( ).
122 lines
3.8 KiB
C
122 lines
3.8 KiB
C
/*
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* Copyright (c) 1987, 1991 Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)endian.h 7.8 (Berkeley) 4/3/91
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* $Id: endian.h,v 1.9 1996/11/29 16:22:22 dyson Exp $
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*/
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#ifndef _MACHINE_ENDIAN_H_
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#define _MACHINE_ENDIAN_H_
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/*
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* Define the order of 32-bit words in 64-bit words.
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*/
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#define _QUAD_HIGHWORD 1
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#define _QUAD_LOWWORD 0
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/*
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* Definitions for byte order, according to byte significance from low
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* address to high.
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*/
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#define LITTLE_ENDIAN 1234 /* LSB first: i386, vax */
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#define BIG_ENDIAN 4321 /* MSB first: 68000, ibm, net */
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#define PDP_ENDIAN 3412 /* LSB first in word, MSW first in long */
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#define BYTE_ORDER LITTLE_ENDIAN
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#ifndef KERNEL
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#include <sys/cdefs.h>
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#endif
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#define __word_swap_long(x) \
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__extension__ ({ register u_long __X = (x); \
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__asm ("rorl $16, %1" \
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: "=r" (__X) \
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: "0" (__X)); \
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__X; })
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#if defined(KERNEL) && (defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)) && !defined(I386_CPU)
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#define __byte_swap_long(x) \
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__extension__ ({ register u_long __X = (x); \
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__asm ("bswap %0" \
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: "=r" (__X) \
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: "0" (__X)); \
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__X; })
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#else
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#define __byte_swap_long(x) \
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__extension__ ({ register u_long __X = (x); \
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__asm ("xchgb %h1, %b1\n\trorl $16, %1\n\txchgb %h1, %b1" \
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: "=q" (__X) \
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: "0" (__X)); \
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__X; })
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#endif
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#define __byte_swap_word(x) \
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__extension__ ({ register u_short __X = (x); \
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__asm ("xchgb %h1, %b1" \
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: "=q" (__X) \
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: "0" (__X)); \
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__X; })
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/*
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* Macros for network/external number representation conversion.
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*/
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#if BYTE_ORDER == BIG_ENDIAN && !defined(lint)
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#define ntohl(x) (x)
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#define ntohs(x) (x)
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#define htonl(x) (x)
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#define htons(x) (x)
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#define NTOHL(x) (x)
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#define NTOHS(x) (x)
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#define HTONL(x) (x)
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#define HTONS(x) (x)
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#else
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#ifdef __GNUC__
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#define ntohl __byte_swap_long
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#define ntohs __byte_swap_word
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#define htonl __byte_swap_long
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#define htons __byte_swap_word
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#endif
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#define NTOHL(x) ((x) = ntohl((u_long)(x)))
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#define NTOHS(x) ((x) = ntohs((u_short)(x)))
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#define HTONL(x) ((x) = htonl((u_long)(x)))
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#define HTONS(x) ((x) = htons((u_short)(x)))
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#endif
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#endif /* !_MACHINE_ENDIAN_H_ */
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