468d6f48b3
* arge0 doesn't (yet) work via the switch PHY ports; I'm not sure why. * arge1 maps to the WAN port. That works. TODO: * The PLL register needs a different (non-default) value for Gigabit Ethernet. The board setup code needs to be extended a bit to allow for non-default pll_1000 values - right now, those values come out of hard-coded values in the per-chip set_pll_ge() routines. Obtained from: Linux / OpenWRT |
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adm5120 | ||
alchemy | ||
atheros | ||
cavium | ||
compile | ||
conf | ||
idt | ||
include | ||
malta | ||
mips | ||
nlm | ||
rmi | ||
rt305x | ||
sentry5 | ||
sibyte |