8e01fdea2b
PL (programmable logic) uses FCLK0..FCLK3 as a clock sources.
Normally they're configured by first stage boot loader (FSBL)
and normal user never has to touch them. These sysctls may come
useful for hardware developers
hw.fpga.fclk.N.source: clock source (IO, DDR, ARM)
hw.fpga.fclk.N.freq: requested frequency in Hz
hw.fpga.fclk.N.actual_freq: actual frequency in Hz (R/O)
hw.fgpa.level_shifters: 0/1 to enable/disable PS-PL level shifters,
normally they're enabled either by FSBL or after programming
FPGA through devcfg(4)
713 lines
17 KiB
C
713 lines
17 KiB
C
/*-
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* Copyright (c) 2013 Thomas Skibo
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Zynq-700 SLCR driver. Provides hooks for cpu_reset and PL control stuff.
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* In the future, maybe MIO control, clock control, etc. could go here.
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*
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* Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
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* (v1.4) November 16, 2012. Xilinx doc UG585.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/sysctl.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/stdarg.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/xilinx/zy7_slcr.h>
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struct zy7_slcr_softc {
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device_t dev;
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struct mtx sc_mtx;
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struct resource *mem_res;
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};
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static struct zy7_slcr_softc *zy7_slcr_softc_p;
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extern void (*zynq7_cpu_reset);
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#define ZSLCR_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
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#define ZSLCR_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
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#define ZSLCR_LOCK_INIT(sc) \
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mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
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"zy7_slcr", MTX_DEF)
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#define ZSLCR_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
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#define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))
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#define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val)))
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#define ZYNQ_DEFAULT_PS_CLK_FREQUENCY 33333333 /* 33.3 Mhz */
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SYSCTL_NODE(_hw, OID_AUTO, zynq, CTLFLAG_RD, 0, "Xilinx Zynq-7000");
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static char zynq_bootmode[64];
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SYSCTL_STRING(_hw_zynq, OID_AUTO, bootmode, CTLFLAG_RD, zynq_bootmode, 0,
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"Zynq boot mode");
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static char zynq_pssid[100];
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SYSCTL_STRING(_hw_zynq, OID_AUTO, pssid, CTLFLAG_RD, zynq_pssid, 0,
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"Zynq PSS IDCODE");
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static uint32_t zynq_reboot_status;
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SYSCTL_INT(_hw_zynq, OID_AUTO, reboot_status, CTLFLAG_RD, &zynq_reboot_status,
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0, "Zynq REBOOT_STATUS register");
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static int ps_clk_frequency;
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SYSCTL_INT(_hw_zynq, OID_AUTO, ps_clk_frequency, CTLFLAG_RD, &ps_clk_frequency,
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0, "Zynq PS_CLK Frequency");
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static int io_pll_frequency;
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SYSCTL_INT(_hw_zynq, OID_AUTO, io_pll_frequency, CTLFLAG_RD, &io_pll_frequency,
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0, "Zynq IO PLL Frequency");
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static int arm_pll_frequency;
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SYSCTL_INT(_hw_zynq, OID_AUTO, arm_pll_frequency, CTLFLAG_RD,
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&arm_pll_frequency, 0, "Zynq ARM PLL Frequency");
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static int ddr_pll_frequency;
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SYSCTL_INT(_hw_zynq, OID_AUTO, ddr_pll_frequency, CTLFLAG_RD,
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&ddr_pll_frequency, 0, "Zynq DDR PLL Frequency");
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static void
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zy7_slcr_unlock(struct zy7_slcr_softc *sc)
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{
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/* Unlock SLCR with magic number. */
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WR4(sc, ZY7_SLCR_UNLOCK, ZY7_SLCR_UNLOCK_MAGIC);
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}
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static void
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zy7_slcr_lock(struct zy7_slcr_softc *sc)
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{
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/* Lock SLCR with magic number. */
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WR4(sc, ZY7_SLCR_LOCK, ZY7_SLCR_LOCK_MAGIC);
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}
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static void
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zy7_slcr_cpu_reset(void)
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{
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struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
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/* Unlock SLCR registers. */
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zy7_slcr_unlock(sc);
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/* This has something to do with a work-around so the fsbl will load
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* the bitstream after soft-reboot. It's very important.
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*/
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WR4(sc, ZY7_SLCR_REBOOT_STAT,
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RD4(sc, ZY7_SLCR_REBOOT_STAT) & 0xf0ffffff);
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/* Soft reset */
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WR4(sc, ZY7_SLCR_PSS_RST_CTRL, ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET);
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for (;;)
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;
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}
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/* Assert PL resets and disable level shifters in preparation of programming
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* the PL (FPGA) section. Called from zy7_devcfg.c.
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*/
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void
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zy7_slcr_preload_pl(void)
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{
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struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
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if (!sc)
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return;
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ZSLCR_LOCK(sc);
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/* Unlock SLCR registers. */
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zy7_slcr_unlock(sc);
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/* Assert top level output resets. */
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WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, ZY7_SLCR_FPGA_RST_CTRL_RST_ALL);
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/* Disable all level shifters. */
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WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0);
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/* Lock SLCR registers. */
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zy7_slcr_lock(sc);
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ZSLCR_UNLOCK(sc);
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}
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/* After PL configuration, enable level shifters and deassert top-level
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* PL resets. Called from zy7_devcfg.c. Optionally, the level shifters
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* can be left disabled but that's rare of an FPGA application. That option
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* is controled by a sysctl in the devcfg driver.
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*/
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void
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zy7_slcr_postload_pl(int en_level_shifters)
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{
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struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
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if (!sc)
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return;
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ZSLCR_LOCK(sc);
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/* Unlock SLCR registers. */
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zy7_slcr_unlock(sc);
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if (en_level_shifters)
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/* Enable level shifters. */
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WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL);
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/* Deassert top level output resets. */
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WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0);
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/* Lock SLCR registers. */
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zy7_slcr_lock(sc);
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ZSLCR_UNLOCK(sc);
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}
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/* Override cgem_set_refclk() in gigabit ethernet driver
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* (sys/dev/cadence/if_cgem.c). This function is called to
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* request a change in the gem's reference clock speed.
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*/
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int
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cgem_set_ref_clk(int unit, int frequency)
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{
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struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
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int div0, div1;
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if (!sc)
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return (-1);
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/* Find suitable divisor pairs. Round result to nearest khz
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* to test for match.
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*/
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for (div1 = 1; div1 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX; div1++) {
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div0 = (io_pll_frequency + div1 * frequency / 2) /
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div1 / frequency;
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if (div0 > 0 && div0 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_MAX &&
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((io_pll_frequency / div0 / div1) + 500) / 1000 ==
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(frequency + 500) / 1000)
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break;
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}
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if (div1 > ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX)
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return (-1);
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ZSLCR_LOCK(sc);
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/* Unlock SLCR registers. */
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zy7_slcr_unlock(sc);
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/* Modify GEM reference clock. */
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WR4(sc, unit ? ZY7_SLCR_GEM1_CLK_CTRL : ZY7_SLCR_GEM0_CLK_CTRL,
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(div1 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_SHIFT) |
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(div0 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_SHIFT) |
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ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_IO_PLL |
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ZY7_SLCR_GEM_CLK_CTRL_CLKACT);
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/* Lock SLCR registers. */
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zy7_slcr_lock(sc);
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ZSLCR_UNLOCK(sc);
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return (0);
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}
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/*
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* PL clocks management function
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*/
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int
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zy7_pl_fclk_set_source(int unit, int source)
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{
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struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
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uint32_t reg;
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if (!sc)
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return (-1);
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ZSLCR_LOCK(sc);
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/* Unlock SLCR registers. */
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zy7_slcr_unlock(sc);
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/* Modify FPGAx source. */
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reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
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reg &= ~(ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_MASK);
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reg |= (source << ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_SHIFT);
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WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg);
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/* Lock SLCR registers. */
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zy7_slcr_lock(sc);
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ZSLCR_UNLOCK(sc);
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return (0);
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}
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int
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zy7_pl_fclk_get_source(int unit)
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{
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struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
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uint32_t reg;
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int source;
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if (!sc)
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return (-1);
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ZSLCR_LOCK(sc);
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/* Modify GEM reference clock. */
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reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
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source = (reg & ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_MASK) >>
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ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_SHIFT;
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/* ZY7_PL_FCLK_SRC_IO is actually b0x */
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if ((source & 2) == 0)
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source = ZY7_PL_FCLK_SRC_IO;
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ZSLCR_UNLOCK(sc);
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return (source);
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}
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int
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zy7_pl_fclk_set_freq(int unit, int frequency)
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{
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struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
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int div0, div1;
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int base_frequency;
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uint32_t reg;
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int source;
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if (!sc)
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return (-1);
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source = zy7_pl_fclk_get_source(unit);
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switch (source) {
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case ZY7_PL_FCLK_SRC_IO:
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base_frequency = io_pll_frequency;
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break;
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case ZY7_PL_FCLK_SRC_ARM:
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base_frequency = arm_pll_frequency;
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break;
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case ZY7_PL_FCLK_SRC_DDR:
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base_frequency = ddr_pll_frequency;
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break;
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default:
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return (-1);
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}
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/* Find suitable divisor pairs. Round result to nearest khz
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* to test for match.
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*/
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for (div1 = 1; div1 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX; div1++) {
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div0 = (base_frequency + div1 * frequency / 2) /
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div1 / frequency;
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if (div0 > 0 && div0 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX &&
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((base_frequency / div0 / div1) + 500) / 1000 ==
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(frequency + 500) / 1000)
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break;
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}
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if (div1 > ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX)
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return (-1);
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ZSLCR_LOCK(sc);
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/* Unlock SLCR registers. */
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zy7_slcr_unlock(sc);
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/* Modify FPGAx reference clock. */
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reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
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reg &= ~(ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK |
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ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK);
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reg |= (div1 << ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT) |
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(div0 << ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_SHIFT);
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WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg);
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/* Lock SLCR registers. */
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zy7_slcr_lock(sc);
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ZSLCR_UNLOCK(sc);
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return (base_frequency / div0 / div1);
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}
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int
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zy7_pl_fclk_get_freq(int unit)
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{
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struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
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int div0, div1;
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int base_frequency;
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int frequency;
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uint32_t reg;
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int source;
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if (!sc)
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return (-1);
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source = zy7_pl_fclk_get_source(unit);
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switch (source) {
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case ZY7_PL_FCLK_SRC_IO:
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base_frequency = io_pll_frequency;
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break;
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case ZY7_PL_FCLK_SRC_ARM:
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base_frequency = arm_pll_frequency;
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break;
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case ZY7_PL_FCLK_SRC_DDR:
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base_frequency = ddr_pll_frequency;
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break;
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default:
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return (-1);
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}
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ZSLCR_LOCK(sc);
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/* Modify FPGAx reference clock. */
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reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
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div1 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK) >>
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ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT;
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div0 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK) >>
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ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_SHIFT;
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ZSLCR_UNLOCK(sc);
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if (div0 == 0)
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div0 = 1;
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if (div1 == 0)
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div1 = 1;
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frequency = (base_frequency / div0 / div1);
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/* Round to KHz */
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frequency = (frequency + 500) / 1000;
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frequency = frequency * 1000;
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return (frequency);
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}
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int
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zy7_pl_fclk_enable(int unit)
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{
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struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
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if (!sc)
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return (-1);
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ZSLCR_LOCK(sc);
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/* Unlock SLCR registers. */
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zy7_slcr_unlock(sc);
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WR4(sc, ZY7_SLCR_FPGA_THR_CTRL(unit), 0);
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WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 0);
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/* Lock SLCR registers. */
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zy7_slcr_lock(sc);
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ZSLCR_UNLOCK(sc);
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return (0);
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}
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int
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zy7_pl_fclk_disable(int unit)
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{
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struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
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if (!sc)
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return (-1);
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ZSLCR_LOCK(sc);
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/* Unlock SLCR registers. */
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zy7_slcr_unlock(sc);
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WR4(sc, ZY7_SLCR_FPGA_THR_CTRL(unit), 0);
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WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 1);
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/* Lock SLCR registers. */
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zy7_slcr_lock(sc);
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ZSLCR_UNLOCK(sc);
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return (0);
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}
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int
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zy7_pl_fclk_enabled(int unit)
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{
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struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
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uint32_t reg;
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if (!sc)
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return (-1);
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ZSLCR_LOCK(sc);
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reg = RD4(sc, ZY7_SLCR_FPGA_THR_CNT(unit));
|
|
ZSLCR_UNLOCK(sc);
|
|
|
|
return !(reg & 1);
|
|
}
|
|
|
|
int
|
|
zy7_pl_level_shifters_enabled()
|
|
{
|
|
struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
|
|
|
|
uint32_t reg;
|
|
|
|
if (!sc)
|
|
return (-1);
|
|
|
|
ZSLCR_LOCK(sc);
|
|
reg = RD4(sc, ZY7_SLCR_LVL_SHFTR_EN);
|
|
ZSLCR_UNLOCK(sc);
|
|
|
|
return (reg == ZY7_SLCR_LVL_SHFTR_EN_ALL);
|
|
}
|
|
|
|
void
|
|
zy7_pl_level_shifters_enable()
|
|
{
|
|
struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
|
|
|
|
if (!sc)
|
|
return;
|
|
|
|
ZSLCR_LOCK(sc);
|
|
zy7_slcr_unlock(sc);
|
|
WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL);
|
|
zy7_slcr_lock(sc);
|
|
ZSLCR_UNLOCK(sc);
|
|
}
|
|
|
|
void
|
|
zy7_pl_level_shifters_disable()
|
|
{
|
|
struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
|
|
|
|
if (!sc)
|
|
return;
|
|
|
|
ZSLCR_LOCK(sc);
|
|
zy7_slcr_unlock(sc);
|
|
WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0);
|
|
zy7_slcr_lock(sc);
|
|
ZSLCR_UNLOCK(sc);
|
|
}
|
|
|
|
static int
|
|
zy7_slcr_probe(device_t dev)
|
|
{
|
|
|
|
if (!ofw_bus_status_okay(dev))
|
|
return (ENXIO);
|
|
|
|
if (!ofw_bus_is_compatible(dev, "xlnx,zy7_slcr"))
|
|
return (ENXIO);
|
|
|
|
device_set_desc(dev, "Zynq-7000 slcr block");
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
zy7_slcr_attach(device_t dev)
|
|
{
|
|
struct zy7_slcr_softc *sc = device_get_softc(dev);
|
|
int rid;
|
|
phandle_t node;
|
|
pcell_t cell;
|
|
uint32_t bootmode;
|
|
uint32_t pss_idcode;
|
|
uint32_t arm_pll_ctrl;
|
|
uint32_t ddr_pll_ctrl;
|
|
uint32_t io_pll_ctrl;
|
|
static char *bootdev_names[] = {
|
|
"JTAG", "Quad-SPI", "NOR", "(3?)",
|
|
"NAND", "SD Card", "(6?)", "(7?)"
|
|
};
|
|
|
|
/* Allow only one attach. */
|
|
if (zy7_slcr_softc_p != NULL)
|
|
return (ENXIO);
|
|
|
|
sc->dev = dev;
|
|
|
|
ZSLCR_LOCK_INIT(sc);
|
|
|
|
/* Get memory resource. */
|
|
rid = 0;
|
|
sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
|
|
RF_ACTIVE);
|
|
if (sc->mem_res == NULL) {
|
|
device_printf(dev, "could not allocate memory resources.\n");
|
|
return (ENOMEM);
|
|
}
|
|
|
|
/* Hook up cpu_reset. */
|
|
zy7_slcr_softc_p = sc;
|
|
zynq7_cpu_reset = zy7_slcr_cpu_reset;
|
|
|
|
/* Read info and set sysctls. */
|
|
bootmode = RD4(sc, ZY7_SLCR_BOOT_MODE);
|
|
snprintf(zynq_bootmode, sizeof(zynq_bootmode),
|
|
"0x%x: boot device: %s", bootmode,
|
|
bootdev_names[bootmode & ZY7_SLCR_BOOT_MODE_BOOTDEV_MASK]);
|
|
|
|
pss_idcode = RD4(sc, ZY7_SLCR_PSS_IDCODE);
|
|
snprintf(zynq_pssid, sizeof(zynq_pssid),
|
|
"0x%x: manufacturer: 0x%x device: 0x%x "
|
|
"family: 0x%x sub-family: 0x%x rev: 0x%x",
|
|
pss_idcode,
|
|
(pss_idcode & ZY7_SLCR_PSS_IDCODE_MNFR_ID_MASK) >>
|
|
ZY7_SLCR_PSS_IDCODE_MNFR_ID_SHIFT,
|
|
(pss_idcode & ZY7_SLCR_PSS_IDCODE_DEVICE_MASK) >>
|
|
ZY7_SLCR_PSS_IDCODE_DEVICE_SHIFT,
|
|
(pss_idcode & ZY7_SLCR_PSS_IDCODE_FAMILY_MASK) >>
|
|
ZY7_SLCR_PSS_IDCODE_FAMILY_SHIFT,
|
|
(pss_idcode & ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_MASK) >>
|
|
ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_SHIFT,
|
|
(pss_idcode & ZY7_SLCR_PSS_IDCODE_REVISION_MASK) >>
|
|
ZY7_SLCR_PSS_IDCODE_REVISION_SHIFT);
|
|
|
|
zynq_reboot_status = RD4(sc, ZY7_SLCR_REBOOT_STAT);
|
|
|
|
/* Derive PLL frequencies from PS_CLK. */
|
|
node = ofw_bus_get_node(dev);
|
|
if (OF_getprop(node, "clock-frequency", &cell, sizeof(cell)) > 0)
|
|
ps_clk_frequency = fdt32_to_cpu(cell);
|
|
else
|
|
ps_clk_frequency = ZYNQ_DEFAULT_PS_CLK_FREQUENCY;
|
|
|
|
arm_pll_ctrl = RD4(sc, ZY7_SLCR_ARM_PLL_CTRL);
|
|
ddr_pll_ctrl = RD4(sc, ZY7_SLCR_DDR_PLL_CTRL);
|
|
io_pll_ctrl = RD4(sc, ZY7_SLCR_IO_PLL_CTRL);
|
|
|
|
/* Determine ARM PLL frequency. */
|
|
if (((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 &&
|
|
(arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) ||
|
|
((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 &&
|
|
(bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0))
|
|
/* PLL is bypassed. */
|
|
arm_pll_frequency = ps_clk_frequency;
|
|
else
|
|
arm_pll_frequency = ps_clk_frequency *
|
|
((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >>
|
|
ZY7_SLCR_PLL_CTRL_FDIV_SHIFT);
|
|
|
|
/* Determine DDR PLL frequency. */
|
|
if (((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 &&
|
|
(ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) ||
|
|
((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 &&
|
|
(bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0))
|
|
/* PLL is bypassed. */
|
|
ddr_pll_frequency = ps_clk_frequency;
|
|
else
|
|
ddr_pll_frequency = ps_clk_frequency *
|
|
((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >>
|
|
ZY7_SLCR_PLL_CTRL_FDIV_SHIFT);
|
|
|
|
/* Determine IO PLL frequency. */
|
|
if (((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 &&
|
|
(io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) ||
|
|
((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 &&
|
|
(bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0))
|
|
/* PLL is bypassed. */
|
|
io_pll_frequency = ps_clk_frequency;
|
|
else
|
|
io_pll_frequency = ps_clk_frequency *
|
|
((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >>
|
|
ZY7_SLCR_PLL_CTRL_FDIV_SHIFT);
|
|
|
|
/* Lock SLCR registers. */
|
|
zy7_slcr_lock(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
zy7_slcr_detach(device_t dev)
|
|
{
|
|
struct zy7_slcr_softc *sc = device_get_softc(dev);
|
|
|
|
bus_generic_detach(dev);
|
|
|
|
/* Release memory resource. */
|
|
if (sc->mem_res != NULL)
|
|
bus_release_resource(dev, SYS_RES_MEMORY,
|
|
rman_get_rid(sc->mem_res), sc->mem_res);
|
|
|
|
zy7_slcr_softc_p = NULL;
|
|
zynq7_cpu_reset = NULL;
|
|
|
|
ZSLCR_LOCK_DESTROY(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t zy7_slcr_methods[] = {
|
|
/* device_if */
|
|
DEVMETHOD(device_probe, zy7_slcr_probe),
|
|
DEVMETHOD(device_attach, zy7_slcr_attach),
|
|
DEVMETHOD(device_detach, zy7_slcr_detach),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t zy7_slcr_driver = {
|
|
"zy7_slcr",
|
|
zy7_slcr_methods,
|
|
sizeof(struct zy7_slcr_softc),
|
|
};
|
|
static devclass_t zy7_slcr_devclass;
|
|
|
|
DRIVER_MODULE(zy7_slcr, simplebus, zy7_slcr_driver, zy7_slcr_devclass, 0, 0);
|
|
MODULE_VERSION(zy7_slcr, 1);
|