d943d79a36
This driver supports internal PCIe Root Complex on Cavium ThunderX Pass 1.1 hardware. Reviewed by: andrew, jhb Obtained from: Semihalf Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D3031
559 lines
15 KiB
C
559 lines
15 KiB
C
/*-
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* Copyright (c) 2015 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Semihalf under
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* the sponsorship of the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* PCIe root complex driver for Cavium Thunder SOC */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/rman.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/cpuset.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcib_private.h>
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#include <machine/cpu.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include "thunder_pcie_common.h"
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#include "pcib_if.h"
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/* Assembling ECAM Configuration Address */
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#define PCIE_BUS_SHIFT 20
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#define PCIE_SLOT_SHIFT 15
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#define PCIE_FUNC_SHIFT 12
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#define PCIE_BUS_MASK 0xFF
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#define PCIE_SLOT_MASK 0x1F
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#define PCIE_FUNC_MASK 0x07
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#define PCIE_REG_MASK 0xFFF
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#define PCIE_ADDR_OFFSET(bus, slot, func, reg) \
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((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \
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(((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \
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(((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \
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((reg) & PCIE_REG_MASK))
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#define THUNDER_ECAM0_CFG_BASE 0x848000000000UL
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#define THUNDER_ECAM1_CFG_BASE 0x849000000000UL
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#define THUNDER_ECAM2_CFG_BASE 0x84a000000000UL
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#define THUNDER_ECAM3_CFG_BASE 0x84b000000000UL
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#define THUNDER_ECAM4_CFG_BASE 0x948000000000UL
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#define THUNDER_ECAM5_CFG_BASE 0x949000000000UL
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#define THUNDER_ECAM6_CFG_BASE 0x94a000000000UL
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#define THUNDER_ECAM7_CFG_BASE 0x94b000000000UL
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#define OFW_CELL_TO_UINT64(cell) \
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(((uint64_t)(*(cell)) << 32) | (uint64_t)(*((cell) + 1)))
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#define SPACE_CODE_SHIFT 24
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#define SPACE_CODE_MASK 0x3
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#define SPACE_CODE_IO_SPACE 0x1
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#define PROPS_CELL_SIZE 1
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#define PCI_ADDR_CELL_SIZE 2
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struct thunder_pcie_softc {
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struct pcie_range ranges[MAX_RANGES_TUPLES];
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struct rman mem_rman;
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struct resource *res;
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int ecam;
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device_t dev;
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};
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/* Forward prototypes */
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static struct resource *thunder_pcie_alloc_resource(device_t,
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device_t, int, int *, u_long, u_long, u_long, u_int);
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static int thunder_pcie_attach(device_t);
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static int thunder_pcie_identify_pcib(device_t);
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static int thunder_pcie_maxslots(device_t);
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static int parse_pci_mem_ranges(struct thunder_pcie_softc *);
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static int thunder_pcie_probe(device_t);
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static uint32_t thunder_pcie_read_config(device_t, u_int, u_int, u_int, u_int,
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int);
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static int thunder_pcie_read_ivar(device_t, device_t, int, uintptr_t *);
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static int thunder_pcie_release_resource(device_t, device_t, int, int,
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struct resource *);
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static void thunder_pcie_write_config(device_t, u_int, u_int,
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u_int, u_int, uint32_t, int);
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static int thunder_pcie_write_ivar(device_t, device_t, int, uintptr_t);
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static int
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thunder_pcie_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_is_compatible(dev, "cavium,thunder-pcie")) {
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device_set_desc(dev, "Cavium Integrated PCI/PCI-E Controller");
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return (BUS_PROBE_DEFAULT);
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}
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return (ENXIO);
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}
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static int
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thunder_pcie_attach(device_t dev)
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{
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int rid;
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struct thunder_pcie_softc *sc;
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int error;
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int tuple;
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uint64_t base, size;
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sc = device_get_softc(dev);
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sc->dev = dev;
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/* Identify pcib domain */
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if (thunder_pcie_identify_pcib(dev))
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return (ENXIO);
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rid = 0;
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sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
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if (sc->res == NULL) {
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device_printf(dev, "could not map memory.\n");
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return (ENXIO);
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}
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sc->mem_rman.rm_type = RMAN_ARRAY;
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sc->mem_rman.rm_descr = "PCIe Memory";
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/* Retrieve 'ranges' property from FDT */
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if (bootverbose)
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device_printf(dev, "parsing FDT for ECAM%d:\n",
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sc->ecam);
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if (parse_pci_mem_ranges(sc))
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return (ENXIO);
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/* Initialize rman and allocate memory regions */
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error = rman_init(&sc->mem_rman);
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if (error) {
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device_printf(dev, "rman_init() failed. error = %d\n", error);
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return (error);
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}
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for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
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base = sc->ranges[tuple].phys_base;
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size = sc->ranges[tuple].size;
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if ((base == 0) || (size == 0))
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continue; /* empty range element */
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error = rman_manage_region(&sc->mem_rman, base, base + size - 1);
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if (error) {
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device_printf(dev, "rman_manage_region() failed. error = %d\n", error);
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rman_fini(&sc->mem_rman);
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return (error);
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}
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}
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device_add_child(dev, "pci", -1);
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return (bus_generic_attach(dev));
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}
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static int
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parse_pci_mem_ranges(struct thunder_pcie_softc *sc)
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{
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phandle_t node;
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pcell_t pci_addr_cells, parent_addr_cells, size_cells;
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pcell_t attributes;
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pcell_t *ranges_buf, *cell_ptr;
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int cells_count, tuples_count;
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int tuple;
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int rv;
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node = ofw_bus_get_node(sc->dev);
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/* Find address cells if present */
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if (OF_getencprop(node, "#address-cells", &pci_addr_cells,
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sizeof(pci_addr_cells)) < sizeof(pci_addr_cells))
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pci_addr_cells = 2;
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/* Find size cells if present */
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if (OF_getencprop(node, "#size-cells", &size_cells,
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sizeof(size_cells)) < sizeof(size_cells))
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size_cells = 1;
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/* Find parent address cells if present */
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if (OF_getencprop(OF_parent(node), "#address-cells",
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&parent_addr_cells, sizeof(parent_addr_cells)) < sizeof(parent_addr_cells))
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parent_addr_cells = 2;
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/* Check if FDT format matches driver requirements */
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if ((parent_addr_cells != 2) || (pci_addr_cells != 3) ||
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(size_cells != 2)) {
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device_printf(sc->dev,
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"Unexpected number of address or size cells in FDT "
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" %d:%d:%d\n",
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parent_addr_cells, pci_addr_cells, size_cells);
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return (ENXIO);
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}
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cells_count = OF_getencprop_alloc(node, "ranges",
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sizeof(pcell_t), (void **)&ranges_buf);
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if (cells_count == -1) {
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device_printf(sc->dev, "Error parsing FDT 'ranges' property\n");
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return (ENXIO);
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}
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tuples_count = cells_count /
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(pci_addr_cells + parent_addr_cells + size_cells);
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if ((tuples_count > MAX_RANGES_TUPLES) ||
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(tuples_count < MIN_RANGES_TUPLES)) {
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device_printf(sc->dev,
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"Unexpected number of 'ranges' tuples in FDT\n");
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rv = ENXIO;
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goto out;
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}
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cell_ptr = ranges_buf;
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for (tuple = 0; tuple < tuples_count; tuple++) {
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/*
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* TUPLE FORMAT:
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* attributes - 32-bit attributes field
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* PCI address - bus address combined of two cells in
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* a following format:
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* <ADDR MSB> <ADDR LSB>
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* PA address - physical address combined of two cells in
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* a following format:
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* <ADDR MSB> <ADDR LSB>
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* size - range size combined of two cells in
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* a following format:
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* <ADDR MSB> <ADDR LSB>
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*/
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attributes = *cell_ptr;
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attributes = (attributes >> SPACE_CODE_SHIFT) & SPACE_CODE_MASK;
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if (attributes == SPACE_CODE_IO_SPACE) {
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/* Internal PCIe does not support IO space, ignore. */
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sc->ranges[tuple].phys_base = 0;
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sc->ranges[tuple].size = 0;
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cell_ptr +=
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(pci_addr_cells + parent_addr_cells + size_cells);
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continue;
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}
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cell_ptr += PROPS_CELL_SIZE;
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sc->ranges[tuple].pci_base = OFW_CELL_TO_UINT64(cell_ptr);
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cell_ptr += PCI_ADDR_CELL_SIZE;
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sc->ranges[tuple].phys_base = OFW_CELL_TO_UINT64(cell_ptr);
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cell_ptr += parent_addr_cells;
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sc->ranges[tuple].size = OFW_CELL_TO_UINT64(cell_ptr);
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cell_ptr += size_cells;
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if (bootverbose) {
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device_printf(sc->dev,
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"\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx\n",
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sc->ranges[tuple].pci_base,
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sc->ranges[tuple].phys_base,
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sc->ranges[tuple].size);
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}
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}
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for (; tuple < MAX_RANGES_TUPLES; tuple++) {
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/* zero-fill remaining tuples to mark empty elements in array */
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sc->ranges[tuple].phys_base = 0;
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sc->ranges[tuple].size = 0;
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}
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rv = 0;
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out:
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free(ranges_buf, M_OFWPROP);
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return (rv);
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}
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static uint32_t
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thunder_pcie_read_config(device_t dev, u_int bus, u_int slot,
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u_int func, u_int reg, int bytes)
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{
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uint64_t offset;
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uint32_t data;
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struct thunder_pcie_softc *sc;
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bus_space_tag_t t;
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bus_space_handle_t h;
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if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
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(func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
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return (~0U);
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sc = device_get_softc(dev);
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offset = PCIE_ADDR_OFFSET(bus, slot, func, reg);
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t = rman_get_bustag(sc->res);
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h = rman_get_bushandle(sc->res);
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switch (bytes) {
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case 1:
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data = bus_space_read_1(t, h, offset);
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break;
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case 2:
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data = le16toh(bus_space_read_2(t, h, offset));
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break;
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case 4:
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data = le32toh(bus_space_read_4(t, h, offset));
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break;
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default:
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return (~0U);
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}
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return (data);
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}
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static void
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thunder_pcie_write_config(device_t dev, u_int bus, u_int slot,
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u_int func, u_int reg, uint32_t val, int bytes)
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{
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uint64_t offset;
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struct thunder_pcie_softc *sc;
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bus_space_tag_t t;
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bus_space_handle_t h;
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if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
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(func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
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return ;
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sc = device_get_softc(dev);
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offset = PCIE_ADDR_OFFSET(bus, slot, func, reg);
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t = rman_get_bustag(sc->res);
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h = rman_get_bushandle(sc->res);
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switch (bytes) {
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case 1:
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bus_space_write_1(t, h, offset, val);
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break;
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case 2:
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bus_space_write_2(t, h, offset, htole16(val));
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break;
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case 4:
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bus_space_write_4(t, h, offset, htole32(val));
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break;
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default:
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return;
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}
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}
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static int
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thunder_pcie_maxslots(device_t dev)
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{
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/* max slots per bus acc. to standard */
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return (PCI_SLOTMAX);
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}
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static int
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thunder_pcie_read_ivar(device_t dev, device_t child, int index,
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uintptr_t *result)
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{
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struct thunder_pcie_softc *sc;
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sc = device_get_softc(dev);
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if (index == PCIB_IVAR_BUS) {
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/* this pcib is always on bus 0 */
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*result = 0;
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return (0);
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}
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if (index == PCIB_IVAR_DOMAIN) {
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*result = sc->ecam;
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return (0);
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}
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return (ENOENT);
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}
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static int
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thunder_pcie_write_ivar(device_t dev, device_t child, int index,
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uintptr_t value)
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{
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return (ENOENT);
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}
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static int
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thunder_pcie_release_resource(device_t dev, device_t child, int type, int rid,
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struct resource *res)
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{
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if (type != SYS_RES_MEMORY)
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return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
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type, rid, res));
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return (rman_release_resource(res));
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}
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static struct resource *
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thunder_pcie_alloc_resource(device_t dev, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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{
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struct thunder_pcie_softc *sc = device_get_softc(dev);
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struct rman *rm = NULL;
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struct resource *res;
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switch (type) {
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case SYS_RES_IOPORT:
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goto fail;
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break;
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case SYS_RES_MEMORY:
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rm = &sc->mem_rman;
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break;
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default:
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return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
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type, rid, start, end, count, flags));
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};
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if ((start == 0UL) && (end == ~0UL)) {
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device_printf(dev,
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"Cannot allocate resource with unspecified range\n");
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goto fail;
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}
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/* Convert input BUS address to required PHYS */
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if (range_addr_is_pci(sc->ranges, start, count) == 0)
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goto fail;
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start = range_addr_pci_to_phys(sc->ranges, start);
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end = start + count - 1;
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if (bootverbose) {
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device_printf(dev,
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"rman_reserve_resource: start=%#lx, end=%#lx, count=%#lx\n",
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start, end, count);
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}
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res = rman_reserve_resource(rm, start, end, count, flags, child);
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if (res == NULL)
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goto fail;
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rman_set_rid(res, *rid);
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if ((flags & RF_ACTIVE) != 0)
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if (bus_activate_resource(child, type, *rid, res)) {
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rman_release_resource(res);
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goto fail;
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}
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return (res);
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fail:
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if (bootverbose) {
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device_printf(dev, "%s FAIL: type=%d, rid=%d, "
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"start=%016lx, end=%016lx, count=%016lx, flags=%x\n",
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__func__, type, *rid, start, end, count, flags);
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}
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return (NULL);
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}
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static int
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thunder_pcie_identify_pcib(device_t dev)
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{
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struct thunder_pcie_softc *sc;
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u_long start;
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sc = device_get_softc(dev);
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start = bus_get_resource_start(dev, SYS_RES_MEMORY, 0);
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switch(start) {
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case THUNDER_ECAM0_CFG_BASE:
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sc->ecam = 0;
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break;
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case THUNDER_ECAM1_CFG_BASE:
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|
sc->ecam = 1;
|
|
break;
|
|
case THUNDER_ECAM2_CFG_BASE:
|
|
sc->ecam = 2;
|
|
break;
|
|
case THUNDER_ECAM3_CFG_BASE:
|
|
sc->ecam = 3;
|
|
break;
|
|
case THUNDER_ECAM4_CFG_BASE:
|
|
sc->ecam = 4;
|
|
break;
|
|
case THUNDER_ECAM5_CFG_BASE:
|
|
sc->ecam = 5;
|
|
break;
|
|
case THUNDER_ECAM6_CFG_BASE:
|
|
sc->ecam = 6;
|
|
break;
|
|
case THUNDER_ECAM7_CFG_BASE:
|
|
sc->ecam = 7;
|
|
break;
|
|
default:
|
|
device_printf(dev,
|
|
"error: incorrect resource address=%#lx.\n", start);
|
|
return (ENXIO);
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t thunder_pcie_methods[] = {
|
|
DEVMETHOD(device_probe, thunder_pcie_probe),
|
|
DEVMETHOD(device_attach, thunder_pcie_attach),
|
|
DEVMETHOD(pcib_maxslots, thunder_pcie_maxslots),
|
|
DEVMETHOD(pcib_read_config, thunder_pcie_read_config),
|
|
DEVMETHOD(pcib_write_config, thunder_pcie_write_config),
|
|
DEVMETHOD(bus_read_ivar, thunder_pcie_read_ivar),
|
|
DEVMETHOD(bus_write_ivar, thunder_pcie_write_ivar),
|
|
DEVMETHOD(bus_alloc_resource, thunder_pcie_alloc_resource),
|
|
DEVMETHOD(bus_release_resource, thunder_pcie_release_resource),
|
|
DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
|
|
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
|
|
DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
|
|
DEVMETHOD(pcib_map_msi, thunder_common_map_msi),
|
|
DEVMETHOD(pcib_alloc_msix, thunder_common_alloc_msix),
|
|
DEVMETHOD(pcib_release_msix, thunder_common_release_msix),
|
|
DEVMETHOD(pcib_alloc_msi, thunder_common_alloc_msi),
|
|
DEVMETHOD(pcib_release_msi, thunder_common_release_msi),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t thunder_pcie_driver = {
|
|
"pcib",
|
|
thunder_pcie_methods,
|
|
sizeof(struct thunder_pcie_softc),
|
|
};
|
|
|
|
static devclass_t thunder_pcie_devclass;
|
|
|
|
DRIVER_MODULE(thunder_pcib, simplebus, thunder_pcie_driver,
|
|
thunder_pcie_devclass, 0, 0);
|
|
DRIVER_MODULE(thunder_pcib, ofwbus, thunder_pcie_driver,
|
|
thunder_pcie_devclass, 0, 0);
|