403 lines
9.7 KiB
C
403 lines
9.7 KiB
C
/*
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* Copyright (c) 1996, by Steve Passe
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: smptests.h,v 1.31 1998/03/07 20:48:16 tegge Exp $
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*/
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#ifndef _MACHINE_SMPTESTS_H_
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#define _MACHINE_SMPTESTS_H_
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/*
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* Various 'tests in progress' and configuration parameters.
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*/
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/*
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* Tor's clock improvements.
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*
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* When the giant kernel lock disappears, a different strategy should
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* probably be used, thus this patch can only be considered a temporary
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* measure.
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*
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* This patch causes (NCPU-1)*(128+100) extra IPIs per second.
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* During profiling, the number is (NCPU-1)*(1024+100) extra IPIs/s
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* in addition to extra IPIs due to forwarding ASTs to other CPUs.
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*
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* Having a shared AST flag in an SMP configuration is wrong, and I've
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* just kludged around it, based upon the kernel lock blocking other
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* processors from entering the kernel while handling an AST for one
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* processor. When the giant kernel lock disappers, this kludge breaks.
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*
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* -- Tor
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*/
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#define BETTER_CLOCK
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/*
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* Control the "giant lock" pushdown by logical steps.
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*/
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#define PUSHDOWN_LEVEL_1
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#define PUSHDOWN_LEVEL_2
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#define PUSHDOWN_LEVEL_3_NOT
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#define PUSHDOWN_LEVEL_4_NOT
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/*
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* XXX some temp debug control of cpl locks
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*/
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#ifdef PUSHDOWN_LEVEL_2
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#define REAL_ECPL /* exception.s: SCPL_LOCK/SCPL_UNLOCK */
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#define REAL_ICPL /* ipl.s: CPL_LOCK/CPL_UNLOCK/FAST */
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#define REAL_AICPL /* apic_ipl.s: SCPL_LOCK/SCPL_UNLOCK */
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#define REAL_AVCPL /* apic_vector.s: CPL_LOCK/CPL_UNLOCK */
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#define REAL_IFCPL /* ipl_funcs.c: SCPL_LOCK/SCPL_UNLOCK */
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#endif /* PUSHDOWN_LEVEL_2 */
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/*
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* The xCPL_LOCK/xCPL_UNLOCK defines control the spinlocks
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* that protect cpl/cml/cil and the spl functions.
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*/
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#ifdef REAL_ECPL
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#define ECPL_LOCK SCPL_LOCK
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#define ECPL_UNLOCK SCPL_UNLOCK
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#else
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#define ECPL_LOCK
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#define ECPL_UNLOCK
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#endif /* REAL_ECPL */
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#ifdef REAL_ICPL
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#define ICPL_LOCK CPL_LOCK
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#define ICPL_UNLOCK CPL_UNLOCK
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#define FAST_ICPL_UNLOCK movl $0, _cpl_lock
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#else
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#define ICPL_LOCK
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#define ICPL_UNLOCK
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#define FAST_ICPL_UNLOCK
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#endif /* REAL_ICPL */
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#ifdef REAL_AICPL
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#define AICPL_LOCK SCPL_LOCK
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#define AICPL_UNLOCK SCPL_UNLOCK
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#else
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#define AICPL_LOCK
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#define AICPL_UNLOCK
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#endif /* REAL_AICPL */
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#ifdef REAL_AVCPL
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#define AVCPL_LOCK CPL_LOCK
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#define AVCPL_UNLOCK CPL_UNLOCK
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#else
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#define AVCPL_LOCK
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#define AVCPL_UNLOCK
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#endif /* REAL_AVCPL */
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#ifdef REAL_IFCPL
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#define IFCPL_LOCK() SCPL_LOCK()
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#define IFCPL_UNLOCK() SCPL_UNLOCK()
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#else
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#define IFCPL_LOCK()
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#define IFCPL_UNLOCK()
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#endif /* REAL_IFCPL */
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/*
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* Debug version of simple_lock. This will store the CPU id of the
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* holding CPU along with the lock. When a CPU fails to get the lock
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* it compares its own id to the holder id. If they are the same it
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* panic()s, as simple locks are binary, and this would cause a deadlock.
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*
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*/
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#define SL_DEBUG
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/*
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* Put FAST_INTR() ISRs at an APIC priority above the regular INTs.
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* Allow the mp_lock() routines to handle FAST interrupts while spinning.
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*/
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#ifdef PUSHDOWN_LEVEL_1
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#define FAST_HI
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#endif
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/*
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* These defines enable critical region locking of areas that were
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* protected via cli/sti in the UP kernel.
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*
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* MPINTRLOCK protects all the generic areas.
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* COMLOCK protects the sio/cy drivers.
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* CLOCKLOCK protects clock hardware and data
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* known to be incomplete:
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* joystick lkm
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* ?
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*/
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#ifdef PUSHDOWN_LEVEL_1
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#define USE_MPINTRLOCK
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#define USE_COMLOCK
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#define USE_CLOCKLOCK
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#endif
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/*
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* Regular INTerrupts without the giant lock, NOT READY YET!!!
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*/
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#ifdef PUSHDOWN_LEVEL_4
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#define INTR_SIMPLELOCK
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#endif
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/*
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* Separate the INTR() portion of cpl into another variable: cml.
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*/
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#ifdef PUSHDOWN_LEVEL_3
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#define CPL_AND_CML
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#endif
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/*
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* Forces spl functions to spin while waiting for safe time to change cpl.
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*
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#define SPL_DEBUG_POSTCODE (slows the system down noticably)
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*/
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#ifdef PUSHDOWN_LEVEL_3
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#define INTR_SPL
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#define SPL_DEBUG
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#endif
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/*
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* Ignore the ipending bits when exiting FAST_INTR() routines.
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*
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***
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* according to Bruce:
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*
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* setsoft*() may set ipending. setsofttty() is actually used in the
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* FAST_INTR handler in some serial drivers. This is necessary to get
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* output completions and other urgent events handled as soon as possible.
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* The flag(s) could be set in a variable other than ipending, but they
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* needs to be checked against cpl to decide whether the software interrupt
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* handler can/should run.
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*
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* (FAST_INTR used to just return
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* in all cases until rev.1.7 of vector.s. This worked OK provided there
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* were no user-mode CPU hogs. CPU hogs caused an average latency of 1/2
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* clock tick for output completions...)
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***
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*
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* So I need to restore cpl handling someday, but AFTER
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* I finish making spl/cpl MP-safe.
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*/
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#ifdef PUSHDOWN_LEVEL_1
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#define FAST_WITHOUTCPL
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#endif
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/*
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* Use a simplelock to serialize FAST_INTR()s.
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* sio.c, and probably other FAST_INTR() drivers, never expected several CPUs
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* to be inside them at once. Things such as global vars prevent more
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* than 1 thread of execution from existing at once, so we serialize
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* the access of FAST_INTR()s via a simple lock.
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* One optimization on this would be a simple lock per DRIVER, but I'm
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* not sure how to organize that yet...
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*/
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#ifdef PUSHDOWN_LEVEL_1
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#define FAST_SIMPLELOCK
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#endif
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/*
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* Portions of the old TEST_LOPRIO code, back from the grave!
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*/
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#define GRAB_LOPRIO
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/*
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* Send CPUSTOP IPI for stop/restart of other CPUs on DDB break.
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*
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#define VERBOSE_CPUSTOP_ON_DDBBREAK
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*/
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#define CPUSTOP_ON_DDBBREAK
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/*
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* Bracket code/comments relevant to the current 'giant lock' model.
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* Everything is now the 'giant lock' model, but we will use this as
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* we start to "push down" the lock.
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*/
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#define GIANT_LOCK
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#ifdef APIC_IO
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/*
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* Enable extra counters for some selected locations in the interrupt handlers.
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* Look in apic_vector.s, apic_ipl.s and ipl.s for APIC_ITRACE or
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* APIC_INTR_DIAGNOSTIC.
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*/
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#undef APIC_INTR_DIAGNOSTIC
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/*
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* Add extra tracking of a specific interrupt. Look in apic_vector.s,
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* apic_ipl.s and ipl.s for APIC_ITRACE and log_intr_event.
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* APIC_INTR_DIAGNOSTIC must be defined for this to work.
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*/
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#ifdef APIC_INTR_DIAGNOSTIC
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#define APIC_INTR_DIAGNOSTIC_IRQ 17
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#endif
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/*
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* Don't assume that slow interrupt handler X is called from vector
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* X + ICU_OFFSET.
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*/
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#define APIC_INTR_REORDER
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/*
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* Redirect clock interrupts to a higher priority (fast intr) vector,
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* while still using the slow interrupt handler. Only effective when
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* APIC_INTR_REORDER is defined.
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*/
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#define APIC_INTR_HIGHPRI_CLOCK
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#endif /* APIC_IO */
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/*
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* Misc. counters.
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*
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#define COUNT_XINVLTLB_HITS
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*/
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/**
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* Hack to "fake-out" kernel into thinking it is running on a 'default config'.
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*
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* value == default type
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#define TEST_DEFAULT_CONFIG 6
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*/
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/*
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* Simple test code for IPI interaction, save for future...
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*
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#define TEST_TEST1
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#define IPI_TARGET_TEST1 1
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*/
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/*
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* Address of POST hardware port.
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* Defining this enables POSTCODE macros.
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*
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#define POST_ADDR 0x80
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*/
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/*
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* POST hardware macros.
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*/
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#ifdef POST_ADDR
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#define ASMPOSTCODE_INC \
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pushl %eax ; \
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movl _current_postcode, %eax ; \
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incl %eax ; \
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andl $0xff, %eax ; \
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movl %eax, _current_postcode ; \
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outb %al, $POST_ADDR ; \
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popl %eax
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/*
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* Overwrite the current_postcode value.
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*/
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#define ASMPOSTCODE(X) \
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pushl %eax ; \
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movl $X, %eax ; \
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movl %eax, _current_postcode ; \
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outb %al, $POST_ADDR ; \
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popl %eax
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/*
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* Overwrite the current_postcode low nibble.
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*/
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#define ASMPOSTCODE_LO(X) \
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pushl %eax ; \
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movl _current_postcode, %eax ; \
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andl $0xf0, %eax ; \
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orl $X, %eax ; \
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movl %eax, _current_postcode ; \
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outb %al, $POST_ADDR ; \
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popl %eax
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/*
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* Overwrite the current_postcode high nibble.
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*/
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#define ASMPOSTCODE_HI(X) \
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pushl %eax ; \
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movl _current_postcode, %eax ; \
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andl $0x0f, %eax ; \
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orl $(X<<4), %eax ; \
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movl %eax, _current_postcode ; \
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outb %al, $POST_ADDR ; \
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popl %eax
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#else
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#define ASMPOSTCODE_INC
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#define ASMPOSTCODE(X)
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#define ASMPOSTCODE_LO(X)
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#define ASMPOSTCODE_HI(X)
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#endif /* POST_ADDR */
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/*
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* These are all temps for debugging...
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*
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#define GUARD_INTS
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*/
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/*
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* This macro traps unexpected INTs to a specific CPU, eg. GUARD_CPU.
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*/
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#ifdef GUARD_INTS
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#define GUARD_CPU 1
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#define MAYBE_PANIC(irq_num) \
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cmpl $GUARD_CPU, _cpuid ; \
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jne 9f ; \
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cmpl $1, _ok_test1 ; \
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jne 9f ; \
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pushl lapic_isr3 ; \
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pushl lapic_isr2 ; \
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pushl lapic_isr1 ; \
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pushl lapic_isr0 ; \
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pushl lapic_irr3 ; \
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pushl lapic_irr2 ; \
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pushl lapic_irr1 ; \
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pushl lapic_irr0 ; \
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pushl $irq_num ; \
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pushl _cpuid ; \
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pushl $panic_msg ; \
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call _printf ; \
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addl $44, %esp ; \
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9:
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#else
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#define MAYBE_PANIC(irq_num)
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#endif /* GUARD_INTS */
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#endif /* _MACHINE_SMPTESTS_H_ */
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