619282986d
threads from compile-time defines to global variables. This removes a significant amount of duplicated runtime patches to the compile-time defines, centralizing the conditional logic in the early startup code. Reviewed by: jhibbits
103 lines
4.5 KiB
C
103 lines
4.5 KiB
C
/*-
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* SPDX-License-Identifier: BSD-4-Clause
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*
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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* Copyright (C) 1995, 1996 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $NetBSD: psl.h,v 1.5 2000/11/19 19:52:37 matt Exp $
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PSL_H_
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#define _MACHINE_PSL_H_
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/*
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* Machine State Register (MSR) - All cores
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*/
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#define PSL_VEC 0x02000000UL /* AltiVec/SPE vector unit available */
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#define PSL_VSX 0x00800000UL /* Vector-Scalar unit available */
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#define PSL_EE 0x00008000UL /* external interrupt enable */
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#define PSL_PR 0x00004000UL /* privilege mode (1 == user) */
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#define PSL_FP 0x00002000UL /* floating point enable */
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#define PSL_ME 0x00001000UL /* machine check enable */
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#define PSL_FE0 0x00000800UL /* floating point interrupt mode 0 */
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#define PSL_FE1 0x00000100UL /* floating point interrupt mode 1 */
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#define PSL_PMM 0x00000004UL /* performance monitor mark */
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#define PSL_RI 0x00000002UL /* recoverable interrupt */
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/* Machine State Register - Book-E cores */
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#ifdef __powerpc64__
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#define PSL_CM 0x80000000UL /* Computation Mode (64-bit) */
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#endif
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#define PSL_GS 0x10000000UL /* Guest state */
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#define PSL_UCLE 0x04000000UL /* User mode cache lock enable */
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#define PSL_WE 0x00040000UL /* Wait state enable */
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#define PSL_CE 0x00020000UL /* Critical interrupt enable */
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#define PSL_UBLE 0x00000400UL /* BTB lock enable - e500 only */
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#define PSL_DWE 0x00000400UL /* Debug Wait Enable - 440 only*/
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#define PSL_DE 0x00000200UL /* Debug interrupt enable */
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#define PSL_IS 0x00000020UL /* Instruction address space */
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#define PSL_DS 0x00000010UL /* Data address space */
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/* Machine State Register (MSR) - AIM cores */
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#ifdef __powerpc64__
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#define PSL_SF 0x8000000000000000UL /* 64-bit addressing */
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#define PSL_HV 0x1000000000000000UL /* hyper-privileged mode */
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#endif
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#define PSL_POW 0x00040000UL /* power management */
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#define PSL_ILE 0x00010000UL /* interrupt endian mode (1 == le) */
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#define PSL_SE 0x00000400UL /* single-step trace enable */
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#define PSL_BE 0x00000200UL /* branch trace enable */
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#define PSL_IP 0x00000040UL /* interrupt prefix - 601 only */
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#define PSL_IR 0x00000020UL /* instruction address relocation */
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#define PSL_DR 0x00000010UL /* data address relocation */
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#define PSL_LE 0x00000001UL /* endian mode (1 == le) */
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/*
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* Floating-point exception modes:
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*/
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#define PSL_FE_DIS 0 /* none */
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#define PSL_FE_NONREC PSL_FE1 /* imprecise non-recoverable */
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#define PSL_FE_REC PSL_FE0 /* imprecise recoverable */
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#define PSL_FE_PREC (PSL_FE0 | PSL_FE1) /* precise */
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#define PSL_FE_DFLT PSL_FE_DIS /* default == none */
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#ifndef LOCORE
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extern register_t psl_kernset; /* Default MSR values for kernel */
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extern register_t psl_userset; /* Default MSR values for userland */
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#ifdef __powerpc64__
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extern register_t psl_userset32; /* Default user MSR values for 32-bit */
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#endif
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extern register_t psl_userstatic; /* Bits of SRR1 userland may not set */
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#endif
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#endif /* _MACHINE_PSL_H_ */
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