1712 lines
44 KiB
C
1712 lines
44 KiB
C
/* $OpenBSD: trap.c,v 1.19 1998/09/30 12:40:41 pefo Exp $ */
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/* tracked to 1.23 */
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/*-
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 1988 University of Utah.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department and Ralph Campbell.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: Utah Hdr: trap.c 1.32 91/04/06
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*
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* from: @(#)trap.c 8.5 (Berkeley) 1/11/94
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* JNPR: trap.c,v 1.13.2.2 2007/08/29 10:03:49 girish
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ddb.h"
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#include "opt_ktrace.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/sysent.h>
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#include <sys/proc.h>
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#include <sys/kernel.h>
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#include <sys/signalvar.h>
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#include <sys/syscall.h>
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#include <sys/lock.h>
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#include <vm/vm.h>
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#include <vm/vm_extern.h>
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#include <vm/vm_kern.h>
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#include <vm/vm_page.h>
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#include <vm/vm_map.h>
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#include <vm/vm_param.h>
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#include <sys/vmmeter.h>
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#include <sys/ptrace.h>
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#include <sys/user.h>
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#include <sys/buf.h>
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#include <sys/vnode.h>
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#include <sys/pioctl.h>
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#include <sys/sysctl.h>
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#include <sys/syslog.h>
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#include <sys/bus.h>
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#ifdef KTRACE
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#include <sys/ktrace.h>
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#endif
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#include <net/netisr.h>
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#include <machine/trap.h>
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#include <machine/cpu.h>
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#include <machine/cpuinfo.h>
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#include <machine/pte.h>
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#include <machine/pmap.h>
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#include <machine/md_var.h>
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#include <machine/mips_opcode.h>
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#include <machine/frame.h>
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#include <machine/regnum.h>
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#include <machine/tls.h>
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#ifdef DDB
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#include <machine/db_machdep.h>
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#include <ddb/db_sym.h>
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#include <ddb/ddb.h>
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#include <sys/kdb.h>
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#endif
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#ifdef KDTRACE_HOOKS
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#include <sys/dtrace_bsd.h>
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#endif
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#ifdef TRAP_DEBUG
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int trap_debug = 0;
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SYSCTL_INT(_machdep, OID_AUTO, trap_debug, CTLFLAG_RW,
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&trap_debug, 0, "Debug information on all traps");
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#endif
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#define lbu_macro(data, addr) \
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__asm __volatile ("lbu %0, 0x0(%1)" \
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: "=r" (data) /* outputs */ \
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: "r" (addr)); /* inputs */
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#define lb_macro(data, addr) \
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__asm __volatile ("lb %0, 0x0(%1)" \
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: "=r" (data) /* outputs */ \
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: "r" (addr)); /* inputs */
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#define lwl_macro(data, addr) \
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__asm __volatile ("lwl %0, 0x0(%1)" \
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: "=r" (data) /* outputs */ \
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: "r" (addr)); /* inputs */
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#define lwr_macro(data, addr) \
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__asm __volatile ("lwr %0, 0x0(%1)" \
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: "=r" (data) /* outputs */ \
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: "r" (addr)); /* inputs */
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#define ldl_macro(data, addr) \
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__asm __volatile ("ldl %0, 0x0(%1)" \
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: "=r" (data) /* outputs */ \
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: "r" (addr)); /* inputs */
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#define ldr_macro(data, addr) \
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__asm __volatile ("ldr %0, 0x0(%1)" \
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: "=r" (data) /* outputs */ \
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: "r" (addr)); /* inputs */
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#define sb_macro(data, addr) \
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__asm __volatile ("sb %0, 0x0(%1)" \
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: /* outputs */ \
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: "r" (data), "r" (addr)); /* inputs */
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#define swl_macro(data, addr) \
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__asm __volatile ("swl %0, 0x0(%1)" \
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: /* outputs */ \
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: "r" (data), "r" (addr)); /* inputs */
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#define swr_macro(data, addr) \
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__asm __volatile ("swr %0, 0x0(%1)" \
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: /* outputs */ \
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: "r" (data), "r" (addr)); /* inputs */
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#define sdl_macro(data, addr) \
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__asm __volatile ("sdl %0, 0x0(%1)" \
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: /* outputs */ \
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: "r" (data), "r" (addr)); /* inputs */
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#define sdr_macro(data, addr) \
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__asm __volatile ("sdr %0, 0x0(%1)" \
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: /* outputs */ \
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: "r" (data), "r" (addr)); /* inputs */
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static void log_illegal_instruction(const char *, struct trapframe *);
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static void log_bad_page_fault(char *, struct trapframe *, int);
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static void log_frame_dump(struct trapframe *frame);
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static void get_mapping_info(vm_offset_t, pd_entry_t **, pt_entry_t **);
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int (*dtrace_invop_jump_addr)(struct trapframe *);
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#ifdef TRAP_DEBUG
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static void trap_frame_dump(struct trapframe *frame);
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#endif
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void (*machExceptionTable[]) (void)= {
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/*
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* The kernel exception handlers.
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*/
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MipsKernIntr, /* external interrupt */
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MipsKernGenException, /* TLB modification */
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MipsTLBInvalidException,/* TLB miss (load or instr. fetch) */
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MipsTLBInvalidException,/* TLB miss (store) */
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MipsKernGenException, /* address error (load or I-fetch) */
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MipsKernGenException, /* address error (store) */
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MipsKernGenException, /* bus error (I-fetch) */
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MipsKernGenException, /* bus error (load or store) */
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MipsKernGenException, /* system call */
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MipsKernGenException, /* breakpoint */
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MipsKernGenException, /* reserved instruction */
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MipsKernGenException, /* coprocessor unusable */
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MipsKernGenException, /* arithmetic overflow */
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MipsKernGenException, /* trap exception */
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MipsKernGenException, /* virtual coherence exception inst */
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MipsKernGenException, /* floating point exception */
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MipsKernGenException, /* reserved */
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MipsKernGenException, /* reserved */
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MipsKernGenException, /* reserved */
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MipsKernGenException, /* reserved */
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MipsKernGenException, /* reserved */
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MipsKernGenException, /* reserved */
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MipsKernGenException, /* reserved */
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MipsKernGenException, /* watch exception */
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MipsKernGenException, /* reserved */
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MipsKernGenException, /* reserved */
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MipsKernGenException, /* reserved */
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MipsKernGenException, /* reserved */
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MipsKernGenException, /* reserved */
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MipsKernGenException, /* reserved */
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MipsKernGenException, /* reserved */
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MipsKernGenException, /* virtual coherence exception data */
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/*
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* The user exception handlers.
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*/
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MipsUserIntr, /* 0 */
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MipsUserGenException, /* 1 */
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MipsTLBInvalidException,/* 2 */
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MipsTLBInvalidException,/* 3 */
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MipsUserGenException, /* 4 */
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MipsUserGenException, /* 5 */
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MipsUserGenException, /* 6 */
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MipsUserGenException, /* 7 */
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MipsUserGenException, /* 8 */
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MipsUserGenException, /* 9 */
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MipsUserGenException, /* 10 */
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MipsUserGenException, /* 11 */
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MipsUserGenException, /* 12 */
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MipsUserGenException, /* 13 */
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MipsUserGenException, /* 14 */
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MipsUserGenException, /* 15 */
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MipsUserGenException, /* 16 */
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MipsUserGenException, /* 17 */
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MipsUserGenException, /* 18 */
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MipsUserGenException, /* 19 */
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MipsUserGenException, /* 20 */
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MipsUserGenException, /* 21 */
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MipsUserGenException, /* 22 */
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MipsUserGenException, /* 23 */
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MipsUserGenException, /* 24 */
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MipsUserGenException, /* 25 */
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MipsUserGenException, /* 26 */
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MipsUserGenException, /* 27 */
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MipsUserGenException, /* 28 */
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MipsUserGenException, /* 29 */
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MipsUserGenException, /* 20 */
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MipsUserGenException, /* 31 */
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};
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char *trap_type[] = {
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"external interrupt",
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"TLB modification",
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"TLB miss (load or instr. fetch)",
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"TLB miss (store)",
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"address error (load or I-fetch)",
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"address error (store)",
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"bus error (I-fetch)",
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"bus error (load or store)",
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"system call",
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"breakpoint",
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"reserved instruction",
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"coprocessor unusable",
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"arithmetic overflow",
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"trap",
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"virtual coherency instruction",
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"floating point",
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"reserved 16",
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"reserved 17",
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"reserved 18",
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"reserved 19",
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"reserved 20",
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"reserved 21",
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"reserved 22",
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"watch",
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"reserved 24",
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"reserved 25",
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"reserved 26",
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"reserved 27",
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"reserved 28",
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"reserved 29",
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"reserved 30",
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"virtual coherency data",
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};
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#if !defined(SMP) && (defined(DDB) || defined(DEBUG))
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struct trapdebug trapdebug[TRAPSIZE], *trp = trapdebug;
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#endif
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#define KERNLAND(x) ((vm_offset_t)(x) >= VM_MIN_KERNEL_ADDRESS && (vm_offset_t)(x) < VM_MAX_KERNEL_ADDRESS)
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#define DELAYBRANCH(x) ((x) & MIPS_CR_BR_DELAY)
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/*
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* MIPS load/store access type
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*/
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enum {
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MIPS_LHU_ACCESS = 1,
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MIPS_LH_ACCESS,
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MIPS_LWU_ACCESS,
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MIPS_LW_ACCESS,
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MIPS_LD_ACCESS,
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MIPS_SH_ACCESS,
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MIPS_SW_ACCESS,
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MIPS_SD_ACCESS
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};
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char *access_name[] = {
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"Load Halfword Unsigned",
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"Load Halfword",
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"Load Word Unsigned",
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"Load Word",
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"Load Doubleword",
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"Store Halfword",
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"Store Word",
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"Store Doubleword"
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};
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#ifdef CPU_CNMIPS
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#include <machine/octeon_cop2.h>
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#endif
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static int allow_unaligned_acc = 1;
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SYSCTL_INT(_vm, OID_AUTO, allow_unaligned_acc, CTLFLAG_RW,
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&allow_unaligned_acc, 0, "Allow unaligned accesses");
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/*
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* FP emulation is assumed to work on O32, but the code is outdated and crufty
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* enough that it's a more sensible default to have it disabled when using
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* other ABIs. At the very least, it needs a lot of help in using
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* type-semantic ABI-oblivious macros for everything it does.
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*/
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#if defined(__mips_o32)
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static int emulate_fp = 1;
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#else
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static int emulate_fp = 0;
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#endif
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SYSCTL_INT(_machdep, OID_AUTO, emulate_fp, CTLFLAG_RW,
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&emulate_fp, 0, "Emulate unimplemented FPU instructions");
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static int emulate_unaligned_access(struct trapframe *frame, int mode);
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extern void fswintrberr(void); /* XXX */
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int
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cpu_fetch_syscall_args(struct thread *td)
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{
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struct trapframe *locr0;
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struct sysentvec *se;
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struct syscall_args *sa;
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int error, nsaved;
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locr0 = td->td_frame;
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sa = &td->td_sa;
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bzero(sa->args, sizeof(sa->args));
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/* compute next PC after syscall instruction */
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td->td_pcb->pcb_tpc = sa->trapframe->pc; /* Remember if restart */
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if (DELAYBRANCH(sa->trapframe->cause)) /* Check BD bit */
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locr0->pc = MipsEmulateBranch(locr0, sa->trapframe->pc, 0, 0);
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else
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locr0->pc += sizeof(int);
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sa->code = locr0->v0;
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switch (sa->code) {
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case SYS___syscall:
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case SYS_syscall:
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/*
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* This is an indirect syscall, in which the code is the first argument.
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*/
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#if (!defined(__mips_n32) && !defined(__mips_n64)) || defined(COMPAT_FREEBSD32)
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if (sa->code == SYS___syscall && SV_PROC_FLAG(td->td_proc, SV_ILP32)) {
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/*
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* Like syscall, but code is a quad, so as to maintain alignment
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* for the rest of the arguments.
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*/
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if (_QUAD_LOWWORD == 0)
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sa->code = locr0->a0;
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else
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sa->code = locr0->a1;
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sa->args[0] = locr0->a2;
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sa->args[1] = locr0->a3;
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nsaved = 2;
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break;
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}
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#endif
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/*
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* This is either not a quad syscall, or is a quad syscall with a
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* new ABI in which quads fit in a single register.
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*/
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sa->code = locr0->a0;
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sa->args[0] = locr0->a1;
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sa->args[1] = locr0->a2;
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sa->args[2] = locr0->a3;
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nsaved = 3;
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#if defined(__mips_n32) || defined(__mips_n64)
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#ifdef COMPAT_FREEBSD32
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if (!SV_PROC_FLAG(td->td_proc, SV_ILP32)) {
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#endif
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/*
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* Non-o32 ABIs support more arguments in registers.
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*/
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sa->args[3] = locr0->a4;
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sa->args[4] = locr0->a5;
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sa->args[5] = locr0->a6;
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sa->args[6] = locr0->a7;
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nsaved += 4;
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#ifdef COMPAT_FREEBSD32
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}
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#endif
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#endif
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break;
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default:
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/*
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* A direct syscall, arguments are just parameters to the syscall.
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*/
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sa->args[0] = locr0->a0;
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sa->args[1] = locr0->a1;
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sa->args[2] = locr0->a2;
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sa->args[3] = locr0->a3;
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nsaved = 4;
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#if defined (__mips_n32) || defined(__mips_n64)
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#ifdef COMPAT_FREEBSD32
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if (!SV_PROC_FLAG(td->td_proc, SV_ILP32)) {
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#endif
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/*
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* Non-o32 ABIs support more arguments in registers.
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*/
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sa->args[4] = locr0->a4;
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sa->args[5] = locr0->a5;
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sa->args[6] = locr0->a6;
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sa->args[7] = locr0->a7;
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nsaved += 4;
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#ifdef COMPAT_FREEBSD32
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}
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#endif
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#endif
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break;
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}
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#ifdef TRAP_DEBUG
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if (trap_debug)
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printf("SYSCALL #%d pid:%u\n", sa->code, td->td_proc->p_pid);
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#endif
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se = td->td_proc->p_sysent;
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/*
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* XXX
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* Shouldn't this go before switching on the code?
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*/
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if (sa->code >= se->sv_size)
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sa->callp = &se->sv_table[0];
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else
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sa->callp = &se->sv_table[sa->code];
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sa->narg = sa->callp->sy_narg;
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if (sa->narg > nsaved) {
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#if defined(__mips_n32) || defined(__mips_n64)
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/*
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* XXX
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* Is this right for new ABIs? I think the 4 there
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* should be 8, size there are 8 registers to skip,
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* not 4, but I'm not certain.
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*/
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#ifdef COMPAT_FREEBSD32
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if (!SV_PROC_FLAG(td->td_proc, SV_ILP32))
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#endif
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printf("SYSCALL #%u pid:%u, narg (%u) > nsaved (%u).\n",
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sa->code, td->td_proc->p_pid, sa->narg, nsaved);
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#endif
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#if (defined(__mips_n32) || defined(__mips_n64)) && defined(COMPAT_FREEBSD32)
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if (SV_PROC_FLAG(td->td_proc, SV_ILP32)) {
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unsigned i;
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int32_t arg;
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error = 0; /* XXX GCC is awful. */
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for (i = nsaved; i < sa->narg; i++) {
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error = copyin((caddr_t)(intptr_t)(locr0->sp +
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(4 + (i - nsaved)) * sizeof(int32_t)),
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(caddr_t)&arg, sizeof arg);
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if (error != 0)
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break;
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sa->args[i] = arg;
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}
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} else
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#endif
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error = copyin((caddr_t)(intptr_t)(locr0->sp +
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4 * sizeof(register_t)), (caddr_t)&sa->args[nsaved],
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(u_int)(sa->narg - nsaved) * sizeof(register_t));
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if (error != 0) {
|
|
locr0->v0 = error;
|
|
locr0->a3 = 1;
|
|
}
|
|
} else
|
|
error = 0;
|
|
|
|
if (error == 0) {
|
|
td->td_retval[0] = 0;
|
|
td->td_retval[1] = locr0->v1;
|
|
}
|
|
|
|
return (error);
|
|
}
|
|
|
|
#undef __FBSDID
|
|
#define __FBSDID(x)
|
|
#include "../../kern/subr_syscall.c"
|
|
|
|
/*
|
|
* Handle an exception.
|
|
* Called from MipsKernGenException() or MipsUserGenException()
|
|
* when a processor trap occurs.
|
|
* In the case of a kernel trap, we return the pc where to resume if
|
|
* p->p_addr->u_pcb.pcb_onfault is set, otherwise, return old pc.
|
|
*/
|
|
register_t
|
|
trap(struct trapframe *trapframe)
|
|
{
|
|
int type, usermode;
|
|
int i = 0;
|
|
unsigned ucode = 0;
|
|
struct thread *td = curthread;
|
|
struct proc *p = curproc;
|
|
vm_prot_t ftype;
|
|
pmap_t pmap;
|
|
int access_type;
|
|
ksiginfo_t ksi;
|
|
char *msg = NULL;
|
|
intptr_t addr = 0;
|
|
register_t pc;
|
|
int cop, error;
|
|
register_t *frame_regs;
|
|
|
|
trapdebug_enter(trapframe, 0);
|
|
#ifdef KDB
|
|
if (kdb_active) {
|
|
kdb_reenter();
|
|
return (0);
|
|
}
|
|
#endif
|
|
type = (trapframe->cause & MIPS_CR_EXC_CODE) >> MIPS_CR_EXC_CODE_SHIFT;
|
|
if (TRAPF_USERMODE(trapframe)) {
|
|
type |= T_USER;
|
|
usermode = 1;
|
|
} else {
|
|
usermode = 0;
|
|
}
|
|
|
|
/*
|
|
* Enable hardware interrupts if they were on before the trap. If it
|
|
* was off disable all so we don't accidently enable it when doing a
|
|
* return to userland.
|
|
*/
|
|
if (trapframe->sr & MIPS_SR_INT_IE) {
|
|
set_intr_mask(trapframe->sr & MIPS_SR_INT_MASK);
|
|
intr_enable();
|
|
} else {
|
|
intr_disable();
|
|
}
|
|
|
|
#ifdef TRAP_DEBUG
|
|
if (trap_debug) {
|
|
static vm_offset_t last_badvaddr = 0;
|
|
static vm_offset_t this_badvaddr = 0;
|
|
static int count = 0;
|
|
u_int32_t pid;
|
|
|
|
printf("trap type %x (%s - ", type,
|
|
trap_type[type & (~T_USER)]);
|
|
|
|
if (type & T_USER)
|
|
printf("user mode)\n");
|
|
else
|
|
printf("kernel mode)\n");
|
|
|
|
#ifdef SMP
|
|
printf("cpuid = %d\n", PCPU_GET(cpuid));
|
|
#endif
|
|
pid = mips_rd_entryhi() & TLBHI_ASID_MASK;
|
|
printf("badaddr = %#jx, pc = %#jx, ra = %#jx, sp = %#jx, sr = %jx, pid = %d, ASID = %u\n",
|
|
(intmax_t)trapframe->badvaddr, (intmax_t)trapframe->pc, (intmax_t)trapframe->ra,
|
|
(intmax_t)trapframe->sp, (intmax_t)trapframe->sr,
|
|
(curproc ? curproc->p_pid : -1), pid);
|
|
|
|
switch (type & ~T_USER) {
|
|
case T_TLB_MOD:
|
|
case T_TLB_LD_MISS:
|
|
case T_TLB_ST_MISS:
|
|
case T_ADDR_ERR_LD:
|
|
case T_ADDR_ERR_ST:
|
|
this_badvaddr = trapframe->badvaddr;
|
|
break;
|
|
case T_SYSCALL:
|
|
this_badvaddr = trapframe->ra;
|
|
break;
|
|
default:
|
|
this_badvaddr = trapframe->pc;
|
|
break;
|
|
}
|
|
if ((last_badvaddr == this_badvaddr) &&
|
|
((type & ~T_USER) != T_SYSCALL) &&
|
|
((type & ~T_USER) != T_COP_UNUSABLE)) {
|
|
if (++count == 3) {
|
|
trap_frame_dump(trapframe);
|
|
panic("too many faults at %p\n", (void *)last_badvaddr);
|
|
}
|
|
} else {
|
|
last_badvaddr = this_badvaddr;
|
|
count = 0;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#ifdef KDTRACE_HOOKS
|
|
/*
|
|
* A trap can occur while DTrace executes a probe. Before
|
|
* executing the probe, DTrace blocks re-scheduling and sets
|
|
* a flag in its per-cpu flags to indicate that it doesn't
|
|
* want to fault. On returning from the probe, the no-fault
|
|
* flag is cleared and finally re-scheduling is enabled.
|
|
*
|
|
* If the DTrace kernel module has registered a trap handler,
|
|
* call it and if it returns non-zero, assume that it has
|
|
* handled the trap and modified the trap frame so that this
|
|
* function can return normally.
|
|
*/
|
|
/*
|
|
* XXXDTRACE: add pid probe handler here (if ever)
|
|
*/
|
|
if (!usermode) {
|
|
if (dtrace_trap_func != NULL &&
|
|
(*dtrace_trap_func)(trapframe, type) != 0)
|
|
return (trapframe->pc);
|
|
}
|
|
#endif
|
|
|
|
switch (type) {
|
|
case T_MCHECK:
|
|
#ifdef DDB
|
|
kdb_trap(type, 0, trapframe);
|
|
#endif
|
|
panic("MCHECK\n");
|
|
break;
|
|
case T_TLB_MOD:
|
|
/* check for kernel address */
|
|
if (KERNLAND(trapframe->badvaddr)) {
|
|
if (pmap_emulate_modified(kernel_pmap,
|
|
trapframe->badvaddr) != 0) {
|
|
ftype = VM_PROT_WRITE;
|
|
goto kernel_fault;
|
|
}
|
|
return (trapframe->pc);
|
|
}
|
|
/* FALLTHROUGH */
|
|
|
|
case T_TLB_MOD + T_USER:
|
|
pmap = &p->p_vmspace->vm_pmap;
|
|
if (pmap_emulate_modified(pmap, trapframe->badvaddr) != 0) {
|
|
ftype = VM_PROT_WRITE;
|
|
goto dofault;
|
|
}
|
|
if (!usermode)
|
|
return (trapframe->pc);
|
|
goto out;
|
|
|
|
case T_TLB_LD_MISS:
|
|
case T_TLB_ST_MISS:
|
|
ftype = (type == T_TLB_ST_MISS) ? VM_PROT_WRITE : VM_PROT_READ;
|
|
/* check for kernel address */
|
|
if (KERNLAND(trapframe->badvaddr)) {
|
|
vm_offset_t va;
|
|
int rv;
|
|
|
|
kernel_fault:
|
|
va = trunc_page((vm_offset_t)trapframe->badvaddr);
|
|
rv = vm_fault(kernel_map, va, ftype, VM_FAULT_NORMAL);
|
|
if (rv == KERN_SUCCESS)
|
|
return (trapframe->pc);
|
|
if (td->td_pcb->pcb_onfault != NULL) {
|
|
pc = (register_t)(intptr_t)td->td_pcb->pcb_onfault;
|
|
td->td_pcb->pcb_onfault = NULL;
|
|
return (pc);
|
|
}
|
|
goto err;
|
|
}
|
|
|
|
/*
|
|
* It is an error for the kernel to access user space except
|
|
* through the copyin/copyout routines.
|
|
*/
|
|
if (td->td_pcb->pcb_onfault == NULL)
|
|
goto err;
|
|
|
|
goto dofault;
|
|
|
|
case T_TLB_LD_MISS + T_USER:
|
|
ftype = VM_PROT_READ;
|
|
goto dofault;
|
|
|
|
case T_TLB_ST_MISS + T_USER:
|
|
ftype = VM_PROT_WRITE;
|
|
dofault:
|
|
{
|
|
vm_offset_t va;
|
|
struct vmspace *vm;
|
|
vm_map_t map;
|
|
int rv = 0;
|
|
|
|
vm = p->p_vmspace;
|
|
map = &vm->vm_map;
|
|
va = trunc_page((vm_offset_t)trapframe->badvaddr);
|
|
if (KERNLAND(trapframe->badvaddr)) {
|
|
/*
|
|
* Don't allow user-mode faults in kernel
|
|
* address space.
|
|
*/
|
|
goto nogo;
|
|
}
|
|
|
|
rv = vm_fault(map, va, ftype, VM_FAULT_NORMAL);
|
|
/*
|
|
* XXXDTRACE: add dtrace_doubletrap_func here?
|
|
*/
|
|
#ifdef VMFAULT_TRACE
|
|
printf("vm_fault(%p (pmap %p), %p (%p), %x, %d) -> %x at pc %p\n",
|
|
map, &vm->vm_pmap, (void *)va, (void *)(intptr_t)trapframe->badvaddr,
|
|
ftype, VM_FAULT_NORMAL, rv, (void *)(intptr_t)trapframe->pc);
|
|
#endif
|
|
|
|
if (rv == KERN_SUCCESS) {
|
|
if (!usermode) {
|
|
return (trapframe->pc);
|
|
}
|
|
goto out;
|
|
}
|
|
nogo:
|
|
if (!usermode) {
|
|
if (td->td_pcb->pcb_onfault != NULL) {
|
|
pc = (register_t)(intptr_t)td->td_pcb->pcb_onfault;
|
|
td->td_pcb->pcb_onfault = NULL;
|
|
return (pc);
|
|
}
|
|
goto err;
|
|
}
|
|
i = SIGSEGV;
|
|
if (rv == KERN_PROTECTION_FAILURE)
|
|
ucode = SEGV_ACCERR;
|
|
else
|
|
ucode = SEGV_MAPERR;
|
|
addr = trapframe->pc;
|
|
|
|
msg = "BAD_PAGE_FAULT";
|
|
log_bad_page_fault(msg, trapframe, type);
|
|
|
|
break;
|
|
}
|
|
|
|
case T_ADDR_ERR_LD + T_USER: /* misaligned or kseg access */
|
|
case T_ADDR_ERR_ST + T_USER: /* misaligned or kseg access */
|
|
if (trapframe->badvaddr < 0 ||
|
|
trapframe->badvaddr >= VM_MAXUSER_ADDRESS) {
|
|
msg = "ADDRESS_SPACE_ERR";
|
|
} else if (allow_unaligned_acc) {
|
|
int mode;
|
|
|
|
if (type == (T_ADDR_ERR_LD + T_USER))
|
|
mode = VM_PROT_READ;
|
|
else
|
|
mode = VM_PROT_WRITE;
|
|
|
|
access_type = emulate_unaligned_access(trapframe, mode);
|
|
if (access_type != 0)
|
|
goto out;
|
|
msg = "ALIGNMENT_FIX_ERR";
|
|
} else {
|
|
msg = "ADDRESS_ERR";
|
|
}
|
|
|
|
/* FALL THROUGH */
|
|
|
|
case T_BUS_ERR_IFETCH + T_USER: /* BERR asserted to cpu */
|
|
case T_BUS_ERR_LD_ST + T_USER: /* BERR asserted to cpu */
|
|
ucode = 0; /* XXX should be VM_PROT_something */
|
|
i = SIGBUS;
|
|
addr = trapframe->pc;
|
|
if (!msg)
|
|
msg = "BUS_ERR";
|
|
log_bad_page_fault(msg, trapframe, type);
|
|
break;
|
|
|
|
case T_SYSCALL + T_USER:
|
|
{
|
|
int error;
|
|
|
|
td->td_sa.trapframe = trapframe;
|
|
error = syscallenter(td);
|
|
|
|
#if !defined(SMP) && (defined(DDB) || defined(DEBUG))
|
|
if (trp == trapdebug)
|
|
trapdebug[TRAPSIZE - 1].code = td->td_sa.code;
|
|
else
|
|
trp[-1].code = td->td_sa.code;
|
|
#endif
|
|
trapdebug_enter(td->td_frame, -td->td_sa.code);
|
|
|
|
/*
|
|
* The sync'ing of I & D caches for SYS_ptrace() is
|
|
* done by procfs_domem() through procfs_rwmem()
|
|
* instead of being done here under a special check
|
|
* for SYS_ptrace().
|
|
*/
|
|
syscallret(td, error);
|
|
return (trapframe->pc);
|
|
}
|
|
|
|
#if defined(KDTRACE_HOOKS) || defined(DDB)
|
|
case T_BREAK:
|
|
#ifdef KDTRACE_HOOKS
|
|
if (!usermode && dtrace_invop_jump_addr != 0) {
|
|
dtrace_invop_jump_addr(trapframe);
|
|
return (trapframe->pc);
|
|
}
|
|
#endif
|
|
#ifdef DDB
|
|
kdb_trap(type, 0, trapframe);
|
|
return (trapframe->pc);
|
|
#endif
|
|
#endif
|
|
|
|
case T_BREAK + T_USER:
|
|
{
|
|
intptr_t va;
|
|
uint32_t instr;
|
|
|
|
i = SIGTRAP;
|
|
ucode = TRAP_BRKPT;
|
|
addr = trapframe->pc;
|
|
|
|
/* compute address of break instruction */
|
|
va = trapframe->pc;
|
|
if (DELAYBRANCH(trapframe->cause))
|
|
va += sizeof(int);
|
|
|
|
if (td->td_md.md_ss_addr != va)
|
|
break;
|
|
|
|
/* read break instruction */
|
|
instr = fuword32((caddr_t)va);
|
|
|
|
if (instr != MIPS_BREAK_SSTEP)
|
|
break;
|
|
|
|
CTR3(KTR_PTRACE,
|
|
"trap: tid %d, single step at %#lx: %#08x",
|
|
td->td_tid, va, instr);
|
|
PROC_LOCK(p);
|
|
_PHOLD(p);
|
|
error = ptrace_clear_single_step(td);
|
|
_PRELE(p);
|
|
PROC_UNLOCK(p);
|
|
if (error == 0)
|
|
ucode = TRAP_TRACE;
|
|
break;
|
|
}
|
|
|
|
case T_IWATCH + T_USER:
|
|
case T_DWATCH + T_USER:
|
|
{
|
|
intptr_t va;
|
|
|
|
/* compute address of trapped instruction */
|
|
va = trapframe->pc;
|
|
if (DELAYBRANCH(trapframe->cause))
|
|
va += sizeof(int);
|
|
printf("watch exception @ %p\n", (void *)va);
|
|
i = SIGTRAP;
|
|
ucode = TRAP_BRKPT;
|
|
addr = va;
|
|
break;
|
|
}
|
|
|
|
case T_TRAP + T_USER:
|
|
{
|
|
intptr_t va;
|
|
struct trapframe *locr0 = td->td_frame;
|
|
|
|
/* compute address of trap instruction */
|
|
va = trapframe->pc;
|
|
if (DELAYBRANCH(trapframe->cause))
|
|
va += sizeof(int);
|
|
|
|
if (DELAYBRANCH(trapframe->cause)) { /* Check BD bit */
|
|
locr0->pc = MipsEmulateBranch(locr0, trapframe->pc, 0,
|
|
0);
|
|
} else {
|
|
locr0->pc += sizeof(int);
|
|
}
|
|
addr = va;
|
|
i = SIGEMT; /* Stuff it with something for now */
|
|
break;
|
|
}
|
|
|
|
case T_RES_INST + T_USER:
|
|
{
|
|
InstFmt inst;
|
|
inst = *(InstFmt *)(intptr_t)trapframe->pc;
|
|
switch (inst.RType.op) {
|
|
case OP_SPECIAL3:
|
|
switch (inst.RType.func) {
|
|
case OP_RDHWR:
|
|
/* Register 29 used for TLS */
|
|
if (inst.RType.rd == 29) {
|
|
frame_regs = &(trapframe->zero);
|
|
frame_regs[inst.RType.rt] = (register_t)(intptr_t)td->td_md.md_tls;
|
|
frame_regs[inst.RType.rt] += td->td_md.md_tls_tcb_offset;
|
|
trapframe->pc += sizeof(int);
|
|
goto out;
|
|
}
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
log_illegal_instruction("RES_INST", trapframe);
|
|
i = SIGILL;
|
|
addr = trapframe->pc;
|
|
}
|
|
break;
|
|
case T_C2E:
|
|
case T_C2E + T_USER:
|
|
goto err;
|
|
break;
|
|
case T_COP_UNUSABLE:
|
|
#ifdef CPU_CNMIPS
|
|
cop = (trapframe->cause & MIPS_CR_COP_ERR) >> MIPS_CR_COP_ERR_SHIFT;
|
|
/* Handle only COP2 exception */
|
|
if (cop != 2)
|
|
goto err;
|
|
|
|
addr = trapframe->pc;
|
|
/* save userland cop2 context if it has been touched */
|
|
if ((td->td_md.md_flags & MDTD_COP2USED) &&
|
|
(td->td_md.md_cop2owner == COP2_OWNER_USERLAND)) {
|
|
if (td->td_md.md_ucop2)
|
|
octeon_cop2_save(td->td_md.md_ucop2);
|
|
else
|
|
panic("COP2 was used in user mode but md_ucop2 is NULL");
|
|
}
|
|
|
|
if (td->td_md.md_cop2 == NULL) {
|
|
td->td_md.md_cop2 = octeon_cop2_alloc_ctx();
|
|
if (td->td_md.md_cop2 == NULL)
|
|
panic("Failed to allocate COP2 context");
|
|
memset(td->td_md.md_cop2, 0, sizeof(*td->td_md.md_cop2));
|
|
}
|
|
|
|
octeon_cop2_restore(td->td_md.md_cop2);
|
|
|
|
/* Make userland re-request its context */
|
|
td->td_frame->sr &= ~MIPS_SR_COP_2_BIT;
|
|
td->td_md.md_flags |= MDTD_COP2USED;
|
|
td->td_md.md_cop2owner = COP2_OWNER_KERNEL;
|
|
/* Enable COP2, it will be disabled in cpu_switch */
|
|
mips_wr_status(mips_rd_status() | MIPS_SR_COP_2_BIT);
|
|
return (trapframe->pc);
|
|
#else
|
|
goto err;
|
|
break;
|
|
#endif
|
|
|
|
case T_COP_UNUSABLE + T_USER:
|
|
cop = (trapframe->cause & MIPS_CR_COP_ERR) >> MIPS_CR_COP_ERR_SHIFT;
|
|
if (cop == 1) {
|
|
/* FP (COP1) instruction */
|
|
if (cpuinfo.fpu_id == 0) {
|
|
log_illegal_instruction("COP1_UNUSABLE",
|
|
trapframe);
|
|
i = SIGILL;
|
|
break;
|
|
}
|
|
addr = trapframe->pc;
|
|
MipsSwitchFPState(PCPU_GET(fpcurthread), td->td_frame);
|
|
PCPU_SET(fpcurthread, td);
|
|
#if defined(__mips_n32) || defined(__mips_n64)
|
|
td->td_frame->sr |= MIPS_SR_COP_1_BIT | MIPS_SR_FR;
|
|
#else
|
|
td->td_frame->sr |= MIPS_SR_COP_1_BIT;
|
|
#endif
|
|
td->td_md.md_flags |= MDTD_FPUSED;
|
|
goto out;
|
|
}
|
|
#ifdef CPU_CNMIPS
|
|
else if (cop == 2) {
|
|
addr = trapframe->pc;
|
|
if ((td->td_md.md_flags & MDTD_COP2USED) &&
|
|
(td->td_md.md_cop2owner == COP2_OWNER_KERNEL)) {
|
|
if (td->td_md.md_cop2)
|
|
octeon_cop2_save(td->td_md.md_cop2);
|
|
else
|
|
panic("COP2 was used in kernel mode but md_cop2 is NULL");
|
|
}
|
|
|
|
if (td->td_md.md_ucop2 == NULL) {
|
|
td->td_md.md_ucop2 = octeon_cop2_alloc_ctx();
|
|
if (td->td_md.md_ucop2 == NULL)
|
|
panic("Failed to allocate userland COP2 context");
|
|
memset(td->td_md.md_ucop2, 0, sizeof(*td->td_md.md_ucop2));
|
|
}
|
|
|
|
octeon_cop2_restore(td->td_md.md_ucop2);
|
|
|
|
td->td_frame->sr |= MIPS_SR_COP_2_BIT;
|
|
td->td_md.md_flags |= MDTD_COP2USED;
|
|
td->td_md.md_cop2owner = COP2_OWNER_USERLAND;
|
|
goto out;
|
|
}
|
|
#endif
|
|
else {
|
|
log_illegal_instruction("COPn_UNUSABLE", trapframe);
|
|
i = SIGILL; /* only FPU instructions allowed */
|
|
break;
|
|
}
|
|
|
|
case T_FPE:
|
|
#if !defined(SMP) && (defined(DDB) || defined(DEBUG))
|
|
trapDump("fpintr");
|
|
#else
|
|
printf("FPU Trap: PC %#jx CR %x SR %x\n",
|
|
(intmax_t)trapframe->pc, (unsigned)trapframe->cause, (unsigned)trapframe->sr);
|
|
goto err;
|
|
#endif
|
|
|
|
case T_FPE + T_USER:
|
|
if (!emulate_fp) {
|
|
i = SIGFPE;
|
|
addr = trapframe->pc;
|
|
break;
|
|
}
|
|
MipsFPTrap(trapframe->sr, trapframe->cause, trapframe->pc);
|
|
goto out;
|
|
|
|
case T_OVFLOW + T_USER:
|
|
i = SIGFPE;
|
|
addr = trapframe->pc;
|
|
break;
|
|
|
|
case T_ADDR_ERR_LD: /* misaligned access */
|
|
case T_ADDR_ERR_ST: /* misaligned access */
|
|
#ifdef TRAP_DEBUG
|
|
if (trap_debug) {
|
|
printf("+++ ADDR_ERR: type = %d, badvaddr = %#jx\n", type,
|
|
(intmax_t)trapframe->badvaddr);
|
|
}
|
|
#endif
|
|
/* Only allow emulation on a user address */
|
|
if (allow_unaligned_acc &&
|
|
((vm_offset_t)trapframe->badvaddr < VM_MAXUSER_ADDRESS)) {
|
|
int mode;
|
|
|
|
if (type == T_ADDR_ERR_LD)
|
|
mode = VM_PROT_READ;
|
|
else
|
|
mode = VM_PROT_WRITE;
|
|
|
|
access_type = emulate_unaligned_access(trapframe, mode);
|
|
if (access_type != 0)
|
|
return (trapframe->pc);
|
|
}
|
|
/* FALLTHROUGH */
|
|
|
|
case T_BUS_ERR_LD_ST: /* BERR asserted to cpu */
|
|
if (td->td_pcb->pcb_onfault != NULL) {
|
|
pc = (register_t)(intptr_t)td->td_pcb->pcb_onfault;
|
|
td->td_pcb->pcb_onfault = NULL;
|
|
return (pc);
|
|
}
|
|
|
|
/* FALLTHROUGH */
|
|
|
|
default:
|
|
err:
|
|
|
|
#if !defined(SMP) && defined(DEBUG)
|
|
trapDump("trap");
|
|
#endif
|
|
#ifdef SMP
|
|
printf("cpu:%d-", PCPU_GET(cpuid));
|
|
#endif
|
|
printf("Trap cause = %d (%s - ", type,
|
|
trap_type[type & (~T_USER)]);
|
|
|
|
if (type & T_USER)
|
|
printf("user mode)\n");
|
|
else
|
|
printf("kernel mode)\n");
|
|
|
|
#ifdef TRAP_DEBUG
|
|
if (trap_debug)
|
|
printf("badvaddr = %#jx, pc = %#jx, ra = %#jx, sr = %#jxx\n",
|
|
(intmax_t)trapframe->badvaddr, (intmax_t)trapframe->pc, (intmax_t)trapframe->ra,
|
|
(intmax_t)trapframe->sr);
|
|
#endif
|
|
|
|
#ifdef KDB
|
|
if (debugger_on_trap) {
|
|
kdb_why = KDB_WHY_TRAP;
|
|
kdb_trap(type, 0, trapframe);
|
|
kdb_why = KDB_WHY_UNSET;
|
|
}
|
|
#endif
|
|
panic("trap");
|
|
}
|
|
td->td_frame->pc = trapframe->pc;
|
|
td->td_frame->cause = trapframe->cause;
|
|
td->td_frame->badvaddr = trapframe->badvaddr;
|
|
ksiginfo_init_trap(&ksi);
|
|
ksi.ksi_signo = i;
|
|
ksi.ksi_code = ucode;
|
|
ksi.ksi_addr = (void *)addr;
|
|
ksi.ksi_trapno = type;
|
|
trapsignal(td, &ksi);
|
|
out:
|
|
|
|
/*
|
|
* Note: we should only get here if returning to user mode.
|
|
*/
|
|
userret(td, trapframe);
|
|
return (trapframe->pc);
|
|
}
|
|
|
|
#if !defined(SMP) && (defined(DDB) || defined(DEBUG))
|
|
void
|
|
trapDump(char *msg)
|
|
{
|
|
register_t s;
|
|
int i;
|
|
|
|
s = intr_disable();
|
|
printf("trapDump(%s)\n", msg);
|
|
for (i = 0; i < TRAPSIZE; i++) {
|
|
if (trp == trapdebug) {
|
|
trp = &trapdebug[TRAPSIZE - 1];
|
|
} else {
|
|
trp--;
|
|
}
|
|
|
|
if (trp->cause == 0)
|
|
break;
|
|
|
|
printf("%s: ADR %jx PC %jx CR %jx SR %jx\n",
|
|
trap_type[(trp->cause & MIPS_CR_EXC_CODE) >>
|
|
MIPS_CR_EXC_CODE_SHIFT],
|
|
(intmax_t)trp->vadr, (intmax_t)trp->pc,
|
|
(intmax_t)trp->cause, (intmax_t)trp->status);
|
|
|
|
printf(" RA %jx SP %jx code %d\n", (intmax_t)trp->ra,
|
|
(intmax_t)trp->sp, (int)trp->code);
|
|
}
|
|
intr_restore(s);
|
|
}
|
|
#endif
|
|
|
|
|
|
/*
|
|
* Return the resulting PC as if the branch was executed.
|
|
*/
|
|
uintptr_t
|
|
MipsEmulateBranch(struct trapframe *framePtr, uintptr_t instPC, int fpcCSR,
|
|
uintptr_t instptr)
|
|
{
|
|
InstFmt inst;
|
|
register_t *regsPtr = (register_t *) framePtr;
|
|
uintptr_t retAddr = 0;
|
|
int condition;
|
|
|
|
#define GetBranchDest(InstPtr, inst) \
|
|
(InstPtr + 4 + ((short)inst.IType.imm << 2))
|
|
|
|
|
|
if (instptr) {
|
|
if (instptr < MIPS_KSEG0_START)
|
|
inst.word = fuword32((void *)instptr);
|
|
else
|
|
inst = *(InstFmt *) instptr;
|
|
} else {
|
|
if ((vm_offset_t)instPC < MIPS_KSEG0_START)
|
|
inst.word = fuword32((void *)instPC);
|
|
else
|
|
inst = *(InstFmt *) instPC;
|
|
}
|
|
|
|
switch ((int)inst.JType.op) {
|
|
case OP_SPECIAL:
|
|
switch ((int)inst.RType.func) {
|
|
case OP_JR:
|
|
case OP_JALR:
|
|
retAddr = regsPtr[inst.RType.rs];
|
|
break;
|
|
|
|
default:
|
|
retAddr = instPC + 4;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case OP_BCOND:
|
|
switch ((int)inst.IType.rt) {
|
|
case OP_BLTZ:
|
|
case OP_BLTZL:
|
|
case OP_BLTZAL:
|
|
case OP_BLTZALL:
|
|
if ((int)(regsPtr[inst.RType.rs]) < 0)
|
|
retAddr = GetBranchDest(instPC, inst);
|
|
else
|
|
retAddr = instPC + 8;
|
|
break;
|
|
|
|
case OP_BGEZ:
|
|
case OP_BGEZL:
|
|
case OP_BGEZAL:
|
|
case OP_BGEZALL:
|
|
if ((int)(regsPtr[inst.RType.rs]) >= 0)
|
|
retAddr = GetBranchDest(instPC, inst);
|
|
else
|
|
retAddr = instPC + 8;
|
|
break;
|
|
|
|
case OP_TGEI:
|
|
case OP_TGEIU:
|
|
case OP_TLTI:
|
|
case OP_TLTIU:
|
|
case OP_TEQI:
|
|
case OP_TNEI:
|
|
retAddr = instPC + 4; /* Like syscall... */
|
|
break;
|
|
|
|
default:
|
|
panic("MipsEmulateBranch: Bad branch cond");
|
|
}
|
|
break;
|
|
|
|
case OP_J:
|
|
case OP_JAL:
|
|
retAddr = (inst.JType.target << 2) |
|
|
((unsigned)(instPC + 4) & 0xF0000000);
|
|
break;
|
|
|
|
case OP_BEQ:
|
|
case OP_BEQL:
|
|
if (regsPtr[inst.RType.rs] == regsPtr[inst.RType.rt])
|
|
retAddr = GetBranchDest(instPC, inst);
|
|
else
|
|
retAddr = instPC + 8;
|
|
break;
|
|
|
|
case OP_BNE:
|
|
case OP_BNEL:
|
|
if (regsPtr[inst.RType.rs] != regsPtr[inst.RType.rt])
|
|
retAddr = GetBranchDest(instPC, inst);
|
|
else
|
|
retAddr = instPC + 8;
|
|
break;
|
|
|
|
case OP_BLEZ:
|
|
case OP_BLEZL:
|
|
if ((int)(regsPtr[inst.RType.rs]) <= 0)
|
|
retAddr = GetBranchDest(instPC, inst);
|
|
else
|
|
retAddr = instPC + 8;
|
|
break;
|
|
|
|
case OP_BGTZ:
|
|
case OP_BGTZL:
|
|
if ((int)(regsPtr[inst.RType.rs]) > 0)
|
|
retAddr = GetBranchDest(instPC, inst);
|
|
else
|
|
retAddr = instPC + 8;
|
|
break;
|
|
|
|
case OP_COP1:
|
|
switch (inst.RType.rs) {
|
|
case OP_BCx:
|
|
case OP_BCy:
|
|
if ((inst.RType.rt & COPz_BC_TF_MASK) == COPz_BC_TRUE)
|
|
condition = fpcCSR & MIPS_FPU_COND_BIT;
|
|
else
|
|
condition = !(fpcCSR & MIPS_FPU_COND_BIT);
|
|
if (condition)
|
|
retAddr = GetBranchDest(instPC, inst);
|
|
else
|
|
retAddr = instPC + 8;
|
|
break;
|
|
|
|
default:
|
|
retAddr = instPC + 4;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
retAddr = instPC + 4;
|
|
}
|
|
return (retAddr);
|
|
}
|
|
|
|
static void
|
|
log_frame_dump(struct trapframe *frame)
|
|
{
|
|
log(LOG_ERR, "Trapframe Register Dump:\n");
|
|
log(LOG_ERR, "\tzero: %#jx\tat: %#jx\tv0: %#jx\tv1: %#jx\n",
|
|
(intmax_t)0, (intmax_t)frame->ast, (intmax_t)frame->v0, (intmax_t)frame->v1);
|
|
|
|
log(LOG_ERR, "\ta0: %#jx\ta1: %#jx\ta2: %#jx\ta3: %#jx\n",
|
|
(intmax_t)frame->a0, (intmax_t)frame->a1, (intmax_t)frame->a2, (intmax_t)frame->a3);
|
|
|
|
#if defined(__mips_n32) || defined(__mips_n64)
|
|
log(LOG_ERR, "\ta4: %#jx\ta5: %#jx\ta6: %#jx\ta6: %#jx\n",
|
|
(intmax_t)frame->a4, (intmax_t)frame->a5, (intmax_t)frame->a6, (intmax_t)frame->a7);
|
|
|
|
log(LOG_ERR, "\tt0: %#jx\tt1: %#jx\tt2: %#jx\tt3: %#jx\n",
|
|
(intmax_t)frame->t0, (intmax_t)frame->t1, (intmax_t)frame->t2, (intmax_t)frame->t3);
|
|
#else
|
|
log(LOG_ERR, "\tt0: %#jx\tt1: %#jx\tt2: %#jx\tt3: %#jx\n",
|
|
(intmax_t)frame->t0, (intmax_t)frame->t1, (intmax_t)frame->t2, (intmax_t)frame->t3);
|
|
|
|
log(LOG_ERR, "\tt4: %#jx\tt5: %#jx\tt6: %#jx\tt7: %#jx\n",
|
|
(intmax_t)frame->t4, (intmax_t)frame->t5, (intmax_t)frame->t6, (intmax_t)frame->t7);
|
|
#endif
|
|
log(LOG_ERR, "\tt8: %#jx\tt9: %#jx\ts0: %#jx\ts1: %#jx\n",
|
|
(intmax_t)frame->t8, (intmax_t)frame->t9, (intmax_t)frame->s0, (intmax_t)frame->s1);
|
|
|
|
log(LOG_ERR, "\ts2: %#jx\ts3: %#jx\ts4: %#jx\ts5: %#jx\n",
|
|
(intmax_t)frame->s2, (intmax_t)frame->s3, (intmax_t)frame->s4, (intmax_t)frame->s5);
|
|
|
|
log(LOG_ERR, "\ts6: %#jx\ts7: %#jx\tk0: %#jx\tk1: %#jx\n",
|
|
(intmax_t)frame->s6, (intmax_t)frame->s7, (intmax_t)frame->k0, (intmax_t)frame->k1);
|
|
|
|
log(LOG_ERR, "\tgp: %#jx\tsp: %#jx\ts8: %#jx\tra: %#jx\n",
|
|
(intmax_t)frame->gp, (intmax_t)frame->sp, (intmax_t)frame->s8, (intmax_t)frame->ra);
|
|
|
|
log(LOG_ERR, "\tsr: %#jx\tmullo: %#jx\tmulhi: %#jx\tbadvaddr: %#jx\n",
|
|
(intmax_t)frame->sr, (intmax_t)frame->mullo, (intmax_t)frame->mulhi, (intmax_t)frame->badvaddr);
|
|
|
|
log(LOG_ERR, "\tcause: %#jx\tpc: %#jx\n",
|
|
(intmax_t)frame->cause, (intmax_t)frame->pc);
|
|
}
|
|
|
|
#ifdef TRAP_DEBUG
|
|
static void
|
|
trap_frame_dump(struct trapframe *frame)
|
|
{
|
|
printf("Trapframe Register Dump:\n");
|
|
printf("\tzero: %#jx\tat: %#jx\tv0: %#jx\tv1: %#jx\n",
|
|
(intmax_t)0, (intmax_t)frame->ast, (intmax_t)frame->v0, (intmax_t)frame->v1);
|
|
|
|
printf("\ta0: %#jx\ta1: %#jx\ta2: %#jx\ta3: %#jx\n",
|
|
(intmax_t)frame->a0, (intmax_t)frame->a1, (intmax_t)frame->a2, (intmax_t)frame->a3);
|
|
#if defined(__mips_n32) || defined(__mips_n64)
|
|
printf("\ta4: %#jx\ta5: %#jx\ta6: %#jx\ta7: %#jx\n",
|
|
(intmax_t)frame->a4, (intmax_t)frame->a5, (intmax_t)frame->a6, (intmax_t)frame->a7);
|
|
|
|
printf("\tt0: %#jx\tt1: %#jx\tt2: %#jx\tt3: %#jx\n",
|
|
(intmax_t)frame->t0, (intmax_t)frame->t1, (intmax_t)frame->t2, (intmax_t)frame->t3);
|
|
#else
|
|
printf("\tt0: %#jx\tt1: %#jx\tt2: %#jx\tt3: %#jx\n",
|
|
(intmax_t)frame->t0, (intmax_t)frame->t1, (intmax_t)frame->t2, (intmax_t)frame->t3);
|
|
|
|
printf("\tt4: %#jx\tt5: %#jx\tt6: %#jx\tt7: %#jx\n",
|
|
(intmax_t)frame->t4, (intmax_t)frame->t5, (intmax_t)frame->t6, (intmax_t)frame->t7);
|
|
#endif
|
|
printf("\tt8: %#jx\tt9: %#jx\ts0: %#jx\ts1: %#jx\n",
|
|
(intmax_t)frame->t8, (intmax_t)frame->t9, (intmax_t)frame->s0, (intmax_t)frame->s1);
|
|
|
|
printf("\ts2: %#jx\ts3: %#jx\ts4: %#jx\ts5: %#jx\n",
|
|
(intmax_t)frame->s2, (intmax_t)frame->s3, (intmax_t)frame->s4, (intmax_t)frame->s5);
|
|
|
|
printf("\ts6: %#jx\ts7: %#jx\tk0: %#jx\tk1: %#jx\n",
|
|
(intmax_t)frame->s6, (intmax_t)frame->s7, (intmax_t)frame->k0, (intmax_t)frame->k1);
|
|
|
|
printf("\tgp: %#jx\tsp: %#jx\ts8: %#jx\tra: %#jx\n",
|
|
(intmax_t)frame->gp, (intmax_t)frame->sp, (intmax_t)frame->s8, (intmax_t)frame->ra);
|
|
|
|
printf("\tsr: %#jx\tmullo: %#jx\tmulhi: %#jx\tbadvaddr: %#jx\n",
|
|
(intmax_t)frame->sr, (intmax_t)frame->mullo, (intmax_t)frame->mulhi, (intmax_t)frame->badvaddr);
|
|
|
|
printf("\tcause: %#jx\tpc: %#jx\n",
|
|
(intmax_t)frame->cause, (intmax_t)frame->pc);
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
static void
|
|
get_mapping_info(vm_offset_t va, pd_entry_t **pdepp, pt_entry_t **ptepp)
|
|
{
|
|
pt_entry_t *ptep;
|
|
pd_entry_t *pdep;
|
|
struct proc *p = curproc;
|
|
|
|
pdep = (&(p->p_vmspace->vm_pmap.pm_segtab[(va >> SEGSHIFT) & (NPDEPG - 1)]));
|
|
if (*pdep)
|
|
ptep = pmap_pte(&p->p_vmspace->vm_pmap, va);
|
|
else
|
|
ptep = (pt_entry_t *)0;
|
|
|
|
*pdepp = pdep;
|
|
*ptepp = ptep;
|
|
}
|
|
|
|
static void
|
|
log_illegal_instruction(const char *msg, struct trapframe *frame)
|
|
{
|
|
pt_entry_t *ptep;
|
|
pd_entry_t *pdep;
|
|
unsigned int *addr;
|
|
struct thread *td;
|
|
struct proc *p;
|
|
register_t pc;
|
|
|
|
td = curthread;
|
|
p = td->td_proc;
|
|
|
|
#ifdef SMP
|
|
printf("cpuid = %d\n", PCPU_GET(cpuid));
|
|
#endif
|
|
pc = frame->pc + (DELAYBRANCH(frame->cause) ? 4 : 0);
|
|
log(LOG_ERR, "%s: pid %d tid %ld (%s), uid %d: pc %#jx ra %#jx\n",
|
|
msg, p->p_pid, (long)td->td_tid, p->p_comm,
|
|
p->p_ucred ? p->p_ucred->cr_uid : -1,
|
|
(intmax_t)pc,
|
|
(intmax_t)frame->ra);
|
|
|
|
/* log registers in trap frame */
|
|
log_frame_dump(frame);
|
|
|
|
get_mapping_info((vm_offset_t)pc, &pdep, &ptep);
|
|
|
|
/*
|
|
* Dump a few words around faulting instruction, if the addres is
|
|
* valid.
|
|
*/
|
|
if (!(pc & 3) &&
|
|
useracc((caddr_t)(intptr_t)pc, sizeof(int) * 4, VM_PROT_READ)) {
|
|
/* dump page table entry for faulting instruction */
|
|
log(LOG_ERR, "Page table info for pc address %#jx: pde = %p, pte = %#jx\n",
|
|
(intmax_t)pc, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
|
|
|
|
addr = (unsigned int *)(intptr_t)pc;
|
|
log(LOG_ERR, "Dumping 4 words starting at pc address %p: \n",
|
|
addr);
|
|
log(LOG_ERR, "%08x %08x %08x %08x\n",
|
|
addr[0], addr[1], addr[2], addr[3]);
|
|
} else {
|
|
log(LOG_ERR, "pc address %#jx is inaccessible, pde = %p, pte = %#jx\n",
|
|
(intmax_t)pc, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
|
|
}
|
|
}
|
|
|
|
static void
|
|
log_bad_page_fault(char *msg, struct trapframe *frame, int trap_type)
|
|
{
|
|
pt_entry_t *ptep;
|
|
pd_entry_t *pdep;
|
|
unsigned int *addr;
|
|
struct thread *td;
|
|
struct proc *p;
|
|
char *read_or_write;
|
|
register_t pc;
|
|
|
|
trap_type &= ~T_USER;
|
|
|
|
td = curthread;
|
|
p = td->td_proc;
|
|
|
|
#ifdef SMP
|
|
printf("cpuid = %d\n", PCPU_GET(cpuid));
|
|
#endif
|
|
switch (trap_type) {
|
|
case T_TLB_MOD:
|
|
case T_TLB_ST_MISS:
|
|
case T_ADDR_ERR_ST:
|
|
read_or_write = "write";
|
|
break;
|
|
case T_TLB_LD_MISS:
|
|
case T_ADDR_ERR_LD:
|
|
case T_BUS_ERR_IFETCH:
|
|
read_or_write = "read";
|
|
break;
|
|
default:
|
|
read_or_write = "unknown";
|
|
}
|
|
|
|
pc = frame->pc + (DELAYBRANCH(frame->cause) ? 4 : 0);
|
|
log(LOG_ERR, "%s: pid %d tid %ld (%s), uid %d: pc %#jx got a %s fault "
|
|
"(type %#x) at %#jx\n",
|
|
msg, p->p_pid, (long)td->td_tid, p->p_comm,
|
|
p->p_ucred ? p->p_ucred->cr_uid : -1,
|
|
(intmax_t)pc,
|
|
read_or_write,
|
|
trap_type,
|
|
(intmax_t)frame->badvaddr);
|
|
|
|
/* log registers in trap frame */
|
|
log_frame_dump(frame);
|
|
|
|
get_mapping_info((vm_offset_t)pc, &pdep, &ptep);
|
|
|
|
/*
|
|
* Dump a few words around faulting instruction, if the addres is
|
|
* valid.
|
|
*/
|
|
if (!(pc & 3) && (pc != frame->badvaddr) &&
|
|
(trap_type != T_BUS_ERR_IFETCH) &&
|
|
useracc((caddr_t)(intptr_t)pc, sizeof(int) * 4, VM_PROT_READ)) {
|
|
/* dump page table entry for faulting instruction */
|
|
log(LOG_ERR, "Page table info for pc address %#jx: pde = %p, pte = %#jx\n",
|
|
(intmax_t)pc, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
|
|
|
|
addr = (unsigned int *)(intptr_t)pc;
|
|
log(LOG_ERR, "Dumping 4 words starting at pc address %p: \n",
|
|
addr);
|
|
log(LOG_ERR, "%08x %08x %08x %08x\n",
|
|
addr[0], addr[1], addr[2], addr[3]);
|
|
} else {
|
|
log(LOG_ERR, "pc address %#jx is inaccessible, pde = %p, pte = %#jx\n",
|
|
(intmax_t)pc, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
|
|
}
|
|
|
|
get_mapping_info((vm_offset_t)frame->badvaddr, &pdep, &ptep);
|
|
log(LOG_ERR, "Page table info for bad address %#jx: pde = %p, pte = %#jx\n",
|
|
(intmax_t)frame->badvaddr, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
|
|
}
|
|
|
|
|
|
/*
|
|
* Unaligned load/store emulation
|
|
*/
|
|
static int
|
|
mips_unaligned_load_store(struct trapframe *frame, int mode, register_t addr, register_t pc)
|
|
{
|
|
register_t *reg = (register_t *) frame;
|
|
u_int32_t inst = *((u_int32_t *)(intptr_t)pc);
|
|
register_t value_msb, value;
|
|
unsigned size;
|
|
|
|
/*
|
|
* ADDR_ERR faults have higher priority than TLB
|
|
* Miss faults. Therefore, it is necessary to
|
|
* verify that the faulting address is a valid
|
|
* virtual address within the process' address space
|
|
* before trying to emulate the unaligned access.
|
|
*/
|
|
switch (MIPS_INST_OPCODE(inst)) {
|
|
case OP_LHU: case OP_LH:
|
|
case OP_SH:
|
|
size = 2;
|
|
break;
|
|
case OP_LWU: case OP_LW:
|
|
case OP_SW:
|
|
size = 4;
|
|
break;
|
|
case OP_LD:
|
|
case OP_SD:
|
|
size = 8;
|
|
break;
|
|
default:
|
|
printf("%s: unhandled opcode in address error: %#x\n", __func__, MIPS_INST_OPCODE(inst));
|
|
return (0);
|
|
}
|
|
|
|
if (!useracc((void *)rounddown2((vm_offset_t)addr, size), size * 2, mode))
|
|
return (0);
|
|
|
|
/*
|
|
* XXX
|
|
* Handle LL/SC LLD/SCD.
|
|
*/
|
|
switch (MIPS_INST_OPCODE(inst)) {
|
|
case OP_LHU:
|
|
KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
|
|
lbu_macro(value_msb, addr);
|
|
addr += 1;
|
|
lbu_macro(value, addr);
|
|
value |= value_msb << 8;
|
|
reg[MIPS_INST_RT(inst)] = value;
|
|
return (MIPS_LHU_ACCESS);
|
|
|
|
case OP_LH:
|
|
KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
|
|
lb_macro(value_msb, addr);
|
|
addr += 1;
|
|
lbu_macro(value, addr);
|
|
value |= value_msb << 8;
|
|
reg[MIPS_INST_RT(inst)] = value;
|
|
return (MIPS_LH_ACCESS);
|
|
|
|
case OP_LWU:
|
|
KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
|
|
lwl_macro(value, addr);
|
|
addr += 3;
|
|
lwr_macro(value, addr);
|
|
value &= 0xffffffff;
|
|
reg[MIPS_INST_RT(inst)] = value;
|
|
return (MIPS_LWU_ACCESS);
|
|
|
|
case OP_LW:
|
|
KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
|
|
lwl_macro(value, addr);
|
|
addr += 3;
|
|
lwr_macro(value, addr);
|
|
reg[MIPS_INST_RT(inst)] = value;
|
|
return (MIPS_LW_ACCESS);
|
|
|
|
#if defined(__mips_n32) || defined(__mips_n64)
|
|
case OP_LD:
|
|
KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
|
|
ldl_macro(value, addr);
|
|
addr += 7;
|
|
ldr_macro(value, addr);
|
|
reg[MIPS_INST_RT(inst)] = value;
|
|
return (MIPS_LD_ACCESS);
|
|
#endif
|
|
|
|
case OP_SH:
|
|
KASSERT(mode == VM_PROT_WRITE, ("access mode must be write for store instruction."));
|
|
value = reg[MIPS_INST_RT(inst)];
|
|
value_msb = value >> 8;
|
|
sb_macro(value_msb, addr);
|
|
addr += 1;
|
|
sb_macro(value, addr);
|
|
return (MIPS_SH_ACCESS);
|
|
|
|
case OP_SW:
|
|
KASSERT(mode == VM_PROT_WRITE, ("access mode must be write for store instruction."));
|
|
value = reg[MIPS_INST_RT(inst)];
|
|
swl_macro(value, addr);
|
|
addr += 3;
|
|
swr_macro(value, addr);
|
|
return (MIPS_SW_ACCESS);
|
|
|
|
#if defined(__mips_n32) || defined(__mips_n64)
|
|
case OP_SD:
|
|
KASSERT(mode == VM_PROT_WRITE, ("access mode must be write for store instruction."));
|
|
value = reg[MIPS_INST_RT(inst)];
|
|
sdl_macro(value, addr);
|
|
addr += 7;
|
|
sdr_macro(value, addr);
|
|
return (MIPS_SD_ACCESS);
|
|
#endif
|
|
}
|
|
panic("%s: should not be reached.", __func__);
|
|
}
|
|
|
|
|
|
/*
|
|
* XXX TODO: SMP?
|
|
*/
|
|
static struct timeval unaligned_lasterr;
|
|
static int unaligned_curerr;
|
|
|
|
static int unaligned_pps_log_limit = 4;
|
|
|
|
SYSCTL_INT(_machdep, OID_AUTO, unaligned_log_pps_limit, CTLFLAG_RWTUN,
|
|
&unaligned_pps_log_limit, 0,
|
|
"limit number of userland unaligned log messages per second");
|
|
|
|
static int
|
|
emulate_unaligned_access(struct trapframe *frame, int mode)
|
|
{
|
|
register_t pc;
|
|
int access_type = 0;
|
|
struct thread *td = curthread;
|
|
struct proc *p = curproc;
|
|
|
|
pc = frame->pc + (DELAYBRANCH(frame->cause) ? 4 : 0);
|
|
|
|
/*
|
|
* Fall through if it's instruction fetch exception
|
|
*/
|
|
if (!((pc & 3) || (pc == frame->badvaddr))) {
|
|
|
|
/*
|
|
* Handle unaligned load and store
|
|
*/
|
|
|
|
/*
|
|
* Return access type if the instruction was emulated.
|
|
* Otherwise restore pc and fall through.
|
|
*/
|
|
access_type = mips_unaligned_load_store(frame,
|
|
mode, frame->badvaddr, pc);
|
|
|
|
if (access_type) {
|
|
if (DELAYBRANCH(frame->cause))
|
|
frame->pc = MipsEmulateBranch(frame, frame->pc,
|
|
0, 0);
|
|
else
|
|
frame->pc += 4;
|
|
|
|
if (ppsratecheck(&unaligned_lasterr,
|
|
&unaligned_curerr, unaligned_pps_log_limit)) {
|
|
/* XXX TODO: keep global/tid/pid counters? */
|
|
log(LOG_INFO,
|
|
"Unaligned %s: pid=%ld (%s), tid=%ld, "
|
|
"pc=%#jx, badvaddr=%#jx\n",
|
|
access_name[access_type - 1],
|
|
(long) p->p_pid,
|
|
p->p_comm,
|
|
(long) td->td_tid,
|
|
(intmax_t)pc,
|
|
(intmax_t)frame->badvaddr);
|
|
}
|
|
}
|
|
}
|
|
return access_type;
|
|
}
|