402 lines
9.1 KiB
ArmAsm
402 lines
9.1 KiB
ArmAsm
/*-
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* Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
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* All rights reserved.
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*
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* Developed by Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of MARVELL nor the names of contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <machine/asm.h>
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__FBSDID("$FreeBSD$");
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#include <machine/param.h>
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.Lsheeva_cache_line_size:
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.word _C_LABEL(arm_pdcache_line_size)
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.Lsheeva_asm_page_mask:
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.word _C_LABEL(PAGE_MASK)
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ENTRY(sheeva_setttb)
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/* Disable irqs */
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mrs r2, cpsr
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orr r3, r2, #I32_bit | F32_bit
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msr cpsr_c, r3
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mov r1, #0
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mcr p15, 0, r1, c7, c5, 0 /* Invalidate ICache */
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1: mrc p15, 0, r15, c7, c14, 3 /* Test, clean and invalidate DCache */
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bne 1b /* More to do? */
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mcr p15, 1, r1, c15, c9, 0 /* Clean L2 */
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mcr p15, 1, r1, c15, c11, 0 /* Invalidate L2 */
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/* Reenable irqs */
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msr cpsr_c, r2
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mcr p15, 0, r1, c7, c10, 4 /* drain the write buffer */
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mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
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mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
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RET
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ENTRY(sheeva_dcache_wbinv_range)
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str lr, [sp, #-4]!
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mrs lr, cpsr
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/* Start with cache line aligned address */
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ldr ip, .Lsheeva_cache_line_size
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ldr ip, [ip]
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sub ip, ip, #1
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and r2, r0, ip
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add r1, r1, r2
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add r1, r1, ip
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bics r1, r1, ip
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bics r0, r0, ip
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ldr ip, .Lsheeva_asm_page_mask
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and r2, r0, ip
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rsb r2, r2, #PAGE_SIZE
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cmp r1, r2
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movcc ip, r1
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movcs ip, r2
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1:
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add r3, r0, ip
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sub r2, r3, #1
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/* Disable irqs */
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orr r3, lr, #I32_bit | F32_bit
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msr cpsr_c, r3
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mcr p15, 5, r0, c15, c15, 0 /* Clean and inv zone start address */
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mcr p15, 5, r2, c15, c15, 1 /* Clean and inv zone end address */
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/* Enable irqs */
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msr cpsr_c, lr
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add r0, r0, ip
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sub r1, r1, ip
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cmp r1, #PAGE_SIZE
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movcc ip, r1
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movcs ip, #PAGE_SIZE
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cmp r1, #0
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bne 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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ldr lr, [sp], #4
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RET
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ENTRY(sheeva_idcache_wbinv_range)
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str lr, [sp, #-4]!
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mrs lr, cpsr
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/* Start with cache line aligned address */
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ldr ip, .Lsheeva_cache_line_size
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ldr ip, [ip]
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sub ip, ip, #1
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and r2, r0, ip
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add r1, r1, r2
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add r1, r1, ip
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bics r1, r1, ip
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bics r0, r0, ip
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ldr ip, .Lsheeva_asm_page_mask
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and r2, r0, ip
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rsb r2, r2, #PAGE_SIZE
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cmp r1, r2
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movcc ip, r1
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movcs ip, r2
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1:
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add r3, r0, ip
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sub r2, r3, #1
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/* Disable irqs */
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orr r3, lr, #I32_bit | F32_bit
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msr cpsr_c, r3
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mcr p15, 5, r0, c15, c15, 0 /* Clean and inv zone start address */
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mcr p15, 5, r2, c15, c15, 1 /* Clean and inv zone end address */
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/* Enable irqs */
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msr cpsr_c, lr
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/* Invalidate and clean icache line by line */
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ldr r3, .Lsheeva_cache_line_size
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ldr r3, [r3]
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2:
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mcr p15, 0, r0, c7, c5, 1
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add r0, r0, r3
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cmp r2, r0
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bhi 2b
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add r0, r2, #1
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sub r1, r1, ip
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cmp r1, #PAGE_SIZE
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movcc ip, r1
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movcs ip, #PAGE_SIZE
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cmp r1, #0
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bne 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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ldr lr, [sp], #4
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RET
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ENTRY(sheeva_dcache_inv_range)
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str lr, [sp, #-4]!
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mrs lr, cpsr
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/* Start with cache line aligned address */
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ldr ip, .Lsheeva_cache_line_size
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ldr ip, [ip]
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sub ip, ip, #1
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and r2, r0, ip
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add r1, r1, r2
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add r1, r1, ip
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bics r1, r1, ip
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bics r0, r0, ip
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ldr ip, .Lsheeva_asm_page_mask
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and r2, r0, ip
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rsb r2, r2, #PAGE_SIZE
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cmp r1, r2
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movcc ip, r1
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movcs ip, r2
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1:
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add r3, r0, ip
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sub r2, r3, #1
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/* Disable irqs */
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orr r3, lr, #I32_bit | F32_bit
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msr cpsr_c, r3
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mcr p15, 5, r0, c15, c14, 0 /* Inv zone start address */
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mcr p15, 5, r2, c15, c14, 1 /* Inv zone end address */
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/* Enable irqs */
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msr cpsr_c, lr
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add r0, r0, ip
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sub r1, r1, ip
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cmp r1, #PAGE_SIZE
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movcc ip, r1
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movcs ip, #PAGE_SIZE
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cmp r1, #0
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bne 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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ldr lr, [sp], #4
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RET
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ENTRY(sheeva_dcache_wb_range)
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str lr, [sp, #-4]!
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mrs lr, cpsr
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/* Start with cache line aligned address */
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ldr ip, .Lsheeva_cache_line_size
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ldr ip, [ip]
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sub ip, ip, #1
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and r2, r0, ip
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add r1, r1, r2
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add r1, r1, ip
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bics r1, r1, ip
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bics r0, r0, ip
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ldr ip, .Lsheeva_asm_page_mask
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and r2, r0, ip
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rsb r2, r2, #PAGE_SIZE
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cmp r1, r2
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movcc ip, r1
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movcs ip, r2
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1:
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add r3, r0, ip
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sub r2, r3, #1
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/* Disable irqs */
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orr r3, lr, #I32_bit | F32_bit
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msr cpsr_c, r3
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mcr p15, 5, r0, c15, c13, 0 /* Clean zone start address */
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mcr p15, 5, r2, c15, c13, 1 /* Clean zone end address */
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/* Enable irqs */
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msr cpsr_c, lr
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add r0, r0, ip
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sub r1, r1, ip
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cmp r1, #PAGE_SIZE
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movcc ip, r1
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movcs ip, #PAGE_SIZE
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cmp r1, #0
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bne 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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ldr lr, [sp], #4
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RET
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ENTRY(sheeva_l2cache_wbinv_range)
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str lr, [sp, #-4]!
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mrs lr, cpsr
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/* Start with cache line aligned address */
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ldr ip, .Lsheeva_cache_line_size
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ldr ip, [ip]
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sub ip, ip, #1
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and r2, r0, ip
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add r1, r1, r2
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add r1, r1, ip
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bics r1, r1, ip
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bics r0, r0, ip
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ldr ip, .Lsheeva_asm_page_mask
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and r2, r0, ip
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rsb r2, r2, #PAGE_SIZE
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cmp r1, r2
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movcc ip, r1
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movcs ip, r2
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1:
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add r3, r0, ip
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sub r2, r3, #1
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/* Disable irqs */
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orr r3, lr, #I32_bit | F32_bit
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msr cpsr_c, r3
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mcr p15, 1, r0, c15, c9, 4 /* Clean L2 zone start address */
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mcr p15, 1, r2, c15, c9, 5 /* Clean L2 zone end address */
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mcr p15, 1, r0, c15, c11, 4 /* Inv L2 zone start address */
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mcr p15, 1, r2, c15, c11, 5 /* Inv L2 zone end address */
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/* Enable irqs */
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msr cpsr_c, lr
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add r0, r0, ip
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sub r1, r1, ip
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cmp r1, #PAGE_SIZE
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movcc ip, r1
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movcs ip, #PAGE_SIZE
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cmp r1, #0
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bne 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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ldr lr, [sp], #4
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RET
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ENTRY(sheeva_l2cache_inv_range)
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str lr, [sp, #-4]!
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mrs lr, cpsr
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/* Start with cache line aligned address */
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ldr ip, .Lsheeva_cache_line_size
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ldr ip, [ip]
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sub ip, ip, #1
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and r2, r0, ip
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add r1, r1, r2
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add r1, r1, ip
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bics r1, r1, ip
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bics r0, r0, ip
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ldr ip, .Lsheeva_asm_page_mask
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and r2, r0, ip
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rsb r2, r2, #PAGE_SIZE
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cmp r1, r2
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movcc ip, r1
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movcs ip, r2
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1:
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add r3, r0, ip
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sub r2, r3, #1
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/* Disable irqs */
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orr r3, lr, #I32_bit | F32_bit
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msr cpsr_c, r3
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mcr p15, 1, r0, c15, c11, 4 /* Inv L2 zone start address */
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mcr p15, 1, r2, c15, c11, 5 /* Inv L2 zone end address */
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/* Enable irqs */
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msr cpsr_c, lr
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add r0, r0, ip
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sub r1, r1, ip
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cmp r1, #PAGE_SIZE
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movcc ip, r1
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movcs ip, #PAGE_SIZE
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cmp r1, #0
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bne 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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ldr lr, [sp], #4
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RET
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ENTRY(sheeva_l2cache_wb_range)
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str lr, [sp, #-4]!
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mrs lr, cpsr
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/* Start with cache line aligned address */
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ldr ip, .Lsheeva_cache_line_size
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ldr ip, [ip]
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sub ip, ip, #1
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and r2, r0, ip
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add r1, r1, r2
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add r1, r1, ip
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bics r1, r1, ip
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bics r0, r0, ip
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ldr ip, .Lsheeva_asm_page_mask
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and r2, r0, ip
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rsb r2, r2, #PAGE_SIZE
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cmp r1, r2
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movcc ip, r1
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movcs ip, r2
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1:
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add r3, r0, ip
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sub r2, r3, #1
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/* Disable irqs */
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orr r3, lr, #I32_bit | F32_bit
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msr cpsr_c, r3
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mcr p15, 1, r0, c15, c9, 4 /* Clean L2 zone start address */
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mcr p15, 1, r2, c15, c9, 5 /* Clean L2 zone end address */
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/* Enable irqs */
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msr cpsr_c, lr
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add r0, r0, ip
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sub r1, r1, ip
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cmp r1, #PAGE_SIZE
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movcc ip, r1
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movcs ip, #PAGE_SIZE
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cmp r1, #0
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bne 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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ldr lr, [sp], #4
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RET
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ENTRY(sheeva_l2cache_wbinv_all)
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mov r0, #0
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mcr p15, 1, r0, c15, c9, 0 /* Clean L2 */
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mcr p15, 1, r0, c15, c11, 0 /* Invalidate L2 */
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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/* This function modifies register value as follows:
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*
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* arg1 arg EFFECT (bit value saved into register)
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* 0 0 not changed
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* 0 1 negated
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* 1 0 cleared
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* 1 1 set
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*/
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ENTRY(sheeva_control_ext)
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mrc p15, 1, r3, c15, c1, 0 /* Read the control register */
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bic r2, r3, r0 /* Clear bits */
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eor r2, r2, r1 /* XOR bits */
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teq r2, r3 /* Only write if there is a change */
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mcrne p15, 1, r2, c15, c1, 0 /* Write new control register */
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mov r0, r3 /* Return old value */
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RET
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ENTRY(sheeva_cpu_sleep)
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
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mcr p15, 0, r0, c7, c0, 4 /* Wait for interrupt */
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mov pc, lr
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