c37904e8ba
and start teaching subsystems about it. The Atheros MIPS platforms don't guarantee any kind of FIFO consistency with interrupts in hardware. So software needs to do a flush when it receives an interrupt and before it calls the interrupt handler. There are new ones for the QCA934x and QCA955x, so do a few things: * Get rid of the individual ones (for ethernet and IP2); * Create a mux and enum listing all the variations on DDR flushes; * replace the uses of IP2 with the relevant one (which will typically be "PCI" here); * call the USB DDR flush before calling the real USB interrupt handlers; * call the ethernet one upon receiving an interrupt that's for us, rather than never calling it during operation. Tested: * QCA9558 (TP-Link archer c7 v2) * AR9331 (Carambola 2) TODO: * PCI, USB, ethernet, etc need to do a double-check to see if the interrupt was truely for them before doing the DDR. For now I prefer "correct" over "fast".
277 lines
7.3 KiB
C
277 lines
7.3 KiB
C
/*-
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* Copyright (c) 2008 Sam Leffler. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* AR71XX attachment driver for the USB Enhanced Host Controller.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_bus.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/condvar.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <dev/usb/usb.h>
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#include <dev/usb/usbdi.h>
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#include <dev/usb/usb_core.h>
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#include <dev/usb/usb_busdma.h>
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#include <dev/usb/usb_process.h>
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#include <dev/usb/usb_util.h>
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#include <dev/usb/usb_controller.h>
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#include <dev/usb/usb_bus.h>
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#include <dev/usb/controller/ehci.h>
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#include <dev/usb/controller/ehcireg.h>
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#include <mips/atheros/ar71xx_setup.h>
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#include <mips/atheros/ar71xxreg.h> /* for stuff in ar71xx_cpudef.h */
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#include <mips/atheros/ar71xx_cpudef.h>
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#include <mips/atheros/ar71xx_bus_space_reversed.h>
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#define EHCI_HC_DEVSTR "AR71XX Integrated USB 2.0 controller"
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struct ar71xx_ehci_softc {
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ehci_softc_t base; /* storage for EHCI code */
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};
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static device_attach_t ar71xx_ehci_attach;
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static device_detach_t ar71xx_ehci_detach;
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bs_r_1_proto(reversed);
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bs_w_1_proto(reversed);
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static int
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ar71xx_ehci_probe(device_t self)
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{
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device_set_desc(self, EHCI_HC_DEVSTR);
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return (BUS_PROBE_NOWILDCARD);
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}
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static void
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ar71xx_ehci_intr(void *arg)
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{
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/* XXX TODO: should really see if this was our interrupt.. */
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ar71xx_device_flush_ddr(AR71XX_CPU_DDR_FLUSH_USB);
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ehci_interrupt(arg);
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}
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static int
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ar71xx_ehci_attach(device_t self)
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{
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struct ar71xx_ehci_softc *isc = device_get_softc(self);
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ehci_softc_t *sc = &isc->base;
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int err;
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int rid;
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/* initialise some bus fields */
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sc->sc_bus.parent = self;
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sc->sc_bus.devices = sc->sc_devices;
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sc->sc_bus.devices_max = EHCI_MAX_DEVICES;
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sc->sc_bus.dma_bits = 32;
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/* get all DMA memory */
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if (usb_bus_mem_alloc_all(&sc->sc_bus,
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USB_GET_DMA_TAG(self), &ehci_iterate_hw_softc)) {
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return (ENOMEM);
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}
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sc->sc_bus.usbrev = USB_REV_2_0;
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/* NB: hints fix the memory location and irq */
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rid = 0;
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sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
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if (!sc->sc_io_res) {
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device_printf(self, "Could not map memory\n");
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goto error;
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}
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/*
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* Craft special resource for bus space ops that handle
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* byte-alignment of non-word addresses.
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*/
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sc->sc_io_tag = ar71xx_bus_space_reversed;
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sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
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sc->sc_io_size = rman_get_size(sc->sc_io_res);
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rid = 0;
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sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
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RF_ACTIVE | RF_SHAREABLE);
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if (sc->sc_irq_res == NULL) {
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device_printf(self, "Could not allocate irq\n");
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goto error;
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}
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sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
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if (!sc->sc_bus.bdev) {
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device_printf(self, "Could not add USB device\n");
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goto error;
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}
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device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
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device_set_desc(sc->sc_bus.bdev, EHCI_HC_DEVSTR);
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sprintf(sc->sc_vendor, "Atheros");
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err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
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NULL, ar71xx_ehci_intr, sc, &sc->sc_intr_hdl);
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if (err) {
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device_printf(self, "Could not setup irq, %d\n", err);
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sc->sc_intr_hdl = NULL;
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goto error;
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}
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/*
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* Arrange to force Host mode, select big-endian byte alignment,
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* and arrange to not terminate reset operations (the adapter
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* will ignore it if we do but might as well save a reg write).
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* Also, the controller has an embedded Transaction Translator
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* which means port speed must be read from the Port Status
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* register following a port enable.
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*/
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sc->sc_flags = EHCI_SCFLG_SETMODE;
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switch (ar71xx_soc) {
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case AR71XX_SOC_AR7241:
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case AR71XX_SOC_AR7242:
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case AR71XX_SOC_AR9130:
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case AR71XX_SOC_AR9132:
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case AR71XX_SOC_AR9330:
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case AR71XX_SOC_AR9331:
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case AR71XX_SOC_AR9341:
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case AR71XX_SOC_AR9342:
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case AR71XX_SOC_AR9344:
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case AR71XX_SOC_QCA9556:
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case AR71XX_SOC_QCA9558:
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sc->sc_flags |= EHCI_SCFLG_TT | EHCI_SCFLG_NORESTERM;
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break;
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default:
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/* fallthrough */
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break;
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}
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/*
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* ehci_reset() needs the correct offset to access the host controller
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* registers. The AR724x/AR913x offsets aren't 0.
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*/
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sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
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(void) ehci_reset(sc);
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err = ehci_init(sc);
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if (!err) {
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err = device_probe_and_attach(sc->sc_bus.bdev);
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}
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if (err) {
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device_printf(self, "USB init failed err=%d\n", err);
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goto error;
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}
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return (0);
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error:
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ar71xx_ehci_detach(self);
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return (ENXIO);
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}
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static int
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ar71xx_ehci_detach(device_t self)
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{
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struct ar71xx_ehci_softc *isc = device_get_softc(self);
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ehci_softc_t *sc = &isc->base;
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device_t bdev;
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int err;
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if (sc->sc_bus.bdev) {
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bdev = sc->sc_bus.bdev;
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device_detach(bdev);
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device_delete_child(self, bdev);
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}
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/* during module unload there are lots of children leftover */
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device_delete_children(self);
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if (sc->sc_irq_res && sc->sc_intr_hdl) {
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/*
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* only call ehci_detach() after ehci_init()
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*/
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ehci_detach(sc);
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err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
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if (err)
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/* XXX or should we panic? */
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device_printf(self, "Could not tear down irq, %d\n",
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err);
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sc->sc_intr_hdl = NULL;
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}
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if (sc->sc_irq_res) {
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bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res);
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sc->sc_irq_res = NULL;
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}
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if (sc->sc_io_res) {
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bus_release_resource(self, SYS_RES_MEMORY, 0,
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sc->sc_io_res);
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sc->sc_io_res = NULL;
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}
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usb_bus_mem_free_all(&sc->sc_bus, &ehci_iterate_hw_softc);
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return (0);
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}
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static device_method_t ehci_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, ar71xx_ehci_probe),
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DEVMETHOD(device_attach, ar71xx_ehci_attach),
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DEVMETHOD(device_detach, ar71xx_ehci_detach),
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DEVMETHOD(device_suspend, bus_generic_suspend),
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DEVMETHOD(device_resume, bus_generic_resume),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD_END
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};
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static driver_t ehci_driver = {
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.name = "ehci",
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.methods = ehci_methods,
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.size = sizeof(struct ar71xx_ehci_softc),
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};
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static devclass_t ehci_devclass;
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DRIVER_MODULE(ehci, nexus, ehci_driver, ehci_devclass, 0, 0);
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DRIVER_MODULE(ehci, apb, ehci_driver, ehci_devclass, 0, 0);
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MODULE_DEPEND(ehci, usb, 1, 1, 1);
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