375 lines
11 KiB
C
375 lines
11 KiB
C
/*
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* Copyright (c) 1992 Terrence R. Lambert.
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* Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
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* Copyright (c) 1997 KATO Takenori.
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* Copyright (c) 2001 Tamotsu Hattori.
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* Copyright (c) 2001 Mitsuru IWASAKI.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
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* $FreeBSD$
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*/
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#include "opt_cpu.h"
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/sysctl.h>
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#include <sys/power.h>
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#include <machine/asmacros.h>
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#include <machine/clock.h>
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#include <machine/cputypes.h>
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#include <machine/segments.h>
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#include <machine/specialreg.h>
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#include <machine/md_var.h>
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#include <amd64/isa/icu.h>
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#include <amd64/isa/intr_machdep.h>
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/* XXX - should be in header file: */
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void printcpuinfo(void);
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void identify_cpu(void);
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void earlysetcpuclass(void);
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void panicifcpuunsupported(void);
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static void print_AMD_features(void);
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static void print_AMD_info(void);
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static void print_AMD_assoc(int i);
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int cpu_class;
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u_int cpu_exthigh; /* Highest arg to extended CPUID */
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char machine[] = "amd64";
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SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
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machine, 0, "Machine class");
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static char cpu_model[128];
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SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
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cpu_model, 0, "Machine model");
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static int hw_clockrate;
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SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
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&hw_clockrate, 0, "CPU instruction clock rate");
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static char cpu_brand[48];
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static struct cpu_nameclass amd64_cpus[] = {
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{ "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */
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{ "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */
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};
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void
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printcpuinfo(void)
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{
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u_int regs[4], i;
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char *brand;
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cpu_class = amd64_cpus[cpu].cpu_class;
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printf("CPU: ");
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strncpy(cpu_model, amd64_cpus[cpu].cpu_name, sizeof (cpu_model));
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/* Check for extended CPUID information and a processor name. */
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if (cpu_high > 0 &&
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(strcmp(cpu_vendor, "GenuineIntel") == 0 ||
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strcmp(cpu_vendor, "AuthenticAMD") == 0)) {
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do_cpuid(0x80000000, regs);
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if (regs[0] >= 0x80000000) {
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cpu_exthigh = regs[0];
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if (cpu_exthigh >= 0x80000004) {
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brand = cpu_brand;
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for (i = 0x80000002; i < 0x80000005; i++) {
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do_cpuid(i, regs);
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memcpy(brand, regs, sizeof(regs));
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brand += sizeof(regs);
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}
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}
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}
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}
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if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
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/* How the hell did you get here?? */
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strcat(cpu_model, "Yamhill?");
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} else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
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/*
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* Values taken from AMD Processor Recognition
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* http://www.amd.com/K6/k6docs/pdf/20734g.pdf
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* (also describes ``Features'' encodings.
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*/
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strcpy(cpu_model, "AMD ");
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switch (cpu_id & 0xF00) {
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case 0xf00:
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strcat(cpu_model, "AMD64 Processor");
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break;
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default:
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strcat(cpu_model, "Unknown");
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break;
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}
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}
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/*
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* Replace cpu_model with cpu_brand minus leading spaces if
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* we have one.
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*/
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brand = cpu_brand;
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while (*brand == ' ')
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++brand;
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if (*brand != '\0')
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strcpy(cpu_model, brand);
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printf("%s (", cpu_model);
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switch(cpu_class) {
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case CPUCLASS_K8:
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hw_clockrate = (tsc_freq + 5000) / 1000000;
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printf("%jd.%02d-MHz ",
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(intmax_t)(tsc_freq + 4999) / 1000000,
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(u_int)((tsc_freq + 4999) / 10000) % 100);
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printf("K8");
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break;
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default:
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printf("Unknown"); /* will panic below... */
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}
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printf("-class CPU)\n");
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if(*cpu_vendor)
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printf(" Origin = \"%s\"",cpu_vendor);
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if(cpu_id)
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printf(" Id = 0x%x", cpu_id);
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if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
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strcmp(cpu_vendor, "AuthenticAMD") == 0) {
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printf(" Stepping = %u", cpu_id & 0xf);
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if (cpu_high > 0) {
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/*
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* Here we should probably set up flags indicating
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* whether or not various features are available.
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* The interesting ones are probably VME, PSE, PAE,
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* and PGE. The code already assumes without bothering
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* to check that all CPUs >= Pentium have a TSC and
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* MSRs.
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*/
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printf("\n Features=0x%b", cpu_feature,
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"\020"
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"\001FPU" /* Integral FPU */
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"\002VME" /* Extended VM86 mode support */
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"\003DE" /* Debugging Extensions (CR4.DE) */
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"\004PSE" /* 4MByte page tables */
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"\005TSC" /* Timestamp counter */
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"\006MSR" /* Machine specific registers */
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"\007PAE" /* Physical address extension */
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"\010MCE" /* Machine Check support */
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"\011CX8" /* CMPEXCH8 instruction */
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"\012APIC" /* SMP local APIC */
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"\013oldMTRR" /* Previous implementation of MTRR */
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"\014SEP" /* Fast System Call */
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"\015MTRR" /* Memory Type Range Registers */
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"\016PGE" /* PG_G (global bit) support */
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"\017MCA" /* Machine Check Architecture */
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"\020CMOV" /* CMOV instruction */
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"\021PAT" /* Page attributes table */
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"\022PSE36" /* 36 bit address space support */
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"\023PN" /* Processor Serial number */
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"\024CLFLUSH" /* Has the CLFLUSH instruction */
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"\025<b20>"
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"\026DTS" /* Debug Trace Store */
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"\027ACPI" /* ACPI support */
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"\030MMX" /* MMX instructions */
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"\031FXSR" /* FXSAVE/FXRSTOR */
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"\032SSE" /* Streaming SIMD Extensions */
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"\033SSE2" /* Streaming SIMD Extensions #2 */
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"\034SS" /* Self snoop */
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"\035HTT" /* Hyperthreading (see EBX bit 16-23) */
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"\036TM" /* Thermal Monitor clock slowdown */
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"\037IA64" /* CPU can execute IA64 instructions */
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"\040PBE" /* Pending Break Enable */
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);
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/*
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* If this CPU supports hyperthreading then mention
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* the number of logical CPU's it contains.
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*/
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if (cpu_feature & CPUID_HTT &&
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(cpu_procinfo & CPUID_HTT_CORES) >> 16 > 1)
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printf("\n Hyperthreading: %d logical CPUs",
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(cpu_procinfo & CPUID_HTT_CORES) >> 16);
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}
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if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
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cpu_exthigh >= 0x80000001)
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print_AMD_features();
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} else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
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}
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/* Avoid ugly blank lines: only print newline when we have to. */
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if (*cpu_vendor || cpu_id)
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printf("\n");
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if (!bootverbose)
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return;
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if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
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print_AMD_info();
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}
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void
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panicifcpuunsupported(void)
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{
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#ifndef HAMMER
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#error "You need to specify a cpu type"
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#endif
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/*
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* Now that we have told the user what they have,
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* let them know if that machine type isn't configured.
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*/
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switch (cpu_class) {
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case CPUCLASS_X86:
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#ifndef HAMMER
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case CPUCLASS_K8:
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#endif
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panic("CPU class not configured");
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default:
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break;
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}
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}
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/*
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* Final stage of CPU identification. -- Should I check TI?
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*/
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void
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identify_cpu(void)
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{
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u_int regs[4];
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do_cpuid(0, regs);
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cpu_high = regs[0];
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((u_int *)&cpu_vendor)[0] = regs[1];
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((u_int *)&cpu_vendor)[1] = regs[3];
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((u_int *)&cpu_vendor)[2] = regs[2];
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cpu_vendor[12] = '\0';
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do_cpuid(1, regs);
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cpu_id = regs[0];
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cpu_procinfo = regs[1];
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cpu_feature = regs[3];
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/* XXX */
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cpu = CPU_CLAWHAMMER;
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}
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static void
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print_AMD_assoc(int i)
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{
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if (i == 255)
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printf(", fully associative\n");
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else
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printf(", %d-way associative\n", i);
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}
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static void
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print_AMD_info(void)
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{
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if (cpu_exthigh >= 0x80000005) {
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u_int regs[4];
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do_cpuid(0x80000005, regs);
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printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
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print_AMD_assoc(regs[1] >> 24);
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printf("Instruction TLB: %d entries", regs[1] & 0xff);
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print_AMD_assoc((regs[1] >> 8) & 0xff);
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printf("L1 data cache: %d kbytes", regs[2] >> 24);
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printf(", %d bytes/line", regs[2] & 0xff);
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printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
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print_AMD_assoc((regs[2] >> 16) & 0xff);
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printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
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printf(", %d bytes/line", regs[3] & 0xff);
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printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
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print_AMD_assoc((regs[3] >> 16) & 0xff);
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if (cpu_exthigh >= 0x80000006) { /* K6-III only */
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do_cpuid(0x80000006, regs);
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printf("L2 internal cache: %d kbytes", regs[2] >> 16);
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printf(", %d bytes/line", regs[2] & 0xff);
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printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
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print_AMD_assoc((regs[2] >> 12) & 0x0f);
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}
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}
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}
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static void
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print_AMD_features(void)
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{
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u_int regs[4];
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/*
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* Values taken from AMD Processor Recognition
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* http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf
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*/
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do_cpuid(0x80000001, regs);
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printf("\n AMD Features=0x%b", regs[3] &~ cpu_feature,
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"\020" /* in hex */
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"\001FPU" /* Integral FPU */
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"\002VME" /* Extended VM86 mode support */
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"\003DE" /* Debug extensions */
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"\004PSE" /* 4MByte page tables */
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"\005TSC" /* Timestamp counter */
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"\006MSR" /* Machine specific registers */
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"\007PAE" /* Physical address extension */
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"\010MCE" /* Machine Check support */
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"\011CX8" /* CMPEXCH8 instruction */
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"\012APIC" /* SMP local APIC */
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"\013<b10>"
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"\014SYSCALL" /* SYSENTER/SYSEXIT instructions */
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"\015MTRR" /* Memory Type Range Registers */
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"\016PGE" /* PG_G (global bit) support */
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"\017MCA" /* Machine Check Architecture */
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"\020ICMOV" /* CMOV instruction */
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"\021PAT" /* Page attributes table */
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"\022PGE36" /* 36 bit address space support */
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"\023RSVD" /* Reserved, unknown */
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"\024MP" /* Multiprocessor Capable */
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"\025NX" /* Has EFER.NXE, NX (no execute pte bit) */
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"\026<b21>"
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"\027MMX+" /* AMD MMX Instruction Extensions */
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"\030MMX"
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"\031FXSAVE" /* FXSAVE/FXRSTOR */
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"\032<b25>"
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"\033<b26>"
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"\034<b27>"
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"\035<b28>"
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"\036LM" /* Long mode */
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"\0373DNow!+" /* AMD 3DNow! Instruction Extensions */
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"\0403DNow!" /* AMD 3DNow! Instructions */
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);
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}
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