278 lines
6.5 KiB
C
278 lines
6.5 KiB
C
/*-
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* Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Portions of this software were developed by SRI International and the
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* University of Cambridge Computer Laboratory under DARPA/AFRL contract
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* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Portions of this software were developed by the University of Cambridge
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* Computer Laboratory as part of the CTSRD Project, with support from the
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* UK Higher Education Innovation Fund (HEIF).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* RISC-V Timer
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*/
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#include "opt_platform.h"
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <sys/watchdog.h>
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#include <sys/proc.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <machine/asm.h>
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#include <machine/trap.h>
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#include <machine/sbi.h>
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#define DEFAULT_FREQ 10000000
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#define TIMER_COUNTS 0x00
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#define TIMER_MTIMECMP(cpu) (cpu * 8)
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struct riscv_timer_softc {
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void *ih;
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uint32_t clkfreq;
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struct eventtimer et;
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};
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static struct riscv_timer_softc *riscv_timer_sc = NULL;
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static timecounter_get_t riscv_timer_get_timecount;
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static struct timecounter riscv_timer_timecount = {
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.tc_name = "RISC-V Timecounter",
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.tc_get_timecount = riscv_timer_get_timecount,
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.tc_poll_pps = NULL,
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.tc_counter_mask = ~0u,
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.tc_frequency = 0,
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.tc_quality = 1000,
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};
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static inline uint64_t
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get_cycles(void)
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{
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uint64_t cycles;
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__asm __volatile("rdtime %0" : "=r" (cycles));
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return (cycles);
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}
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static long
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get_counts(struct riscv_timer_softc *sc)
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{
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uint64_t counts;
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counts = get_cycles();
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return (counts);
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}
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static unsigned
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riscv_timer_get_timecount(struct timecounter *tc)
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{
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struct riscv_timer_softc *sc;
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sc = tc->tc_priv;
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return (get_counts(sc));
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}
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static int
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riscv_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
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{
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uint64_t counts;
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if (first != 0) {
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counts = ((uint32_t)et->et_frequency * first) >> 32;
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sbi_set_timer(get_cycles() + counts);
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csr_set(sie, SIE_STIE);
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return (0);
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}
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return (EINVAL);
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}
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static int
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riscv_timer_stop(struct eventtimer *et)
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{
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/* TODO */
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return (0);
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}
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static int
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riscv_timer_intr(void *arg)
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{
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struct riscv_timer_softc *sc;
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sc = (struct riscv_timer_softc *)arg;
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csr_clear(sip, SIP_STIP);
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if (sc->et.et_active)
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sc->et.et_event_cb(&sc->et, sc->et.et_arg);
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return (FILTER_HANDLED);
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}
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static int
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riscv_timer_probe(device_t dev)
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{
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device_set_desc(dev, "RISC-V Timer");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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riscv_timer_attach(device_t dev)
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{
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struct riscv_timer_softc *sc;
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int error;
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sc = device_get_softc(dev);
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if (riscv_timer_sc)
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return (ENXIO);
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if (device_get_unit(dev) != 0)
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return ENXIO;
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sc->clkfreq = DEFAULT_FREQ;
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if (sc->clkfreq == 0) {
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device_printf(dev, "No clock frequency specified\n");
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return (ENXIO);
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}
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riscv_timer_sc = sc;
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/* Setup IRQs handler */
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error = riscv_setup_intr(device_get_nameunit(dev), riscv_timer_intr,
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NULL, sc, IRQ_TIMER_SUPERVISOR, INTR_TYPE_CLK, &sc->ih);
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if (error) {
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device_printf(dev, "Unable to alloc int resource.\n");
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return (ENXIO);
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}
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riscv_timer_timecount.tc_frequency = sc->clkfreq;
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riscv_timer_timecount.tc_priv = sc;
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tc_init(&riscv_timer_timecount);
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sc->et.et_name = "RISC-V Eventtimer";
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sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
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sc->et.et_quality = 1000;
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sc->et.et_frequency = sc->clkfreq;
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sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
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sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
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sc->et.et_start = riscv_timer_start;
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sc->et.et_stop = riscv_timer_stop;
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sc->et.et_priv = sc;
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et_register(&sc->et);
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return (0);
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}
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static device_method_t riscv_timer_methods[] = {
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DEVMETHOD(device_probe, riscv_timer_probe),
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DEVMETHOD(device_attach, riscv_timer_attach),
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{ 0, 0 }
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};
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static driver_t riscv_timer_driver = {
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"timer",
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riscv_timer_methods,
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sizeof(struct riscv_timer_softc),
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};
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static devclass_t riscv_timer_devclass;
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EARLY_DRIVER_MODULE(timer, nexus, riscv_timer_driver, riscv_timer_devclass,
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0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
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void
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DELAY(int usec)
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{
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int64_t counts, counts_per_usec;
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uint64_t first, last;
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/*
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* Check the timers are setup, if not just
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* use a for loop for the meantime
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*/
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if (riscv_timer_sc == NULL) {
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for (; usec > 0; usec--)
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for (counts = 200; counts > 0; counts--)
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/*
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* Prevent the compiler from optimizing
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* out the loop
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*/
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cpufunc_nullop();
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return;
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}
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TSENTER();
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/* Get the number of times to count */
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counts_per_usec = ((riscv_timer_timecount.tc_frequency / 1000000) + 1);
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/*
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* Clamp the timeout at a maximum value (about 32 seconds with
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* a 66MHz clock). *Nobody* should be delay()ing for anywhere
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* near that length of time and if they are, they should be hung
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* out to dry.
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*/
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if (usec >= (0x80000000U / counts_per_usec))
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counts = (0x80000000U / counts_per_usec) - 1;
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else
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counts = usec * counts_per_usec;
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first = get_counts(riscv_timer_sc);
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while (counts > 0) {
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last = get_counts(riscv_timer_sc);
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counts -= (int64_t)(last - first);
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first = last;
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}
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TSEXIT();
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}
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