1e2ceeb16a
The RISC-V spec defines several performance counter CSRs such as: cycle, time, instret, hpmcounter(3...31). They are defined to be 64-bits wide on all RISC-V architectures. On RV64 and RV128 they can be read from a single CSR. On RV32, additional CSRs (given the suffix "h") are present which contain the upper 32 bits of these counters, and must be read as well. (See section 2.8 in the User ISA Spec for full details.) This change adds macros for reading these values safely on any RISC-V ISA length. Obviously we aren't supporting anything other than RV64 at the moment, but this ensures we won't need to change how we read these values if we ever do. Submitted by: Mitchell Horne <mhorne063@gmail.com> Reviewed by: jhb MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D17952
118 lines
3.0 KiB
C
118 lines
3.0 KiB
C
/*-
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* Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Portions of this software were developed by SRI International and the
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* University of Cambridge Computer Laboratory under DARPA/AFRL contract
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* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Portions of this software were developed by the University of Cambridge
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* Computer Laboratory as part of the CTSRD Project, with support from the
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* UK Higher Education Innovation Fund (HEIF).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_CPUFUNC_H_
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#define _MACHINE_CPUFUNC_H_
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static __inline void
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breakpoint(void)
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{
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__asm("ebreak");
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}
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#ifdef _KERNEL
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#include <machine/riscvreg.h>
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static __inline register_t
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intr_disable(void)
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{
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uint64_t ret;
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__asm __volatile(
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"csrrci %0, sstatus, %1"
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: "=&r" (ret) : "i" (SSTATUS_SIE)
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);
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return (ret & (SSTATUS_SIE));
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}
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static __inline void
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intr_restore(register_t s)
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{
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__asm __volatile(
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"csrs sstatus, %0"
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:: "r" (s)
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);
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}
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static __inline void
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intr_enable(void)
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{
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__asm __volatile(
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"csrsi sstatus, %0"
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:: "i" (SSTATUS_SIE)
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);
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}
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/* NB: fence() is defined as a macro in <machine/atomic.h>. */
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static __inline void
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fence_i(void)
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{
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__asm __volatile("fence.i" ::: "memory");
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}
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static __inline void
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sfence_vma(void)
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{
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__asm __volatile("sfence.vma" ::: "memory");
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}
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static __inline void
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sfence_vma_page(uintptr_t addr)
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{
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__asm __volatile("sfence.vma %0" :: "r" (addr) : "memory");
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}
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#define rdcycle() csr_read64(cycle)
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#define rdtime() csr_read64(time)
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#define rdinstret() csr_read64(instret)
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#define rdhpmcounter(n) csr_read64(hpmcounter##n)
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#define cpufunc_nullop() riscv_nullop()
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void riscv_nullop(void);
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#endif /* _KERNEL */
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#endif /* _MACHINE_CPUFUNC_H_ */
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