c626f1fe9a
attach to the hostb driver instead. This means that agp can now be loaded at runtime (in theory at least). Also, the drivers no longer have to explicity call device_verbose() to cancel out any earlier calls to device_quiet() by the hostb(4) driver (this shows a limitation in new-bus, drivers really shouldn't be doing device_quiet() until they know they are going to drive that device, i.e. in attach).
430 lines
11 KiB
C
430 lines
11 KiB
C
/*-
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* Copyright (c) 2000 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_bus.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/proc.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <pci/agppriv.h>
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#include <pci/agpreg.h>
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#include <vm/vm.h>
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#include <vm/vm_object.h>
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#include <vm/pmap.h>
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#define MAX_APSIZE 0x3f /* 256 MB */
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struct agp_intel_softc {
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struct agp_softc agp;
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u_int32_t initial_aperture; /* aperture size at startup */
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struct agp_gatt *gatt;
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u_int aperture_mask;
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};
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static const char*
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agp_intel_match(device_t dev)
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{
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if (pci_get_class(dev) != PCIC_BRIDGE
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|| pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
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return NULL;
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if (agp_find_caps(dev) == 0)
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return NULL;
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switch (pci_get_devid(dev)) {
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/* Intel -- vendor 0x8086 */
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case 0x71808086:
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return ("Intel 82443LX (440 LX) host to PCI bridge");
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case 0x71908086:
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return ("Intel 82443BX (440 BX) host to PCI bridge");
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case 0x71a08086:
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return ("Intel 82443GX host to PCI bridge");
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case 0x71a18086:
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return ("Intel 82443GX host to AGP bridge");
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case 0x11308086:
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return ("Intel 82815 (i815 GMCH) host to PCI bridge");
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case 0x25008086:
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case 0x25018086:
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return ("Intel 82820 host to AGP bridge");
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case 0x35758086:
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return ("Intel 82830 host to AGP bridge");
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case 0x1a218086:
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return ("Intel 82840 host to AGP bridge");
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case 0x1a308086:
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return ("Intel 82845 host to AGP bridge");
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case 0x25308086:
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return ("Intel 82850 host to AGP bridge");
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case 0x33408086:
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return ("Intel 82855 host to AGP bridge");
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case 0x25318086:
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return ("Intel 82860 host to AGP bridge");
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case 0x25708086:
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return ("Intel 82865 host to AGP bridge");
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case 0x255d8086:
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return ("Intel E7205 host to AGP bridge");
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case 0x25788086:
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return ("Intel 82875P host to AGP bridge");
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case 0x25608086:
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return ("Intel 82845G host to AGP bridge");
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case 0x35808086:
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return ("Intel 82855GM host to AGP bridge");
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};
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return NULL;
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}
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static int
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agp_intel_probe(device_t dev)
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{
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const char *desc;
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if (resource_disabled("agp", device_get_unit(dev)))
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return (ENXIO);
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desc = agp_intel_match(dev);
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if (desc) {
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device_set_desc(dev, desc);
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return BUS_PROBE_DEFAULT;
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}
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return ENXIO;
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}
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static int
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agp_intel_attach(device_t dev)
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{
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struct agp_intel_softc *sc = device_get_softc(dev);
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struct agp_gatt *gatt;
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u_int32_t type = pci_get_devid(dev);
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u_int32_t value;
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int error;
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error = agp_generic_attach(dev);
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if (error)
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return error;
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/* Determine maximum supported aperture size. */
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value = pci_read_config(dev, AGP_INTEL_APSIZE, 1);
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pci_write_config(dev, AGP_INTEL_APSIZE, MAX_APSIZE, 1);
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sc->aperture_mask = pci_read_config(dev, AGP_INTEL_APSIZE, 1) &
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MAX_APSIZE;
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pci_write_config(dev, AGP_INTEL_APSIZE, value, 1);
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sc->initial_aperture = AGP_GET_APERTURE(dev);
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for (;;) {
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gatt = agp_alloc_gatt(dev);
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if (gatt)
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break;
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/*
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* Probably contigmalloc failure. Try reducing the
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* aperture so that the gatt size reduces.
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*/
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if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
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agp_generic_detach(dev);
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return ENOMEM;
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}
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}
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sc->gatt = gatt;
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/* Install the gatt. */
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pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4);
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/* Enable the GLTB and setup the control register. */
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switch (type) {
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case 0x71908086: /* 440LX/EX */
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pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2080, 4);
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break;
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case 0x71808086: /* 440BX */
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/*
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* XXX: Should be 0xa080? Bit 9 is undefined, and
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* bit 13 being on and bit 15 being clear is illegal.
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*/
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pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);
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break;
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default:
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value = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4);
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pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4);
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}
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/* Enable things, clear errors etc. */
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switch (type) {
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case 0x1a218086: /* i840 */
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case 0x25308086: /* i850 */
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case 0x25318086: /* i860 */
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pci_write_config(dev, AGP_INTEL_MCHCFG,
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(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
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| (1 << 9)), 2);
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break;
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case 0x25008086: /* i820 */
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case 0x25018086: /* i820 */
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pci_write_config(dev, AGP_INTEL_I820_RDCR,
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(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
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| (1 << 1)), 1);
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break;
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case 0x1a308086: /* i845 */
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case 0x33408086: /* i855 */
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case 0x35808086: /* i855GM */
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case 0x255d8086: /* E7205 */
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case 0x25708086: /* i865 */
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case 0x25788086: /* i875P */
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case 0x25608086: /* i845G */
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pci_write_config(dev, AGP_INTEL_I845_MCHCFG,
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(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
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| (1 << 1)), 1);
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break;
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default: /* Intel Generic (maybe) */
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pci_write_config(dev, AGP_INTEL_NBXCFG,
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(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
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& ~(1 << 10)) | (1 << 9), 4);
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}
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switch (type) {
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case 0x1a218086: /* i840 */
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pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
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break;
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case 0x25008086: /* i820 */
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case 0x25018086: /* i820 */
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case 0x1a308086: /* i845 */
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case 0x25308086: /* i850 */
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case 0x33408086: /* i855 */
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case 0x255d8086: /* E7205 */
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case 0x25318086: /* i860 */
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case 0x25708086: /* i865 */
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case 0x25788086: /* i875P */
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case 0x25608086: /* i845G */
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pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2);
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break;
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default: /* Intel Generic (maybe) */
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pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
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}
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return 0;
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}
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static int
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agp_intel_detach(device_t dev)
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{
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struct agp_intel_softc *sc = device_get_softc(dev);
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u_int32_t type = pci_get_devid(dev);
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int error;
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error = agp_generic_detach(dev);
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if (error)
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return error;
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switch (type) {
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case 0x1a218086: /* i840 */
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case 0x25308086: /* i850 */
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case 0x25318086: /* i860 */
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printf("%s: set MCHCFG to %x\n", __func__, (unsigned)
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(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
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& ~(1 << 9)));
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pci_write_config(dev, AGP_INTEL_MCHCFG,
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(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
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& ~(1 << 9)), 2);
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case 0x25008086: /* i820 */
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case 0x25018086: /* i820 */
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printf("%s: set RDCR to %x\n", __func__, (unsigned)
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(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
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& ~(1 << 1)));
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pci_write_config(dev, AGP_INTEL_I820_RDCR,
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(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
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& ~(1 << 1)), 1);
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case 0x1a308086: /* i845 */
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case 0x25608086: /* i845G */
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case 0x33408086: /* i855 */
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case 0x35808086: /* i855GM */
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case 0x255d8086: /* E7205 */
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case 0x25708086: /* i865 */
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case 0x25788086: /* i875P */
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printf("%s: set MCHCFG to %x\n", __func__, (unsigned)
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(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
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& ~(1 << 1)));
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pci_write_config(dev, AGP_INTEL_MCHCFG,
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(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
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& ~(1 << 1)), 1);
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default: /* Intel Generic (maybe) */
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printf("%s: set NBXCFG to %x\n", __func__,
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(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
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& ~(1 << 9)));
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pci_write_config(dev, AGP_INTEL_NBXCFG,
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(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
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& ~(1 << 9)), 4);
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}
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pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
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AGP_SET_APERTURE(dev, sc->initial_aperture);
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agp_free_gatt(sc->gatt);
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return 0;
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}
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static u_int32_t
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agp_intel_get_aperture(device_t dev)
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{
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struct agp_intel_softc *sc = device_get_softc(dev);
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u_int32_t apsize;
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apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & sc->aperture_mask;
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/*
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* The size is determined by the number of low bits of
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* register APBASE which are forced to zero. The low 22 bits
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* are always forced to zero and each zero bit in the apsize
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* field just read forces the corresponding bit in the 27:22
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* to be zero. We calculate the aperture size accordingly.
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*/
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return (((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1;
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}
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static int
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agp_intel_set_aperture(device_t dev, u_int32_t aperture)
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{
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struct agp_intel_softc *sc = device_get_softc(dev);
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u_int32_t apsize;
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/*
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* Reverse the magic from get_aperture.
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*/
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apsize = ((aperture - 1) >> 22) ^ sc->aperture_mask;
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/*
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* Double check for sanity.
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*/
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if ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1 != aperture)
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return EINVAL;
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pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1);
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return 0;
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}
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static int
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agp_intel_bind_page(device_t dev, int offset, vm_offset_t physical)
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{
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struct agp_intel_softc *sc = device_get_softc(dev);
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if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
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return EINVAL;
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sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17;
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return 0;
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}
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static int
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agp_intel_unbind_page(device_t dev, int offset)
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{
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struct agp_intel_softc *sc = device_get_softc(dev);
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if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
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return EINVAL;
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sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
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return 0;
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}
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static void
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agp_intel_flush_tlb(device_t dev)
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{
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u_int32_t val;
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val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4);
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pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 7), 4);
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pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4);
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}
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static device_method_t agp_intel_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, agp_intel_probe),
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DEVMETHOD(device_attach, agp_intel_attach),
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DEVMETHOD(device_detach, agp_intel_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD(device_suspend, bus_generic_suspend),
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DEVMETHOD(device_resume, bus_generic_resume),
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/* AGP interface */
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DEVMETHOD(agp_get_aperture, agp_intel_get_aperture),
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DEVMETHOD(agp_set_aperture, agp_intel_set_aperture),
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DEVMETHOD(agp_bind_page, agp_intel_bind_page),
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DEVMETHOD(agp_unbind_page, agp_intel_unbind_page),
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DEVMETHOD(agp_flush_tlb, agp_intel_flush_tlb),
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DEVMETHOD(agp_enable, agp_generic_enable),
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DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
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DEVMETHOD(agp_free_memory, agp_generic_free_memory),
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DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
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DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
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{ 0, 0 }
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};
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static driver_t agp_intel_driver = {
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"agp",
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agp_intel_methods,
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sizeof(struct agp_intel_softc),
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};
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static devclass_t agp_devclass;
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DRIVER_MODULE(agp_intel, hostb, agp_intel_driver, agp_devclass, 0, 0);
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MODULE_DEPEND(agp_intel, agp, 1, 1, 1);
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MODULE_DEPEND(agp_intel, pci, 1, 1, 1);
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