875e2e9ca9
Without this option it is not possible to omit the driver from the configuration file and successfully build a kernel. This option is specific to alpha.
282 lines
6.1 KiB
C
282 lines
6.1 KiB
C
/*
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* Copyright (c) 1995, 1996, 1997 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*
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* Additional Copyright (c) 1997 by Matthew Jacob for NASA/Ames Research Center
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*/
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/*
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* Additional Copyright (c) 1998 by Andrew Gallatin for Duke University
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ddb.h"
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#include "opt_dev_sc.h"
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#include <sys/param.h>
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#include <sys/reboot.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/termios.h>
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#include <machine/clock.h>
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#include <machine/cpuconf.h>
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#include <machine/intr.h>
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#include <machine/md_var.h>
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#include <machine/rpb.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <alpha/pci/ciareg.h>
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#include <alpha/pci/ciavar.h>
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#ifndef NO_SIO
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#ifndef CONSPEED
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#define CONSPEED TTYDEF_SPEED
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#endif
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static int comcnrate = CONSPEED;
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extern int comconsole;
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extern int siocnattach(int, int);
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extern int siogdbattach(int, int);
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#endif
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extern int sccnattach(void);
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void st550_init(void);
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static void st550_cons_init(void);
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static void st550_intr_init(void);
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static void pyxis_intr_enable(int);
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static void pyxis_intr_disable(int);
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static void st550_intr_enable(int);
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static void st550_intr_disable(int);
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static void st550_intr_map(void *);
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#define ST550_PCI_IRQ_BEGIN 8
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#define ST550_PCI_MAX_IRQ 47
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void
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st550_init()
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{
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platform.family = "Digital Personal Workstation (Miata)";
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if ((platform.model = alpha_dsr_sysname()) == NULL) {
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/* XXX Don't know the system variations, yet. */
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platform.model = alpha_unknown_sysname();
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}
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platform.iobus = "cia";
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platform.cons_init = st550_cons_init;
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platform.pci_intr_init = st550_intr_init;
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platform.pci_intr_map = st550_intr_map;
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platform.pci_intr_disable = st550_intr_disable;
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platform.pci_intr_enable = st550_intr_enable;
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}
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static void
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st550_cons_init()
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{
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struct ctb *ctb;
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cia_init();
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#ifndef NO_SIO
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#ifdef DDB
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siogdbattach(0x2f8, 57600);
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#endif
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#endif
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ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off);
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switch (ctb->ctb_term_type) {
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case 2:
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#ifndef NO_SIO
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/* serial console ... */
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/* XXX */
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/*
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* Delay to allow PROM putchars to complete.
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* FIFO depth * character time,
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* character time = (1000000 / (defaultrate / 10))
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*/
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DELAY(160000000 / comcnrate);
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comconsole = 0;
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if (siocnattach(0x3f8, comcnrate))
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panic("can't init serial console");
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boothowto |= RB_SERIAL;
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#endif
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break;
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case 3:
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/* display console ... */
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/* XXX */
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#ifdef DEV_SC
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sccnattach();
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#else
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panic("not configured to use display && keyboard console");
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#endif
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break;
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default:
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printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type);
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printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot);
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panic("consinit: unknown console type %ld\n",
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ctb->ctb_term_type);
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}
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}
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static void
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st550_intr_init()
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{
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/* This is here because we need to disable extraneous pci interrupts. */
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int i;
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for(i = ST550_PCI_IRQ_BEGIN; i <= ST550_PCI_MAX_IRQ; i++)
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pyxis_intr_disable(i);
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/* From Linux... */
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pyxis_intr_enable(2); /* enable HALT switch */
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pyxis_intr_enable(6); /* enable timer */
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pyxis_intr_enable(7); /* enable ISA PIC cascade */
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}
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static void
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st550_intr_map(void *arg)
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{
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pcicfgregs *cfg;
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cfg = (pcicfgregs *)arg;
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/* There are two main variants of Miata: Miata 1 (Intel SIO)
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* and Miata {1.5,2} (Cypress).
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*
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* The Miata 1 has a CMD PCI IDE wired to compatibility mode at
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* slot 4 of bus 0. This variant has the Pyxis DMA bug.
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*
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* On the Miata 1.5 and Miata 2, the Cypress PCI-ISA bridge lives
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* on device 7 of bus 0. This device has PCI IDE wired to
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* compatibility mode on functions 1 and 2.
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*
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* There will be no interrupt mapping for these devices, so just
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* bail out now.
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*/
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if(cfg->bus == 0) {
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if ((hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) {
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/* Miata 1 */
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if (cfg->slot == 7)
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return;
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else if (cfg->func == 4)
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return;
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} else {
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/* Miata 1.5 or Miata 2 */
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if (cfg->slot == 7) {
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if (cfg->func == 0)
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return;
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return;
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}
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}
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}
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/* Account for the PCI interrupt offset. */
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/* cfg->intline += ST550_PCI_IRQ_BEGIN; */
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return;
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}
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/*
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* The functions below were written based on a draft copy of the
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* 21174 TRM.
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*/
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static void
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pyxis_intr_enable(irq)
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int irq;
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{
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volatile u_int64_t temp;
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alpha_mb();
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temp = REGVAL64(PYXIS_INT_MASK);
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alpha_mb();
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temp |= ( 1L << irq );
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REGVAL64(PYXIS_INT_MASK) = temp;
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alpha_mb();
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temp = REGVAL64(PYXIS_INT_MASK);
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#if 0
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printf("pyxis_intr_enable: enabling %d, current mask= ", irq);
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{
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int i;
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for ( i = 0; i < 61; i++)
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if (temp & (1 << i)) {
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printf("%d " , i);
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}
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printf("\n");
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}
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#endif
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}
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static void
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pyxis_intr_disable(irq)
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int irq;
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{
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volatile u_int64_t temp;
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alpha_mb();
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temp = REGVAL64(PYXIS_INT_MASK);
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temp &= ~(1L << irq );
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REGVAL64(PYXIS_INT_MASK) = temp;
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alpha_mb();
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temp = REGVAL64(PYXIS_INT_MASK);
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#if 0
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printf("pyxis_intr_disable: disabled %d, current mask ", irq);
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{
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int i;
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for ( i = 0; i < 61; i++)
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if (temp & (1 << i)) {
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printf("%d ", i);
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}
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printf("\n");
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}
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#endif
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}
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static void
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st550_intr_enable(irq)
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int irq;
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{
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pyxis_intr_enable(irq + ST550_PCI_IRQ_BEGIN);
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}
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static void
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st550_intr_disable(irq)
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int irq;
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{
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pyxis_intr_disable(irq + ST550_PCI_IRQ_BEGIN);
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}
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