046b51bfdd
In order to become independent of Coherency Fabric frequency, configure Timer and Watchdog to operate in 25MHz mode. Submitted by: Zbigniew Bodek <zbb@semihalf.com>
444 lines
14 KiB
C
444 lines
14 KiB
C
/*-
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* Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD.
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* All rights reserved.
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*
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* Developed by Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of MARVELL nor the names of contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MVREG_H_
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#define _MVREG_H_
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#if defined(SOC_MV_DISCOVERY)
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#define IRQ_CAUSE_ERROR 0x0
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#define IRQ_CAUSE 0x4
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#define IRQ_CAUSE_HI 0x8
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#define IRQ_MASK_ERROR 0xC
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#define IRQ_MASK 0x10
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#define IRQ_MASK_HI 0x14
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#define IRQ_CAUSE_SELECT 0x18
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#define FIQ_MASK_ERROR 0x1C
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#define FIQ_MASK 0x20
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#define FIQ_MASK_HI 0x24
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#define FIQ_CAUSE_SELECT 0x28
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#define ENDPOINT_IRQ_MASK_ERROR(n) 0x2C
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#define ENDPOINT_IRQ_MASK(n) 0x30
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#define ENDPOINT_IRQ_MASK_HI(n) 0x34
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#define ENDPOINT_IRQ_CAUSE_SELECT 0x38
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#elif defined (SOC_MV_LOKIPLUS) || defined (SOC_MV_FREY)
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#define IRQ_CAUSE 0x0
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#define IRQ_MASK 0x4
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#define FIQ_MASK 0x8
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#define ENDPOINT_IRQ_MASK(n) (0xC + (n) * 4)
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#define IRQ_CAUSE_HI (-1) /* Fake defines for unified */
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#define IRQ_MASK_HI (-1) /* interrupt controller code */
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#define FIQ_MASK_HI (-1)
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#define ENDPOINT_IRQ_MASK_HI(n) (-1)
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#define ENDPOINT_IRQ_MASK_ERROR(n) (-1)
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#define IRQ_CAUSE_ERROR (-1)
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#define IRQ_MASK_ERROR (-1)
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#elif defined (SOC_MV_ARMADAXP)
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#define IRQ_CAUSE 0x18
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#define IRQ_MASK 0x30
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#else /* !SOC_MV_DISCOVERY && !SOC_MV_LOKIPLUS */
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#define IRQ_CAUSE 0x0
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#define IRQ_MASK 0x4
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#define FIQ_MASK 0x8
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#define ENDPOINT_IRQ_MASK(n) 0xC
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#define IRQ_CAUSE_HI 0x10
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#define IRQ_MASK_HI 0x14
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#define FIQ_MASK_HI 0x18
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#define ENDPOINT_IRQ_MASK_HI(n) 0x1C
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#define ENDPOINT_IRQ_MASK_ERROR(n) (-1)
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#define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */
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#define IRQ_MASK_ERROR (-1) /* interrupt controller code */
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#endif
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#if defined(SOC_MV_FREY)
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#define BRIDGE_IRQ_CAUSE 0x118
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#define IRQ_TIMER0 0x00000002
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#define IRQ_TIMER1 0x00000004
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#define IRQ_TIMER_WD 0x00000008
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#define BRIDGE_IRQ_MASK 0x11c
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#define IRQ_TIMER0_MASK 0x00000002
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#define IRQ_TIMER1_MASK 0x00000004
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#define IRQ_TIMER_WD_MASK 0x00000008
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#elif defined(SOC_MV_ARMADAXP)
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#define BRIDGE_IRQ_CAUSE 0x68
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#define IRQ_TIMER0 0x00000001
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#define IRQ_TIMER1 0x00000002
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#define IRQ_TIMER_WD 0x00000004
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#else
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#define BRIDGE_IRQ_CAUSE 0x10
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#define IRQ_CPU_SELF 0x00000001
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#define IRQ_TIMER0 0x00000002
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#define IRQ_TIMER1 0x00000004
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#define IRQ_TIMER_WD 0x00000008
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#define BRIDGE_IRQ_MASK 0x14
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#define IRQ_CPU_MASK 0x00000001
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#define IRQ_TIMER0_MASK 0x00000002
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#define IRQ_TIMER1_MASK 0x00000004
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#define IRQ_TIMER_WD_MASK 0x00000008
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#endif
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#if defined(SOC_MV_LOKIPLUS) || defined(SOC_MV_FREY)
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#define IRQ_CPU_SELF_CLR IRQ_CPU_SELF
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#define IRQ_TIMER0_CLR IRQ_TIMER0
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#define IRQ_TIMER1_CLR IRQ_TIMER1
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#define IRQ_TIMER_WD_CLR IRQ_TIMER_WD
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#else
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#define IRQ_CPU_SELF_CLR (~IRQ_CPU_SELF)
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#define IRQ_TIMER0_CLR (~IRQ_TIMER0)
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#define IRQ_TIMER1_CLR (~IRQ_TIMER1)
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#define IRQ_TIMER_WD_CLR (~IRQ_TIMER_WD)
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#endif
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/*
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* System reset
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*/
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#if defined(SOC_MV_ARMADAXP)
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#define RSTOUTn_MASK 0x60
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#define SYSTEM_SOFT_RESET 0x64
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#define WD_RSTOUTn_MASK 0x4
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#define WD_GLOBAL_MASK 0x00000100
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#define WD_CPU0_MASK 0x00000001
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#define SOFT_RST_OUT_EN 0x00000001
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#define SYS_SOFT_RST 0x00000001
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#else
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#define RSTOUTn_MASK 0x8
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#define WD_RST_OUT_EN 0x00000002
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#define SOFT_RST_OUT_EN 0x00000004
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#define SYSTEM_SOFT_RESET 0xc
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#define SYS_SOFT_RST 0x00000001
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#endif
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/*
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* Power Control
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*/
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#define CPU_PM_CTRL 0x1C
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#define CPU_PM_CTRL_NONE 0
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#define CPU_PM_CTRL_ALL ~0x0
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#if defined(SOC_MV_KIRKWOOD)
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#define CPU_PM_CTRL_GE0 (1 << 0)
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#define CPU_PM_CTRL_PEX0_PHY (1 << 1)
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#define CPU_PM_CTRL_PEX0 (1 << 2)
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#define CPU_PM_CTRL_USB0 (1 << 3)
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#define CPU_PM_CTRL_SDIO (1 << 4)
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#define CPU_PM_CTRL_TSU (1 << 5)
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#define CPU_PM_CTRL_DUNIT (1 << 6)
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#define CPU_PM_CTRL_RUNIT (1 << 7)
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#define CPU_PM_CTRL_XOR0 (1 << 8)
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#define CPU_PM_CTRL_AUDIO (1 << 9)
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#define CPU_PM_CTRL_SATA0 (1 << 14)
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#define CPU_PM_CTRL_SATA1 (1 << 15)
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#define CPU_PM_CTRL_XOR1 (1 << 16)
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#define CPU_PM_CTRL_CRYPTO (1 << 17)
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#define CPU_PM_CTRL_GE1 (1 << 19)
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#define CPU_PM_CTRL_TDM (1 << 20)
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#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_XOR0 | CPU_PM_CTRL_XOR1)
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#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_USB0)
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#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1)
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#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \
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(1 - (u)))
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#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE)
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#elif defined(SOC_MV_DISCOVERY)
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#define CPU_PM_CTRL_GE0 (1 << 1)
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#define CPU_PM_CTRL_GE1 (1 << 2)
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#define CPU_PM_CTRL_PEX00 (1 << 5)
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#define CPU_PM_CTRL_PEX01 (1 << 6)
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#define CPU_PM_CTRL_PEX02 (1 << 7)
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#define CPU_PM_CTRL_PEX03 (1 << 8)
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#define CPU_PM_CTRL_PEX10 (1 << 9)
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#define CPU_PM_CTRL_PEX11 (1 << 10)
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#define CPU_PM_CTRL_PEX12 (1 << 11)
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#define CPU_PM_CTRL_PEX13 (1 << 12)
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#define CPU_PM_CTRL_SATA0_PHY (1 << 13)
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#define CPU_PM_CTRL_SATA0 (1 << 14)
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#define CPU_PM_CTRL_SATA1_PHY (1 << 15)
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#define CPU_PM_CTRL_SATA1 (1 << 16)
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#define CPU_PM_CTRL_USB0 (1 << 17)
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#define CPU_PM_CTRL_USB1 (1 << 18)
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#define CPU_PM_CTRL_USB2 (1 << 19)
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#define CPU_PM_CTRL_IDMA (1 << 20)
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#define CPU_PM_CTRL_XOR (1 << 21)
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#define CPU_PM_CTRL_CRYPTO (1 << 22)
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#define CPU_PM_CTRL_DEVICE (1 << 23)
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#define CPU_PM_CTRL_USB(u) (1 << (17 + (u)))
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#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1)
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#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \
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(1 - (u)))
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#else
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#define CPU_PM_CTRL_CRYPTO (CPU_PM_CTRL_NONE)
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#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE)
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#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_NONE)
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#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_NONE)
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#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_NONE)
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#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_NONE)
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#endif
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/*
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* Timers
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*/
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#define CPU_TIMERS_BASE 0x300
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#define CPU_TIMER_CONTROL 0x0
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#define CPU_TIMER0_EN 0x00000001
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#define CPU_TIMER0_AUTO 0x00000002
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#define CPU_TIMER1_EN 0x00000004
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#define CPU_TIMER1_AUTO 0x00000008
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#define CPU_TIMER_WD_EN 0x00000010
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#define CPU_TIMER_WD_AUTO 0x00000020
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/* 25MHz mode is Armada XP - specific */
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#define CPU_TIMER_WD_25MHZ_EN 0x00000400
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#define CPU_TIMER0_25MHZ_EN 0x00000800
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#define CPU_TIMER1_25MHZ_EN 0x00001000
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#define CPU_TIMER0_REL 0x10
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#define CPU_TIMER0 0x14
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/*
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* SATA
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*/
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#define SATA_CHAN_NUM 2
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#define EDMA_REGISTERS_OFFSET 0x2000
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#define EDMA_REGISTERS_SIZE 0x2000
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#define SATA_EDMA_BASE(ch) (EDMA_REGISTERS_OFFSET + \
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((ch) * EDMA_REGISTERS_SIZE))
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/* SATAHC registers */
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#define SATA_CR 0x000 /* Configuration Reg. */
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#define SATA_CR_NODMABS (1 << 8)
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#define SATA_CR_NOEDMABS (1 << 9)
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#define SATA_CR_NOPRDPBS (1 << 10)
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#define SATA_CR_COALDIS(ch) (1 << (24 + ch))
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/* Interrupt Coalescing Threshold Reg. */
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#define SATA_ICTR 0x00C
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#define SATA_ICTR_MAX ((1 << 8) - 1)
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/* Interrupt Time Threshold Reg. */
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#define SATA_ITTR 0x010
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#define SATA_ITTR_MAX ((1 << 24) - 1)
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#define SATA_ICR 0x014 /* Interrupt Cause Reg. */
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#define SATA_ICR_DMADONE(ch) (1 << (ch))
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#define SATA_ICR_COAL (1 << 4)
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#define SATA_ICR_DEV(ch) (1 << (8 + ch))
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#define SATA_MICR 0x020 /* Main Interrupt Cause Reg. */
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#define SATA_MICR_ERR(ch) (1 << (2 * ch))
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#define SATA_MICR_DONE(ch) (1 << ((2 * ch) + 1))
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#define SATA_MICR_DMADONE(ch) (1 << (4 + ch))
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#define SATA_MICR_COAL (1 << 8)
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#define SATA_MIMR 0x024 /* Main Interrupt Mask Reg. */
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/* Shadow registers */
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#define SATA_SHADOWR_BASE(ch) (SATA_EDMA_BASE(ch) + 0x100)
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#define SATA_SHADOWR_CONTROL(ch) (SATA_EDMA_BASE(ch) + 0x120)
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/* SATA registers */
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#define SATA_SATA_SSTATUS(ch) (SATA_EDMA_BASE(ch) + 0x300)
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#define SATA_SATA_SERROR(ch) (SATA_EDMA_BASE(ch) + 0x304)
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#define SATA_SATA_SCONTROL(ch) (SATA_EDMA_BASE(ch) + 0x308)
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#define SATA_SATA_FISICR(ch) (SATA_EDMA_BASE(ch) + 0x364)
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/* EDMA registers */
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#define SATA_EDMA_CFG(ch) (SATA_EDMA_BASE(ch) + 0x000)
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#define SATA_EDMA_CFG_QL128 (1 << 19)
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#define SATA_EDMA_CFG_HQCACHE (1 << 22)
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#define SATA_EDMA_IECR(ch) (SATA_EDMA_BASE(ch) + 0x008)
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#define SATA_EDMA_IEMR(ch) (SATA_EDMA_BASE(ch) + 0x00C)
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#define SATA_EDMA_REQBAHR(ch) (SATA_EDMA_BASE(ch) + 0x010)
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#define SATA_EDMA_REQIPR(ch) (SATA_EDMA_BASE(ch) + 0x014)
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#define SATA_EDMA_REQOPR(ch) (SATA_EDMA_BASE(ch) + 0x018)
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#define SATA_EDMA_RESBAHR(ch) (SATA_EDMA_BASE(ch) + 0x01C)
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#define SATA_EDMA_RESIPR(ch) (SATA_EDMA_BASE(ch) + 0x020)
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#define SATA_EDMA_RESOPR(ch) (SATA_EDMA_BASE(ch) + 0x024)
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#define SATA_EDMA_CMD(ch) (SATA_EDMA_BASE(ch) + 0x028)
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#define SATA_EDMA_CMD_ENABLE (1 << 0)
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#define SATA_EDMA_CMD_DISABLE (1 << 1)
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#define SATA_EDMA_CMD_RESET (1 << 2)
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#define SATA_EDMA_STATUS(ch) (SATA_EDMA_BASE(ch) + 0x030)
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#define SATA_EDMA_STATUS_IDLE (1 << 7)
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/* Offset to extract input slot from REQIPR register */
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#define SATA_EDMA_REQIS_OFS 5
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/* Offset to extract input slot from RESOPR register */
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#define SATA_EDMA_RESOS_OFS 3
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/*
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* GPIO
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*/
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#define GPIO_DATA_OUT 0x00
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#define GPIO_DATA_OUT_EN_CTRL 0x04
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#define GPIO_BLINK_EN 0x08
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#define GPIO_DATA_IN_POLAR 0x0c
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#define GPIO_DATA_IN 0x10
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#define GPIO_INT_CAUSE 0x14
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#define GPIO_INT_EDGE_MASK 0x18
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#define GPIO_INT_LEV_MASK 0x1c
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#define GPIO_HI_DATA_OUT 0x40
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#define GPIO_HI_DATA_OUT_EN_CTRL 0x44
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#define GPIO_HI_BLINK_EN 0x48
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#define GPIO_HI_DATA_IN_POLAR 0x4c
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#define GPIO_HI_DATA_IN 0x50
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#define GPIO_HI_INT_CAUSE 0x54
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#define GPIO_HI_INT_EDGE_MASK 0x58
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#define GPIO_HI_INT_LEV_MASK 0x5c
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#define GPIO(n) (1 << (n))
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#define MV_GPIO_MAX_NPINS 64
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#define MV_GPIO_IN_NONE 0x0
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#define MV_GPIO_IN_POL_LOW (1 << 16)
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#define MV_GPIO_IN_IRQ_EDGE (2 << 16)
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#define MV_GPIO_IN_IRQ_LEVEL (4 << 16)
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#define MV_GPIO_OUT_NONE 0x0
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#define MV_GPIO_OUT_BLINK 0x1
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#define MV_GPIO_OUT_OPEN_DRAIN 0x2
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#define MV_GPIO_OUT_OPEN_SRC 0x4
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#define IS_GPIO_IRQ(irq) ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS)
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#define GPIO2IRQ(gpio) ((gpio) + NIRQ)
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#define IRQ2GPIO(irq) ((irq) - NIRQ)
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#if defined(SOC_MV_ORION) || defined(SOC_MV_LOKIPLUS)
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#define SAMPLE_AT_RESET 0x10
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#elif defined(SOC_MV_KIRKWOOD)
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#define SAMPLE_AT_RESET 0x30
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#elif defined(SOC_MV_FREY)
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#define SAMPLE_AT_RESET 0x100
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#endif
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#if defined(SOC_MV_DISCOVERY)
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#define SAMPLE_AT_RESET_LO 0x30
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#define SAMPLE_AT_RESET_HI 0x34
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#elif defined(SOC_MV_DOVE)
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#define SAMPLE_AT_RESET_LO 0x14
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#define SAMPLE_AT_RESET_HI 0x18
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#elif defined(SOC_MV_ARMADAXP)
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#define SAMPLE_AT_RESET_LO 0x30
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#define SAMPLE_AT_RESET_HI 0x34
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#endif
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/*
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* Clocks
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*/
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#if defined(SOC_MV_ORION)
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#define TCLK_MASK 0x00000300
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#define TCLK_SHIFT 0x08
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#elif defined(SOC_MV_DISCOVERY)
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#define TCLK_MASK 0x00000180
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#define TCLK_SHIFT 0x07
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#elif defined(SOC_MV_LOKIPLUS)
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#define TCLK_MASK 0x0000F000
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#define TCLK_SHIFT 0x0C
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#endif
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#define TCLK_100MHZ 100000000
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#define TCLK_125MHZ 125000000
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#define TCLK_133MHZ 133333333
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#define TCLK_150MHZ 150000000
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#define TCLK_166MHZ 166666667
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#define TCLK_200MHZ 200000000
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#define TCLK_250MHZ 250000000
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#define TCLK_300MHZ 300000000
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#define TCLK_667MHZ 667000000
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/*
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* CPU Cache Configuration
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*/
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#define CPU_CONFIG 0x00000000
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#define CPU_CONFIG_IC_PREF 0x00010000
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#define CPU_CONFIG_DC_PREF 0x00020000
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#define CPU_CONTROL 0x00000004
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#define CPU_CONTROL_L2_SIZE 0x00200000 /* Only on Discovery */
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#define CPU_CONTROL_L2_MODE 0x00020000 /* Only on Discovery */
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#define CPU_L2_CONFIG 0x00000028 /* Only on Kirkwood */
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#define CPU_L2_CONFIG_MODE 0x00000010 /* Only on Kirkwood */
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/*
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* PCI Express port control (CPU Control registers)
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*/
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#define CPU_CONTROL_PCIE_DISABLE(n) (1 << (3 * (n)))
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/*
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* Vendor ID
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*/
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#define PCI_VENDORID_MRVL 0x11AB
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#define PCI_VENDORID_MRVL2 0x1B4B
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/*
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* Chip ID
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*/
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#define MV_DEV_88F5181 0x5181
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#define MV_DEV_88F5182 0x5182
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#define MV_DEV_88F5281 0x5281
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#define MV_DEV_88F6281 0x6281
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#define MV_DEV_88F6282 0x6282
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#define MV_DEV_88F6781 0x6781
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#define MV_DEV_MV78100_Z0 0x6381
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#define MV_DEV_MV78100 0x7810
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#define MV_DEV_MV78130 0x7813
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#define MV_DEV_MV78160 0x7816
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#define MV_DEV_MV78230 0x7823
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#define MV_DEV_MV78260 0x7826
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#define MV_DEV_MV78460 0x7846
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#define MV_DEV_88RC8180 0x8180
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#define MV_DEV_88RC9480 0x9480
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#define MV_DEV_88RC9580 0x9580
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#define MV_DEV_FAMILY_MASK 0xff00
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#define MV_DEV_DISCOVERY 0x7800
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/*
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* Doorbell register control
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*/
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#define MV_DRBL_PCIE_TO_CPU 0
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#define MV_DRBL_CPU_TO_PCIE 1
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#if defined(SOC_MV_FREY)
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#define MV_DRBL_CAUSE(d,u) (0x60 + 0x20 * (d) + 0x8 * (u))
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#define MV_DRBL_MASK(d,u) (0x60 + 0x20 * (d) + 0x8 * (u) + 0x4)
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#define MV_DRBL_MSG(m,d,u) (0x8 * (u) + 0x20 * (d) + 0x4 * (m))
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#else
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#define MV_DRBL_CAUSE(d,u) (0x10 * (u) + 0x8 * (d))
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#define MV_DRBL_MASK(d,u) (0x10 * (u) + 0x8 * (d) + 0x4)
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#define MV_DRBL_MSG(m,d,u) (0x10 * (u) + 0x8 * (d) + 0x4 * (m) + 0x30)
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#endif
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#endif /* _MVREG_H_ */
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