6ca0b78179
and provides sysctl tunables for enable/disable FPGA<->HPS bridges. Sponsored by: DARPA, AFRL
55 lines
2.8 KiB
C
55 lines
2.8 KiB
C
/*-
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* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define L3REGS_REMAP 0x0 /* Remap */
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#define REMAP_LWHPS2FPGA (1 << 4)
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#define REMAP_HPS2FPGA (1 << 3)
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#define REMAP_MPUZERO (1 << 0)
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#define L3REGS_L4MAIN 0x8 /* L4 main peripherals security */
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#define L3REGS_L4SP 0xC /* L4 SP Peripherals Security */
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#define L3REGS_L4MP 0x10 /* L4 MP Peripherals Security */
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#define L3REGS_L4OSC1 0x14 /* L4 OSC1 Peripherals Security */
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#define L3REGS_L4SPIM 0x18 /* L4 SPIM Peripherals Security */
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#define L3REGS_STM 0x1C /* STM Peripheral Security */
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#define L3REGS_LWHPS2FPGAREGS 0x20 /* LWHPS2FPGA AXI Bridge Security */
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#define L3REGS_USB1 0x28 /* USB1 Peripheral Security */
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#define L3REGS_NANDDATA 0x2C /* NAND Flash Controller Data Sec */
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#define L3REGS_USB0 0x80 /* USB0 Peripheral Security */
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#define L3REGS_NANDREGS 0x84 /* NAND Flash Controller Security */
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#define L3REGS_QSPIDATA 0x88 /* QSPI Flash Controller Data Sec */
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#define L3REGS_FPGAMGRDATA 0x8C /* FPGA Manager Data Peripheral Sec */
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#define L3REGS_HPS2FPGAREGS 0x90 /* HPS2FPGA AXI Bridge Perip. Sec */
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#define L3REGS_ACP 0x94 /* MPU ACP Peripheral Security */
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#define L3REGS_ROM 0x98 /* ROM Peripheral Security */
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#define L3REGS_OCRAM 0x9C /* On-chip RAM Peripheral Security */
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#define L3REGS_SDRDATA 0xA0 /* SDRAM Data Peripheral Security */
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