Hidetoshi Shimokawa 73aa55ba0a - The payload of Write Request Quad and Read Response Quad must be ...

network byte order.
- Set ATRetries register after each bus reset because the value is 'undef'
	in OHCI spec.

2003-03-24 04:06:21 +00:00

..

00README

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firewire_phy.h

…

firewire.c

MFp4(simokawa_sbp)

2003-03-06 05:06:44 +00:00

firewire.h

MFp4(simokawa_sbp)

2003-03-06 05:06:44 +00:00

firewirereg.h

MFp4(simokawa_sbp)

2003-03-06 05:06:44 +00:00

fwcrom.c

- Handle zero sized directory right way.

2003-01-04 10:32:31 +00:00

fwdev.c

MFp4(simokawa_sbp)

2003-03-06 05:06:44 +00:00

fwmem.c

- The payload of Write Request Quad and Read Response Quad must be

2003-03-24 04:06:21 +00:00

fwmem.h

- Implement write part.

2003-02-04 17:09:59 +00:00

fwohci_pci.c

Safe PCI configuration.

2003-03-24 03:47:36 +00:00

fwohci.c

- The payload of Write Request Quad and Read Response Quad must be

2003-03-24 04:06:21 +00:00

fwohcireg.h

Use pci_get_devid().

2003-02-18 10:01:44 +00:00

fwohcivar.h

function name change.

2003-01-31 14:14:45 +00:00

iec13213.h

- Add more CSR related definitions (IEEE-1212).

2002-12-30 09:41:32 +00:00

iec68113.h

Fix typo

2003-02-21 02:09:39 +00:00

if_fwe.c

Clear channel and tag bits before set them.

2003-03-19 07:04:11 +00:00

if_fwevar.h

MFp4(simokawa_sbp)

2003-03-06 05:06:44 +00:00

sbp.c

Put back including sys/devicestat.h for 4-stable.

2003-03-12 10:36:53 +00:00