331 lines
7.1 KiB
C
331 lines
7.1 KiB
C
/* $NetBSD: db_interface.c,v 1.33 2003/08/25 04:51:10 mrg Exp $ */
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/*-
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* Copyright (c) 1996 Scott K. Stevens
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*
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* Mach Operating System
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* Copyright (c) 1991,1990 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
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* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*
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* From: db_interface.c,v 2.4 1991/02/05 17:11:13 mrt (CMU)
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*/
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/*
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* Interface to new debugger.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/proc.h>
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#include <sys/reboot.h>
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#include <sys/systm.h> /* just for boothowto */
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#include <sys/exec.h>
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#ifdef KDB
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#include <sys/kdb.h>
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#endif
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <vm/vm_map.h>
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#include <vm/vm_extern.h>
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#include <machine/db_machdep.h>
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#include <machine/machdep.h>
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#include <machine/vmparam.h>
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#include <machine/cpu.h>
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#include <ddb/ddb.h>
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#include <ddb/db_access.h>
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#include <ddb/db_command.h>
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#include <ddb/db_output.h>
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#include <ddb/db_variables.h>
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#include <ddb/db_sym.h>
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#include <sys/cons.h>
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static int nil = 0;
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int db_access_und_sp (struct db_variable *, db_expr_t *, int);
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int db_access_abt_sp (struct db_variable *, db_expr_t *, int);
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int db_access_irq_sp (struct db_variable *, db_expr_t *, int);
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static db_varfcn_t db_frame;
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#define DB_OFFSET(x) (db_expr_t *)offsetof(struct trapframe, x)
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struct db_variable db_regs[] = {
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{ "spsr", DB_OFFSET(tf_spsr), db_frame },
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{ "r0", DB_OFFSET(tf_r0), db_frame },
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{ "r1", DB_OFFSET(tf_r1), db_frame },
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{ "r2", DB_OFFSET(tf_r2), db_frame },
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{ "r3", DB_OFFSET(tf_r3), db_frame },
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{ "r4", DB_OFFSET(tf_r4), db_frame },
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{ "r5", DB_OFFSET(tf_r5), db_frame },
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{ "r6", DB_OFFSET(tf_r6), db_frame },
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{ "r7", DB_OFFSET(tf_r7), db_frame },
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{ "r8", DB_OFFSET(tf_r8), db_frame },
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{ "r9", DB_OFFSET(tf_r9), db_frame },
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{ "r10", DB_OFFSET(tf_r10), db_frame },
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{ "r11", DB_OFFSET(tf_r11), db_frame },
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{ "r12", DB_OFFSET(tf_r12), db_frame },
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{ "usr_sp", DB_OFFSET(tf_usr_sp), db_frame },
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{ "usr_lr", DB_OFFSET(tf_usr_lr), db_frame },
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{ "svc_sp", DB_OFFSET(tf_svc_sp), db_frame },
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{ "svc_lr", DB_OFFSET(tf_svc_lr), db_frame },
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{ "pc", DB_OFFSET(tf_pc), db_frame },
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{ "und_sp", &nil, db_access_und_sp, },
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{ "abt_sp", &nil, db_access_abt_sp, },
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{ "irq_sp", &nil, db_access_irq_sp, },
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};
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struct db_variable *db_eregs = db_regs + sizeof(db_regs)/sizeof(db_regs[0]);
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int
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db_access_und_sp(struct db_variable *vp, db_expr_t *valp, int rw)
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{
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if (rw == DB_VAR_GET) {
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*valp = get_stackptr(PSR_UND32_MODE);
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return (1);
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}
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return (0);
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}
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int
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db_access_abt_sp(struct db_variable *vp, db_expr_t *valp, int rw)
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{
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if (rw == DB_VAR_GET) {
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*valp = get_stackptr(PSR_ABT32_MODE);
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return (1);
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}
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return (0);
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}
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int
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db_access_irq_sp(struct db_variable *vp, db_expr_t *valp, int rw)
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{
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if (rw == DB_VAR_GET) {
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*valp = get_stackptr(PSR_IRQ32_MODE);
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return (1);
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}
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return (0);
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}
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int db_frame(struct db_variable *vp, db_expr_t *valp, int rw)
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{
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int *reg;
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if (kdb_frame == NULL)
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return (0);
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reg = (int *)((uintptr_t)kdb_frame + (db_expr_t)vp->valuep);
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if (rw == DB_VAR_GET)
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*valp = *reg;
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else
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*reg = *valp;
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return (1);
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}
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void
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db_show_mdpcpu(struct pcpu *pc)
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{
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#if __ARM_ARCH >= 6
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db_printf("curpmap = %p\n", pc->pc_curpmap);
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#endif
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}
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int
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db_validate_address(vm_offset_t addr)
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{
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struct proc *p = curproc;
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struct pmap *pmap;
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if (!p || !p->p_vmspace || !p->p_vmspace->vm_map.pmap ||
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#ifndef ARM32_NEW_VM_LAYOUT
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addr >= VM_MAXUSER_ADDRESS
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#else
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addr >= VM_MIN_KERNEL_ADDRESS
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#endif
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)
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pmap = kernel_pmap;
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else
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pmap = p->p_vmspace->vm_map.pmap;
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return (pmap_extract(pmap, addr) == FALSE);
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}
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/*
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* Read bytes from kernel address space for debugger.
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*/
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int
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db_read_bytes(addr, size, data)
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vm_offset_t addr;
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size_t size;
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char *data;
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{
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char *src = (char *)addr;
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if (db_validate_address((u_int)src)) {
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db_printf("address %p is invalid\n", src);
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return (-1);
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}
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if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) {
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*((int*)data) = *((int*)src);
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return (0);
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}
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if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) {
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*((short*)data) = *((short*)src);
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return (0);
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}
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while (size-- > 0) {
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if (db_validate_address((u_int)src)) {
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db_printf("address %p is invalid\n", src);
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return (-1);
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}
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*data++ = *src++;
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}
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return (0);
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}
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/*
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* Write bytes to kernel address space for debugger.
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*/
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int
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db_write_bytes(vm_offset_t addr, size_t size, char *data)
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{
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char *dst;
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size_t loop;
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dst = (char *)addr;
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if (db_validate_address((u_int)dst)) {
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db_printf("address %p is invalid\n", dst);
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return (0);
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}
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if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0)
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*((int*)dst) = *((int*)data);
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else
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if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0)
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*((short*)dst) = *((short*)data);
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else {
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loop = size;
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while (loop-- > 0) {
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if (db_validate_address((u_int)dst)) {
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db_printf("address %p is invalid\n", dst);
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return (-1);
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}
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*dst++ = *data++;
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}
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}
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/* make sure the caches and memory are in sync */
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cpu_icache_sync_range(addr, size);
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/* In case the current page tables have been modified ... */
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cpu_tlb_flushID();
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cpu_cpwait();
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return (0);
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}
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static u_int
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db_fetch_reg(int reg)
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{
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switch (reg) {
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case 0:
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return (kdb_frame->tf_r0);
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case 1:
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return (kdb_frame->tf_r1);
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case 2:
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return (kdb_frame->tf_r2);
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case 3:
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return (kdb_frame->tf_r3);
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case 4:
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return (kdb_frame->tf_r4);
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case 5:
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return (kdb_frame->tf_r5);
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case 6:
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return (kdb_frame->tf_r6);
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case 7:
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return (kdb_frame->tf_r7);
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case 8:
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return (kdb_frame->tf_r8);
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case 9:
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return (kdb_frame->tf_r9);
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case 10:
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return (kdb_frame->tf_r10);
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case 11:
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return (kdb_frame->tf_r11);
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case 12:
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return (kdb_frame->tf_r12);
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case 13:
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return (kdb_frame->tf_svc_sp);
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case 14:
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return (kdb_frame->tf_svc_lr);
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case 15:
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return (kdb_frame->tf_pc);
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default:
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panic("db_fetch_reg: botch");
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}
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}
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static u_int
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db_branch_taken_read_int(void *cookie __unused, vm_offset_t offset, u_int *val)
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{
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u_int ret;
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db_read_bytes(offset, 4, (char *)&ret);
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*val = ret;
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return (0);
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}
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static u_int
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db_branch_taken_fetch_reg(void *cookie __unused, int reg)
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{
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return (db_fetch_reg(reg));
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}
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u_int
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branch_taken(u_int insn, db_addr_t pc)
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{
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register_t new_pc;
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int ret;
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ret = arm_predict_branch(NULL, insn, (register_t)pc, &new_pc,
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db_branch_taken_fetch_reg, db_branch_taken_read_int);
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if (ret != 0)
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kdb_reenter();
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return (new_pc);
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}
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