748 lines
21 KiB
C
748 lines
21 KiB
C
/*-
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* Copyright 2007-2009 Solarflare Communications Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _SYS_EFX_IMPL_H
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#define _SYS_EFX_IMPL_H
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#include "efsys.h"
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#include "efx.h"
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#include "efx_regs.h"
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#if EFSYS_OPT_FALCON
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#include "falcon_impl.h"
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#endif /* EFSYS_OPT_FALCON */
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#if EFSYS_OPT_SIENA
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#include "siena_impl.h"
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#endif /* EFSYS_OPT_SIENA */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define EFX_MOD_MCDI 0x00000001
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#define EFX_MOD_PROBE 0x00000002
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#define EFX_MOD_NVRAM 0x00000004
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#define EFX_MOD_VPD 0x00000008
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#define EFX_MOD_NIC 0x00000010
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#define EFX_MOD_INTR 0x00000020
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#define EFX_MOD_EV 0x00000040
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#define EFX_MOD_RX 0x00000080
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#define EFX_MOD_TX 0x00000100
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#define EFX_MOD_PORT 0x00000200
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#define EFX_MOD_MON 0x00000400
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#define EFX_MOD_WOL 0x00000800
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#define EFX_MOD_FILTER 0x00001000
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#define EFX_RESET_MAC 0x00000001
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#define EFX_RESET_PHY 0x00000002
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typedef enum efx_mac_type_e {
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EFX_MAC_INVALID = 0,
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EFX_MAC_FALCON_GMAC,
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EFX_MAC_FALCON_XMAC,
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EFX_MAC_SIENA,
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EFX_MAC_NTYPES
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} efx_mac_type_t;
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typedef struct efx_mac_ops_s {
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int (*emo_reset)(efx_nic_t *); /* optional */
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int (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
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int (*emo_up)(efx_nic_t *, boolean_t *);
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int (*emo_reconfigure)(efx_nic_t *);
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#if EFSYS_OPT_LOOPBACK
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int (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
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efx_loopback_type_t);
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#endif /* EFSYS_OPT_LOOPBACK */
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#if EFSYS_OPT_MAC_STATS
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int (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
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int (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
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uint16_t, boolean_t);
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int (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
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efsys_stat_t *, uint32_t *);
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#endif /* EFSYS_OPT_MAC_STATS */
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} efx_mac_ops_t;
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typedef struct efx_phy_ops_s {
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int (*epo_power)(efx_nic_t *, boolean_t); /* optional */
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int (*epo_reset)(efx_nic_t *);
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int (*epo_reconfigure)(efx_nic_t *);
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int (*epo_verify)(efx_nic_t *);
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int (*epo_uplink_check)(efx_nic_t *,
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boolean_t *); /* optional */
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int (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *,
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unsigned int *, uint32_t *);
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int (*epo_oui_get)(efx_nic_t *, uint32_t *);
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#if EFSYS_OPT_PHY_STATS
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int (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
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uint32_t *);
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#endif /* EFSYS_OPT_PHY_STATS */
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#if EFSYS_OPT_PHY_PROPS
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#if EFSYS_OPT_NAMES
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const char __cs *(*epo_prop_name)(efx_nic_t *, unsigned int);
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#endif /* EFSYS_OPT_PHY_PROPS */
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int (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t,
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uint32_t *);
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int (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t);
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#endif /* EFSYS_OPT_PHY_PROPS */
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#if EFSYS_OPT_PHY_BIST
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int (*epo_bist_start)(efx_nic_t *, efx_phy_bist_type_t);
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int (*epo_bist_poll)(efx_nic_t *, efx_phy_bist_type_t,
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efx_phy_bist_result_t *, uint32_t *,
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unsigned long *, size_t);
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void (*epo_bist_stop)(efx_nic_t *, efx_phy_bist_type_t);
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#endif /* EFSYS_OPT_PHY_BIST */
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} efx_phy_ops_t;
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typedef struct efx_port_s {
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efx_mac_type_t ep_mac_type;
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uint32_t ep_phy_type;
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uint8_t ep_port;
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uint32_t ep_mac_pdu;
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uint8_t ep_mac_addr[6];
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efx_link_mode_t ep_link_mode;
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boolean_t ep_unicst;
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boolean_t ep_brdcst;
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unsigned int ep_fcntl;
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boolean_t ep_fcntl_autoneg;
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efx_oword_t ep_multicst_hash[2];
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#if EFSYS_OPT_LOOPBACK
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efx_loopback_type_t ep_loopback_type;
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efx_link_mode_t ep_loopback_link_mode;
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#endif /* EFSYS_OPT_LOOPBACK */
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#if EFSYS_OPT_PHY_FLAGS
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uint32_t ep_phy_flags;
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#endif /* EFSYS_OPT_PHY_FLAGS */
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#if EFSYS_OPT_PHY_LED_CONTROL
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efx_phy_led_mode_t ep_phy_led_mode;
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#endif /* EFSYS_OPT_PHY_LED_CONTROL */
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efx_phy_media_type_t ep_fixed_port_type;
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efx_phy_media_type_t ep_module_type;
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uint32_t ep_adv_cap_mask;
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uint32_t ep_lp_cap_mask;
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uint32_t ep_default_adv_cap_mask;
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uint32_t ep_phy_cap_mask;
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#if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C
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union {
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struct {
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unsigned int bug10934_count;
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} ep_txc43128;
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struct {
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unsigned int bug17190_count;
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} ep_qt2025c;
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};
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#endif
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boolean_t ep_mac_poll_needed; /* falcon only */
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boolean_t ep_mac_up; /* falcon only */
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uint32_t ep_fwver; /* falcon only */
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boolean_t ep_mac_drain;
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boolean_t ep_mac_stats_pending;
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#if EFSYS_OPT_PHY_BIST
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efx_phy_bist_type_t ep_current_bist;
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#endif
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efx_mac_ops_t *ep_emop;
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efx_phy_ops_t *ep_epop;
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} efx_port_t;
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typedef struct efx_mon_ops_s {
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int (*emo_reset)(efx_nic_t *);
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int (*emo_reconfigure)(efx_nic_t *);
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#if EFSYS_OPT_MON_STATS
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int (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
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efx_mon_stat_value_t *);
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#endif /* EFSYS_OPT_MON_STATS */
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} efx_mon_ops_t;
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typedef struct efx_mon_s {
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efx_mon_type_t em_type;
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efx_mon_ops_t *em_emop;
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} efx_mon_t;
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typedef struct efx_intr_s {
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efx_intr_type_t ei_type;
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efsys_mem_t *ei_esmp;
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unsigned int ei_level;
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} efx_intr_t;
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typedef struct efx_nic_ops_s {
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int (*eno_probe)(efx_nic_t *);
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int (*eno_reset)(efx_nic_t *);
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int (*eno_init)(efx_nic_t *);
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#if EFSYS_OPT_DIAG
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int (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t);
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int (*eno_register_test)(efx_nic_t *);
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#endif /* EFSYS_OPT_DIAG */
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void (*eno_fini)(efx_nic_t *);
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void (*eno_unprobe)(efx_nic_t *);
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} efx_nic_ops_t;
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#ifndef EFX_TXQ_LIMIT_TARGET
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# define EFX_TXQ_LIMIT_TARGET 259
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#endif
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#ifndef EFX_RXQ_LIMIT_TARGET
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# define EFX_RXQ_LIMIT_TARGET 512
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#endif
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#ifndef EFX_TXQ_DC_SIZE
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#define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
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#endif
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#ifndef EFX_RXQ_DC_SIZE
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#define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
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#endif
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#if EFSYS_OPT_FILTER
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typedef enum efx_filter_type_e {
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EFX_FILTER_RX_TCP_FULL, /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */
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EFX_FILTER_RX_TCP_WILD, /* TCP/IPv4 dest {dIP,dTCP, -, -} */
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EFX_FILTER_RX_UDP_FULL, /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */
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EFX_FILTER_RX_UDP_WILD, /* UDP/IPv4 dest {dIP,dUDP, -, -} */
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#if EFSYS_OPT_SIENA
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EFX_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
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EFX_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
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EFX_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
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EFX_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
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EFX_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
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EFX_FILTER_TX_UDP_WILD, /* UDP/IPv4 source (host, port) */
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EFX_FILTER_TX_MAC_FULL, /* Ethernet source (MAC address, VLAN ID) */
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EFX_FILTER_TX_MAC_WILD, /* Ethernet source (MAC address) */
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#endif /* EFSYS_OPT_SIENA */
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EFX_FILTER_NTYPES
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} efx_filter_type_t;
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typedef enum efx_filter_tbl_id_e {
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EFX_FILTER_TBL_RX_IP = 0,
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EFX_FILTER_TBL_RX_MAC,
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EFX_FILTER_TBL_TX_IP,
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EFX_FILTER_TBL_TX_MAC,
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EFX_FILTER_NTBLS
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} efx_filter_tbl_id_t;
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typedef struct efx_filter_tbl_s {
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int eft_size; /* number of entries */
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int eft_used; /* active count */
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uint32_t *eft_bitmap; /* active bitmap */
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efx_filter_spec_t *eft_spec; /* array of saved specs */
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} efx_filter_tbl_t;
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typedef struct efx_filter_s {
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efx_filter_tbl_t ef_tbl[EFX_FILTER_NTBLS];
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unsigned int ef_depth[EFX_FILTER_NTYPES];
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} efx_filter_t;
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extern __checkReturn int
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efx_filter_insert_filter(
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__in efx_nic_t *enp,
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__in efx_filter_spec_t *spec,
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__in boolean_t replace);
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extern __checkReturn int
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efx_filter_remove_filter(
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__in efx_nic_t *enp,
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__in efx_filter_spec_t *spec);
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extern void
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efx_filter_remove_index(
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__inout efx_nic_t *enp,
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__in efx_filter_type_t type,
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__in int filter_idx);
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extern void
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efx_filter_redirect_index(
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__inout efx_nic_t *enp,
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__in efx_filter_type_t type,
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__in int filter_index,
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__in int rxq_index);
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extern __checkReturn int
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efx_filter_clear_tbl(
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__in efx_nic_t *enp,
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__in efx_filter_tbl_id_t tbl);
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#endif /* EFSYS_OPT_FILTER */
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#if EFSYS_OPT_NVRAM
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typedef struct efx_nvram_ops_s {
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#if EFSYS_OPT_DIAG
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int (*envo_test)(efx_nic_t *);
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#endif /* EFSYS_OPT_DIAG */
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int (*envo_size)(efx_nic_t *, efx_nvram_type_t, size_t *);
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int (*envo_get_version)(efx_nic_t *, efx_nvram_type_t,
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uint32_t *, uint16_t *);
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int (*envo_rw_start)(efx_nic_t *, efx_nvram_type_t, size_t *);
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int (*envo_read_chunk)(efx_nic_t *, efx_nvram_type_t,
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unsigned int, caddr_t, size_t);
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int (*envo_erase)(efx_nic_t *, efx_nvram_type_t);
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int (*envo_write_chunk)(efx_nic_t *, efx_nvram_type_t,
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unsigned int, caddr_t, size_t);
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void (*envo_rw_finish)(efx_nic_t *, efx_nvram_type_t);
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int (*envo_set_version)(efx_nic_t *, efx_nvram_type_t, uint16_t *);
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} efx_nvram_ops_t;
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#endif /* EFSYS_OPT_NVRAM */
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#if EFSYS_OPT_VPD
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typedef struct efx_vpd_ops_s {
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int (*evpdo_init)(efx_nic_t *);
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int (*evpdo_size)(efx_nic_t *, size_t *);
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int (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
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int (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
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int (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
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int (*evpdo_get)(efx_nic_t *, caddr_t, size_t, efx_vpd_value_t *);
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int (*evpdo_set)(efx_nic_t *, caddr_t, size_t, efx_vpd_value_t *);
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int (*evpdo_next)(efx_nic_t *, caddr_t, size_t, efx_vpd_value_t *,
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unsigned int *);
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int (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
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void (*evpdo_fini)(efx_nic_t *);
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} efx_vpd_ops_t;
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#endif /* EFSYS_OPT_VPD */
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struct efx_nic_s {
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uint32_t en_magic;
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efx_family_t en_family;
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uint32_t en_features;
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efsys_identifier_t *en_esip;
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efsys_lock_t *en_eslp;
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efsys_bar_t *en_esbp;
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unsigned int en_mod_flags;
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unsigned int en_reset_flags;
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efx_nic_cfg_t en_nic_cfg;
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efx_port_t en_port;
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efx_mon_t en_mon;
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efx_intr_t en_intr;
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uint32_t en_ev_qcount;
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uint32_t en_rx_qcount;
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uint32_t en_tx_qcount;
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efx_nic_ops_t *en_enop;
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#if EFSYS_OPT_FILTER
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efx_filter_t en_filter;
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#endif /* EFSYS_OPT_FILTER */
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#if EFSYS_OPT_NVRAM
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efx_nvram_type_t en_nvram_locked;
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efx_nvram_ops_t *en_envop;
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#endif /* EFSYS_OPT_NVRAM */
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#if EFSYS_OPT_VPD
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efx_vpd_ops_t *en_evpdop;
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#endif /* EFSYS_OPT_VPD */
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union {
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#if EFSYS_OPT_FALCON
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struct {
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falcon_spi_dev_t enu_fsd[FALCON_SPI_NTYPES];
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falcon_i2c_t enu_fip;
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boolean_t enu_i2c_locked;
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#if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE
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const uint8_t *enu_forced_cfg;
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#endif /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */
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uint8_t enu_mon_devid;
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#if EFSYS_OPT_PCIE_TUNE
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unsigned int enu_nlanes;
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#endif /* EFSYS_OPT_PCIE_TUNE */
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uint16_t enu_board_rev;
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boolean_t enu_internal_sram;
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uint8_t enu_sram_num_bank;
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uint8_t enu_sram_bank_size;
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} falcon;
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#endif /* EFSYS_OPT_FALCON */
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#if EFSYS_OPT_SIENA
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struct {
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#if EFSYS_OPT_MCDI
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efx_mcdi_iface_t enu_mip;
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#endif /* EFSYS_OPT_MCDI */
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#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
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unsigned int enu_partn_mask;
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#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
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#if EFSYS_OPT_VPD
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caddr_t enu_svpd;
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size_t enu_svpd_length;
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#endif /* EFSYS_OPT_VPD */
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} siena;
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#endif /* EFSYS_OPT_SIENA */
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} en_u;
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};
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#define EFX_NIC_MAGIC 0x02121996
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typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
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const efx_ev_callbacks_t *, void *);
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struct efx_evq_s {
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uint32_t ee_magic;
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efx_nic_t *ee_enp;
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unsigned int ee_index;
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unsigned int ee_mask;
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efsys_mem_t *ee_esmp;
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#if EFSYS_OPT_QSTATS
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uint32_t ee_stat[EV_NQSTATS];
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#endif /* EFSYS_OPT_QSTATS */
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efx_ev_handler_t ee_handler[1 << FSF_AZ_EV_CODE_WIDTH];
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};
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#define EFX_EVQ_MAGIC 0x08081997
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#define EFX_EVQ_FALCON_TIMER_QUANTUM_NS 4968 /* 621 cycles */
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#define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
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struct efx_rxq_s {
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uint32_t er_magic;
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efx_nic_t *er_enp;
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unsigned int er_index;
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unsigned int er_mask;
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efsys_mem_t *er_esmp;
|
|
};
|
|
|
|
#define EFX_RXQ_MAGIC 0x15022005
|
|
|
|
struct efx_txq_s {
|
|
uint32_t et_magic;
|
|
efx_nic_t *et_enp;
|
|
unsigned int et_index;
|
|
unsigned int et_mask;
|
|
efsys_mem_t *et_esmp;
|
|
#if EFSYS_OPT_QSTATS
|
|
uint32_t et_stat[TX_NQSTATS];
|
|
#endif /* EFSYS_OPT_QSTATS */
|
|
};
|
|
|
|
#define EFX_TXQ_MAGIC 0x05092005
|
|
|
|
#define EFX_MAC_ADDR_COPY(_dst, _src) \
|
|
do { \
|
|
(_dst)[0] = (_src)[0]; \
|
|
(_dst)[1] = (_src)[1]; \
|
|
(_dst)[2] = (_src)[2]; \
|
|
(_dst)[3] = (_src)[3]; \
|
|
(_dst)[4] = (_src)[4]; \
|
|
(_dst)[5] = (_src)[5]; \
|
|
_NOTE(CONSTANTCONDITION) \
|
|
} while (B_FALSE)
|
|
|
|
#if EFSYS_OPT_CHECK_REG
|
|
#define EFX_CHECK_REG(_enp, _reg) \
|
|
do { \
|
|
const char __cs *name = #_reg; \
|
|
char min = name[4]; \
|
|
char max = name[5]; \
|
|
char rev; \
|
|
\
|
|
switch ((_enp)->en_family) { \
|
|
case EFX_FAMILY_FALCON: \
|
|
rev = 'B'; \
|
|
break; \
|
|
\
|
|
case EFX_FAMILY_SIENA: \
|
|
rev = 'C'; \
|
|
break; \
|
|
\
|
|
default: \
|
|
rev = '?'; \
|
|
break; \
|
|
} \
|
|
\
|
|
EFSYS_ASSERT3S(rev, >=, min); \
|
|
EFSYS_ASSERT3S(rev, <=, max); \
|
|
\
|
|
_NOTE(CONSTANTCONDITION) \
|
|
} while (B_FALSE)
|
|
#else
|
|
#define EFX_CHECK_REG(_enp, _reg) do { \
|
|
_NOTE(CONSTANTCONDITION) \
|
|
} while(B_FALSE)
|
|
#endif
|
|
|
|
#define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
|
|
do { \
|
|
EFX_CHECK_REG((_enp), (_reg)); \
|
|
EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
|
|
(_edp), (_lock)); \
|
|
EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
|
|
uint32_t, _reg ## _OFST, \
|
|
uint32_t, (_edp)->ed_u32[0]); \
|
|
_NOTE(CONSTANTCONDITION) \
|
|
} while (B_FALSE)
|
|
|
|
#define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
|
|
do { \
|
|
EFX_CHECK_REG((_enp), (_reg)); \
|
|
EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
|
|
uint32_t, _reg ## _OFST, \
|
|
uint32_t, (_edp)->ed_u32[0]); \
|
|
EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
|
|
(_edp), (_lock)); \
|
|
_NOTE(CONSTANTCONDITION) \
|
|
} while (B_FALSE)
|
|
|
|
#define EFX_BAR_READQ(_enp, _reg, _eqp) \
|
|
do { \
|
|
EFX_CHECK_REG((_enp), (_reg)); \
|
|
EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
|
|
(_eqp)); \
|
|
EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
|
|
uint32_t, _reg ## _OFST, \
|
|
uint32_t, (_eqp)->eq_u32[1], \
|
|
uint32_t, (_eqp)->eq_u32[0]); \
|
|
_NOTE(CONSTANTCONDITION) \
|
|
} while (B_FALSE)
|
|
|
|
#define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
|
|
do { \
|
|
EFX_CHECK_REG((_enp), (_reg)); \
|
|
EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
|
|
uint32_t, _reg ## _OFST, \
|
|
uint32_t, (_eqp)->eq_u32[1], \
|
|
uint32_t, (_eqp)->eq_u32[0]); \
|
|
EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
|
|
(_eqp)); \
|
|
_NOTE(CONSTANTCONDITION) \
|
|
} while (B_FALSE)
|
|
|
|
#define EFX_BAR_READO(_enp, _reg, _eop) \
|
|
do { \
|
|
EFX_CHECK_REG((_enp), (_reg)); \
|
|
EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
|
|
(_eop), B_TRUE); \
|
|
EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
|
|
uint32_t, _reg ## _OFST, \
|
|
uint32_t, (_eop)->eo_u32[3], \
|
|
uint32_t, (_eop)->eo_u32[2], \
|
|
uint32_t, (_eop)->eo_u32[1], \
|
|
uint32_t, (_eop)->eo_u32[0]); \
|
|
_NOTE(CONSTANTCONDITION) \
|
|
} while (B_FALSE)
|
|
|
|
#define EFX_BAR_WRITEO(_enp, _reg, _eop) \
|
|
do { \
|
|
EFX_CHECK_REG((_enp), (_reg)); \
|
|
EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
|
|
uint32_t, _reg ## _OFST, \
|
|
uint32_t, (_eop)->eo_u32[3], \
|
|
uint32_t, (_eop)->eo_u32[2], \
|
|
uint32_t, (_eop)->eo_u32[1], \
|
|
uint32_t, (_eop)->eo_u32[0]); \
|
|
EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
|
|
(_eop), B_TRUE); \
|
|
_NOTE(CONSTANTCONDITION) \
|
|
} while (B_FALSE)
|
|
|
|
#define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
|
|
do { \
|
|
EFX_CHECK_REG((_enp), (_reg)); \
|
|
EFSYS_BAR_READD((_enp)->en_esbp, \
|
|
(_reg ## _OFST + ((_index) * _reg ## _STEP)), \
|
|
(_edp), (_lock)); \
|
|
EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
|
|
uint32_t, (_index), \
|
|
uint32_t, _reg ## _OFST, \
|
|
uint32_t, (_edp)->ed_u32[0]); \
|
|
_NOTE(CONSTANTCONDITION) \
|
|
} while (B_FALSE)
|
|
|
|
#define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
|
|
do { \
|
|
EFX_CHECK_REG((_enp), (_reg)); \
|
|
EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
|
|
uint32_t, (_index), \
|
|
uint32_t, _reg ## _OFST, \
|
|
uint32_t, (_edp)->ed_u32[0]); \
|
|
EFSYS_BAR_WRITED((_enp)->en_esbp, \
|
|
(_reg ## _OFST + ((_index) * _reg ## _STEP)), \
|
|
(_edp), (_lock)); \
|
|
_NOTE(CONSTANTCONDITION) \
|
|
} while (B_FALSE)
|
|
|
|
#define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
|
|
do { \
|
|
EFX_CHECK_REG((_enp), (_reg)); \
|
|
EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
|
|
uint32_t, (_index), \
|
|
uint32_t, _reg ## _OFST, \
|
|
uint32_t, (_edp)->ed_u32[0]); \
|
|
EFSYS_BAR_WRITED((_enp)->en_esbp, \
|
|
(_reg ## _OFST + \
|
|
(3 * sizeof (efx_dword_t)) + \
|
|
((_index) * _reg ## _STEP)), \
|
|
(_edp), (_lock)); \
|
|
_NOTE(CONSTANTCONDITION) \
|
|
} while (B_FALSE)
|
|
|
|
#define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
|
|
do { \
|
|
EFX_CHECK_REG((_enp), (_reg)); \
|
|
EFSYS_BAR_READQ((_enp)->en_esbp, \
|
|
(_reg ## _OFST + ((_index) * _reg ## _STEP)), \
|
|
(_eqp)); \
|
|
EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
|
|
uint32_t, (_index), \
|
|
uint32_t, _reg ## _OFST, \
|
|
uint32_t, (_eqp)->eq_u32[1], \
|
|
uint32_t, (_eqp)->eq_u32[0]); \
|
|
_NOTE(CONSTANTCONDITION) \
|
|
} while (B_FALSE)
|
|
|
|
#define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
|
|
do { \
|
|
EFX_CHECK_REG((_enp), (_reg)); \
|
|
EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
|
|
uint32_t, (_index), \
|
|
uint32_t, _reg ## _OFST, \
|
|
uint32_t, (_eqp)->eq_u32[1], \
|
|
uint32_t, (_eqp)->eq_u32[0]); \
|
|
EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
|
|
(_reg ## _OFST + ((_index) * _reg ## _STEP)), \
|
|
(_eqp)); \
|
|
_NOTE(CONSTANTCONDITION) \
|
|
} while (B_FALSE)
|
|
|
|
#define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop) \
|
|
do { \
|
|
EFX_CHECK_REG((_enp), (_reg)); \
|
|
EFSYS_BAR_READO((_enp)->en_esbp, \
|
|
(_reg ## _OFST + ((_index) * _reg ## _STEP)), \
|
|
(_eop), B_TRUE); \
|
|
EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
|
|
uint32_t, (_index), \
|
|
uint32_t, _reg ## _OFST, \
|
|
uint32_t, (_eop)->eo_u32[3], \
|
|
uint32_t, (_eop)->eo_u32[2], \
|
|
uint32_t, (_eop)->eo_u32[1], \
|
|
uint32_t, (_eop)->eo_u32[0]); \
|
|
_NOTE(CONSTANTCONDITION) \
|
|
} while (B_FALSE)
|
|
|
|
#define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop) \
|
|
do { \
|
|
EFX_CHECK_REG((_enp), (_reg)); \
|
|
EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
|
|
uint32_t, (_index), \
|
|
uint32_t, _reg ## _OFST, \
|
|
uint32_t, (_eop)->eo_u32[3], \
|
|
uint32_t, (_eop)->eo_u32[2], \
|
|
uint32_t, (_eop)->eo_u32[1], \
|
|
uint32_t, (_eop)->eo_u32[0]); \
|
|
EFSYS_BAR_WRITEO((_enp)->en_esbp, \
|
|
(_reg ## _OFST + ((_index) * _reg ## _STEP)), \
|
|
(_eop), B_TRUE); \
|
|
_NOTE(CONSTANTCONDITION) \
|
|
} while (B_FALSE)
|
|
|
|
extern __checkReturn int
|
|
efx_mac_select(
|
|
__in efx_nic_t *enp);
|
|
|
|
extern __checkReturn int
|
|
efx_phy_probe(
|
|
__in efx_nic_t *enp);
|
|
|
|
extern void
|
|
efx_phy_unprobe(
|
|
__in efx_nic_t *enp);
|
|
|
|
#if EFSYS_OPT_VPD
|
|
|
|
/* VPD utility functions */
|
|
|
|
extern __checkReturn int
|
|
efx_vpd_hunk_length(
|
|
__in_bcount(size) caddr_t data,
|
|
__in size_t size,
|
|
__out size_t *lengthp);
|
|
|
|
extern __checkReturn int
|
|
efx_vpd_hunk_verify(
|
|
__in_bcount(size) caddr_t data,
|
|
__in size_t size,
|
|
__out_opt boolean_t *cksummedp);
|
|
|
|
extern __checkReturn int
|
|
efx_vpd_hunk_reinit(
|
|
__in caddr_t data,
|
|
__in size_t size,
|
|
__in boolean_t wantpid);
|
|
|
|
extern __checkReturn int
|
|
efx_vpd_hunk_get(
|
|
__in_bcount(size) caddr_t data,
|
|
__in size_t size,
|
|
__in efx_vpd_tag_t tag,
|
|
__in efx_vpd_keyword_t keyword,
|
|
__out unsigned int *payloadp,
|
|
__out uint8_t *paylenp);
|
|
|
|
extern __checkReturn int
|
|
efx_vpd_hunk_next(
|
|
__in_bcount(size) caddr_t data,
|
|
__in size_t size,
|
|
__out efx_vpd_tag_t *tagp,
|
|
__out efx_vpd_keyword_t *keyword,
|
|
__out_bcount_opt(*paylenp) unsigned int *payloadp,
|
|
__out_opt uint8_t *paylenp,
|
|
__inout unsigned int *contp);
|
|
|
|
extern __checkReturn int
|
|
efx_vpd_hunk_set(
|
|
__in_bcount(size) caddr_t data,
|
|
__in size_t size,
|
|
__in efx_vpd_value_t *evvp);
|
|
|
|
#endif /* EFSYS_OPT_VPD */
|
|
|
|
#if EFSYS_OPT_DIAG
|
|
|
|
extern efx_sram_pattern_fn_t __cs __efx_sram_pattern_fns[];
|
|
|
|
typedef struct efx_register_set_s {
|
|
unsigned int address;
|
|
unsigned int step;
|
|
unsigned int rows;
|
|
efx_oword_t mask;
|
|
} efx_register_set_t;
|
|
|
|
extern __checkReturn int
|
|
efx_nic_test_registers(
|
|
__in efx_nic_t *enp,
|
|
__in efx_register_set_t *rsp,
|
|
__in size_t count);
|
|
|
|
extern __checkReturn int
|
|
efx_nic_test_tables(
|
|
__in efx_nic_t *enp,
|
|
__in efx_register_set_t *rsp,
|
|
__in efx_pattern_type_t pattern,
|
|
__in size_t count);
|
|
|
|
#endif /* EFSYS_OPT_DIAG */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* _SYS_EFX_IMPL_H */
|