7672807356
is returned from the card to the driver. Add a counter that shows how many times this allocation has failed. Note, that we could even further delay the allocation of the mbuf until we know, that we need it (there are no receive errors and the connection is open). This will be done in a later commit. Print the new statistics field in atmconfig.
617 lines
19 KiB
C
617 lines
19 KiB
C
/*
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* Copyright (c) 2001-2003
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* Fraunhofer Institute for Open Communication Systems (FhG Fokus).
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Author: Hartmut Brandt <harti@freebsd.org>
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*
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* $FreeBSD$
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*
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* Fore HE driver for NATM
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*/
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/*
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* Debug statistics of the HE driver
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*/
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struct istats {
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uint32_t tdprq_full;
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uint32_t hbuf_error;
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uint32_t crc_error;
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uint32_t len_error;
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uint32_t flow_closed;
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uint32_t flow_drop;
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uint32_t tpd_no_mem;
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uint32_t rx_seg;
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uint32_t empty_hbuf;
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uint32_t short_aal5;
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uint32_t badlen_aal5;
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uint32_t bug_bad_isw;
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uint32_t bug_no_irq_upd;
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uint32_t itype_tbrq;
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uint32_t itype_tpd;
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uint32_t itype_rbps;
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uint32_t itype_rbpl;
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uint32_t itype_rbrq;
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uint32_t itype_rbrqt;
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uint32_t itype_unknown;
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uint32_t itype_phys;
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uint32_t itype_err;
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uint32_t defrag;
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uint32_t mcc;
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uint32_t oec;
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uint32_t dcc;
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uint32_t cec;
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uint32_t no_rcv_mbuf;
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};
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/* Card memory layout parameters */
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#define HE_CONFIG_MEM_LAYOUT { \
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{ /* 155 */ \
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20, /* cells_per_row */ \
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1024, /* bytes_per_row */ \
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512, /* r0_numrows */ \
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1018, /* tx_numrows */ \
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512, /* r1_numrows */ \
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6, /* r0_startrow */ \
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2 /* cells_per_lbuf */ \
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}, { /* 622 */ \
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40, /* cells_per_row */ \
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2048, /* bytes_per_row */ \
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256, /* r0_numrows */ \
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512, /* tx_numrows */ \
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256, /* r1_numrows */ \
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0, /* r0_startrow */ \
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4 /* cells_per_lbuf */ \
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} \
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}
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/*********************************************************************/
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struct hatm_softc;
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/*
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* A chunk of DMA-able memory
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*/
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struct dmamem {
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u_int size; /* in bytes */
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u_int align; /* alignement */
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bus_dma_tag_t tag; /* DMA tag */
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void *base; /* the memory */
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bus_addr_t paddr; /* physical address */
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bus_dmamap_t map; /* the MAP */
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};
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/*
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* RBP (Receive Buffer Pool) queue entry and queue.
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*/
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struct herbp {
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u_int size; /* RBP number of entries (power of two) */
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u_int thresh; /* interrupt treshold */
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uint32_t bsize; /* buffer size in bytes */
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u_int offset; /* free space at start for small bufs */
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uint32_t mask; /* mask for index */
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struct dmamem mem; /* the queue area */
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struct he_rbpen *rbp;
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uint32_t head, tail; /* head and tail */
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};
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/*
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* RBRQ (Receive Buffer Return Queue) entry and queue.
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*/
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struct herbrq {
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u_int size; /* number of entries */
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u_int thresh; /* interrupt threshold */
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u_int tout; /* timeout value */
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u_int pcnt; /* packet count threshold */
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struct dmamem mem; /* memory */
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struct he_rbrqen *rbrq;
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uint32_t head; /* driver end */
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};
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/*
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* TPDRQ (Transmit Packet Descriptor Ready Queue) entry and queue
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*/
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struct hetpdrq {
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u_int size; /* number of entries */
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struct dmamem mem; /* memory */
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struct he_tpdrqen *tpdrq;
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u_int head; /* head (copy of adapter) */
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u_int tail; /* written back to adapter */
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};
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/*
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* TBRQ (Transmit Buffer Return Queue) entry and queue
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*/
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struct hetbrq {
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u_int size; /* number of entries */
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u_int thresh; /* interrupt threshold */
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struct dmamem mem; /* memory */
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struct he_tbrqen *tbrq;
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u_int head; /* adapter end */
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};
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/*==================================================================*/
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/*
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* TPDs are 32 byte and must be aligned on 64 byte boundaries. That means,
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* that half of the space is free. We use this space to plug in a link for
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* the list of free TPDs. Note, that the m_act member of the mbufs contain
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* a pointer to the dmamap.
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*
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* The maximum number of TDPs is the size of the common transmit packet
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* descriptor ready queue plus the sizes of the transmit buffer return queues
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* (currently only queue 0). We allocate and map these TPD when initializing
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* the card. We also allocate on DMA map for each TPD. Only the map in the
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* last TPD of a packets is used when a packet is transmitted.
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* This is signalled by having the mbuf member of this TPD non-zero and
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* pointing to the mbuf.
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*/
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#define HE_TPD_SIZE 64
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struct tpd {
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struct he_tpd tpd; /* at beginning */
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SLIST_ENTRY(tpd) link; /* free cid list link */
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struct mbuf *mbuf; /* the buf chain */
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bus_dmamap_t map; /* map */
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uint32_t cid; /* CID */
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uint16_t no; /* number of this tpd */
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};
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SLIST_HEAD(tpd_list, tpd);
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#define TPD_SET_USED(SC, I) do { \
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(SC)->tpd_used[(I) / 8] |= (1 << ((I) % 8)); \
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} while (0)
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#define TPD_CLR_USED(SC, I) do { \
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(SC)->tpd_used[(I) / 8] &= ~(1 << ((I) % 8)); \
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} while (0)
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#define TPD_TST_USED(SC, I) ((SC)->tpd_used[(I) / 8] & (1 << ((I) % 8)))
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#define TPD_ADDR(SC, I) ((struct tpd *)((char *)sc->tpds.base + \
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(I) * HE_TPD_SIZE))
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/*==================================================================*/
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/*
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* External MBUFs. The card needs a lot of mbufs in the pools for high
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* performance. The problem with using mbufs directly is that we would need
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* a dmamap for each of the mbufs. This can exhaust iommu space on the sparc
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* and it eats also a lot of processing time. So we use external mbufs
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* for the small buffers and clusters for the large buffers.
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* For receive group 0 we use 5 ATM cells, for group 1 one (52 byte) ATM
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* cell. The mbuf storage is allocated pagewise and one dmamap is used per
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* page.
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*
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* The handle we give to the card for the small buffers is a word combined
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* of the page number and the number of the chunk in the page. This restricts
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* the number of chunks per page to 256 (8 bit) and the number of pages to
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* 65536 (16 bits).
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*
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* A chunk may be in one of three states: free, on the card and floating around
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* in the system. If it is free, it is on one of the two free lists and
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* start with a struct mbufx_free. Each page has a bitmap that tracks where
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* its chunks are.
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*
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* For large buffers we use mbuf clusters. Here we have two problems: we need
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* to track the buffers on the card (in the case we want to stop it) and
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* we need to map the 64bit mbuf address to a 26bit handle for 64-bit machines.
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* The card uses the buffers in the order we give it to the card. Therefor
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* we can use a private array holding pointers to the mbufs as a circular
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* queue for both tasks. This is done with the lbufs member of softc. The
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* handle for these buffer is the lbufs index ored with a flag.
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*/
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#define MBUF0_SIZE (5 * 48) /* 240 */
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#define MBUF1_SIZE (52)
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#define MBUF0_CHUNK 256 /* 16 free bytes */
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#define MBUF1_CHUNK 96 /* 44 free bytes */
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#ifdef XXX
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#define MBUF0_OFFSET (MBUF0_CHUNK - sizeof(struct mbuf_chunk_hdr) \
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- MBUF0_SIZE)
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#else
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#define MBUF0_OFFSET 0
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#endif
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#define MBUF1_OFFSET (MBUF1_CHUNK - sizeof(struct mbuf_chunk_hdr) \
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- MBUF1_SIZE)
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#define MBUFL_OFFSET 16 /* two pointers for HARP */
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#define MBUF_ALLOC_SIZE (PAGE_SIZE)
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/* each allocated page has one of these structures at its very end. */
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struct mbuf_page_hdr {
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uint8_t card[32]; /* bitmap for on-card */
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uint16_t nchunks; /* chunks on this page */
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bus_dmamap_t map; /* the DMA MAP */
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uint32_t phys; /* physical base address */
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uint32_t hdroff; /* chunk header offset */
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uint32_t chunksize; /* chunk size */
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};
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struct mbuf_page {
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char storage[MBUF_ALLOC_SIZE - sizeof(struct mbuf_page_hdr)];
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struct mbuf_page_hdr hdr;
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};
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/* numbers per page */
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#define MBUF0_PER_PAGE ((MBUF_ALLOC_SIZE - sizeof(struct mbuf_page_hdr)) / \
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MBUF0_CHUNK)
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#define MBUF1_PER_PAGE ((MBUF_ALLOC_SIZE - sizeof(struct mbuf_page_hdr)) / \
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MBUF1_CHUNK)
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#define MBUF_CLR_BIT(ARRAY, BIT) ((ARRAY)[(BIT) / 8] &= ~(1 << ((BIT) % 8)))
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#define MBUF_SET_BIT(ARRAY, BIT) ((ARRAY)[(BIT) / 8] |= (1 << ((BIT) % 8)))
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#define MBUF_TST_BIT(ARRAY, BIT) ((ARRAY)[(BIT) / 8] & (1 << ((BIT) % 8)))
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#define MBUF_MAKE_HANDLE(PAGENO, CHUNKNO) \
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(((PAGENO) << 10) | (CHUNKNO))
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#define MBUF_PARSE_HANDLE(HANDLE, PAGENO, CHUNKNO) do { \
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(CHUNKNO) = (HANDLE) & 0x3ff; \
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(PAGENO) = ((HANDLE) >> 10) & 0x3ff; \
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} while (0)
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#define MBUF_LARGE_FLAG (1 << 20)
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/* chunks have the following structure at the end (4 byte) */
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struct mbuf_chunk_hdr {
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uint16_t pageno;
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uint16_t chunkno;
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};
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#define MBUFX_STORAGE_SIZE(X) (MBUF##X##_CHUNK \
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- sizeof(struct mbuf_chunk_hdr))
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struct mbuf0_chunk {
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char storage[MBUFX_STORAGE_SIZE(0)];
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struct mbuf_chunk_hdr hdr;
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};
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struct mbuf1_chunk {
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char storage[MBUFX_STORAGE_SIZE(1)];
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struct mbuf_chunk_hdr hdr;
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};
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struct mbufx_free {
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struct mbufx_free *link;
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};
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/*==================================================================*/
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/*
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* Interrupt queue
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*/
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struct heirq {
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u_int size; /* number of entries */
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u_int thresh; /* re-interrupt threshold */
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u_int line; /* interrupt line to use */
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struct dmamem mem; /* interrupt queues */
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uint32_t * irq; /* interrupt queue */
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uint32_t head; /* head index */
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uint32_t * tailp; /* pointer to tail */
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struct hatm_softc *sc; /* back pointer */
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u_int group; /* interrupt group */
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};
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/*
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* This structure describes all information for a VCC open on the card.
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* The array of these structures is indexed by the compressed connection ID
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* (CID). This structure must begin with the atmio_vcc.
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*/
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struct hevcc {
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struct atmio_vcc param; /* traffic parameters */
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void * rxhand; /* NATM protocol block */
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u_int vflags; /* private flags */
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uint32_t ipackets;
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uint32_t opackets;
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uint32_t ibytes;
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uint32_t obytes;
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u_int rc; /* rate control group for CBR */
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struct mbuf * chain; /* partial received PDU */
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struct mbuf * last; /* last mbuf in chain */
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u_int ntpds; /* number of active TPDs */
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};
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#define HE_VCC_OPEN 0x000f0000
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#define HE_VCC_RX_OPEN 0x00010000
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#define HE_VCC_RX_CLOSING 0x00020000
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#define HE_VCC_TX_OPEN 0x00040000
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#define HE_VCC_TX_CLOSING 0x00080000
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#define HE_VCC_FLOW_CTRL 0x00100000
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/*
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* CBR rate groups
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*/
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struct herg {
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u_int refcnt; /* how many connections reference this group */
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u_int rate; /* the value */
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};
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/*
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* Softc
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*/
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struct hatm_softc {
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struct ifatm ifatm; /* common ATM stuff */
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struct mtx mtx; /* lock */
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struct ifmedia media; /* media */
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device_t dev; /* device */
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int memid; /* resoure id for memory */
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struct resource * memres; /* memory resource */
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bus_space_handle_t memh; /* handle */
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bus_space_tag_t memt; /* ... and tag */
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bus_dma_tag_t parent_tag; /* global restriction */
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struct cv vcc_cv; /* condition variable */
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int irqid; /* resource id */
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struct resource * irqres; /* resource */
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void * ih; /* interrupt handle */
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struct utopia utopia; /* utopia state */
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/* rest has to be reset by stop */
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int he622; /* this is a HE622 */
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int pci64; /* 64bit bus */
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char prod_id[HE_EEPROM_PROD_ID_LEN + 1];
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char rev[HE_EEPROM_REV_LEN + 1];
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struct heirq irq_0; /* interrupt queues 0 */
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/* generic network controller state */
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u_int cells_per_row;
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u_int bytes_per_row;
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u_int r0_numrows;
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u_int tx_numrows;
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u_int r1_numrows;
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u_int r0_startrow;
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u_int tx_startrow;
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u_int r1_startrow;
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u_int cells_per_lbuf;
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u_int r0_numbuffs;
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u_int r1_numbuffs;
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u_int tx_numbuffs;
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/* HSP */
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struct he_hsp *hsp;
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struct dmamem hsp_mem;
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/*** TX ***/
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struct hetbrq tbrq; /* TBRQ 0 */
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struct hetpdrq tpdrq; /* TPDRQ */
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struct tpd_list tpd_free; /* Free TPDs */
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u_int tpd_nfree; /* number of free TPDs */
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u_int tpd_total; /* total TPDs */
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uint8_t *tpd_used; /* bitmap of used TPDs */
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struct dmamem tpds; /* TPD memory */
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bus_dma_tag_t tx_tag; /* DMA tag for all tx mbufs */
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/*** RX ***/
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/* receive/transmit groups */
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struct herbp rbp_s0; /* RBPS0 */
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struct herbp rbp_l0; /* RBPL0 */
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struct herbp rbp_s1; /* RBPS1 */
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struct herbrq rbrq_0; /* RBRQ0 */
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struct herbrq rbrq_1; /* RBRQ1 */
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/* list of external mbuf storage */
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bus_dma_tag_t mbuf_tag;
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struct mbuf_page **mbuf_pages;
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u_int mbuf_npages;
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struct mbufx_free *mbuf_list[2];
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/* mbuf cluster tracking and mapping for group 0 */
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struct mbuf **lbufs; /* mbufs */
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bus_dmamap_t *rmaps; /* DMA maps */
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u_int lbufs_size;
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u_int lbufs_next;
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/* VCCs */
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struct hevcc *vccs[HE_MAX_VCCS];
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u_int cbr_bw; /* BW allocated to CBR */
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u_int max_tpd; /* per VCC */
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u_int open_vccs;
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uma_zone_t vcc_zone;
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/* rate groups */
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struct herg rate_ctrl[HE_REGN_CS_STPER];
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/* memory offsets */
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u_int tsrb, tsrc, tsrd;
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u_int rsrb;
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struct cv cv_rcclose; /* condition variable */
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uint32_t rate_grid[16][16]; /* our copy */
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/* sysctl support */
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struct sysctl_ctx_list sysctl_ctx;
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struct sysctl_oid *sysctl_tree;
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/* internal statistics */
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struct istats istats;
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#ifdef HATM_DEBUG
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/* debugging */
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u_int debug;
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#endif
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};
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#define READ4(SC,OFF) bus_space_read_4(SC->memt, SC->memh, (OFF))
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#define READ2(SC,OFF) bus_space_read_2(SC->memt, SC->memh, (OFF))
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#define READ1(SC,OFF) bus_space_read_1(SC->memt, SC->memh, (OFF))
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#define WRITE4(SC,OFF,VAL) bus_space_write_4(SC->memt, SC->memh, (OFF), (VAL))
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#define WRITE2(SC,OFF,VAL) bus_space_write_2(SC->memt, SC->memh, (OFF), (VAL))
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#define WRITE1(SC,OFF,VAL) bus_space_write_1(SC->memt, SC->memh, (OFF), (VAL))
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#define BARRIER_R(SC) bus_space_barrier(SC->memt, SC->memh, 0, HE_REGO_END, \
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BUS_SPACE_BARRIER_READ)
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#define BARRIER_W(SC) bus_space_barrier(SC->memt, SC->memh, 0, HE_REGO_END, \
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BUS_SPACE_BARRIER_WRITE)
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#define BARRIER_RW(SC) bus_space_barrier(SC->memt, SC->memh, 0, HE_REGO_END, \
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
|
|
|
|
#define READ_SUNI(SC,OFF) READ4(SC, HE_REGO_SUNI + 4 * (OFF))
|
|
#define WRITE_SUNI(SC,OFF,VAL) WRITE4(SC, HE_REGO_SUNI + 4 * (OFF), (VAL))
|
|
|
|
#define READ_LB4(SC,OFF) \
|
|
({ \
|
|
WRITE4(SC, HE_REGO_LB_MEM_ADDR, (OFF)); \
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|
WRITE4(SC, HE_REGO_LB_MEM_ACCESS, \
|
|
(HE_REGM_LB_MEM_HNDSHK | HE_REGM_LB_MEM_READ)); \
|
|
while((READ4(SC, HE_REGO_LB_MEM_ACCESS) & HE_REGM_LB_MEM_HNDSHK))\
|
|
; \
|
|
READ4(SC, HE_REGO_LB_MEM_DATA); \
|
|
})
|
|
#define WRITE_LB4(SC,OFF,VAL) \
|
|
do { \
|
|
WRITE4(SC, HE_REGO_LB_MEM_ADDR, (OFF)); \
|
|
WRITE4(SC, HE_REGO_LB_MEM_DATA, (VAL)); \
|
|
WRITE4(SC, HE_REGO_LB_MEM_ACCESS, \
|
|
(HE_REGM_LB_MEM_HNDSHK | HE_REGM_LB_MEM_WRITE)); \
|
|
while((READ4(SC, HE_REGO_LB_MEM_ACCESS) & HE_REGM_LB_MEM_HNDSHK))\
|
|
; \
|
|
} while(0)
|
|
|
|
#define WRITE_MEM4(SC,OFF,VAL,SPACE) \
|
|
do { \
|
|
WRITE4(SC, HE_REGO_CON_DAT, (VAL)); \
|
|
WRITE4(SC, HE_REGO_CON_CTL, \
|
|
(SPACE | HE_REGM_CON_WE | HE_REGM_CON_STATUS | (OFF))); \
|
|
while((READ4(SC, HE_REGO_CON_CTL) & HE_REGM_CON_STATUS) != 0) \
|
|
; \
|
|
} while(0)
|
|
|
|
#define READ_MEM4(SC,OFF,SPACE) \
|
|
({ \
|
|
WRITE4(SC, HE_REGO_CON_CTL, \
|
|
(SPACE | HE_REGM_CON_STATUS | (OFF))); \
|
|
while((READ4(SC, HE_REGO_CON_CTL) & HE_REGM_CON_STATUS) != 0) \
|
|
; \
|
|
READ4(SC, HE_REGO_CON_DAT); \
|
|
})
|
|
|
|
#define WRITE_TCM4(SC,OFF,VAL) WRITE_MEM4(SC,(OFF),(VAL),HE_REGM_CON_TCM)
|
|
#define WRITE_RCM4(SC,OFF,VAL) WRITE_MEM4(SC,(OFF),(VAL),HE_REGM_CON_RCM)
|
|
#define WRITE_MBOX4(SC,OFF,VAL) WRITE_MEM4(SC,(OFF),(VAL),HE_REGM_CON_MBOX)
|
|
|
|
#define READ_TCM4(SC,OFF) READ_MEM4(SC,(OFF),HE_REGM_CON_TCM)
|
|
#define READ_RCM4(SC,OFF) READ_MEM4(SC,(OFF),HE_REGM_CON_RCM)
|
|
#define READ_MBOX4(SC,OFF) READ_MEM4(SC,(OFF),HE_REGM_CON_MBOX)
|
|
|
|
#define WRITE_TCM(SC,OFF,BYTES,VAL) \
|
|
WRITE_MEM4(SC,(OFF) | ((~(BYTES) & 0xf) << HE_REGS_CON_DIS), \
|
|
(VAL), HE_REGM_CON_TCM)
|
|
#define WRITE_RCM(SC,OFF,BYTES,VAL) \
|
|
WRITE_MEM4(SC,(OFF) | ((~(BYTES) & 0xf) << HE_REGS_CON_DIS), \
|
|
(VAL), HE_REGM_CON_RCM)
|
|
|
|
#define READ_TSR(SC,CID,NR) \
|
|
({ \
|
|
uint32_t _v; \
|
|
if((NR) <= 7) { \
|
|
_v = READ_TCM4(SC, HE_REGO_TSRA(0,CID,NR)); \
|
|
} else if((NR) <= 11) { \
|
|
_v = READ_TCM4(SC, HE_REGO_TSRB((SC)->tsrb,CID,(NR-8)));\
|
|
} else if((NR) <= 13) { \
|
|
_v = READ_TCM4(SC, HE_REGO_TSRC((SC)->tsrc,CID,(NR-12)));\
|
|
} else { \
|
|
_v = READ_TCM4(SC, HE_REGO_TSRD((SC)->tsrd,CID)); \
|
|
} \
|
|
_v; \
|
|
})
|
|
|
|
#define WRITE_TSR(SC,CID,NR,BEN,VAL) \
|
|
do { \
|
|
if((NR) <= 7) { \
|
|
WRITE_TCM(SC, HE_REGO_TSRA(0,CID,NR),BEN,VAL); \
|
|
} else if((NR) <= 11) { \
|
|
WRITE_TCM(SC, HE_REGO_TSRB((SC)->tsrb,CID,(NR-8)),BEN,VAL);\
|
|
} else if((NR) <= 13) { \
|
|
WRITE_TCM(SC, HE_REGO_TSRC((SC)->tsrc,CID,(NR-12)),BEN,VAL);\
|
|
} else { \
|
|
WRITE_TCM(SC, HE_REGO_TSRD((SC)->tsrd,CID),BEN,VAL); \
|
|
} \
|
|
} while(0)
|
|
|
|
#define READ_RSR(SC,CID,NR) \
|
|
({ \
|
|
uint32_t _v; \
|
|
if((NR) <= 7) { \
|
|
_v = READ_RCM4(SC, HE_REGO_RSRA(0,CID,NR)); \
|
|
} else { \
|
|
_v = READ_RCM4(SC, HE_REGO_RSRB((SC)->rsrb,CID,(NR-8)));\
|
|
} \
|
|
_v; \
|
|
})
|
|
|
|
#define WRITE_RSR(SC,CID,NR,BEN,VAL) \
|
|
do { \
|
|
if((NR) <= 7) { \
|
|
WRITE_RCM(SC, HE_REGO_RSRA(0,CID,NR),BEN,VAL); \
|
|
} else { \
|
|
WRITE_RCM(SC, HE_REGO_RSRB((SC)->rsrb,CID,(NR-8)),BEN,VAL);\
|
|
} \
|
|
} while(0)
|
|
|
|
#ifdef HATM_DEBUG
|
|
#define DBG(SC, FL, PRINT) do { \
|
|
if((SC)->debug & DBG_##FL) { \
|
|
if_printf(&(SC)->ifatm.ifnet, "%s: ", __func__); \
|
|
printf PRINT; \
|
|
printf("\n"); \
|
|
} \
|
|
} while (0)
|
|
|
|
enum {
|
|
DBG_RX = 0x0001,
|
|
DBG_TX = 0x0002,
|
|
DBG_VCC = 0x0004,
|
|
DBG_IOCTL = 0x0008,
|
|
DBG_ATTACH = 0x0010,
|
|
DBG_INTR = 0x0020,
|
|
DBG_DMA = 0x0040,
|
|
DBG_DMAH = 0x0080,
|
|
|
|
DBG_ALL = 0x00ff
|
|
};
|
|
|
|
#else
|
|
#define DBG(SC, FL, PRINT)
|
|
#endif
|
|
|
|
u_int hatm_cps2atmf(uint32_t);
|
|
u_int hatm_atmf2cps(uint32_t);
|
|
|
|
void hatm_intr(void *);
|
|
int hatm_ioctl(struct ifnet *, u_long, caddr_t);
|
|
void hatm_initialize(struct hatm_softc *);
|
|
void hatm_stop(struct hatm_softc *sc);
|
|
void hatm_start(struct ifnet *);
|
|
|
|
void hatm_rx(struct hatm_softc *sc, u_int cid, u_int flags, struct mbuf *m,
|
|
u_int len);
|
|
void hatm_tx_complete(struct hatm_softc *sc, struct tpd *tpd, uint32_t);
|
|
|
|
int hatm_tx_vcc_can_open(struct hatm_softc *sc, u_int cid, struct hevcc *);
|
|
void hatm_tx_vcc_open(struct hatm_softc *sc, u_int cid);
|
|
void hatm_rx_vcc_open(struct hatm_softc *sc, u_int cid);
|
|
void hatm_tx_vcc_close(struct hatm_softc *sc, u_int cid);
|
|
void hatm_rx_vcc_close(struct hatm_softc *sc, u_int cid);
|
|
void hatm_tx_vcc_closed(struct hatm_softc *sc, u_int cid);
|
|
void hatm_vcc_closed(struct hatm_softc *sc, u_int cid);
|
|
void hatm_load_vc(struct hatm_softc *sc, u_int cid, int reopen);
|