4a35efc720
the TLBs in order to get rid of the user mappings but instead traverse
them an flush only the latter like we also do for the Spitfire-class.
Also flushing the unlocked kernel entries can cause instant faults which
when called from within cpu_switch() are handled with the scheduler lock
held which in turn can cause timeouts on the acquisition of the lock by
other CPUs. This was easily seen with a 16-core V890 but occasionally
also happened with 2-way machines.
While at it, move the SPARC64-V support code entirely to zeus.c. This
causes a little bit of duplication but is less confusing than partially
using Cheetah-class bits for these.
- For SPARC64-V ensure that 4-Mbyte page entries are stored in the 1024-
entry, 2-way set associative TLB.
- In {d,i}tlb_get_data_sun4u() turn off the interrupts in order to ensure
that ASI_{D,I}TLB_DATA_ACCESS_REG actually are read twice back-to-back.
Tested by: Peter Jeremy (16-core US-IV), Michael Moll (2-way SPARC64-V)
172 lines
4.5 KiB
C
172 lines
4.5 KiB
C
/*-
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* Copyright (c) 2010 - 2011 Marius Strobl <marius@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <machine/asi.h>
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#include <machine/cache.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/mcntl.h>
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#include <machine/lsu.h>
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#include <machine/tlb.h>
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#include <machine/tte.h>
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#include <machine/vmparam.h>
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#define ZEUS_FTLB_ENTRIES 32
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#define ZEUS_STLB_ENTRIES 2048
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/*
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* CPU-specific initialization for Fujitsu Zeus CPUs
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*/
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void
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zeus_init(u_int cpu_impl)
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{
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u_long val;
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/* Ensure the TSB Extension Registers hold 0 as TSB_Base. */
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stxa(AA_DMMU_TSB_PEXT_REG, ASI_DMMU, 0);
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stxa(AA_IMMU_TSB_PEXT_REG, ASI_IMMU, 0);
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membar(Sync);
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stxa(AA_DMMU_TSB_SEXT_REG, ASI_DMMU, 0);
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/*
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* NB: the secondary context was removed from the iMMU.
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*/
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membar(Sync);
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stxa(AA_DMMU_TSB_NEXT_REG, ASI_DMMU, 0);
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stxa(AA_IMMU_TSB_NEXT_REG, ASI_IMMU, 0);
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membar(Sync);
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val = ldxa(AA_MCNTL, ASI_MCNTL);
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/* Ensure MCNTL_JPS1_TSBP is 0. */
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val &= ~MCNTL_JPS1_TSBP;
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/*
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* Ensure 4-Mbyte page entries are stored in the 1024-entry, 2-way set
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* associative TLB.
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*/
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val = (val & ~MCNTL_RMD_MASK) | MCNTL_RMD_1024;
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stxa(AA_MCNTL, ASI_MCNTL, val);
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}
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/*
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* Enable level 1 caches.
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*/
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void
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zeus_cache_enable(u_int cpu_impl)
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{
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u_long lsu;
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lsu = ldxa(0, ASI_LSU_CTL_REG);
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stxa(0, ASI_LSU_CTL_REG, lsu | LSU_IC | LSU_DC);
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flush(KERNBASE);
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}
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/*
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* Flush all lines from the level 1 caches.
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*/
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void
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zeus_cache_flush(void)
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{
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stxa_sync(0, ASI_FLUSH_L1I, 0);
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}
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/*
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* Flush a physical page from the data cache. Data cache consistency is
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* maintained by hardware.
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*/
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void
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zeus_dcache_page_inval(vm_paddr_t spa __unused)
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{
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}
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/*
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* Flush a physical page from the intsruction cache. Instruction cache
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* consistency is maintained by hardware.
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*/
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void
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zeus_icache_page_inval(vm_paddr_t pa __unused)
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{
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}
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/*
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* Flush all non-locked mappings from the TLBs.
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*/
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void
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zeus_tlb_flush_nonlocked(void)
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{
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stxa(TLB_DEMAP_ALL, ASI_DMMU_DEMAP, 0);
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stxa(TLB_DEMAP_ALL, ASI_IMMU_DEMAP, 0);
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flush(KERNBASE);
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}
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/*
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* Flush all user mappings from the TLBs.
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*/
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void
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zeus_tlb_flush_user(void)
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{
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u_long data, tag;
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u_int i, slot;
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for (i = 0; i < ZEUS_FTLB_ENTRIES; i++) {
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slot = TLB_DAR_SLOT(TLB_DAR_FTLB, i);
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data = ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
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tag = ldxa(slot, ASI_DTLB_TAG_READ_REG);
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if ((data & TD_V) != 0 && (data & TD_L) == 0 &&
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TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
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stxa_sync(slot, ASI_DTLB_DATA_ACCESS_REG, 0);
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data = ldxa(slot, ASI_ITLB_DATA_ACCESS_REG);
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tag = ldxa(slot, ASI_ITLB_TAG_READ_REG);
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if ((data & TD_V) != 0 && (data & TD_L) == 0 &&
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TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
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stxa_sync(slot, ASI_ITLB_DATA_ACCESS_REG, 0);
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}
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for (i = 0; i < ZEUS_STLB_ENTRIES; i++) {
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slot = TLB_DAR_SLOT(TLB_DAR_STLB, i);
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data = ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
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tag = ldxa(slot, ASI_DTLB_TAG_READ_REG);
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if ((data & TD_V) != 0 && (data & TD_L) == 0 &&
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TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
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stxa_sync(slot, ASI_DTLB_DATA_ACCESS_REG, 0);
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data = ldxa(slot, ASI_ITLB_DATA_ACCESS_REG);
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tag = ldxa(slot, ASI_ITLB_TAG_READ_REG);
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if ((data & TD_V) != 0 && (data & TD_L) == 0 &&
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TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
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stxa_sync(slot, ASI_ITLB_DATA_ACCESS_REG, 0);
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}
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}
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