1fa7f10bac
domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
170 lines
5.6 KiB
C
170 lines
5.6 KiB
C
/*-
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* Copyright (c) 2003-2005,2008 Joseph Koshy
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* Copyright (c) 2007 The FreeBSD Foundation
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* All rights reserved.
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*
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* Portions of this software were developed by A. Joseph Koshy under
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* sponsorship from the FreeBSD Foundation and Google, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PMC_MDEP_H
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#define _MACHINE_PMC_MDEP_H 1
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#ifdef _KERNEL
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struct pmc_mdep;
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#endif
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/*
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* On the i386 platform we support the following PMCs.
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*
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* TSC The timestamp counter
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* K7 AMD Athlon XP/MP and other 32 bit processors.
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* K8 AMD Athlon64 and Opteron PMCs in 32 bit mode.
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* PIV Intel P4/HTT and P4/EMT64
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* PPRO Intel Pentium Pro, Pentium-II, Pentium-III, Celeron and
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* Pentium-M processors
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* PENTIUM Intel Pentium MMX.
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* IAP Intel Core/Core2/Atom programmable PMCs.
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* IAF Intel fixed-function PMCs.
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* UCP Intel Uncore programmable PMCs.
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* UCF Intel Uncore fixed-function PMCs.
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*/
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#include <dev/hwpmc/hwpmc_amd.h> /* K7 and K8 */
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#include <dev/hwpmc/hwpmc_core.h>
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#include <dev/hwpmc/hwpmc_piv.h>
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#include <dev/hwpmc/hwpmc_ppro.h>
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#include <dev/hwpmc/hwpmc_pentium.h>
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#include <dev/hwpmc/hwpmc_tsc.h>
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#include <dev/hwpmc/hwpmc_uncore.h>
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/*
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* Intel processors implementing V2 and later of the Intel performance
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* measurement architecture have PMCs of the following classes: TSC,
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* IAF, IAP, UCF and UCP.
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*/
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#define PMC_MDEP_CLASS_INDEX_TSC 0
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#define PMC_MDEP_CLASS_INDEX_K7 1
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#define PMC_MDEP_CLASS_INDEX_K8 1
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#define PMC_MDEP_CLASS_INDEX_P4 1
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#define PMC_MDEP_CLASS_INDEX_P5 1
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#define PMC_MDEP_CLASS_INDEX_P6 1
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#define PMC_MDEP_CLASS_INDEX_IAP 1
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#define PMC_MDEP_CLASS_INDEX_IAF 2
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#define PMC_MDEP_CLASS_INDEX_UCP 3
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#define PMC_MDEP_CLASS_INDEX_UCF 4
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/*
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* Architecture specific extensions to <sys/pmc.h> structures.
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*/
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union pmc_md_op_pmcallocate {
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struct pmc_md_amd_op_pmcallocate pm_amd;
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struct pmc_md_iaf_op_pmcallocate pm_iaf;
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struct pmc_md_iap_op_pmcallocate pm_iap;
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struct pmc_md_ucf_op_pmcallocate pm_ucf;
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struct pmc_md_ucp_op_pmcallocate pm_ucp;
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struct pmc_md_p4_op_pmcallocate pm_p4;
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struct pmc_md_pentium_op_pmcallocate pm_pentium;
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struct pmc_md_ppro_op_pmcallocate pm_ppro;
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uint64_t __pad[4];
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};
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/* Logging */
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#define PMCLOG_READADDR PMCLOG_READ32
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#define PMCLOG_EMITADDR PMCLOG_EMIT32
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#ifdef _KERNEL
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/* MD extension for 'struct pmc' */
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union pmc_md_pmc {
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struct pmc_md_amd_pmc pm_amd;
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struct pmc_md_iaf_pmc pm_iaf;
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struct pmc_md_iap_pmc pm_iap;
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struct pmc_md_ucf_pmc pm_ucf;
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struct pmc_md_ucp_pmc pm_ucp;
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struct pmc_md_p4_pmc pm_p4;
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struct pmc_md_pentium_pmc pm_pentium;
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struct pmc_md_ppro_pmc pm_ppro;
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};
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struct pmc;
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struct pmc_mdep;
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#define PMC_TRAPFRAME_TO_PC(TF) ((TF)->tf_eip)
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#define PMC_TRAPFRAME_TO_FP(TF) ((TF)->tf_ebp)
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/*
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* The layout of the stack frame on entry into the NMI handler depends on
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* whether a privilege level change (and consequent stack switch) was
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* required for entry.
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*
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* When processing an interrupt when in user mode, the processor switches
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* stacks, and saves the user mode stack pointer on the kernel stack. The
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* user mode stack pointer is then available to the interrupt handler
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* at frame->tf_esp.
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*
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* When processing an interrupt while in kernel mode, the processor
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* continues to use the existing (kernel) stack. Therefore we determine
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* the stack pointer for the interrupted kernel procedure by adding an
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* offset to the current frame pointer.
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*/
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#define PMC_TRAPFRAME_TO_USER_SP(TF) ((TF)->tf_esp)
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#define PMC_TRAPFRAME_TO_KERNEL_SP(TF) ((uintptr_t) &((TF)->tf_esp))
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#define PMC_IN_KERNEL_STACK(S,START,END) \
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((S) >= (START) && (S) < (END))
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#define PMC_IN_KERNEL(va) (((va) >= USRSTACK) && \
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((va) < VM_MAX_KERNEL_ADDRESS))
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#define PMC_IN_USERSPACE(va) ((va) <= VM_MAXUSER_ADDRESS)
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#define PMC_IN_TRAP_HANDLER(PC) \
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((PC) >= (uintptr_t) start_exceptions && \
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(PC) < (uintptr_t) end_exceptions)
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#define PMC_AT_FUNCTION_PROLOGUE_PUSH_BP(I) \
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(((I) & 0x00ffffff) == 0xe58955) /* pushl %ebp; movl %esp,%ebp */
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#define PMC_AT_FUNCTION_PROLOGUE_MOV_SP_BP(I) \
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(((I) & 0x0000ffff) == 0xe589) /* movl %esp,%ebp */
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#define PMC_AT_FUNCTION_EPILOGUE_RET(I) \
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(((I) & 0xFF) == 0xC3) /* ret */
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/*
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* Prototypes
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*/
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void start_exceptions(void), end_exceptions(void);
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struct pmc_mdep *pmc_amd_initialize(void);
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void pmc_amd_finalize(struct pmc_mdep *_md);
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struct pmc_mdep *pmc_intel_initialize(void);
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void pmc_intel_finalize(struct pmc_mdep *_md);
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#endif /* _KERNEL */
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#endif /* _MACHINE_PMC_MDEP_H */
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