1030 lines
26 KiB
C
1030 lines
26 KiB
C
/*-
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* Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp>
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* Copyright (c) 2001 Cameron Grant <cg@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <dev/sound/pcm/sound.h>
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#include <dev/sound/pcm/ac97.h>
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#include <dev/sound/pci/ich.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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SND_DECLARE_FILE("$FreeBSD$");
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/* -------------------------------------------------------------------- */
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#define ICH_TIMEOUT 1000 /* semaphore timeout polling count */
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#define ICH_DTBL_LENGTH 32
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#define ICH_DEFAULT_BUFSZ 16384
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#define ICH_MAX_BUFSZ 65536
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#define INTEL_VENDORID 0x8086
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#define SIS_VENDORID 0x1039
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#define NVIDIA_VENDORID 0x10de
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#define AMD_VENDORID 0x1022
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#define INTEL_82440MX 0x7195
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#define INTEL_82801AA 0x2415
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#define INTEL_82801AB 0x2425
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#define INTEL_82801BA 0x2445
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#define INTEL_82801CA 0x2485
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#define INTEL_82801DB 0x24c5 /* ICH4 needs special handling */
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#define INTEL_82801EB 0x24d5 /* ICH5 needs to be treated as ICH4 */
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#define INTEL_6300ESB 0x25a6 /* 6300ESB needs to be treated as ICH4 */
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#define INTEL_82801FB 0x266e /* ICH6 needs to be treated as ICH4 */
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#define INTEL_82801GB 0x27de /* ICH7 needs to be treated as ICH4 */
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#define SIS_7012 0x7012 /* SiS 7012 needs special handling */
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#define NVIDIA_NFORCE 0x01b1
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#define NVIDIA_NFORCE2 0x006a
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#define NVIDIA_NFORCE2_400 0x008a
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#define NVIDIA_NFORCE3 0x00da
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#define NVIDIA_NFORCE3_250 0x00ea
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#define NVIDIA_NFORCE4 0x0059
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#define AMD_768 0x7445
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#define AMD_8111 0x746d
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#define ICH_LOCK(sc) snd_mtxlock((sc)->ich_lock)
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#define ICH_UNLOCK(sc) snd_mtxunlock((sc)->ich_lock)
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#define ICH_LOCK_ASSERT(sc) snd_mtxassert((sc)->ich_lock)
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static const struct ich_type {
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uint16_t vendor;
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uint16_t devid;
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uint32_t options;
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#define PROBE_LOW 0x01
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char *name;
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} ich_devs[] = {
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{ INTEL_VENDORID, INTEL_82440MX, 0,
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"Intel 440MX" },
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{ INTEL_VENDORID, INTEL_82801AA, 0,
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"Intel ICH (82801AA)" },
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{ INTEL_VENDORID, INTEL_82801AB, 0,
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"Intel ICH (82801AB)" },
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{ INTEL_VENDORID, INTEL_82801BA, 0,
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"Intel ICH2 (82801BA)" },
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{ INTEL_VENDORID, INTEL_82801CA, 0,
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"Intel ICH3 (82801CA)" },
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{ INTEL_VENDORID, INTEL_82801DB, PROBE_LOW,
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"Intel ICH4 (82801DB)" },
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{ INTEL_VENDORID, INTEL_82801EB, PROBE_LOW,
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"Intel ICH5 (82801EB)" },
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{ INTEL_VENDORID, INTEL_6300ESB, PROBE_LOW,
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"Intel 6300ESB" },
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{ INTEL_VENDORID, INTEL_82801FB, PROBE_LOW,
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"Intel ICH6 (82801FB)" },
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{ INTEL_VENDORID, INTEL_82801GB, PROBE_LOW,
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"Intel ICH7 (82801GB)" },
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{ SIS_VENDORID, SIS_7012, 0,
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"SiS 7012" },
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{ NVIDIA_VENDORID, NVIDIA_NFORCE, 0,
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"nVidia nForce" },
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{ NVIDIA_VENDORID, NVIDIA_NFORCE2, 0,
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"nVidia nForce2" },
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{ NVIDIA_VENDORID, NVIDIA_NFORCE2_400, 0,
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"nVidia nForce2 400" },
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{ NVIDIA_VENDORID, NVIDIA_NFORCE3, 0,
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"nVidia nForce3" },
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{ NVIDIA_VENDORID, NVIDIA_NFORCE3_250, 0,
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"nVidia nForce3 250" },
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{ NVIDIA_VENDORID, NVIDIA_NFORCE4, 0,
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"nVidia nForce4" },
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{ AMD_VENDORID, AMD_768, 0,
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"AMD-768" },
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{ AMD_VENDORID, AMD_8111, 0,
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"AMD-8111" }
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};
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/* buffer descriptor */
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struct ich_desc {
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volatile u_int32_t buffer;
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volatile u_int32_t length;
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};
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struct sc_info;
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/* channel registers */
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struct sc_chinfo {
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u_int32_t num:8, run:1, run_save:1;
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u_int32_t blksz, blkcnt, spd;
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u_int32_t regbase, spdreg;
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u_int32_t imask;
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u_int32_t civ;
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struct snd_dbuf *buffer;
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struct pcm_channel *channel;
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struct sc_info *parent;
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struct ich_desc *dtbl;
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bus_addr_t desc_addr;
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};
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/* device private data */
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struct sc_info {
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device_t dev;
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int hasvra, hasvrm, hasmic;
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unsigned int chnum, bufsz;
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int sample_size, swap_reg;
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struct resource *nambar, *nabmbar, *irq;
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int regtype, nambarid, nabmbarid, irqid;
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bus_space_tag_t nambart, nabmbart;
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bus_space_handle_t nambarh, nabmbarh;
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bus_dma_tag_t dmat;
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bus_dmamap_t dtmap;
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void *ih;
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struct ac97_info *codec;
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struct sc_chinfo ch[3];
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int ac97rate;
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struct ich_desc *dtbl;
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bus_addr_t desc_addr;
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struct intr_config_hook intrhook;
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int use_intrhook;
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uint16_t vendor;
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uint16_t devid;
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uint32_t flags;
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#define IGNORE_PCR 0x01
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struct mtx *ich_lock;
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};
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/* -------------------------------------------------------------------- */
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static u_int32_t ich_fmt[] = {
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AFMT_STEREO | AFMT_S16_LE,
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0
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};
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static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0};
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static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0};
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/* -------------------------------------------------------------------- */
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/* Hardware */
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static __inline u_int32_t
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ich_rd(struct sc_info *sc, int regno, int size)
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{
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switch (size) {
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case 1:
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return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno);
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case 2:
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return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno);
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case 4:
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return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno);
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default:
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return 0xffffffff;
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}
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}
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static __inline void
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ich_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
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{
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switch (size) {
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case 1:
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bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data);
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break;
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case 2:
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bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data);
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break;
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case 4:
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bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data);
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break;
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}
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}
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/* ac97 codec */
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static int
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ich_waitcd(void *devinfo)
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{
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int i;
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u_int32_t data;
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struct sc_info *sc = (struct sc_info *)devinfo;
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for (i = 0; i < ICH_TIMEOUT; i++) {
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data = ich_rd(sc, ICH_REG_ACC_SEMA, 1);
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if ((data & 0x01) == 0)
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return 0;
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DELAY(1);
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}
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if ((sc->flags & IGNORE_PCR) != 0)
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return (0);
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device_printf(sc->dev, "CODEC semaphore timeout\n");
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return ETIMEDOUT;
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}
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static int
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ich_rdcd(kobj_t obj, void *devinfo, int regno)
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{
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struct sc_info *sc = (struct sc_info *)devinfo;
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regno &= 0xff;
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ich_waitcd(sc);
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return bus_space_read_2(sc->nambart, sc->nambarh, regno);
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}
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static int
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ich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data)
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{
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struct sc_info *sc = (struct sc_info *)devinfo;
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regno &= 0xff;
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ich_waitcd(sc);
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bus_space_write_2(sc->nambart, sc->nambarh, regno, data);
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return 0;
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}
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static kobj_method_t ich_ac97_methods[] = {
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KOBJMETHOD(ac97_read, ich_rdcd),
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KOBJMETHOD(ac97_write, ich_wrcd),
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{ 0, 0 }
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};
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AC97_DECLARE(ich_ac97);
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/* -------------------------------------------------------------------- */
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/* common routines */
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static void
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ich_filldtbl(struct sc_chinfo *ch)
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{
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struct sc_info *sc = ch->parent;
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u_int32_t base;
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int i;
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base = sndbuf_getbufaddr(ch->buffer);
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if (ch->blksz > sc->bufsz / ch->blkcnt)
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ch->blksz = sc->bufsz / ch->blkcnt;
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sndbuf_resize(ch->buffer, ch->blkcnt, ch->blksz);
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ch->blksz = sndbuf_getblksz(ch->buffer);
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for (i = 0; i < ICH_DTBL_LENGTH; i++) {
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ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt));
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ch->dtbl[i].length = ICH_BDC_IOC
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| (ch->blksz / ch->parent->sample_size);
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}
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}
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static int
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ich_resetchan(struct sc_info *sc, int num)
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{
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int i, cr, regbase;
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if (num == 0)
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regbase = ICH_REG_PO_BASE;
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else if (num == 1)
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regbase = ICH_REG_PI_BASE;
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else if (num == 2)
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regbase = ICH_REG_MC_BASE;
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else
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return ENXIO;
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ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1);
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#if 1
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/* This may result in no sound output on NForce 2 MBs, see PR 73987 */
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DELAY(100);
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#else
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(void)ich_rd(sc, regbase + ICH_REG_X_CR, 1);
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#endif
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ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1);
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for (i = 0; i < ICH_TIMEOUT; i++) {
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cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1);
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if (cr == 0)
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return 0;
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}
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device_printf(sc->dev, "cannot reset channel %d\n", num);
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return ENXIO;
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}
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/* -------------------------------------------------------------------- */
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/* channel interface */
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static void *
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ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
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{
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struct sc_info *sc = devinfo;
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struct sc_chinfo *ch;
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unsigned int num;
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ICH_LOCK(sc);
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num = sc->chnum++;
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ch = &sc->ch[num];
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ch->num = num;
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ch->buffer = b;
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ch->channel = c;
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ch->parent = sc;
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ch->run = 0;
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ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH);
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ch->desc_addr = sc->desc_addr + (ch->num * ICH_DTBL_LENGTH) *
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sizeof(struct ich_desc);
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ch->blkcnt = 2;
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ch->blksz = sc->bufsz / ch->blkcnt;
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switch(ch->num) {
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case 0: /* play */
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KASSERT(dir == PCMDIR_PLAY, ("wrong direction"));
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ch->regbase = ICH_REG_PO_BASE;
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ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0;
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ch->imask = ICH_GLOB_STA_POINT;
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break;
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case 1: /* record */
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KASSERT(dir == PCMDIR_REC, ("wrong direction"));
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ch->regbase = ICH_REG_PI_BASE;
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ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0;
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ch->imask = ICH_GLOB_STA_PIINT;
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break;
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case 2: /* mic */
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KASSERT(dir == PCMDIR_REC, ("wrong direction"));
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ch->regbase = ICH_REG_MC_BASE;
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ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0;
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ch->imask = ICH_GLOB_STA_MINT;
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break;
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default:
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return NULL;
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}
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ICH_UNLOCK(sc);
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if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz) != 0)
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return NULL;
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ICH_LOCK(sc);
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ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4);
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ICH_UNLOCK(sc);
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return ch;
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}
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static int
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ichchan_setformat(kobj_t obj, void *data, u_int32_t format)
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{
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return 0;
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}
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static int
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ichchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
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{
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struct sc_chinfo *ch = data;
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struct sc_info *sc = ch->parent;
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if (ch->spdreg) {
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int r, ac97rate;
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ICH_LOCK(sc);
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if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000)
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sc->ac97rate = 48000;
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ac97rate = sc->ac97rate;
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ICH_UNLOCK(sc);
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r = (speed * 48000) / ac97rate;
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/*
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* Cast the return value of ac97_setrate() to u_int so that
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* the math don't overflow into the negative range.
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*/
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ch->spd = ((u_int)ac97_setrate(sc->codec, ch->spdreg, r) *
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ac97rate) / 48000;
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} else {
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ch->spd = 48000;
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}
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return ch->spd;
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}
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static int
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ichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
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{
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struct sc_chinfo *ch = data;
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struct sc_info *sc = ch->parent;
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ch->blksz = blocksize;
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ich_filldtbl(ch);
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ICH_LOCK(sc);
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ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1);
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ICH_UNLOCK(sc);
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return ch->blksz;
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}
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static int
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ichchan_trigger(kobj_t obj, void *data, int go)
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{
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struct sc_chinfo *ch = data;
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struct sc_info *sc = ch->parent;
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switch (go) {
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case PCMTRIG_START:
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ch->run = 1;
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ICH_LOCK(sc);
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ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4);
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ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1);
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ICH_UNLOCK(sc);
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break;
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case PCMTRIG_ABORT:
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ICH_LOCK(sc);
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ich_resetchan(sc, ch->num);
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ICH_UNLOCK(sc);
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ch->run = 0;
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break;
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}
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return 0;
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}
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static int
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ichchan_getptr(kobj_t obj, void *data)
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{
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struct sc_chinfo *ch = data;
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struct sc_info *sc = ch->parent;
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u_int32_t pos;
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ICH_LOCK(sc);
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ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt;
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ICH_UNLOCK(sc);
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pos = ch->civ * ch->blksz;
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return pos;
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}
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static struct pcmchan_caps *
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ichchan_getcaps(kobj_t obj, void *data)
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{
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struct sc_chinfo *ch = data;
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return ch->spdreg? &ich_vrcaps : &ich_caps;
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}
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static kobj_method_t ichchan_methods[] = {
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KOBJMETHOD(channel_init, ichchan_init),
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KOBJMETHOD(channel_setformat, ichchan_setformat),
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KOBJMETHOD(channel_setspeed, ichchan_setspeed),
|
|
KOBJMETHOD(channel_setblocksize, ichchan_setblocksize),
|
|
KOBJMETHOD(channel_trigger, ichchan_trigger),
|
|
KOBJMETHOD(channel_getptr, ichchan_getptr),
|
|
KOBJMETHOD(channel_getcaps, ichchan_getcaps),
|
|
{ 0, 0 }
|
|
};
|
|
CHANNEL_DECLARE(ichchan);
|
|
|
|
/* -------------------------------------------------------------------- */
|
|
/* The interrupt handler */
|
|
|
|
static void
|
|
ich_intr(void *p)
|
|
{
|
|
struct sc_info *sc = (struct sc_info *)p;
|
|
struct sc_chinfo *ch;
|
|
u_int32_t cbi, lbi, lvi, st, gs;
|
|
int i;
|
|
|
|
ICH_LOCK(sc);
|
|
gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK;
|
|
if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) {
|
|
/* Clear resume interrupt(s) - nothing doing with them */
|
|
ich_wr(sc, ICH_REG_GLOB_STA, gs, 4);
|
|
}
|
|
gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES);
|
|
|
|
for (i = 0; i < 3; i++) {
|
|
ch = &sc->ch[i];
|
|
if ((ch->imask & gs) == 0)
|
|
continue;
|
|
gs &= ~ch->imask;
|
|
st = ich_rd(sc, ch->regbase +
|
|
(sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR),
|
|
2);
|
|
st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI;
|
|
if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) {
|
|
/* block complete - update buffer */
|
|
if (ch->run) {
|
|
ICH_UNLOCK(sc);
|
|
chn_intr(ch->channel);
|
|
ICH_LOCK(sc);
|
|
}
|
|
lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1);
|
|
cbi = ch->civ % ch->blkcnt;
|
|
if (cbi == 0)
|
|
cbi = ch->blkcnt - 1;
|
|
else
|
|
cbi--;
|
|
lbi = lvi % ch->blkcnt;
|
|
if (cbi >= lbi)
|
|
lvi += cbi - lbi;
|
|
else
|
|
lvi += cbi + ch->blkcnt - lbi;
|
|
lvi %= ICH_DTBL_LENGTH;
|
|
ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1);
|
|
|
|
}
|
|
/* clear status bit */
|
|
ich_wr(sc, ch->regbase +
|
|
(sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR),
|
|
st, 2);
|
|
}
|
|
ICH_UNLOCK(sc);
|
|
if (gs != 0) {
|
|
device_printf(sc->dev,
|
|
"Unhandled interrupt, gs_intr = %x\n", gs);
|
|
}
|
|
}
|
|
|
|
/* ------------------------------------------------------------------------- */
|
|
/* Sysctl to control ac97 speed (some boards appear to end up using
|
|
* XTAL_IN rather than BIT_CLK for link timing).
|
|
*/
|
|
|
|
static int
|
|
ich_initsys(struct sc_info* sc)
|
|
{
|
|
#ifdef SND_DYNSYSCTL
|
|
SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev),
|
|
SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)),
|
|
OID_AUTO, "ac97rate", CTLFLAG_RW,
|
|
&sc->ac97rate, 48000,
|
|
"AC97 link rate (default = 48000)");
|
|
#endif /* SND_DYNSYSCTL */
|
|
return 0;
|
|
}
|
|
|
|
/* -------------------------------------------------------------------- */
|
|
/* Calibrate card to determine the clock source. The source maybe a
|
|
* function of the ac97 codec initialization code (to be investigated).
|
|
*/
|
|
|
|
static
|
|
void ich_calibrate(void *arg)
|
|
{
|
|
struct sc_info *sc;
|
|
struct sc_chinfo *ch;
|
|
struct timeval t1, t2;
|
|
u_int8_t ociv, nciv;
|
|
u_int32_t wait_us, actual_48k_rate, bytes;
|
|
|
|
sc = (struct sc_info *)arg;
|
|
ch = &sc->ch[1];
|
|
|
|
if (sc->use_intrhook)
|
|
config_intrhook_disestablish(&sc->intrhook);
|
|
|
|
/*
|
|
* Grab audio from input for fixed interval and compare how
|
|
* much we actually get with what we expect. Interval needs
|
|
* to be sufficiently short that no interrupts are
|
|
* generated.
|
|
*/
|
|
|
|
KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction"));
|
|
|
|
bytes = sndbuf_getsize(ch->buffer) / 2;
|
|
ichchan_setblocksize(0, ch, bytes);
|
|
|
|
/*
|
|
* our data format is stereo, 16 bit so each sample is 4 bytes.
|
|
* assuming we get 48000 samples per second, we get 192000 bytes/sec.
|
|
* we're going to start recording with interrupts disabled and measure
|
|
* the time taken for one block to complete. we know the block size,
|
|
* we know the time in microseconds, we calculate the sample rate:
|
|
*
|
|
* actual_rate [bps] = bytes / (time [s] * 4)
|
|
* actual_rate [bps] = (bytes * 1000000) / (time [us] * 4)
|
|
* actual_rate [Hz] = (bytes * 250000) / time [us]
|
|
*/
|
|
|
|
/* prepare */
|
|
ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1);
|
|
nciv = ociv;
|
|
ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)(ch->desc_addr), 4);
|
|
|
|
/* start */
|
|
microtime(&t1);
|
|
ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1);
|
|
|
|
/* wait */
|
|
while (nciv == ociv) {
|
|
microtime(&t2);
|
|
if (t2.tv_sec - t1.tv_sec > 1)
|
|
break;
|
|
nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1);
|
|
}
|
|
microtime(&t2);
|
|
|
|
/* stop */
|
|
ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1);
|
|
|
|
/* reset */
|
|
DELAY(100);
|
|
ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1);
|
|
|
|
/* turn time delta into us */
|
|
wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec;
|
|
|
|
if (nciv == ociv) {
|
|
device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us);
|
|
return;
|
|
}
|
|
|
|
actual_48k_rate = (bytes * 250000) / wait_us;
|
|
|
|
if (actual_48k_rate < 47500 || actual_48k_rate > 48500) {
|
|
sc->ac97rate = actual_48k_rate;
|
|
} else {
|
|
sc->ac97rate = 48000;
|
|
}
|
|
|
|
if (bootverbose || sc->ac97rate != 48000) {
|
|
device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate);
|
|
if (sc->ac97rate != actual_48k_rate)
|
|
printf(", will use %d Hz", sc->ac97rate);
|
|
printf("\n");
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
/* -------------------------------------------------------------------- */
|
|
/* Probe and attach the card */
|
|
|
|
static void
|
|
ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
|
|
{
|
|
struct sc_info *sc = (struct sc_info *)arg;
|
|
sc->desc_addr = segs->ds_addr;
|
|
return;
|
|
}
|
|
|
|
static int
|
|
ich_init(struct sc_info *sc)
|
|
{
|
|
u_int32_t stat;
|
|
int sz;
|
|
|
|
ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4);
|
|
DELAY(600000);
|
|
stat = ich_rd(sc, ICH_REG_GLOB_STA, 4);
|
|
|
|
if ((stat & ICH_GLOB_STA_PCR) == 0) {
|
|
/* ICH4/ICH5 may fail when busmastering is enabled. Continue */
|
|
if (sc->vendor == INTEL_VENDORID && (
|
|
sc->devid == INTEL_82801DB || sc->devid == INTEL_82801EB ||
|
|
sc->devid == INTEL_6300ESB || sc->devid == INTEL_82801FB ||
|
|
sc->devid == INTEL_82801GB)) {
|
|
sc->flags |= IGNORE_PCR;
|
|
device_printf(sc->dev, "primary codec not ready!\n");
|
|
}
|
|
}
|
|
|
|
ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4);
|
|
|
|
if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1))
|
|
return ENXIO;
|
|
if (sc->hasmic && ich_resetchan(sc, 2))
|
|
return ENXIO;
|
|
|
|
if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, &sc->dtmap))
|
|
return ENOSPC;
|
|
|
|
sz = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3;
|
|
if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sz, ich_setmap, sc, 0)) {
|
|
bus_dmamem_free(sc->dmat, (void **)&sc->dtbl, sc->dtmap);
|
|
return ENOSPC;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
ich_pci_probe(device_t dev)
|
|
{
|
|
int i;
|
|
uint16_t devid, vendor;
|
|
|
|
vendor = pci_get_vendor(dev);
|
|
devid = pci_get_device(dev);
|
|
for (i = 0; i < sizeof(ich_devs)/sizeof(ich_devs[0]); i++) {
|
|
if (vendor == ich_devs[i].vendor &&
|
|
devid == ich_devs[i].devid) {
|
|
device_set_desc(dev, ich_devs[i].name);
|
|
/* allow a better driver to override us */
|
|
if ((ich_devs[i].options & PROBE_LOW) != 0)
|
|
return (BUS_PROBE_LOW_PRIORITY);
|
|
return (BUS_PROBE_DEFAULT);
|
|
}
|
|
}
|
|
return (ENXIO);
|
|
}
|
|
|
|
static int
|
|
ich_pci_attach(device_t dev)
|
|
{
|
|
uint32_t subdev;
|
|
u_int16_t extcaps;
|
|
uint16_t devid, vendor;
|
|
struct sc_info *sc;
|
|
char status[SND_STATUSLEN];
|
|
|
|
if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) {
|
|
device_printf(dev, "cannot allocate softc\n");
|
|
return ENXIO;
|
|
}
|
|
|
|
sc->ich_lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc");
|
|
sc->dev = dev;
|
|
|
|
vendor = sc->vendor = pci_get_vendor(dev);
|
|
devid = sc->devid = pci_get_device(dev);
|
|
subdev = (pci_get_subdevice(dev) << 16) | pci_get_subvendor(dev);
|
|
/*
|
|
* The SiS 7012 register set isn't quite like the standard ich.
|
|
* There really should be a general "quirks" mechanism.
|
|
*/
|
|
if (vendor == SIS_VENDORID && devid == SIS_7012) {
|
|
sc->swap_reg = 1;
|
|
sc->sample_size = 1;
|
|
} else {
|
|
sc->swap_reg = 0;
|
|
sc->sample_size = 2;
|
|
}
|
|
|
|
/*
|
|
* Enable bus master. On ich4/5 this may prevent the detection of
|
|
* the primary codec becoming ready in ich_init().
|
|
*/
|
|
pci_enable_busmaster(dev);
|
|
|
|
/*
|
|
* By default, ich4 has NAMBAR and NABMBAR i/o spaces as
|
|
* read-only. Need to enable "legacy support", by poking into
|
|
* pci config space. The driver should use MMBAR and MBBAR,
|
|
* but doing so will mess things up here. ich4 has enough new
|
|
* features it warrants it's own driver.
|
|
*/
|
|
if (vendor == INTEL_VENDORID && (devid == INTEL_82801DB ||
|
|
devid == INTEL_82801EB || devid == INTEL_6300ESB ||
|
|
devid == INTEL_82801FB || devid == INTEL_82801GB)) {
|
|
sc->nambarid = PCIR_MMBAR;
|
|
sc->nabmbarid = PCIR_MBBAR;
|
|
sc->regtype = SYS_RES_MEMORY;
|
|
pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1);
|
|
} else {
|
|
sc->nambarid = PCIR_NAMBAR;
|
|
sc->nabmbarid = PCIR_NABMBAR;
|
|
sc->regtype = SYS_RES_IOPORT;
|
|
}
|
|
|
|
sc->nambar = bus_alloc_resource_any(dev, sc->regtype,
|
|
&sc->nambarid, RF_ACTIVE);
|
|
sc->nabmbar = bus_alloc_resource_any(dev, sc->regtype,
|
|
&sc->nabmbarid, RF_ACTIVE);
|
|
|
|
if (!sc->nambar || !sc->nabmbar) {
|
|
device_printf(dev, "unable to map IO port space\n");
|
|
goto bad;
|
|
}
|
|
|
|
sc->nambart = rman_get_bustag(sc->nambar);
|
|
sc->nambarh = rman_get_bushandle(sc->nambar);
|
|
sc->nabmbart = rman_get_bustag(sc->nabmbar);
|
|
sc->nabmbarh = rman_get_bushandle(sc->nabmbar);
|
|
|
|
sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ);
|
|
if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
|
|
NULL, NULL, sc->bufsz, 1, 0x3ffff, 0,
|
|
NULL, NULL, &sc->dmat) != 0) {
|
|
device_printf(dev, "unable to create dma tag\n");
|
|
goto bad;
|
|
}
|
|
|
|
sc->irqid = 0;
|
|
sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
|
|
RF_ACTIVE | RF_SHAREABLE);
|
|
if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, sc, &sc->ih)) {
|
|
device_printf(dev, "unable to map interrupt\n");
|
|
goto bad;
|
|
}
|
|
|
|
if (ich_init(sc)) {
|
|
device_printf(dev, "unable to initialize the card\n");
|
|
goto bad;
|
|
}
|
|
|
|
sc->codec = AC97_CREATE(dev, sc, ich_ac97);
|
|
if (sc->codec == NULL)
|
|
goto bad;
|
|
|
|
/*
|
|
* Turn on inverted external amplifier sense flags for few
|
|
* 'special' boards.
|
|
*/
|
|
switch (subdev) {
|
|
case 0x202f161f: /* Gateway 7326GZ */
|
|
case 0x203a161f: /* Gateway 4028GZ */
|
|
case 0x8144104d: /* Sony VAIO PCG-TR* */
|
|
case 0x8197104d: /* Sony S1XP */
|
|
ac97_setflags(sc->codec, ac97_getflags(sc->codec) | AC97_F_EAPD_INV);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
mixer_init(dev, ac97_getmixerclass(), sc->codec);
|
|
|
|
/* check and set VRA function */
|
|
extcaps = ac97_getextcaps(sc->codec);
|
|
sc->hasvra = extcaps & AC97_EXTCAP_VRA;
|
|
sc->hasvrm = extcaps & AC97_EXTCAP_VRM;
|
|
sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL;
|
|
ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm);
|
|
|
|
if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1))
|
|
goto bad;
|
|
|
|
pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */
|
|
pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */
|
|
if (sc->hasmic)
|
|
pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */
|
|
|
|
snprintf(status, SND_STATUSLEN, "at io 0x%lx, 0x%lx irq %ld bufsz %u %s",
|
|
rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), rman_get_start(sc->irq), sc->bufsz,PCM_KLDSTRING(snd_ich));
|
|
|
|
pcm_setstatus(dev, status);
|
|
|
|
ich_initsys(sc);
|
|
|
|
sc->intrhook.ich_func = ich_calibrate;
|
|
sc->intrhook.ich_arg = sc;
|
|
sc->use_intrhook = 1;
|
|
if (config_intrhook_establish(&sc->intrhook) != 0) {
|
|
device_printf(dev, "Cannot establish calibration hook, will calibrate now\n");
|
|
sc->use_intrhook = 0;
|
|
ich_calibrate(sc);
|
|
}
|
|
|
|
return 0;
|
|
|
|
bad:
|
|
if (sc->codec)
|
|
ac97_destroy(sc->codec);
|
|
if (sc->ih)
|
|
bus_teardown_intr(dev, sc->irq, sc->ih);
|
|
if (sc->irq)
|
|
bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
|
|
if (sc->nambar)
|
|
bus_release_resource(dev, sc->regtype,
|
|
sc->nambarid, sc->nambar);
|
|
if (sc->nabmbar)
|
|
bus_release_resource(dev, sc->regtype,
|
|
sc->nabmbarid, sc->nabmbar);
|
|
if (sc->ich_lock)
|
|
snd_mtxfree(sc->ich_lock);
|
|
free(sc, M_DEVBUF);
|
|
return ENXIO;
|
|
}
|
|
|
|
static int
|
|
ich_pci_detach(device_t dev)
|
|
{
|
|
struct sc_info *sc;
|
|
int r;
|
|
|
|
r = pcm_unregister(dev);
|
|
if (r)
|
|
return r;
|
|
sc = pcm_getdevinfo(dev);
|
|
|
|
bus_teardown_intr(dev, sc->irq, sc->ih);
|
|
bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
|
|
bus_release_resource(dev, sc->regtype, sc->nambarid, sc->nambar);
|
|
bus_release_resource(dev, sc->regtype, sc->nabmbarid, sc->nabmbar);
|
|
bus_dma_tag_destroy(sc->dmat);
|
|
snd_mtxfree(sc->ich_lock);
|
|
free(sc, M_DEVBUF);
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
ich_pci_codec_reset(struct sc_info *sc)
|
|
{
|
|
int i;
|
|
uint32_t control;
|
|
|
|
control = ich_rd(sc, ICH_REG_GLOB_CNT, 4);
|
|
control &= ~(ICH_GLOB_CTL_SHUT);
|
|
control |= (control & ICH_GLOB_CTL_COLD) ?
|
|
ICH_GLOB_CTL_WARM : ICH_GLOB_CTL_COLD;
|
|
ich_wr(sc, ICH_REG_GLOB_CNT, control, 4);
|
|
|
|
for (i = 500000; i; i--) {
|
|
if (ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_PCR)
|
|
break; /* or ICH_SCR? */
|
|
DELAY(1);
|
|
}
|
|
|
|
if (i <= 0)
|
|
printf("%s: time out\n", __func__);
|
|
}
|
|
|
|
static int
|
|
ich_pci_suspend(device_t dev)
|
|
{
|
|
struct sc_info *sc;
|
|
int i;
|
|
|
|
sc = pcm_getdevinfo(dev);
|
|
ICH_LOCK(sc);
|
|
for (i = 0 ; i < 3; i++) {
|
|
sc->ch[i].run_save = sc->ch[i].run;
|
|
if (sc->ch[i].run) {
|
|
ICH_UNLOCK(sc);
|
|
ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT);
|
|
ICH_LOCK(sc);
|
|
}
|
|
}
|
|
ICH_UNLOCK(sc);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
ich_pci_resume(device_t dev)
|
|
{
|
|
struct sc_info *sc;
|
|
int i;
|
|
|
|
sc = pcm_getdevinfo(dev);
|
|
|
|
if (sc->regtype == SYS_RES_IOPORT)
|
|
pci_enable_io(dev, SYS_RES_IOPORT);
|
|
else
|
|
pci_enable_io(dev, SYS_RES_MEMORY);
|
|
pci_enable_busmaster(dev);
|
|
|
|
ICH_LOCK(sc);
|
|
/* Reinit audio device */
|
|
if (ich_init(sc) == -1) {
|
|
device_printf(dev, "unable to reinitialize the card\n");
|
|
ICH_UNLOCK(sc);
|
|
return ENXIO;
|
|
}
|
|
/* Reinit mixer */
|
|
ich_pci_codec_reset(sc);
|
|
ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm);
|
|
if (mixer_reinit(dev) == -1) {
|
|
device_printf(dev, "unable to reinitialize the mixer\n");
|
|
ICH_UNLOCK(sc);
|
|
return ENXIO;
|
|
}
|
|
/* Re-start DMA engines */
|
|
for (i = 0 ; i < 3; i++) {
|
|
struct sc_chinfo *ch = &sc->ch[i];
|
|
if (sc->ch[i].run_save) {
|
|
ICH_UNLOCK(sc);
|
|
ichchan_setblocksize(0, ch, ch->blksz);
|
|
ichchan_setspeed(0, ch, ch->spd);
|
|
ichchan_trigger(0, ch, PCMTRIG_START);
|
|
ICH_LOCK(sc);
|
|
}
|
|
}
|
|
ICH_UNLOCK(sc);
|
|
return 0;
|
|
}
|
|
|
|
static device_method_t ich_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, ich_pci_probe),
|
|
DEVMETHOD(device_attach, ich_pci_attach),
|
|
DEVMETHOD(device_detach, ich_pci_detach),
|
|
DEVMETHOD(device_suspend, ich_pci_suspend),
|
|
DEVMETHOD(device_resume, ich_pci_resume),
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t ich_driver = {
|
|
"pcm",
|
|
ich_methods,
|
|
PCM_SOFTC_SIZE,
|
|
};
|
|
|
|
DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0);
|
|
MODULE_DEPEND(snd_ich, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
|
|
MODULE_VERSION(snd_ich, 1);
|