d3c7b9a08a
Bring in a driver for the LSI Logic MPT2 6Gb SAS controllers. This driver supports basic I/O, and works with SAS and SATA drives and expanders. Basic error recovery works (i.e. timeouts and aborts) as well. Integrated RAID isn't supported yet, and there are some known bugs. So this isn't ready for production use, but is certainly ready for testing and additional development. For the moment, new commits to this driver should go into the FreeBSD Perforce repository first (//depot/projects/mps/...) and then get merged into -current once they've been vetted. This has only been added to the amd64 GENERIC, since that is the only architecture I have tested this driver with. Submitted by: scottl Discussed with: imp, gibbs, will Sponsored by: Yahoo, Spectra Logic Corporation
1415 lines
69 KiB
C
1415 lines
69 KiB
C
/* $FreeBSD$ */
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/*
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* Copyright (c) 2000-2009 LSI Corporation.
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*
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*
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* Name: mpi2_ioc.h
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* Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
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* Creation Date: October 11, 2006
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*
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* mpi2_ioc.h Version: 02.00.13
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*
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* Version History
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* ---------------
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*
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* Date Version Description
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* -------- -------- ------------------------------------------------------
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* 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
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* 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to
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* MaxTargets.
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* Added TotalImageSize field to FWDownload Request.
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* Added reserved words to FWUpload Request.
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* 06-26-07 02.00.02 Added IR Configuration Change List Event.
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* 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit
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* request and replaced it with
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* ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
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* Replaced the MinReplyQueueDepth field of the IOCFacts
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* reply with MaxReplyDescriptorPostQueueDepth.
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* Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
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* depth for the Reply Descriptor Post Queue.
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* Added SASAddress field to Initiator Device Table
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* Overflow Event data.
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* 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
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* for SAS Initiator Device Status Change Event data.
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* Modified Reason Code defines for SAS Topology Change
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* List Event data, including adding a bit for PHY Vacant
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* status, and adding a mask for the Reason Code.
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* Added define for
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* MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
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* Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
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* 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of
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* the IOCFacts Reply.
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* Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
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* Moved MPI2_VERSION_UNION to mpi2.h.
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* Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
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* instead of enables, and added SASBroadcastPrimitiveMasks
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* field.
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* Added Log Entry Added Event and related structure.
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* 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
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* Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
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* Added MaxVolumes and MaxPersistentEntries fields to
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* IOCFacts reply.
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* Added ProtocalFlags and IOCCapabilities fields to
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* MPI2_FW_IMAGE_HEADER.
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* Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
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* 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
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* a U16 (from a U32).
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* Removed extra 's' from EventMasks name.
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* 06-27-08 02.00.08 Fixed an offset in a comment.
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* 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
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* Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
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* renamed MinReplyFrameSize to ReplyFrameSize.
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* Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
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* Added two new RAIDOperation values for Integrated RAID
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* Operations Status Event data.
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* Added four new IR Configuration Change List Event data
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* ReasonCode values.
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* Added two new ReasonCode defines for SAS Device Status
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* Change Event data.
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* Added three new DiscoveryStatus bits for the SAS
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* Discovery event data.
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* Added Multiplexing Status Change bit to the PhyStatus
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* field of the SAS Topology Change List event data.
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* Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
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* BootFlags are now product-specific.
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* Added defines for the indivdual signature bytes
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* for MPI2_INIT_IMAGE_FOOTER.
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* 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
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* Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
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* define.
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* Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
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* define.
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* Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
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* 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
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* Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
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* Added two new reason codes for SAS Device Status Change
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* Event.
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* Added new event: SAS PHY Counter.
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* 07-30-09 02.00.12 Added GPIO Interrupt event define and structure.
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* Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
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* Added new product id family for 2208.
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* 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
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* Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
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* Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
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* Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
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* Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
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* Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
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* Added Host Based Discovery Phy Event data.
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* Added defines for ProductID Product field
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* (MPI2_FW_HEADER_PID_).
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* Modified values for SAS ProductID Family
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* (MPI2_FW_HEADER_PID_FAMILY_).
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* --------------------------------------------------------------------------
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*/
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#ifndef MPI2_IOC_H
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#define MPI2_IOC_H
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/*****************************************************************************
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*
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* IOC Messages
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*
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*****************************************************************************/
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/****************************************************************************
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* IOCInit message
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****************************************************************************/
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/* IOCInit Request message */
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typedef struct _MPI2_IOC_INIT_REQUEST
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{
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U8 WhoInit; /* 0x00 */
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U8 Reserved1; /* 0x01 */
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U8 ChainOffset; /* 0x02 */
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U8 Function; /* 0x03 */
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U16 Reserved2; /* 0x04 */
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U8 Reserved3; /* 0x06 */
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U8 MsgFlags; /* 0x07 */
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U8 VP_ID; /* 0x08 */
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U8 VF_ID; /* 0x09 */
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U16 Reserved4; /* 0x0A */
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U16 MsgVersion; /* 0x0C */
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U16 HeaderVersion; /* 0x0E */
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U32 Reserved5; /* 0x10 */
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U16 Reserved6; /* 0x14 */
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U8 Reserved7; /* 0x16 */
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U8 HostMSIxVectors; /* 0x17 */
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U16 Reserved8; /* 0x18 */
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U16 SystemRequestFrameSize; /* 0x1A */
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U16 ReplyDescriptorPostQueueDepth; /* 0x1C */
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U16 ReplyFreeQueueDepth; /* 0x1E */
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U32 SenseBufferAddressHigh; /* 0x20 */
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U32 SystemReplyAddressHigh; /* 0x24 */
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U64 SystemRequestFrameBaseAddress; /* 0x28 */
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U64 ReplyDescriptorPostQueueAddress;/* 0x30 */
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U64 ReplyFreeQueueAddress; /* 0x38 */
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U64 TimeStamp; /* 0x40 */
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} MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
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Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
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/* WhoInit values */
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#define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
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#define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
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#define MPI2_WHOINIT_ROM_BIOS (0x02)
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#define MPI2_WHOINIT_PCI_PEER (0x03)
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#define MPI2_WHOINIT_HOST_DRIVER (0x04)
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#define MPI2_WHOINIT_MANUFACTURER (0x05)
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/* MsgVersion */
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#define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
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#define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
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#define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
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#define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
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/* HeaderVersion */
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#define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00)
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#define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8)
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#define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)
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#define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)
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/* minimum depth for the Reply Descriptor Post Queue */
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#define MPI2_RDPQ_DEPTH_MIN (16)
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/* IOCInit Reply message */
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typedef struct _MPI2_IOC_INIT_REPLY
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{
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U8 WhoInit; /* 0x00 */
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U8 Reserved1; /* 0x01 */
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U8 MsgLength; /* 0x02 */
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U8 Function; /* 0x03 */
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U16 Reserved2; /* 0x04 */
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U8 Reserved3; /* 0x06 */
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U8 MsgFlags; /* 0x07 */
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U8 VP_ID; /* 0x08 */
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U8 VF_ID; /* 0x09 */
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U16 Reserved4; /* 0x0A */
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U16 Reserved5; /* 0x0C */
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U16 IOCStatus; /* 0x0E */
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U32 IOCLogInfo; /* 0x10 */
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} MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY,
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Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t;
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/****************************************************************************
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* IOCFacts message
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****************************************************************************/
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/* IOCFacts Request message */
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typedef struct _MPI2_IOC_FACTS_REQUEST
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{
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U16 Reserved1; /* 0x00 */
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U8 ChainOffset; /* 0x02 */
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U8 Function; /* 0x03 */
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U16 Reserved2; /* 0x04 */
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U8 Reserved3; /* 0x06 */
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U8 MsgFlags; /* 0x07 */
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U8 VP_ID; /* 0x08 */
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U8 VF_ID; /* 0x09 */
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U16 Reserved4; /* 0x0A */
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} MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST,
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Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t;
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/* IOCFacts Reply message */
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typedef struct _MPI2_IOC_FACTS_REPLY
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{
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U16 MsgVersion; /* 0x00 */
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U8 MsgLength; /* 0x02 */
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U8 Function; /* 0x03 */
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U16 HeaderVersion; /* 0x04 */
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U8 IOCNumber; /* 0x06 */
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U8 MsgFlags; /* 0x07 */
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U8 VP_ID; /* 0x08 */
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U8 VF_ID; /* 0x09 */
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U16 Reserved1; /* 0x0A */
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U16 IOCExceptions; /* 0x0C */
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U16 IOCStatus; /* 0x0E */
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U32 IOCLogInfo; /* 0x10 */
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U8 MaxChainDepth; /* 0x14 */
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U8 WhoInit; /* 0x15 */
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U8 NumberOfPorts; /* 0x16 */
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U8 MaxMSIxVectors; /* 0x17 */
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U16 RequestCredit; /* 0x18 */
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U16 ProductID; /* 0x1A */
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U32 IOCCapabilities; /* 0x1C */
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MPI2_VERSION_UNION FWVersion; /* 0x20 */
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U16 IOCRequestFrameSize; /* 0x24 */
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U16 Reserved3; /* 0x26 */
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U16 MaxInitiators; /* 0x28 */
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U16 MaxTargets; /* 0x2A */
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U16 MaxSasExpanders; /* 0x2C */
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U16 MaxEnclosures; /* 0x2E */
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U16 ProtocolFlags; /* 0x30 */
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U16 HighPriorityCredit; /* 0x32 */
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U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */
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U8 ReplyFrameSize; /* 0x36 */
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U8 MaxVolumes; /* 0x37 */
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U16 MaxDevHandle; /* 0x38 */
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U16 MaxPersistentEntries; /* 0x3A */
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U16 MinDevHandle; /* 0x3C */
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U16 Reserved4; /* 0x3E */
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} MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY,
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Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t;
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/* MsgVersion */
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#define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
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#define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
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#define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
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#define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
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/* HeaderVersion */
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#define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
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#define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
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#define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
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#define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
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/* IOCExceptions */
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#define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
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#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)
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#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)
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#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)
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#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)
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#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)
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#define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
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#define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)
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#define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
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#define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
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#define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
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/* defines for WhoInit field are after the IOCInit Request */
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/* ProductID field uses MPI2_FW_HEADER_PID_ */
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/* IOCCapabilities */
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#define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000)
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#define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000)
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#define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000)
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#define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)
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#define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)
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#define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)
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#define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
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#define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
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#define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
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#define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
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#define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
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#define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
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#define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
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/* ProtocolFlags */
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#define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
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#define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
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/****************************************************************************
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* PortFacts message
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****************************************************************************/
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/* PortFacts Request message */
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typedef struct _MPI2_PORT_FACTS_REQUEST
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{
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U16 Reserved1; /* 0x00 */
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U8 ChainOffset; /* 0x02 */
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U8 Function; /* 0x03 */
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U16 Reserved2; /* 0x04 */
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U8 PortNumber; /* 0x06 */
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U8 MsgFlags; /* 0x07 */
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U8 VP_ID; /* 0x08 */
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U8 VF_ID; /* 0x09 */
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U16 Reserved3; /* 0x0A */
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} MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST,
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Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t;
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/* PortFacts Reply message */
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typedef struct _MPI2_PORT_FACTS_REPLY
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{
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U16 Reserved1; /* 0x00 */
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U8 MsgLength; /* 0x02 */
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U8 Function; /* 0x03 */
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U16 Reserved2; /* 0x04 */
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U8 PortNumber; /* 0x06 */
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U8 MsgFlags; /* 0x07 */
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U8 VP_ID; /* 0x08 */
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U8 VF_ID; /* 0x09 */
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U16 Reserved3; /* 0x0A */
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U16 Reserved4; /* 0x0C */
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U16 IOCStatus; /* 0x0E */
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U32 IOCLogInfo; /* 0x10 */
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U8 Reserved5; /* 0x14 */
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U8 PortType; /* 0x15 */
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U16 Reserved6; /* 0x16 */
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U16 MaxPostedCmdBuffers; /* 0x18 */
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U16 Reserved7; /* 0x1A */
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} MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY,
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Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t;
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/* PortType values */
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#define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00)
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#define MPI2_PORTFACTS_PORTTYPE_FC (0x10)
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#define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20)
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#define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30)
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#define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31)
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/****************************************************************************
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* PortEnable message
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****************************************************************************/
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/* PortEnable Request message */
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typedef struct _MPI2_PORT_ENABLE_REQUEST
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{
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U16 Reserved1; /* 0x00 */
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U8 ChainOffset; /* 0x02 */
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U8 Function; /* 0x03 */
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U8 Reserved2; /* 0x04 */
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U8 PortFlags; /* 0x05 */
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U8 Reserved3; /* 0x06 */
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U8 MsgFlags; /* 0x07 */
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U8 VP_ID; /* 0x08 */
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U8 VF_ID; /* 0x09 */
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U16 Reserved4; /* 0x0A */
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} MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST,
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Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t;
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/* PortEnable Reply message */
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typedef struct _MPI2_PORT_ENABLE_REPLY
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{
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U16 Reserved1; /* 0x00 */
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U8 MsgLength; /* 0x02 */
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U8 Function; /* 0x03 */
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U8 Reserved2; /* 0x04 */
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U8 PortFlags; /* 0x05 */
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U8 Reserved3; /* 0x06 */
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U8 MsgFlags; /* 0x07 */
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U8 VP_ID; /* 0x08 */
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U8 VF_ID; /* 0x09 */
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U16 Reserved4; /* 0x0A */
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U16 Reserved5; /* 0x0C */
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U16 IOCStatus; /* 0x0E */
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U32 IOCLogInfo; /* 0x10 */
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} MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY,
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Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t;
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/****************************************************************************
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* EventNotification message
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****************************************************************************/
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/* EventNotification Request message */
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#define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4)
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typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST
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{
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U16 Reserved1; /* 0x00 */
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U8 ChainOffset; /* 0x02 */
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U8 Function; /* 0x03 */
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U16 Reserved2; /* 0x04 */
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U8 Reserved3; /* 0x06 */
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U8 MsgFlags; /* 0x07 */
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U8 VP_ID; /* 0x08 */
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U8 VF_ID; /* 0x09 */
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U16 Reserved4; /* 0x0A */
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U32 Reserved5; /* 0x0C */
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U32 Reserved6; /* 0x10 */
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U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */
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U16 SASBroadcastPrimitiveMasks; /* 0x24 */
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U16 Reserved7; /* 0x26 */
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U32 Reserved8; /* 0x28 */
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} MPI2_EVENT_NOTIFICATION_REQUEST,
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MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
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Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t;
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/* EventNotification Reply message */
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typedef struct _MPI2_EVENT_NOTIFICATION_REPLY
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{
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U16 EventDataLength; /* 0x00 */
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U8 MsgLength; /* 0x02 */
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U8 Function; /* 0x03 */
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U16 Reserved1; /* 0x04 */
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U8 AckRequired; /* 0x06 */
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U8 MsgFlags; /* 0x07 */
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U8 VP_ID; /* 0x08 */
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U8 VF_ID; /* 0x09 */
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U16 Reserved2; /* 0x0A */
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U16 Reserved3; /* 0x0C */
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U16 IOCStatus; /* 0x0E */
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U32 IOCLogInfo; /* 0x10 */
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U16 Event; /* 0x14 */
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U16 Reserved4; /* 0x16 */
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U32 EventContext; /* 0x18 */
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U32 EventData[1]; /* 0x1C */
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} MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY,
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Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t;
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/* AckRequired */
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#define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
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#define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
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/* Event */
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#define MPI2_EVENT_LOG_DATA (0x0001)
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#define MPI2_EVENT_STATE_CHANGE (0x0002)
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#define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)
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#define MPI2_EVENT_EVENT_CHANGE (0x000A)
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#define MPI2_EVENT_TASK_SET_FULL (0x000E)
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#define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)
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#define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)
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#define MPI2_EVENT_SAS_DISCOVERY (0x0016)
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#define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)
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#define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)
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#define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
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#define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
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#define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
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#define MPI2_EVENT_IR_VOLUME (0x001E)
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#define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
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#define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
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#define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
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#define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
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#define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
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#define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024)
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/* Log Entry Added Event data */
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/* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
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#define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)
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typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED
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{
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U64 TimeStamp; /* 0x00 */
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U32 Reserved1; /* 0x08 */
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U16 LogSequence; /* 0x0C */
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U16 LogEntryQualifier; /* 0x0E */
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U8 VP_ID; /* 0x10 */
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U8 VF_ID; /* 0x11 */
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U16 Reserved2; /* 0x12 */
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U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */
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} MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
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MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
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Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t;
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/* GPIO Interrupt Event data */
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typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT
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{
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U8 GPIONum; /* 0x00 */
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U8 Reserved1; /* 0x01 */
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U16 Reserved2; /* 0x02 */
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} MPI2_EVENT_DATA_GPIO_INTERRUPT,
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MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
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Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t;
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/* Hard Reset Received Event data */
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typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
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{
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U8 Reserved1; /* 0x00 */
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U8 Port; /* 0x01 */
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U16 Reserved2; /* 0x02 */
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} MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
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MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
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Mpi2EventDataHardResetReceived_t,
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MPI2_POINTER pMpi2EventDataHardResetReceived_t;
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/* Task Set Full Event data */
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typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL
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{
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U16 DevHandle; /* 0x00 */
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U16 CurrentDepth; /* 0x02 */
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} MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
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Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t;
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/* SAS Device Status Change Event data */
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typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
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{
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U16 TaskTag; /* 0x00 */
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U8 ReasonCode; /* 0x02 */
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U8 Reserved1; /* 0x03 */
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U8 ASC; /* 0x04 */
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U8 ASCQ; /* 0x05 */
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U16 DevHandle; /* 0x06 */
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U32 Reserved2; /* 0x08 */
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U64 SASAddress; /* 0x0C */
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U8 LUN[8]; /* 0x14 */
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} MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
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MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
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Mpi2EventDataSasDeviceStatusChange_t,
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MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t;
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/* SAS Device Status Change Event data ReasonCode values */
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#define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)
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#define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)
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#define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
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#define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
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#define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
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#define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
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#define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
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#define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
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#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
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#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
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#define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10)
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#define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11)
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#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12)
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/* Integrated RAID Operation Status Event data */
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typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS
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{
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U16 VolDevHandle; /* 0x00 */
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U16 Reserved1; /* 0x02 */
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U8 RAIDOperation; /* 0x04 */
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U8 PercentComplete; /* 0x05 */
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U16 Reserved2; /* 0x06 */
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U32 Resereved3; /* 0x08 */
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} MPI2_EVENT_DATA_IR_OPERATION_STATUS,
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MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
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Mpi2EventDataIrOperationStatus_t,
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MPI2_POINTER pMpi2EventDataIrOperationStatus_t;
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/* Integrated RAID Operation Status Event data RAIDOperation values */
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#define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00)
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#define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01)
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#define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02)
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#define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03)
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#define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04)
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/* Integrated RAID Volume Event data */
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typedef struct _MPI2_EVENT_DATA_IR_VOLUME
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{
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|
U16 VolDevHandle; /* 0x00 */
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U8 ReasonCode; /* 0x02 */
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U8 Reserved1; /* 0x03 */
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U32 NewValue; /* 0x04 */
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U32 PreviousValue; /* 0x08 */
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} MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME,
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Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t;
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/* Integrated RAID Volume Event data ReasonCode values */
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#define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01)
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#define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02)
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#define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03)
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/* Integrated RAID Physical Disk Event data */
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typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK
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{
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|
U16 Reserved1; /* 0x00 */
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|
U8 ReasonCode; /* 0x02 */
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|
U8 PhysDiskNum; /* 0x03 */
|
|
U16 PhysDiskDevHandle; /* 0x04 */
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U16 Reserved2; /* 0x06 */
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|
U16 Slot; /* 0x08 */
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U16 EnclosureHandle; /* 0x0A */
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U32 NewValue; /* 0x0C */
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U32 PreviousValue; /* 0x10 */
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} MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
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MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
|
|
Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t;
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/* Integrated RAID Physical Disk Event data ReasonCode values */
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|
#define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01)
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#define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02)
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#define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03)
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/* Integrated RAID Configuration Change List Event data */
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|
/*
|
|
* Host code (drivers, BIOS, utilities, etc.) should leave this define set to
|
|
* one and check NumElements at runtime.
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|
*/
|
|
#ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
|
|
#define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1)
|
|
#endif
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|
|
typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT
|
|
{
|
|
U16 ElementFlags; /* 0x00 */
|
|
U16 VolDevHandle; /* 0x02 */
|
|
U8 ReasonCode; /* 0x04 */
|
|
U8 PhysDiskNum; /* 0x05 */
|
|
U16 PhysDiskDevHandle; /* 0x06 */
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|
} MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
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Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t;
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|
|
/* IR Configuration Change List Event data ElementFlags values */
|
|
#define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F)
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#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000)
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#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
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#define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002)
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/* IR Configuration Change List Event data ReasonCode values */
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#define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01)
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#define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02)
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#define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03)
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|
#define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04)
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#define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05)
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#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06)
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|
#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07)
|
|
#define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08)
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|
#define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09)
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|
|
typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST
|
|
{
|
|
U8 NumElements; /* 0x00 */
|
|
U8 Reserved1; /* 0x01 */
|
|
U8 Reserved2; /* 0x02 */
|
|
U8 ConfigNum; /* 0x03 */
|
|
U32 Flags; /* 0x04 */
|
|
MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */
|
|
} MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
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|
MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
|
|
Mpi2EventDataIrConfigChangeList_t,
|
|
MPI2_POINTER pMpi2EventDataIrConfigChangeList_t;
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|
|
/* IR Configuration Change List Event data Flags values */
|
|
#define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001)
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|
/* SAS Discovery Event data */
|
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|
|
typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY
|
|
{
|
|
U8 Flags; /* 0x00 */
|
|
U8 ReasonCode; /* 0x01 */
|
|
U8 PhysicalPort; /* 0x02 */
|
|
U8 Reserved1; /* 0x03 */
|
|
U32 DiscoveryStatus; /* 0x04 */
|
|
} MPI2_EVENT_DATA_SAS_DISCOVERY,
|
|
MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
|
|
Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t;
|
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|
|
/* SAS Discovery Event data Flags values */
|
|
#define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02)
|
|
#define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01)
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|
|
/* SAS Discovery Event data ReasonCode values */
|
|
#define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01)
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|
#define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02)
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|
|
/* SAS Discovery Event data DiscoveryStatus values */
|
|
#define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
|
|
#define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000)
|
|
#define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000)
|
|
#define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
|
|
#define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000)
|
|
#define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
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|
#define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
|
|
#define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000)
|
|
#define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
|
|
#define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800)
|
|
#define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400)
|
|
#define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200)
|
|
#define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100)
|
|
#define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080)
|
|
#define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040)
|
|
#define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020)
|
|
#define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010)
|
|
#define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004)
|
|
#define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002)
|
|
#define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001)
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|
|
|
|
|
/* SAS Broadcast Primitive Event data */
|
|
|
|
typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
|
|
{
|
|
U8 PhyNum; /* 0x00 */
|
|
U8 Port; /* 0x01 */
|
|
U8 PortWidth; /* 0x02 */
|
|
U8 Primitive; /* 0x03 */
|
|
} MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
|
|
MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
|
|
Mpi2EventDataSasBroadcastPrimitive_t,
|
|
MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t;
|
|
|
|
/* defines for the Primitive field */
|
|
#define MPI2_EVENT_PRIMITIVE_CHANGE (0x01)
|
|
#define MPI2_EVENT_PRIMITIVE_SES (0x02)
|
|
#define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03)
|
|
#define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
|
|
#define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05)
|
|
#define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06)
|
|
#define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)
|
|
#define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)
|
|
|
|
|
|
/* SAS Initiator Device Status Change Event data */
|
|
|
|
typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
|
|
{
|
|
U8 ReasonCode; /* 0x00 */
|
|
U8 PhysicalPort; /* 0x01 */
|
|
U16 DevHandle; /* 0x02 */
|
|
U64 SASAddress; /* 0x04 */
|
|
} MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
|
|
MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
|
|
Mpi2EventDataSasInitDevStatusChange_t,
|
|
MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t;
|
|
|
|
/* SAS Initiator Device Status Change event ReasonCode values */
|
|
#define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01)
|
|
#define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
|
|
|
|
|
|
/* SAS Initiator Device Table Overflow Event data */
|
|
|
|
typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
|
|
{
|
|
U16 MaxInit; /* 0x00 */
|
|
U16 CurrentInit; /* 0x02 */
|
|
U64 SASAddress; /* 0x04 */
|
|
} MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
|
|
MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
|
|
Mpi2EventDataSasInitTableOverflow_t,
|
|
MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t;
|
|
|
|
|
|
/* SAS Topology Change List Event data */
|
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/*
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* Host code (drivers, BIOS, utilities, etc.) should leave this define set to
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* one and check NumEntries at runtime.
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*/
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#ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
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#define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1)
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#endif
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typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY
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{
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U16 AttachedDevHandle; /* 0x00 */
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U8 LinkRate; /* 0x02 */
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U8 PhyStatus; /* 0x03 */
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} MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
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Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t;
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typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
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{
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U16 EnclosureHandle; /* 0x00 */
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U16 ExpanderDevHandle; /* 0x02 */
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U8 NumPhys; /* 0x04 */
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U8 Reserved1; /* 0x05 */
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U16 Reserved2; /* 0x06 */
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U8 NumEntries; /* 0x08 */
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U8 StartPhyNum; /* 0x09 */
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U8 ExpStatus; /* 0x0A */
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U8 PhysicalPort; /* 0x0B */
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MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/
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} MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
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MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
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Mpi2EventDataSasTopologyChangeList_t,
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MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t;
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/* values for the ExpStatus field */
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#define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00)
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#define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)
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#define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
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#define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
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#define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
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/* defines for the LinkRate field */
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#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)
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#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
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#define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)
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#define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
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#define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
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#define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
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#define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
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#define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
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#define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
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#define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
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#define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)
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#define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
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#define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
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/* values for the PhyStatus field */
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#define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
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#define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)
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/* values for the PhyStatus ReasonCode sub-field */
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#define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)
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#define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)
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#define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)
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#define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)
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#define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)
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#define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)
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/* SAS Enclosure Device Status Change Event data */
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typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
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{
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U16 EnclosureHandle; /* 0x00 */
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U8 ReasonCode; /* 0x02 */
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U8 PhysicalPort; /* 0x03 */
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U64 EnclosureLogicalID; /* 0x04 */
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U16 NumSlots; /* 0x0C */
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U16 StartSlot; /* 0x0E */
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U32 PhyBits; /* 0x10 */
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} MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
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MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
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Mpi2EventDataSasEnclDevStatusChange_t,
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MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t;
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/* SAS Enclosure Device Status Change event ReasonCode values */
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#define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01)
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#define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02)
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/* SAS PHY Counter Event data */
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typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER
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{
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U64 TimeStamp; /* 0x00 */
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U32 Reserved1; /* 0x08 */
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U8 PhyEventCode; /* 0x0C */
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U8 PhyNum; /* 0x0D */
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U16 Reserved2; /* 0x0E */
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U32 PhyEventInfo; /* 0x10 */
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U8 CounterType; /* 0x14 */
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U8 ThresholdWindow; /* 0x15 */
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U8 TimeUnits; /* 0x16 */
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U8 Reserved3; /* 0x17 */
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U32 EventThreshold; /* 0x18 */
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U16 ThresholdFlags; /* 0x1C */
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U16 Reserved4; /* 0x1E */
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} MPI2_EVENT_DATA_SAS_PHY_COUNTER,
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MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
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Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t;
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/* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the PhyEventCode field */
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/* use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */
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/* use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */
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/* use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */
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/* Host Based Discovery Phy Event data */
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typedef struct _MPI2_EVENT_HBD_PHY_SAS
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{
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U8 Flags; /* 0x00 */
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U8 NegotiatedLinkRate; /* 0x01 */
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U8 PhyNum; /* 0x02 */
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U8 PhysicalPort; /* 0x03 */
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U32 Reserved1; /* 0x04 */
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U8 InitialFrame[28]; /* 0x08 */
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} MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS,
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Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t;
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/* values for the Flags field */
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#define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02)
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#define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01)
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/* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for the NegotiatedLinkRate field */
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typedef union _MPI2_EVENT_HBD_DESCRIPTOR
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{
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MPI2_EVENT_HBD_PHY_SAS Sas;
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} MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR,
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Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t;
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typedef struct _MPI2_EVENT_DATA_HBD_PHY
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{
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U8 DescriptorType; /* 0x00 */
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U8 Reserved1; /* 0x01 */
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U16 Reserved2; /* 0x02 */
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U32 Reserved3; /* 0x04 */
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MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */
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} MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY,
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Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t;
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/* values for the DescriptorType field */
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#define MPI2_EVENT_HBD_DT_SAS (0x01)
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/****************************************************************************
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* EventAck message
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****************************************************************************/
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/* EventAck Request message */
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typedef struct _MPI2_EVENT_ACK_REQUEST
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{
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U16 Reserved1; /* 0x00 */
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U8 ChainOffset; /* 0x02 */
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U8 Function; /* 0x03 */
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U16 Reserved2; /* 0x04 */
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U8 Reserved3; /* 0x06 */
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U8 MsgFlags; /* 0x07 */
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U8 VP_ID; /* 0x08 */
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U8 VF_ID; /* 0x09 */
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U16 Reserved4; /* 0x0A */
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U16 Event; /* 0x0C */
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U16 Reserved5; /* 0x0E */
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U32 EventContext; /* 0x10 */
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} MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST,
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Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t;
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/* EventAck Reply message */
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typedef struct _MPI2_EVENT_ACK_REPLY
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{
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U16 Reserved1; /* 0x00 */
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U8 MsgLength; /* 0x02 */
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U8 Function; /* 0x03 */
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U16 Reserved2; /* 0x04 */
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U8 Reserved3; /* 0x06 */
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U8 MsgFlags; /* 0x07 */
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U8 VP_ID; /* 0x08 */
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U8 VF_ID; /* 0x09 */
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U16 Reserved4; /* 0x0A */
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U16 Reserved5; /* 0x0C */
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U16 IOCStatus; /* 0x0E */
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U32 IOCLogInfo; /* 0x10 */
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} MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY,
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Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t;
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/****************************************************************************
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* FWDownload message
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****************************************************************************/
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/* FWDownload Request message */
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typedef struct _MPI2_FW_DOWNLOAD_REQUEST
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{
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U8 ImageType; /* 0x00 */
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U8 Reserved1; /* 0x01 */
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U8 ChainOffset; /* 0x02 */
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U8 Function; /* 0x03 */
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U16 Reserved2; /* 0x04 */
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U8 Reserved3; /* 0x06 */
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U8 MsgFlags; /* 0x07 */
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U8 VP_ID; /* 0x08 */
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U8 VF_ID; /* 0x09 */
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U16 Reserved4; /* 0x0A */
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U32 TotalImageSize; /* 0x0C */
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U32 Reserved5; /* 0x10 */
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MPI2_MPI_SGE_UNION SGL; /* 0x14 */
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} MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST,
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Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest;
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#define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
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#define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)
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#define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)
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#define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
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#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
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#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
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#define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
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#define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
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/* FWDownload TransactionContext Element */
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typedef struct _MPI2_FW_DOWNLOAD_TCSGE
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{
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U8 Reserved1; /* 0x00 */
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U8 ContextSize; /* 0x01 */
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U8 DetailsLength; /* 0x02 */
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U8 Flags; /* 0x03 */
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U32 Reserved2; /* 0x04 */
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U32 ImageOffset; /* 0x08 */
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U32 ImageSize; /* 0x0C */
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} MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE,
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Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t;
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/* FWDownload Reply message */
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typedef struct _MPI2_FW_DOWNLOAD_REPLY
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{
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U8 ImageType; /* 0x00 */
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U8 Reserved1; /* 0x01 */
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U8 MsgLength; /* 0x02 */
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U8 Function; /* 0x03 */
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U16 Reserved2; /* 0x04 */
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U8 Reserved3; /* 0x06 */
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U8 MsgFlags; /* 0x07 */
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U8 VP_ID; /* 0x08 */
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U8 VF_ID; /* 0x09 */
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U16 Reserved4; /* 0x0A */
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U16 Reserved5; /* 0x0C */
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U16 IOCStatus; /* 0x0E */
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U32 IOCLogInfo; /* 0x10 */
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} MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY,
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Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t;
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/****************************************************************************
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* FWUpload message
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****************************************************************************/
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/* FWUpload Request message */
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typedef struct _MPI2_FW_UPLOAD_REQUEST
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{
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U8 ImageType; /* 0x00 */
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U8 Reserved1; /* 0x01 */
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U8 ChainOffset; /* 0x02 */
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U8 Function; /* 0x03 */
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U16 Reserved2; /* 0x04 */
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U8 Reserved3; /* 0x06 */
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U8 MsgFlags; /* 0x07 */
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U8 VP_ID; /* 0x08 */
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U8 VF_ID; /* 0x09 */
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U16 Reserved4; /* 0x0A */
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U32 Reserved5; /* 0x0C */
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U32 Reserved6; /* 0x10 */
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MPI2_MPI_SGE_UNION SGL; /* 0x14 */
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} MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST,
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Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t;
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#define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)
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#define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
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#define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
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#define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
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#define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
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#define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
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#define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
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#define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
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#define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
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#define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
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typedef struct _MPI2_FW_UPLOAD_TCSGE
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{
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U8 Reserved1; /* 0x00 */
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U8 ContextSize; /* 0x01 */
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U8 DetailsLength; /* 0x02 */
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U8 Flags; /* 0x03 */
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U32 Reserved2; /* 0x04 */
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U32 ImageOffset; /* 0x08 */
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U32 ImageSize; /* 0x0C */
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} MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE,
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Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t;
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/* FWUpload Reply message */
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typedef struct _MPI2_FW_UPLOAD_REPLY
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{
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U8 ImageType; /* 0x00 */
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U8 Reserved1; /* 0x01 */
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U8 MsgLength; /* 0x02 */
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U8 Function; /* 0x03 */
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U16 Reserved2; /* 0x04 */
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U8 Reserved3; /* 0x06 */
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U8 MsgFlags; /* 0x07 */
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U8 VP_ID; /* 0x08 */
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U8 VF_ID; /* 0x09 */
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U16 Reserved4; /* 0x0A */
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U16 Reserved5; /* 0x0C */
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U16 IOCStatus; /* 0x0E */
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U32 IOCLogInfo; /* 0x10 */
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U32 ActualImageSize; /* 0x14 */
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} MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY,
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Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t;
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|
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/* FW Image Header */
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typedef struct _MPI2_FW_IMAGE_HEADER
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{
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U32 Signature; /* 0x00 */
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U32 Signature0; /* 0x04 */
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U32 Signature1; /* 0x08 */
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U32 Signature2; /* 0x0C */
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MPI2_VERSION_UNION MPIVersion; /* 0x10 */
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MPI2_VERSION_UNION FWVersion; /* 0x14 */
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MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */
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MPI2_VERSION_UNION PackageVersion; /* 0x1C */
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U16 VendorID; /* 0x20 */
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|
U16 ProductID; /* 0x22 */
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|
U16 ProtocolFlags; /* 0x24 */
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|
U16 Reserved26; /* 0x26 */
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|
U32 IOCCapabilities; /* 0x28 */
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U32 ImageSize; /* 0x2C */
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U32 NextImageHeaderOffset; /* 0x30 */
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|
U32 Checksum; /* 0x34 */
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|
U32 Reserved38; /* 0x38 */
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|
U32 Reserved3C; /* 0x3C */
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|
U32 Reserved40; /* 0x40 */
|
|
U32 Reserved44; /* 0x44 */
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U32 Reserved48; /* 0x48 */
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U32 Reserved4C; /* 0x4C */
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U32 Reserved50; /* 0x50 */
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U32 Reserved54; /* 0x54 */
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|
U32 Reserved58; /* 0x58 */
|
|
U32 Reserved5C; /* 0x5C */
|
|
U32 Reserved60; /* 0x60 */
|
|
U32 FirmwareVersionNameWhat; /* 0x64 */
|
|
U8 FirmwareVersionName[32]; /* 0x68 */
|
|
U32 VendorNameWhat; /* 0x88 */
|
|
U8 VendorName[32]; /* 0x8C */
|
|
U32 PackageNameWhat; /* 0x88 */
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U8 PackageName[32]; /* 0x8C */
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U32 ReservedD0; /* 0xD0 */
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U32 ReservedD4; /* 0xD4 */
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U32 ReservedD8; /* 0xD8 */
|
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U32 ReservedDC; /* 0xDC */
|
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U32 ReservedE0; /* 0xE0 */
|
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U32 ReservedE4; /* 0xE4 */
|
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U32 ReservedE8; /* 0xE8 */
|
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U32 ReservedEC; /* 0xEC */
|
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U32 ReservedF0; /* 0xF0 */
|
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U32 ReservedF4; /* 0xF4 */
|
|
U32 ReservedF8; /* 0xF8 */
|
|
U32 ReservedFC; /* 0xFC */
|
|
} MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER,
|
|
Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t;
|
|
|
|
/* Signature field */
|
|
#define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00)
|
|
#define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000)
|
|
#define MPI2_FW_HEADER_SIGNATURE (0xEA000000)
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|
|
|
/* Signature0 field */
|
|
#define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
|
|
#define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
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|
|
|
/* Signature1 field */
|
|
#define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
|
|
#define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
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/* Signature2 field */
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#define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
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#define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
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/* defines for using the ProductID field */
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#define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
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#define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
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#define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
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#define MPI2_FW_HEADER_PID_PROD_A (0x0000)
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#define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
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#define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200)
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#define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700)
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#define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
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/* SAS */
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#define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013)
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#define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014)
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/* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
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/* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
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#define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
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#define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
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#define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
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#define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
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#define MPI2_FW_HEADER_SIZE (0x100)
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/* Extended Image Header */
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typedef struct _MPI2_EXT_IMAGE_HEADER
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{
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U8 ImageType; /* 0x00 */
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U8 Reserved1; /* 0x01 */
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U16 Reserved2; /* 0x02 */
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U32 Checksum; /* 0x04 */
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U32 ImageSize; /* 0x08 */
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U32 NextImageHeaderOffset; /* 0x0C */
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U32 PackageVersion; /* 0x10 */
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U32 Reserved3; /* 0x14 */
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U32 Reserved4; /* 0x18 */
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U32 Reserved5; /* 0x1C */
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U8 IdentifyString[32]; /* 0x20 */
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} MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER,
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Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t;
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/* useful offsets */
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#define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00)
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#define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08)
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#define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C)
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#define MPI2_EXT_IMAGE_HEADER_SIZE (0x40)
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/* defines for the ImageType field */
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#define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
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#define MPI2_EXT_IMAGE_TYPE_FW (0x01)
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#define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03)
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#define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04)
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#define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05)
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#define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06)
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#define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07)
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#define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08)
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#define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MEGARAID)
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/* FLASH Layout Extended Image Data */
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/*
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* Host code (drivers, BIOS, utilities, etc.) should leave this define set to
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* one and check RegionsPerLayout at runtime.
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*/
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#ifndef MPI2_FLASH_NUMBER_OF_REGIONS
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#define MPI2_FLASH_NUMBER_OF_REGIONS (1)
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#endif
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/*
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* Host code (drivers, BIOS, utilities, etc.) should leave this define set to
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* one and check NumberOfLayouts at runtime.
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*/
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#ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
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#define MPI2_FLASH_NUMBER_OF_LAYOUTS (1)
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#endif
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typedef struct _MPI2_FLASH_REGION
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{
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U8 RegionType; /* 0x00 */
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U8 Reserved1; /* 0x01 */
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U16 Reserved2; /* 0x02 */
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U32 RegionOffset; /* 0x04 */
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U32 RegionSize; /* 0x08 */
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U32 Reserved3; /* 0x0C */
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} MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION,
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Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t;
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typedef struct _MPI2_FLASH_LAYOUT
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{
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U32 FlashSize; /* 0x00 */
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U32 Reserved1; /* 0x04 */
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U32 Reserved2; /* 0x08 */
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U32 Reserved3; /* 0x0C */
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MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */
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} MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT,
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Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t;
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typedef struct _MPI2_FLASH_LAYOUT_DATA
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{
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U8 ImageRevision; /* 0x00 */
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U8 Reserved1; /* 0x01 */
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U8 SizeOfRegion; /* 0x02 */
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U8 Reserved2; /* 0x03 */
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U16 NumberOfLayouts; /* 0x04 */
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U16 RegionsPerLayout; /* 0x06 */
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U16 MinimumSectorAlignment; /* 0x08 */
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U16 Reserved3; /* 0x0A */
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U32 Reserved4; /* 0x0C */
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MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */
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} MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA,
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Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t;
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/* defines for the RegionType field */
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#define MPI2_FLASH_REGION_UNUSED (0x00)
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#define MPI2_FLASH_REGION_FIRMWARE (0x01)
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#define MPI2_FLASH_REGION_BIOS (0x02)
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#define MPI2_FLASH_REGION_NVDATA (0x03)
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#define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05)
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#define MPI2_FLASH_REGION_MFG_INFORMATION (0x06)
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#define MPI2_FLASH_REGION_CONFIG_1 (0x07)
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#define MPI2_FLASH_REGION_CONFIG_2 (0x08)
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#define MPI2_FLASH_REGION_MEGARAID (0x09)
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#define MPI2_FLASH_REGION_INIT (0x0A)
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/* ImageRevision */
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#define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
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/* Supported Devices Extended Image Data */
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/*
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* Host code (drivers, BIOS, utilities, etc.) should leave this define set to
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* one and check NumberOfDevices at runtime.
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*/
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#ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
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#define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1)
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#endif
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typedef struct _MPI2_SUPPORTED_DEVICE
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{
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U16 DeviceID; /* 0x00 */
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U16 VendorID; /* 0x02 */
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U16 DeviceIDMask; /* 0x04 */
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U16 Reserved1; /* 0x06 */
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U8 LowPCIRev; /* 0x08 */
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U8 HighPCIRev; /* 0x09 */
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U16 Reserved2; /* 0x0A */
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U32 Reserved3; /* 0x0C */
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} MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE,
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Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t;
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typedef struct _MPI2_SUPPORTED_DEVICES_DATA
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{
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U8 ImageRevision; /* 0x00 */
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U8 Reserved1; /* 0x01 */
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U8 NumberOfDevices; /* 0x02 */
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U8 Reserved2; /* 0x03 */
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U32 Reserved3; /* 0x04 */
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MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */
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} MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA,
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Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t;
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/* ImageRevision */
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#define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00)
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/* Init Extended Image Data */
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typedef struct _MPI2_INIT_IMAGE_FOOTER
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{
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U32 BootFlags; /* 0x00 */
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U32 ImageSize; /* 0x04 */
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U32 Signature0; /* 0x08 */
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U32 Signature1; /* 0x0C */
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U32 Signature2; /* 0x10 */
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U32 ResetVector; /* 0x14 */
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} MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER,
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Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t;
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/* defines for the BootFlags field */
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#define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00)
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/* defines for the ImageSize field */
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#define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04)
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/* defines for the Signature0 field */
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#define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08)
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#define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA)
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/* defines for the Signature1 field */
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#define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C)
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#define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5)
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/* defines for the Signature2 field */
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#define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10)
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#define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A)
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/* Signature fields as individual bytes */
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#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA)
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#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A)
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#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5)
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#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A)
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#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5)
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#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA)
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#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A)
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#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5)
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#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A)
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#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5)
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#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA)
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#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A)
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/* defines for the ResetVector field */
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#define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14)
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#endif
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