7abf460488
Currently the feature is implemented only for a subset of errors reported via Bank 4. The subset includes only DRAM-related errors. The new code builds upon and reuses the Intel CMC (Correctable MCE Counters) support code. However, the AMD feature is quite different and, unfortunately, much less regular. For references please see AMD BKDGs for models 10h - 16h. Specifically, see MSR0000_0413 NB Machine Check Misc (Thresholding) Register (MC4_MISC0). http://developer.amd.com/resources/developer-guides-manuals/ Reviewed by: jhb MFC after: 1 month Differential Revision: https://reviews.freebsd.org/D9613 |
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acpica | ||
bios | ||
cpufreq | ||
include | ||
iommu | ||
isa | ||
pci | ||
x86 | ||
xen |