55aaf894e8
support machines having multiple independently numbered PCI domains and don't support reenumeration without ambiguity amongst the devices as seen by the OS and represented by PCI location strings. This includes introducing a function pci_find_dbsf(9) which works like pci_find_bsf(9) but additionally takes a domain number argument and limiting pci_find_bsf(9) to only search devices in domain 0 (the only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order to no longer report false positives when searching for siblings and dupe devices in the same domain respectively. Along with this change the sole host-PCI bridge driver converted to actually make use of PCI domain support is uninorth(4), the others continue to use domain 0 only for now and need to be converted as appropriate later on. Note that this means that the format of the location strings as used by pciconf(8) has been changed and that consumers of <sys/pciio.h> potentially need to be recompiled. Suggested by: jhb Reviewed by: grehan, jhb, marcel Approved by: re (kensmith), jhb (PCI maintainer hat)
475 lines
13 KiB
C
475 lines
13 KiB
C
/* $NetBSD: ixp425_pci.c,v 1.5 2006/04/10 03:36:03 simonb Exp $ */
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/*
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* Copyright (c) 2003
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* Ichiro FUKUHARA <ichiro@ichiro.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Ichiro FUKUHARA.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#define _ARM32_BUS_DMA_PRIVATE
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/pcb.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <vm/vm_extern.h>
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#include <machine/pmap.h>
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#include <arm/xscale/ixp425/ixp425reg.h>
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#include <arm/xscale/ixp425/ixp425var.h>
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#include <dev/pci/pcib_private.h>
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#include "pcib_if.h"
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#include <dev/pci/pcireg.h>
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extern struct ixp425_softc *ixp425_softc;
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#define PCI_CSR_WRITE_4(sc, reg, data) \
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bus_write_4(sc->sc_csr, reg, data)
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#define PCI_CSR_READ_4(sc, reg) \
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bus_read_4(sc->sc_csr, reg)
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#define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit)
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#define PCI_CONF_UNLOCK(s) restore_interrupts((s))
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static device_probe_t ixppcib_probe;
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static device_attach_t ixppcib_attach;
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static bus_read_ivar_t ixppcib_read_ivar;
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static bus_write_ivar_t ixppcib_write_ivar;
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static bus_setup_intr_t ixppcib_setup_intr;
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static bus_teardown_intr_t ixppcib_teardown_intr;
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static bus_alloc_resource_t ixppcib_alloc_resource;
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static bus_activate_resource_t ixppcib_activate_resource;
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static bus_deactivate_resource_t ixppcib_deactivate_resource;
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static bus_release_resource_t ixppcib_release_resource;
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static pcib_maxslots_t ixppcib_maxslots;
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static pcib_read_config_t ixppcib_read_config;
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static pcib_write_config_t ixppcib_write_config;
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static pcib_route_interrupt_t ixppcib_route_interrupt;
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static int
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ixppcib_probe(device_t dev)
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{
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device_set_desc(dev, "IXP425 PCI Bus");
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return (0);
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}
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static void
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ixp425_pci_conf_reg_write(struct ixppcib_softc *sc, uint32_t reg,
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uint32_t data)
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{
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PCI_CSR_WRITE_4(sc,
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PCI_CRP_AD_CBE, ((reg & ~3) | COMMAND_CRP_WRITE));
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PCI_CSR_WRITE_4(sc,
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PCI_CRP_AD_WDATA, data);
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}
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static int
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ixppcib_attach(device_t dev)
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{
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int rid;
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struct ixppcib_softc *sc;
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sc = device_get_softc(dev);
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rid = 0;
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sc->sc_csr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
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IXP425_PCI_HWBASE, IXP425_PCI_HWBASE + IXP425_PCI_SIZE,
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IXP425_PCI_SIZE, RF_ACTIVE);
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if (sc->sc_csr == NULL)
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panic("cannot allocate PCI CSR registers");
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ixp425_md_attach(dev);
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/* always setup the base, incase another OS messes w/ it */
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PCI_CSR_WRITE_4(sc, PCI_PCIMEMBASE, 0x48494a4b);
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rid = 0;
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sc->sc_mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
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IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE,
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IXP425_PCI_MEM_SIZE, RF_ACTIVE);
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if (sc->sc_mem == NULL)
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panic("cannot allocate PCI MEM space");
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#define AHB_OFFSET 0x10000000UL
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if (bus_dma_tag_create(NULL, 1, 0, AHB_OFFSET + 64 * 1024 * 1024,
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BUS_SPACE_MAXADDR, NULL, NULL, 0xffffffff, 0xff, 0xffffffff, 0,
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NULL, NULL, &sc->sc_dmat))
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panic("couldn't create the PCI dma tag !");
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/*
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* The PCI bus can only address 64MB. However, due to the way our
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* implementation of busdma works, busdma can't tell if a device
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* is a PCI device or not. So defaults to the PCI dma tag, which
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* restrict the DMA'able memory to the first 64MB, and explicitely
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* create less restrictive tags for non-PCI devices.
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*/
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arm_root_dma_tag = sc->sc_dmat;
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/*
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* Initialize the bus space tags.
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*/
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ixp425_io_bs_init(&sc->sc_pci_iot, sc);
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ixp425_mem_bs_init(&sc->sc_pci_memt, sc);
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sc->sc_dev = dev;
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/* Initialize memory and i/o rmans. */
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sc->sc_io_rman.rm_type = RMAN_ARRAY;
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sc->sc_io_rman.rm_descr = "IXP425 PCI I/O Ports";
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if (rman_init(&sc->sc_io_rman) != 0 ||
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rman_manage_region(&sc->sc_io_rman, 0,
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IXP425_PCI_IO_SIZE) != 0) {
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panic("ixppcib_probe: failed to set up I/O rman");
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}
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sc->sc_mem_rman.rm_type = RMAN_ARRAY;
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sc->sc_mem_rman.rm_descr = "IXP425 PCI Memory";
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if (rman_init(&sc->sc_mem_rman) != 0 ||
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rman_manage_region(&sc->sc_mem_rman, IXP425_PCI_MEM_HWBASE,
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IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE) != 0) {
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panic("ixppcib_probe: failed to set up memory rman");
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}
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/*
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* PCI->AHB address translation
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* begin at the physical memory start + OFFSET
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*/
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PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE,
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(AHB_OFFSET & 0xFF000000) +
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((AHB_OFFSET & 0xFF000000) >> 8) +
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((AHB_OFFSET & 0xFF000000) >> 16) +
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((AHB_OFFSET & 0xFF000000) >> 24) +
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0x00010203);
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#define IXPPCIB_WRITE_CONF(sc, reg, val) \
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ixp425_pci_conf_reg_write(sc, reg, val)
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/* Write Mapping registers PCI Configuration Registers */
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/* Base Address 0 - 3 */
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IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR0, AHB_OFFSET + 0x00000000);
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IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR1, AHB_OFFSET + 0x01000000);
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IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR2, AHB_OFFSET + 0x02000000);
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IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR3, AHB_OFFSET + 0x03000000);
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/* Base Address 4 */
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IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR4, 0xffffffff);
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/* Base Address 5 */
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IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR5, 0x00000000);
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/* Assert some PCI errors */
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PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_AHBE | ISR_PPE | ISR_PFE | ISR_PSE);
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#ifdef __ARMEB__
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/*
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* Set up byte lane swapping between little-endian PCI
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* and the big-endian AHB bus
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*/
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PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE | CSR_PDS);
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#else
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PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE);
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#endif
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/*
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* Enable bus mastering and I/O,memory access
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*/
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IXPPCIB_WRITE_CONF(sc, PCIR_COMMAND,
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PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
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/*
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* Wait some more to ensure PCI devices have stabilised.
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*/
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DELAY(50000);
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device_add_child(dev, "pci", -1);
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return (bus_generic_attach(dev));
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}
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static int
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ixppcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
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{
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struct ixppcib_softc *sc;
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sc = device_get_softc(dev);
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switch (which) {
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case PCIB_IVAR_DOMAIN:
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*result = 0;
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return (0);
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case PCIB_IVAR_BUS:
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*result = sc->sc_bus;
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return (0);
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}
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return (ENOENT);
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}
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static int
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ixppcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
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{
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struct ixppcib_softc *sc;
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sc = device_get_softc(dev);
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switch (which) {
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case PCIB_IVAR_DOMAIN:
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return (EINVAL);
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case PCIB_IVAR_BUS:
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sc->sc_bus = value;
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return (0);
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}
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return (ENOENT);
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}
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static int
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ixppcib_setup_intr(device_t dev, device_t child, struct resource *ires,
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int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
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void **cookiep)
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{
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return (BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags,
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filt, intr, arg, cookiep));
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}
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static int
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ixppcib_teardown_intr(device_t dev, device_t child, struct resource *vec,
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void *cookie)
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{
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return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, cookie));
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}
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static struct resource *
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ixppcib_alloc_resource(device_t bus, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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{
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bus_space_tag_t tag;
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struct ixppcib_softc *sc = device_get_softc(bus);
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struct rman *rmanp;
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struct resource *rv;
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tag = NULL; /* shut up stupid gcc */
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rv = NULL;
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switch (type) {
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case SYS_RES_IRQ:
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rmanp = &sc->sc_irq_rman;
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break;
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case SYS_RES_IOPORT:
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rmanp = &sc->sc_io_rman;
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tag = &sc->sc_pci_iot;
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break;
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case SYS_RES_MEMORY:
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rmanp = &sc->sc_mem_rman;
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tag = &sc->sc_pci_memt;
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break;
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default:
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return (rv);
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}
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rv = rman_reserve_resource(rmanp, start, end, count, flags, child);
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if (rv != NULL) {
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rman_set_rid(rv, *rid);
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if (type == SYS_RES_IOPORT) {
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rman_set_bustag(rv, tag);
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rman_set_bushandle(rv, rman_get_start(rv));
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} else if (type == SYS_RES_MEMORY) {
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rman_set_bustag(rv, tag);
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rman_set_bushandle(rv, rman_get_bushandle(sc->sc_mem) +
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(rman_get_start(rv) - IXP425_PCI_MEM_HWBASE));
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}
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}
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return (rv);
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}
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static int
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ixppcib_activate_resource(device_t bus, device_t child, int type, int rid,
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struct resource *r)
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{
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device_printf(bus, "%s called activate_resource\n", device_get_nameunit(child));
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return (ENXIO);
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}
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static int
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ixppcib_deactivate_resource(device_t bus, device_t child, int type, int rid,
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struct resource *r)
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{
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device_printf(bus, "%s called deactivate_resource\n", device_get_nameunit(child));
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return (ENXIO);
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}
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static int
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ixppcib_release_resource(device_t bus, device_t child, int type, int rid,
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struct resource *r)
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{
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device_printf(bus, "%s called release_resource\n", device_get_nameunit(child));
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return (ENXIO);
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}
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static void
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ixppcib_conf_setup(struct ixppcib_softc *sc, int bus, int slot, int func,
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int reg)
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{
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if (bus == 0) {
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if (slot == 0 && func == 0) {
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PCI_CSR_WRITE_4(sc, PCI_NP_AD, (reg & ~3));
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} else {
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bus &= 0xff;
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slot &= 0x1f;
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func &= 0x07;
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/* configuration type 0 */
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PCI_CSR_WRITE_4(sc, PCI_NP_AD, (1U << (32 - slot)) |
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(func << 8) | (reg & ~3));
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}
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} else {
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/* configuration type 1 */
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PCI_CSR_WRITE_4(sc, PCI_NP_AD,
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(bus << 16) | (slot << 11) |
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(func << 8) | (reg & ~3) | 1);
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}
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}
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static int
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ixppcib_maxslots(device_t dev)
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{
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return (PCI_SLOTMAX);
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}
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static u_int32_t
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ixppcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
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int bytes)
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{
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struct ixppcib_softc *sc = device_get_softc(dev);
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u_int32_t data, ret;
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ixppcib_conf_setup(sc, bus, slot, func, reg & ~3);
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PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_READ);
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ret = PCI_CSR_READ_4(sc, PCI_NP_RDATA);
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ret >>= (reg & 3) * 8;
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ret &= 0xffffffff >> ((4 - bytes) * 8);
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#if 0
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device_printf(dev, "read config: %u:%u:%u %#x(%d) = %#x\n", bus, slot, func, reg, bytes, ret);
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#endif
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/* check & clear PCI abort */
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data = PCI_CSR_READ_4(sc, PCI_ISR);
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if (data & ISR_PFE) {
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PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE);
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return (-1);
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}
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return (ret);
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}
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static const int byteenables[] = { 0, 0x10, 0x30, 0x70, 0xf0 };
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static void
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ixppcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
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u_int32_t val, int bytes)
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{
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struct ixppcib_softc *sc = device_get_softc(dev);
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u_int32_t data;
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#if 0
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device_printf(dev, "write config: %u:%u:%u %#x(%d) = %#x\n", bus, slot, func, reg, bytes, val);
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#endif
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ixppcib_conf_setup(sc, bus, slot, func, reg & ~3);
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/* Byte enables are active low, so not them first */
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PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_WRITE |
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(~(byteenables[bytes] << (reg & 3)) & 0xf0));
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PCI_CSR_WRITE_4(sc, PCI_NP_WDATA, val << ((reg & 3) * 8));
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/* check & clear PCI abort */
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data = PCI_CSR_READ_4(sc, PCI_ISR);
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if (data & ISR_PFE)
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PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE);
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}
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static int
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ixppcib_route_interrupt(device_t bridge, device_t device, int pin)
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{
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return (ixp425_md_route_interrupt(bridge, device, pin));
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}
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static device_method_t ixppcib_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, ixppcib_probe),
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DEVMETHOD(device_attach, ixppcib_attach),
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/* Bus interface */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_read_ivar, ixppcib_read_ivar),
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DEVMETHOD(bus_write_ivar, ixppcib_write_ivar),
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DEVMETHOD(bus_setup_intr, ixppcib_setup_intr),
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DEVMETHOD(bus_teardown_intr, ixppcib_teardown_intr),
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DEVMETHOD(bus_alloc_resource, ixppcib_alloc_resource),
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DEVMETHOD(bus_activate_resource, ixppcib_activate_resource),
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DEVMETHOD(bus_deactivate_resource, ixppcib_deactivate_resource),
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DEVMETHOD(bus_release_resource, ixppcib_release_resource),
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/* DEVMETHOD(bus_get_dma_tag, ixppcib_get_dma_tag), */
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/* pcib interface */
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DEVMETHOD(pcib_maxslots, ixppcib_maxslots),
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DEVMETHOD(pcib_read_config, ixppcib_read_config),
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DEVMETHOD(pcib_write_config, ixppcib_write_config),
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DEVMETHOD(pcib_route_interrupt, ixppcib_route_interrupt),
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{0, 0},
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};
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static driver_t ixppcib_driver = {
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"pcib",
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ixppcib_methods,
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sizeof(struct ixppcib_softc),
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};
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static devclass_t ixppcib_devclass;
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DRIVER_MODULE(ixppcib, ixp, ixppcib_driver, ixppcib_devclass, 0, 0);
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