fc7682b17f
Sync the e1000 shared code with DPDK shared code "cid-gigabit.2020.06.05.tar.gz released by ND" Primary focus was on client platforms (ich8lan). More work remains here but we need an Intel contact for client networking. Reviewed by: grehan, Intel Networking (erj, earlier rev) Obtained from: DPDK <http://git.dpdk.org/dpdk/tree/drivers/net/e1000/base> MFC after: 1 week Sponsored by: me Differential Revision: https://reviews.freebsd.org/D31547
111 lines
4.3 KiB
C
111 lines
4.3 KiB
C
/******************************************************************************
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SPDX-License-Identifier: BSD-3-Clause
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Copyright (c) 2001-2020, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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#ifndef _E1000_I210_H_
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#define _E1000_I210_H_
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bool e1000_get_flash_presence_i210(struct e1000_hw *hw);
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s32 e1000_update_flash_i210(struct e1000_hw *hw);
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s32 e1000_update_nvm_checksum_i210(struct e1000_hw *hw);
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s32 e1000_validate_nvm_checksum_i210(struct e1000_hw *hw);
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s32 e1000_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset,
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u16 words, u16 *data);
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s32 e1000_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset,
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u16 words, u16 *data);
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s32 e1000_read_invm_version(struct e1000_hw *hw,
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struct e1000_fw_version *invm_ver);
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s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,
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u16 *data);
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s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,
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u16 data);
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s32 e1000_init_hw_i210(struct e1000_hw *hw);
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#define E1000_STM_OPCODE 0xDB00
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#define E1000_EEPROM_FLASH_SIZE_WORD 0x11
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#define INVM_DWORD_TO_RECORD_TYPE(invm_dword) \
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(u8)((invm_dword) & 0x7)
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#define INVM_DWORD_TO_WORD_ADDRESS(invm_dword) \
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(u8)(((invm_dword) & 0x0000FE00) >> 9)
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#define INVM_DWORD_TO_WORD_DATA(invm_dword) \
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(u16)(((invm_dword) & 0xFFFF0000) >> 16)
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enum E1000_INVM_STRUCTURE_TYPE {
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E1000_INVM_UNINITIALIZED_STRUCTURE = 0x00,
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E1000_INVM_WORD_AUTOLOAD_STRUCTURE = 0x01,
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E1000_INVM_CSR_AUTOLOAD_STRUCTURE = 0x02,
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E1000_INVM_PHY_REGISTER_AUTOLOAD_STRUCTURE = 0x03,
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E1000_INVM_RSA_KEY_SHA256_STRUCTURE = 0x04,
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E1000_INVM_INVALIDATED_STRUCTURE = 0x0F,
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};
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#define E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS 8
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#define E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS 1
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#define E1000_INVM_ULT_BYTES_SIZE 8
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#define E1000_INVM_RECORD_SIZE_IN_BYTES 4
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#define E1000_INVM_VER_FIELD_ONE 0x1FF8
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#define E1000_INVM_VER_FIELD_TWO 0x7FE000
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#define E1000_INVM_IMGTYPE_FIELD 0x1F800000
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#define E1000_INVM_MAJOR_MASK 0x3F0
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#define E1000_INVM_MINOR_MASK 0xF
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#define E1000_INVM_MAJOR_SHIFT 4
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#define ID_LED_DEFAULT_I210 ((ID_LED_OFF1_ON2 << 8) | \
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(ID_LED_DEF1_DEF2 << 4) | \
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(ID_LED_OFF1_OFF2))
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#define ID_LED_DEFAULT_I210_SERDES ((ID_LED_DEF1_DEF2 << 8) | \
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(ID_LED_DEF1_DEF2 << 4) | \
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(ID_LED_OFF1_ON2))
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/* NVM offset defaults for I211 devices */
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#define NVM_INIT_CTRL_2_DEFAULT_I211 0X7243
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#define NVM_INIT_CTRL_4_DEFAULT_I211 0x00C1
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#define NVM_LED_1_CFG_DEFAULT_I211 0x0184
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#define NVM_LED_0_2_CFG_DEFAULT_I211 0x200C
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/* PLL Defines */
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#define E1000_PCI_PMCSR 0x44
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#define E1000_PCI_PMCSR_D3 0x03
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#define E1000_MAX_PLL_TRIES 5
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#define E1000_PHY_PLL_UNCONF 0xFF
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#define E1000_PHY_PLL_FREQ_PAGE 0xFC0000
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#define E1000_PHY_PLL_FREQ_REG 0x000E
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#define E1000_INVM_DEFAULT_AL 0x202F
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#define E1000_INVM_AUTOLOAD 0x0A
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#define E1000_INVM_PLL_WO_VAL 0x0010
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#endif
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