1c96bdd146
provided, for example, on the PowerPC 970 (G5), as well as on related CPUs like the POWER3 and POWER4. This also adds support for various built-in hardware found on Apple G5 hardware (e.g. the IBM CPC925 northbridge). Reviewed by: grehan
351 lines
9.7 KiB
C
351 lines
9.7 KiB
C
/*-
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* Copyright (c) 2001 Matt Thomas.
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* Copyright (c) 2001 Tsubai Masanari.
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* Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by
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* Internet Research Institute, Inc.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (C) 2003 Benno Rice.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* from $NetBSD: cpu_subr.c,v 1.1 2003/02/03 17:10:09 matt Exp $
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* $FreeBSD$
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/sysctl.h>
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#include <machine/bus.h>
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#include <machine/hid.h>
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#include <machine/md_var.h>
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#include <machine/spr.h>
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int powerpc_pow_enabled;
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struct cputab {
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const char *name;
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uint16_t version;
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uint16_t revfmt;
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};
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#define REVFMT_MAJMIN 1 /* %u.%u */
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#define REVFMT_HEX 2 /* 0x%04x */
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#define REVFMT_DEC 3 /* %u */
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static const struct cputab models[] = {
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{ "Motorola PowerPC 601", MPC601, REVFMT_DEC },
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{ "Motorola PowerPC 602", MPC602, REVFMT_DEC },
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{ "Motorola PowerPC 603", MPC603, REVFMT_MAJMIN },
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{ "Motorola PowerPC 603e", MPC603e, REVFMT_MAJMIN },
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{ "Motorola PowerPC 603ev", MPC603ev, REVFMT_MAJMIN },
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{ "Motorola PowerPC 604", MPC604, REVFMT_MAJMIN },
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{ "Motorola PowerPC 604ev", MPC604ev, REVFMT_MAJMIN },
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{ "Motorola PowerPC 620", MPC620, REVFMT_HEX },
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{ "Motorola PowerPC 750", MPC750, REVFMT_MAJMIN },
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{ "IBM PowerPC 750FX", IBM750FX, REVFMT_MAJMIN },
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{ "IBM PowerPC 970", IBM970, REVFMT_MAJMIN },
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{ "IBM PowerPC 970FX", IBM970FX, REVFMT_MAJMIN },
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{ "IBM PowerPC 970GX", IBM970GX, REVFMT_MAJMIN },
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{ "IBM PowerPC 970MP", IBM970MP, REVFMT_MAJMIN },
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{ "Motorola PowerPC 7400", MPC7400, REVFMT_MAJMIN },
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{ "Motorola PowerPC 7410", MPC7410, REVFMT_MAJMIN },
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{ "Motorola PowerPC 7450", MPC7450, REVFMT_MAJMIN },
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{ "Motorola PowerPC 7455", MPC7455, REVFMT_MAJMIN },
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{ "Motorola PowerPC 7457", MPC7457, REVFMT_MAJMIN },
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{ "Motorola PowerPC 7447A", MPC7447A, REVFMT_MAJMIN },
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{ "Motorola PowerPC 7448", MPC7448, REVFMT_MAJMIN },
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{ "Motorola PowerPC 8240", MPC8240, REVFMT_MAJMIN },
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{ "Freescale e500v1 core", FSL_E500v1, REVFMT_MAJMIN },
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{ "Freescale e500v2 core", FSL_E500v2, REVFMT_MAJMIN },
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{ "Unknown PowerPC CPU", 0, REVFMT_HEX }
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};
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static char model[64];
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SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, model, 0, "");
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register_t l2cr_config = 0;
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register_t l3cr_config = 0;
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static void cpu_print_speed(void);
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static void cpu_print_cacheinfo(u_int, uint16_t);
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void
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cpu_setup(u_int cpuid)
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{
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u_int pvr, maj, min, hid0;
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uint16_t vers, rev, revfmt;
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const struct cputab *cp;
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const char *name;
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char *bitmask;
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pvr = mfpvr();
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vers = pvr >> 16;
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rev = pvr;
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switch (vers) {
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case MPC7410:
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min = (pvr >> 0) & 0xff;
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maj = min <= 4 ? 1 : 2;
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break;
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case FSL_E500v1:
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case FSL_E500v2:
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maj = (pvr >> 4) & 0xf;
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min = (pvr >> 0) & 0xf;
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break;
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default:
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maj = (pvr >> 8) & 0xf;
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min = (pvr >> 0) & 0xf;
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}
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for (cp = models; cp->version != 0; cp++) {
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if (cp->version == vers)
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break;
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}
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revfmt = cp->revfmt;
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name = cp->name;
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if (rev == MPC750 && pvr == 15) {
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name = "Motorola MPC755";
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revfmt = REVFMT_HEX;
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}
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strncpy(model, name, sizeof(model) - 1);
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printf("cpu%d: %s revision ", cpuid, name);
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switch (revfmt) {
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case REVFMT_MAJMIN:
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printf("%u.%u", maj, min);
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break;
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case REVFMT_HEX:
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printf("0x%04x", rev);
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break;
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case REVFMT_DEC:
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printf("%u", rev);
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break;
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}
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hid0 = mfspr(SPR_HID0);
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/*
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* Configure power-saving mode.
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*/
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switch (vers) {
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case MPC603:
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case MPC603e:
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case MPC603ev:
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case MPC604ev:
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case MPC750:
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case IBM750FX:
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case MPC7400:
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case MPC7410:
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case MPC8240:
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case MPC8245:
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/* Select DOZE mode. */
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hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
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hid0 |= HID0_DOZE | HID0_DPM;
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powerpc_pow_enabled = 1;
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break;
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case MPC7448:
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case MPC7447A:
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case MPC7457:
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case MPC7455:
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case MPC7450:
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/* Enable the 7450 branch caches */
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hid0 |= HID0_SGE | HID0_BTIC;
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hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT;
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/* Disable BTIC on 7450 Rev 2.0 or earlier and on 7457 */
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if (((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200)
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|| (pvr >> 16) == MPC7457)
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hid0 &= ~HID0_BTIC;
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/* Select NAP mode. */
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hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
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hid0 |= HID0_NAP | HID0_DPM;
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powerpc_pow_enabled = 1;
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break;
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default:
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/* No power-saving mode is available. */ ;
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}
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switch (vers) {
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case IBM750FX:
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case MPC750:
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hid0 &= ~HID0_DBP; /* XXX correct? */
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hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
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break;
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case MPC7400:
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case MPC7410:
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hid0 &= ~HID0_SPD;
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hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
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hid0 |= HID0_EIEC;
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break;
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case FSL_E500v1:
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case FSL_E500v2:
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hid0 |= HID0_EMCP;
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break;
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}
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mtspr(SPR_HID0, hid0);
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switch (vers) {
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case MPC7447A:
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case MPC7448:
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case MPC7450:
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case MPC7455:
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case MPC7457:
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bitmask = HID0_7450_BITMASK;
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break;
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case FSL_E500v1:
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case FSL_E500v2:
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bitmask = HID0_E500_BITMASK;
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break;
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default:
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bitmask = HID0_BITMASK;
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break;
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}
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switch (vers) {
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case MPC7450:
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case MPC7455:
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case MPC7457:
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/* Only MPC745x CPUs have an L3 cache. */
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l3cr_config = mfspr(SPR_L3CR);
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/* Fallthrough */
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case MPC750:
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case IBM750FX:
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case MPC7400:
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case MPC7410:
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case MPC7447A:
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case MPC7448:
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cpu_print_speed();
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printf("\n");
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l2cr_config = mfspr(SPR_L2CR);
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if (bootverbose)
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cpu_print_cacheinfo(cpuid, vers);
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break;
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default:
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printf("\n");
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break;
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}
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printf("cpu%d: HID0 %b\n", cpuid, hid0, bitmask);
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}
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void
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cpu_print_speed(void)
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{
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uint64_t cps;
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mtspr(SPR_MMCR0, SPR_MMCR0_FC);
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mtspr(SPR_PMC1, 0);
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mtspr(SPR_MMCR0, SPR_MMCR0_PMC1SEL(PMCN_CYCLES));
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DELAY(100000);
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cps = (mfspr(SPR_PMC1) * 10) + 4999;
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printf(", %lld.%02lld MHz", cps / 1000000, (cps / 10000) % 100);
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}
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void
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cpu_print_cacheinfo(u_int cpuid, uint16_t vers)
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{
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uint32_t hid;
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hid = mfspr(SPR_HID0);
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printf("cpu%u: ", cpuid);
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printf("L1 I-cache %sabled, ", (hid & HID0_ICE) ? "en" : "dis");
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printf("L1 D-cache %sabled\n", (hid & HID0_DCE) ? "en" : "dis");
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printf("cpu%u: ", cpuid);
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if (l2cr_config & L2CR_L2E) {
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switch (vers) {
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case MPC7450:
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case MPC7455:
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case MPC7457:
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printf("256KB L2 cache, ");
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if (l3cr_config & L3CR_L3E)
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printf("%cMB L3 backside cache",
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l3cr_config & L3CR_L3SIZ ? '2' : '1');
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else
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printf("L3 cache disabled");
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printf("\n");
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break;
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case IBM750FX:
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printf("512KB L2 cache\n");
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break;
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default:
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switch (l2cr_config & L2CR_L2SIZ) {
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case L2SIZ_256K:
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printf("256KB ");
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break;
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case L2SIZ_512K:
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printf("512KB ");
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break;
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case L2SIZ_1M:
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printf("1MB ");
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break;
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}
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printf("write-%s", (l2cr_config & L2CR_L2WT)
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? "through" : "back");
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if (l2cr_config & L2CR_L2PE)
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printf(", with parity");
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printf(" backside cache\n");
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break;
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}
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} else
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printf("L2 cache disabled\n");
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}
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