e8ef0c2923
- Fix up TX speed changes. - Make mpi-350 cards sort-of work with new firmware. It RXs okay but TXs only work for about 14 packets then fails to get an interrupt. The TX watchdog fires. It has been reported that my hack for now doesn't break cards with the older firmware. It appears my card has lost the ability to RX or TX at all but other peoples cards work. I assume it got damaged in tansport. MFC: 1 week.
554 lines
16 KiB
C
554 lines
16 KiB
C
/*
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* Copyright (c) 1997, 1998, 1999
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* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define AN_TIMEOUT 65536
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/* Default network name: <empty string> */
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#define AN_DEFAULT_NETNAME ""
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/* The nodename must be less than 16 bytes */
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#define AN_DEFAULT_NODENAME "FreeBSD"
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#define AN_DEFAULT_IBSS "FreeBSD IBSS"
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/*
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* register space access macros
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*/
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#define CSR_WRITE_2(sc, reg, val) \
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bus_space_write_2(sc->an_btag, sc->an_bhandle, reg, val)
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#define CSR_READ_2(sc, reg) \
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bus_space_read_2(sc->an_btag, sc->an_bhandle, reg)
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#define CSR_WRITE_1(sc, reg, val) \
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bus_space_write_1(sc->an_btag, sc->an_bhandle, reg, val)
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#define CSR_READ_1(sc, reg) \
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bus_space_read_1(sc->an_btag, sc->an_bhandle, reg)
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/*
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* memory space access macros
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*/
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#define CSR_MEM_WRITE_2(sc, reg, val) \
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bus_space_write_2(sc->an_mem_btag, sc->an_mem_bhandle, reg, val)
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#define CSR_MEM_READ_2(sc, reg) \
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bus_space_read_2(sc->an_mem_btag, sc->an_mem_bhandle, reg)
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#define CSR_MEM_WRITE_1(sc, reg, val) \
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bus_space_write_1(sc->an_mem_btag, sc->an_mem_bhandle, reg, val)
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#define CSR_MEM_READ_1(sc, reg) \
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bus_space_read_1(sc->an_mem_btag, sc->an_mem_bhandle, reg)
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/*
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* aux. memory space access macros
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*/
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#define CSR_MEM_AUX_WRITE_4(sc, reg, val) \
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bus_space_write_4(sc->an_mem_aux_btag, sc->an_mem_aux_bhandle, reg, val)
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#define CSR_MEM_AUX_READ_4(sc, reg) \
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bus_space_read_4(sc->an_mem_aux_btag, sc->an_mem_aux_bhandle, reg)
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#define CSR_MEM_AUX_WRITE_1(sc, reg, val) \
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bus_space_write_1(sc->an_mem_aux_btag, sc->an_mem_aux_bhandle, reg, val)
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#define CSR_MEM_AUX_READ_1(sc, reg) \
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bus_space_read_1(sc->an_mem_aux_btag, sc->an_mem_aux_bhandle, reg)
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/*
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* Size of Aironet I/O space.
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*/
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#define AN_IOSIZ 0x40
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/*
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* Size of aux. memory space ... probably not needed DJA
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*/
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#define AN_AUX_MEM_SIZE (256 * 1024)
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/*
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* Hermes register definitions and what little I know about them.
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*/
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/* Hermes command/status registers. */
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#define AN_COMMAND(x) (x ? 0x00 : 0x00)
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#define AN_PARAM0(x) (x ? 0x04 : 0x02)
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#define AN_PARAM1(x) (x ? 0x08 : 0x04)
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#define AN_PARAM2(x) (x ? 0x0c : 0x06)
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#define AN_STATUS(x) (x ? 0x10 : 0x08)
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#define AN_RESP0(x) (x ? 0x14 : 0x0A)
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#define AN_RESP1(x) (x ? 0x18 : 0x0C)
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#define AN_RESP2(x) (x ? 0x1c : 0x0E)
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#define AN_LINKSTAT(x) (x ? 0x20 : 0x10)
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/* Command register */
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#define AN_CMD_BUSY 0x8000 /* busy bit */
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#define AN_CMD_NO_ACK 0x0080 /* don't acknowledge command */
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#define AN_CMD_CODE_MASK 0x003F
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#define AN_CMD_QUAL_MASK 0x7F00
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/* Command codes */
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#define AN_CMD_NOOP 0x0000 /* no-op */
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#define AN_CMD_ENABLE 0x0001 /* enable */
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#define AN_CMD_DISABLE 0x0002 /* disable */
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#define AN_CMD_FORCE_SYNCLOSS 0x0003 /* force loss of sync */
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#define AN_CMD_FW_RESTART 0x0004 /* firmware restart */
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#define AN_CMD_HOST_SLEEP 0x0005
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#define AN_CMD_MAGIC_PKT 0x0006
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#define AN_CMD_READCFG 0x0008
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#define AN_CMD_SET_MODE 0x0009
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#define AN_CMD_ALLOC_MEM 0x000A /* allocate NIC memory */
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#define AN_CMD_TX 0x000B /* transmit */
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#define AN_CMD_DEALLOC_MEM 0x000C
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#define AN_CMD_NOOP2 0x0010
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#define AN_CMD_ALLOC_DESC 0x0020
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#define AN_CMD_ACCESS 0x0021
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#define AN_CMD_ALLOC_BUF 0x0028
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#define AN_CMD_PSP_NODES 0x0030
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#define AN_CMD_SET_PHYREG 0x003E
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#define AN_CMD_TX_TEST 0x003F
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#define AN_CMD_SLEEP 0x0085
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#define AN_CMD_SAVECFG 0x0108
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/*
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* MPI 350 DMA descriptor information
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*/
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#define AN_DESCRIPTOR_TX 0x01
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#define AN_DESCRIPTOR_RX 0x02
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#define AN_DESCRIPTOR_TXCMP 0x04
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#define AN_DESCRIPTOR_HOSTWRITE 0x08
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#define AN_DESCRIPTOR_HOSTREAD 0x10
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#define AN_DESCRIPTOR_HOSTRW 0x20
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#define AN_MAX_RX_DESC 1
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#define AN_MAX_TX_DESC 1
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#define AN_HOSTBUFSIZ 1840
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struct an_card_rid_desc
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{
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unsigned an_rid:16;
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unsigned an_len:15;
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unsigned an_valid:1;
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u_int64_t an_phys;
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};
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struct an_card_rx_desc
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{
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unsigned an_ctrl:15;
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unsigned an_done:1;
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unsigned an_len:15;
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unsigned an_valid:1;
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u_int64_t an_phys;
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};
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struct an_card_tx_desc
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{
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unsigned an_offset:15;
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unsigned an_eoc:1;
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unsigned an_len:15;
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unsigned an_valid:1;
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u_int64_t an_phys;
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};
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#define AN_RID_BUFFER_SIZE AN_MAX_DATALEN
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#define AN_RX_BUFFER_SIZE AN_HOSTBUFSIZ
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#define AN_TX_BUFFER_SIZE AN_HOSTBUFSIZ
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/*#define AN_HOST_DESC_OFFSET 0xC sort of works */
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#define AN_HOST_DESC_OFFSET 0x800
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#define AN_RX_DESC_OFFSET (AN_HOST_DESC_OFFSET + \
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sizeof(struct an_card_rid_desc))
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#define AN_TX_DESC_OFFSET (AN_RX_DESC_OFFSET + \
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(AN_MAX_RX_DESC * sizeof(struct an_card_rx_desc)))
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struct an_command {
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u_int16_t an_cmd;
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u_int16_t an_parm0;
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u_int16_t an_parm1;
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u_int16_t an_parm2;
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};
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struct an_reply {
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u_int16_t an_status;
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u_int16_t an_resp0;
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u_int16_t an_resp1;
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u_int16_t an_resp2;
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};
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/*
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* Reclaim qualifier bit, applicable to the
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* TX command.
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*/
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#define AN_RECLAIM 0x0100 /* reclaim NIC memory */
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/*
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* ACCESS command qualifier bits.
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*/
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#define AN_ACCESS_READ 0x0000
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#define AN_ACCESS_WRITE 0x0100
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/*
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* PROGRAM command qualifier bits.
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*/
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#define AN_PROGRAM_DISABLE 0x0000
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#define AN_PROGRAM_ENABLE_RAM 0x0100
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#define AN_PROGRAM_ENABLE_NVRAM 0x0200
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#define AN_PROGRAM_NVRAM 0x0300
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/* Status register values */
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#define AN_STAT_CMD_CODE 0x003F
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#define AN_STAT_CMD_RESULT 0x7F00
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/* Linkstat register */
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#define AN_LINKSTAT_ASSOCIATED 0x0400
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#define AN_LINKSTAT_AUTHFAIL 0x0300
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#define AN_LINKSTAT_ASSOC_FAIL 0x8400
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#define AN_LINKSTAT_DISASSOC 0x8200
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#define AN_LINKSTAT_DEAUTH 0x8100
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#define AN_LINKSTAT_SYNCLOST_TSF 0x8004
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#define AN_LINKSTAT_SYNCLOST_HOSTREQ 0x8003
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#define AN_LINKSTAT_SYNCLOST_AVGRETRY 0x8002
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#define AN_LINKSTAT_SYNCLOST_MAXRETRY 0x8001
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#define AN_LINKSTAT_SYNCLOST_MISSBEACON 0x8000
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/* memory handle management registers */
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#define AN_RX_FID 0x20
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#define AN_ALLOC_FID 0x22
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#define AN_TX_CMP_FID(x) (x ? 0x1a : 0x24)
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/*
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* Buffer Access Path (BAP) registers.
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* These are I/O channels. I believe you can use each one for
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* any desired purpose independently of the other. In general
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* though, we use BAP1 for reading and writing LTV records and
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* reading received data frames, and BAP0 for writing transmit
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* frames. This is a convention though, not a rule.
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*/
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#define AN_SEL0 0x18
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#define AN_SEL1 0x1A
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#define AN_OFF0 0x1C
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#define AN_OFF1 0x1E
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#define AN_DATA0 0x36
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#define AN_DATA1 0x38
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#define AN_BAP0 AN_DATA0
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#define AN_BAP1 AN_DATA1
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#define AN_OFF_BUSY 0x8000
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#define AN_OFF_ERR 0x4000
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#define AN_OFF_DONE 0x2000
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#define AN_OFF_DATAOFF 0x0FFF
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/* Event registers */
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#define AN_EVENT_STAT(x) (x ? 0x60 : 0x30) /* Event status */
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#define AN_INT_EN(x) (x ? 0x64 : 0x32) /* Interrupt enable/
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disable */
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#define AN_EVENT_ACK(x) (x ? 0x68 : 0x34) /* Ack event */
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/* Events */
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#define AN_EV_CLR_STUCK_BUSY 0x4000 /* clear stuck busy bit */
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#define AN_EV_WAKEREQUEST 0x2000 /* awaken from PSP mode */
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#define AN_EV_MIC 0x1000 /* Message Integrity Check*/
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#define AN_EV_AWAKE 0x0100 /* station woke up from PSP mode*/
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#define AN_EV_LINKSTAT 0x0080 /* link status available */
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#define AN_EV_CMD 0x0010 /* command completed */
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#define AN_EV_ALLOC 0x0008 /* async alloc/reclaim completed */
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#define AN_EV_TX_CPY 0x0400
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#define AN_EV_TX_EXC 0x0004 /* async xmit completed with failure */
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#define AN_EV_TX 0x0002 /* async xmit completed succesfully */
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#define AN_EV_RX 0x0001 /* async rx completed */
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#define AN_INTRS(x) \
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( x ? (AN_EV_RX|AN_EV_TX|AN_EV_TX_EXC|AN_EV_TX_CPY|AN_EV_ALLOC \
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|AN_EV_LINKSTAT|AN_EV_MIC) \
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: \
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(AN_EV_RX|AN_EV_TX|AN_EV_TX_EXC|AN_EV_ALLOC \
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|AN_EV_LINKSTAT|AN_EV_MIC) \
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)
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/* Host software registers */
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#define AN_SW0(x) (x ? 0x50 : 0x28)
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#define AN_SW1(x) (x ? 0x54 : 0x2A)
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#define AN_SW2(x) (x ? 0x58 : 0x2C)
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#define AN_SW3(x) (x ? 0x5c : 0x2E)
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#define AN_CNTL 0x14
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#define AN_CNTL_AUX_ENA 0xC000
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#define AN_CNTL_AUX_ENA_STAT 0xC000
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#define AN_CNTL_AUX_DIS_STAT 0x0000
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#define AN_CNTL_AUX_ENA_CNTL 0x8000
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#define AN_CNTL_AUX_DIS_CNTL 0x4000
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#define AN_AUX_PAGE 0x3A
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#define AN_AUX_OFFSET 0x3C
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#define AN_AUX_DATA 0x3E
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/*
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* Length, Type, Value (LTV) record definitions and RID values.
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*/
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struct an_ltv_gen {
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u_int16_t an_len;
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u_int16_t an_type;
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u_int16_t an_val;
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};
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#define AN_DEF_SSID_LEN 7
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#define AN_DEF_SSID "tsunami"
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#define AN_RXGAP_MAX 8
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/*
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* Transmit frame structure.
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*/
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struct an_txframe {
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u_int32_t an_tx_sw; /* 0x00 */
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u_int16_t an_tx_status; /* 0x04 */
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u_int16_t an_tx_payload_len; /* 0x06 */
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u_int16_t an_tx_ctl; /* 0x08 */
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u_int16_t an_tx_assoc_id; /* 0x0A */
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u_int16_t an_tx_retry; /* 0x0C */
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u_int8_t an_tx_assoc_cnt; /* 0x0E */
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u_int8_t an_tx_rate; /* 0x0F */
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u_int8_t an_tx_max_long_retries; /* 0x10 */
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u_int8_t an_tx_max_short_retries; /*0x11 */
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u_int8_t an_rsvd0[2]; /* 0x12 */
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u_int16_t an_frame_ctl; /* 0x14 */
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u_int16_t an_duration; /* 0x16 */
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u_int8_t an_addr1[6]; /* 0x18 */
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u_int8_t an_addr2[6]; /* 0x1E */
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u_int8_t an_addr3[6]; /* 0x24 */
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u_int16_t an_seq_ctl; /* 0x2A */
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u_int8_t an_addr4[6]; /* 0x2C */
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u_int8_t an_gaplen; /* 0x32 */
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} __packed;
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struct an_rxframe_802_3 {
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u_int16_t an_rx_802_3_status; /* 0x34 */
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u_int16_t an_rx_802_3_payload_len;/* 0x36 */
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u_int8_t an_rx_dst_addr[6]; /* 0x38 */
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u_int8_t an_rx_src_addr[6]; /* 0x3E */
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};
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#define AN_RXGAP_MAX 8
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struct an_txframe_802_3 {
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/*
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* Transmit 802.3 header structure.
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*/
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u_int16_t an_tx_802_3_status; /* 0x34 */
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u_int16_t an_tx_802_3_payload_len;/* 0x36 */
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u_int8_t an_tx_dst_addr[6]; /* 0x38 */
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u_int8_t an_tx_src_addr[6]; /* 0x3E */
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};
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#define AN_TXSTAT_EXCESS_RETRY 0x0002
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#define AN_TXSTAT_LIFE_EXCEEDED 0x0004
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#define AN_TXSTAT_AID_FAIL 0x0008
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#define AN_TXSTAT_MAC_DISABLED 0x0010
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#define AN_TXSTAT_ASSOC_LOST 0x0020
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#define AN_TXCTL_RSVD 0x0001
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#define AN_TXCTL_TXOK_INTR 0x0002
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#define AN_TXCTL_TXERR_INTR 0x0004
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#define AN_TXCTL_HEADER_TYPE 0x0008
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#define AN_TXCTL_PAYLOAD_TYPE 0x0010
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#define AN_TXCTL_NORELEASE 0x0020
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#define AN_TXCTL_NORETRIES 0x0040
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#define AN_TXCTL_CLEAR_AID 0x0080
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#define AN_TXCTL_STRICT_ORDER 0x0100
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#define AN_TXCTL_USE_RTS 0x0200
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#define AN_HEADERTYPE_8023 0x0000
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#define AN_HEADERTYPE_80211 0x0008
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#define AN_PAYLOADTYPE_ETHER 0x0000
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#define AN_PAYLOADTYPE_LLC 0x0010
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#define AN_TXCTL_80211 \
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(AN_TXCTL_TXOK_INTR|AN_TXCTL_TXERR_INTR|AN_HEADERTYPE_80211| \
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AN_PAYLOADTYPE_LLC|AN_TXCTL_NORELEASE)
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#define AN_TXCTL_8023 \
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(AN_TXCTL_TXOK_INTR|AN_TXCTL_TXERR_INTR|AN_HEADERTYPE_8023| \
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AN_PAYLOADTYPE_ETHER|AN_TXCTL_NORELEASE)
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#define AN_TXGAP_80211 0
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#define AN_TXGAP_8023 0
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struct an_802_3_hdr {
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u_int16_t an_8023_status;
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u_int16_t an_8023_payload_len;
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u_int8_t an_8023_dst_addr[6];
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u_int8_t an_8023_src_addr[6];
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u_int16_t an_8023_dat[3]; /* SNAP header */
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u_int16_t an_8023_type;
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};
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struct an_snap_hdr {
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u_int16_t an_snap_dat[3]; /* SNAP header */
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u_int16_t an_snap_type;
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};
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struct an_dma_alloc {
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u_int32_t an_dma_paddr;
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caddr_t an_dma_vaddr;
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bus_dmamap_t an_dma_map;
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bus_dma_segment_t an_dma_seg;
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bus_size_t an_dma_size;
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int an_dma_nseg;
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};
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#define AN_TX_RING_CNT 4
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#define AN_INC(x, y) (x) = (x + 1) % y
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struct an_tx_ring_data {
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u_int16_t an_tx_fids[AN_TX_RING_CNT];
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u_int16_t an_tx_ring[AN_TX_RING_CNT];
|
|
int an_tx_prod;
|
|
int an_tx_cons;
|
|
int an_tx_empty;
|
|
};
|
|
|
|
struct an_softc {
|
|
struct arpcom arpcom;
|
|
|
|
int an_unit;
|
|
|
|
int port_rid; /* resource id for port range */
|
|
struct resource* port_res; /* resource for port range */
|
|
int mem_rid; /* resource id for memory range */
|
|
int mem_used; /* nonzero if memory used */
|
|
struct resource* mem_res; /* resource for memory range */
|
|
int mem_aux_rid; /* resource id for memory range */
|
|
int mem_aux_used; /* nonzero if memory used */
|
|
struct resource* mem_aux_res; /* resource for memory range */
|
|
int irq_rid; /* resource id for irq */
|
|
void* irq_handle; /* handle for irq handler */
|
|
struct resource* irq_res; /* resource for irq */
|
|
|
|
bus_space_handle_t an_bhandle_p;
|
|
bus_space_handle_t an_bhandle;
|
|
bus_space_tag_t an_btag;
|
|
bus_space_handle_t an_mem_bhandle;
|
|
bus_space_tag_t an_mem_btag;
|
|
bus_space_handle_t an_mem_aux_bhandle;
|
|
bus_space_tag_t an_mem_aux_btag;
|
|
bus_dma_tag_t an_dtag;
|
|
struct an_ltv_genconfig an_config;
|
|
struct an_ltv_caps an_caps;
|
|
struct an_ltv_ssidlist_new an_ssidlist;
|
|
struct an_ltv_aplist an_aplist;
|
|
struct an_ltv_key an_temp_keys[4];
|
|
int an_tx_rate;
|
|
int an_rxmode;
|
|
int an_gone;
|
|
int an_if_flags;
|
|
u_int8_t an_txbuf[1536];
|
|
struct an_tx_ring_data an_rdata;
|
|
struct an_ltv_stats an_stats;
|
|
struct an_ltv_status an_status;
|
|
u_int8_t an_associated;
|
|
#ifdef ANCACHE
|
|
int an_sigitems;
|
|
struct an_sigcache an_sigcache[MAXANCACHE];
|
|
int an_nextitem;
|
|
int an_have_rssimap;
|
|
struct an_ltv_rssi_map an_rssimap;
|
|
#endif
|
|
struct callout_handle an_stat_ch;
|
|
struct mtx an_mtx;
|
|
device_t an_dev;
|
|
struct ifmedia an_ifmedia;
|
|
int an_monitor;
|
|
int an_was_monitor;
|
|
u_char buf_802_11[MCLBYTES];
|
|
struct an_req areq;
|
|
unsigned short* an_flash_buffer;
|
|
int mpi350;
|
|
struct an_dma_alloc an_rid_buffer;
|
|
struct an_dma_alloc an_rx_buffer[AN_MAX_RX_DESC];
|
|
struct an_dma_alloc an_tx_buffer[AN_MAX_TX_DESC];
|
|
};
|
|
|
|
#define AN_LOCK(_sc) mtx_lock(&(_sc)->an_mtx)
|
|
#define AN_UNLOCK(_sc) mtx_unlock(&(_sc)->an_mtx)
|
|
|
|
void an_release_resources (device_t);
|
|
int an_alloc_port (device_t, int, int);
|
|
int an_alloc_memory (device_t, int, int);
|
|
int an_alloc_aux_memory (device_t, int, int);
|
|
int an_alloc_irq (device_t, int, int);
|
|
int an_probe (device_t);
|
|
void an_shutdown (device_t);
|
|
void an_resume (device_t);
|
|
int an_attach (struct an_softc *, int, int);
|
|
void an_stop (struct an_softc *);
|
|
|
|
driver_intr_t an_intr;
|
|
|
|
#define AN_802_3_OFFSET 0x2E
|
|
#define AN_802_11_OFFSET 0x44
|
|
#define AN_802_11_OFFSET_RAW 0x3C
|
|
|
|
#define AN_STAT_BADCRC 0x0001
|
|
#define AN_STAT_UNDECRYPTABLE 0x0002
|
|
#define AN_STAT_ERRSTAT 0x0003
|
|
#define AN_STAT_MAC_PORT 0x0700
|
|
#define AN_STAT_1042 0x2000 /* RFC1042 encoded */
|
|
#define AN_STAT_TUNNEL 0x4000 /* Bridge-tunnel encoded */
|
|
#define AN_STAT_WMP_MSG 0x6000 /* WaveLAN-II management protocol */
|
|
#define AN_RXSTAT_MSG_TYPE 0xE000
|
|
|
|
#define AN_ENC_TX_802_3 0x00
|
|
#define AN_ENC_TX_802_11 0x11
|
|
#define AN_ENC_TX_E_II 0x0E
|
|
|
|
#define AN_ENC_TX_1042 0x00
|
|
#define AN_ENC_TX_TUNNEL 0xF8
|
|
|
|
#define AN_TXCNTL_MACPORT 0x00FF
|
|
#define AN_TXCNTL_STRUCTTYPE 0xFF00
|
|
|
|
/*
|
|
* SNAP (sub-network access protocol) constants for transmission
|
|
* of IP datagrams over IEEE 802 networks, taken from RFC1042.
|
|
* We need these for the LLC/SNAP header fields in the TX/RX frame
|
|
* structure.
|
|
*/
|
|
#define AN_SNAP_K1 0xaa /* assigned global SAP for SNAP */
|
|
#define AN_SNAP_K2 0x00
|
|
#define AN_SNAP_CONTROL 0x03 /* unnumbered information format */
|
|
#define AN_SNAP_WORD0 (AN_SNAP_K1 | (AN_SNAP_K1 << 8))
|
|
#define AN_SNAP_WORD1 (AN_SNAP_K2 | (AN_SNAP_CONTROL << 8))
|
|
#define AN_SNAPHDR_LEN 0x6
|