Roger Pau Monné 5ea878684f bhyve/ioapic: improve the tracking of IRR bit ... One common method of EOI'ing an interrupt at the IO-APIC level is to switch the pin to edge triggering mode and then back into level mode. That would cause the IRR bit to be cleared and thus further interrupts to be injected. FreeBSD does indeed use that method if the IO-APIC EOI register is not supported. The bhyve IO-APIC emulation code didn't clear the IRR bit when doing that switch, and was also missing acknowledging the IRR state when trying to inject an interrupt in vioapic_send_intr. Reviewed by: grehan Differential revision: https://reviews.freebsd.org/D28238		2021-02-02 09:47:00 +01:00
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iommu.c
iommu.h
ppt.c	Pull the check for VM ownership into ppt_find().	2020-11-24 23:56:33 +00:00
ppt.h	Honor the disabled setting for MSI-X interrupts for passthrough devices.	2020-11-24 23:18:52 +00:00
vatpic.c	amd64: clean up empty lines in .c and .h files	2020-09-01 21:16:54 +00:00
vatpic.h
vatpit.c	amd64: clean up empty lines in .c and .h files	2020-09-01 21:16:54 +00:00
vatpit.h
vhpet.c
vhpet.h
vioapic.c	bhyve/ioapic: improve the tracking of IRR bit	2021-02-02 09:47:00 +01:00
vioapic.h
vlapic_priv.h
vlapic.c	amd64: clean up empty lines in .c and .h files	2020-09-01 21:16:54 +00:00
vlapic.h
vpmtmr.c
vpmtmr.h
vrtc.c
vrtc.h