a89156f53f
in all but ARMv4 specific files. Expand ARMv6 compatibility stubs in cpu-v4.h. Use physical address in L2 cache functions if ARM_L2_PIPT is defined.
530 lines
15 KiB
C
530 lines
15 KiB
C
/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */
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/*-
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* Copyright (c) 1997 Mark Brinicombe.
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* Copyright (c) 1997 Causality Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Causality Limited.
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* 4. The name of Causality Limited may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RiscBSD kernel project
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*
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* cpufunc.h
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*
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* Prototypes for cpu, mmu and tlb related functions.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_CPUFUNC_H_
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#define _MACHINE_CPUFUNC_H_
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#ifdef _KERNEL
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#include <sys/types.h>
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#include <machine/armreg.h>
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#include <machine/cpuconf.h>
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static __inline void
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breakpoint(void)
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{
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__asm(".word 0xe7ffffff");
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}
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struct cpu_functions {
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/* CPU functions */
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void (*cf_cpwait) (void);
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/* MMU functions */
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u_int (*cf_control) (u_int bic, u_int eor);
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void (*cf_setttb) (u_int ttb);
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/* TLB functions */
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void (*cf_tlb_flushID) (void);
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void (*cf_tlb_flushID_SE) (u_int va);
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void (*cf_tlb_flushD) (void);
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void (*cf_tlb_flushD_SE) (u_int va);
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/*
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* Cache operations:
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*
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* We define the following primitives:
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*
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* icache_sync_range Synchronize I-cache range
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*
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* dcache_wbinv_all Write-back and Invalidate D-cache
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* dcache_wbinv_range Write-back and Invalidate D-cache range
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* dcache_inv_range Invalidate D-cache range
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* dcache_wb_range Write-back D-cache range
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*
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* idcache_wbinv_all Write-back and Invalidate D-cache,
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* Invalidate I-cache
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* idcache_wbinv_range Write-back and Invalidate D-cache,
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* Invalidate I-cache range
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*
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* Note that the ARM term for "write-back" is "clean". We use
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* the term "write-back" since it's a more common way to describe
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* the operation.
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*
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* There are some rules that must be followed:
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*
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* ID-cache Invalidate All:
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* Unlike other functions, this one must never write back.
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* It is used to intialize the MMU when it is in an unknown
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* state (such as when it may have lines tagged as valid
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* that belong to a previous set of mappings).
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*
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* I-cache Sync range:
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* The goal is to synchronize the instruction stream,
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* so you may beed to write-back dirty D-cache blocks
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* first. If a range is requested, and you can't
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* synchronize just a range, you have to hit the whole
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* thing.
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*
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* D-cache Write-Back and Invalidate range:
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* If you can't WB-Inv a range, you must WB-Inv the
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* entire D-cache.
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*
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* D-cache Invalidate:
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* If you can't Inv the D-cache, you must Write-Back
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* and Invalidate. Code that uses this operation
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* MUST NOT assume that the D-cache will not be written
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* back to memory.
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*
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* D-cache Write-Back:
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* If you can't Write-back without doing an Inv,
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* that's fine. Then treat this as a WB-Inv.
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* Skipping the invalidate is merely an optimization.
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*
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* All operations:
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* Valid virtual addresses must be passed to each
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* cache operation.
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*/
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void (*cf_icache_sync_range) (vm_offset_t, vm_size_t);
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void (*cf_dcache_wbinv_all) (void);
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void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t);
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void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t);
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void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t);
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void (*cf_idcache_inv_all) (void);
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void (*cf_idcache_wbinv_all) (void);
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void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t);
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void (*cf_l2cache_wbinv_all) (void);
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void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t);
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void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t);
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void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t);
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void (*cf_l2cache_drain_writebuf) (void);
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/* Other functions */
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void (*cf_drain_writebuf) (void);
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void (*cf_sleep) (int mode);
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/* Soft functions */
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void (*cf_context_switch) (void);
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void (*cf_setup) (void);
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};
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extern struct cpu_functions cpufuncs;
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extern u_int cputype;
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#if __ARM_ARCH < 6
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#define cpu_cpwait() cpufuncs.cf_cpwait()
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#endif
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#define cpu_control(c, e) cpufuncs.cf_control(c, e)
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#if __ARM_ARCH < 6
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#define cpu_setttb(t) cpufuncs.cf_setttb(t)
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#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID()
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#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e)
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#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD()
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#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e)
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#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s))
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#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all()
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#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s))
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#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s))
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#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s))
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#define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all()
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#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all()
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#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))
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#endif
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#define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all()
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#define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s))
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#define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s))
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#define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s))
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#define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf()
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#if __ARM_ARCH < 6
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#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf()
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#endif
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#define cpu_sleep(m) cpufuncs.cf_sleep(m)
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#define cpu_setup() cpufuncs.cf_setup()
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int set_cpufuncs (void);
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#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */
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#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */
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void cpufunc_nullop (void);
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u_int cpu_ident (void);
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u_int cpufunc_control (u_int clear, u_int bic);
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void cpu_domains (u_int domains);
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u_int cpu_faultstatus (void);
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u_int cpu_faultaddress (void);
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u_int cpu_get_control (void);
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u_int cpu_pfr (int);
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#if defined(CPU_FA526)
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void fa526_setup (void);
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void fa526_setttb (u_int ttb);
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void fa526_context_switch (void);
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void fa526_cpu_sleep (int);
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void fa526_tlb_flushID_SE (u_int);
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void fa526_icache_sync_range(vm_offset_t start, vm_size_t end);
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void fa526_dcache_wbinv_all (void);
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void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end);
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void fa526_dcache_inv_range (vm_offset_t start, vm_size_t end);
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void fa526_dcache_wb_range (vm_offset_t start, vm_size_t end);
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void fa526_idcache_wbinv_all(void);
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void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end);
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#endif
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#if defined(CPU_ARM9) || defined(CPU_ARM9E)
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void arm9_setttb (u_int);
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void arm9_tlb_flushID_SE (u_int va);
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void arm9_context_switch (void);
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#endif
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#if defined(CPU_ARM9)
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void arm9_icache_sync_range (vm_offset_t, vm_size_t);
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void arm9_dcache_wbinv_all (void);
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void arm9_dcache_wbinv_range (vm_offset_t, vm_size_t);
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void arm9_dcache_inv_range (vm_offset_t, vm_size_t);
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void arm9_dcache_wb_range (vm_offset_t, vm_size_t);
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void arm9_idcache_wbinv_all (void);
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void arm9_idcache_wbinv_range (vm_offset_t, vm_size_t);
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void arm9_setup (void);
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extern unsigned arm9_dcache_sets_max;
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extern unsigned arm9_dcache_sets_inc;
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extern unsigned arm9_dcache_index_max;
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extern unsigned arm9_dcache_index_inc;
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#endif
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#if defined(CPU_ARM9E)
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void arm10_setup (void);
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u_int sheeva_control_ext (u_int, u_int);
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void sheeva_cpu_sleep (int);
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void sheeva_setttb (u_int);
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void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t);
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void sheeva_dcache_inv_range (vm_offset_t, vm_size_t);
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void sheeva_dcache_wb_range (vm_offset_t, vm_size_t);
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void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t);
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void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t);
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void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t);
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void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t);
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void sheeva_l2cache_wbinv_all (void);
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#endif
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#if defined(CPU_MV_PJ4B)
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void armv6_idcache_wbinv_all (void);
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#endif
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#if defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT)
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void armv7_setttb (u_int);
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void armv7_tlb_flushID (void);
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void armv7_tlb_flushID_SE (u_int);
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void armv7_icache_sync_range (vm_offset_t, vm_size_t);
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void armv7_idcache_wbinv_range (vm_offset_t, vm_size_t);
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void armv7_idcache_inv_all (void);
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void armv7_dcache_wbinv_all (void);
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void armv7_idcache_wbinv_all (void);
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void armv7_dcache_wbinv_range (vm_offset_t, vm_size_t);
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void armv7_dcache_inv_range (vm_offset_t, vm_size_t);
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void armv7_dcache_wb_range (vm_offset_t, vm_size_t);
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void armv7_cpu_sleep (int);
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void armv7_setup (void);
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void armv7_context_switch (void);
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void armv7_drain_writebuf (void);
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void armv7_sev (void);
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u_int armv7_auxctrl (u_int, u_int);
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void armadaxp_idcache_wbinv_all (void);
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void cortexa_setup (void);
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#endif
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#if defined(CPU_MV_PJ4B)
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void pj4b_config (void);
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void pj4bv7_setup (void);
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#endif
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#if defined(CPU_ARM1176)
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void arm11_tlb_flushID (void);
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void arm11_tlb_flushID_SE (u_int);
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void arm11_tlb_flushD (void);
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void arm11_tlb_flushD_SE (u_int va);
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void arm11_context_switch (void);
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void arm11_drain_writebuf (void);
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void armv6_dcache_wbinv_range (vm_offset_t, vm_size_t);
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void armv6_dcache_inv_range (vm_offset_t, vm_size_t);
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void armv6_dcache_wb_range (vm_offset_t, vm_size_t);
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void armv6_idcache_inv_all (void);
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void arm11x6_setttb (u_int);
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void arm11x6_idcache_wbinv_all (void);
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void arm11x6_dcache_wbinv_all (void);
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void arm11x6_icache_sync_range (vm_offset_t, vm_size_t);
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void arm11x6_idcache_wbinv_range (vm_offset_t, vm_size_t);
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void arm11x6_setup (void);
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void arm11x6_sleep (int); /* no ref. for errata */
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#endif
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#if defined(CPU_ARM9E)
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void armv5_ec_setttb(u_int);
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void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t);
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void armv5_ec_dcache_wbinv_all(void);
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void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t);
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void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t);
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void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t);
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void armv5_ec_idcache_wbinv_all(void);
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void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t);
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#endif
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#if defined(CPU_ARM9) || defined(CPU_ARM9E) || \
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defined(CPU_FA526) || \
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defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
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defined(CPU_XSCALE_81342)
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void armv4_tlb_flushID (void);
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void armv4_tlb_flushD (void);
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void armv4_tlb_flushD_SE (u_int va);
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void armv4_drain_writebuf (void);
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void armv4_idcache_inv_all (void);
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#endif
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#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
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defined(CPU_XSCALE_81342)
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void xscale_cpwait (void);
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void xscale_cpu_sleep (int mode);
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u_int xscale_control (u_int clear, u_int bic);
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void xscale_setttb (u_int ttb);
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void xscale_tlb_flushID_SE (u_int va);
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void xscale_cache_flushID (void);
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void xscale_cache_flushI (void);
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void xscale_cache_flushD (void);
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void xscale_cache_flushD_SE (u_int entry);
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void xscale_cache_cleanID (void);
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void xscale_cache_cleanD (void);
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void xscale_cache_cleanD_E (u_int entry);
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void xscale_cache_clean_minidata (void);
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void xscale_cache_purgeID (void);
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void xscale_cache_purgeID_E (u_int entry);
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void xscale_cache_purgeD (void);
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void xscale_cache_purgeD_E (u_int entry);
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void xscale_cache_syncI (void);
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void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
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void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
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void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
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void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
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void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end);
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void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end);
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void xscale_context_switch (void);
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void xscale_setup (void);
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#endif /* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */
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#ifdef CPU_XSCALE_81342
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void xscalec3_l2cache_purge (void);
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void xscalec3_cache_purgeID (void);
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void xscalec3_cache_purgeD (void);
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void xscalec3_cache_cleanID (void);
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void xscalec3_cache_cleanD (void);
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void xscalec3_cache_syncI (void);
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void xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
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void xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
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void xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
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void xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
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void xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end);
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void xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t);
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void xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end);
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void xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end);
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void xscalec3_setttb (u_int ttb);
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void xscalec3_context_switch (void);
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#endif /* CPU_XSCALE_81342 */
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/*
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* Macros for manipulating CPU interrupts
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*/
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#if __ARM_ARCH < 6
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#define __ARM_INTR_BITS (PSR_I | PSR_F)
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#else
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#define __ARM_INTR_BITS (PSR_I | PSR_F | PSR_A)
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#endif
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static __inline uint32_t
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__set_cpsr(uint32_t bic, uint32_t eor)
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{
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uint32_t tmp, ret;
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__asm __volatile(
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"mrs %0, cpsr\n" /* Get the CPSR */
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"bic %1, %0, %2\n" /* Clear bits */
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"eor %1, %1, %3\n" /* XOR bits */
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"msr cpsr_xc, %1\n" /* Set the CPSR */
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: "=&r" (ret), "=&r" (tmp)
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: "r" (bic), "r" (eor) : "memory");
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return ret;
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}
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static __inline uint32_t
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disable_interrupts(uint32_t mask)
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{
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return (__set_cpsr(mask & __ARM_INTR_BITS, mask & __ARM_INTR_BITS));
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}
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static __inline uint32_t
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enable_interrupts(uint32_t mask)
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{
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return (__set_cpsr(mask & __ARM_INTR_BITS, 0));
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}
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static __inline uint32_t
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restore_interrupts(uint32_t old_cpsr)
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{
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return (__set_cpsr(__ARM_INTR_BITS, old_cpsr & __ARM_INTR_BITS));
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}
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static __inline register_t
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intr_disable(void)
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{
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return (disable_interrupts(PSR_I | PSR_F));
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}
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static __inline void
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intr_restore(register_t s)
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{
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restore_interrupts(s);
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}
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#undef __ARM_INTR_BITS
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/*
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* Functions to manipulate cpu r13
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* (in arm/arm32/setstack.S)
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*/
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void set_stackptr (u_int mode, u_int address);
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u_int get_stackptr (u_int mode);
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/*
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* Miscellany
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*/
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int get_pc_str_offset (void);
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/*
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* CPU functions from locore.S
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*/
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void cpu_reset (void) __attribute__((__noreturn__));
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/*
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* Cache info variables.
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*/
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/* PRIMARY CACHE VARIABLES */
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extern int arm_picache_size;
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extern int arm_picache_line_size;
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extern int arm_picache_ways;
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extern int arm_pdcache_size; /* and unified */
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extern int arm_pdcache_line_size;
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extern int arm_pdcache_ways;
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extern int arm_pcache_type;
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extern int arm_pcache_unified;
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|
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extern int arm_dcache_align;
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extern int arm_dcache_align_mask;
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extern u_int arm_cache_level;
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extern u_int arm_cache_loc;
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extern u_int arm_cache_type[14];
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#endif /* _KERNEL */
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#endif /* _MACHINE_CPUFUNC_H_ */
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/* End of cpufunc.h */
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