219d14fe5f
Executive is a library that can be used by standalone applications and kernels to abstract access to Octeon SoC and board-specific hardware and facilities. The FreeBSD port to Octeon will be updated to use this where possible.
74293 lines
5.5 MiB
74293 lines
5.5 MiB
/***********************license start***************
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* Copyright (c) 2003-2009 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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*
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
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* OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
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* RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
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* REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
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* DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
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* OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
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* PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
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* POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
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* OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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*
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*
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* For any questions regarding licensing please contact marketing@caviumnetworks.com
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*
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***********************license end**************************************/
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/**
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* @file
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*
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* Configuration and status register (CSR) address and type definitions for
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* Octeon.
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*
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* This file is auto generated. Do not edit.
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*
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* <hr>$Revision: 41586 $<hr>
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*
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*/
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#include "cvmx-csr-db.h"
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static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn38xxp2[] = {
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/* name , ---------------type, bits, off, #field, fld of */
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{"cvmx_asx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 4, 0},
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{"cvmx_asx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 4, 4},
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{"cvmx_asx#_prt_loop" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 3, 8},
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{"cvmx_asx#_rld_bypass" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 2, 11},
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{"cvmx_asx#_rld_bypass_setting", CVMX_CSR_DB_TYPE_RSL, 64, 8, 2, 13},
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{"cvmx_asx#_rld_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 3, 15},
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{"cvmx_asx#_rld_data_drv" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 3, 18},
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{"cvmx_asx#_rld_fcram_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 2, 21},
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{"cvmx_asx#_rld_nctl_strong" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 2, 23},
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{"cvmx_asx#_rld_nctl_weak" , CVMX_CSR_DB_TYPE_RSL, 64, 18, 2, 25},
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{"cvmx_asx#_rld_pctl_strong" , CVMX_CSR_DB_TYPE_RSL, 64, 20, 2, 27},
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{"cvmx_asx#_rld_pctl_weak" , CVMX_CSR_DB_TYPE_RSL, 64, 22, 2, 29},
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{"cvmx_asx#_rld_setting" , CVMX_CSR_DB_TYPE_RSL, 64, 24, 2, 31},
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{"cvmx_asx#_rx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 26, 2, 33},
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{"cvmx_asx#_rx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 34, 2, 35},
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{"cvmx_asx#_rx_wol" , CVMX_CSR_DB_TYPE_RSL, 64, 36, 3, 37},
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{"cvmx_asx#_rx_wol_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 38, 1, 40},
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{"cvmx_asx#_rx_wol_powok" , CVMX_CSR_DB_TYPE_RSL, 64, 40, 2, 41},
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{"cvmx_asx#_rx_wol_sig" , CVMX_CSR_DB_TYPE_RSL, 64, 42, 2, 43},
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{"cvmx_asx#_tx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 44, 2, 45},
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{"cvmx_asx#_tx_comp_byp" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 3, 47},
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{"cvmx_asx#_tx_hi_water#" , CVMX_CSR_DB_TYPE_RSL, 64, 54, 2, 50},
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{"cvmx_asx#_tx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 62, 2, 52},
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{"cvmx_asx0_dbg_data_drv" , CVMX_CSR_DB_TYPE_RSL, 64, 64, 3, 54},
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{"cvmx_asx0_dbg_data_enable" , CVMX_CSR_DB_TYPE_RSL, 64, 65, 2, 57},
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{"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 66, 2, 59},
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{"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 67, 2, 61},
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{"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 68, 2, 63},
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{"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 69, 2, 65},
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{"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 70, 15, 67},
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{"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 103, 2, 82},
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{"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 136, 15, 84},
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{"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 169, 2, 99},
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{"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 170, 2, 101},
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{"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 186, 2, 103},
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{"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 202, 2, 105},
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{"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 203, 2, 107},
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{"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 204, 2, 109},
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{"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 205, 1, 111},
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{"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 221, 3, 112},
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{"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 222, 2, 115},
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{"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 223, 4, 117},
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{"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 224, 2, 121},
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{"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 225, 3, 123},
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{"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 229, 7, 126},
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{"cvmx_dbg_data" , CVMX_CSR_DB_TYPE_NCB, 64, 245, 7, 133},
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{"cvmx_dfa_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 246, 3, 140},
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{"cvmx_dfa_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 247, 10, 143},
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{"cvmx_dfa_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 248, 2, 153},
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{"cvmx_dfa_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 249, 2, 155},
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{"cvmx_dfa_difctl" , CVMX_CSR_DB_TYPE_NCB, 64, 250, 4, 157},
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{"cvmx_dfa_difrdptr" , CVMX_CSR_DB_TYPE_NCB, 64, 251, 3, 161},
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{"cvmx_dfa_err" , CVMX_CSR_DB_TYPE_RSL, 64, 252, 21, 164},
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{"cvmx_dfa_memcfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 253, 16, 185},
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{"cvmx_dfa_memcfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 254, 11, 201},
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{"cvmx_dfa_memcfg2" , CVMX_CSR_DB_TYPE_RSL, 64, 255, 8, 212},
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{"cvmx_dfa_memfadr" , CVMX_CSR_DB_TYPE_RSL, 64, 256, 6, 220},
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{"cvmx_dfa_memfcr" , CVMX_CSR_DB_TYPE_RSL, 64, 257, 6, 226},
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{"cvmx_dfa_memrld" , CVMX_CSR_DB_TYPE_RSL, 64, 258, 2, 232},
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{"cvmx_dfa_ncbctl" , CVMX_CSR_DB_TYPE_RSL, 64, 259, 8, 234},
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{"cvmx_dfa_sbd_dbg0" , CVMX_CSR_DB_TYPE_RSL, 64, 260, 1, 242},
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{"cvmx_dfa_sbd_dbg1" , CVMX_CSR_DB_TYPE_RSL, 64, 261, 1, 243},
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{"cvmx_dfa_sbd_dbg2" , CVMX_CSR_DB_TYPE_RSL, 64, 262, 1, 244},
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{"cvmx_dfa_sbd_dbg3" , CVMX_CSR_DB_TYPE_RSL, 64, 263, 1, 245},
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{"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 264, 6, 246},
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{"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 265, 7, 252},
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{"cvmx_fpa_fpf#_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 266, 3, 259},
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{"cvmx_fpa_fpf#_size" , CVMX_CSR_DB_TYPE_RSL, 64, 273, 2, 262},
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{"cvmx_fpa_fpf0_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 280, 3, 264},
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{"cvmx_fpa_fpf0_size" , CVMX_CSR_DB_TYPE_RSL, 64, 281, 2, 267},
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{"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 282, 29, 269},
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{"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 283, 29, 298},
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{"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 284, 2, 327},
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{"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 292, 2, 329},
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{"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 300, 3, 331},
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{"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 301, 3, 334},
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{"cvmx_fpa_wart_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 302, 2, 337},
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{"cvmx_fpa_wart_status" , CVMX_CSR_DB_TYPE_RSL, 64, 303, 2, 339},
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{"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 304, 8, 341},
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{"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 306, 2, 349},
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{"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 308, 3, 351},
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{"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 310, 2, 354},
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{"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 312, 5, 356},
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{"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 320, 1, 361},
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{"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 328, 1, 362},
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{"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 336, 1, 363},
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{"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 344, 1, 364},
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{"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 352, 1, 365},
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{"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 360, 1, 366},
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{"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 368, 2, 367},
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{"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 376, 4, 369},
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{"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 384, 2, 373},
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{"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 392, 11, 375},
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{"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 400, 9, 386},
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{"cvmx_gmx#_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 408, 2, 395},
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{"cvmx_gmx#_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 416, 2, 397},
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{"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 424, 2, 399},
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{"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 432, 20, 401},
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{"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 440, 20, 421},
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{"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 448, 2, 441},
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{"cvmx_gmx#_rx#_rx_inbnd" , CVMX_CSR_DB_TYPE_RSL, 64, 456, 4, 443},
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{"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 464, 2, 447},
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{"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 472, 2, 449},
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{"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 480, 2, 451},
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{"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 488, 2, 453},
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{"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 496, 2, 455},
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{"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 504, 2, 457},
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{"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 512, 2, 459},
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{"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 520, 2, 461},
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{"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 528, 2, 463},
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{"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 536, 2, 465},
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{"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 544, 4, 467},
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{"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 552, 2, 471},
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{"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 560, 2, 473},
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{"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 568, 2, 475},
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{"cvmx_gmx#_rx_pass_en" , CVMX_CSR_DB_TYPE_RSL, 64, 576, 2, 477},
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{"cvmx_gmx#_rx_pass_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 578, 2, 479},
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{"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 610, 2, 481},
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{"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 612, 2, 483},
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{"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 620, 3, 485},
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{"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 622, 5, 488},
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{"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 630, 2, 493},
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{"cvmx_gmx#_tx#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 638, 2, 495},
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{"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 646, 3, 497},
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{"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 654, 2, 500},
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{"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 662, 2, 502},
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{"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 670, 2, 504},
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{"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 678, 2, 506},
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{"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 686, 2, 508},
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{"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 694, 2, 510},
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{"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 702, 2, 512},
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{"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 710, 2, 514},
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{"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 718, 2, 516},
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{"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 726, 2, 518},
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{"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 734, 2, 520},
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{"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 742, 2, 522},
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{"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 750, 2, 524},
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{"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 758, 2, 526},
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{"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 766, 2, 528},
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{"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 774, 2, 530},
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{"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 782, 2, 532},
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{"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 790, 2, 534},
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{"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 798, 2, 536},
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{"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 806, 2, 538},
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{"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 808, 2, 540},
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{"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 810, 2, 542},
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{"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 812, 3, 544},
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{"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 814, 7, 547},
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{"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 816, 7, 554},
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{"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 818, 2, 561},
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{"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 820, 2, 563},
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{"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 822, 4, 565},
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{"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 824, 2, 569},
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{"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 826, 2, 571},
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{"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 828, 2, 573},
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{"cvmx_gmx#_tx_spi_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 830, 3, 575},
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|
{"cvmx_gmx#_tx_spi_max" , CVMX_CSR_DB_TYPE_RSL, 64, 832, 3, 578},
|
|
{"cvmx_gmx#_tx_spi_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 834, 2, 581},
|
|
{"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 836, 7, 583},
|
|
{"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 852, 2, 590},
|
|
{"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 853, 2, 592},
|
|
{"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 854, 2, 594},
|
|
{"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 855, 2, 596},
|
|
{"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 856, 19, 598},
|
|
{"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 857, 6, 617},
|
|
{"cvmx_iob_dwb_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 858, 3, 623},
|
|
{"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 859, 3, 626},
|
|
{"cvmx_iob_i2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 860, 3, 629},
|
|
{"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 861, 5, 632},
|
|
{"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 862, 5, 637},
|
|
{"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 863, 1, 642},
|
|
{"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 864, 1, 643},
|
|
{"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 865, 5, 644},
|
|
{"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 866, 5, 649},
|
|
{"cvmx_iob_n2c_l2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 867, 3, 654},
|
|
{"cvmx_iob_n2c_rsp_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 868, 3, 657},
|
|
{"cvmx_iob_outb_com_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 869, 3, 660},
|
|
{"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 870, 5, 663},
|
|
{"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 871, 5, 668},
|
|
{"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 872, 1, 673},
|
|
{"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 873, 1, 674},
|
|
{"cvmx_iob_outb_fpa_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 874, 3, 675},
|
|
{"cvmx_iob_outb_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 875, 3, 678},
|
|
{"cvmx_iob_p2c_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 876, 3, 681},
|
|
{"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 877, 2, 684},
|
|
{"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 878, 2, 686},
|
|
{"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 879, 2, 688},
|
|
{"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 880, 2, 690},
|
|
{"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 881, 17, 692},
|
|
{"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 882, 2, 709},
|
|
{"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 883, 1, 711},
|
|
{"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 884, 9, 712},
|
|
{"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 885, 6, 721},
|
|
{"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 886, 6, 727},
|
|
{"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 887, 2, 733},
|
|
{"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 888, 2, 735},
|
|
{"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 889, 3, 737},
|
|
{"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 925, 2, 740},
|
|
{"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 961, 6, 742},
|
|
{"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 962, 2, 748},
|
|
{"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 970, 2, 750},
|
|
{"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 971, 3, 752},
|
|
{"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 972, 5, 755},
|
|
{"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 980, 3, 760},
|
|
{"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 981, 2, 763},
|
|
{"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 982, 2, 765},
|
|
{"cvmx_key_bist_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 983, 4, 767},
|
|
{"cvmx_key_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 984, 3, 771},
|
|
{"cvmx_key_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 985, 5, 774},
|
|
{"cvmx_key_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 986, 5, 779},
|
|
{"cvmx_l2c_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 987, 5, 784},
|
|
{"cvmx_l2c_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 988, 5, 789},
|
|
{"cvmx_l2c_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 989, 8, 794},
|
|
{"cvmx_l2c_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 990, 9, 802},
|
|
{"cvmx_l2c_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 991, 8, 811},
|
|
{"cvmx_l2c_dut" , CVMX_CSR_DB_TYPE_RSL, 64, 992, 5, 819},
|
|
{"cvmx_l2c_lckbase" , CVMX_CSR_DB_TYPE_RSL, 64, 993, 4, 824},
|
|
{"cvmx_l2c_lckoff" , CVMX_CSR_DB_TYPE_RSL, 64, 994, 2, 828},
|
|
{"cvmx_l2c_lfb0" , CVMX_CSR_DB_TYPE_RSL, 64, 995, 14, 830},
|
|
{"cvmx_l2c_lfb1" , CVMX_CSR_DB_TYPE_RSL, 64, 996, 19, 844},
|
|
{"cvmx_l2c_lfb2" , CVMX_CSR_DB_TYPE_RSL, 64, 997, 3, 863},
|
|
{"cvmx_l2c_lfb3" , CVMX_CSR_DB_TYPE_RSL, 64, 998, 3, 866},
|
|
{"cvmx_l2c_pfc#" , CVMX_CSR_DB_TYPE_RSL, 64, 999, 2, 869},
|
|
{"cvmx_l2c_pfctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1003, 17, 871},
|
|
{"cvmx_l2c_spar0" , CVMX_CSR_DB_TYPE_RSL, 64, 1004, 5, 888},
|
|
{"cvmx_l2c_spar1" , CVMX_CSR_DB_TYPE_RSL, 64, 1005, 5, 893},
|
|
{"cvmx_l2c_spar2" , CVMX_CSR_DB_TYPE_RSL, 64, 1006, 5, 898},
|
|
{"cvmx_l2c_spar3" , CVMX_CSR_DB_TYPE_RSL, 64, 1007, 5, 903},
|
|
{"cvmx_l2c_spar4" , CVMX_CSR_DB_TYPE_RSL, 64, 1008, 2, 908},
|
|
{"cvmx_l2d_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 1009, 3, 910},
|
|
{"cvmx_l2d_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 1010, 2, 913},
|
|
{"cvmx_l2d_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 1011, 2, 915},
|
|
{"cvmx_l2d_bst3" , CVMX_CSR_DB_TYPE_RSL, 64, 1012, 2, 917},
|
|
{"cvmx_l2d_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1013, 7, 919},
|
|
{"cvmx_l2d_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1014, 4, 926},
|
|
{"cvmx_l2d_fsyn0" , CVMX_CSR_DB_TYPE_RSL, 64, 1015, 3, 930},
|
|
{"cvmx_l2d_fsyn1" , CVMX_CSR_DB_TYPE_RSL, 64, 1016, 3, 933},
|
|
{"cvmx_l2d_fus0" , CVMX_CSR_DB_TYPE_RSL, 64, 1017, 2, 936},
|
|
{"cvmx_l2d_fus1" , CVMX_CSR_DB_TYPE_RSL, 64, 1018, 2, 938},
|
|
{"cvmx_l2d_fus2" , CVMX_CSR_DB_TYPE_RSL, 64, 1019, 2, 940},
|
|
{"cvmx_l2d_fus3" , CVMX_CSR_DB_TYPE_RSL, 64, 1020, 4, 942},
|
|
{"cvmx_l2t_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1021, 13, 946},
|
|
{"cvmx_led_blink" , CVMX_CSR_DB_TYPE_RSL, 64, 1022, 2, 959},
|
|
{"cvmx_led_clk_phase" , CVMX_CSR_DB_TYPE_RSL, 64, 1023, 2, 961},
|
|
{"cvmx_led_cylon" , CVMX_CSR_DB_TYPE_RSL, 64, 1024, 2, 963},
|
|
{"cvmx_led_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1025, 2, 965},
|
|
{"cvmx_led_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1026, 2, 967},
|
|
{"cvmx_led_polarity" , CVMX_CSR_DB_TYPE_RSL, 64, 1027, 2, 969},
|
|
{"cvmx_led_prt" , CVMX_CSR_DB_TYPE_RSL, 64, 1028, 2, 971},
|
|
{"cvmx_led_prt_fmt" , CVMX_CSR_DB_TYPE_RSL, 64, 1029, 2, 973},
|
|
{"cvmx_led_prt_status#" , CVMX_CSR_DB_TYPE_RSL, 64, 1030, 2, 975},
|
|
{"cvmx_led_udd_cnt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1038, 2, 977},
|
|
{"cvmx_led_udd_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 1040, 2, 979},
|
|
{"cvmx_led_udd_dat_clr#" , CVMX_CSR_DB_TYPE_RSL, 64, 1042, 2, 981},
|
|
{"cvmx_led_udd_dat_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 1044, 2, 983},
|
|
{"cvmx_lmc#_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1046, 9, 985},
|
|
{"cvmx_lmc#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1047, 19, 994},
|
|
{"cvmx_lmc#_dclk_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1048, 2, 1013},
|
|
{"cvmx_lmc#_dclk_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1049, 2, 1015},
|
|
{"cvmx_lmc#_ddr2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1050, 18, 1017},
|
|
{"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 1051, 5, 1035},
|
|
{"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1052, 6, 1040},
|
|
{"cvmx_lmc#_ifb_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1053, 2, 1046},
|
|
{"cvmx_lmc#_ifb_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1054, 2, 1048},
|
|
{"cvmx_lmc#_mem_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 1055, 14, 1050},
|
|
{"cvmx_lmc#_mem_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 1056, 9, 1064},
|
|
{"cvmx_lmc#_ops_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1057, 2, 1073},
|
|
{"cvmx_lmc#_ops_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1058, 2, 1075},
|
|
{"cvmx_lmc#_pll_bwctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1059, 3, 1077},
|
|
{"cvmx_lmc#_rodt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1060, 9, 1080},
|
|
{"cvmx_lmc#_wodt_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 1061, 9, 1089},
|
|
{"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 1062, 4, 1098},
|
|
{"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1063, 3, 1102},
|
|
{"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1064, 3, 1105},
|
|
{"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1065, 3, 1108},
|
|
{"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1066, 5, 1111},
|
|
{"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1068, 1, 1116},
|
|
{"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1069, 6, 1117},
|
|
{"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 1077, 13, 1123},
|
|
{"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1085, 4, 1136},
|
|
{"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 1086, 2, 1140},
|
|
{"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 1087, 2, 1142},
|
|
{"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 1088, 8, 1144},
|
|
{"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 1089, 7, 1152},
|
|
{"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 1090, 2, 1159},
|
|
{"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1091, 8, 1161},
|
|
{"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1092, 2, 1169},
|
|
{"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1093, 8, 1171},
|
|
{"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 1094, 12, 1179},
|
|
{"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 1095, 3, 1191},
|
|
{"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 1096, 3, 1194},
|
|
{"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 1097, 2, 1197},
|
|
{"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 1099, 2, 1199},
|
|
{"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 1101, 2, 1201},
|
|
{"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1103, 7, 1203},
|
|
{"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 1105, 2, 1210},
|
|
{"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 1107, 7, 1212},
|
|
{"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 1109, 4, 1219},
|
|
{"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1111, 8, 1223},
|
|
{"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 1113, 9, 1231},
|
|
{"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1115, 7, 1240},
|
|
{"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 1117, 9, 1247},
|
|
{"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 1119, 2, 1256},
|
|
{"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1121, 2, 1258},
|
|
{"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 1123, 4, 1260},
|
|
{"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1125, 2, 1264},
|
|
{"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 1127, 2, 1266},
|
|
{"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 1129, 2, 1268},
|
|
{"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 1131, 4, 1270},
|
|
{"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 1133, 2, 1274},
|
|
{"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 1135, 2, 1276},
|
|
{"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 1137, 2, 1278},
|
|
{"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1139, 2, 1280},
|
|
{"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 1141, 2, 1282},
|
|
{"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1143, 2, 1284},
|
|
{"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 1145, 6, 1286},
|
|
{"cvmx_npi_base_addr_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 1147, 2, 1292},
|
|
{"cvmx_npi_base_addr_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1151, 2, 1294},
|
|
{"cvmx_npi_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1155, 21, 1296},
|
|
{"cvmx_npi_buff_size_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1156, 3, 1317},
|
|
{"cvmx_npi_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1160, 21, 1320},
|
|
{"cvmx_npi_dbg_select" , CVMX_CSR_DB_TYPE_NCB, 64, 1161, 2, 1341},
|
|
{"cvmx_npi_dma_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1162, 13, 1343},
|
|
{"cvmx_npi_dma_highp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 1163, 3, 1356},
|
|
{"cvmx_npi_dma_highp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1164, 3, 1359},
|
|
{"cvmx_npi_dma_lowp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 1165, 3, 1362},
|
|
{"cvmx_npi_dma_lowp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1166, 3, 1365},
|
|
{"cvmx_npi_highp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 1167, 2, 1368},
|
|
{"cvmx_npi_highp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1168, 2, 1370},
|
|
{"cvmx_npi_input_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1169, 9, 1372},
|
|
{"cvmx_npi_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 1170, 43, 1381},
|
|
{"cvmx_npi_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 1171, 43, 1424},
|
|
{"cvmx_npi_lowp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 1172, 2, 1467},
|
|
{"cvmx_npi_lowp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1173, 2, 1469},
|
|
{"cvmx_npi_mem_access_subid#" , CVMX_CSR_DB_TYPE_NCB, 64, 1174, 8, 1471},
|
|
{"cvmx_npi_msi_rcv" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1178, 1, 1479},
|
|
{"cvmx_npi_num_desc_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1179, 2, 1480},
|
|
{"cvmx_npi_output_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1183, 38, 1482},
|
|
{"cvmx_npi_p#_dbpair_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 1184, 3, 1520},
|
|
{"cvmx_npi_p#_instr_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 1188, 2, 1523},
|
|
{"cvmx_npi_p#_instr_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 1192, 3, 1525},
|
|
{"cvmx_npi_p#_pair_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 1196, 3, 1528},
|
|
{"cvmx_npi_pci_burst_size" , CVMX_CSR_DB_TYPE_NCB, 64, 1200, 3, 1531},
|
|
{"cvmx_npi_pci_int_arb_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 1201, 4, 1534},
|
|
{"cvmx_npi_pci_read_cmd" , CVMX_CSR_DB_TYPE_NCB, 64, 1202, 2, 1538},
|
|
{"cvmx_npi_port32_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1203, 13, 1540},
|
|
{"cvmx_npi_port33_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1204, 13, 1553},
|
|
{"cvmx_npi_port34_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1205, 13, 1566},
|
|
{"cvmx_npi_port35_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1206, 13, 1579},
|
|
{"cvmx_npi_port_bp_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1207, 3, 1592},
|
|
{"cvmx_npi_rsl_int_blocks" , CVMX_CSR_DB_TYPE_NCB, 64, 1208, 33, 1595},
|
|
{"cvmx_npi_size_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 1209, 2, 1628},
|
|
{"cvmx_npi_win_read_to" , CVMX_CSR_DB_TYPE_NCB, 64, 1213, 2, 1630},
|
|
{"cvmx_pci_bar1_index#" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1214, 5, 1632},
|
|
{"cvmx_pci_cfg00" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1246, 2, 1637},
|
|
{"cvmx_pci_cfg01" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1247, 24, 1639},
|
|
{"cvmx_pci_cfg02" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1248, 2, 1663},
|
|
{"cvmx_pci_cfg03" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1249, 7, 1665},
|
|
{"cvmx_pci_cfg04" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1250, 5, 1672},
|
|
{"cvmx_pci_cfg05" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1251, 1, 1677},
|
|
{"cvmx_pci_cfg06" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1252, 5, 1678},
|
|
{"cvmx_pci_cfg07" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1253, 1, 1683},
|
|
{"cvmx_pci_cfg08" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1254, 4, 1684},
|
|
{"cvmx_pci_cfg09" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1255, 2, 1688},
|
|
{"cvmx_pci_cfg10" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1256, 1, 1690},
|
|
{"cvmx_pci_cfg11" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1257, 2, 1691},
|
|
{"cvmx_pci_cfg12" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1258, 4, 1693},
|
|
{"cvmx_pci_cfg13" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1259, 2, 1697},
|
|
{"cvmx_pci_cfg15" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1260, 4, 1699},
|
|
{"cvmx_pci_cfg16" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1261, 16, 1703},
|
|
{"cvmx_pci_cfg17" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1262, 1, 1719},
|
|
{"cvmx_pci_cfg18" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1263, 1, 1720},
|
|
{"cvmx_pci_cfg19" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1264, 18, 1721},
|
|
{"cvmx_pci_cfg20" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1265, 1, 1739},
|
|
{"cvmx_pci_cfg21" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1266, 1, 1740},
|
|
{"cvmx_pci_cfg22" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1267, 7, 1741},
|
|
{"cvmx_pci_cfg56" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1268, 7, 1748},
|
|
{"cvmx_pci_cfg57" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1269, 13, 1755},
|
|
{"cvmx_pci_cfg58" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1270, 10, 1768},
|
|
{"cvmx_pci_cfg59" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1271, 10, 1778},
|
|
{"cvmx_pci_cfg60" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1272, 7, 1788},
|
|
{"cvmx_pci_cfg61" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1273, 2, 1795},
|
|
{"cvmx_pci_cfg62" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1274, 1, 1797},
|
|
{"cvmx_pci_cfg63" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1275, 2, 1798},
|
|
{"cvmx_pci_ctl_status_2" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1276, 16, 1800},
|
|
{"cvmx_pci_dbell#" , CVMX_CSR_DB_TYPE_PCI, 32, 1277, 2, 1816},
|
|
{"cvmx_pci_dma_cnt#" , CVMX_CSR_DB_TYPE_PCI, 32, 1281, 1, 1818},
|
|
{"cvmx_pci_dma_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 1283, 1, 1819},
|
|
{"cvmx_pci_dma_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 1285, 1, 1820},
|
|
{"cvmx_pci_instr_count#" , CVMX_CSR_DB_TYPE_PCI, 32, 1287, 1, 1821},
|
|
{"cvmx_pci_int_enb" , CVMX_CSR_DB_TYPE_PCI, 64, 1291, 35, 1822},
|
|
{"cvmx_pci_int_enb2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1292, 35, 1857},
|
|
{"cvmx_pci_int_sum" , CVMX_CSR_DB_TYPE_PCI, 64, 1293, 35, 1892},
|
|
{"cvmx_pci_int_sum2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1294, 35, 1927},
|
|
{"cvmx_pci_msi_rcv" , CVMX_CSR_DB_TYPE_PCI, 32, 1295, 2, 1962},
|
|
{"cvmx_pci_pkt_credits#" , CVMX_CSR_DB_TYPE_PCI, 32, 1296, 2, 1964},
|
|
{"cvmx_pci_pkts_sent#" , CVMX_CSR_DB_TYPE_PCI, 32, 1300, 1, 1966},
|
|
{"cvmx_pci_pkts_sent_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 1304, 1, 1967},
|
|
{"cvmx_pci_pkts_sent_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 1308, 1, 1968},
|
|
{"cvmx_pci_read_cmd_6" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1312, 3, 1969},
|
|
{"cvmx_pci_read_cmd_c" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1313, 3, 1972},
|
|
{"cvmx_pci_read_cmd_e" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1314, 3, 1975},
|
|
{"cvmx_pci_read_timeout" , CVMX_CSR_DB_TYPE_NCB, 64, 1315, 3, 1978},
|
|
{"cvmx_pci_scm_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1316, 2, 1981},
|
|
{"cvmx_pci_tsr_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1317, 2, 1983},
|
|
{"cvmx_pci_win_rd_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 1318, 4, 1985},
|
|
{"cvmx_pci_win_rd_data" , CVMX_CSR_DB_TYPE_PCI, 64, 1319, 1, 1989},
|
|
{"cvmx_pci_win_wr_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 1320, 4, 1990},
|
|
{"cvmx_pci_win_wr_data" , CVMX_CSR_DB_TYPE_PCI, 64, 1321, 1, 1994},
|
|
{"cvmx_pci_win_wr_mask" , CVMX_CSR_DB_TYPE_PCI, 64, 1322, 2, 1995},
|
|
{"cvmx_pip_bck_prs" , CVMX_CSR_DB_TYPE_RSL, 64, 1323, 5, 1997},
|
|
{"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1324, 2, 2002},
|
|
{"cvmx_pip_crc_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 1325, 3, 2004},
|
|
{"cvmx_pip_crc_iv#" , CVMX_CSR_DB_TYPE_RSL, 64, 1327, 2, 2007},
|
|
{"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 1329, 4, 2009},
|
|
{"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1333, 8, 2013},
|
|
{"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1334, 16, 2021},
|
|
{"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1335, 10, 2037},
|
|
{"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1336, 10, 2047},
|
|
{"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 1337, 2, 2057},
|
|
{"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1338, 18, 2059},
|
|
{"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 1374, 25, 2077},
|
|
{"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 1410, 2, 2102},
|
|
{"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 1474, 2, 2104},
|
|
{"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 1482, 9, 2106},
|
|
{"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 1486, 2, 2115},
|
|
{"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1487, 2, 2117},
|
|
{"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1523, 2, 2119},
|
|
{"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1559, 2, 2121},
|
|
{"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1595, 2, 2123},
|
|
{"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1631, 2, 2125},
|
|
{"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1667, 2, 2127},
|
|
{"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1703, 2, 2129},
|
|
{"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1739, 2, 2131},
|
|
{"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1775, 2, 2133},
|
|
{"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1811, 2, 2135},
|
|
{"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1847, 2, 2137},
|
|
{"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 1848, 2, 2139},
|
|
{"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 1884, 2, 2141},
|
|
{"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 1920, 2, 2143},
|
|
{"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 1956, 2, 2145},
|
|
{"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2020, 2, 2147},
|
|
{"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 2021, 3, 2149},
|
|
{"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 2022, 3, 2152},
|
|
{"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 2023, 2, 2155},
|
|
{"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 2024, 2, 2157},
|
|
{"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2025, 4, 2159},
|
|
{"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2026, 5, 2163},
|
|
{"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 2027, 4, 2168},
|
|
{"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 2028, 5, 2172},
|
|
{"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 2029, 1, 2177},
|
|
{"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 2030, 4, 2178},
|
|
{"cvmx_pko_mem_debug14" , CVMX_CSR_DB_TYPE_RSL, 64, 2031, 2, 2182},
|
|
{"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2032, 5, 2184},
|
|
{"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2033, 5, 2189},
|
|
{"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 2034, 1, 2194},
|
|
{"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 2035, 19, 2195},
|
|
{"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 2036, 7, 2214},
|
|
{"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 2037, 4, 2221},
|
|
{"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 2038, 6, 2225},
|
|
{"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 2039, 7, 2231},
|
|
{"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 2040, 9, 2238},
|
|
{"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 2041, 5, 2247},
|
|
{"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2042, 13, 2252},
|
|
{"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2043, 4, 2265},
|
|
{"cvmx_pko_reg_crc_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 2044, 3, 2269},
|
|
{"cvmx_pko_reg_crc_enable" , CVMX_CSR_DB_TYPE_RSL, 64, 2046, 2, 2272},
|
|
{"cvmx_pko_reg_crc_iv#" , CVMX_CSR_DB_TYPE_RSL, 64, 2047, 2, 2274},
|
|
{"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2049, 2, 2276},
|
|
{"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2050, 3, 2278},
|
|
{"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2051, 5, 2281},
|
|
{"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2052, 3, 2286},
|
|
{"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2053, 3, 2289},
|
|
{"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2054, 2, 2292},
|
|
{"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2055, 3, 2294},
|
|
{"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 2056, 13, 2297},
|
|
{"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2057, 2, 2310},
|
|
{"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 2058, 9, 2312},
|
|
{"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 2059, 3, 2321},
|
|
{"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2060, 2, 2324},
|
|
{"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2068, 2, 2326},
|
|
{"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2069, 2, 2328},
|
|
{"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 2070, 2, 2330},
|
|
{"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 2071, 2, 2332},
|
|
{"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 2087, 5, 2334},
|
|
{"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2095, 8, 2339},
|
|
{"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2103, 2, 2347},
|
|
{"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2104, 2, 2349},
|
|
{"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2105, 2, 2351},
|
|
{"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 2113, 3, 2353},
|
|
{"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2114, 4, 2356},
|
|
{"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2130, 5, 2360},
|
|
{"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2131, 7, 2365},
|
|
{"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2147, 2, 2372},
|
|
{"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2163, 3, 2374},
|
|
{"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2164, 5, 2377},
|
|
{"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 2165, 8, 2382},
|
|
{"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2166, 6, 2390},
|
|
{"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2167, 2, 2396},
|
|
{"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2168, 4, 2398},
|
|
{"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2169, 4, 2402},
|
|
{"cvmx_spx#_bckprs_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2170, 2, 2406},
|
|
{"cvmx_spx#_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2172, 4, 2408},
|
|
{"cvmx_spx#_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2174, 11, 2412},
|
|
{"cvmx_spx#_clk_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2176, 9, 2423},
|
|
{"cvmx_spx#_dbg_deskew_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2178, 16, 2432},
|
|
{"cvmx_spx#_dbg_deskew_state" , CVMX_CSR_DB_TYPE_RSL, 64, 2180, 5, 2448},
|
|
{"cvmx_spx#_drv_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2182, 4, 2453},
|
|
{"cvmx_spx#_err_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2184, 6, 2457},
|
|
{"cvmx_spx#_int_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2186, 6, 2463},
|
|
{"cvmx_spx#_int_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2188, 12, 2469},
|
|
{"cvmx_spx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2190, 14, 2481},
|
|
{"cvmx_spx#_int_sync" , CVMX_CSR_DB_TYPE_RSL, 64, 2192, 12, 2495},
|
|
{"cvmx_spx#_tpa_acc" , CVMX_CSR_DB_TYPE_RSL, 64, 2194, 2, 2507},
|
|
{"cvmx_spx#_tpa_max" , CVMX_CSR_DB_TYPE_RSL, 64, 2196, 2, 2509},
|
|
{"cvmx_spx#_tpa_sel" , CVMX_CSR_DB_TYPE_RSL, 64, 2198, 2, 2511},
|
|
{"cvmx_spx#_trn4_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2200, 8, 2513},
|
|
{"cvmx_spx0_pll_bw_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2202, 2, 2521},
|
|
{"cvmx_spx0_pll_setting" , CVMX_CSR_DB_TYPE_RSL, 64, 2203, 2, 2523},
|
|
{"cvmx_srx#_com_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2204, 5, 2525},
|
|
{"cvmx_srx#_ign_rx_full" , CVMX_CSR_DB_TYPE_RSL, 64, 2206, 2, 2530},
|
|
{"cvmx_srx#_spi4_cal#" , CVMX_CSR_DB_TYPE_RSL, 64, 2208, 6, 2532},
|
|
{"cvmx_srx#_spi4_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2272, 4, 2538},
|
|
{"cvmx_stx#_arb_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2274, 5, 2542},
|
|
{"cvmx_stx#_bckprs_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2276, 2, 2547},
|
|
{"cvmx_stx#_com_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2278, 4, 2549},
|
|
{"cvmx_stx#_dip_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2280, 3, 2553},
|
|
{"cvmx_stx#_ign_cal" , CVMX_CSR_DB_TYPE_RSL, 64, 2282, 2, 2556},
|
|
{"cvmx_stx#_int_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2284, 9, 2558},
|
|
{"cvmx_stx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2286, 10, 2567},
|
|
{"cvmx_stx#_int_sync" , CVMX_CSR_DB_TYPE_RSL, 64, 2288, 9, 2577},
|
|
{"cvmx_stx#_min_bst" , CVMX_CSR_DB_TYPE_RSL, 64, 2290, 2, 2586},
|
|
{"cvmx_stx#_spi4_cal#" , CVMX_CSR_DB_TYPE_RSL, 64, 2292, 6, 2588},
|
|
{"cvmx_stx#_spi4_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2356, 3, 2594},
|
|
{"cvmx_stx#_spi4_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2358, 4, 2597},
|
|
{"cvmx_stx#_stat_bytes_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 2360, 2, 2601},
|
|
{"cvmx_stx#_stat_bytes_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 2362, 2, 2603},
|
|
{"cvmx_stx#_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2364, 3, 2605},
|
|
{"cvmx_stx#_stat_pkt_xmt" , CVMX_CSR_DB_TYPE_RSL, 64, 2366, 2, 2608},
|
|
{"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2368, 6, 2610},
|
|
{"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2369, 3, 2616},
|
|
{"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2370, 5, 2619},
|
|
{"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 2371, 4, 2624},
|
|
{"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 2372, 6, 2628},
|
|
{"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2373, 4, 2634},
|
|
{"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2374, 2, 2638},
|
|
{"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2375, 4, 2640},
|
|
{"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2376, 2, 2644},
|
|
{"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2377, 3, 2646},
|
|
{"cvmx_tra_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2378, 4, 2649},
|
|
{"cvmx_tra_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2379, 12, 2653},
|
|
{"cvmx_tra_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 2380, 3, 2665},
|
|
{"cvmx_tra_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2381, 2, 2668},
|
|
{"cvmx_tra_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2382, 2, 2670},
|
|
{"cvmx_tra_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2383, 17, 2672},
|
|
{"cvmx_tra_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2384, 12, 2689},
|
|
{"cvmx_tra_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2385, 6, 2701},
|
|
{"cvmx_tra_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2386, 5, 2707},
|
|
{"cvmx_tra_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2387, 1, 2712},
|
|
{"cvmx_tra_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2388, 2, 2713},
|
|
{"cvmx_tra_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2389, 2, 2715},
|
|
{"cvmx_tra_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2390, 17, 2717},
|
|
{"cvmx_tra_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2391, 12, 2734},
|
|
{"cvmx_tra_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2392, 6, 2746},
|
|
{"cvmx_tra_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2393, 2, 2752},
|
|
{"cvmx_tra_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2394, 2, 2754},
|
|
{"cvmx_tra_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2395, 17, 2756},
|
|
{"cvmx_tra_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2396, 12, 2773},
|
|
{"cvmx_tra_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2397, 6, 2785},
|
|
{"cvmx_zip_cmd_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2398, 3, 2791},
|
|
{"cvmx_zip_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2399, 5, 2794},
|
|
{"cvmx_zip_cmd_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2400, 3, 2799},
|
|
{"cvmx_zip_constants" , CVMX_CSR_DB_TYPE_RSL, 64, 2401, 6, 2802},
|
|
{"cvmx_zip_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2402, 2, 2808},
|
|
{"cvmx_zip_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2403, 2, 2810},
|
|
{"cvmx_zip_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2404, 2, 2812},
|
|
{NULL,0,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
|
|
/* name , --------------address, ---------------type, bits, csr offset */
|
|
{"ASX0_INT_EN" , 0x11800B0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
|
|
{"ASX1_INT_EN" , 0x11800B8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
|
|
{"ASX0_INT_REG" , 0x11800B0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
|
|
{"ASX1_INT_REG" , 0x11800B8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
|
|
{"ASX0_PRT_LOOP" , 0x11800B0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
|
|
{"ASX1_PRT_LOOP" , 0x11800B8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
|
|
{"ASX0_RLD_BYPASS" , 0x11800B0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
|
|
{"ASX1_RLD_BYPASS" , 0x11800B8000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
|
|
{"ASX0_RLD_BYPASS_SETTING" , 0x11800B0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
|
|
{"ASX1_RLD_BYPASS_SETTING" , 0x11800B8000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
|
|
{"ASX0_RLD_COMP" , 0x11800B0000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
|
|
{"ASX1_RLD_COMP" , 0x11800B8000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
|
|
{"ASX0_RLD_DATA_DRV" , 0x11800B0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
|
|
{"ASX1_RLD_DATA_DRV" , 0x11800B8000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
|
|
{"ASX0_RLD_FCRAM_MODE" , 0x11800B0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
|
|
{"ASX1_RLD_FCRAM_MODE" , 0x11800B8000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
|
|
{"ASX0_RLD_NCTL_STRONG" , 0x11800B0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
|
|
{"ASX1_RLD_NCTL_STRONG" , 0x11800B8000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
|
|
{"ASX0_RLD_NCTL_WEAK" , 0x11800B0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
|
|
{"ASX1_RLD_NCTL_WEAK" , 0x11800B8000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
|
|
{"ASX0_RLD_PCTL_STRONG" , 0x11800B0000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
|
|
{"ASX1_RLD_PCTL_STRONG" , 0x11800B8000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
|
|
{"ASX0_RLD_PCTL_WEAK" , 0x11800B0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
|
|
{"ASX1_RLD_PCTL_WEAK" , 0x11800B8000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
|
|
{"ASX0_RLD_SETTING" , 0x11800B0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"ASX1_RLD_SETTING" , 0x11800B8000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"ASX0_RX_CLK_SET000" , 0x11800B0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"ASX0_RX_CLK_SET001" , 0x11800B0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"ASX0_RX_CLK_SET002" , 0x11800B0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"ASX0_RX_CLK_SET003" , 0x11800B0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"ASX1_RX_CLK_SET000" , 0x11800B8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"ASX1_RX_CLK_SET001" , 0x11800B8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"ASX1_RX_CLK_SET002" , 0x11800B8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"ASX1_RX_CLK_SET003" , 0x11800B8000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"ASX0_RX_PRT_EN" , 0x11800B0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"ASX1_RX_PRT_EN" , 0x11800B8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"ASX0_RX_WOL" , 0x11800B0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
|
|
{"ASX1_RX_WOL" , 0x11800B8000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
|
|
{"ASX0_RX_WOL_MSK" , 0x11800B0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"ASX1_RX_WOL_MSK" , 0x11800B8000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"ASX0_RX_WOL_POWOK" , 0x11800B0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
|
|
{"ASX1_RX_WOL_POWOK" , 0x11800B8000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
|
|
{"ASX0_RX_WOL_SIG" , 0x11800B0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
|
|
{"ASX1_RX_WOL_SIG" , 0x11800B8000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
|
|
{"ASX0_TX_CLK_SET000" , 0x11800B0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
|
|
{"ASX0_TX_CLK_SET001" , 0x11800B0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
|
|
{"ASX0_TX_CLK_SET002" , 0x11800B0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
|
|
{"ASX0_TX_CLK_SET003" , 0x11800B0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
|
|
{"ASX1_TX_CLK_SET000" , 0x11800B8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
|
|
{"ASX1_TX_CLK_SET001" , 0x11800B8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
|
|
{"ASX1_TX_CLK_SET002" , 0x11800B8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
|
|
{"ASX1_TX_CLK_SET003" , 0x11800B8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
|
|
{"ASX0_TX_COMP_BYP" , 0x11800B0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
|
|
{"ASX1_TX_COMP_BYP" , 0x11800B8000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
|
|
{"ASX0_TX_HI_WATER000" , 0x11800B0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
|
|
{"ASX0_TX_HI_WATER001" , 0x11800B0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
|
|
{"ASX0_TX_HI_WATER002" , 0x11800B0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
|
|
{"ASX0_TX_HI_WATER003" , 0x11800B0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
|
|
{"ASX1_TX_HI_WATER000" , 0x11800B8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
|
|
{"ASX1_TX_HI_WATER001" , 0x11800B8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
|
|
{"ASX1_TX_HI_WATER002" , 0x11800B8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
|
|
{"ASX1_TX_HI_WATER003" , 0x11800B8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
|
|
{"ASX0_TX_PRT_EN" , 0x11800B0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
|
|
{"ASX1_TX_PRT_EN" , 0x11800B8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
|
|
{"ASX0_DBG_DATA_DRV" , 0x11800B0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
|
|
{"ASX0_DBG_DATA_ENABLE" , 0x11800B0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
|
|
{"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT4_EN0" , 0x1070000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT5_EN0" , 0x1070000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT6_EN0" , 0x1070000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT7_EN0" , 0x1070000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT8_EN0" , 0x1070000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT9_EN0" , 0x1070000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT10_EN0" , 0x10700000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT11_EN0" , 0x10700000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT12_EN0" , 0x10700000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT13_EN0" , 0x10700000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT14_EN0" , 0x10700000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT15_EN0" , 0x10700000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT16_EN0" , 0x1070000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT17_EN0" , 0x1070000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT18_EN0" , 0x1070000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT19_EN0" , 0x1070000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT20_EN0" , 0x1070000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT21_EN0" , 0x1070000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT22_EN0" , 0x1070000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT23_EN0" , 0x1070000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT24_EN0" , 0x1070000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT25_EN0" , 0x1070000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT26_EN0" , 0x10700000003A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT27_EN0" , 0x10700000003B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT28_EN0" , 0x10700000003C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT29_EN0" , 0x10700000003D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT30_EN0" , 0x10700000003E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT31_EN0" , 0x10700000003F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT4_EN1" , 0x1070000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT5_EN1" , 0x1070000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT6_EN1" , 0x1070000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT7_EN1" , 0x1070000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT8_EN1" , 0x1070000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT9_EN1" , 0x1070000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT10_EN1" , 0x10700000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT11_EN1" , 0x10700000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT12_EN1" , 0x10700000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT13_EN1" , 0x10700000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT14_EN1" , 0x10700000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT15_EN1" , 0x10700000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT16_EN1" , 0x1070000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT17_EN1" , 0x1070000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT18_EN1" , 0x1070000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT19_EN1" , 0x1070000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT20_EN1" , 0x1070000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT21_EN1" , 0x1070000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT22_EN1" , 0x1070000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT23_EN1" , 0x1070000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT24_EN1" , 0x1070000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT25_EN1" , 0x1070000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT26_EN1" , 0x10700000003A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT27_EN1" , 0x10700000003B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT28_EN1" , 0x10700000003C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT29_EN1" , 0x10700000003D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT30_EN1" , 0x10700000003E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT31_EN1" , 0x10700000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT4_SUM0" , 0x1070000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT5_SUM0" , 0x1070000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT6_SUM0" , 0x1070000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT7_SUM0" , 0x1070000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT8_SUM0" , 0x1070000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT9_SUM0" , 0x1070000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT10_SUM0" , 0x1070000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT11_SUM0" , 0x1070000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT12_SUM0" , 0x1070000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT13_SUM0" , 0x1070000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT14_SUM0" , 0x1070000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT15_SUM0" , 0x1070000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT16_SUM0" , 0x1070000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT17_SUM0" , 0x1070000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT18_SUM0" , 0x1070000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT19_SUM0" , 0x1070000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT20_SUM0" , 0x10700000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT21_SUM0" , 0x10700000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT22_SUM0" , 0x10700000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT23_SUM0" , 0x10700000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT24_SUM0" , 0x10700000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT25_SUM0" , 0x10700000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT26_SUM0" , 0x10700000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT27_SUM0" , 0x10700000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT28_SUM0" , 0x10700000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT29_SUM0" , 0x10700000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT30_SUM0" , 0x10700000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT31_SUM0" , 0x10700000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR2" , 0x1070000000690ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR3" , 0x1070000000698ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR4" , 0x10700000006A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR5" , 0x10700000006A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR6" , 0x10700000006B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR7" , 0x10700000006B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR8" , 0x10700000006C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR9" , 0x10700000006C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR10" , 0x10700000006D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR11" , 0x10700000006D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR12" , 0x10700000006E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR13" , 0x10700000006E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR14" , 0x10700000006F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR15" , 0x10700000006F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET2" , 0x1070000000610ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET3" , 0x1070000000618ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET4" , 0x1070000000620ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET5" , 0x1070000000628ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET6" , 0x1070000000630ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET7" , 0x1070000000638ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET8" , 0x1070000000640ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET9" , 0x1070000000648ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET10" , 0x1070000000650ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET11" , 0x1070000000658ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET12" , 0x1070000000660ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET13" , 0x1070000000668ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET14" , 0x1070000000670ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET15" , 0x1070000000678ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
|
|
{"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
|
|
{"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE2" , 0x1070000000590ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE3" , 0x1070000000598ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE4" , 0x10700000005A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE5" , 0x10700000005A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE6" , 0x10700000005B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE7" , 0x10700000005B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE8" , 0x10700000005C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE9" , 0x10700000005C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE10" , 0x10700000005D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE11" , 0x10700000005D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE12" , 0x10700000005E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE13" , 0x10700000005E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE14" , 0x10700000005F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE15" , 0x10700000005F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
|
|
{"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
|
|
{"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 41},
|
|
{"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
|
|
{"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
|
|
{"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
|
|
{"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
|
|
{"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
|
|
{"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG2" , 0x1070000000510ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG3" , 0x1070000000518ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG4" , 0x1070000000520ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG5" , 0x1070000000528ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG6" , 0x1070000000530ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG7" , 0x1070000000538ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG8" , 0x1070000000540ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG9" , 0x1070000000548ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG10" , 0x1070000000550ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG11" , 0x1070000000558ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG12" , 0x1070000000560ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG13" , 0x1070000000568ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG14" , 0x1070000000570ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG15" , 0x1070000000578ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"DBG_DATA" , 0x11F00000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 45},
|
|
{"DFA_BST0" , 0x11800300007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
|
|
{"DFA_BST1" , 0x11800300007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
|
|
{"DFA_CFG" , 0x1180030000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
|
|
{"DFA_DBELL" , 0x1370000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 49},
|
|
{"DFA_DIFCTL" , 0x1370600000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
|
|
{"DFA_DIFRDPTR" , 0x1370200000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 51},
|
|
{"DFA_ERR" , 0x1180030000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
|
|
{"DFA_MEMCFG0" , 0x1180030000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
|
|
{"DFA_MEMCFG1" , 0x1180030000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
|
|
{"DFA_MEMCFG2" , 0x1180030000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
|
|
{"DFA_MEMFADR" , 0x1180030000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
|
|
{"DFA_MEMFCR" , 0x1180030000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
|
|
{"DFA_MEMRLD" , 0x1180030000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
|
|
{"DFA_NCBCTL" , 0x1180030000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
|
|
{"DFA_SBD_DBG0" , 0x1180030000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
|
|
{"DFA_SBD_DBG1" , 0x1180030000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
|
|
{"DFA_SBD_DBG2" , 0x1180030000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
|
|
{"DFA_SBD_DBG3" , 0x1180030000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
|
|
{"FPA_BIST_STATUS" , 0x11800280000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
|
|
{"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
|
|
{"FPA_FPF1_MARKS" , 0x1180028000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"FPA_FPF2_MARKS" , 0x1180028000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"FPA_FPF3_MARKS" , 0x1180028000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"FPA_FPF4_MARKS" , 0x1180028000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"FPA_FPF5_MARKS" , 0x1180028000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"FPA_FPF6_MARKS" , 0x1180028000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"FPA_FPF7_MARKS" , 0x1180028000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"FPA_FPF1_SIZE" , 0x1180028000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"FPA_FPF2_SIZE" , 0x1180028000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"FPA_FPF3_SIZE" , 0x1180028000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"FPA_FPF4_SIZE" , 0x1180028000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"FPA_FPF5_SIZE" , 0x1180028000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"FPA_FPF6_SIZE" , 0x1180028000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"FPA_FPF7_SIZE" , 0x1180028000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"FPA_FPF0_MARKS" , 0x1180028000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
|
|
{"FPA_FPF0_SIZE" , 0x1180028000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
|
|
{"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
|
|
{"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
|
|
{"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_QUE1_AVAILABLE" , 0x11800280000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_QUE2_AVAILABLE" , 0x11800280000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_QUE3_AVAILABLE" , 0x11800280000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_QUE4_AVAILABLE" , 0x11800280000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_QUE5_AVAILABLE" , 0x11800280000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_QUE6_AVAILABLE" , 0x11800280000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_QUE7_AVAILABLE" , 0x11800280000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_QUE0_PAGE_INDEX" , 0x11800280000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"FPA_QUE1_PAGE_INDEX" , 0x11800280000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
|
|
{"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
|
|
{"FPA_WART_CTL" , 0x11800280000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
|
|
{"FPA_WART_STATUS" , 0x11800280000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
|
|
{"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
|
|
{"GMX1_BAD_REG" , 0x1180010000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
|
|
{"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
|
|
{"GMX1_BIST" , 0x1180010000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
|
|
{"GMX0_INF_MODE" , 0x11800080007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
|
|
{"GMX1_INF_MODE" , 0x11800100007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
|
|
{"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
|
|
{"GMX1_NXA_ADR" , 0x1180010000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
|
|
{"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX0_PRT003_CFG" , 0x1180008001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX1_PRT000_CFG" , 0x1180010000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX1_PRT001_CFG" , 0x1180010000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX1_PRT002_CFG" , 0x1180010001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX1_PRT003_CFG" , 0x1180010001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX0_RX003_ADR_CAM0" , 0x1180008001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX1_RX000_ADR_CAM0" , 0x1180010000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX1_RX001_ADR_CAM0" , 0x1180010000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX1_RX002_ADR_CAM0" , 0x1180010001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX1_RX003_ADR_CAM0" , 0x1180010001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX0_RX003_ADR_CAM1" , 0x1180008001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX1_RX000_ADR_CAM1" , 0x1180010000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX1_RX001_ADR_CAM1" , 0x1180010000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX1_RX002_ADR_CAM1" , 0x1180010001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX1_RX003_ADR_CAM1" , 0x1180010001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX0_RX003_ADR_CAM2" , 0x1180008001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX1_RX000_ADR_CAM2" , 0x1180010000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX1_RX001_ADR_CAM2" , 0x1180010000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX1_RX002_ADR_CAM2" , 0x1180010001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX1_RX003_ADR_CAM2" , 0x1180010001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX0_RX003_ADR_CAM3" , 0x1180008001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX1_RX000_ADR_CAM3" , 0x1180010000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX1_RX001_ADR_CAM3" , 0x1180010000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX1_RX002_ADR_CAM3" , 0x1180010001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX1_RX003_ADR_CAM3" , 0x1180010001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX0_RX000_ADR_CAM4" , 0x11800080001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX0_RX001_ADR_CAM4" , 0x11800080009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX0_RX002_ADR_CAM4" , 0x11800080011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX0_RX003_ADR_CAM4" , 0x11800080019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX1_RX000_ADR_CAM4" , 0x11800100001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX1_RX001_ADR_CAM4" , 0x11800100009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX1_RX002_ADR_CAM4" , 0x11800100011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX1_RX003_ADR_CAM4" , 0x11800100019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX0_RX000_ADR_CAM5" , 0x11800080001A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX0_RX001_ADR_CAM5" , 0x11800080009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX0_RX002_ADR_CAM5" , 0x11800080011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX0_RX003_ADR_CAM5" , 0x11800080019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX1_RX000_ADR_CAM5" , 0x11800100001A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX1_RX001_ADR_CAM5" , 0x11800100009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX1_RX002_ADR_CAM5" , 0x11800100011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX1_RX003_ADR_CAM5" , 0x11800100019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_RX003_ADR_CAM_EN" , 0x1180008001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX1_RX000_ADR_CAM_EN" , 0x1180010000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX1_RX001_ADR_CAM_EN" , 0x1180010000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX1_RX002_ADR_CAM_EN" , 0x1180010001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX1_RX003_ADR_CAM_EN" , 0x1180010001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_RX003_ADR_CTL" , 0x1180008001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX1_RX000_ADR_CTL" , 0x1180010000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX1_RX001_ADR_CTL" , 0x1180010000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX1_RX002_ADR_CTL" , 0x1180010001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX1_RX003_ADR_CTL" , 0x1180010001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_RX003_DECISION" , 0x1180008001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX1_RX000_DECISION" , 0x1180010000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX1_RX001_DECISION" , 0x1180010000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX1_RX002_DECISION" , 0x1180010001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX1_RX003_DECISION" , 0x1180010001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_RX003_FRM_CHK" , 0x1180008001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX1_RX000_FRM_CHK" , 0x1180010000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX1_RX001_FRM_CHK" , 0x1180010000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX1_RX002_FRM_CHK" , 0x1180010001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX1_RX003_FRM_CHK" , 0x1180010001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_RX003_FRM_CTL" , 0x1180008001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX1_RX000_FRM_CTL" , 0x1180010000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX1_RX001_FRM_CTL" , 0x1180010000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX1_RX002_FRM_CTL" , 0x1180010001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX1_RX003_FRM_CTL" , 0x1180010001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_RX000_FRM_MAX" , 0x1180008000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_RX001_FRM_MAX" , 0x1180008000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_RX002_FRM_MAX" , 0x1180008001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_RX003_FRM_MAX" , 0x1180008001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX1_RX000_FRM_MAX" , 0x1180010000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX1_RX001_FRM_MAX" , 0x1180010000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX1_RX002_FRM_MAX" , 0x1180010001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX1_RX003_FRM_MAX" , 0x1180010001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_RX000_FRM_MIN" , 0x1180008000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_RX001_FRM_MIN" , 0x1180008000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_RX002_FRM_MIN" , 0x1180008001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_RX003_FRM_MIN" , 0x1180008001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX1_RX000_FRM_MIN" , 0x1180010000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX1_RX001_FRM_MIN" , 0x1180010000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX1_RX002_FRM_MIN" , 0x1180010001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX1_RX003_FRM_MIN" , 0x1180010001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_RX003_IFG" , 0x1180008001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX1_RX000_IFG" , 0x1180010000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX1_RX001_IFG" , 0x1180010000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX1_RX002_IFG" , 0x1180010001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX1_RX003_IFG" , 0x1180010001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_RX003_INT_EN" , 0x1180008001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX1_RX000_INT_EN" , 0x1180010000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX1_RX001_INT_EN" , 0x1180010000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX1_RX002_INT_EN" , 0x1180010001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX1_RX003_INT_EN" , 0x1180010001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_RX003_INT_REG" , 0x1180008001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX1_RX000_INT_REG" , 0x1180010000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX1_RX001_INT_REG" , 0x1180010000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX1_RX002_INT_REG" , 0x1180010001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX1_RX003_INT_REG" , 0x1180010001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_RX003_JABBER" , 0x1180008001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX1_RX000_JABBER" , 0x1180010000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX1_RX001_JABBER" , 0x1180010000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX1_RX002_JABBER" , 0x1180010001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX1_RX003_JABBER" , 0x1180010001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_RX000_RX_INBND" , 0x1180008000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_RX001_RX_INBND" , 0x1180008000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_RX002_RX_INBND" , 0x1180008001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_RX003_RX_INBND" , 0x1180008001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX1_RX000_RX_INBND" , 0x1180010000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX1_RX001_RX_INBND" , 0x1180010000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX1_RX002_RX_INBND" , 0x1180010001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX1_RX003_RX_INBND" , 0x1180010001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX0_RX003_STATS_CTL" , 0x1180008001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX1_RX000_STATS_CTL" , 0x1180010000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX1_RX001_STATS_CTL" , 0x1180010000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX1_RX002_STATS_CTL" , 0x1180010001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX1_RX003_STATS_CTL" , 0x1180010001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX0_RX003_STATS_OCTS" , 0x1180008001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX1_RX000_STATS_OCTS" , 0x1180010000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX1_RX001_STATS_OCTS" , 0x1180010000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX1_RX002_STATS_OCTS" , 0x1180010001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX1_RX003_STATS_OCTS" , 0x1180010001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX0_RX003_STATS_OCTS_CTL" , 0x1180008001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX1_RX000_STATS_OCTS_CTL" , 0x1180010000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX1_RX001_STATS_OCTS_CTL" , 0x1180010000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX1_RX002_STATS_OCTS_CTL" , 0x1180010001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX1_RX003_STATS_OCTS_CTL" , 0x1180010001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_RX003_STATS_OCTS_DMAC" , 0x11800080018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX1_RX000_STATS_OCTS_DMAC" , 0x11800100000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX1_RX001_STATS_OCTS_DMAC" , 0x11800100008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX1_RX002_STATS_OCTS_DMAC" , 0x11800100010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX1_RX003_STATS_OCTS_DMAC" , 0x11800100018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX0_RX003_STATS_OCTS_DRP" , 0x11800080018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX1_RX000_STATS_OCTS_DRP" , 0x11800100000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX1_RX001_STATS_OCTS_DRP" , 0x11800100008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX1_RX002_STATS_OCTS_DRP" , 0x11800100010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX1_RX003_STATS_OCTS_DRP" , 0x11800100018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_RX003_STATS_PKTS" , 0x1180008001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX1_RX000_STATS_PKTS" , 0x1180010000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX1_RX001_STATS_PKTS" , 0x1180010000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX1_RX002_STATS_PKTS" , 0x1180010001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX1_RX003_STATS_PKTS" , 0x1180010001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_RX003_STATS_PKTS_BAD" , 0x11800080018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX1_RX000_STATS_PKTS_BAD" , 0x11800100000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX1_RX001_STATS_PKTS_BAD" , 0x11800100008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX1_RX002_STATS_PKTS_BAD" , 0x11800100010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX1_RX003_STATS_PKTS_BAD" , 0x11800100018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX0_RX003_STATS_PKTS_CTL" , 0x1180008001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX1_RX000_STATS_PKTS_CTL" , 0x1180010000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX1_RX001_STATS_PKTS_CTL" , 0x1180010000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX1_RX002_STATS_PKTS_CTL" , 0x1180010001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX1_RX003_STATS_PKTS_CTL" , 0x1180010001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_RX003_STATS_PKTS_DMAC" , 0x11800080018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX1_RX000_STATS_PKTS_DMAC" , 0x11800100000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX1_RX001_STATS_PKTS_DMAC" , 0x11800100008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX1_RX002_STATS_PKTS_DMAC" , 0x11800100010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX1_RX003_STATS_PKTS_DMAC" , 0x11800100018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX0_RX003_STATS_PKTS_DRP" , 0x11800080018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX1_RX000_STATS_PKTS_DRP" , 0x11800100000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX1_RX001_STATS_PKTS_DRP" , 0x11800100008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX1_RX002_STATS_PKTS_DRP" , 0x11800100010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX1_RX003_STATS_PKTS_DRP" , 0x11800100018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX0_RX003_UDD_SKP" , 0x1180008001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX1_RX000_UDD_SKP" , 0x1180010000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX1_RX001_UDD_SKP" , 0x1180010000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX1_RX002_UDD_SKP" , 0x1180010001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX1_RX003_UDD_SKP" , 0x1180010001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX0_RX_BP_DROP003" , 0x1180008000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX1_RX_BP_DROP000" , 0x1180010000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX1_RX_BP_DROP001" , 0x1180010000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX1_RX_BP_DROP002" , 0x1180010000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX1_RX_BP_DROP003" , 0x1180010000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX0_RX_BP_OFF003" , 0x1180008000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX1_RX_BP_OFF000" , 0x1180010000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX1_RX_BP_OFF001" , 0x1180010000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX1_RX_BP_OFF002" , 0x1180010000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX1_RX_BP_OFF003" , 0x1180010000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_RX_BP_ON003" , 0x1180008000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX1_RX_BP_ON000" , 0x1180010000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX1_RX_BP_ON001" , 0x1180010000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX1_RX_BP_ON002" , 0x1180010000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX1_RX_BP_ON003" , 0x1180010000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_RX_PASS_EN" , 0x11800080005F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX1_RX_PASS_EN" , 0x11800100005F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX0_RX_PASS_MAP000" , 0x1180008000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP001" , 0x1180008000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP002" , 0x1180008000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP003" , 0x1180008000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP004" , 0x1180008000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP005" , 0x1180008000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP006" , 0x1180008000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP007" , 0x1180008000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP008" , 0x1180008000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP009" , 0x1180008000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP010" , 0x1180008000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP011" , 0x1180008000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP012" , 0x1180008000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP013" , 0x1180008000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP014" , 0x1180008000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP015" , 0x1180008000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP000" , 0x1180010000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP001" , 0x1180010000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP002" , 0x1180010000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP003" , 0x1180010000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP004" , 0x1180010000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP005" , 0x1180010000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP006" , 0x1180010000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP007" , 0x1180010000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP008" , 0x1180010000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP009" , 0x1180010000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP010" , 0x1180010000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP011" , 0x1180010000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP012" , 0x1180010000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP013" , 0x1180010000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP014" , 0x1180010000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP015" , 0x1180010000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX1_RX_PRTS" , 0x1180010000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX0_SMAC001" , 0x1180008000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX0_SMAC003" , 0x1180008001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX1_SMAC000" , 0x1180010000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX1_SMAC001" , 0x1180010000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX1_SMAC002" , 0x1180010001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX1_SMAC003" , 0x1180010001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX1_STAT_BP" , 0x1180010000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX0_TX001_APPEND" , 0x1180008000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX0_TX003_APPEND" , 0x1180008001A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX1_TX000_APPEND" , 0x1180010000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX1_TX001_APPEND" , 0x1180010000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX1_TX002_APPEND" , 0x1180010001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX1_TX003_APPEND" , 0x1180010001A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_TX001_BURST" , 0x1180008000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_TX003_BURST" , 0x1180008001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX1_TX000_BURST" , 0x1180010000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX1_TX001_BURST" , 0x1180010000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX1_TX002_BURST" , 0x1180010001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX1_TX003_BURST" , 0x1180010001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_TX000_CLK" , 0x1180008000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_TX001_CLK" , 0x1180008000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_TX002_CLK" , 0x1180008001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_TX003_CLK" , 0x1180008001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX1_TX000_CLK" , 0x1180010000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX1_TX001_CLK" , 0x1180010000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX1_TX002_CLK" , 0x1180010001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX1_TX003_CLK" , 0x1180010001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_TX001_CTL" , 0x1180008000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_TX003_CTL" , 0x1180008001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX1_TX000_CTL" , 0x1180010000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX1_TX001_CTL" , 0x1180010000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX1_TX002_CTL" , 0x1180010001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX1_TX003_CTL" , 0x1180010001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_TX001_MIN_PKT" , 0x1180008000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_TX003_MIN_PKT" , 0x1180008001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_TX000_MIN_PKT" , 0x1180010000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_TX001_MIN_PKT" , 0x1180010000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_TX002_MIN_PKT" , 0x1180010001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_TX003_MIN_PKT" , 0x1180010001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_TX003_PAUSE_PKT_INTERVAL", 0x1180008001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX1_TX000_PAUSE_PKT_INTERVAL", 0x1180010000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX1_TX001_PAUSE_PKT_INTERVAL", 0x1180010000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX1_TX002_PAUSE_PKT_INTERVAL", 0x1180010001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX1_TX003_PAUSE_PKT_INTERVAL", 0x1180010001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_TX003_PAUSE_PKT_TIME" , 0x1180008001A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX1_TX000_PAUSE_PKT_TIME" , 0x1180010000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX1_TX001_PAUSE_PKT_TIME" , 0x1180010000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX1_TX002_PAUSE_PKT_TIME" , 0x1180010001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX1_TX003_PAUSE_PKT_TIME" , 0x1180010001A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_TX001_PAUSE_TOGO" , 0x1180008000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_TX003_PAUSE_TOGO" , 0x1180008001A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX1_TX000_PAUSE_TOGO" , 0x1180010000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX1_TX001_PAUSE_TOGO" , 0x1180010000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX1_TX002_PAUSE_TOGO" , 0x1180010001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX1_TX003_PAUSE_TOGO" , 0x1180010001A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_TX001_PAUSE_ZERO" , 0x1180008000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_TX003_PAUSE_ZERO" , 0x1180008001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX1_TX000_PAUSE_ZERO" , 0x1180010000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX1_TX001_PAUSE_ZERO" , 0x1180010000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX1_TX002_PAUSE_ZERO" , 0x1180010001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX1_TX003_PAUSE_ZERO" , 0x1180010001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_TX001_SLOT" , 0x1180008000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_TX003_SLOT" , 0x1180008001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX1_TX000_SLOT" , 0x1180010000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX1_TX001_SLOT" , 0x1180010000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX1_TX002_SLOT" , 0x1180010001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX1_TX003_SLOT" , 0x1180010001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_TX001_SOFT_PAUSE" , 0x1180008000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_TX003_SOFT_PAUSE" , 0x1180008001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX1_TX000_SOFT_PAUSE" , 0x1180010000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX1_TX001_SOFT_PAUSE" , 0x1180010000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX1_TX002_SOFT_PAUSE" , 0x1180010001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX1_TX003_SOFT_PAUSE" , 0x1180010001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_TX001_STAT0" , 0x1180008000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_TX003_STAT0" , 0x1180008001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX1_TX000_STAT0" , 0x1180010000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX1_TX001_STAT0" , 0x1180010000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX1_TX002_STAT0" , 0x1180010001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX1_TX003_STAT0" , 0x1180010001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_TX001_STAT1" , 0x1180008000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_TX003_STAT1" , 0x1180008001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX1_TX000_STAT1" , 0x1180010000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX1_TX001_STAT1" , 0x1180010000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX1_TX002_STAT1" , 0x1180010001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX1_TX003_STAT1" , 0x1180010001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_TX001_STAT2" , 0x1180008000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_TX003_STAT2" , 0x1180008001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX1_TX000_STAT2" , 0x1180010000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX1_TX001_STAT2" , 0x1180010000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX1_TX002_STAT2" , 0x1180010001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX1_TX003_STAT2" , 0x1180010001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_TX001_STAT3" , 0x1180008000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_TX003_STAT3" , 0x1180008001A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX1_TX000_STAT3" , 0x1180010000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX1_TX001_STAT3" , 0x1180010000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX1_TX002_STAT3" , 0x1180010001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX1_TX003_STAT3" , 0x1180010001A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_TX000_STAT4" , 0x11800080002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_TX001_STAT4" , 0x1180008000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_TX002_STAT4" , 0x11800080012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_TX003_STAT4" , 0x1180008001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX1_TX000_STAT4" , 0x11800100002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX1_TX001_STAT4" , 0x1180010000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX1_TX002_STAT4" , 0x11800100012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX1_TX003_STAT4" , 0x1180010001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_TX000_STAT5" , 0x11800080002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_TX001_STAT5" , 0x1180008000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_TX002_STAT5" , 0x11800080012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_TX003_STAT5" , 0x1180008001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX1_TX000_STAT5" , 0x11800100002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX1_TX001_STAT5" , 0x1180010000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX1_TX002_STAT5" , 0x11800100012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX1_TX003_STAT5" , 0x1180010001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_TX000_STAT6" , 0x11800080002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_TX001_STAT6" , 0x1180008000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_TX002_STAT6" , 0x11800080012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_TX003_STAT6" , 0x1180008001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX1_TX000_STAT6" , 0x11800100002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX1_TX001_STAT6" , 0x1180010000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX1_TX002_STAT6" , 0x11800100012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX1_TX003_STAT6" , 0x1180010001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_TX000_STAT7" , 0x11800080002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_TX001_STAT7" , 0x1180008000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_TX002_STAT7" , 0x11800080012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_TX003_STAT7" , 0x1180008001AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX1_TX000_STAT7" , 0x11800100002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX1_TX001_STAT7" , 0x1180010000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX1_TX002_STAT7" , 0x11800100012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX1_TX003_STAT7" , 0x1180010001AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_TX000_STAT8" , 0x11800080002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_TX001_STAT8" , 0x1180008000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_TX002_STAT8" , 0x11800080012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_TX003_STAT8" , 0x1180008001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX1_TX000_STAT8" , 0x11800100002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX1_TX001_STAT8" , 0x1180010000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX1_TX002_STAT8" , 0x11800100012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX1_TX003_STAT8" , 0x1180010001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_TX000_STAT9" , 0x11800080002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_TX001_STAT9" , 0x1180008000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_TX002_STAT9" , 0x11800080012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_TX003_STAT9" , 0x1180008001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX1_TX000_STAT9" , 0x11800100002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX1_TX001_STAT9" , 0x1180010000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX1_TX002_STAT9" , 0x11800100012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX1_TX003_STAT9" , 0x1180010001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_TX001_STATS_CTL" , 0x1180008000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_TX003_STATS_CTL" , 0x1180008001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX1_TX000_STATS_CTL" , 0x1180010000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX1_TX001_STATS_CTL" , 0x1180010000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX1_TX002_STATS_CTL" , 0x1180010001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX1_TX003_STATS_CTL" , 0x1180010001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_TX001_THRESH" , 0x1180008000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_TX003_THRESH" , 0x1180008001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX1_TX000_THRESH" , 0x1180010000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX1_TX001_THRESH" , 0x1180010000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX1_TX002_THRESH" , 0x1180010001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX1_TX003_THRESH" , 0x1180010001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_TX_BP" , 0x11800080004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX1_TX_BP" , 0x11800100004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX1_TX_COL_ATTEMPT" , 0x1180010000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX0_TX_CORRUPT" , 0x11800080004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX1_TX_CORRUPT" , 0x11800100004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX1_TX_IFG" , 0x1180010000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX1_TX_INT_EN" , 0x1180010000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX1_TX_INT_REG" , 0x1180010000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX1_TX_JAM" , 0x1180010000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX0_TX_LFSR" , 0x11800080004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX1_TX_LFSR" , 0x11800100004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX0_TX_OVR_BP" , 0x11800080004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX1_TX_OVR_BP" , 0x11800100004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX1_TX_PAUSE_PKT_DMAC" , 0x11800100004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX1_TX_PAUSE_PKT_TYPE" , 0x11800100004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX1_TX_PRTS" , 0x1180010000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX0_TX_SPI_CTL" , 0x11800080004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX1_TX_SPI_CTL" , 0x11800100004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX0_TX_SPI_MAX" , 0x11800080004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX1_TX_SPI_MAX" , 0x11800100004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX0_TX_SPI_THRESH" , 0x11800080004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX1_TX_SPI_THRESH" , 0x11800100004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
|
|
{"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
|
|
{"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
|
|
{"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
|
|
{"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
|
|
{"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
|
|
{"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
|
|
{"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
|
|
{"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
|
|
{"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
|
|
{"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
|
|
{"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
|
|
{"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
|
|
{"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
|
|
{"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
|
|
{"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
|
|
{"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
|
|
{"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
|
|
{"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
|
|
{"IOB_BIST_STATUS" , 0x11800F00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
|
|
{"IOB_CTL_STATUS" , 0x11800F0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
|
|
{"IOB_DWB_PRI_CNT" , 0x11800F0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"IOB_FAU_TIMEOUT" , 0x11800F0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"IOB_I2C_PRI_CNT" , 0x11800F0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"IOB_INB_CONTROL_MATCH" , 0x11800F0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
|
|
{"IOB_INB_CONTROL_MATCH_ENB" , 0x11800F0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"IOB_INB_DATA_MATCH" , 0x11800F0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"IOB_INB_DATA_MATCH_ENB" , 0x11800F0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"IOB_INT_ENB" , 0x11800F0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"IOB_INT_SUM" , 0x11800F0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"IOB_N2C_L2C_PRI_CNT" , 0x11800F0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"IOB_N2C_RSP_PRI_CNT" , 0x11800F0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"IOB_OUTB_COM_PRI_CNT" , 0x11800F0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"IOB_OUTB_CONTROL_MATCH" , 0x11800F0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
|
|
{"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800F00000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
|
|
{"IOB_OUTB_DATA_MATCH" , 0x11800F0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
|
|
{"IOB_OUTB_DATA_MATCH_ENB" , 0x11800F00000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
|
|
{"IOB_OUTB_FPA_PRI_CNT" , 0x11800F0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
|
|
{"IOB_OUTB_REQ_PRI_CNT" , 0x11800F0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
|
|
{"IOB_P2C_REQ_PRI_CNT" , 0x11800F0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
|
|
{"IOB_PKT_ERR" , 0x11800F0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
|
|
{"IPD_1ST_MBUFF_SKIP" , 0x14F0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 185},
|
|
{"IPD_1ST_NEXT_PTR_BACK" , 0x14F0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 186},
|
|
{"IPD_2ND_NEXT_PTR_BACK" , 0x14F0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 187},
|
|
{"IPD_BIST_STATUS" , 0x14F00000007F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
|
|
{"IPD_BP_PRT_RED_END" , 0x14F0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
|
|
{"IPD_CLK_COUNT" , 0x14F0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
|
|
{"IPD_CTL_STATUS" , 0x14F0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"IPD_INT_ENB" , 0x14F0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
|
|
{"IPD_INT_SUM" , 0x14F0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 193},
|
|
{"IPD_NOT_1ST_MBUFF_SKIP" , 0x14F0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 194},
|
|
{"IPD_PACKET_MBUFF_SIZE" , 0x14F0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 195},
|
|
{"IPD_PORT0_BP_PAGE_CNT" , 0x14F0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT1_BP_PAGE_CNT" , 0x14F0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT2_BP_PAGE_CNT" , 0x14F0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT3_BP_PAGE_CNT" , 0x14F0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT4_BP_PAGE_CNT" , 0x14F0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT5_BP_PAGE_CNT" , 0x14F0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT6_BP_PAGE_CNT" , 0x14F0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT7_BP_PAGE_CNT" , 0x14F0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT8_BP_PAGE_CNT" , 0x14F0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT9_BP_PAGE_CNT" , 0x14F0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT10_BP_PAGE_CNT" , 0x14F0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT11_BP_PAGE_CNT" , 0x14F0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT12_BP_PAGE_CNT" , 0x14F0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT13_BP_PAGE_CNT" , 0x14F0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT14_BP_PAGE_CNT" , 0x14F0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT15_BP_PAGE_CNT" , 0x14F00000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT16_BP_PAGE_CNT" , 0x14F00000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT17_BP_PAGE_CNT" , 0x14F00000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT18_BP_PAGE_CNT" , 0x14F00000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT19_BP_PAGE_CNT" , 0x14F00000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT20_BP_PAGE_CNT" , 0x14F00000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT21_BP_PAGE_CNT" , 0x14F00000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT22_BP_PAGE_CNT" , 0x14F00000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT23_BP_PAGE_CNT" , 0x14F00000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT24_BP_PAGE_CNT" , 0x14F00000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT25_BP_PAGE_CNT" , 0x14F00000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT26_BP_PAGE_CNT" , 0x14F00000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT27_BP_PAGE_CNT" , 0x14F0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT28_BP_PAGE_CNT" , 0x14F0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT29_BP_PAGE_CNT" , 0x14F0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT30_BP_PAGE_CNT" , 0x14F0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT31_BP_PAGE_CNT" , 0x14F0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT32_BP_PAGE_CNT" , 0x14F0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT33_BP_PAGE_CNT" , 0x14F0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT34_BP_PAGE_CNT" , 0x14F0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT35_BP_PAGE_CNT" , 0x14F0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14F00000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14F00000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14F00000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR3" , 0x14F00000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR4" , 0x14F00000001D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR5" , 0x14F00000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR6" , 0x14F00000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR7" , 0x14F00000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR8" , 0x14F00000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR9" , 0x14F0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR10" , 0x14F0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR11" , 0x14F0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR12" , 0x14F0000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR13" , 0x14F0000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR14" , 0x14F0000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR15" , 0x14F0000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR16" , 0x14F0000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR17" , 0x14F0000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR18" , 0x14F0000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR19" , 0x14F0000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR20" , 0x14F0000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR21" , 0x14F0000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR22" , 0x14F0000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR23" , 0x14F0000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR24" , 0x14F0000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR25" , 0x14F0000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR26" , 0x14F0000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR27" , 0x14F0000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR28" , 0x14F0000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR29" , 0x14F00000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR30" , 0x14F00000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR31" , 0x14F00000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14F00000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR33" , 0x14F00000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR34" , 0x14F00000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR35" , 0x14F00000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PTR_COUNT" , 0x14F0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 198},
|
|
{"IPD_QOS0_RED_MARKS" , 0x14F0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_QOS1_RED_MARKS" , 0x14F0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_QOS2_RED_MARKS" , 0x14F0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_QOS3_RED_MARKS" , 0x14F0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_QOS4_RED_MARKS" , 0x14F0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_QOS5_RED_MARKS" , 0x14F00000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_QOS6_RED_MARKS" , 0x14F00000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_QOS7_RED_MARKS" , 0x14F00000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_QUE0_FREE_PAGE_CNT" , 0x14F0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_RED_PORT_ENABLE" , 0x14F00000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_RED_QUE0_PARAM" , 0x14F00000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"IPD_RED_QUE1_PARAM" , 0x14F00000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"IPD_RED_QUE2_PARAM" , 0x14F00000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"IPD_RED_QUE3_PARAM" , 0x14F00000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"IPD_RED_QUE4_PARAM" , 0x14F0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"IPD_RED_QUE5_PARAM" , 0x14F0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"IPD_RED_QUE6_PARAM" , 0x14F0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"IPD_RED_QUE7_PARAM" , 0x14F0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14F0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
|
|
{"IPD_SUB_PORT_FCS" , 0x14F0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
|
|
{"IPD_WQE_FPA_QUEUE" , 0x14F0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
|
|
{"KEY_BIST_REG" , 0x1180020000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 206},
|
|
{"KEY_CTL_STATUS" , 0x1180020000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 207},
|
|
{"KEY_INT_ENB" , 0x1180020000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 208},
|
|
{"KEY_INT_SUM" , 0x1180020000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 209},
|
|
{"L2C_BST0" , 0x11800800007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 210},
|
|
{"L2C_BST1" , 0x11800800007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
|
|
{"L2C_BST2" , 0x11800800007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
|
|
{"L2C_CFG" , 0x1180080000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
|
|
{"L2C_DBG" , 0x1180080000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
|
|
{"L2C_DUT" , 0x1180080000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
|
|
{"L2C_LCKBASE" , 0x1180080000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
|
|
{"L2C_LCKOFF" , 0x1180080000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
|
|
{"L2C_LFB0" , 0x1180080000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
|
|
{"L2C_LFB1" , 0x1180080000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
|
|
{"L2C_LFB2" , 0x1180080000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
|
|
{"L2C_LFB3" , 0x11800800000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
|
|
{"L2C_PFC0" , 0x1180080000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
|
|
{"L2C_PFC1" , 0x11800800000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
|
|
{"L2C_PFC2" , 0x11800800000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
|
|
{"L2C_PFC3" , 0x11800800000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
|
|
{"L2C_PFCTL" , 0x1180080000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
|
|
{"L2C_SPAR0" , 0x1180080000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
|
|
{"L2C_SPAR1" , 0x1180080000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
|
|
{"L2C_SPAR2" , 0x1180080000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
|
|
{"L2C_SPAR3" , 0x1180080000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
|
|
{"L2C_SPAR4" , 0x1180080000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
|
|
{"L2D_BST0" , 0x1180080000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
|
|
{"L2D_BST1" , 0x1180080000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
|
|
{"L2D_BST2" , 0x1180080000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
|
|
{"L2D_BST3" , 0x1180080000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
|
|
{"L2D_ERR" , 0x1180080000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
|
|
{"L2D_FADR" , 0x1180080000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
|
|
{"L2D_FSYN0" , 0x1180080000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
|
|
{"L2D_FSYN1" , 0x1180080000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
|
|
{"L2D_FUS0" , 0x11800800007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
|
|
{"L2D_FUS1" , 0x11800800007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
|
|
{"L2D_FUS2" , 0x11800800007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
|
|
{"L2D_FUS3" , 0x11800800007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
|
|
{"L2T_ERR" , 0x1180080000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
|
|
{"LED_BLINK" , 0x1180000001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
|
|
{"LED_CLK_PHASE" , 0x1180000001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
|
|
{"LED_CYLON" , 0x1180000001AF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
|
|
{"LED_DBG" , 0x1180000001A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
|
|
{"LED_EN" , 0x1180000001A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
|
|
{"LED_POLARITY" , 0x1180000001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
|
|
{"LED_PRT" , 0x1180000001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
|
|
{"LED_PRT_FMT" , 0x1180000001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
|
|
{"LED_PRT_STATUS0" , 0x1180000001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
|
|
{"LED_PRT_STATUS1" , 0x1180000001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
|
|
{"LED_PRT_STATUS2" , 0x1180000001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
|
|
{"LED_PRT_STATUS3" , 0x1180000001A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
|
|
{"LED_PRT_STATUS4" , 0x1180000001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
|
|
{"LED_PRT_STATUS5" , 0x1180000001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
|
|
{"LED_PRT_STATUS6" , 0x1180000001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
|
|
{"LED_PRT_STATUS7" , 0x1180000001AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
|
|
{"LED_UDD_CNT0" , 0x1180000001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
|
|
{"LED_UDD_CNT1" , 0x1180000001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
|
|
{"LED_UDD_DAT0" , 0x1180000001A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
|
|
{"LED_UDD_DAT1" , 0x1180000001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
|
|
{"LED_UDD_DAT_CLR0" , 0x1180000001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
|
|
{"LED_UDD_DAT_CLR1" , 0x1180000001AD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
|
|
{"LED_UDD_DAT_SET0" , 0x1180000001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
|
|
{"LED_UDD_DAT_SET1" , 0x1180000001AD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
|
|
{"LMC0_COMP_CTL" , 0x1180088000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
|
|
{"LMC0_CTL" , 0x1180088000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
|
|
{"LMC0_DCLK_CNT_HI" , 0x1180088000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
|
|
{"LMC0_DCLK_CNT_LO" , 0x1180088000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
|
|
{"LMC0_DDR2_CTL" , 0x1180088000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
|
|
{"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
|
|
{"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
|
|
{"LMC0_IFB_CNT_HI" , 0x1180088000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
|
|
{"LMC0_IFB_CNT_LO" , 0x1180088000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
|
|
{"LMC0_MEM_CFG0" , 0x1180088000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
|
|
{"LMC0_MEM_CFG1" , 0x1180088000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
|
|
{"LMC0_OPS_CNT_HI" , 0x1180088000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
|
|
{"LMC0_OPS_CNT_LO" , 0x1180088000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
|
|
{"LMC0_PLL_BWCTL" , 0x1180088000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
|
|
{"LMC0_RODT_CTL" , 0x1180088000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
|
|
{"LMC0_WODT_CTL0" , 0x1180088000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
|
|
{"MIO_BOOT_BIST_STAT" , 0x11800000000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
|
|
{"MIO_BOOT_ERR" , 0x11800000000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
|
|
{"MIO_BOOT_INT" , 0x11800000000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
|
|
{"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
|
|
{"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
|
|
{"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
|
|
{"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
|
|
{"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
|
|
{"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
|
|
{"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
|
|
{"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
|
|
{"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
|
|
{"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
|
|
{"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
|
|
{"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
|
|
{"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
|
|
{"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
|
|
{"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
|
|
{"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
|
|
{"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
|
|
{"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
|
|
{"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
|
|
{"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
|
|
{"MIO_BOOT_THR" , 0x11800000000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
|
|
{"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
|
|
{"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
|
|
{"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
|
|
{"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
|
|
{"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
|
|
{"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
|
|
{"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
|
|
{"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
|
|
{"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
|
|
{"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 289},
|
|
{"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
|
|
{"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
|
|
{"MIO_UART1_DLH" , 0x1180000000C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
|
|
{"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
|
|
{"MIO_UART1_DLL" , 0x1180000000C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
|
|
{"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
|
|
{"MIO_UART1_FAR" , 0x1180000000D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
|
|
{"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
|
|
{"MIO_UART1_FCR" , 0x1180000000C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
|
|
{"MIO_UART0_HTX" , 0x1180000000B08ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
|
|
{"MIO_UART1_HTX" , 0x1180000000F08ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
|
|
{"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
|
|
{"MIO_UART1_IER" , 0x1180000000C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
|
|
{"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
|
|
{"MIO_UART1_IIR" , 0x1180000000C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
|
|
{"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
|
|
{"MIO_UART1_LCR" , 0x1180000000C18ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
|
|
{"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
|
|
{"MIO_UART1_LSR" , 0x1180000000C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
|
|
{"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
|
|
{"MIO_UART1_MCR" , 0x1180000000C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
|
|
{"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
|
|
{"MIO_UART1_MSR" , 0x1180000000C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
|
|
{"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
|
|
{"MIO_UART1_RBR" , 0x1180000000C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
|
|
{"MIO_UART0_RFL" , 0x1180000000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
|
|
{"MIO_UART1_RFL" , 0x1180000000E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
|
|
{"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
|
|
{"MIO_UART1_RFW" , 0x1180000000D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
|
|
{"MIO_UART0_SBCR" , 0x1180000000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
|
|
{"MIO_UART1_SBCR" , 0x1180000000E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
|
|
{"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
|
|
{"MIO_UART1_SCR" , 0x1180000000C38ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
|
|
{"MIO_UART0_SFE" , 0x1180000000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
|
|
{"MIO_UART1_SFE" , 0x1180000000E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
|
|
{"MIO_UART0_SRR" , 0x1180000000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
|
|
{"MIO_UART1_SRR" , 0x1180000000E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
|
|
{"MIO_UART0_SRT" , 0x1180000000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
|
|
{"MIO_UART1_SRT" , 0x1180000000E38ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
|
|
{"MIO_UART0_SRTS" , 0x1180000000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
|
|
{"MIO_UART1_SRTS" , 0x1180000000E18ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
|
|
{"MIO_UART0_STT" , 0x1180000000B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
|
|
{"MIO_UART1_STT" , 0x1180000000F00ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
|
|
{"MIO_UART0_TFL" , 0x1180000000A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
|
|
{"MIO_UART1_TFL" , 0x1180000000E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
|
|
{"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
|
|
{"MIO_UART1_TFR" , 0x1180000000D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
|
|
{"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
|
|
{"MIO_UART1_THR" , 0x1180000000C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
|
|
{"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
|
|
{"MIO_UART1_USR" , 0x1180000000D38ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
|
|
{"NPI_BASE_ADDR_INPUT0" , 0x11F0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 316},
|
|
{"NPI_BASE_ADDR_INPUT1" , 0x11F0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 316},
|
|
{"NPI_BASE_ADDR_INPUT2" , 0x11F0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 316},
|
|
{"NPI_BASE_ADDR_INPUT3" , 0x11F00000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 316},
|
|
{"NPI_BASE_ADDR_OUTPUT0" , 0x11F00000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
|
|
{"NPI_BASE_ADDR_OUTPUT1" , 0x11F00000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
|
|
{"NPI_BASE_ADDR_OUTPUT2" , 0x11F00000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
|
|
{"NPI_BASE_ADDR_OUTPUT3" , 0x11F00000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
|
|
{"NPI_BIST_STATUS" , 0x11F00000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 318},
|
|
{"NPI_BUFF_SIZE_OUTPUT0" , 0x11F00000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
|
|
{"NPI_BUFF_SIZE_OUTPUT1" , 0x11F00000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
|
|
{"NPI_BUFF_SIZE_OUTPUT2" , 0x11F00000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
|
|
{"NPI_BUFF_SIZE_OUTPUT3" , 0x11F00000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
|
|
{"NPI_CTL_STATUS" , 0x11F0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 320},
|
|
{"NPI_DBG_SELECT" , 0x11F0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 321},
|
|
{"NPI_DMA_CONTROL" , 0x11F0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
|
|
{"NPI_DMA_HIGHP_COUNTS" , 0x11F0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 323},
|
|
{"NPI_DMA_HIGHP_NADDR" , 0x11F0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 324},
|
|
{"NPI_DMA_LOWP_COUNTS" , 0x11F0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 325},
|
|
{"NPI_DMA_LOWP_NADDR" , 0x11F0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
|
|
{"NPI_HIGHP_DBELL" , 0x11F0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
|
|
{"NPI_HIGHP_IBUFF_SADDR" , 0x11F0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 328},
|
|
{"NPI_INPUT_CONTROL" , 0x11F0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 329},
|
|
{"NPI_INT_ENB" , 0x11F0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 330},
|
|
{"NPI_INT_SUM" , 0x11F0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 331},
|
|
{"NPI_LOWP_DBELL" , 0x11F0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 332},
|
|
{"NPI_LOWP_IBUFF_SADDR" , 0x11F0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 333},
|
|
{"NPI_MEM_ACCESS_SUBID3" , 0x11F0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 334},
|
|
{"NPI_MEM_ACCESS_SUBID4" , 0x11F0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 334},
|
|
{"NPI_MEM_ACCESS_SUBID5" , 0x11F0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 334},
|
|
{"NPI_MEM_ACCESS_SUBID6" , 0x11F0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 334},
|
|
{"NPI_MSI_RCV" , 0x11F0000001190ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 335},
|
|
{"NPI_NUM_DESC_OUTPUT0" , 0x11F0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
|
|
{"NPI_NUM_DESC_OUTPUT1" , 0x11F0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
|
|
{"NPI_NUM_DESC_OUTPUT2" , 0x11F0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
|
|
{"NPI_NUM_DESC_OUTPUT3" , 0x11F0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
|
|
{"NPI_OUTPUT_CONTROL" , 0x11F0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
|
|
{"NPI_P0_DBPAIR_ADDR" , 0x11F0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
|
|
{"NPI_P1_DBPAIR_ADDR" , 0x11F0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
|
|
{"NPI_P2_DBPAIR_ADDR" , 0x11F0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
|
|
{"NPI_P3_DBPAIR_ADDR" , 0x11F0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
|
|
{"NPI_P0_INSTR_ADDR" , 0x11F00000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
|
|
{"NPI_P1_INSTR_ADDR" , 0x11F00000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
|
|
{"NPI_P2_INSTR_ADDR" , 0x11F00000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
|
|
{"NPI_P3_INSTR_ADDR" , 0x11F00000001D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
|
|
{"NPI_P0_INSTR_CNTS" , 0x11F00000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
|
|
{"NPI_P1_INSTR_CNTS" , 0x11F00000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
|
|
{"NPI_P2_INSTR_CNTS" , 0x11F00000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
|
|
{"NPI_P3_INSTR_CNTS" , 0x11F00000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
|
|
{"NPI_P0_PAIR_CNTS" , 0x11F0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
|
|
{"NPI_P1_PAIR_CNTS" , 0x11F0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
|
|
{"NPI_P2_PAIR_CNTS" , 0x11F0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
|
|
{"NPI_P3_PAIR_CNTS" , 0x11F0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
|
|
{"NPI_PCI_BURST_SIZE" , 0x11F00000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
|
|
{"NPI_PCI_INT_ARB_CFG" , 0x11F0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
|
|
{"NPI_PCI_READ_CMD" , 0x11F0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 344},
|
|
{"NPI_PORT32_INSTR_HDR" , 0x11F00000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
|
|
{"NPI_PORT33_INSTR_HDR" , 0x11F0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 346},
|
|
{"NPI_PORT34_INSTR_HDR" , 0x11F0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 347},
|
|
{"NPI_PORT35_INSTR_HDR" , 0x11F0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 348},
|
|
{"NPI_PORT_BP_CONTROL" , 0x11F00000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
|
|
{"NPI_RSL_INT_BLOCKS" , 0x11F0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
|
|
{"NPI_SIZE_INPUT0" , 0x11F0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
|
|
{"NPI_SIZE_INPUT1" , 0x11F0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
|
|
{"NPI_SIZE_INPUT2" , 0x11F0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
|
|
{"NPI_SIZE_INPUT3" , 0x11F00000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
|
|
{"NPI_WIN_READ_TO" , 0x11F00000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 352},
|
|
{"PCI_BAR1_INDEX0" , 0x11F0000001100ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX1" , 0x11F0000001104ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX2" , 0x11F0000001108ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX3" , 0x11F000000110Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX4" , 0x11F0000001110ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX5" , 0x11F0000001114ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX6" , 0x11F0000001118ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX7" , 0x11F000000111Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX8" , 0x11F0000001120ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX9" , 0x11F0000001124ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX10" , 0x11F0000001128ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX11" , 0x11F000000112Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX12" , 0x11F0000001130ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX13" , 0x11F0000001134ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX14" , 0x11F0000001138ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX15" , 0x11F000000113Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX16" , 0x11F0000001140ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX17" , 0x11F0000001144ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX18" , 0x11F0000001148ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX19" , 0x11F000000114Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX20" , 0x11F0000001150ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX21" , 0x11F0000001154ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX22" , 0x11F0000001158ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX23" , 0x11F000000115Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX24" , 0x11F0000001160ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX25" , 0x11F0000001164ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX26" , 0x11F0000001168ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX27" , 0x11F000000116Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX28" , 0x11F0000001170ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX29" , 0x11F0000001174ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX30" , 0x11F0000001178ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_BAR1_INDEX31" , 0x11F000000117Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_CFG00" , 0x11F0000001800ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 354},
|
|
{"PCI_CFG01" , 0x11F0000001804ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 355},
|
|
{"PCI_CFG02" , 0x11F0000001808ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 356},
|
|
{"PCI_CFG03" , 0x11F000000180Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 357},
|
|
{"PCI_CFG04" , 0x11F0000001810ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 358},
|
|
{"PCI_CFG05" , 0x11F0000001814ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 359},
|
|
{"PCI_CFG06" , 0x11F0000001818ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 360},
|
|
{"PCI_CFG07" , 0x11F000000181Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 361},
|
|
{"PCI_CFG08" , 0x11F0000001820ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 362},
|
|
{"PCI_CFG09" , 0x11F0000001824ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 363},
|
|
{"PCI_CFG10" , 0x11F0000001828ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 364},
|
|
{"PCI_CFG11" , 0x11F000000182Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 365},
|
|
{"PCI_CFG12" , 0x11F0000001830ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 366},
|
|
{"PCI_CFG13" , 0x11F0000001834ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 367},
|
|
{"PCI_CFG15" , 0x11F000000183Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 368},
|
|
{"PCI_CFG16" , 0x11F0000001840ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 369},
|
|
{"PCI_CFG17" , 0x11F0000001844ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 370},
|
|
{"PCI_CFG18" , 0x11F0000001848ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 371},
|
|
{"PCI_CFG19" , 0x11F000000184Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 372},
|
|
{"PCI_CFG20" , 0x11F0000001850ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 373},
|
|
{"PCI_CFG21" , 0x11F0000001854ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 374},
|
|
{"PCI_CFG22" , 0x11F0000001858ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 375},
|
|
{"PCI_CFG56" , 0x11F00000018E0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 376},
|
|
{"PCI_CFG57" , 0x11F00000018E4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 377},
|
|
{"PCI_CFG58" , 0x11F00000018E8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 378},
|
|
{"PCI_CFG59" , 0x11F00000018ECull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 379},
|
|
{"PCI_CFG60" , 0x11F00000018F0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 380},
|
|
{"PCI_CFG61" , 0x11F00000018F4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 381},
|
|
{"PCI_CFG62" , 0x11F00000018F8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 382},
|
|
{"PCI_CFG63" , 0x11F00000018FCull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 383},
|
|
{"PCI_CTL_STATUS_2" , 0x11F000000118Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 384},
|
|
{"PCI_DBELL0" , 0x80ull, CVMX_CSR_DB_TYPE_PCI, 32, 385},
|
|
{"PCI_DBELL1" , 0x88ull, CVMX_CSR_DB_TYPE_PCI, 32, 385},
|
|
{"PCI_DBELL2" , 0x90ull, CVMX_CSR_DB_TYPE_PCI, 32, 385},
|
|
{"PCI_DBELL3" , 0x98ull, CVMX_CSR_DB_TYPE_PCI, 32, 385},
|
|
{"PCI_DMA_CNT0" , 0xA0ull, CVMX_CSR_DB_TYPE_PCI, 32, 386},
|
|
{"PCI_DMA_CNT1" , 0xA8ull, CVMX_CSR_DB_TYPE_PCI, 32, 386},
|
|
{"PCI_DMA_INT_LEV0" , 0xA4ull, CVMX_CSR_DB_TYPE_PCI, 32, 387},
|
|
{"PCI_DMA_INT_LEV1" , 0xACull, CVMX_CSR_DB_TYPE_PCI, 32, 387},
|
|
{"PCI_DMA_TIME0" , 0xB0ull, CVMX_CSR_DB_TYPE_PCI, 32, 388},
|
|
{"PCI_DMA_TIME1" , 0xB4ull, CVMX_CSR_DB_TYPE_PCI, 32, 388},
|
|
{"PCI_INSTR_COUNT0" , 0x84ull, CVMX_CSR_DB_TYPE_PCI, 32, 389},
|
|
{"PCI_INSTR_COUNT1" , 0x8Cull, CVMX_CSR_DB_TYPE_PCI, 32, 389},
|
|
{"PCI_INSTR_COUNT2" , 0x94ull, CVMX_CSR_DB_TYPE_PCI, 32, 389},
|
|
{"PCI_INSTR_COUNT3" , 0x9Cull, CVMX_CSR_DB_TYPE_PCI, 32, 389},
|
|
{"PCI_INT_ENB" , 0x38ull, CVMX_CSR_DB_TYPE_PCI, 64, 390},
|
|
{"PCI_INT_ENB2" , 0x11F00000011A0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 391},
|
|
{"PCI_INT_SUM" , 0x30ull, CVMX_CSR_DB_TYPE_PCI, 64, 392},
|
|
{"PCI_INT_SUM2" , 0x11F0000001198ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 393},
|
|
{"PCI_MSI_RCV" , 0xF0ull, CVMX_CSR_DB_TYPE_PCI, 32, 394},
|
|
{"PCI_PKT_CREDITS0" , 0x44ull, CVMX_CSR_DB_TYPE_PCI, 32, 395},
|
|
{"PCI_PKT_CREDITS1" , 0x54ull, CVMX_CSR_DB_TYPE_PCI, 32, 395},
|
|
{"PCI_PKT_CREDITS2" , 0x64ull, CVMX_CSR_DB_TYPE_PCI, 32, 395},
|
|
{"PCI_PKT_CREDITS3" , 0x74ull, CVMX_CSR_DB_TYPE_PCI, 32, 395},
|
|
{"PCI_PKTS_SENT0" , 0x40ull, CVMX_CSR_DB_TYPE_PCI, 32, 396},
|
|
{"PCI_PKTS_SENT1" , 0x50ull, CVMX_CSR_DB_TYPE_PCI, 32, 396},
|
|
{"PCI_PKTS_SENT2" , 0x60ull, CVMX_CSR_DB_TYPE_PCI, 32, 396},
|
|
{"PCI_PKTS_SENT3" , 0x70ull, CVMX_CSR_DB_TYPE_PCI, 32, 396},
|
|
{"PCI_PKTS_SENT_INT_LEV0" , 0x48ull, CVMX_CSR_DB_TYPE_PCI, 32, 397},
|
|
{"PCI_PKTS_SENT_INT_LEV1" , 0x58ull, CVMX_CSR_DB_TYPE_PCI, 32, 397},
|
|
{"PCI_PKTS_SENT_INT_LEV2" , 0x68ull, CVMX_CSR_DB_TYPE_PCI, 32, 397},
|
|
{"PCI_PKTS_SENT_INT_LEV3" , 0x78ull, CVMX_CSR_DB_TYPE_PCI, 32, 397},
|
|
{"PCI_PKTS_SENT_TIME0" , 0x4Cull, CVMX_CSR_DB_TYPE_PCI, 32, 398},
|
|
{"PCI_PKTS_SENT_TIME1" , 0x5Cull, CVMX_CSR_DB_TYPE_PCI, 32, 398},
|
|
{"PCI_PKTS_SENT_TIME2" , 0x6Cull, CVMX_CSR_DB_TYPE_PCI, 32, 398},
|
|
{"PCI_PKTS_SENT_TIME3" , 0x7Cull, CVMX_CSR_DB_TYPE_PCI, 32, 398},
|
|
{"PCI_READ_CMD_6" , 0x11F0000001180ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 399},
|
|
{"PCI_READ_CMD_C" , 0x11F0000001184ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 400},
|
|
{"PCI_READ_CMD_E" , 0x11F0000001188ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 401},
|
|
{"PCI_READ_TIMEOUT" , 0x11F00000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
|
|
{"PCI_SCM_REG" , 0x11F00000011A8ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 403},
|
|
{"PCI_TSR_REG" , 0x11F00000011B0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 404},
|
|
{"PCI_WIN_RD_ADDR" , 0x8ull, CVMX_CSR_DB_TYPE_PCI, 64, 405},
|
|
{"PCI_WIN_RD_DATA" , 0x20ull, CVMX_CSR_DB_TYPE_PCI, 64, 406},
|
|
{"PCI_WIN_WR_ADDR" , 0x0ull, CVMX_CSR_DB_TYPE_PCI, 64, 407},
|
|
{"PCI_WIN_WR_DATA" , 0x10ull, CVMX_CSR_DB_TYPE_PCI, 64, 408},
|
|
{"PCI_WIN_WR_MASK" , 0x18ull, CVMX_CSR_DB_TYPE_PCI, 64, 409},
|
|
{"PIP_BCK_PRS" , 0x11800A0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
|
|
{"PIP_BIST_STATUS" , 0x11800A0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
|
|
{"PIP_CRC_CTL0" , 0x11800A0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
|
|
{"PIP_CRC_CTL1" , 0x11800A0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
|
|
{"PIP_CRC_IV0" , 0x11800A0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
|
|
{"PIP_CRC_IV1" , 0x11800A0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
|
|
{"PIP_DEC_IPSEC0" , 0x11800A0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
|
|
{"PIP_DEC_IPSEC1" , 0x11800A0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
|
|
{"PIP_DEC_IPSEC2" , 0x11800A0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
|
|
{"PIP_DEC_IPSEC3" , 0x11800A0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
|
|
{"PIP_GBL_CFG" , 0x11800A0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_GBL_CTL" , 0x11800A0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
|
|
{"PIP_INT_EN" , 0x11800A0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
|
|
{"PIP_INT_REG" , 0x11800A0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
|
|
{"PIP_IP_OFFSET" , 0x11800A0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
|
|
{"PIP_PRT_CFG0" , 0x11800A0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG1" , 0x11800A0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG2" , 0x11800A0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG3" , 0x11800A0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG4" , 0x11800A0000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG5" , 0x11800A0000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG6" , 0x11800A0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG7" , 0x11800A0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG8" , 0x11800A0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG9" , 0x11800A0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG10" , 0x11800A0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG11" , 0x11800A0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG12" , 0x11800A0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG13" , 0x11800A0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG14" , 0x11800A0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG15" , 0x11800A0000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG16" , 0x11800A0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG17" , 0x11800A0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG18" , 0x11800A0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG19" , 0x11800A0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG20" , 0x11800A00002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG21" , 0x11800A00002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG22" , 0x11800A00002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG23" , 0x11800A00002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG24" , 0x11800A00002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG25" , 0x11800A00002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG26" , 0x11800A00002D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG27" , 0x11800A00002D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG28" , 0x11800A00002E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG29" , 0x11800A00002E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG30" , 0x11800A00002F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG31" , 0x11800A00002F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG32" , 0x11800A0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG33" , 0x11800A0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG34" , 0x11800A0000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_CFG35" , 0x11800A0000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_PRT_TAG0" , 0x11800A0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG1" , 0x11800A0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG2" , 0x11800A0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG3" , 0x11800A0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG4" , 0x11800A0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG5" , 0x11800A0000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG6" , 0x11800A0000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG7" , 0x11800A0000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG8" , 0x11800A0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG9" , 0x11800A0000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG10" , 0x11800A0000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG11" , 0x11800A0000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG12" , 0x11800A0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG13" , 0x11800A0000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG14" , 0x11800A0000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG15" , 0x11800A0000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG16" , 0x11800A0000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG17" , 0x11800A0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG18" , 0x11800A0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG19" , 0x11800A0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG20" , 0x11800A00004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG21" , 0x11800A00004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG22" , 0x11800A00004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG23" , 0x11800A00004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG24" , 0x11800A00004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG25" , 0x11800A00004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG26" , 0x11800A00004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG27" , 0x11800A00004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG28" , 0x11800A00004E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG29" , 0x11800A00004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG30" , 0x11800A00004F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG31" , 0x11800A00004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG32" , 0x11800A0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG33" , 0x11800A0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG34" , 0x11800A0000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_PRT_TAG35" , 0x11800A0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_QOS_DIFF0" , 0x11800A0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF1" , 0x11800A0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF2" , 0x11800A0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF3" , 0x11800A0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF4" , 0x11800A0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF5" , 0x11800A0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF6" , 0x11800A0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF7" , 0x11800A0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF8" , 0x11800A0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF9" , 0x11800A0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF10" , 0x11800A0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF11" , 0x11800A0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF12" , 0x11800A0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF13" , 0x11800A0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF14" , 0x11800A0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF15" , 0x11800A0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF16" , 0x11800A0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF17" , 0x11800A0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF18" , 0x11800A0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF19" , 0x11800A0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF20" , 0x11800A00006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF21" , 0x11800A00006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF22" , 0x11800A00006B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF23" , 0x11800A00006B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF24" , 0x11800A00006C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF25" , 0x11800A00006C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF26" , 0x11800A00006D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF27" , 0x11800A00006D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF28" , 0x11800A00006E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF29" , 0x11800A00006E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF30" , 0x11800A00006F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF31" , 0x11800A00006F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF32" , 0x11800A0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF33" , 0x11800A0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF34" , 0x11800A0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF35" , 0x11800A0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF36" , 0x11800A0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF37" , 0x11800A0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF38" , 0x11800A0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF39" , 0x11800A0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF40" , 0x11800A0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF41" , 0x11800A0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF42" , 0x11800A0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF43" , 0x11800A0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF44" , 0x11800A0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF45" , 0x11800A0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF46" , 0x11800A0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF47" , 0x11800A0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF48" , 0x11800A0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF49" , 0x11800A0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF50" , 0x11800A0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF51" , 0x11800A0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF52" , 0x11800A00007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF53" , 0x11800A00007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF54" , 0x11800A00007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF55" , 0x11800A00007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF56" , 0x11800A00007C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF57" , 0x11800A00007C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF58" , 0x11800A00007D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF59" , 0x11800A00007D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF60" , 0x11800A00007E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF61" , 0x11800A00007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF62" , 0x11800A00007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_DIFF63" , 0x11800A00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_VLAN0" , 0x11800A00000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
|
|
{"PIP_QOS_VLAN1" , 0x11800A00000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
|
|
{"PIP_QOS_VLAN2" , 0x11800A00000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
|
|
{"PIP_QOS_VLAN3" , 0x11800A00000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
|
|
{"PIP_QOS_VLAN4" , 0x11800A00000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
|
|
{"PIP_QOS_VLAN5" , 0x11800A00000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
|
|
{"PIP_QOS_VLAN6" , 0x11800A00000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
|
|
{"PIP_QOS_VLAN7" , 0x11800A00000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
|
|
{"PIP_QOS_WATCH0" , 0x11800A0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
|
|
{"PIP_QOS_WATCH1" , 0x11800A0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
|
|
{"PIP_QOS_WATCH2" , 0x11800A0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
|
|
{"PIP_QOS_WATCH3" , 0x11800A0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
|
|
{"PIP_RAW_WORD" , 0x11800A00000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
|
|
{"PIP_STAT0_PRT0" , 0x11800A0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT1" , 0x11800A0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT2" , 0x11800A00008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT3" , 0x11800A00008F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT4" , 0x11800A0000940ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT5" , 0x11800A0000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT6" , 0x11800A00009E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT7" , 0x11800A0000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT8" , 0x11800A0000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT9" , 0x11800A0000AD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT10" , 0x11800A0000B20ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT11" , 0x11800A0000B70ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT12" , 0x11800A0000BC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT13" , 0x11800A0000C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT14" , 0x11800A0000C60ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT15" , 0x11800A0000CB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT16" , 0x11800A0000D00ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT17" , 0x11800A0000D50ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT18" , 0x11800A0000DA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT19" , 0x11800A0000DF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT20" , 0x11800A0000E40ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT21" , 0x11800A0000E90ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT22" , 0x11800A0000EE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT23" , 0x11800A0000F30ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT24" , 0x11800A0000F80ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT25" , 0x11800A0000FD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT26" , 0x11800A0001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT27" , 0x11800A0001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT28" , 0x11800A00010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT29" , 0x11800A0001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT30" , 0x11800A0001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT31" , 0x11800A00011B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT32" , 0x11800A0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT33" , 0x11800A0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT34" , 0x11800A00012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT0_PRT35" , 0x11800A00012F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT1_PRT0" , 0x11800A0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT1" , 0x11800A0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT2" , 0x11800A00008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT3" , 0x11800A00008F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT4" , 0x11800A0000948ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT5" , 0x11800A0000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT6" , 0x11800A00009E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT7" , 0x11800A0000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT8" , 0x11800A0000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT9" , 0x11800A0000AD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT10" , 0x11800A0000B28ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT11" , 0x11800A0000B78ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT12" , 0x11800A0000BC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT13" , 0x11800A0000C18ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT14" , 0x11800A0000C68ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT15" , 0x11800A0000CB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT16" , 0x11800A0000D08ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT17" , 0x11800A0000D58ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT18" , 0x11800A0000DA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT19" , 0x11800A0000DF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT20" , 0x11800A0000E48ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT21" , 0x11800A0000E98ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT22" , 0x11800A0000EE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT23" , 0x11800A0000F38ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT24" , 0x11800A0000F88ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT25" , 0x11800A0000FD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT26" , 0x11800A0001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT27" , 0x11800A0001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT28" , 0x11800A00010C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT29" , 0x11800A0001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT30" , 0x11800A0001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT31" , 0x11800A00011B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT32" , 0x11800A0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT33" , 0x11800A0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT34" , 0x11800A00012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT1_PRT35" , 0x11800A00012F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT2_PRT0" , 0x11800A0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT1" , 0x11800A0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT2" , 0x11800A00008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT3" , 0x11800A0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT4" , 0x11800A0000950ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT5" , 0x11800A00009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT6" , 0x11800A00009F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT7" , 0x11800A0000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT8" , 0x11800A0000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT9" , 0x11800A0000AE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT10" , 0x11800A0000B30ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT11" , 0x11800A0000B80ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT12" , 0x11800A0000BD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT13" , 0x11800A0000C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT14" , 0x11800A0000C70ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT15" , 0x11800A0000CC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT16" , 0x11800A0000D10ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT17" , 0x11800A0000D60ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT18" , 0x11800A0000DB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT19" , 0x11800A0000E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT20" , 0x11800A0000E50ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT21" , 0x11800A0000EA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT22" , 0x11800A0000EF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT23" , 0x11800A0000F40ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT24" , 0x11800A0000F90ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT25" , 0x11800A0000FE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT26" , 0x11800A0001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT27" , 0x11800A0001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT28" , 0x11800A00010D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT29" , 0x11800A0001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT30" , 0x11800A0001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT31" , 0x11800A00011C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT32" , 0x11800A0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT33" , 0x11800A0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT34" , 0x11800A00012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT2_PRT35" , 0x11800A0001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT3_PRT0" , 0x11800A0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT1" , 0x11800A0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT2" , 0x11800A00008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT3" , 0x11800A0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT4" , 0x11800A0000958ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT5" , 0x11800A00009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT6" , 0x11800A00009F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT7" , 0x11800A0000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT8" , 0x11800A0000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT9" , 0x11800A0000AE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT10" , 0x11800A0000B38ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT11" , 0x11800A0000B88ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT12" , 0x11800A0000BD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT13" , 0x11800A0000C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT14" , 0x11800A0000C78ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT15" , 0x11800A0000CC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT16" , 0x11800A0000D18ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT17" , 0x11800A0000D68ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT18" , 0x11800A0000DB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT19" , 0x11800A0000E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT20" , 0x11800A0000E58ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT21" , 0x11800A0000EA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT22" , 0x11800A0000EF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT23" , 0x11800A0000F48ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT24" , 0x11800A0000F98ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT25" , 0x11800A0000FE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT26" , 0x11800A0001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT27" , 0x11800A0001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT28" , 0x11800A00010D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT29" , 0x11800A0001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT30" , 0x11800A0001178ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT31" , 0x11800A00011C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT32" , 0x11800A0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT33" , 0x11800A0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT34" , 0x11800A00012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT3_PRT35" , 0x11800A0001308ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT4_PRT0" , 0x11800A0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT1" , 0x11800A0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT2" , 0x11800A00008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT3" , 0x11800A0000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT4" , 0x11800A0000960ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT5" , 0x11800A00009B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT6" , 0x11800A0000A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT7" , 0x11800A0000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT8" , 0x11800A0000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT9" , 0x11800A0000AF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT10" , 0x11800A0000B40ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT11" , 0x11800A0000B90ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT12" , 0x11800A0000BE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT13" , 0x11800A0000C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT14" , 0x11800A0000C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT15" , 0x11800A0000CD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT16" , 0x11800A0000D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT17" , 0x11800A0000D70ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT18" , 0x11800A0000DC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT19" , 0x11800A0000E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT20" , 0x11800A0000E60ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT21" , 0x11800A0000EB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT22" , 0x11800A0000F00ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT23" , 0x11800A0000F50ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT24" , 0x11800A0000FA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT25" , 0x11800A0000FF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT26" , 0x11800A0001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT27" , 0x11800A0001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT28" , 0x11800A00010E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT29" , 0x11800A0001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT30" , 0x11800A0001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT31" , 0x11800A00011D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT32" , 0x11800A0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT33" , 0x11800A0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT34" , 0x11800A00012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT4_PRT35" , 0x11800A0001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT5_PRT0" , 0x11800A0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT1" , 0x11800A0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT2" , 0x11800A00008C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT3" , 0x11800A0000918ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT4" , 0x11800A0000968ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT5" , 0x11800A00009B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT6" , 0x11800A0000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT7" , 0x11800A0000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT8" , 0x11800A0000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT9" , 0x11800A0000AF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT10" , 0x11800A0000B48ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT11" , 0x11800A0000B98ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT12" , 0x11800A0000BE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT13" , 0x11800A0000C38ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT14" , 0x11800A0000C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT15" , 0x11800A0000CD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT16" , 0x11800A0000D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT17" , 0x11800A0000D78ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT18" , 0x11800A0000DC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT19" , 0x11800A0000E18ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT20" , 0x11800A0000E68ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT21" , 0x11800A0000EB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT22" , 0x11800A0000F08ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT23" , 0x11800A0000F58ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT24" , 0x11800A0000FA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT25" , 0x11800A0000FF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT26" , 0x11800A0001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT27" , 0x11800A0001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT28" , 0x11800A00010E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT29" , 0x11800A0001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT30" , 0x11800A0001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT31" , 0x11800A00011D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT32" , 0x11800A0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT33" , 0x11800A0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT34" , 0x11800A00012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT5_PRT35" , 0x11800A0001318ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT6_PRT0" , 0x11800A0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT1" , 0x11800A0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT2" , 0x11800A00008D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT3" , 0x11800A0000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT4" , 0x11800A0000970ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT5" , 0x11800A00009C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT6" , 0x11800A0000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT7" , 0x11800A0000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT8" , 0x11800A0000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT9" , 0x11800A0000B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT10" , 0x11800A0000B50ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT11" , 0x11800A0000BA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT12" , 0x11800A0000BF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT13" , 0x11800A0000C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT14" , 0x11800A0000C90ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT15" , 0x11800A0000CE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT16" , 0x11800A0000D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT17" , 0x11800A0000D80ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT18" , 0x11800A0000DD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT19" , 0x11800A0000E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT20" , 0x11800A0000E70ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT21" , 0x11800A0000EC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT22" , 0x11800A0000F10ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT23" , 0x11800A0000F60ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT24" , 0x11800A0000FB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT25" , 0x11800A0001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT26" , 0x11800A0001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT27" , 0x11800A00010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT28" , 0x11800A00010F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT29" , 0x11800A0001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT30" , 0x11800A0001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT31" , 0x11800A00011E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT32" , 0x11800A0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT33" , 0x11800A0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT34" , 0x11800A00012D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT6_PRT35" , 0x11800A0001320ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT7_PRT0" , 0x11800A0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT1" , 0x11800A0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT2" , 0x11800A00008D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT3" , 0x11800A0000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT4" , 0x11800A0000978ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT5" , 0x11800A00009C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT6" , 0x11800A0000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT7" , 0x11800A0000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT8" , 0x11800A0000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT9" , 0x11800A0000B08ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT10" , 0x11800A0000B58ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT11" , 0x11800A0000BA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT12" , 0x11800A0000BF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT13" , 0x11800A0000C48ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT14" , 0x11800A0000C98ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT15" , 0x11800A0000CE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT16" , 0x11800A0000D38ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT17" , 0x11800A0000D88ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT18" , 0x11800A0000DD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT19" , 0x11800A0000E28ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT20" , 0x11800A0000E78ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT21" , 0x11800A0000EC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT22" , 0x11800A0000F18ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT23" , 0x11800A0000F68ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT24" , 0x11800A0000FB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT25" , 0x11800A0001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT26" , 0x11800A0001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT27" , 0x11800A00010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT28" , 0x11800A00010F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT29" , 0x11800A0001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT30" , 0x11800A0001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT31" , 0x11800A00011E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT32" , 0x11800A0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT33" , 0x11800A0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT34" , 0x11800A00012D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT7_PRT35" , 0x11800A0001328ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT8_PRT0" , 0x11800A0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT1" , 0x11800A0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT2" , 0x11800A00008E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT3" , 0x11800A0000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT4" , 0x11800A0000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT5" , 0x11800A00009D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT6" , 0x11800A0000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT7" , 0x11800A0000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT8" , 0x11800A0000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT9" , 0x11800A0000B10ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT10" , 0x11800A0000B60ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT11" , 0x11800A0000BB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT12" , 0x11800A0000C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT13" , 0x11800A0000C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT14" , 0x11800A0000CA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT15" , 0x11800A0000CF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT16" , 0x11800A0000D40ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT17" , 0x11800A0000D90ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT18" , 0x11800A0000DE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT19" , 0x11800A0000E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT20" , 0x11800A0000E80ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT21" , 0x11800A0000ED0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT22" , 0x11800A0000F20ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT23" , 0x11800A0000F70ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT24" , 0x11800A0000FC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT25" , 0x11800A0001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT26" , 0x11800A0001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT27" , 0x11800A00010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT28" , 0x11800A0001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT29" , 0x11800A0001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT30" , 0x11800A00011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT31" , 0x11800A00011F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT32" , 0x11800A0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT33" , 0x11800A0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT34" , 0x11800A00012E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT8_PRT35" , 0x11800A0001330ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT9_PRT0" , 0x11800A0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT1" , 0x11800A0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT2" , 0x11800A00008E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT3" , 0x11800A0000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT4" , 0x11800A0000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT5" , 0x11800A00009D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT6" , 0x11800A0000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT7" , 0x11800A0000A78ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT8" , 0x11800A0000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT9" , 0x11800A0000B18ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT10" , 0x11800A0000B68ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT11" , 0x11800A0000BB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT12" , 0x11800A0000C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT13" , 0x11800A0000C58ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT14" , 0x11800A0000CA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT15" , 0x11800A0000CF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT16" , 0x11800A0000D48ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT17" , 0x11800A0000D98ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT18" , 0x11800A0000DE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT19" , 0x11800A0000E38ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT20" , 0x11800A0000E88ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT21" , 0x11800A0000ED8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT22" , 0x11800A0000F28ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT23" , 0x11800A0000F78ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT24" , 0x11800A0000FC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT25" , 0x11800A0001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT26" , 0x11800A0001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT27" , 0x11800A00010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT28" , 0x11800A0001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT29" , 0x11800A0001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT30" , 0x11800A00011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT31" , 0x11800A00011F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT32" , 0x11800A0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT33" , 0x11800A0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT34" , 0x11800A00012E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT9_PRT35" , 0x11800A0001338ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT_CTL" , 0x11800A0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
|
|
{"PIP_STAT_INB_ERRS0" , 0x11800A0001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS1" , 0x11800A0001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS2" , 0x11800A0001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS3" , 0x11800A0001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS4" , 0x11800A0001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS5" , 0x11800A0001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS6" , 0x11800A0001AD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS7" , 0x11800A0001AF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS8" , 0x11800A0001B10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS9" , 0x11800A0001B30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS10" , 0x11800A0001B50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS11" , 0x11800A0001B70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS12" , 0x11800A0001B90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS13" , 0x11800A0001BB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS14" , 0x11800A0001BD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS15" , 0x11800A0001BF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS16" , 0x11800A0001C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS17" , 0x11800A0001C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS18" , 0x11800A0001C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS19" , 0x11800A0001C70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS20" , 0x11800A0001C90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS21" , 0x11800A0001CB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS22" , 0x11800A0001CD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS23" , 0x11800A0001CF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS24" , 0x11800A0001D10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS25" , 0x11800A0001D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS26" , 0x11800A0001D50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS27" , 0x11800A0001D70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS28" , 0x11800A0001D90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS29" , 0x11800A0001DB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS30" , 0x11800A0001DD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS31" , 0x11800A0001DF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS32" , 0x11800A0001E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS33" , 0x11800A0001E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS34" , 0x11800A0001E50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_ERRS35" , 0x11800A0001E70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_OCTS0" , 0x11800A0001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS1" , 0x11800A0001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS2" , 0x11800A0001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS3" , 0x11800A0001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS4" , 0x11800A0001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS5" , 0x11800A0001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS6" , 0x11800A0001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS7" , 0x11800A0001AE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS8" , 0x11800A0001B08ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS9" , 0x11800A0001B28ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS10" , 0x11800A0001B48ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS11" , 0x11800A0001B68ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS12" , 0x11800A0001B88ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS13" , 0x11800A0001BA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS14" , 0x11800A0001BC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS15" , 0x11800A0001BE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS16" , 0x11800A0001C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS17" , 0x11800A0001C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS18" , 0x11800A0001C48ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS19" , 0x11800A0001C68ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS20" , 0x11800A0001C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS21" , 0x11800A0001CA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS22" , 0x11800A0001CC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS23" , 0x11800A0001CE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS24" , 0x11800A0001D08ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS25" , 0x11800A0001D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS26" , 0x11800A0001D48ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS27" , 0x11800A0001D68ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS28" , 0x11800A0001D88ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS29" , 0x11800A0001DA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS30" , 0x11800A0001DC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS31" , 0x11800A0001DE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS32" , 0x11800A0001E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS33" , 0x11800A0001E28ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS34" , 0x11800A0001E48ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_OCTS35" , 0x11800A0001E68ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_PKTS0" , 0x11800A0001A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS1" , 0x11800A0001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS2" , 0x11800A0001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS3" , 0x11800A0001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS4" , 0x11800A0001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS5" , 0x11800A0001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS6" , 0x11800A0001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS7" , 0x11800A0001AE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS8" , 0x11800A0001B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS9" , 0x11800A0001B20ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS10" , 0x11800A0001B40ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS11" , 0x11800A0001B60ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS12" , 0x11800A0001B80ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS13" , 0x11800A0001BA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS14" , 0x11800A0001BC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS15" , 0x11800A0001BE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS16" , 0x11800A0001C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS17" , 0x11800A0001C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS18" , 0x11800A0001C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS19" , 0x11800A0001C60ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS20" , 0x11800A0001C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS21" , 0x11800A0001CA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS22" , 0x11800A0001CC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS23" , 0x11800A0001CE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS24" , 0x11800A0001D00ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS25" , 0x11800A0001D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS26" , 0x11800A0001D40ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS27" , 0x11800A0001D60ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS28" , 0x11800A0001D80ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS29" , 0x11800A0001DA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS30" , 0x11800A0001DC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS31" , 0x11800A0001DE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS32" , 0x11800A0001E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS33" , 0x11800A0001E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS34" , 0x11800A0001E40ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT_INB_PKTS35" , 0x11800A0001E60ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC0" , 0x11800A0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC1" , 0x11800A0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC2" , 0x11800A0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC3" , 0x11800A0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC4" , 0x11800A0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC5" , 0x11800A0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC6" , 0x11800A0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC7" , 0x11800A0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC8" , 0x11800A0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC9" , 0x11800A0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC10" , 0x11800A0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC11" , 0x11800A0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC12" , 0x11800A0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC13" , 0x11800A0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC14" , 0x11800A0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC15" , 0x11800A0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC16" , 0x11800A0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC17" , 0x11800A0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC18" , 0x11800A0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC19" , 0x11800A0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC20" , 0x11800A00018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC21" , 0x11800A00018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC22" , 0x11800A00018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC23" , 0x11800A00018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC24" , 0x11800A00018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC25" , 0x11800A00018C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC26" , 0x11800A00018D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC27" , 0x11800A00018D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC28" , 0x11800A00018E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC29" , 0x11800A00018E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC30" , 0x11800A00018F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC31" , 0x11800A00018F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC32" , 0x11800A0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC33" , 0x11800A0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC34" , 0x11800A0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC35" , 0x11800A0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC36" , 0x11800A0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC37" , 0x11800A0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC38" , 0x11800A0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC39" , 0x11800A0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC40" , 0x11800A0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC41" , 0x11800A0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC42" , 0x11800A0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC43" , 0x11800A0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC44" , 0x11800A0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC45" , 0x11800A0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC46" , 0x11800A0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC47" , 0x11800A0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC48" , 0x11800A0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC49" , 0x11800A0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC50" , 0x11800A0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC51" , 0x11800A0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC52" , 0x11800A00019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC53" , 0x11800A00019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC54" , 0x11800A00019B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC55" , 0x11800A00019B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC56" , 0x11800A00019C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC57" , 0x11800A00019C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC58" , 0x11800A00019D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC59" , 0x11800A00019D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC60" , 0x11800A00019E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC61" , 0x11800A00019E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC62" , 0x11800A00019F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_INC63" , 0x11800A00019F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_MASK" , 0x11800A0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_TAG_SECRET" , 0x11800A0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_TODO_ENTRY" , 0x11800A0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
|
|
{"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PKO_MEM_DEBUG14" , 0x1180050001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PKO_REG_CRC_CTL0" , 0x1180050000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PKO_REG_CRC_CTL1" , 0x1180050000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PKO_REG_CRC_ENABLE" , 0x1180050000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PKO_REG_CRC_IV0" , 0x1180050000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PKO_REG_CRC_IV1" , 0x1180050000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 468},
|
|
{"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 473},
|
|
{"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 474},
|
|
{"POW_BIST_STAT" , 0x16700000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
|
|
{"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 476},
|
|
{"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 477},
|
|
{"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 478},
|
|
{"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
|
|
{"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
|
|
{"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
|
|
{"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
|
|
{"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
|
|
{"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
|
|
{"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
|
|
{"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
|
|
{"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
|
|
{"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
|
|
{"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 482},
|
|
{"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_PP_GRP_MSK2" , 0x1670000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_PP_GRP_MSK3" , 0x1670000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_PP_GRP_MSK4" , 0x1670000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_PP_GRP_MSK5" , 0x1670000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_PP_GRP_MSK6" , 0x1670000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_PP_GRP_MSK7" , 0x1670000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_PP_GRP_MSK8" , 0x1670000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_PP_GRP_MSK9" , 0x1670000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_PP_GRP_MSK10" , 0x1670000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_PP_GRP_MSK11" , 0x1670000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_PP_GRP_MSK12" , 0x1670000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_PP_GRP_MSK13" , 0x1670000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_PP_GRP_MSK14" , 0x1670000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_PP_GRP_MSK15" , 0x1670000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_QOS_RND0" , 0x16700000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
|
|
{"POW_QOS_RND1" , 0x16700000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
|
|
{"POW_QOS_RND2" , 0x16700000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
|
|
{"POW_QOS_RND3" , 0x16700000001D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
|
|
{"POW_QOS_RND4" , 0x16700000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
|
|
{"POW_QOS_RND5" , 0x16700000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
|
|
{"POW_QOS_RND6" , 0x16700000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
|
|
{"POW_QOS_RND7" , 0x16700000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
|
|
{"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_QOS_THR4" , 0x16700000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_QOS_THR5" , 0x16700000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_QOS_THR6" , 0x16700000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_QOS_THR7" , 0x16700000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
|
|
{"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
|
|
{"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
|
|
{"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
|
|
{"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
|
|
{"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
|
|
{"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
|
|
{"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
|
|
{"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
|
|
{"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
|
|
{"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
|
|
{"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
|
|
{"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
|
|
{"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
|
|
{"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
|
|
{"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
|
|
{"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
|
|
{"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
|
|
{"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
|
|
{"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 491},
|
|
{"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
|
|
{"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
|
|
{"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
|
|
{"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
|
|
{"POW_WQ_INT_THR4" , 0x16700000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
|
|
{"POW_WQ_INT_THR5" , 0x16700000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
|
|
{"POW_WQ_INT_THR6" , 0x16700000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
|
|
{"POW_WQ_INT_THR7" , 0x16700000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
|
|
{"POW_WQ_INT_THR8" , 0x16700000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
|
|
{"POW_WQ_INT_THR9" , 0x16700000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
|
|
{"POW_WQ_INT_THR10" , 0x16700000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
|
|
{"POW_WQ_INT_THR11" , 0x16700000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
|
|
{"POW_WQ_INT_THR12" , 0x16700000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
|
|
{"POW_WQ_INT_THR13" , 0x16700000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
|
|
{"POW_WQ_INT_THR14" , 0x16700000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
|
|
{"POW_WQ_INT_THR15" , 0x16700000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
|
|
{"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
|
|
{"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
|
|
{"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
|
|
{"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
|
|
{"POW_WS_PC4" , 0x16700000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
|
|
{"POW_WS_PC5" , 0x16700000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
|
|
{"POW_WS_PC6" , 0x16700000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
|
|
{"POW_WS_PC7" , 0x16700000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
|
|
{"POW_WS_PC8" , 0x16700000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
|
|
{"POW_WS_PC9" , 0x16700000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
|
|
{"POW_WS_PC10" , 0x16700000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
|
|
{"POW_WS_PC11" , 0x16700000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
|
|
{"POW_WS_PC12" , 0x16700000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
|
|
{"POW_WS_PC13" , 0x16700000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
|
|
{"POW_WS_PC14" , 0x16700000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
|
|
{"POW_WS_PC15" , 0x16700000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
|
|
{"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 494},
|
|
{"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 495},
|
|
{"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
|
|
{"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
|
|
{"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
|
|
{"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
|
|
{"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
|
|
{"SPX0_BCKPRS_CNT" , 0x1180090000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
|
|
{"SPX1_BCKPRS_CNT" , 0x1180098000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
|
|
{"SPX0_BIST_STAT" , 0x11800900007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
|
|
{"SPX1_BIST_STAT" , 0x11800980007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
|
|
{"SPX0_CLK_CTL" , 0x1180090000348ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
|
|
{"SPX1_CLK_CTL" , 0x1180098000348ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
|
|
{"SPX0_CLK_STAT" , 0x1180090000350ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
|
|
{"SPX1_CLK_STAT" , 0x1180098000350ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
|
|
{"SPX0_DBG_DESKEW_CTL" , 0x1180090000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
|
|
{"SPX1_DBG_DESKEW_CTL" , 0x1180098000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
|
|
{"SPX0_DBG_DESKEW_STATE" , 0x1180090000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
|
|
{"SPX1_DBG_DESKEW_STATE" , 0x1180098000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
|
|
{"SPX0_DRV_CTL" , 0x1180090000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
|
|
{"SPX1_DRV_CTL" , 0x1180098000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
|
|
{"SPX0_ERR_CTL" , 0x1180090000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
|
|
{"SPX1_ERR_CTL" , 0x1180098000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
|
|
{"SPX0_INT_DAT" , 0x1180090000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
|
|
{"SPX1_INT_DAT" , 0x1180098000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
|
|
{"SPX0_INT_MSK" , 0x1180090000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
|
|
{"SPX1_INT_MSK" , 0x1180098000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
|
|
{"SPX0_INT_REG" , 0x1180090000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
|
|
{"SPX1_INT_REG" , 0x1180098000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
|
|
{"SPX0_INT_SYNC" , 0x1180090000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
|
|
{"SPX1_INT_SYNC" , 0x1180098000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
|
|
{"SPX0_TPA_ACC" , 0x1180090000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
|
|
{"SPX1_TPA_ACC" , 0x1180098000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
|
|
{"SPX0_TPA_MAX" , 0x1180090000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
|
|
{"SPX1_TPA_MAX" , 0x1180098000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
|
|
{"SPX0_TPA_SEL" , 0x1180090000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 515},
|
|
{"SPX1_TPA_SEL" , 0x1180098000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 515},
|
|
{"SPX0_TRN4_CTL" , 0x1180090000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 516},
|
|
{"SPX1_TRN4_CTL" , 0x1180098000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 516},
|
|
{"SPX0_PLL_BW_CTL" , 0x1180090000388ull, CVMX_CSR_DB_TYPE_RSL, 64, 517},
|
|
{"SPX0_PLL_SETTING" , 0x1180090000380ull, CVMX_CSR_DB_TYPE_RSL, 64, 518},
|
|
{"SRX0_COM_CTL" , 0x1180090000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 519},
|
|
{"SRX1_COM_CTL" , 0x1180098000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 519},
|
|
{"SRX0_IGN_RX_FULL" , 0x1180090000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 520},
|
|
{"SRX1_IGN_RX_FULL" , 0x1180098000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 520},
|
|
{"SRX0_SPI4_CAL000" , 0x1180090000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL001" , 0x1180090000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL002" , 0x1180090000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL003" , 0x1180090000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL004" , 0x1180090000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL005" , 0x1180090000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL006" , 0x1180090000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL007" , 0x1180090000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL008" , 0x1180090000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL009" , 0x1180090000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL010" , 0x1180090000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL011" , 0x1180090000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL012" , 0x1180090000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL013" , 0x1180090000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL014" , 0x1180090000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL015" , 0x1180090000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL016" , 0x1180090000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL017" , 0x1180090000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL018" , 0x1180090000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL019" , 0x1180090000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL020" , 0x11800900000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL021" , 0x11800900000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL022" , 0x11800900000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL023" , 0x11800900000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL024" , 0x11800900000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL025" , 0x11800900000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL026" , 0x11800900000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL027" , 0x11800900000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL028" , 0x11800900000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL029" , 0x11800900000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL030" , 0x11800900000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_CAL031" , 0x11800900000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL000" , 0x1180098000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL001" , 0x1180098000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL002" , 0x1180098000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL003" , 0x1180098000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL004" , 0x1180098000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL005" , 0x1180098000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL006" , 0x1180098000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL007" , 0x1180098000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL008" , 0x1180098000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL009" , 0x1180098000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL010" , 0x1180098000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL011" , 0x1180098000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL012" , 0x1180098000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL013" , 0x1180098000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL014" , 0x1180098000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL015" , 0x1180098000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL016" , 0x1180098000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL017" , 0x1180098000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL018" , 0x1180098000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL019" , 0x1180098000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL020" , 0x11800980000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL021" , 0x11800980000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL022" , 0x11800980000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL023" , 0x11800980000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL024" , 0x11800980000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL025" , 0x11800980000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL026" , 0x11800980000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL027" , 0x11800980000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL028" , 0x11800980000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL029" , 0x11800980000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL030" , 0x11800980000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX1_SPI4_CAL031" , 0x11800980000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SRX0_SPI4_STAT" , 0x1180090000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 522},
|
|
{"SRX1_SPI4_STAT" , 0x1180098000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 522},
|
|
{"STX0_ARB_CTL" , 0x1180090000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 523},
|
|
{"STX1_ARB_CTL" , 0x1180098000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 523},
|
|
{"STX0_BCKPRS_CNT" , 0x1180090000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 524},
|
|
{"STX1_BCKPRS_CNT" , 0x1180098000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 524},
|
|
{"STX0_COM_CTL" , 0x1180090000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
|
|
{"STX1_COM_CTL" , 0x1180098000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
|
|
{"STX0_DIP_CNT" , 0x1180090000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 526},
|
|
{"STX1_DIP_CNT" , 0x1180098000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 526},
|
|
{"STX0_IGN_CAL" , 0x1180090000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 527},
|
|
{"STX1_IGN_CAL" , 0x1180098000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 527},
|
|
{"STX0_INT_MSK" , 0x11800900006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 528},
|
|
{"STX1_INT_MSK" , 0x11800980006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 528},
|
|
{"STX0_INT_REG" , 0x1180090000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 529},
|
|
{"STX1_INT_REG" , 0x1180098000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 529},
|
|
{"STX0_INT_SYNC" , 0x11800900006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 530},
|
|
{"STX1_INT_SYNC" , 0x11800980006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 530},
|
|
{"STX0_MIN_BST" , 0x1180090000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 531},
|
|
{"STX1_MIN_BST" , 0x1180098000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 531},
|
|
{"STX0_SPI4_CAL000" , 0x1180090000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL001" , 0x1180090000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL002" , 0x1180090000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL003" , 0x1180090000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL004" , 0x1180090000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL005" , 0x1180090000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL006" , 0x1180090000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL007" , 0x1180090000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL008" , 0x1180090000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL009" , 0x1180090000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL010" , 0x1180090000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL011" , 0x1180090000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL012" , 0x1180090000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL013" , 0x1180090000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL014" , 0x1180090000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL015" , 0x1180090000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL016" , 0x1180090000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL017" , 0x1180090000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL018" , 0x1180090000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL019" , 0x1180090000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL020" , 0x11800900004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL021" , 0x11800900004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL022" , 0x11800900004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL023" , 0x11800900004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL024" , 0x11800900004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL025" , 0x11800900004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL026" , 0x11800900004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL027" , 0x11800900004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL028" , 0x11800900004E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL029" , 0x11800900004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL030" , 0x11800900004F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_CAL031" , 0x11800900004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL000" , 0x1180098000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL001" , 0x1180098000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL002" , 0x1180098000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL003" , 0x1180098000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL004" , 0x1180098000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL005" , 0x1180098000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL006" , 0x1180098000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL007" , 0x1180098000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL008" , 0x1180098000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL009" , 0x1180098000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL010" , 0x1180098000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL011" , 0x1180098000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL012" , 0x1180098000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL013" , 0x1180098000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL014" , 0x1180098000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL015" , 0x1180098000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL016" , 0x1180098000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL017" , 0x1180098000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL018" , 0x1180098000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL019" , 0x1180098000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL020" , 0x11800980004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL021" , 0x11800980004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL022" , 0x11800980004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL023" , 0x11800980004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL024" , 0x11800980004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL025" , 0x11800980004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL026" , 0x11800980004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL027" , 0x11800980004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL028" , 0x11800980004E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL029" , 0x11800980004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL030" , 0x11800980004F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX1_SPI4_CAL031" , 0x11800980004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"STX0_SPI4_DAT" , 0x1180090000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 533},
|
|
{"STX1_SPI4_DAT" , 0x1180098000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 533},
|
|
{"STX0_SPI4_STAT" , 0x1180090000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 534},
|
|
{"STX1_SPI4_STAT" , 0x1180098000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 534},
|
|
{"STX0_STAT_BYTES_HI" , 0x1180090000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 535},
|
|
{"STX1_STAT_BYTES_HI" , 0x1180098000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 535},
|
|
{"STX0_STAT_BYTES_LO" , 0x1180090000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 536},
|
|
{"STX1_STAT_BYTES_LO" , 0x1180098000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 536},
|
|
{"STX0_STAT_CTL" , 0x1180090000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 537},
|
|
{"STX1_STAT_CTL" , 0x1180098000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 537},
|
|
{"STX0_STAT_PKT_XMT" , 0x1180090000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 538},
|
|
{"STX1_STAT_PKT_XMT" , 0x1180098000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 538},
|
|
{"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 539},
|
|
{"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
|
|
{"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 541},
|
|
{"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 542},
|
|
{"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 543},
|
|
{"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 544},
|
|
{"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 546},
|
|
{"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 547},
|
|
{"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 548},
|
|
{"TRA_BIST_STATUS" , 0x11800A8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 549},
|
|
{"TRA_CTL" , 0x11800A8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 550},
|
|
{"TRA_CYCLES_SINCE" , 0x11800A8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 551},
|
|
{"TRA_FILT_ADR_ADR" , 0x11800A8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 552},
|
|
{"TRA_FILT_ADR_MSK" , 0x11800A8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 553},
|
|
{"TRA_FILT_CMD" , 0x11800A8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 554},
|
|
{"TRA_FILT_DID" , 0x11800A8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"TRA_FILT_SID" , 0x11800A8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 556},
|
|
{"TRA_INT_STATUS" , 0x11800A8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 557},
|
|
{"TRA_READ_DAT" , 0x11800A8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"TRA_TRIG0_ADR_ADR" , 0x11800A8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 559},
|
|
{"TRA_TRIG0_ADR_MSK" , 0x11800A80000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 560},
|
|
{"TRA_TRIG0_CMD" , 0x11800A8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 561},
|
|
{"TRA_TRIG0_DID" , 0x11800A8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 562},
|
|
{"TRA_TRIG0_SID" , 0x11800A8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 563},
|
|
{"TRA_TRIG1_ADR_ADR" , 0x11800A80000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 564},
|
|
{"TRA_TRIG1_ADR_MSK" , 0x11800A80000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 565},
|
|
{"TRA_TRIG1_CMD" , 0x11800A80000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 566},
|
|
{"TRA_TRIG1_DID" , 0x11800A80000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 567},
|
|
{"TRA_TRIG1_SID" , 0x11800A80000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"ZIP_CMD_BIST_RESULT" , 0x1180038000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 569},
|
|
{"ZIP_CMD_BUF" , 0x1180038000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 570},
|
|
{"ZIP_CMD_CTL" , 0x1180038000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 571},
|
|
{"ZIP_CONSTANTS" , 0x11800380000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 572},
|
|
{"ZIP_DEBUG0" , 0x1180038000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 573},
|
|
{"ZIP_ERROR" , 0x1180038000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 574},
|
|
{"ZIP_INT_MASK" , 0x1180038000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 575},
|
|
{NULL,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xxp2[] = {
|
|
/* name , bit, width, csr, type, rst un, typ un, reset, typical */
|
|
{"OVRFLW" , 0, 4, 0, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXPOP" , 4, 4, 0, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXPSH" , 8, 4, 0, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_12_63" , 12, 52, 0, "RAZ", 1, 1, 0, 0},
|
|
{"OVRFLW" , 0, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXPOP" , 4, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXPSH" , 8, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 1, "RAZ", 1, 1, 0, 0},
|
|
{"INT_LOOP" , 0, 4, 2, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EXT_LOOP" , 4, 4, 2, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 2, "RAZ", 1, 1, 0, 0},
|
|
{"BYPASS" , 0, 1, 3, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 3, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 4, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 4, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 4, 5, "RO", 0, 1, 0ull, 0},
|
|
{"PCTL" , 4, 4, 5, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 5, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 4, 6, "R/W", 0, 1, 0ull, 0},
|
|
{"PCTL" , 4, 4, 6, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 6, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 0, 1, 7, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 7, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 5, 8, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 8, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 5, 9, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 9, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL" , 0, 5, 10, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 10, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL" , 0, 5, 11, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 11, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 12, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_5_63" , 5, 59, 12, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 13, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_5_63" , 5, 59, 13, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_EN" , 0, 4, 14, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 14, "RAZ", 1, 1, 0, 0},
|
|
{"ENABLE" , 0, 1, 15, "RO", 1, 1, 0, 0},
|
|
{"STATUS" , 1, 1, 15, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_2_63" , 2, 62, 15, "RAZ", 1, 1, 0, 0},
|
|
{"MSK" , 0, 64, 16, "R/W", 0, 1, 0ull, 0},
|
|
{"POWEROK" , 0, 1, 17, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 17, "RAZ", 1, 1, 0, 0},
|
|
{"SIG" , 0, 32, 18, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 18, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 19, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_5_63" , 5, 59, 19, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 4, 20, "R/W", 0, 0, 8ull, 8ull},
|
|
{"PCTL" , 4, 4, 20, "R/W", 0, 0, 8ull, 8ull},
|
|
{"RESERVED_8_63" , 8, 56, 20, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 4, 21, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 21, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_EN" , 0, 4, 22, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 22, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 4, 23, "R/W", 0, 1, 15ull, 0},
|
|
{"PCTL" , 4, 4, 23, "R/W", 0, 1, 15ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 23, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 24, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 24, "RAZ", 1, 1, 0, 0},
|
|
{"BIST" , 0, 4, 25, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 25, "RAZ", 1, 1, 0, 0},
|
|
{"DINT" , 0, 16, 26, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 26, "RAZ", 1, 1, 0, 0},
|
|
{"FUSE" , 0, 16, 27, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_16_63" , 16, 48, 27, "RAZ", 1, 1, 0, 0},
|
|
{"GSTOP" , 0, 1, 28, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 28, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 29, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 29, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 16, 30, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 30, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 31, "RO", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 31, "RO", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 31, "RO", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 31, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 31, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 31, "RO", 0, 0, 0ull, 0ull},
|
|
{"WDOG_SUM" , 44, 1, 31, "RO", 0, 0, 0ull, 0ull},
|
|
{"TWSI" , 45, 1, 31, "RO", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 31, "RO", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 31, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 31, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 31, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 31, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 31, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 31, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 16, 32, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 32, "RAZ", 1, 1, 0, 0},
|
|
{"BITS" , 0, 32, 33, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 33, "RAZ", 1, 1, 0, 0},
|
|
{"BITS" , 0, 32, 34, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 34, "RAZ", 1, 1, 0, 0},
|
|
{"NMI" , 0, 16, 35, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 35, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 0, 2, 36, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 36, "RAZ", 1, 1, 0, 0},
|
|
{"PPDBG" , 0, 16, 37, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 37, "RAZ", 1, 1, 0, 0},
|
|
{"POKE" , 0, 64, 38, "RAZ", 1, 1, 0, 0},
|
|
{"RST0" , 0, 1, 39, "R/W", 1, 1, 0, 0},
|
|
{"RST" , 1, 15, 39, "R/W", 0, 0, 32767ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 39, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_BIST" , 0, 1, 40, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 40, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_PRST" , 0, 1, 41, "R/W", 0, 0, 1ull, 0ull},
|
|
{"NPI" , 1, 1, 41, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HOST64" , 2, 1, 41, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_3_63" , 3, 61, 41, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_RST" , 0, 1, 42, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 42, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 36, 43, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ONE_SHOT" , 36, 1, 43, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 43, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 0, 2, 44, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STATE" , 2, 2, 44, "RO", 0, 0, 0ull, 0ull},
|
|
{"LEN" , 4, 16, 44, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 20, 24, 44, "RO", 0, 0, 0ull, 0ull},
|
|
{"DSTOP" , 44, 1, 44, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GSTOPEN" , 45, 1, 44, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_46_63" , 46, 18, 44, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 17, 45, "RO", 0, 1, 0ull, 0},
|
|
{"DSEL_EXT" , 17, 1, 45, "R/W", 0, 0, 1ull, 0ull},
|
|
{"C_MUL" , 18, 5, 45, "RO", 1, 1, 0, 0},
|
|
{"CCLK_DIV2" , 23, 1, 45, "RO", 1, 1, 0, 0},
|
|
{"DCLK_MUL2" , 24, 1, 45, "RO", 1, 1, 0, 0},
|
|
{"D_MUL" , 25, 4, 45, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 45, "RAZ", 1, 1, 0, 0},
|
|
{"PDF" , 0, 16, 46, "RO", 0, 0, 0ull, 0ull},
|
|
{"RDF" , 16, 16, 46, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 46, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"P1_BRF" , 0, 8, 47, "RO", 0, 0, 0ull, 0ull},
|
|
{"P0_BRF" , 8, 8, 47, "RO", 0, 0, 0ull, 0ull},
|
|
{"P1_BWB" , 16, 1, 47, "RO", 0, 0, 0ull, 0ull},
|
|
{"P0_BWB" , 17, 1, 47, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRF" , 18, 1, 47, "RO", 0, 0, 0ull, 0ull},
|
|
{"DRF" , 19, 1, 47, "RO", 0, 0, 0ull, 0ull},
|
|
{"GFU" , 20, 1, 47, "RO", 0, 0, 0ull, 0ull},
|
|
{"IFU" , 21, 1, 47, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRQ" , 22, 1, 47, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 47, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SARB" , 0, 1, 48, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 48, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 20, 49, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_63" , 20, 44, 49, "RAZ", 1, 1, 0, 0},
|
|
{"SIZE" , 0, 9, 50, "R/W", 0, 1, 3ull, 0},
|
|
{"POOL" , 9, 3, 50, "R/W", 0, 1, 0ull, 0},
|
|
{"DWBCNT" , 12, 8, 50, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_20_63" , 20, 44, 50, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_4" , 0, 5, 51, "RAZ", 1, 1, 0, 0},
|
|
{"RDPTR" , 5, 31, 51, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 51, "RAZ", 1, 1, 0, 0},
|
|
{"CP2ECCENA" , 0, 1, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2SBE" , 1, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CP2DBE" , 2, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CP2SBINA" , 3, 1, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2DBINA" , 4, 1, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2SYN" , 5, 8, 52, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTEECCENA" , 13, 1, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DTESBE" , 14, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTEDBE" , 15, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTESBINA" , 16, 1, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DTEDBINA" , 17, 1, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DTESYN" , 18, 7, 52, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTEPARENA" , 25, 1, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DTEPERR" , 26, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTEPINA" , 27, 1, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2PARENA" , 28, 1, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2PERR" , 29, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CP2PINA" , 30, 1, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DBLOVF" , 31, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DBLINA" , 32, 1, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_33_63" , 33, 31, 52, "RAZ", 1, 1, 0, 0},
|
|
{"ENA_P1" , 0, 1, 53, "R/W", 0, 0, 1ull, 1ull},
|
|
{"ENA_P0" , 1, 1, 53, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_2" , 2, 1, 53, "RAZ", 1, 1, 0, 0},
|
|
{"MTYPE" , 3, 1, 53, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SIL_LAT" , 4, 2, 53, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RW_DLY" , 6, 4, 53, "R/W", 0, 0, 1ull, 1ull},
|
|
{"WR_DLY" , 10, 4, 53, "R/W", 0, 0, 2ull, 2ull},
|
|
{"FPRCH" , 14, 2, 53, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BPRCH" , 16, 2, 53, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BLEN" , 18, 1, 53, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PBUNK" , 19, 3, 53, "R/W", 0, 0, 2ull, 2ull},
|
|
{"R2R_PBUNK" , 22, 1, 53, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INIT_P1" , 23, 1, 53, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INIT_P0" , 24, 1, 53, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BUNK_INIT" , 25, 2, 53, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_27_63" , 27, 37, 53, "RAZ", 1, 1, 0, 0},
|
|
{"REF_INT" , 0, 4, 54, "R/W", 0, 0, 3ull, 3ull},
|
|
{"TSKW" , 4, 2, 54, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 54, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TRL" , 8, 4, 54, "R/W", 0, 0, 6ull, 6ull},
|
|
{"TWL" , 12, 4, 54, "R/W", 0, 0, 7ull, 7ull},
|
|
{"TRC" , 16, 4, 54, "R/W", 0, 0, 6ull, 6ull},
|
|
{"TMRSC" , 20, 3, 54, "R/W", 0, 0, 6ull, 6ull},
|
|
{"MRS_ENA" , 23, 1, 54, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AREF_ENA" , 24, 1, 54, "R/W", 0, 0, 0ull, 0ull},
|
|
{"REF_INTLO" , 25, 9, 54, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 54, "RAZ", 1, 1, 0, 0},
|
|
{"FCRAM2P" , 0, 1, 55, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAXBNK" , 1, 1, 55, "R/W", 0, 0, 1ull, 1ull},
|
|
{"UA_START" , 2, 2, 55, "R/W", 0, 0, 1ull, 1ull},
|
|
{"REFSHORT" , 4, 1, 55, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRFC" , 5, 5, 55, "R/W", 0, 0, 9ull, 9ull},
|
|
{"SILRST" , 10, 1, 55, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DTECLKDIS" , 11, 1, 55, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 55, "RAZ", 1, 1, 0, 0},
|
|
{"MADDR" , 0, 24, 56, "RO", 0, 0, 0ull, 0ull},
|
|
{"BNUM" , 24, 3, 56, "RO", 0, 0, 0ull, 0ull},
|
|
{"PNUM" , 27, 1, 56, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSRC" , 28, 2, 56, "RO", 0, 0, 0ull, 0ull},
|
|
{"FDST" , 30, 9, 56, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_39_63" , 39, 25, 56, "RAZ", 1, 1, 0, 0},
|
|
{"MRS" , 0, 15, 57, "R/W", 0, 0, 66ull, 66ull},
|
|
{"RESERVED_15_15" , 15, 1, 57, "RAZ", 1, 1, 0, 0},
|
|
{"EMRS" , 16, 15, 57, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_31_31" , 31, 1, 57, "RAZ", 1, 1, 0, 0},
|
|
{"EMRS2" , 32, 15, 57, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_47_63" , 47, 17, 57, "RAZ", 1, 1, 0, 0},
|
|
{"MRSDAT" , 0, 23, 58, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_23_63" , 23, 41, 58, "RAZ", 1, 1, 0, 0},
|
|
{"IMODE" , 0, 1, 59, "R/W", 0, 0, 1ull, 1ull},
|
|
{"QMODE" , 1, 1, 59, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PMODE" , 2, 1, 59, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DTMODE" , 3, 1, 59, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DCMODE" , 4, 1, 59, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SBDLCK" , 5, 1, 59, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SBDNUM" , 6, 4, 59, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 59, "RAZ", 1, 1, 0, 0},
|
|
{"SBD0" , 0, 64, 60, "RO", 1, 1, 0, 0},
|
|
{"SBD1" , 0, 64, 61, "RO", 1, 1, 0, 0},
|
|
{"SBD2" , 0, 64, 62, "RO", 1, 1, 0, 0},
|
|
{"SBD3" , 0, 64, 63, "RO", 1, 1, 0, 0},
|
|
{"FDR" , 0, 1, 64, "RO", 0, 0, 0ull, 0ull},
|
|
{"FFR" , 1, 1, 64, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPF1" , 2, 1, 64, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPF0" , 3, 1, 64, "RO", 0, 0, 0ull, 0ull},
|
|
{"FRD" , 4, 1, 64, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 64, "RAZ", 1, 1, 0, 0},
|
|
{"MEM0_ERR" , 0, 7, 65, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM1_ERR" , 7, 7, 65, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 14, 1, 65, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USE_STT" , 15, 1, 65, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USE_LDT" , 16, 1, 65, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 17, 1, 65, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 65, "RAZ", 1, 1, 0, 0},
|
|
{"FPF_RD" , 0, 11, 66, "R/W", 0, 0, 64ull, 0ull},
|
|
{"FPF_WR" , 11, 11, 66, "R/W", 0, 0, 196ull, 0ull},
|
|
{"RESERVED_22_63" , 22, 42, 66, "RAZ", 1, 1, 0, 0},
|
|
{"FPF_SIZ" , 0, 11, 67, "R/W", 0, 0, 256ull, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 67, "RAZ", 1, 1, 0, 0},
|
|
{"FPF_RD" , 0, 12, 68, "R/W", 0, 0, 64ull, 0ull},
|
|
{"FPF_WR" , 12, 12, 68, "R/W", 0, 0, 196ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 68, "RAZ", 1, 1, 0, 0},
|
|
{"FPF_SIZ" , 0, 12, 69, "R/W", 0, 0, 256ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 69, "RAZ", 1, 1, 0, 0},
|
|
{"FED0_SBE" , 0, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED0_DBE" , 1, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED1_SBE" , 2, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED1_DBE" , 3, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_UND" , 4, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_COFF" , 5, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_PERR" , 6, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_UND" , 7, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_COFF" , 8, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_PERR" , 9, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_UND" , 10, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_COFF" , 11, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_PERR" , 12, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_UND" , 13, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_COFF" , 14, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_PERR" , 15, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_UND" , 16, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_COFF" , 17, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_PERR" , 18, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_UND" , 19, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_COFF" , 20, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_PERR" , 21, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_UND" , 22, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_COFF" , 23, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_PERR" , 24, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_UND" , 25, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_COFF" , 26, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_PERR" , 27, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 70, "RAZ", 1, 1, 0, 0},
|
|
{"FED0_SBE" , 0, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED0_DBE" , 1, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED1_SBE" , 2, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED1_DBE" , 3, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_UND" , 4, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_COFF" , 5, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_PERR" , 6, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_UND" , 7, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_COFF" , 8, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_PERR" , 9, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_UND" , 10, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_COFF" , 11, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_PERR" , 12, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_UND" , 13, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_COFF" , 14, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_PERR" , 15, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_UND" , 16, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_COFF" , 17, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_PERR" , 18, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_UND" , 19, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_COFF" , 20, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_PERR" , 21, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_UND" , 22, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_COFF" , 23, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_PERR" , 24, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_UND" , 25, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_COFF" , 26, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_PERR" , 27, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 71, "RAZ", 1, 1, 0, 0},
|
|
{"QUE_SIZ" , 0, 29, 72, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 72, "RAZ", 1, 1, 0, 0},
|
|
{"PG_NUM" , 0, 25, 73, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 73, "RAZ", 1, 1, 0, 0},
|
|
{"ACT_INDX" , 0, 26, 74, "RO", 0, 1, 0ull, 0},
|
|
{"ACT_QUE" , 26, 3, 74, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 74, "RAZ", 0, 0, 0ull, 7ull},
|
|
{"EXP_INDX" , 0, 26, 75, "RO", 0, 1, 0ull, 0},
|
|
{"EXP_QUE" , 26, 3, 75, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 75, "RAZ", 0, 0, 0ull, 7ull},
|
|
{"CTL" , 0, 16, 76, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 76, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 32, 77, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 77, "RAZ", 1, 1, 0, 0},
|
|
{"OUT_COL" , 0, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NCB_OVR" , 1, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OUT_OVR" , 2, 16, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_21" , 18, 4, 78, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LOSTSTAT" , 22, 4, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"STATOVR" , 26, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INB_NXA" , 27, 4, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 78, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 10, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 79, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 1, 80, "RO", 1, 1, 0, 0},
|
|
{"EN" , 1, 1, 80, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_2_63" , 2, 62, 80, "RAZ", 1, 1, 0, 0},
|
|
{"PRT" , 0, 6, 81, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 81, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 82, "R/W", 0, 1, 0ull, 0},
|
|
{"SPEED" , 1, 1, 82, "R/W", 0, 1, 1ull, 0},
|
|
{"DUPLEX" , 2, 1, 82, "R/W", 0, 1, 1ull, 0},
|
|
{"SLOTTIME" , 3, 1, 82, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 82, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 64, 83, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 84, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 85, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 86, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 87, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 88, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 0, 8, 89, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 89, "RAZ", 1, 1, 0, 0},
|
|
{"BCST" , 0, 1, 90, "R/W", 0, 1, 1ull, 0},
|
|
{"MCST" , 1, 2, 90, "R/W", 0, 1, 0ull, 0},
|
|
{"CAM_MODE" , 3, 1, 90, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 90, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 5, 91, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_5_63" , 5, 59, 91, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CAREXT" , 1, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MAXERR" , 2, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"JABBER" , 3, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCSERR" , 4, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"ALNERR" , 5, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"LENERR" , 6, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RCVERR" , 7, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SKPERR" , 8, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"NIBERR" , 9, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_10_63" , 10, 54, 92, "RAZ", 1, 1, 0, 0},
|
|
{"PRE_CHK" , 0, 1, 93, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PRE_STRP" , 1, 1, 93, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_DRP" , 2, 1, 93, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_BCK" , 3, 1, 93, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_MCST" , 4, 1, 93, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_SMAC" , 5, 1, 93, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PRE_FREE" , 6, 1, 93, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VLAN_LEN" , 7, 1, 93, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 93, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 16, 94, "R/W", 0, 0, 1536ull, 1536ull},
|
|
{"RESERVED_16_63" , 16, 48, 94, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 16, 95, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_16_63" , 16, 48, 95, "RAZ", 1, 1, 0, 0},
|
|
{"IFG" , 0, 4, 96, "R/W", 0, 0, 12ull, 12ull},
|
|
{"RESERVED_4_63" , 4, 60, 96, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAREXT" , 1, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 2, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"JABBER" , 3, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ALNERR" , 5, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 6, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RCVERR" , 7, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NIBERR" , 9, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OVRERR" , 10, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHY_LINK" , 16, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHY_SPD" , 17, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHY_DUPX" , 18, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 97, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CAREXT" , 1, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 2, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"JABBER" , 3, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ALNERR" , 5, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 6, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RCVERR" , 7, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NIBERR" , 9, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OVRERR" , 10, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PHY_LINK" , 16, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PHY_SPD" , 17, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PHY_DUPX" , 18, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 98, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 99, "R/W", 0, 0, 10240ull, 10240ull},
|
|
{"RESERVED_16_63" , 16, 48, 99, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 1, 100, "RO", 0, 1, 0ull, 0},
|
|
{"SPEED" , 1, 2, 100, "RO", 0, 1, 0ull, 0},
|
|
{"DUPLEX" , 3, 1, 100, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 100, "RAZ", 1, 1, 0, 0},
|
|
{"RD_CLR" , 0, 1, 101, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 101, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 102, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 102, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 103, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 103, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 104, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 104, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 105, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 105, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 106, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 106, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 107, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 107, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 108, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 108, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 109, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 109, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 110, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 110, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 7, 111, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 111, "RAZ", 1, 1, 0, 0},
|
|
{"FCSSEL" , 8, 1, 111, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 111, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 112, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_6_63" , 6, 58, 112, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 113, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_6_63" , 6, 58, 113, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 9, 114, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_9_63" , 9, 55, 114, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 16, 115, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 115, "RAZ", 1, 1, 0, 0},
|
|
{"DPRT" , 0, 4, 116, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 116, "RAZ", 1, 1, 0, 0},
|
|
{"PRTS" , 0, 3, 117, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_3_63" , 3, 61, 117, "RAZ", 1, 1, 0, 0},
|
|
{"SMAC" , 0, 48, 118, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 118, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 119, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP" , 16, 1, 119, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 119, "RAZ", 1, 1, 0, 0},
|
|
{"PREAMBLE" , 0, 1, 120, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PAD" , 1, 1, 120, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCS" , 2, 1, 120, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FORCE_FCS" , 3, 1, 120, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 120, "RAZ", 1, 1, 0, 0},
|
|
{"BURST" , 0, 16, 121, "R/W", 0, 0, 8192ull, 8192ull},
|
|
{"RESERVED_16_63" , 16, 48, 121, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_CNT" , 0, 6, 122, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_63" , 6, 58, 122, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL_EN" , 0, 1, 123, "R/W", 0, 0, 1ull, 1ull},
|
|
{"XSDEF_EN" , 1, 1, 123, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 123, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_SIZE" , 0, 8, 124, "R/W", 0, 0, 59ull, 59ull},
|
|
{"RESERVED_8_63" , 8, 56, 124, "RAZ", 1, 1, 0, 0},
|
|
{"INTERVAL" , 0, 16, 125, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 125, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 126, "R/W", 0, 1, 96ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 126, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 127, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_16_63" , 16, 48, 127, "RAZ", 1, 1, 0, 0},
|
|
{"SEND" , 0, 1, 128, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 128, "RAZ", 1, 1, 0, 0},
|
|
{"SLOT" , 0, 10, 129, "R/W", 0, 0, 512ull, 512ull},
|
|
{"RESERVED_10_63" , 10, 54, 129, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 130, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 130, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL" , 0, 32, 131, "RC/W", 0, 1, 0ull, 0},
|
|
{"XSDEF" , 32, 32, 131, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCOL" , 0, 32, 132, "RC/W", 0, 1, 0ull, 0},
|
|
{"SCOL" , 32, 32, 132, "RC/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 133, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 133, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 134, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 134, "RAZ", 1, 1, 0, 0},
|
|
{"HIST0" , 0, 32, 135, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST1" , 32, 32, 135, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST2" , 0, 32, 136, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST3" , 32, 32, 136, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST4" , 0, 32, 137, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST5" , 32, 32, 137, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST6" , 0, 32, 138, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST7" , 32, 32, 138, "RC/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 0, 32, 139, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 32, 32, 139, "RC/W", 0, 1, 0ull, 0},
|
|
{"CTL" , 0, 32, 140, "RC/W", 0, 1, 0ull, 0},
|
|
{"UNDFLW" , 32, 32, 140, "RC/W", 0, 1, 0ull, 0},
|
|
{"RD_CLR" , 0, 1, 141, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 141, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 9, 142, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_9_63" , 9, 55, 142, "RAZ", 1, 1, 0, 0},
|
|
{"BP" , 0, 4, 143, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 143, "RAZ", 1, 1, 0, 0},
|
|
{"LIMIT" , 0, 5, 144, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_5_63" , 5, 59, 144, "RAZ", 1, 1, 0, 0},
|
|
{"CORRUPT" , 0, 4, 145, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_4_63" , 4, 60, 145, "RAZ", 1, 1, 0, 0},
|
|
{"IFG1" , 0, 4, 146, "R/W", 0, 1, 8ull, 0},
|
|
{"IFG2" , 4, 4, 146, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 146, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 147, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NCB_NXA" , 1, 1, 147, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 4, 147, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 147, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 4, 147, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 4, 147, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 147, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 148, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NCB_NXA" , 1, 1, 148, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 4, 148, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 148, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 4, 148, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 4, 148, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 148, "RAZ", 1, 1, 0, 0},
|
|
{"JAM" , 0, 8, 149, "R/W", 0, 1, 238ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 149, "RAZ", 1, 1, 0, 0},
|
|
{"LFSR" , 0, 16, 150, "R/W", 0, 1, 65535ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 150, "RAZ", 1, 1, 0, 0},
|
|
{"IGN_FULL" , 0, 4, 151, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP" , 4, 4, 151, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EN" , 8, 4, 151, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 151, "RAZ", 1, 1, 0, 0},
|
|
{"DMAC" , 0, 48, 152, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
|
|
{"RESERVED_48_63" , 48, 16, 152, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 153, "R/W", 0, 0, 34824ull, 34824ull},
|
|
{"RESERVED_16_63" , 16, 48, 153, "RAZ", 1, 1, 0, 0},
|
|
{"PRTS" , 0, 5, 154, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 154, "RAZ", 1, 1, 0, 0},
|
|
{"CONT_PKT" , 0, 1, 155, "R/W", 0, 1, 0ull, 0},
|
|
{"TPA_CLR" , 1, 1, 155, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 155, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX1" , 0, 8, 156, "R/W", 0, 1, 8ull, 0},
|
|
{"MAX2" , 8, 8, 156, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 156, "RAZ", 1, 1, 0, 0},
|
|
{"THRESH" , 0, 6, 157, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 157, "RAZ", 1, 1, 0, 0},
|
|
{"TX_OE" , 0, 1, 158, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RX_XOR" , 1, 1, 158, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_EN" , 2, 1, 158, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_TYPE" , 3, 1, 158, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_CNT" , 4, 4, 158, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_SEL" , 8, 4, 158, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 158, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 159, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 159, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 160, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 160, "RAZ", 1, 1, 0, 0},
|
|
{"CLR" , 0, 16, 161, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 161, "RAZ", 1, 1, 0, 0},
|
|
{"SET" , 0, 16, 162, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 162, "RAZ", 1, 1, 0, 0},
|
|
{"ICD" , 0, 1, 163, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBD" , 1, 1, 163, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRP1" , 2, 1, 163, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRP0" , 3, 1, 163, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRN1" , 4, 1, 163, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRN0" , 5, 1, 163, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBRQ1" , 6, 1, 163, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBRQ0" , 7, 1, 163, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNRT" , 8, 1, 163, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBR1" , 9, 1, 163, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBR0" , 10, 1, 163, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBDR1" , 11, 1, 163, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBDR0" , 12, 1, 163, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNR0" , 13, 1, 163, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNR1" , 14, 1, 163, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICR1" , 15, 1, 163, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICR0" , 16, 1, 163, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNRCB" , 17, 1, 163, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 163, "RAZ", 1, 1, 0, 0},
|
|
{"FAU_END" , 0, 1, 164, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB_ENB" , 1, 1, 164, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PKO_ENB" , 2, 1, 164, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INB_MAT" , 3, 1, 164, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OUTB_MAT" , 4, 1, 164, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 164, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 165, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 165, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 165, "RAZ", 1, 1, 0, 0},
|
|
{"TOUT_VAL" , 0, 12, 166, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TOUT_ENB" , 12, 1, 166, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 166, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 167, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 167, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 167, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 8, 168, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 8, 9, 168, "R/W", 0, 1, 0ull, 0},
|
|
{"OPC" , 17, 4, 168, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 21, 8, 168, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 168, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 8, 169, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 8, 9, 169, "R/W", 0, 1, 0ull, 0},
|
|
{"OPC" , 17, 4, 169, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 21, 8, 169, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 169, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 170, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 171, "R/W", 0, 1, 0ull, 0},
|
|
{"NP_SOP" , 0, 1, 172, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NP_EOP" , 1, 1, 172, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_SOP" , 2, 1, 172, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_EOP" , 3, 1, 172, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 172, "RAZ", 1, 1, 0, 0},
|
|
{"NP_SOP" , 0, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NP_EOP" , 1, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_SOP" , 2, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_EOP" , 3, 1, 173, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 173, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 174, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 174, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 174, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 175, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 175, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 175, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 176, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 176, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 176, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 9, 177, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 9, 8, 177, "R/W", 0, 1, 0ull, 0},
|
|
{"EOT" , 17, 1, 177, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 18, 8, 177, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_26_63" , 26, 38, 177, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 9, 178, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 9, 8, 178, "R/W", 0, 1, 0ull, 0},
|
|
{"EOT" , 17, 1, 178, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 18, 8, 178, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_26_63" , 26, 38, 178, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 179, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 180, "R/W", 0, 1, 0ull, 0},
|
|
{"CNT_VAL" , 0, 15, 181, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 181, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 181, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 182, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 182, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 182, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 183, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 183, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 183, "RAZ", 1, 1, 0, 0},
|
|
{"PORT" , 0, 6, 184, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 184, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP_SZ" , 0, 6, 185, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 185, "RAZ", 1, 1, 0, 0},
|
|
{"BACK" , 0, 4, 186, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 186, "RAZ", 1, 1, 0, 0},
|
|
{"BACK" , 0, 4, 187, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 187, "RAZ", 1, 1, 0, 0},
|
|
{"PWP" , 0, 1, 188, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_NEW" , 1, 1, 188, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_OLD" , 2, 1, 188, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRC_OFF" , 3, 1, 188, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ0" , 4, 1, 188, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ1" , 5, 1, 188, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM_WORD" , 6, 1, 188, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM0" , 7, 1, 188, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM1" , 8, 1, 188, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM2" , 9, 1, 188, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM3" , 10, 1, 188, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPQ_PBE0" , 11, 1, 188, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPQ_PBE1" , 12, 1, 188, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_POW" , 13, 1, 188, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_WP1" , 14, 1, 188, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_WQED" , 15, 1, 188, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 188, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_ENB" , 0, 36, 189, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 189, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_CNT" , 0, 64, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_EN" , 0, 1, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OPC_MODE" , 1, 2, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PBP_EN" , 3, 1, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WQE_LEND" , 4, 1, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKT_LEND" , 5, 1, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NADDBUF" , 6, 1, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDPKT" , 7, 1, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 8, 1, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 191, "RAZ", 1, 1, 0, 0},
|
|
{"PRC_PAR0" , 0, 1, 192, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR1" , 1, 1, 192, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR2" , 2, 1, 192, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR3" , 3, 1, 192, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_SUB" , 4, 1, 192, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 192, "RAZ", 1, 1, 0, 0},
|
|
{"PRC_PAR0" , 0, 1, 193, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR1" , 1, 1, 193, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR2" , 2, 1, 193, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR3" , 3, 1, 193, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP_SUB" , 4, 1, 193, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 193, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP_SZ" , 0, 6, 194, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 194, "RAZ", 1, 1, 0, 0},
|
|
{"MB_SIZE" , 0, 12, 195, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_12_63" , 12, 52, 195, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 17, 196, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_ENB" , 17, 1, 196, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 196, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 25, 197, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 197, "RAZ", 1, 1, 0, 0},
|
|
{"WQE_PCNT" , 0, 7, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_PCNT" , 7, 7, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"PFIF_CNT" , 14, 3, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"WQEV_CNT" , 17, 1, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTV_CNT" , 18, 1, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 198, "RAZ", 1, 1, 0, 0},
|
|
{"PASS" , 0, 32, 199, "R/W", 0, 1, 0ull, 0},
|
|
{"DROP" , 32, 32, 199, "R/W", 0, 1, 0ull, 0},
|
|
{"Q0_PCNT" , 0, 32, 200, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 200, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_ENB" , 0, 36, 201, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AVG_DLY" , 36, 14, 201, "R/W", 0, 1, 0ull, 0},
|
|
{"PRB_DLY" , 50, 14, 201, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRB_CON" , 0, 32, 202, "R/W", 0, 1, 0ull, 0},
|
|
{"AVG_CON" , 32, 8, 202, "R/W", 0, 1, 0ull, 0},
|
|
{"NEW_CON" , 40, 8, 202, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_PCNT" , 48, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 202, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 25, 203, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT" , 25, 6, 203, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 203, "RAZ", 1, 1, 0, 0},
|
|
{"PORT_BIT" , 0, 32, 204, "R/W", 0, 0, 4294967295ull, 4294967295ull},
|
|
{"RESERVED_32_63" , 32, 32, 204, "RAZ", 1, 1, 0, 0},
|
|
{"WQE_POOL" , 0, 3, 205, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_3_63" , 3, 61, 205, "RAZ", 1, 1, 0, 0},
|
|
{"MEM0" , 0, 1, 206, "RO", 0, 0, 0ull, 0ull},
|
|
{"MEM1" , 1, 1, 206, "RO", 0, 0, 0ull, 0ull},
|
|
{"RRC" , 2, 1, 206, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 206, "RAZ", 1, 1, 0, 0},
|
|
{"MEM0_ERR" , 0, 7, 207, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM1_ERR" , 7, 7, 207, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 207, "RAZ", 1, 1, 0, 0},
|
|
{"KED0_SBE" , 0, 1, 208, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KED0_DBE" , 1, 1, 208, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KED1_SBE" , 2, 1, 208, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KED1_DBE" , 3, 1, 208, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 208, "RAZ", 1, 1, 0, 0},
|
|
{"KED0_SBE" , 0, 1, 209, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KED0_DBE" , 1, 1, 209, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KED1_SBE" , 2, 1, 209, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KED1_DBE" , 3, 1, 209, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 209, "RAZ", 1, 1, 0, 0},
|
|
{"WLB_DAT" , 0, 4, 210, "RO", 0, 0, 0ull, 0ull},
|
|
{"STIN_MSK" , 4, 1, 210, "RO", 0, 0, 0ull, 0ull},
|
|
{"DT" , 5, 1, 210, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTCNT" , 6, 13, 210, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 210, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"L2T" , 0, 9, 211, "RO", 0, 0, 0ull, 0ull},
|
|
{"VAB_VWCF" , 9, 1, 211, "RO", 0, 0, 0ull, 0ull},
|
|
{"LRF" , 10, 2, 211, "RO", 0, 0, 0ull, 0ull},
|
|
{"VWDF" , 12, 4, 211, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 211, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XRDDAT" , 0, 1, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"XRDMSK" , 1, 1, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"PICBST" , 2, 1, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPCBST" , 3, 1, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"RHDF" , 4, 4, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"RMDF" , 8, 4, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRB" , 12, 4, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 212, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LRF_ARB_MODE" , 0, 1, 213, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RFB_ARB_MODE" , 1, 1, 213, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RSP_ARB_MODE" , 2, 1, 213, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MWF_CRD" , 3, 4, 213, "R/W", 0, 0, 2ull, 2ull},
|
|
{"IDXALIAS" , 7, 1, 213, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPEN" , 8, 1, 213, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FPEMPTY" , 9, 1, 213, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FPEXP" , 10, 4, 213, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 213, "RAZ", 1, 1, 0, 0},
|
|
{"L2T" , 0, 1, 214, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2D" , 1, 1, 214, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FINV" , 2, 1, 214, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SET" , 3, 3, 214, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PPNUM" , 6, 4, 214, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LFB_DMP" , 10, 1, 214, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LFB_ENUM" , 11, 4, 214, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 214, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DT_TAG" , 0, 29, 215, "RO", 0, 0, 0ull, 0ull},
|
|
{"DT_VLD" , 29, 1, 215, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_30" , 30, 1, 215, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DTENA" , 31, 1, 215, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 215, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_ENA" , 0, 1, 216, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_3" , 1, 3, 216, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_BASE" , 4, 27, 216, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 216, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_OFFSET" , 0, 10, 217, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 217, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VLD" , 0, 1, 218, "RO", 0, 0, 0ull, 0ull},
|
|
{"CMD" , 1, 4, 218, "RO", 0, 0, 0ull, 0ull},
|
|
{"SID" , 5, 9, 218, "RO", 0, 0, 0ull, 0ull},
|
|
{"VABNUM" , 14, 4, 218, "RO", 0, 0, 0ull, 0ull},
|
|
{"SET" , 18, 3, 218, "RO", 0, 0, 0ull, 0ull},
|
|
{"IHD" , 21, 1, 218, "RO", 0, 0, 0ull, 0ull},
|
|
{"ITL" , 22, 1, 218, "RO", 0, 0, 0ull, 0ull},
|
|
{"INXT" , 23, 4, 218, "RO", 0, 0, 0ull, 0ull},
|
|
{"VAM" , 27, 1, 218, "RO", 0, 0, 0ull, 0ull},
|
|
{"STCFL" , 28, 1, 218, "RO", 0, 0, 0ull, 0ull},
|
|
{"STINV" , 29, 1, 218, "RO", 0, 0, 0ull, 0ull},
|
|
{"STPND" , 30, 1, 218, "RO", 0, 0, 0ull, 0ull},
|
|
{"STCPND" , 31, 1, 218, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 218, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VLD" , 0, 1, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTPRB" , 1, 1, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRBRTY" , 2, 1, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTMFL" , 3, 1, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTVTM" , 4, 1, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTRSC" , 5, 1, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTRSP" , 6, 1, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTDT" , 7, 1, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTRDA" , 8, 1, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTM" , 9, 1, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWRM" , 10, 1, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWHF" , 11, 1, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWHP" , 12, 1, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTDQ" , 13, 1, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTDW" , 14, 1, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTRSP" , 15, 1, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"BID" , 16, 2, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"DSGOING" , 18, 1, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 219, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_IDX" , 0, 10, 220, "RO", 0, 0, 0ull, 0ull},
|
|
{"LFB_TAG" , 10, 17, 220, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_63" , 27, 37, 220, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_HWM" , 0, 4, 221, "R/W", 0, 0, 15ull, 15ull},
|
|
{"STPARTDIS" , 4, 1, 221, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 221, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PFCNT0" , 0, 36, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 222, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT0SEL" , 0, 6, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0CLR" , 6, 1, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0ENA" , 7, 1, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1SEL" , 8, 6, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1CLR" , 14, 1, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1ENA" , 15, 1, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2SEL" , 16, 6, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2CLR" , 22, 1, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2ENA" , 23, 1, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3SEL" , 24, 6, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3CLR" , 30, 1, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3ENA" , 31, 1, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0RDCLR" , 32, 1, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1RDCLR" , 33, 1, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2RDCLR" , 34, 1, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3RDCLR" , 35, 1, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 223, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK0" , 0, 8, 224, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK1" , 8, 8, 224, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK2" , 16, 8, 224, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK3" , 24, 8, 224, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 224, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK4" , 0, 8, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK5" , 8, 8, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK6" , 16, 8, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK7" , 24, 8, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 225, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK8" , 0, 8, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK9" , 8, 8, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK10" , 16, 8, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK11" , 24, 8, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 226, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK12" , 0, 8, 227, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK13" , 8, 8, 227, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK14" , 16, 8, 227, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK15" , 24, 8, 227, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 227, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSKIOB" , 0, 8, 228, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 228, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q0STAT" , 0, 34, 229, "RO", 0, 0, 0ull, 0ull},
|
|
{"FTL" , 34, 1, 229, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_35_63" , 35, 29, 229, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q1STAT" , 0, 34, 230, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 230, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q2STAT" , 0, 34, 231, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 231, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q3STAT" , 0, 34, 232, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 232, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 0, 1, 233, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_INTENA" , 1, 1, 233, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DED_INTENA" , 2, 1, 233, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 3, 1, 233, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 4, 1, 233, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BMHCLSEL" , 5, 1, 233, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 233, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 0, 11, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSET" , 11, 3, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"FOWMSK" , 14, 4, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 234, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW0" , 0, 10, 235, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW1" , 10, 10, 235, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 235, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW2" , 0, 10, 236, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW3" , 10, 10, 236, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 236, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q0FUS" , 0, 34, 237, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 237, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q1FUS" , 0, 34, 238, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 238, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q2FUS" , 0, 34, 239, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 239, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q3FUS" , 0, 34, 240, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRIP_512K" , 34, 1, 240, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRIP_256K" , 35, 1, 240, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 240, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 0, 1, 241, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_INTENA" , 1, 1, 241, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DED_INTENA" , 2, 1, 241, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 3, 1, 241, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 4, 1, 241, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FSYN" , 5, 6, 241, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 11, 10, 241, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSET" , 21, 3, 241, "RO", 0, 0, 0ull, 0ull},
|
|
{"LCKERR" , 24, 1, 241, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK_INTENA" , 25, 1, 241, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LCKERR2" , 26, 1, 241, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK_INTENA2" , 27, 1, 241, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_28_63" , 28, 36, 241, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RATE" , 0, 8, 242, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_8_63" , 8, 56, 242, "RAZ", 1, 1, 0, 0},
|
|
{"PHASE" , 0, 7, 243, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_7_63" , 7, 57, 243, "RAZ", 1, 1, 0, 0},
|
|
{"RATE" , 0, 16, 244, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 244, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_EN" , 0, 1, 245, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 245, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 246, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 246, "RAZ", 1, 1, 0, 0},
|
|
{"POLARITY" , 0, 1, 247, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 247, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_EN" , 0, 8, 248, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 248, "RAZ", 1, 1, 0, 0},
|
|
{"FORMAT" , 0, 4, 249, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 249, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 6, 250, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 250, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 6, 251, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 251, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 32, 252, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 252, "RAZ", 1, 1, 0, 0},
|
|
{"CLR" , 0, 32, 253, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 253, "RAZ", 1, 1, 0, 0},
|
|
{"SET" , 0, 32, 254, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 254, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL_DAT" , 0, 4, 255, "R/W", 0, 1, 0ull, 0},
|
|
{"PCTL_CMD" , 4, 4, 255, "R/W", 0, 1, 0ull, 0},
|
|
{"PCTL_CLK" , 8, 4, 255, "R/W", 0, 1, 0ull, 0},
|
|
{"PCTL_CSR" , 12, 4, 255, "R/W", 0, 1, 15ull, 0},
|
|
{"NCTL_DAT" , 16, 4, 255, "R/W", 0, 1, 0ull, 0},
|
|
{"NCTL_CMD" , 20, 4, 255, "R/W", 0, 1, 0ull, 0},
|
|
{"NCTL_CLK" , 24, 4, 255, "R/W", 0, 1, 0ull, 0},
|
|
{"NCTL_CSR" , 28, 4, 255, "R/W", 0, 1, 15ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 255, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DIC" , 0, 2, 256, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QS_DIC" , 2, 2, 256, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TSKW" , 4, 2, 256, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SIL_LAT" , 6, 2, 256, "R/W", 0, 0, 1ull, 1ull},
|
|
{"BPRCH" , 8, 1, 256, "R/W", 0, 1, 0ull, 0},
|
|
{"FPRCH2" , 9, 1, 256, "R/W", 0, 0, 0ull, 1ull},
|
|
{"MODE128B" , 10, 1, 256, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SET_ZERO" , 11, 1, 256, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INORDER_MRF" , 12, 1, 256, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INORDER_MWF" , 13, 1, 256, "R/W", 0, 0, 0ull, 0ull},
|
|
{"R2R_SLOT" , 14, 1, 256, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RDIMM_ENA" , 15, 1, 256, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_17" , 16, 2, 256, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX_WRITE_BATCH" , 18, 4, 256, "R/W", 0, 0, 8ull, 8ull},
|
|
{"XOR_BANK" , 22, 1, 256, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SLOW_SCF" , 23, 1, 256, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DDR__PCTL" , 24, 4, 256, "RO", 1, 1, 0, 0},
|
|
{"DDR__NCTL" , 28, 4, 256, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 256, "RAZ", 1, 1, 0, 0},
|
|
{"DCLKCNT_HI" , 0, 32, 257, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 257, "RAZ", 1, 1, 0, 0},
|
|
{"DCLKCNT_LO" , 0, 32, 258, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 258, "RAZ", 1, 1, 0, 0},
|
|
{"DDR2" , 0, 1, 259, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RDQS" , 1, 1, 259, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLL90_BYP" , 2, 1, 259, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLL90_VLU" , 3, 5, 259, "R/W", 0, 1, 0ull, 0},
|
|
{"QDLL_ENA" , 8, 1, 259, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ODT_ENA" , 9, 1, 259, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DDR2T" , 10, 1, 259, "R/W", 0, 1, 0ull, 0},
|
|
{"CRIP_MODE" , 11, 1, 259, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TFAW" , 12, 5, 259, "R/W", 0, 0, 0ull, 9ull},
|
|
{"DDR_EOF" , 17, 4, 259, "R/W", 0, 0, 2ull, 2ull},
|
|
{"SILO_HC" , 21, 1, 259, "R/W", 0, 1, 1ull, 0},
|
|
{"TWR" , 22, 3, 259, "R/W", 0, 0, 3ull, 1ull},
|
|
{"BWCNT" , 25, 1, 259, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POCAS" , 26, 1, 259, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDLAT" , 27, 3, 259, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BURST8" , 30, 1, 259, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BANK8" , 31, 1, 259, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 259, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN0" , 0, 8, 260, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN1" , 8, 8, 260, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN2" , 16, 8, 260, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN3" , 24, 8, 260, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 260, "RAZ", 1, 1, 0, 0},
|
|
{"FCOL" , 0, 12, 261, "RO", 0, 0, 0ull, 0ull},
|
|
{"FROW" , 12, 14, 261, "RO", 0, 0, 0ull, 0ull},
|
|
{"FBANK" , 26, 3, 261, "RO", 0, 0, 0ull, 0ull},
|
|
{"FBUNK" , 29, 1, 261, "RO", 0, 0, 0ull, 0ull},
|
|
{"FDIMM" , 30, 2, 261, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 261, "RAZ", 1, 1, 0, 0},
|
|
{"IFBCNT_HI" , 0, 32, 262, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 262, "RAZ", 1, 1, 0, 0},
|
|
{"IFBCNT_LO" , 0, 32, 263, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 263, "RAZ", 1, 1, 0, 0},
|
|
{"INIT_START" , 0, 1, 264, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 1, 1, 264, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ROW_LSB" , 2, 3, 264, "R/W", 0, 1, 3ull, 0},
|
|
{"PBANK_LSB" , 5, 4, 264, "R/W", 0, 1, 5ull, 0},
|
|
{"REF_INT" , 9, 6, 264, "R/W", 0, 0, 1ull, 2ull},
|
|
{"TCL" , 15, 4, 264, "R/W", 0, 1, 3ull, 0},
|
|
{"INTR_SEC_ENA" , 19, 1, 264, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INTR_DED_ENA" , 20, 1, 264, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 21, 4, 264, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 25, 4, 264, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BUNK_ENA" , 29, 1, 264, "R/W", 0, 1, 0ull, 0},
|
|
{"SILO_QC" , 30, 1, 264, "R/W", 0, 1, 0ull, 0},
|
|
{"RESET" , 31, 1, 264, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 264, "RAZ", 1, 1, 0, 0},
|
|
{"TRAS" , 0, 5, 265, "R/W", 0, 0, 12ull, 12ull},
|
|
{"TRCD" , 5, 4, 265, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TWTR" , 9, 4, 265, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TRP" , 13, 4, 265, "R/W", 0, 0, 5ull, 4ull},
|
|
{"TRFC" , 17, 5, 265, "R/W", 0, 0, 6ull, 7ull},
|
|
{"TMRD" , 22, 3, 265, "R/W", 0, 0, 2ull, 2ull},
|
|
{"CASLAT" , 25, 3, 265, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TRRD" , 28, 3, 265, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_31_63" , 31, 33, 265, "RAZ", 1, 1, 0, 0},
|
|
{"OPSCNT_HI" , 0, 32, 266, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 266, "RAZ", 1, 1, 0, 0},
|
|
{"OPSCNT_LO" , 0, 32, 267, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 267, "RAZ", 1, 1, 0, 0},
|
|
{"BWCTL" , 0, 4, 268, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BWUPD" , 4, 1, 268, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 268, "RAZ", 1, 1, 0, 0},
|
|
{"RODT_LO0" , 0, 4, 269, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_LO1" , 4, 4, 269, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_LO2" , 8, 4, 269, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_LO3" , 12, 4, 269, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI0" , 16, 4, 269, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI1" , 20, 4, 269, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI2" , 24, 4, 269, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI3" , 28, 4, 269, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_32_63" , 32, 32, 269, "RAZ", 1, 1, 0, 0},
|
|
{"WODT_LO0" , 0, 4, 270, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_LO1" , 4, 4, 270, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_LO2" , 8, 4, 270, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_LO3" , 12, 4, 270, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_HI0" , 16, 4, 270, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_HI1" , 20, 4, 270, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_HI2" , 24, 4, 270, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_HI3" , 28, 4, 270, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_32_63" , 32, 32, 270, "RAZ", 1, 1, 0, 0},
|
|
{"NCBI" , 0, 1, 271, "RO", 0, 0, 0ull, 0ull},
|
|
{"LOC" , 1, 1, 271, "RO", 0, 0, 0ull, 0ull},
|
|
{"NCBO_0" , 2, 1, 271, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 271, "RAZ", 1, 1, 0, 0},
|
|
{"ADR_ERR" , 0, 1, 272, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WAIT_ERR" , 1, 1, 272, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 272, "RAZ", 1, 1, 0, 0},
|
|
{"ADR_INT" , 0, 1, 273, "R/W", 0, 1, 0ull, 0},
|
|
{"WAIT_INT" , 1, 1, 273, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 273, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 274, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 3, 5, 274, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 274, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 275, "RAZ", 1, 1, 0, 0},
|
|
{"BASE" , 3, 25, 275, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_30" , 28, 3, 275, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 31, 1, 275, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 275, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 276, "R/W", 1, 1, 0, 0},
|
|
{"BASE" , 0, 16, 277, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 16, 12, 277, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_29" , 28, 2, 277, "RAZ", 1, 1, 0, 0},
|
|
{"ORBIT" , 30, 1, 277, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 31, 1, 277, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 277, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 6, 278, "R/W", 0, 1, 63ull, 0},
|
|
{"CE" , 6, 6, 278, "R/W", 0, 1, 63ull, 0},
|
|
{"OE" , 12, 6, 278, "R/W", 0, 1, 63ull, 0},
|
|
{"WE" , 18, 6, 278, "R/W", 0, 1, 63ull, 0},
|
|
{"RD_HLD" , 24, 6, 278, "R/W", 0, 1, 63ull, 0},
|
|
{"WR_HLD" , 30, 6, 278, "R/W", 0, 1, 63ull, 0},
|
|
{"PAUSE" , 36, 6, 278, "R/W", 0, 1, 63ull, 0},
|
|
{"WAIT" , 42, 6, 278, "R/W", 0, 1, 63ull, 0},
|
|
{"PAGE" , 48, 6, 278, "R/W", 0, 1, 63ull, 0},
|
|
{"RESERVED_54_59" , 54, 6, 278, "RAZ", 1, 1, 0, 0},
|
|
{"PAGES" , 60, 2, 278, "R/W", 0, 1, 0ull, 0},
|
|
{"WAITM" , 62, 1, 278, "R/W", 0, 1, 0ull, 0},
|
|
{"PAGEM" , 63, 1, 278, "R/W", 0, 1, 0ull, 0},
|
|
{"FIF_THR" , 0, 6, 279, "R/W", 0, 0, 26ull, 26ull},
|
|
{"RESERVED_6_7" , 6, 2, 279, "RAZ", 1, 1, 0, 0},
|
|
{"FIF_CNT" , 8, 6, 279, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_63" , 14, 50, 279, "RAZ", 1, 1, 0, 0},
|
|
{"MAN_INFO" , 0, 32, 280, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 280, "RAZ", 1, 1, 0, 0},
|
|
{"MAN_INFO" , 0, 32, 281, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 281, "RAZ", 1, 1, 0, 0},
|
|
{"PP_DIS" , 0, 16, 282, "RO", 1, 1, 0, 0},
|
|
{"CHIP_ID" , 16, 8, 282, "RO", 1, 1, 0, 0},
|
|
{"BIST_DIS" , 24, 1, 282, "RO", 1, 1, 0, 0},
|
|
{"RST_SHT" , 25, 1, 282, "RO", 1, 1, 0, 0},
|
|
{"NOCRYPTO" , 26, 1, 282, "RO", 1, 1, 0, 0},
|
|
{"NOMUL" , 27, 1, 282, "RO", 1, 1, 0, 0},
|
|
{"NODFA_CP2" , 28, 1, 282, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 282, "RAZ", 1, 1, 0, 0},
|
|
{"ICACHE" , 0, 24, 283, "RO", 1, 1, 0, 0},
|
|
{"NODFA_DTE" , 24, 1, 283, "RO", 1, 1, 0, 0},
|
|
{"NOZIP" , 25, 1, 283, "RO", 1, 1, 0, 0},
|
|
{"EFUS_IGN" , 26, 1, 283, "RO", 1, 1, 0, 0},
|
|
{"EFUS_LCK" , 27, 1, 283, "RO", 1, 1, 0, 0},
|
|
{"BAR2_EN" , 28, 1, 283, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 283, "RAZ", 1, 1, 0, 0},
|
|
{"PROG" , 0, 1, 284, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_1_63" , 1, 63, 284, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 7, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 285, "RAZ", 1, 1, 0, 0},
|
|
{"EFUSE" , 8, 1, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 285, "RAZ", 1, 1, 0, 0},
|
|
{"PEND" , 12, 1, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 285, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 16, 8, 285, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_24_63" , 24, 40, 285, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 10, 286, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_10_63" , 10, 54, 286, "RAZ", 1, 1, 0, 0},
|
|
{"ST_INT" , 0, 1, 287, "R/W1C", 0, 1, 0ull, 0},
|
|
{"TS_INT" , 1, 1, 287, "R/W1C", 0, 1, 0ull, 0},
|
|
{"CORE_INT" , 2, 1, 287, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_3" , 3, 1, 287, "RAZ", 1, 1, 0, 0},
|
|
{"ST_EN" , 4, 1, 287, "R/W", 0, 1, 0ull, 0},
|
|
{"TS_EN" , 5, 1, 287, "R/W", 0, 1, 0ull, 0},
|
|
{"CORE_EN" , 6, 1, 287, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 287, "RAZ", 1, 1, 0, 0},
|
|
{"D" , 0, 32, 288, "R/W", 0, 1, 0ull, 0},
|
|
{"EOP_IA" , 32, 3, 288, "R/W", 0, 1, 0ull, 0},
|
|
{"IA" , 35, 5, 288, "R/W", 0, 1, 0ull, 0},
|
|
{"A" , 40, 10, 288, "R/W", 0, 1, 0ull, 0},
|
|
{"SCR" , 50, 2, 288, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 52, 3, 288, "R/W", 0, 1, 0ull, 0},
|
|
{"SOVR" , 55, 1, 288, "R/W", 0, 1, 0ull, 0},
|
|
{"R" , 56, 1, 288, "R/W", 0, 1, 0ull, 0},
|
|
{"OP" , 57, 4, 288, "R/W", 0, 1, 0ull, 0},
|
|
{"EIA" , 61, 1, 288, "R/W", 0, 1, 0ull, 0},
|
|
{"SLONLY" , 62, 1, 288, "R/W", 0, 1, 0ull, 0},
|
|
{"V" , 63, 1, 288, "RC/W", 0, 1, 0ull, 0},
|
|
{"D" , 0, 32, 289, "R/W", 0, 1, 0ull, 0},
|
|
{"IA" , 32, 8, 289, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_40_63" , 40, 24, 289, "RAZ", 1, 1, 0, 0},
|
|
{"D" , 0, 32, 290, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_32_61" , 32, 30, 290, "RAZ", 1, 1, 0, 0},
|
|
{"V" , 62, 2, 290, "RC/W", 0, 1, 0ull, 0},
|
|
{"DLH" , 0, 8, 291, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 291, "RAZ", 1, 1, 0, 0},
|
|
{"DLL" , 0, 8, 292, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 292, "RAZ", 1, 1, 0, 0},
|
|
{"FAR" , 0, 1, 293, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 293, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 294, "WO", 0, 1, 0ull, 0},
|
|
{"RXFR" , 1, 1, 294, "WO", 0, 1, 0ull, 0},
|
|
{"TXFR" , 2, 1, 294, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_3" , 3, 1, 294, "RAZ", 0, 1, 0ull, 0},
|
|
{"TXTRIG" , 4, 2, 294, "WO", 0, 1, 0ull, 0},
|
|
{"RXTRIG" , 6, 2, 294, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 294, "RAZ", 1, 1, 0, 0},
|
|
{"HTX" , 0, 1, 295, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 295, "RAZ", 1, 1, 0, 0},
|
|
{"ERBFI" , 0, 1, 296, "R/W", 0, 1, 0ull, 0},
|
|
{"ETBEI" , 1, 1, 296, "R/W", 0, 1, 0ull, 0},
|
|
{"ELSI" , 2, 1, 296, "R/W", 0, 1, 0ull, 0},
|
|
{"EDSSI" , 3, 1, 296, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_6" , 4, 3, 296, "RAZ", 0, 1, 0ull, 0},
|
|
{"PTIME" , 7, 1, 296, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 296, "RAZ", 1, 1, 0, 0},
|
|
{"IID" , 0, 4, 297, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_4_5" , 4, 2, 297, "RAZ", 0, 1, 0ull, 0},
|
|
{"FEN" , 6, 2, 297, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 297, "RAZ", 1, 1, 0, 0},
|
|
{"CLS" , 0, 2, 298, "R/W", 0, 1, 0ull, 0},
|
|
{"STOP" , 2, 1, 298, "R/W", 0, 1, 0ull, 0},
|
|
{"PEN" , 3, 1, 298, "R/W", 0, 1, 0ull, 0},
|
|
{"EPS" , 4, 1, 298, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_5" , 5, 1, 298, "RAZ", 0, 1, 0ull, 0},
|
|
{"BRK" , 6, 1, 298, "R/W", 0, 1, 0ull, 0},
|
|
{"DLAB" , 7, 1, 298, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 298, "RAZ", 1, 1, 0, 0},
|
|
{"DR" , 0, 1, 299, "RO", 0, 1, 0ull, 0},
|
|
{"OE" , 1, 1, 299, "RC", 0, 1, 0ull, 0},
|
|
{"PE" , 2, 1, 299, "RC", 0, 1, 0ull, 0},
|
|
{"FE" , 3, 1, 299, "RC", 0, 1, 0ull, 0},
|
|
{"BI" , 4, 1, 299, "RC", 0, 1, 0ull, 0},
|
|
{"THRE" , 5, 1, 299, "RO", 0, 1, 1ull, 0},
|
|
{"TEMT" , 6, 1, 299, "RO", 0, 1, 1ull, 0},
|
|
{"FERR" , 7, 1, 299, "RC", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 299, "RAZ", 1, 1, 0, 0},
|
|
{"DTR" , 0, 1, 300, "R/W", 0, 1, 0ull, 0},
|
|
{"RTS" , 1, 1, 300, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT1" , 2, 1, 300, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT2" , 3, 1, 300, "R/W", 0, 1, 0ull, 0},
|
|
{"LOOP" , 4, 1, 300, "R/W", 0, 1, 0ull, 0},
|
|
{"AFCE" , 5, 1, 300, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 300, "RAZ", 0, 1, 0ull, 0},
|
|
{"DCTS" , 0, 1, 301, "RC", 0, 1, 0ull, 0},
|
|
{"DDSR" , 1, 1, 301, "RC", 0, 1, 0ull, 0},
|
|
{"TERI" , 2, 1, 301, "RC", 0, 1, 0ull, 0},
|
|
{"DDCD" , 3, 1, 301, "RC", 0, 1, 0ull, 0},
|
|
{"CTS" , 4, 1, 301, "RO", 1, 1, 0, 0},
|
|
{"DSR" , 5, 1, 301, "RO", 0, 1, 0ull, 0},
|
|
{"RI" , 6, 1, 301, "RO", 0, 1, 0ull, 0},
|
|
{"DCD" , 7, 1, 301, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 301, "RAZ", 1, 1, 0, 0},
|
|
{"RBR" , 0, 8, 302, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 302, "RAZ", 1, 1, 0, 0},
|
|
{"RFL" , 0, 7, 303, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 303, "RAZ", 1, 1, 0, 0},
|
|
{"RFWD" , 0, 8, 304, "WO", 0, 1, 0ull, 0},
|
|
{"RFPE" , 8, 1, 304, "WO", 0, 1, 0ull, 0},
|
|
{"RFFE" , 9, 1, 304, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_10_63" , 10, 54, 304, "RAZ", 1, 1, 0, 0},
|
|
{"SBCR" , 0, 1, 305, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 305, "RAZ", 1, 1, 0, 0},
|
|
{"SCR" , 0, 8, 306, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 306, "RAZ", 1, 1, 0, 0},
|
|
{"SFE" , 0, 1, 307, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 307, "RAZ", 1, 1, 0, 0},
|
|
{"USR" , 0, 1, 308, "WO", 0, 1, 0ull, 0},
|
|
{"SRFR" , 1, 1, 308, "WO", 0, 1, 0ull, 0},
|
|
{"STFR" , 2, 1, 308, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_63" , 3, 61, 308, "RAZ", 1, 1, 0, 0},
|
|
{"SRT" , 0, 2, 309, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 309, "RAZ", 1, 1, 0, 0},
|
|
{"SRTS" , 0, 1, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 310, "RAZ", 1, 1, 0, 0},
|
|
{"STT" , 0, 2, 311, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 311, "RAZ", 1, 1, 0, 0},
|
|
{"TFL" , 0, 7, 312, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 312, "RAZ", 1, 1, 0, 0},
|
|
{"TFR" , 0, 8, 313, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 313, "RAZ", 1, 1, 0, 0},
|
|
{"THR" , 0, 8, 314, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 314, "RAZ", 1, 1, 0, 0},
|
|
{"BUSY" , 0, 1, 315, "RO", 0, 1, 0ull, 0},
|
|
{"TFNF" , 1, 1, 315, "RO", 0, 1, 1ull, 0},
|
|
{"TFE" , 2, 1, 315, "RO", 0, 1, 1ull, 0},
|
|
{"RFNE" , 3, 1, 315, "RO", 0, 1, 0ull, 0},
|
|
{"RFF" , 4, 1, 315, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 315, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 316, "RAZ", 1, 1, 0, 0},
|
|
{"BADDR" , 3, 61, 316, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_0_2" , 0, 3, 317, "RAZ", 1, 1, 0, 0},
|
|
{"BADDR" , 3, 61, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"DPI_BS" , 0, 1, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"PDF_BS" , 1, 1, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"DOB_BS" , 2, 1, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"NUS_BS" , 3, 1, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"POS_BS" , 4, 1, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"POF3_BS" , 5, 1, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"POF2_BS" , 6, 1, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"POF1_BS" , 7, 1, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"POF0_BS" , 8, 1, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"PIG_BS" , 9, 1, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"PGF_BS" , 10, 1, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"RDNL_BS" , 11, 1, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCAD_BS" , 12, 1, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCAC_BS" , 13, 1, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"RDN_BS" , 14, 1, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCN_BS" , 15, 1, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCNC_BS" , 16, 1, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"RDP_BS" , 17, 1, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF_BS" , 18, 1, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSR_BS" , 19, 1, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 318, "RAZ", 1, 1, 0, 0},
|
|
{"BSIZE" , 0, 16, 319, "R/W", 0, 1, 1024ull, 0},
|
|
{"ISIZE" , 16, 7, 319, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_23_63" , 23, 41, 319, "RAZ", 1, 1, 0, 0},
|
|
{"TIMER" , 0, 10, 320, "R/W", 0, 0, 0ull, 50ull},
|
|
{"RESERVED_10_31" , 10, 22, 320, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX_WORD" , 32, 5, 320, "R/W", 0, 0, 2ull, 0ull},
|
|
{"RESERVED_37_39" , 37, 3, 320, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WAIT_COM" , 40, 1, 320, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCI_WDIS" , 41, 1, 320, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INS0_64B" , 42, 1, 320, "R/W", 0, 1, 0ull, 0},
|
|
{"INS1_64B" , 43, 1, 320, "R/W", 0, 1, 0ull, 0},
|
|
{"INS2_64B" , 44, 1, 320, "R/W", 0, 1, 0ull, 0},
|
|
{"INS3_64B" , 45, 1, 320, "R/W", 0, 1, 0ull, 0},
|
|
{"INS0_ENB" , 46, 1, 320, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INS1_ENB" , 47, 1, 320, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INS2_ENB" , 48, 1, 320, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INS3_ENB" , 49, 1, 320, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OUT0_ENB" , 50, 1, 320, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OUT1_ENB" , 51, 1, 320, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OUT2_ENB" , 52, 1, 320, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OUT3_ENB" , 53, 1, 320, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DIS_PNIW" , 54, 1, 320, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CHIP_REV" , 55, 8, 320, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_63_63" , 63, 1, 320, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_SEL" , 0, 16, 321, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 321, "RAZ", 1, 1, 0, 0},
|
|
{"CSIZE" , 0, 14, 322, "R/W", 0, 1, 0ull, 0},
|
|
{"LP_ENB" , 14, 1, 322, "R/W", 0, 0, 0ull, 1ull},
|
|
{"HP_ENB" , 15, 1, 322, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O_MODE" , 16, 1, 322, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O_ES" , 17, 2, 322, "R/W", 0, 1, 0ull, 0},
|
|
{"O_NS" , 19, 1, 322, "R/W", 0, 1, 0ull, 0},
|
|
{"O_RO" , 20, 1, 322, "R/W", 0, 1, 0ull, 0},
|
|
{"O_ADD1" , 21, 1, 322, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA_QUE" , 22, 3, 322, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB_ICHK" , 25, 9, 322, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB_DENB" , 34, 1, 322, "R/W", 0, 0, 0ull, 1ull},
|
|
{"B0_LEND" , 35, 1, 322, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 322, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 32, 323, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 7, 323, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_39_63" , 39, 25, 323, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 324, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 36, 4, 324, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 324, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 32, 325, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 7, 325, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_39_63" , 39, 25, 325, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 326, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 36, 4, 326, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 326, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 16, 327, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 327, "RAZ", 1, 1, 0, 0},
|
|
{"SADDR" , 0, 36, 328, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 328, "RAZ", 1, 1, 0, 0},
|
|
{"ROR" , 0, 1, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR" , 1, 2, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR" , 3, 1, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_CSR" , 4, 1, 329, "R/W", 0, 0, 0ull, 1ull},
|
|
{"D_ROR" , 5, 1, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"D_ESR" , 6, 2, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"D_NSR" , 8, 1, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP_DHI" , 9, 13, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_22_63" , 22, 42, 329, "RAZ", 1, 1, 0, 0},
|
|
{"RML_RTO" , 0, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RML_WTO" , 1, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCI_RSL" , 2, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PO0_2SML" , 3, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PO1_2SML" , 4, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PO2_2SML" , 5, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PO3_2SML" , 6, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I0_RTOUT" , 7, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I1_RTOUT" , 8, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I2_RTOUT" , 9, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I3_RTOUT" , 10, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I0_OVERF" , 11, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I1_OVERF" , 12, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I2_OVERF" , 13, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I3_OVERF" , 14, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P0_RTOUT" , 15, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_RTOUT" , 16, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P2_RTOUT" , 17, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P3_RTOUT" , 18, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P0_PERR" , 19, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_PERR" , 20, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P2_PERR" , 21, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P3_PERR" , 22, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"G0_RTOUT" , 23, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"G1_RTOUT" , 24, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"G2_RTOUT" , 25, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"G3_RTOUT" , 26, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P0_PPERR" , 27, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_PPERR" , 28, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P2_PPERR" , 29, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P3_PPERR" , 30, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P0_PTOUT" , 31, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_PTOUT" , 32, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P2_PTOUT" , 33, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P3_PTOUT" , 34, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I0_PPERR" , 35, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I1_PPERR" , 36, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I2_PPERR" , 37, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I3_PPERR" , 38, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"WIN_RTO" , 39, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P_DPERR" , 40, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 41, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_42_63" , 42, 22, 330, "RAZ", 1, 1, 0, 0},
|
|
{"RML_RTO" , 0, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RML_WTO" , 1, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCI_RSL" , 2, 1, 331, "RO", 0, 0, 0ull, 0ull},
|
|
{"PO0_2SML" , 3, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PO1_2SML" , 4, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PO2_2SML" , 5, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PO3_2SML" , 6, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I0_RTOUT" , 7, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I1_RTOUT" , 8, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I2_RTOUT" , 9, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I3_RTOUT" , 10, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I0_OVERF" , 11, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I1_OVERF" , 12, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I2_OVERF" , 13, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I3_OVERF" , 14, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P0_RTOUT" , 15, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_RTOUT" , 16, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P2_RTOUT" , 17, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P3_RTOUT" , 18, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P0_PERR" , 19, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_PERR" , 20, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P2_PERR" , 21, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P3_PERR" , 22, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"G0_RTOUT" , 23, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"G1_RTOUT" , 24, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"G2_RTOUT" , 25, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"G3_RTOUT" , 26, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P0_PPERR" , 27, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_PPERR" , 28, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P2_PPERR" , 29, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P3_PPERR" , 30, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P0_PTOUT" , 31, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_PTOUT" , 32, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P2_PTOUT" , 33, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P3_PTOUT" , 34, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I0_PPERR" , 35, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I1_PPERR" , 36, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I2_PPERR" , 37, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I3_PPERR" , 38, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WIN_RTO" , 39, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_DPERR" , 40, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IOBDMA" , 41, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_42_63" , 42, 22, 331, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 16, 332, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 332, "RAZ", 1, 1, 0, 0},
|
|
{"SADDR" , 0, 36, 333, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 333, "RAZ", 1, 1, 0, 0},
|
|
{"BA" , 0, 28, 334, "R/W", 0, 1, 0ull, 0},
|
|
{"ROW" , 28, 1, 334, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR" , 29, 1, 334, "R/W", 0, 1, 0ull, 0},
|
|
{"NSW" , 30, 1, 334, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR" , 31, 1, 334, "R/W", 0, 1, 0ull, 0},
|
|
{"ESW" , 32, 2, 334, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR" , 34, 2, 334, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 334, "RAZ", 1, 1, 0, 0},
|
|
{"INT_VEC" , 0, 64, 335, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 0, 32, 336, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 336, "RAZ", 1, 1, 0, 0},
|
|
{"ROR_SL0" , 0, 1, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR_SL0" , 1, 1, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR_SL0" , 2, 2, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR_SL1" , 4, 1, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR_SL1" , 5, 1, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR_SL1" , 6, 2, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR_SL2" , 8, 1, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR_SL2" , 9, 1, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR_SL2" , 10, 2, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR_SL3" , 12, 1, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR_SL3" , 13, 1, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR_SL3" , 14, 2, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"IPTR_O0" , 16, 1, 337, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IPTR_O1" , 17, 1, 337, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IPTR_O2" , 18, 1, 337, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IPTR_O3" , 19, 1, 337, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_20_23" , 20, 4, 337, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"O0_CSRM" , 24, 1, 337, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O1_CSRM" , 25, 1, 337, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O2_CSRM" , 26, 1, 337, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O3_CSRM" , 27, 1, 337, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O0_RO" , 28, 1, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"O0_NS" , 29, 1, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"O0_ES" , 30, 2, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"O1_RO" , 32, 1, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"O1_NS" , 33, 1, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"O1_ES" , 34, 2, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"O2_RO" , 36, 1, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"O2_NS" , 37, 1, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"O2_ES" , 38, 2, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"O3_RO" , 40, 1, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"O3_NS" , 41, 1, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"O3_ES" , 42, 2, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"P0_BMODE" , 44, 1, 337, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P1_BMODE" , 45, 1, 337, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P2_BMODE" , 46, 1, 337, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P3_BMODE" , 47, 1, 337, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 337, "RAZ", 1, 1, 0, 0},
|
|
{"NADDR" , 0, 61, 338, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 61, 2, 338, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_63_63" , 63, 1, 338, "RAZ", 1, 1, 0, 0},
|
|
{"NADDR" , 0, 61, 339, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 61, 3, 339, "RO", 0, 0, 0ull, 0ull},
|
|
{"AVAIL" , 0, 32, 340, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 6, 340, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 340, "RAZ", 1, 1, 0, 0},
|
|
{"AVAIL" , 0, 32, 341, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 5, 341, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 341, "RAZ", 1, 1, 0, 0},
|
|
{"RD_BRST" , 0, 7, 342, "R/W", 0, 0, 17ull, 64ull},
|
|
{"WR_BRST" , 7, 7, 342, "R/W", 0, 0, 16ull, 64ull},
|
|
{"RESERVED_14_63" , 14, 50, 342, "RAZ", 1, 1, 0, 0},
|
|
{"PARK_DEV" , 0, 3, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"PARK_MOD" , 3, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 4, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 343, "RAZ", 1, 1, 0, 0},
|
|
{"CMD_SIZE" , 0, 11, 344, "R/W", 0, 0, 9ull, 9ull},
|
|
{"RESERVED_11_63" , 11, 53, 344, "RAZ", 1, 1, 0, 0},
|
|
{"RSV_A" , 0, 6, 345, "R/W", 0, 1, 0ull, 0},
|
|
{"SKP_LEN" , 6, 7, 345, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_B" , 13, 1, 345, "R/W", 0, 1, 0ull, 0},
|
|
{"PAR_MODE" , 14, 2, 345, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_C" , 16, 5, 345, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_IHDR" , 21, 1, 345, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_D" , 22, 6, 345, "R/W", 0, 1, 0ull, 0},
|
|
{"RSKP_LEN" , 28, 7, 345, "R/W", 0, 1, 8ull, 0},
|
|
{"RSV_E" , 35, 1, 345, "R/W", 0, 1, 0ull, 0},
|
|
{"RPARMODE" , 36, 2, 345, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_F" , 38, 5, 345, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP" , 43, 1, 345, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 345, "RAZ", 1, 1, 0, 0},
|
|
{"RSV_A" , 0, 6, 346, "R/W", 0, 1, 0ull, 0},
|
|
{"SKP_LEN" , 6, 7, 346, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_B" , 13, 1, 346, "R/W", 0, 1, 0ull, 0},
|
|
{"PAR_MODE" , 14, 2, 346, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_C" , 16, 5, 346, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_IHDR" , 21, 1, 346, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_D" , 22, 6, 346, "R/W", 0, 1, 0ull, 0},
|
|
{"RSKP_LEN" , 28, 7, 346, "R/W", 0, 1, 8ull, 0},
|
|
{"RSV_E" , 35, 1, 346, "R/W", 0, 1, 0ull, 0},
|
|
{"RPARMODE" , 36, 2, 346, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_F" , 38, 5, 346, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP" , 43, 1, 346, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 346, "RAZ", 1, 1, 0, 0},
|
|
{"RSV_A" , 0, 6, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"SKP_LEN" , 6, 7, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_B" , 13, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"PAR_MODE" , 14, 2, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_C" , 16, 5, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_IHDR" , 21, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_D" , 22, 6, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"RSKP_LEN" , 28, 7, 347, "R/W", 0, 1, 8ull, 0},
|
|
{"RSV_E" , 35, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"RPARMODE" , 36, 2, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_F" , 38, 5, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP" , 43, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 347, "RAZ", 1, 1, 0, 0},
|
|
{"RSV_A" , 0, 6, 348, "R/W", 0, 1, 0ull, 0},
|
|
{"SKP_LEN" , 6, 7, 348, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_B" , 13, 1, 348, "R/W", 0, 1, 0ull, 0},
|
|
{"PAR_MODE" , 14, 2, 348, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_C" , 16, 5, 348, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_IHDR" , 21, 1, 348, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_D" , 22, 6, 348, "R/W", 0, 1, 0ull, 0},
|
|
{"RSKP_LEN" , 28, 7, 348, "R/W", 0, 1, 8ull, 0},
|
|
{"RSV_E" , 35, 1, 348, "R/W", 0, 1, 0ull, 0},
|
|
{"RPARMODE" , 36, 2, 348, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_F" , 38, 5, 348, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP" , 43, 1, 348, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 348, "RAZ", 1, 1, 0, 0},
|
|
{"ENB" , 0, 4, 349, "R/W", 0, 0, 15ull, 15ull},
|
|
{"BP_ON" , 4, 4, 349, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 349, "RAZ", 1, 1, 0, 0},
|
|
{"MIO" , 0, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX0" , 1, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX1" , 2, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPI" , 3, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"KEY" , 4, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPA" , 5, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"DFA" , 6, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"ZIP" , 7, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_8" , 8, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD" , 9, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 10, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"TIM" , 11, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"POW" , 12, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_13" , 13, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_14" , 14, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_15" , 15, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"L2C" , 16, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"LMC" , 17, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"SPX0" , 18, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"SPX1" , 19, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"PIP" , 20, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_21" , 21, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASX0" , 22, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASX1" , 23, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_24" , 24, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_25" , 25, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_26" , 26, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_27" , 27, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_28" , 28, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_29" , 29, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"IOB" , 30, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_31" , 31, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 350, "RAZ", 1, 1, 0, 0},
|
|
{"SIZE" , 0, 32, 351, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 351, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 32, 352, "R/W", 0, 0, 0ull, 131072ull},
|
|
{"RESERVED_32_63" , 32, 32, 352, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR_V" , 0, 1, 353, "R/W", 0, 1, 0ull, 0},
|
|
{"END_SWP" , 1, 2, 353, "R/W", 0, 1, 0ull, 0},
|
|
{"CA" , 3, 1, 353, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDR_IDX" , 4, 14, 353, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_31" , 18, 14, 353, "RAZ", 1, 1, 0, 0},
|
|
{"VENDID" , 0, 16, 354, "RO", 0, 0, 6013ull, 6013ull},
|
|
{"DEVID" , 16, 16, 354, "RO", 0, 0, 4ull, 4ull},
|
|
{"ISAE" , 0, 1, 355, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSAE" , 1, 1, 355, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ME" , 2, 1, 355, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SCSE" , 3, 1, 355, "RO", 0, 0, 0ull, 0ull},
|
|
{"MWICE" , 4, 1, 355, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VPS" , 5, 1, 355, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEE" , 6, 1, 355, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ADS" , 7, 1, 355, "RO", 0, 0, 0ull, 0ull},
|
|
{"SEE" , 8, 1, 355, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FBBE" , 9, 1, 355, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I_DIS" , 10, 1, 355, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_18" , 11, 8, 355, "RAZ", 1, 1, 0, 0},
|
|
{"I_STAT" , 19, 1, 355, "RO", 0, 0, 0ull, 0ull},
|
|
{"CLE" , 20, 1, 355, "RO", 0, 0, 1ull, 1ull},
|
|
{"M66" , 21, 1, 355, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_22_22" , 22, 1, 355, "RAZ", 1, 1, 0, 0},
|
|
{"FBB" , 23, 1, 355, "RO", 0, 1, 1ull, 0},
|
|
{"MDPE" , 24, 1, 355, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DEVT" , 25, 2, 355, "RO", 0, 0, 1ull, 1ull},
|
|
{"STA" , 27, 1, 355, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTA" , 28, 1, 355, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RMA" , 29, 1, 355, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SSE" , 30, 1, 355, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPE" , 31, 1, 355, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RID" , 0, 8, 356, "RO", 0, 0, 1ull, 1ull},
|
|
{"CC" , 8, 24, 356, "RO", 0, 0, 1048576ull, 1048576ull},
|
|
{"CLS" , 0, 8, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"LT" , 8, 8, 357, "R/W", 0, 0, 0ull, 64ull},
|
|
{"HT" , 16, 8, 357, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCOD" , 24, 4, 357, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_29" , 28, 2, 357, "RAZ", 1, 1, 0, 0},
|
|
{"BRB" , 30, 1, 357, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BCAP" , 31, 1, 357, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSPC" , 0, 1, 358, "RO", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 358, "RO", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 358, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBASEZ" , 4, 8, 358, "RO", 0, 0, 0ull, 0ull},
|
|
{"LBASE" , 12, 20, 358, "R/W", 0, 1, 0ull, 0},
|
|
{"HBASE" , 0, 32, 359, "R/W", 0, 1, 0ull, 0},
|
|
{"MSPC" , 0, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 360, "RO", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 360, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBASEZ" , 4, 23, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"LBASE" , 27, 5, 360, "R/W", 0, 1, 0ull, 0},
|
|
{"HBASE" , 0, 32, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"MSPC" , 0, 1, 362, "RO", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 362, "RO", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 362, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBASEZ" , 4, 28, 362, "RO", 0, 0, 0ull, 0ull},
|
|
{"HBASEZ" , 0, 7, 363, "RO", 0, 0, 0ull, 0ull},
|
|
{"HBASE" , 7, 25, 363, "R/W", 0, 1, 0ull, 0},
|
|
{"CISP" , 0, 32, 364, "RO", 0, 0, 0ull, 0ull},
|
|
{"SSVID" , 0, 16, 365, "RO", 0, 0, 6013ull, 6013ull},
|
|
{"SSID" , 16, 16, 365, "RO", 0, 0, 1ull, 1ull},
|
|
{"ERBAR_EN" , 0, 1, 366, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_10" , 1, 10, 366, "RAZ", 1, 1, 0, 0},
|
|
{"ERBARZ" , 11, 5, 366, "RO", 0, 0, 0ull, 0ull},
|
|
{"ERBAR" , 16, 16, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"CP" , 0, 8, 367, "RO", 0, 0, 224ull, 224ull},
|
|
{"RESERVED_8_31" , 8, 24, 367, "RAZ", 1, 1, 0, 0},
|
|
{"IL" , 0, 8, 368, "R/W", 0, 1, 0ull, 0},
|
|
{"INTA" , 8, 8, 368, "RO", 0, 0, 1ull, 1ull},
|
|
{"MG" , 16, 8, 368, "RO", 0, 0, 64ull, 64ull},
|
|
{"ML" , 24, 8, 368, "RO", 0, 0, 64ull, 64ull},
|
|
{"MLTD" , 0, 1, 369, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TSWC" , 1, 1, 369, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 369, "RAZ", 1, 1, 0, 0},
|
|
{"DPPMR" , 3, 1, 369, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PBE" , 4, 12, 369, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TILT" , 16, 4, 369, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TSLTE" , 20, 3, 369, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TMAE" , 23, 1, 369, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWTAE" , 24, 1, 369, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWSEN" , 25, 1, 369, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWSEI" , 26, 1, 369, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRTAE" , 27, 1, 369, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRDRS" , 28, 1, 369, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RDSATI" , 29, 1, 369, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRDARD" , 30, 1, 369, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TRDNPR" , 31, 1, 369, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TSCME" , 0, 32, 370, "R/W1C", 0, 1, 0ull, 0},
|
|
{"TDSRPS" , 0, 32, 371, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TDOMC" , 0, 5, 372, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TIDOMC" , 5, 1, 372, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_6" , 6, 1, 372, "RAZ", 1, 1, 0, 0},
|
|
{"TIBDE" , 7, 1, 372, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIBCD" , 8, 1, 372, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_10" , 9, 2, 372, "RAZ", 1, 1, 0, 0},
|
|
{"TMAPES" , 11, 1, 372, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TMDPES" , 12, 1, 372, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TMSE" , 13, 1, 372, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TMEI" , 14, 1, 372, "RO", 0, 0, 0ull, 0ull},
|
|
{"TECI" , 15, 1, 372, "RO", 0, 0, 0ull, 0ull},
|
|
{"TMES" , 16, 8, 372, "RO", 0, 0, 0ull, 0ull},
|
|
{"MDRRMC" , 24, 3, 372, "R/W", 0, 0, 2ull, 2ull},
|
|
{"MDRIMC" , 27, 1, 372, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MDRE" , 28, 1, 372, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MDWE" , 29, 1, 372, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRBCI" , 30, 1, 372, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRBCM" , 31, 1, 372, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MDSP" , 0, 32, 373, "R/W1C", 0, 1, 0ull, 0},
|
|
{"SCMRE" , 0, 32, 374, "R/W1C", 0, 1, 0ull, 0},
|
|
{"MTTV" , 0, 8, 375, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRV" , 8, 8, 375, "R/W", 0, 0, 0ull, 255ull},
|
|
{"MTTA" , 16, 1, 375, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRA" , 17, 1, 375, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FLUSH" , 18, 1, 375, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_19_24" , 19, 6, 375, "RAZ", 1, 1, 0, 0},
|
|
{"MAC" , 25, 7, 375, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PXCID" , 0, 8, 376, "RO", 0, 0, 7ull, 7ull},
|
|
{"NCP" , 8, 8, 376, "RO", 0, 0, 232ull, 232ull},
|
|
{"DPERE" , 16, 1, 376, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROE" , 17, 1, 376, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MMBC" , 18, 2, 376, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MOST" , 20, 3, 376, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_23_31" , 23, 9, 376, "RAZ", 1, 1, 0, 0},
|
|
{"FN" , 0, 3, 377, "RO", 0, 0, 0ull, 0ull},
|
|
{"DN" , 3, 5, 377, "RO", 0, 0, 31ull, 31ull},
|
|
{"BN" , 8, 8, 377, "RO", 0, 1, 17ull, 0},
|
|
{"W64" , 16, 1, 377, "RO", 0, 0, 1ull, 1ull},
|
|
{"M133" , 17, 1, 377, "RO", 0, 0, 1ull, 1ull},
|
|
{"SCD" , 18, 1, 377, "R/W1C", 0, 1, 0ull, 0},
|
|
{"USC" , 19, 1, 377, "R/W1C", 0, 1, 0ull, 0},
|
|
{"DC" , 20, 1, 377, "RO", 0, 0, 0ull, 0ull},
|
|
{"MMRBCD" , 21, 2, 377, "RO", 0, 0, 2ull, 2ull},
|
|
{"MOSTD" , 23, 3, 377, "RO", 0, 0, 3ull, 3ull},
|
|
{"MCRSD" , 26, 3, 377, "RO", 0, 0, 7ull, 7ull},
|
|
{"SCEMR" , 29, 1, 377, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_30_31" , 30, 2, 377, "RAZ", 1, 1, 0, 0},
|
|
{"PMCID" , 0, 8, 378, "RO", 0, 0, 1ull, 1ull},
|
|
{"NCP" , 8, 8, 378, "RO", 0, 0, 240ull, 240ull},
|
|
{"PCIMIV" , 16, 3, 378, "RO", 0, 0, 2ull, 2ull},
|
|
{"PMEC" , 19, 1, 378, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 378, "RAZ", 1, 1, 0, 0},
|
|
{"DSI" , 21, 1, 378, "RO", 0, 0, 0ull, 0ull},
|
|
{"AUXC" , 22, 3, 378, "RO", 0, 0, 0ull, 0ull},
|
|
{"D1S" , 25, 1, 378, "RO", 0, 0, 0ull, 0ull},
|
|
{"D2S" , 26, 1, 378, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMES" , 27, 5, 378, "RO", 0, 0, 0ull, 0ull},
|
|
{"PS" , 0, 2, 379, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_7" , 2, 6, 379, "RAZ", 1, 1, 0, 0},
|
|
{"PMEENS" , 8, 1, 379, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMDS" , 9, 4, 379, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMEDSIA" , 13, 2, 379, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMESS" , 15, 1, 379, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_21" , 16, 6, 379, "RAZ", 1, 1, 0, 0},
|
|
{"BD3H" , 22, 1, 379, "RO", 0, 0, 0ull, 0ull},
|
|
{"BPCCEN" , 23, 1, 379, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMDIA" , 24, 8, 379, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSICID" , 0, 8, 380, "RO", 0, 0, 5ull, 5ull},
|
|
{"NCP" , 8, 8, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSIEN" , 16, 1, 380, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MMC" , 17, 3, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"MME" , 20, 3, 380, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M64" , 23, 1, 380, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_24_31" , 24, 8, 380, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 381, "RAZ", 1, 1, 0, 0},
|
|
{"MSI31T2" , 2, 30, 381, "R/W", 0, 1, 0ull, 0},
|
|
{"MSI" , 0, 32, 382, "R/W", 0, 1, 0ull, 0},
|
|
{"MSIMD" , 0, 16, 383, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_31" , 16, 16, 383, "RAZ", 1, 1, 0, 0},
|
|
{"BAR2_CAX" , 0, 1, 384, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAR2_ESX" , 1, 2, 384, "R/W", 0, 1, 0ull, 0},
|
|
{"BAR2_ENB" , 3, 1, 384, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TSR_HWM" , 4, 3, 384, "R/W", 0, 1, 1ull, 0},
|
|
{"PMO_FPC" , 7, 3, 384, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMO_AMOD" , 10, 1, 384, "R/W", 0, 0, 0ull, 0ull},
|
|
{"B12_BIST" , 11, 1, 384, "RO", 0, 0, 0ull, 0ull},
|
|
{"AP_64AD" , 12, 1, 384, "RO", 1, 1, 0, 0},
|
|
{"AP_PCIX" , 13, 1, 384, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_14_14" , 14, 1, 384, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EN_WFILT" , 15, 1, 384, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SCM" , 16, 1, 384, "RO", 0, 1, 0ull, 0},
|
|
{"SCMTYP" , 17, 1, 384, "RO", 0, 1, 0ull, 0},
|
|
{"BAR2PRES" , 18, 1, 384, "R/W", 1, 1, 0, 0},
|
|
{"ERST_N" , 19, 1, 384, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_20_31" , 20, 12, 384, "RAZ", 1, 1, 0, 0},
|
|
{"INC_VAL" , 0, 16, 385, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_31" , 16, 16, 385, "RAZ", 1, 1, 0, 0},
|
|
{"DMA_CNT" , 0, 32, 386, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKT_CNT" , 0, 32, 387, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA_TIME" , 0, 32, 388, "R/W", 0, 1, 0ull, 0},
|
|
{"ICNT" , 0, 32, 389, "RO", 0, 0, 0ull, 0ull},
|
|
{"ITR_WABT" , 0, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_WABT" , 1, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_WTTO" , 2, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"ITR_ABT" , 3, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_ABT" , 4, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_TTO" , 5, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSI_PER" , 6, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSI_TABT" , 7, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSI_MABT" , 8, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSC_MSG" , 9, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"ITSR_ABT" , 10, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"ISERR" , 11, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"IAPERR" , 12, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"IDPERR" , 13, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RWR" , 14, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RRD" , 15, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"IRSL_INT" , 16, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"IPCNT0" , 17, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"IPCNT1" , 18, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"IPCNT2" , 19, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"IPCNT3" , 20, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"IPTIME0" , 21, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"IPTIME1" , 22, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"IPTIME2" , 23, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"IPTIME3" , 24, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"IDCNT0" , 25, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"IDCNT1" , 26, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"IDTIME0" , 27, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"IDTIME1" , 28, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA0_FI" , 29, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA1_FI" , 30, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"WIN_WR" , 31, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_WR" , 32, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RD" , 33, 1, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_34_63" , 34, 30, 390, "RAZ", 1, 1, 0, 0},
|
|
{"RTR_WABT" , 0, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_WABT" , 1, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_WTTO" , 2, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RTR_ABT" , 3, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_ABT" , 4, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_TTO" , 5, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSI_PER" , 6, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSI_TABT" , 7, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSI_MABT" , 8, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSC_MSG" , 9, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RTSR_ABT" , 10, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RSERR" , 11, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RAPERR" , 12, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RDPERR" , 13, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RWR" , 14, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RRD" , 15, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RRSL_INT" , 16, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RPCNT0" , 17, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RPCNT1" , 18, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RPCNT2" , 19, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RPCNT3" , 20, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RPTIME0" , 21, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RPTIME1" , 22, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RPTIME2" , 23, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RPTIME3" , 24, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RDCNT0" , 25, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RDCNT1" , 26, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RDTIME0" , 27, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RDTIME1" , 28, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA0_FI" , 29, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA1_FI" , 30, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"WIN_WR" , 31, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_WR" , 32, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RD" , 33, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_34_63" , 34, 30, 391, "RAZ", 1, 1, 0, 0},
|
|
{"TR_WABT" , 0, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WABT" , 1, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WTTO" , 2, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TR_ABT" , 3, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_ABT" , 4, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_TTO" , 5, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_PER" , 6, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_TABT" , 7, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_MABT" , 8, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSC_MSG" , 9, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TSR_ABT" , 10, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SERR" , 11, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"APERR" , 12, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPERR" , 13, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RWR" , 14, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RRD" , 15, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSL_INT" , 16, 1, 392, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCNT0" , 17, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT1" , 18, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT2" , 19, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT3" , 20, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME0" , 21, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME1" , 22, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME2" , 23, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME3" , 24, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT0" , 25, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT1" , 26, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME0" , 27, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME1" , 28, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA0_FI" , 29, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1_FI" , 30, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WIN_WR" , 31, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_WR" , 32, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RD" , 33, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 392, "RAZ", 1, 1, 0, 0},
|
|
{"TR_WABT" , 0, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WABT" , 1, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WTTO" , 2, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TR_ABT" , 3, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_ABT" , 4, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_TTO" , 5, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_PER" , 6, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_TABT" , 7, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_MABT" , 8, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSC_MSG" , 9, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TSR_ABT" , 10, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SERR" , 11, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"APERR" , 12, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPERR" , 13, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RWR" , 14, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RRD" , 15, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSL_INT" , 16, 1, 393, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCNT0" , 17, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT1" , 18, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT2" , 19, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT3" , 20, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME0" , 21, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME1" , 22, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME2" , 23, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME3" , 24, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT0" , 25, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT1" , 26, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME0" , 27, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME1" , 28, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA0_FI" , 29, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1_FI" , 30, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WIN_WR" , 31, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_WR" , 32, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RD" , 33, 1, 393, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 393, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 0, 6, 394, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_31" , 6, 26, 394, "R/W", 1, 1, 0, 0},
|
|
{"PTR_CNT" , 0, 16, 395, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_CNT" , 16, 16, 395, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_CNT" , 0, 32, 396, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_CNT" , 0, 32, 397, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_TIME" , 0, 32, 398, "R/W", 0, 1, 0ull, 0},
|
|
{"PREFETCH" , 0, 3, 399, "R/W", 0, 0, 0ull, 2ull},
|
|
{"MIN_DATA" , 3, 6, 399, "R/W", 0, 0, 0ull, 4ull},
|
|
{"RESERVED_9_31" , 9, 23, 399, "RAZ", 1, 1, 0, 0},
|
|
{"PREFETCH" , 0, 3, 400, "R/W", 0, 0, 0ull, 3ull},
|
|
{"MIN_DATA" , 3, 6, 400, "R/W", 0, 0, 0ull, 6ull},
|
|
{"RESERVED_9_31" , 9, 23, 400, "RAZ", 1, 1, 0, 0},
|
|
{"PREFETCH" , 0, 3, 401, "R/W", 0, 0, 0ull, 3ull},
|
|
{"MIN_DATA" , 3, 6, 401, "R/W", 0, 0, 0ull, 6ull},
|
|
{"RESERVED_9_31" , 9, 23, 401, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 31, 402, "R/W", 0, 0, 10000ull, 10000ull},
|
|
{"ENB" , 31, 1, 402, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_32_63" , 32, 32, 402, "RAZ", 1, 1, 0, 0},
|
|
{"SCM" , 0, 32, 403, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 403, "RAZ", 1, 1, 0, 0},
|
|
{"TSR" , 0, 36, 404, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 404, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 405, "RAZ", 1, 1, 0, 0},
|
|
{"RD_ADDR" , 3, 45, 405, "R/W", 0, 1, 0ull, 0},
|
|
{"IOBIT" , 48, 1, 405, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 405, "RAZ", 1, 1, 0, 0},
|
|
{"RD_DATA" , 0, 64, 406, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_0_2" , 0, 3, 407, "RAZ", 1, 1, 0, 0},
|
|
{"WR_ADDR" , 3, 45, 407, "R/W", 0, 1, 0ull, 0},
|
|
{"IOBIT" , 48, 1, 407, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 407, "RAZ", 1, 1, 0, 0},
|
|
{"WR_DATA" , 0, 64, 408, "R/W", 0, 1, 0ull, 0},
|
|
{"WR_MASK" , 0, 8, 409, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 409, "RAZ", 1, 1, 0, 0},
|
|
{"LOWATER" , 0, 5, 410, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_5_7" , 5, 3, 410, "RAZ", 0, 1, 0ull, 0},
|
|
{"HIWATER" , 8, 5, 410, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_13_62" , 13, 50, 410, "RAZ", 0, 1, 0ull, 0},
|
|
{"BCKPRS" , 63, 1, 410, "RO", 0, 0, 0ull, 0ull},
|
|
{"BIST" , 0, 18, 411, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 411, "RAZ", 1, 1, 0, 0},
|
|
{"REFLECT" , 0, 1, 412, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INVRES" , 1, 1, 412, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 412, "RAZ", 1, 1, 0, 0},
|
|
{"IV" , 0, 32, 413, "R/W", 0, 0, 1185899593ull, 1185899593ull},
|
|
{"RESERVED_32_63" , 32, 32, 413, "RAZ", 1, 1, 0, 0},
|
|
{"DPRT" , 0, 16, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UDP" , 16, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP" , 17, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 414, "RAZ", 1, 1, 0, 0},
|
|
{"NIP_SHF" , 0, 3, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_7" , 3, 5, 415, "RAZ", 1, 1, 0, 0},
|
|
{"RAW_SHF" , 8, 3, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_15" , 11, 5, 415, "RAZ", 1, 1, 0, 0},
|
|
{"MAX_L2" , 16, 1, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_UDP" , 17, 1, 415, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TAG_SYN" , 18, 1, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 415, "RAZ", 1, 1, 0, 0},
|
|
{"IP_CHK" , 0, 1, 416, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP_MAL" , 1, 1, 416, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP_HOP" , 2, 1, 416, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP4_OPTS" , 3, 1, 416, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP6_EEXT" , 4, 2, 416, "R/W", 0, 0, 1ull, 3ull},
|
|
{"RESERVED_6_7" , 6, 2, 416, "RAZ", 0, 1, 0ull, 0},
|
|
{"L4_MAL" , 8, 1, 416, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_PRT" , 9, 1, 416, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_CHK" , 10, 1, 416, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_LEN" , 11, 1, 416, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TCP_FLAG" , 12, 1, 416, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L2_MAL" , 13, 1, 416, "R/W", 0, 0, 1ull, 1ull},
|
|
{"VS_QOS" , 14, 1, 416, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VS_WQE" , 15, 1, 416, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IGNRS" , 16, 1, 416, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 416, "RAZ", 0, 1, 0ull, 0},
|
|
{"PKTDRP" , 0, 1, 417, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CRCERR" , 1, 1, 417, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BCKPRS" , 2, 1, 417, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 3, 1, 417, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BADTAG" , 4, 1, 417, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPRUNT" , 5, 1, 417, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TODOOVR" , 6, 1, 417, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FEPERR" , 7, 1, 417, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BEPERR" , 8, 1, 417, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 417, "RAZ", 1, 1, 0, 0},
|
|
{"PKTDRP" , 0, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CRCERR" , 1, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BCKPRS" , 2, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 3, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BADTAG" , 4, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPRUNT" , 5, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TODOOVR" , 6, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FEPERR" , 7, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BEPERR" , 8, 1, 418, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 418, "RAZ", 1, 1, 0, 0},
|
|
{"OFFSET" , 0, 3, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 419, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP" , 0, 7, 420, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 420, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 8, 2, 420, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_11" , 10, 2, 420, "RAZ", 1, 1, 0, 0},
|
|
{"CRC_EN" , 12, 1, 420, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_13_15" , 13, 3, 420, "RAZ", 1, 1, 0, 0},
|
|
{"QOS_VLAN" , 16, 1, 420, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS_DIFF" , 17, 1, 420, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_19" , 18, 2, 420, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"QOS_WAT" , 20, 4, 420, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS" , 24, 3, 420, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 420, "RAZ", 1, 1, 0, 0},
|
|
{"GRP_WAT" , 28, 4, 420, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INST_HDR" , 32, 1, 420, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DYN_RS" , 33, 1, 420, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TAG_INC" , 34, 2, 420, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RAWDRP" , 36, 1, 420, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 420, "RAZ", 1, 1, 0, 0},
|
|
{"GRP" , 0, 4, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NON_TAG_TYPE" , 4, 2, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_TAG_TYPE" , 6, 2, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_TAG_TYPE" , 8, 2, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP4_TAG_TYPE" , 10, 2, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP6_TAG_TYPE" , 12, 2, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_SRC_FLAG" , 14, 1, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_SRC_FLAG" , 15, 1, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_DST_FLAG" , 16, 1, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_DST_FLAG" , 17, 1, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_PCTL_FLAG" , 18, 1, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_NXTH_FLAG" , 19, 1, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_SPRT_FLAG" , 20, 1, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_SPRT_FLAG" , 21, 1, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_DPRT_FLAG" , 22, 1, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_DPRT_FLAG" , 23, 1, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_PRT_FLAG" , 24, 1, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_VLAN" , 25, 1, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_VS" , 26, 2, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TAG_MODE" , 28, 2, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_30" , 30, 1, 421, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"GRPTAG" , 31, 1, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAGMASK" , 32, 4, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAGBASE" , 36, 4, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 421, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 0, 3, 422, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 422, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 0, 3, 423, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 423, "RAZ", 1, 1, 0, 0},
|
|
{"MATCH_VALUE" , 0, 16, 424, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MATCH_TYPE" , 16, 2, 424, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_19" , 18, 2, 424, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 20, 3, 424, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 424, "RAZ", 1, 1, 0, 0},
|
|
{"GRP" , 24, 4, 424, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_31" , 28, 4, 424, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 32, 16, 424, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 424, "RAZ", 1, 1, 0, 0},
|
|
{"WORD" , 0, 56, 425, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 425, "RAZ", 1, 1, 0, 0},
|
|
{"DRP_OCTS" , 0, 32, 426, "R/W", 0, 1, 0ull, 0},
|
|
{"DRP_PKTS" , 32, 32, 426, "R/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 427, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 427, "RAZ", 1, 1, 0, 0},
|
|
{"RAW" , 0, 32, 428, "R/W", 0, 1, 0ull, 0},
|
|
{"PKTS" , 32, 32, 428, "R/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 0, 32, 429, "R/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 32, 32, 429, "R/W", 0, 1, 0ull, 0},
|
|
{"H64" , 0, 32, 430, "R/W", 0, 1, 0ull, 0},
|
|
{"H65TO127" , 32, 32, 430, "R/W", 0, 1, 0ull, 0},
|
|
{"H128TO255" , 0, 32, 431, "R/W", 0, 1, 0ull, 0},
|
|
{"H256TO511" , 32, 32, 431, "R/W", 0, 1, 0ull, 0},
|
|
{"H512TO1023" , 0, 32, 432, "R/W", 0, 1, 0ull, 0},
|
|
{"H1024TO1518" , 32, 32, 432, "R/W", 0, 1, 0ull, 0},
|
|
{"H1519" , 0, 32, 433, "R/W", 0, 1, 0ull, 0},
|
|
{"FCS" , 32, 32, 433, "R/W", 0, 1, 0ull, 0},
|
|
{"UNDERSZ" , 0, 32, 434, "R/W", 0, 1, 0ull, 0},
|
|
{"FRAG" , 32, 32, 434, "R/W", 0, 1, 0ull, 0},
|
|
{"OVERSZ" , 0, 32, 435, "R/W", 0, 1, 0ull, 0},
|
|
{"JABBER" , 32, 32, 435, "R/W", 0, 1, 0ull, 0},
|
|
{"RDCLR" , 0, 1, 436, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 436, "RAZ", 1, 1, 0, 0},
|
|
{"ERRS" , 0, 16, 437, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 437, "RAZ", 1, 1, 0, 0},
|
|
{"OCTS" , 0, 48, 438, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 438, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 439, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 439, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 8, 440, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 440, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 0, 16, 441, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 441, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 16, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DST" , 16, 16, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 442, "RAZ", 1, 1, 0, 0},
|
|
{"ENTRY" , 0, 62, 443, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_62_62" , 62, 1, 443, "RAZ", 1, 1, 0, 0},
|
|
{"VAL" , 63, 1, 443, "RO", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 32, 444, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 444, "RAZ", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 48, 445, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 445, "RAZ", 1, 1, 0, 0},
|
|
{"SIZE" , 0, 16, 446, "RO", 1, 0, 0, 0ull},
|
|
{"SEGS" , 16, 6, 446, "RO", 1, 0, 0, 0ull},
|
|
{"CMD" , 22, 14, 446, "RO", 1, 0, 0, 0ull},
|
|
{"FAU" , 36, 28, 446, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 447, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 447, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 447, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 447, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 447, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 16, 448, "RO", 1, 0, 0, 0ull},
|
|
{"SEGS" , 16, 6, 448, "RO", 1, 0, 0, 0ull},
|
|
{"CMD" , 22, 14, 448, "RO", 1, 0, 0, 0ull},
|
|
{"FAU" , 36, 28, 448, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 449, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 449, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 449, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 449, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 449, "RO", 1, 0, 0, 0ull},
|
|
{"DATA" , 0, 64, 450, "RO", 1, 0, 0, 0ull},
|
|
{"WIDX2" , 0, 17, 451, "RO", 1, 0, 0, 0ull},
|
|
{"RIDX2" , 17, 17, 451, "RO", 1, 0, 0, 0ull},
|
|
{"WIDX" , 34, 17, 451, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_51_63" , 51, 13, 451, "RAZ", 1, 0, 0, 0ull},
|
|
{"RIDX" , 0, 17, 452, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 452, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 453, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 453, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 453, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 453, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 453, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 454, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 454, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 454, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 454, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 454, "RO", 1, 0, 0, 0ull},
|
|
{"DATA" , 0, 64, 455, "RO", 1, 0, 0, 0ull},
|
|
{"MAJOR" , 0, 4, 456, "RO", 1, 0, 0, 0ull},
|
|
{"MINOR" , 4, 2, 456, "RO", 1, 0, 0, 0ull},
|
|
{"WAIT" , 6, 1, 456, "RO", 1, 0, 0, 0ull},
|
|
{"QID_BASE" , 7, 7, 456, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFF" , 14, 3, 456, "RO", 1, 0, 0, 0ull},
|
|
{"QCB_RIDX" , 17, 5, 456, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 22, 3, 456, "RO", 1, 0, 0, 0ull},
|
|
{"ACTIVE" , 25, 1, 456, "RO", 1, 0, 0, 0ull},
|
|
{"CHK_MODE" , 26, 1, 456, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 456, "RAZ", 1, 0, 0, 0ull},
|
|
{"CBUF_FRE" , 28, 1, 456, "RO", 1, 0, 0, 0ull},
|
|
{"XFER_DWR" , 29, 1, 456, "RO", 1, 0, 0, 0ull},
|
|
{"XFER_WOR" , 30, 1, 456, "RO", 1, 0, 0, 0ull},
|
|
{"UID" , 31, 1, 456, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_SIZ" , 32, 16, 456, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_CNT" , 48, 13, 456, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_LEN" , 61, 1, 456, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_SOP" , 62, 1, 456, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_MOD" , 63, 1, 456, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_MOD" , 0, 2, 457, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_UID" , 2, 1, 457, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_CHK" , 3, 1, 457, "RO", 1, 0, 0, 0ull},
|
|
{"WORK_MIN" , 4, 3, 457, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 7, 1, 457, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFFM" , 8, 3, 457, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 457, "RAZ", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 16, 458, "RO", 1, 0, 0, 0ull},
|
|
{"START" , 16, 33, 458, "RO", 1, 0, 0, 0ull},
|
|
{"DWB" , 49, 9, 458, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_58_63" , 58, 6, 458, "RAZ", 1, 0, 0, 0ull},
|
|
{"QCB_RIDX" , 0, 6, 459, "RO", 1, 0, 0, 0ull},
|
|
{"QCB_WIDX" , 6, 6, 459, "RO", 1, 0, 0, 0ull},
|
|
{"BUF_PTR" , 12, 33, 459, "RO", 1, 0, 0, 0ull},
|
|
{"BUF_SIZ" , 45, 13, 459, "RO", 1, 0, 0, 0ull},
|
|
{"TAIL" , 58, 1, 459, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 59, 5, 459, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 0, 3, 460, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_Q" , 3, 1, 460, "RO", 1, 0, 0, 0ull},
|
|
{"S_TAIL" , 4, 1, 460, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 5, 1, 460, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 460, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 8, 20, 460, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 460, "RAZ", 1, 0, 0, 0ull},
|
|
{"QUEUE" , 0, 7, 461, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT" , 7, 6, 461, "WR0", 1, 0, 0, 0ull},
|
|
{"INDEX" , 13, 3, 461, "WR0", 1, 0, 0, 0ull},
|
|
{"TAIL" , 16, 1, 461, "R/W", 1, 0, 0, 0ull},
|
|
{"BUF_PTR" , 17, 36, 461, "R/W", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 461, "R/W", 1, 0, 0, 0ull},
|
|
{"STATIC_Q" , 61, 1, 461, "WR0", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 62, 1, 461, "WR0", 1, 0, 0, 0ull},
|
|
{"S_TAIL" , 63, 1, 461, "WR0", 1, 0, 0, 0ull},
|
|
{"QID" , 0, 7, 462, "R/W", 1, 0, 0, 0ull},
|
|
{"PID" , 7, 6, 462, "WR0", 1, 0, 0, 0ull},
|
|
{"RESERVED_13_52" , 13, 40, 462, "RAZ", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 462, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_61_63" , 61, 3, 462, "RAZ", 1, 0, 0, 0ull},
|
|
{"PSB" , 0, 7, 463, "RO", 1, 0, 0, 0ull},
|
|
{"PDB" , 7, 4, 463, "RO", 1, 0, 0, 0ull},
|
|
{"QCB" , 11, 2, 463, "RO", 1, 0, 0, 0ull},
|
|
{"QSB" , 13, 2, 463, "RO", 1, 0, 0, 0ull},
|
|
{"CHK" , 15, 1, 463, "RO", 1, 0, 0, 0ull},
|
|
{"CRC" , 16, 1, 463, "RO", 1, 0, 0, 0ull},
|
|
{"OUT" , 17, 1, 463, "RO", 1, 0, 0, 0ull},
|
|
{"NCB" , 18, 1, 463, "RO", 1, 0, 0, 0ull},
|
|
{"WIF" , 19, 1, 463, "RO", 1, 0, 0, 0ull},
|
|
{"RIF" , 20, 1, 463, "RO", 1, 0, 0, 0ull},
|
|
{"COUNT" , 21, 1, 463, "RO", 1, 0, 0, 0ull},
|
|
{"PSB2" , 22, 5, 463, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_27_63" , 27, 37, 463, "RAZ", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 13, 464, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_19" , 13, 7, 464, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 20, 3, 464, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 464, "RAZ", 1, 0, 0, 0ull},
|
|
{"REFIN" , 0, 1, 465, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INVRES" , 1, 1, 465, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 465, "RAZ", 1, 1, 0, 0},
|
|
{"ENABLE" , 0, 32, 466, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 466, "RAZ", 1, 0, 0, 0ull},
|
|
{"IV" , 0, 32, 467, "R/W", 0, 0, 1185899593ull, 1185899593ull},
|
|
{"RESERVED_32_63" , 32, 32, 467, "RAZ", 1, 1, 0, 0},
|
|
{"ASSERTS" , 0, 17, 468, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 468, "RAZ", 1, 0, 0, 0ull},
|
|
{"PARITY" , 0, 1, 469, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 1, 1, 469, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 469, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENA_PKO" , 0, 1, 470, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENA_DWB" , 1, 1, 470, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STORE_BE" , 2, 1, 470, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 3, 1, 470, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 470, "RAZ", 1, 0, 0, 0ull},
|
|
{"MODE0" , 0, 3, 471, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MODE1" , 3, 3, 471, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 471, "RAZ", 1, 0, 0, 0ull},
|
|
{"PARITY" , 0, 1, 472, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 1, 1, 472, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 472, "RAZ", 1, 0, 0, 0ull},
|
|
{"MODE" , 0, 2, 473, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 473, "RAZ", 1, 0, 0, 0ull},
|
|
{"INDEX" , 0, 8, 474, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 8, 8, 474, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 474, "RAZ", 1, 0, 0, 0ull},
|
|
{"ADR0" , 0, 1, 475, "RO", 0, 0, 0ull, 0ull},
|
|
{"ADR1" , 1, 1, 475, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEND0" , 2, 1, 475, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEND1" , 3, 1, 475, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBR0" , 4, 1, 475, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBR1" , 5, 1, 475, "RO", 0, 0, 0ull, 0ull},
|
|
{"FIDX" , 6, 1, 475, "RO", 0, 0, 0ull, 0ull},
|
|
{"INDEX" , 7, 1, 475, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBT" , 8, 1, 475, "RO", 0, 0, 0ull, 0ull},
|
|
{"CAM" , 9, 1, 475, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_15" , 10, 6, 475, "RAZ", 1, 1, 0, 0},
|
|
{"PP" , 16, 16, 475, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 475, "RAZ", 1, 1, 0, 0},
|
|
{"DS_PC" , 0, 32, 476, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 476, "RAZ", 1, 1, 0, 0},
|
|
{"SBE" , 0, 1, 477, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DBE" , 1, 1, 477, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SBE_IE" , 2, 1, 477, "R/W", 0, 1, 0ull, 0},
|
|
{"DBE_IE" , 3, 1, 477, "R/W", 0, 1, 0ull, 0},
|
|
{"SYN" , 4, 5, 477, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_9_11" , 9, 3, 477, "RAZ", 1, 1, 0, 0},
|
|
{"RPE" , 12, 1, 477, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPE_IE" , 13, 1, 477, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_63" , 14, 50, 477, "RAZ", 1, 1, 0, 0},
|
|
{"NBR_THR" , 0, 5, 478, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PFR_DIS" , 5, 1, 478, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 478, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 32, 479, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 479, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 32, 480, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 480, "RAZ", 1, 1, 0, 0},
|
|
{"NOS_CNT" , 0, 12, 481, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_12_63" , 12, 52, 481, "RAZ", 1, 1, 0, 0},
|
|
{"NW_TIM" , 0, 10, 482, "R/W", 0, 0, 0ull, 1023ull},
|
|
{"RESERVED_10_63" , 10, 54, 482, "RAZ", 1, 1, 0, 0},
|
|
{"GRP_MSK" , 0, 16, 483, "R/W", 0, 0, 65535ull, 65535ull},
|
|
{"RESERVED_16_63" , 16, 48, 483, "RAZ", 1, 1, 0, 0},
|
|
{"RND" , 0, 8, 484, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P1" , 8, 8, 484, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P2" , 16, 8, 484, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P3" , 24, 8, 484, "R/W", 0, 1, 255ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 484, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_THR" , 0, 11, 485, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_11_11" , 11, 1, 485, "RAZ", 1, 1, 0, 0},
|
|
{"MAX_THR" , 12, 11, 485, "R/W", 0, 1, 2047ull, 0},
|
|
{"RESERVED_23_23" , 23, 1, 485, "RAZ", 1, 1, 0, 0},
|
|
{"FREE_CNT" , 24, 12, 485, "RO", 0, 1, 2027ull, 0},
|
|
{"BUF_CNT" , 36, 12, 485, "RO", 0, 1, 0ull, 0},
|
|
{"DES_CNT" , 48, 12, 485, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 485, "RAZ", 1, 1, 0, 0},
|
|
{"TS_PC" , 0, 32, 486, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 486, "RAZ", 1, 1, 0, 0},
|
|
{"WA_PC" , 0, 32, 487, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 487, "RAZ", 1, 1, 0, 0},
|
|
{"WA_PC" , 0, 32, 488, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 488, "RAZ", 1, 1, 0, 0},
|
|
{"WQ_INT" , 0, 16, 489, "R/W1C", 0, 1, 0ull, 0},
|
|
{"IQ_DIS" , 16, 16, 489, "R/W1", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 489, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 12, 490, "RO", 0, 1, 0ull, 0},
|
|
{"DS_CNT" , 12, 12, 490, "RO", 0, 1, 0ull, 0},
|
|
{"TC_CNT" , 24, 4, 490, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_63" , 28, 36, 490, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 491, "RAZ", 1, 1, 0, 0},
|
|
{"PC_THR" , 8, 20, 491, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_31" , 28, 4, 491, "RAZ", 1, 1, 0, 0},
|
|
{"PC" , 32, 28, 491, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 491, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_THR" , 0, 11, 492, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_11_11" , 11, 1, 492, "RAZ", 1, 1, 0, 0},
|
|
{"DS_THR" , 12, 11, 492, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_23_23" , 23, 1, 492, "RAZ", 1, 1, 0, 0},
|
|
{"TC_THR" , 24, 4, 492, "R/W", 0, 1, 0ull, 0},
|
|
{"TC_EN" , 28, 1, 492, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 492, "RAZ", 1, 1, 0, 0},
|
|
{"WS_PC" , 0, 32, 493, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 493, "RAZ", 1, 1, 0, 0},
|
|
{"MEM" , 0, 1, 494, "RO", 0, 0, 0ull, 0ull},
|
|
{"RRC" , 1, 1, 494, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 494, "RAZ", 1, 1, 0, 0},
|
|
{"ENT_EN" , 0, 1, 495, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNG_EN" , 1, 1, 495, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNM_RST" , 2, 1, 495, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNG_RST" , 3, 1, 495, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 495, "RAZ", 1, 1, 0, 0},
|
|
{"PHASE" , 0, 8, 496, "R/W", 0, 0, 100ull, 100ull},
|
|
{"SAMPLE" , 8, 4, 496, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PREAMBLE" , 12, 1, 496, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CLK_IDLE" , 13, 1, 496, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_14" , 14, 1, 496, "RAZ", 1, 1, 0, 0},
|
|
{"SAMPLE_MODE" , 15, 1, 496, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SAMPLE_HI" , 16, 5, 496, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_63" , 21, 43, 496, "RAZ", 1, 1, 0, 0},
|
|
{"REG_ADR" , 0, 5, 497, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 497, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_ADR" , 8, 5, 497, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_13_15" , 13, 3, 497, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_OP" , 16, 1, 497, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_17_63" , 17, 47, 497, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 498, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 498, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 499, "RO", 0, 1, 0ull, 0},
|
|
{"VAL" , 16, 1, 499, "RO", 0, 1, 0ull, 0},
|
|
{"PENDING" , 17, 1, 499, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 499, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 500, "R/W", 0, 1, 0ull, 0},
|
|
{"VAL" , 16, 1, 500, "RO", 0, 1, 0ull, 0},
|
|
{"PENDING" , 17, 1, 500, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 500, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 501, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 501, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STAT0" , 0, 1, 502, "RO", 0, 0, 0ull, 0ull},
|
|
{"STAT1" , 1, 1, 502, "RO", 0, 0, 0ull, 0ull},
|
|
{"STAT2" , 2, 1, 502, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 502, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SRXDLCK" , 0, 1, 503, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RCVTRN" , 1, 1, 503, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DRPTRN" , 2, 1, 503, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SNDTRN" , 3, 1, 503, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STATRCV" , 4, 1, 503, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STATDRV" , 5, 1, 503, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RUNBIST" , 6, 1, 503, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLKDLY" , 7, 5, 503, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_12_15" , 12, 4, 503, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SEETRN" , 16, 1, 503, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 503, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_3" , 0, 4, 504, "RAZ", 0, 1, 0ull, 0},
|
|
{"D4CLK0" , 4, 1, 504, "R/W1C", 0, 1, 0ull, 0},
|
|
{"D4CLK1" , 5, 1, 504, "R/W1C", 0, 1, 0ull, 0},
|
|
{"S4CLK0" , 6, 1, 504, "R/W1C", 0, 1, 0ull, 0},
|
|
{"S4CLK1" , 7, 1, 504, "R/W1C", 0, 1, 0ull, 0},
|
|
{"SRXTRN" , 8, 1, 504, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_9_9" , 9, 1, 504, "RAZ", 0, 1, 0ull, 0},
|
|
{"STXCAL" , 10, 1, 504, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_11_63" , 11, 53, 504, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DLLDIS" , 0, 1, 505, "R/W", 1, 0, 0, 0ull},
|
|
{"DLLFRC" , 1, 1, 505, "WR0", 1, 0, 0, 0ull},
|
|
{"OFFDLY" , 2, 6, 505, "R/W", 1, 0, 0, 0ull},
|
|
{"BITSEL" , 8, 5, 505, "R/W", 1, 1, 0, 0},
|
|
{"OFFSET" , 13, 5, 505, "R/W", 1, 1, 0, 0},
|
|
{"MUX" , 18, 1, 505, "WR0", 1, 1, 0, 0},
|
|
{"INC" , 19, 1, 505, "WR0", 1, 1, 0, 0},
|
|
{"DEC" , 20, 1, 505, "WR0", 1, 1, 0, 0},
|
|
{"CLRDLY" , 21, 1, 505, "WR0", 1, 1, 0, 0},
|
|
{"RESERVED_22_23" , 22, 2, 505, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SSTEP" , 24, 1, 505, "R/W", 1, 0, 0, 0ull},
|
|
{"SSTEP_GO" , 25, 1, 505, "WR0", 1, 1, 0, 0},
|
|
{"RESERVED_26_27" , 26, 2, 505, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FALL8" , 28, 1, 505, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FALLNOP" , 29, 1, 505, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_63" , 30, 34, 505, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OFFSET" , 0, 5, 506, "RO", 0, 1, 0ull, 0},
|
|
{"MUXSEL" , 5, 2, 506, "RO", 0, 1, 0ull, 0},
|
|
{"UNXTERM" , 7, 1, 506, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TESTRES" , 8, 1, 506, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 506, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SRX4CMP" , 0, 8, 507, "R/W", 0, 1, 0ull, 0},
|
|
{"STX4PCMP" , 8, 4, 507, "R/W", 0, 1, 0ull, 0},
|
|
{"STX4NCMP" , 12, 4, 507, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 507, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ERRCNT" , 0, 4, 508, "R/W", 0, 0, 0ull, 3ull},
|
|
{"RESERVED_4_5" , 4, 2, 508, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DIPPAY" , 6, 1, 508, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DIPCLS" , 7, 1, 508, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 8, 1, 508, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 508, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRT" , 0, 8, 509, "RO", 0, 0, 0ull, 0ull},
|
|
{"RSVOP" , 8, 4, 509, "RO", 0, 0, 0ull, 0ull},
|
|
{"CALBNK" , 12, 2, 509, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_30" , 14, 17, 509, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MUL" , 31, 1, 509, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 509, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 0, 1, 510, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ABNORM" , 1, 1, 510, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_3" , 2, 2, 510, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SPIOVR" , 4, 1, 510, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLSERR" , 5, 1, 510, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRWNNG" , 6, 1, 510, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 7, 1, 510, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TPAOVR" , 8, 1, 510, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DIPERR" , 9, 1, 510, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SYNCERR" , 10, 1, 510, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CALERR" , 11, 1, 510, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 510, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 0, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ABNORM" , 1, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_3" , 2, 2, 511, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SPIOVR" , 4, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CLSERR" , 5, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DRWNNG" , 6, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 7, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TPAOVR" , 8, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DIPERR" , 9, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SYNCERR" , 10, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CALERR" , 11, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_30" , 12, 19, 511, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SPF" , 31, 1, 511, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 511, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 0, 1, 512, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ABNORM" , 1, 1, 512, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_3" , 2, 2, 512, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SPIOVR" , 4, 1, 512, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLSERR" , 5, 1, 512, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRWNNG" , 6, 1, 512, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 7, 1, 512, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TPAOVR" , 8, 1, 512, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DIPERR" , 9, 1, 512, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SYNCERR" , 10, 1, 512, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CALERR" , 11, 1, 512, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 512, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 0, 32, 513, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 513, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX" , 0, 32, 514, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 514, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRTSEL" , 0, 4, 515, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 515, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MUX_EN" , 0, 1, 516, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MACRO_EN" , 1, 1, 516, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAXDIST" , 2, 5, 516, "R/W", 0, 0, 0ull, 8ull},
|
|
{"SET_BOOT" , 7, 1, 516, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLR_BOOT" , 8, 1, 516, "R/W", 0, 0, 0ull, 0ull},
|
|
{"JITTER" , 9, 3, 516, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TRNTEST" , 12, 1, 516, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 516, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"BW_CTL" , 0, 5, 517, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 517, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SETTING" , 0, 17, 518, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_17_63" , 17, 47, 518, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"INF_EN" , 0, 1, 519, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_2" , 1, 2, 519, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ST_EN" , 3, 1, 519, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PRTS" , 4, 4, 519, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 519, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IGNORE" , 0, 16, 520, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 520, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRT0" , 0, 4, 521, "R/W", 1, 1, 0, 0},
|
|
{"PRT1" , 4, 4, 521, "R/W", 1, 1, 0, 0},
|
|
{"PRT2" , 8, 4, 521, "R/W", 1, 1, 0, 0},
|
|
{"PRT3" , 12, 4, 521, "R/W", 1, 1, 0, 0},
|
|
{"ODDPAR" , 16, 1, 521, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_17_63" , 17, 47, 521, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LEN" , 0, 7, 522, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_7" , 7, 1, 522, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"M" , 8, 8, 522, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 522, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_2" , 0, 3, 523, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IGNTPA" , 3, 1, 523, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_4" , 4, 1, 523, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MINTRN" , 5, 1, 523, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 523, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 0, 32, 524, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 524, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"INF_EN" , 0, 1, 525, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_2" , 1, 2, 525, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ST_EN" , 3, 1, 525, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 525, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DIPMAX" , 0, 4, 526, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMMAX" , 4, 4, 526, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 526, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IGNTPA" , 0, 16, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 527, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CALPAR0" , 0, 1, 528, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CALPAR1" , 1, 1, 528, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OVRBST" , 2, 1, 528, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DATOVR" , 3, 1, 528, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DIPERR" , 4, 1, 528, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NOSYNC" , 5, 1, 528, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UNXFRM" , 6, 1, 528, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMERR" , 7, 1, 528, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 528, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CALPAR0" , 0, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CALPAR1" , 1, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OVRBST" , 2, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DATOVR" , 3, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DIPERR" , 4, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NOSYNC" , 5, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UNXFRM" , 6, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FRMERR" , 7, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SYNCERR" , 8, 1, 529, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 529, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CALPAR0" , 0, 1, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CALPAR1" , 1, 1, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OVRBST" , 2, 1, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DATOVR" , 3, 1, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DIPERR" , 4, 1, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NOSYNC" , 5, 1, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UNXFRM" , 6, 1, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMERR" , 7, 1, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 530, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MINB" , 0, 9, 531, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 531, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRT0" , 0, 4, 532, "R/W", 1, 1, 0, 0},
|
|
{"PRT1" , 4, 4, 532, "R/W", 1, 1, 0, 0},
|
|
{"PRT2" , 8, 4, 532, "R/W", 1, 1, 0, 0},
|
|
{"PRT3" , 12, 4, 532, "R/W", 1, 1, 0, 0},
|
|
{"ODDPAR" , 16, 1, 532, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_17_63" , 17, 47, 532, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX_T" , 0, 16, 533, "R/W", 0, 1, 0ull, 0},
|
|
{"ALPHA" , 16, 16, 533, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 533, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LEN" , 0, 7, 534, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_7" , 7, 1, 534, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"M" , 8, 8, 534, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 534, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 0, 32, 535, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 535, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 0, 32, 536, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 536, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"BCKPRS" , 0, 4, 537, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLR" , 4, 1, 537, "WR0", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 537, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 0, 32, 538, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 538, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"INTERVAL" , 0, 22, 539, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 539, "RAZ", 1, 0, 0, 0ull},
|
|
{"COUNT" , 24, 22, 539, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_46_46" , 46, 1, 539, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENA" , 47, 1, 539, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 539, "RAZ", 1, 0, 0, 0ull},
|
|
{"BSIZE" , 0, 20, 540, "RO", 1, 0, 0, 0ull},
|
|
{"BASE" , 20, 31, 540, "RO", 1, 0, 0, 0ull},
|
|
{"BUCKET" , 51, 13, 540, "RO", 1, 0, 0, 0ull},
|
|
{"BUCKET" , 0, 7, 541, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 541, "RAZ", 1, 0, 0, 0ull},
|
|
{"CSIZE" , 8, 13, 541, "RO", 1, 0, 0, 0ull},
|
|
{"CPOOL" , 21, 3, 541, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 541, "RAZ", 1, 0, 0, 0ull},
|
|
{"RING" , 0, 4, 542, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NUM_BUCKETS" , 4, 20, 542, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIRST_BUCKET" , 24, 31, 542, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_55_63" , 55, 9, 542, "RAZ", 1, 0, 0, 0ull},
|
|
{"RING" , 0, 4, 543, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTERVAL" , 4, 22, 543, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WORDS_PER_CHUNK" , 26, 13, 543, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 39, 3, 543, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENABLE" , 42, 1, 543, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_43_63" , 43, 21, 543, "RAZ", 1, 0, 0, 0ull},
|
|
{"CTL" , 0, 1, 544, "RO", 1, 0, 0, 0ull},
|
|
{"NCB" , 1, 1, 544, "RO", 1, 0, 0, 0ull},
|
|
{"STA" , 2, 2, 544, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 544, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 16, 545, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 545, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENABLE_TIMERS" , 0, 1, 546, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENABLE_DWB" , 1, 1, 546, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 2, 1, 546, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 546, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 16, 547, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 547, "RAZ", 1, 0, 0, 0ull},
|
|
{"INDEX" , 0, 8, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 8, 8, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 548, "RAZ", 1, 0, 0, 0ull},
|
|
{"TDF0" , 0, 1, 549, "RO", 0, 0, 0ull, 0ull},
|
|
{"TDF1" , 1, 1, 549, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCF" , 2, 1, 549, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 549, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ENA" , 0, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WRAP" , 1, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRIG_CTL" , 2, 2, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIME_GRN" , 4, 3, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FULL_THR" , 7, 2, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CIU_TRG" , 9, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CIU_THR" , 10, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_TRG" , 11, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_THR" , 12, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_ENA" , 13, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IGNORE_O" , 14, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 550, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WPTR" , 0, 8, 551, "RO", 0, 0, 0ull, 0ull},
|
|
{"RPTR" , 8, 8, 551, "RO", 0, 0, 0ull, 0ull},
|
|
{"CYCLES" , 16, 48, 551, "RO", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 552, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 552, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 553, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 553, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 554, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 554, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 554, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 554, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 554, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 554, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 554, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 554, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 554, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 554, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 554, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 554, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 554, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 554, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 554, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 554, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_16_63" , 16, 48, 554, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 555, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 555, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 555, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 555, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 555, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 555, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 555, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 555, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 555, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 555, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 555, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 555, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 556, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CIU_TRG" , 0, 1, 557, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CIU_THR" , 1, 1, 557, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MCD0_TRG" , 2, 1, 557, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MCD0_THR" , 3, 1, 557, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 557, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DATA" , 0, 64, 558, "RO", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 559, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 559, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 560, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 561, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 561, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 561, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 561, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 561, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 561, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 561, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 561, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 561, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 561, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 561, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 561, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 561, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 561, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 561, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 561, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_16_63" , 16, 48, 561, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 562, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 562, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 562, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 562, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 562, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 562, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 562, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 562, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 562, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 562, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 562, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 562, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 563, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 564, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 564, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 565, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 565, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 566, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 566, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 566, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 566, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 566, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 566, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 566, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 566, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 566, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 566, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 566, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 566, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 566, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 566, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 566, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 566, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_16_63" , 16, 48, 566, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 567, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 567, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 567, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 567, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 567, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 567, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 567, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 567, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 567, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 567, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 567, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 567, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 568, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 568, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 568, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 568, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 568, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 568, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ZIP_CTL" , 0, 4, 569, "RO", 1, 0, 0, 0ull},
|
|
{"ZIP_CORE" , 4, 27, 569, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 569, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 33, 570, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 33, 13, 570, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 46, 3, 570, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 49, 9, 570, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_58_63" , 58, 6, 570, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 0, 1, 571, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FORCECLK" , 1, 1, 571, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 571, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DISABLED" , 0, 1, 572, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_7" , 1, 7, 572, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CTXSIZE" , 8, 12, 572, "RO", 0, 0, 1536ull, 1536ull},
|
|
{"ONFSIZE" , 20, 12, 572, "RO", 0, 0, 512ull, 512ull},
|
|
{"DEPTH" , 32, 16, 572, "RO", 0, 0, 15360ull, 15360ull},
|
|
{"RESERVED_48_63" , 48, 16, 572, "RAZ", 1, 0, 0, 0ull},
|
|
{"ASSERTS" , 0, 14, 573, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 573, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 0, 1, 574, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 574, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 0, 1, 575, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 575, "RAZ", 1, 0, 0, 0ull},
|
|
{NULL,0,0,0,0,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn31xx[] = {
|
|
/* name , ---------------type, bits, off, #field, fld of */
|
|
{"cvmx_asx#_gmii_rx_clk_set" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 2, 0},
|
|
{"cvmx_asx#_gmii_rx_dat_set" , CVMX_CSR_DB_TYPE_RSL, 64, 1, 2, 2},
|
|
{"cvmx_asx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 6, 4},
|
|
{"cvmx_asx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 3, 6, 10},
|
|
{"cvmx_asx#_prt_loop" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 4, 16},
|
|
{"cvmx_asx#_rx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 5, 2, 20},
|
|
{"cvmx_asx#_rx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 8, 2, 22},
|
|
{"cvmx_asx#_tx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 9, 2, 24},
|
|
{"cvmx_asx#_tx_comp_byp" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 4, 26},
|
|
{"cvmx_asx#_tx_hi_water#" , CVMX_CSR_DB_TYPE_RSL, 64, 13, 2, 30},
|
|
{"cvmx_asx#_tx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 2, 32},
|
|
{"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 17, 2, 34},
|
|
{"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 18, 2, 36},
|
|
{"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 19, 2, 38},
|
|
{"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 20, 2, 40},
|
|
{"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 21, 19, 42},
|
|
{"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 26, 2, 61},
|
|
{"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 31, 19, 63},
|
|
{"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 36, 2, 82},
|
|
{"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 37, 2, 84},
|
|
{"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 39, 2, 86},
|
|
{"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 41, 2, 88},
|
|
{"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 42, 2, 90},
|
|
{"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 43, 2, 92},
|
|
{"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 44, 1, 94},
|
|
{"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 46, 3, 95},
|
|
{"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 47, 2, 98},
|
|
{"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 48, 4, 100},
|
|
{"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 49, 2, 104},
|
|
{"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 50, 3, 106},
|
|
{"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 54, 7, 109},
|
|
{"cvmx_dbg_data" , CVMX_CSR_DB_TYPE_NCB, 64, 56, 6, 116},
|
|
{"cvmx_dfa_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 57, 3, 122},
|
|
{"cvmx_dfa_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 58, 7, 125},
|
|
{"cvmx_dfa_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 59, 2, 132},
|
|
{"cvmx_dfa_ddr2_addr" , CVMX_CSR_DB_TYPE_RSL, 64, 60, 6, 134},
|
|
{"cvmx_dfa_ddr2_bus" , CVMX_CSR_DB_TYPE_RSL, 64, 61, 2, 140},
|
|
{"cvmx_dfa_ddr2_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 62, 16, 142},
|
|
{"cvmx_dfa_ddr2_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 63, 6, 158},
|
|
{"cvmx_dfa_ddr2_emrs" , CVMX_CSR_DB_TYPE_RSL, 64, 64, 4, 164},
|
|
{"cvmx_dfa_ddr2_fcnt" , CVMX_CSR_DB_TYPE_RSL, 64, 65, 2, 168},
|
|
{"cvmx_dfa_ddr2_mrs" , CVMX_CSR_DB_TYPE_RSL, 64, 66, 4, 170},
|
|
{"cvmx_dfa_ddr2_opt" , CVMX_CSR_DB_TYPE_RSL, 64, 67, 3, 174},
|
|
{"cvmx_dfa_ddr2_pll" , CVMX_CSR_DB_TYPE_RSL, 64, 68, 14, 177},
|
|
{"cvmx_dfa_ddr2_tmg" , CVMX_CSR_DB_TYPE_RSL, 64, 69, 21, 191},
|
|
{"cvmx_dfa_difctl" , CVMX_CSR_DB_TYPE_NCB, 64, 70, 4, 212},
|
|
{"cvmx_dfa_difrdptr" , CVMX_CSR_DB_TYPE_NCB, 64, 71, 3, 216},
|
|
{"cvmx_dfa_eclkcfg" , CVMX_CSR_DB_TYPE_RSL, 64, 72, 14, 219},
|
|
{"cvmx_dfa_err" , CVMX_CSR_DB_TYPE_RSL, 64, 73, 21, 233},
|
|
{"cvmx_dfa_memfadr" , CVMX_CSR_DB_TYPE_RSL, 64, 74, 6, 254},
|
|
{"cvmx_dfa_sbd_dbg0" , CVMX_CSR_DB_TYPE_RSL, 64, 75, 1, 260},
|
|
{"cvmx_dfa_sbd_dbg1" , CVMX_CSR_DB_TYPE_RSL, 64, 76, 1, 261},
|
|
{"cvmx_dfa_sbd_dbg2" , CVMX_CSR_DB_TYPE_RSL, 64, 77, 1, 262},
|
|
{"cvmx_dfa_sbd_dbg3" , CVMX_CSR_DB_TYPE_RSL, 64, 78, 1, 263},
|
|
{"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 79, 6, 264},
|
|
{"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 80, 7, 270},
|
|
{"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 81, 29, 277},
|
|
{"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 82, 29, 306},
|
|
{"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 83, 2, 335},
|
|
{"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 91, 2, 337},
|
|
{"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 99, 3, 339},
|
|
{"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 100, 3, 342},
|
|
{"cvmx_fpa_wart_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 101, 2, 345},
|
|
{"cvmx_fpa_wart_status" , CVMX_CSR_DB_TYPE_RSL, 64, 102, 2, 347},
|
|
{"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 103, 8, 349},
|
|
{"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 104, 2, 357},
|
|
{"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 105, 3, 359},
|
|
{"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 106, 2, 362},
|
|
{"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 107, 5, 364},
|
|
{"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 110, 1, 369},
|
|
{"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 113, 1, 370},
|
|
{"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 116, 1, 371},
|
|
{"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 119, 1, 372},
|
|
{"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 122, 1, 373},
|
|
{"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 125, 1, 374},
|
|
{"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 128, 2, 375},
|
|
{"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 131, 4, 377},
|
|
{"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 134, 2, 381},
|
|
{"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 137, 11, 383},
|
|
{"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 140, 9, 394},
|
|
{"cvmx_gmx#_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 143, 2, 403},
|
|
{"cvmx_gmx#_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 146, 2, 405},
|
|
{"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 149, 2, 407},
|
|
{"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 152, 20, 409},
|
|
{"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 155, 20, 429},
|
|
{"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 158, 2, 449},
|
|
{"cvmx_gmx#_rx#_rx_inbnd" , CVMX_CSR_DB_TYPE_RSL, 64, 161, 4, 451},
|
|
{"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 164, 2, 455},
|
|
{"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 167, 2, 457},
|
|
{"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 170, 2, 459},
|
|
{"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 173, 2, 461},
|
|
{"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 176, 2, 463},
|
|
{"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 179, 2, 465},
|
|
{"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 182, 2, 467},
|
|
{"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 185, 2, 469},
|
|
{"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 188, 2, 471},
|
|
{"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 191, 2, 473},
|
|
{"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 194, 4, 475},
|
|
{"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 197, 2, 479},
|
|
{"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 200, 2, 481},
|
|
{"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 203, 2, 483},
|
|
{"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 206, 4, 485},
|
|
{"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 207, 2, 489},
|
|
{"cvmx_gmx#_rx_tx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 208, 4, 491},
|
|
{"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 209, 2, 495},
|
|
{"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 212, 3, 497},
|
|
{"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 213, 5, 500},
|
|
{"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 216, 2, 505},
|
|
{"cvmx_gmx#_tx#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 219, 2, 507},
|
|
{"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 222, 3, 509},
|
|
{"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 225, 2, 512},
|
|
{"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 228, 2, 514},
|
|
{"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 231, 2, 516},
|
|
{"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 234, 2, 518},
|
|
{"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 237, 2, 520},
|
|
{"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 240, 2, 522},
|
|
{"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 243, 2, 524},
|
|
{"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 246, 2, 526},
|
|
{"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 249, 2, 528},
|
|
{"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 252, 2, 530},
|
|
{"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 255, 2, 532},
|
|
{"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 258, 2, 534},
|
|
{"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 261, 2, 536},
|
|
{"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 264, 2, 538},
|
|
{"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 267, 2, 540},
|
|
{"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 270, 2, 542},
|
|
{"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 273, 2, 544},
|
|
{"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 276, 2, 546},
|
|
{"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 279, 2, 548},
|
|
{"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 282, 2, 550},
|
|
{"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 283, 2, 552},
|
|
{"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 284, 2, 554},
|
|
{"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 285, 3, 556},
|
|
{"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 286, 8, 559},
|
|
{"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 287, 8, 567},
|
|
{"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 288, 2, 575},
|
|
{"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 289, 2, 577},
|
|
{"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 290, 6, 579},
|
|
{"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 291, 2, 585},
|
|
{"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 292, 2, 587},
|
|
{"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 293, 2, 589},
|
|
{"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 294, 7, 591},
|
|
{"cvmx_gpio_boot_ena" , CVMX_CSR_DB_TYPE_NCB, 64, 310, 3, 598},
|
|
{"cvmx_gpio_dbg_ena" , CVMX_CSR_DB_TYPE_NCB, 64, 311, 2, 601},
|
|
{"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 312, 2, 603},
|
|
{"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 313, 2, 605},
|
|
{"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 314, 2, 607},
|
|
{"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 315, 2, 609},
|
|
{"cvmx_gpio_xbit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 316, 6, 611},
|
|
{"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 324, 19, 617},
|
|
{"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 325, 6, 636},
|
|
{"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 326, 3, 642},
|
|
{"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 327, 5, 645},
|
|
{"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 328, 5, 650},
|
|
{"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 329, 1, 655},
|
|
{"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 330, 1, 656},
|
|
{"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 331, 5, 657},
|
|
{"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 332, 5, 662},
|
|
{"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 333, 5, 667},
|
|
{"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 334, 5, 672},
|
|
{"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 335, 1, 677},
|
|
{"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 336, 1, 678},
|
|
{"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 337, 2, 679},
|
|
{"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 338, 2, 681},
|
|
{"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 339, 2, 683},
|
|
{"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 340, 2, 685},
|
|
{"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 341, 17, 687},
|
|
{"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 342, 2, 704},
|
|
{"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 343, 1, 706},
|
|
{"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 344, 10, 707},
|
|
{"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 345, 6, 717},
|
|
{"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 346, 6, 723},
|
|
{"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 347, 2, 729},
|
|
{"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 348, 2, 731},
|
|
{"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 349, 2, 733},
|
|
{"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 350, 3, 735},
|
|
{"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 355, 2, 738},
|
|
{"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 360, 6, 740},
|
|
{"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 361, 5, 746},
|
|
{"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 362, 6, 751},
|
|
{"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 363, 7, 757},
|
|
{"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 364, 2, 764},
|
|
{"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 372, 2, 766},
|
|
{"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 373, 3, 768},
|
|
{"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 374, 5, 771},
|
|
{"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 382, 3, 776},
|
|
{"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 383, 2, 779},
|
|
{"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 384, 2, 781},
|
|
{"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 385, 2, 783},
|
|
{"cvmx_l2c_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 386, 7, 785},
|
|
{"cvmx_l2c_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 387, 6, 792},
|
|
{"cvmx_l2c_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 388, 8, 798},
|
|
{"cvmx_l2c_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 389, 9, 806},
|
|
{"cvmx_l2c_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 390, 10, 815},
|
|
{"cvmx_l2c_dut" , CVMX_CSR_DB_TYPE_RSL, 64, 391, 5, 825},
|
|
{"cvmx_l2c_lckbase" , CVMX_CSR_DB_TYPE_RSL, 64, 392, 4, 830},
|
|
{"cvmx_l2c_lckoff" , CVMX_CSR_DB_TYPE_RSL, 64, 393, 2, 834},
|
|
{"cvmx_l2c_lfb0" , CVMX_CSR_DB_TYPE_RSL, 64, 394, 17, 836},
|
|
{"cvmx_l2c_lfb1" , CVMX_CSR_DB_TYPE_RSL, 64, 395, 19, 853},
|
|
{"cvmx_l2c_lfb2" , CVMX_CSR_DB_TYPE_RSL, 64, 396, 3, 872},
|
|
{"cvmx_l2c_lfb3" , CVMX_CSR_DB_TYPE_RSL, 64, 397, 4, 875},
|
|
{"cvmx_l2c_pfc#" , CVMX_CSR_DB_TYPE_RSL, 64, 398, 2, 879},
|
|
{"cvmx_l2c_pfctl" , CVMX_CSR_DB_TYPE_RSL, 64, 402, 17, 881},
|
|
{"cvmx_l2c_spar0" , CVMX_CSR_DB_TYPE_RSL, 64, 403, 4, 898},
|
|
{"cvmx_l2c_spar4" , CVMX_CSR_DB_TYPE_RSL, 64, 404, 2, 902},
|
|
{"cvmx_l2d_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 405, 3, 904},
|
|
{"cvmx_l2d_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 406, 2, 907},
|
|
{"cvmx_l2d_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 407, 2, 909},
|
|
{"cvmx_l2d_bst3" , CVMX_CSR_DB_TYPE_RSL, 64, 408, 2, 911},
|
|
{"cvmx_l2d_err" , CVMX_CSR_DB_TYPE_RSL, 64, 409, 7, 913},
|
|
{"cvmx_l2d_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 410, 6, 920},
|
|
{"cvmx_l2d_fsyn0" , CVMX_CSR_DB_TYPE_RSL, 64, 411, 3, 926},
|
|
{"cvmx_l2d_fsyn1" , CVMX_CSR_DB_TYPE_RSL, 64, 412, 3, 929},
|
|
{"cvmx_l2d_fus0" , CVMX_CSR_DB_TYPE_RSL, 64, 413, 2, 932},
|
|
{"cvmx_l2d_fus1" , CVMX_CSR_DB_TYPE_RSL, 64, 414, 2, 934},
|
|
{"cvmx_l2d_fus2" , CVMX_CSR_DB_TYPE_RSL, 64, 415, 2, 936},
|
|
{"cvmx_l2d_fus3" , CVMX_CSR_DB_TYPE_RSL, 64, 416, 3, 938},
|
|
{"cvmx_l2t_err" , CVMX_CSR_DB_TYPE_RSL, 64, 417, 15, 941},
|
|
{"cvmx_lmc#_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 418, 9, 956},
|
|
{"cvmx_lmc#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 419, 20, 965},
|
|
{"cvmx_lmc#_dclk_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 420, 2, 985},
|
|
{"cvmx_lmc#_dclk_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 421, 2, 987},
|
|
{"cvmx_lmc#_ddr2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 422, 18, 989},
|
|
{"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 423, 5, 1007},
|
|
{"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 424, 6, 1012},
|
|
{"cvmx_lmc#_ifb_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 425, 2, 1018},
|
|
{"cvmx_lmc#_ifb_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 426, 2, 1020},
|
|
{"cvmx_lmc#_mem_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 427, 14, 1022},
|
|
{"cvmx_lmc#_mem_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 428, 10, 1036},
|
|
{"cvmx_lmc#_ops_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 429, 2, 1046},
|
|
{"cvmx_lmc#_ops_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 430, 2, 1048},
|
|
{"cvmx_lmc#_pll_bwctl" , CVMX_CSR_DB_TYPE_RSL, 64, 431, 3, 1050},
|
|
{"cvmx_lmc#_rodt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 432, 9, 1053},
|
|
{"cvmx_lmc#_wodt_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 433, 5, 1062},
|
|
{"cvmx_lmc#_wodt_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 434, 5, 1067},
|
|
{"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 435, 5, 1072},
|
|
{"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 436, 3, 1077},
|
|
{"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 437, 3, 1080},
|
|
{"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 438, 3, 1083},
|
|
{"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 439, 5, 1086},
|
|
{"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 441, 1, 1091},
|
|
{"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 442, 10, 1092},
|
|
{"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 450, 13, 1102},
|
|
{"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 458, 4, 1115},
|
|
{"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 459, 2, 1119},
|
|
{"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 460, 2, 1121},
|
|
{"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 461, 10, 1123},
|
|
{"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 462, 9, 1133},
|
|
{"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 463, 2, 1142},
|
|
{"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 464, 8, 1144},
|
|
{"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 465, 4, 1152},
|
|
{"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 466, 2, 1156},
|
|
{"cvmx_mio_fus_unlock" , CVMX_CSR_DB_TYPE_RSL, 64, 467, 2, 1158},
|
|
{"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 468, 2, 1160},
|
|
{"cvmx_mio_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 469, 2, 1162},
|
|
{"cvmx_mio_pll_setting" , CVMX_CSR_DB_TYPE_RSL, 64, 470, 2, 1164},
|
|
{"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 471, 13, 1166},
|
|
{"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 472, 12, 1179},
|
|
{"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 473, 3, 1191},
|
|
{"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 474, 3, 1194},
|
|
{"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 475, 2, 1197},
|
|
{"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 477, 2, 1199},
|
|
{"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 479, 2, 1201},
|
|
{"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 481, 7, 1203},
|
|
{"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 483, 2, 1210},
|
|
{"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 485, 7, 1212},
|
|
{"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 487, 4, 1219},
|
|
{"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 489, 8, 1223},
|
|
{"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 491, 9, 1231},
|
|
{"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 493, 7, 1240},
|
|
{"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 495, 9, 1247},
|
|
{"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 497, 2, 1256},
|
|
{"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 499, 2, 1258},
|
|
{"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 501, 4, 1260},
|
|
{"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 503, 2, 1264},
|
|
{"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 505, 2, 1266},
|
|
{"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 507, 2, 1268},
|
|
{"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 509, 4, 1270},
|
|
{"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 511, 2, 1274},
|
|
{"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 513, 2, 1276},
|
|
{"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 515, 2, 1278},
|
|
{"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 517, 2, 1280},
|
|
{"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 519, 2, 1282},
|
|
{"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 521, 2, 1284},
|
|
{"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 523, 6, 1286},
|
|
{"cvmx_mpi_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 525, 13, 1292},
|
|
{"cvmx_mpi_dat#" , CVMX_CSR_DB_TYPE_NCB, 64, 526, 2, 1305},
|
|
{"cvmx_mpi_sts" , CVMX_CSR_DB_TYPE_NCB, 64, 535, 4, 1307},
|
|
{"cvmx_mpi_tx" , CVMX_CSR_DB_TYPE_NCB, 64, 536, 6, 1311},
|
|
{"cvmx_npi_base_addr_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 537, 2, 1317},
|
|
{"cvmx_npi_base_addr_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 539, 2, 1319},
|
|
{"cvmx_npi_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 541, 21, 1321},
|
|
{"cvmx_npi_buff_size_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 542, 3, 1342},
|
|
{"cvmx_npi_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 544, 18, 1345},
|
|
{"cvmx_npi_dbg_select" , CVMX_CSR_DB_TYPE_NCB, 64, 545, 2, 1363},
|
|
{"cvmx_npi_dma_control" , CVMX_CSR_DB_TYPE_NCB, 64, 546, 13, 1365},
|
|
{"cvmx_npi_dma_highp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 547, 3, 1378},
|
|
{"cvmx_npi_dma_highp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 548, 3, 1381},
|
|
{"cvmx_npi_dma_lowp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 549, 3, 1384},
|
|
{"cvmx_npi_dma_lowp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 550, 3, 1387},
|
|
{"cvmx_npi_highp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 551, 2, 1390},
|
|
{"cvmx_npi_highp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 552, 2, 1392},
|
|
{"cvmx_npi_input_control" , CVMX_CSR_DB_TYPE_NCB, 64, 553, 9, 1394},
|
|
{"cvmx_npi_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 554, 54, 1403},
|
|
{"cvmx_npi_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 555, 54, 1457},
|
|
{"cvmx_npi_lowp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 556, 2, 1511},
|
|
{"cvmx_npi_lowp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 557, 2, 1513},
|
|
{"cvmx_npi_mem_access_subid#" , CVMX_CSR_DB_TYPE_NCB, 64, 558, 8, 1515},
|
|
{"cvmx_npi_msi_rcv" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 562, 1, 1523},
|
|
{"cvmx_npi_num_desc_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 563, 2, 1524},
|
|
{"cvmx_npi_output_control" , CVMX_CSR_DB_TYPE_NCB, 64, 565, 23, 1526},
|
|
{"cvmx_npi_p#_dbpair_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 566, 3, 1549},
|
|
{"cvmx_npi_p#_instr_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 568, 2, 1552},
|
|
{"cvmx_npi_p#_instr_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 570, 3, 1554},
|
|
{"cvmx_npi_p#_pair_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 572, 3, 1557},
|
|
{"cvmx_npi_pci_burst_size" , CVMX_CSR_DB_TYPE_NCB, 64, 574, 3, 1560},
|
|
{"cvmx_npi_pci_int_arb_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 575, 4, 1563},
|
|
{"cvmx_npi_pci_read_cmd" , CVMX_CSR_DB_TYPE_NCB, 64, 576, 2, 1567},
|
|
{"cvmx_npi_port32_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 577, 13, 1569},
|
|
{"cvmx_npi_port33_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 578, 13, 1582},
|
|
{"cvmx_npi_port_bp_control" , CVMX_CSR_DB_TYPE_NCB, 64, 579, 3, 1595},
|
|
{"cvmx_npi_rsl_int_blocks" , CVMX_CSR_DB_TYPE_NCB, 64, 580, 33, 1598},
|
|
{"cvmx_npi_size_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 581, 2, 1631},
|
|
{"cvmx_npi_win_read_to" , CVMX_CSR_DB_TYPE_NCB, 64, 583, 2, 1633},
|
|
{"cvmx_pci_bar1_index#" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 584, 5, 1635},
|
|
{"cvmx_pci_cfg00" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 616, 2, 1640},
|
|
{"cvmx_pci_cfg01" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 617, 24, 1642},
|
|
{"cvmx_pci_cfg02" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 618, 2, 1666},
|
|
{"cvmx_pci_cfg03" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 619, 7, 1668},
|
|
{"cvmx_pci_cfg04" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 620, 5, 1675},
|
|
{"cvmx_pci_cfg05" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 621, 1, 1680},
|
|
{"cvmx_pci_cfg06" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 622, 5, 1681},
|
|
{"cvmx_pci_cfg07" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 623, 1, 1686},
|
|
{"cvmx_pci_cfg08" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 624, 4, 1687},
|
|
{"cvmx_pci_cfg09" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 625, 2, 1691},
|
|
{"cvmx_pci_cfg10" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 626, 1, 1693},
|
|
{"cvmx_pci_cfg11" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 627, 2, 1694},
|
|
{"cvmx_pci_cfg12" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 628, 4, 1696},
|
|
{"cvmx_pci_cfg13" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 629, 2, 1700},
|
|
{"cvmx_pci_cfg15" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 630, 4, 1702},
|
|
{"cvmx_pci_cfg16" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 631, 16, 1706},
|
|
{"cvmx_pci_cfg17" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 632, 1, 1722},
|
|
{"cvmx_pci_cfg18" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 633, 1, 1723},
|
|
{"cvmx_pci_cfg19" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 634, 18, 1724},
|
|
{"cvmx_pci_cfg20" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 635, 1, 1742},
|
|
{"cvmx_pci_cfg21" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 636, 1, 1743},
|
|
{"cvmx_pci_cfg22" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 637, 7, 1744},
|
|
{"cvmx_pci_cfg56" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 638, 7, 1751},
|
|
{"cvmx_pci_cfg57" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 639, 13, 1758},
|
|
{"cvmx_pci_cfg58" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 640, 10, 1771},
|
|
{"cvmx_pci_cfg59" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 641, 10, 1781},
|
|
{"cvmx_pci_cfg60" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 642, 7, 1791},
|
|
{"cvmx_pci_cfg61" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 643, 2, 1798},
|
|
{"cvmx_pci_cfg62" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 644, 1, 1800},
|
|
{"cvmx_pci_cfg63" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 645, 2, 1801},
|
|
{"cvmx_pci_ctl_status_2" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 646, 16, 1803},
|
|
{"cvmx_pci_dbell#" , CVMX_CSR_DB_TYPE_PCI, 32, 647, 2, 1819},
|
|
{"cvmx_pci_dma_cnt#" , CVMX_CSR_DB_TYPE_PCI, 32, 649, 1, 1821},
|
|
{"cvmx_pci_dma_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 651, 1, 1822},
|
|
{"cvmx_pci_dma_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 653, 1, 1823},
|
|
{"cvmx_pci_instr_count#" , CVMX_CSR_DB_TYPE_PCI, 32, 655, 1, 1824},
|
|
{"cvmx_pci_int_enb" , CVMX_CSR_DB_TYPE_PCI, 64, 657, 33, 1825},
|
|
{"cvmx_pci_int_enb2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 658, 33, 1858},
|
|
{"cvmx_pci_int_sum" , CVMX_CSR_DB_TYPE_PCI, 64, 659, 33, 1891},
|
|
{"cvmx_pci_int_sum2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 660, 33, 1924},
|
|
{"cvmx_pci_msi_rcv" , CVMX_CSR_DB_TYPE_PCI, 32, 661, 2, 1957},
|
|
{"cvmx_pci_pkt_credits#" , CVMX_CSR_DB_TYPE_PCI, 32, 662, 2, 1959},
|
|
{"cvmx_pci_pkts_sent#" , CVMX_CSR_DB_TYPE_PCI, 32, 664, 1, 1961},
|
|
{"cvmx_pci_pkts_sent_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 666, 1, 1962},
|
|
{"cvmx_pci_pkts_sent_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 668, 1, 1963},
|
|
{"cvmx_pci_read_cmd_6" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 670, 3, 1964},
|
|
{"cvmx_pci_read_cmd_c" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 671, 3, 1967},
|
|
{"cvmx_pci_read_cmd_e" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 672, 3, 1970},
|
|
{"cvmx_pci_read_timeout" , CVMX_CSR_DB_TYPE_NCB, 64, 673, 3, 1973},
|
|
{"cvmx_pci_scm_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 674, 2, 1976},
|
|
{"cvmx_pci_tsr_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 675, 2, 1978},
|
|
{"cvmx_pci_win_rd_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 676, 4, 1980},
|
|
{"cvmx_pci_win_rd_data" , CVMX_CSR_DB_TYPE_PCI, 64, 677, 1, 1984},
|
|
{"cvmx_pci_win_wr_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 678, 4, 1985},
|
|
{"cvmx_pci_win_wr_data" , CVMX_CSR_DB_TYPE_PCI, 64, 679, 1, 1989},
|
|
{"cvmx_pci_win_wr_mask" , CVMX_CSR_DB_TYPE_PCI, 64, 680, 2, 1990},
|
|
{"cvmx_pcm#_dma_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 681, 12, 1992},
|
|
{"cvmx_pcm#_int_ena" , CVMX_CSR_DB_TYPE_NCB, 64, 685, 9, 2004},
|
|
{"cvmx_pcm#_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 689, 9, 2013},
|
|
{"cvmx_pcm#_rxaddr" , CVMX_CSR_DB_TYPE_NCB, 64, 693, 2, 2022},
|
|
{"cvmx_pcm#_rxcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 697, 2, 2024},
|
|
{"cvmx_pcm#_rxmsk0" , CVMX_CSR_DB_TYPE_NCB, 64, 701, 1, 2026},
|
|
{"cvmx_pcm#_rxmsk1" , CVMX_CSR_DB_TYPE_NCB, 64, 705, 1, 2027},
|
|
{"cvmx_pcm#_rxmsk2" , CVMX_CSR_DB_TYPE_NCB, 64, 709, 1, 2028},
|
|
{"cvmx_pcm#_rxmsk3" , CVMX_CSR_DB_TYPE_NCB, 64, 713, 1, 2029},
|
|
{"cvmx_pcm#_rxmsk4" , CVMX_CSR_DB_TYPE_NCB, 64, 717, 1, 2030},
|
|
{"cvmx_pcm#_rxmsk5" , CVMX_CSR_DB_TYPE_NCB, 64, 721, 1, 2031},
|
|
{"cvmx_pcm#_rxmsk6" , CVMX_CSR_DB_TYPE_NCB, 64, 725, 1, 2032},
|
|
{"cvmx_pcm#_rxmsk7" , CVMX_CSR_DB_TYPE_NCB, 64, 729, 1, 2033},
|
|
{"cvmx_pcm#_rxstart" , CVMX_CSR_DB_TYPE_NCB, 64, 733, 3, 2034},
|
|
{"cvmx_pcm#_tdm_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 737, 6, 2037},
|
|
{"cvmx_pcm#_tdm_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 741, 1, 2043},
|
|
{"cvmx_pcm#_txaddr" , CVMX_CSR_DB_TYPE_NCB, 64, 745, 3, 2044},
|
|
{"cvmx_pcm#_txcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 749, 2, 2047},
|
|
{"cvmx_pcm#_txmsk0" , CVMX_CSR_DB_TYPE_NCB, 64, 753, 1, 2049},
|
|
{"cvmx_pcm#_txmsk1" , CVMX_CSR_DB_TYPE_NCB, 64, 757, 1, 2050},
|
|
{"cvmx_pcm#_txmsk2" , CVMX_CSR_DB_TYPE_NCB, 64, 761, 1, 2051},
|
|
{"cvmx_pcm#_txmsk3" , CVMX_CSR_DB_TYPE_NCB, 64, 765, 1, 2052},
|
|
{"cvmx_pcm#_txmsk4" , CVMX_CSR_DB_TYPE_NCB, 64, 769, 1, 2053},
|
|
{"cvmx_pcm#_txmsk5" , CVMX_CSR_DB_TYPE_NCB, 64, 773, 1, 2054},
|
|
{"cvmx_pcm#_txmsk6" , CVMX_CSR_DB_TYPE_NCB, 64, 777, 1, 2055},
|
|
{"cvmx_pcm#_txmsk7" , CVMX_CSR_DB_TYPE_NCB, 64, 781, 1, 2056},
|
|
{"cvmx_pcm#_txstart" , CVMX_CSR_DB_TYPE_NCB, 64, 785, 3, 2057},
|
|
{"cvmx_pcm_clk#_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 789, 12, 2060},
|
|
{"cvmx_pcm_clk#_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 791, 1, 2072},
|
|
{"cvmx_pcm_clk#_gen" , CVMX_CSR_DB_TYPE_NCB, 64, 793, 3, 2073},
|
|
{"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 795, 2, 2076},
|
|
{"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 796, 4, 2078},
|
|
{"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 800, 8, 2082},
|
|
{"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 801, 16, 2090},
|
|
{"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 802, 10, 2106},
|
|
{"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 803, 10, 2116},
|
|
{"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 804, 2, 2126},
|
|
{"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 805, 16, 2128},
|
|
{"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 810, 25, 2144},
|
|
{"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 815, 2, 2169},
|
|
{"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 879, 2, 2171},
|
|
{"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 887, 9, 2173},
|
|
{"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 891, 2, 2182},
|
|
{"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 892, 2, 2184},
|
|
{"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 893, 2, 2186},
|
|
{"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 898, 2, 2188},
|
|
{"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 903, 2, 2190},
|
|
{"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 908, 2, 2192},
|
|
{"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 913, 2, 2194},
|
|
{"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 918, 2, 2196},
|
|
{"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 923, 2, 2198},
|
|
{"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 928, 2, 2200},
|
|
{"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 933, 2, 2202},
|
|
{"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 938, 2, 2204},
|
|
{"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 943, 2, 2206},
|
|
{"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 944, 2, 2208},
|
|
{"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 949, 2, 2210},
|
|
{"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 954, 2, 2212},
|
|
{"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 959, 2, 2214},
|
|
{"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1023, 2, 2216},
|
|
{"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 1024, 3, 2218},
|
|
{"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 1025, 3, 2221},
|
|
{"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 1026, 2, 2224},
|
|
{"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 1027, 2, 2226},
|
|
{"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1028, 4, 2228},
|
|
{"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 1029, 5, 2232},
|
|
{"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 1030, 4, 2237},
|
|
{"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 1031, 5, 2241},
|
|
{"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 1032, 1, 2246},
|
|
{"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 1033, 4, 2247},
|
|
{"cvmx_pko_mem_debug14" , CVMX_CSR_DB_TYPE_RSL, 64, 1034, 2, 2251},
|
|
{"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 1035, 5, 2253},
|
|
{"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 1036, 5, 2258},
|
|
{"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 1037, 1, 2263},
|
|
{"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 1038, 19, 2264},
|
|
{"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 1039, 7, 2283},
|
|
{"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 1040, 4, 2290},
|
|
{"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 1041, 6, 2294},
|
|
{"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 1042, 6, 2300},
|
|
{"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 1043, 9, 2306},
|
|
{"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 1044, 5, 2315},
|
|
{"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1045, 13, 2320},
|
|
{"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 1046, 4, 2333},
|
|
{"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1047, 2, 2337},
|
|
{"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 1048, 3, 2339},
|
|
{"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 1049, 5, 2342},
|
|
{"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 1050, 3, 2347},
|
|
{"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1051, 3, 2350},
|
|
{"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 1052, 2, 2353},
|
|
{"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 1053, 3, 2355},
|
|
{"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 1054, 12, 2358},
|
|
{"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1055, 2, 2370},
|
|
{"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 1056, 9, 2372},
|
|
{"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1057, 3, 2381},
|
|
{"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 1058, 2, 2384},
|
|
{"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1066, 2, 2386},
|
|
{"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1067, 2, 2388},
|
|
{"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 1068, 2, 2390},
|
|
{"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 1069, 2, 2392},
|
|
{"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 1071, 5, 2394},
|
|
{"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 1079, 10, 2399},
|
|
{"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1087, 2, 2409},
|
|
{"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1088, 2, 2411},
|
|
{"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 1089, 2, 2413},
|
|
{"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 1097, 3, 2415},
|
|
{"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 1098, 6, 2418},
|
|
{"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1114, 5, 2424},
|
|
{"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 1115, 7, 2429},
|
|
{"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 1131, 2, 2436},
|
|
{"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1147, 3, 2438},
|
|
{"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1148, 5, 2441},
|
|
{"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 1149, 8, 2446},
|
|
{"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1150, 6, 2454},
|
|
{"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1151, 2, 2460},
|
|
{"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1152, 4, 2462},
|
|
{"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1153, 4, 2466},
|
|
{"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1154, 6, 2470},
|
|
{"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 1155, 3, 2476},
|
|
{"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 1156, 5, 2479},
|
|
{"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 1157, 4, 2484},
|
|
{"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 1158, 6, 2488},
|
|
{"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1159, 4, 2494},
|
|
{"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 1160, 2, 2498},
|
|
{"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 1161, 4, 2500},
|
|
{"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1162, 2, 2504},
|
|
{"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 1163, 3, 2506},
|
|
{"cvmx_tra_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1164, 4, 2509},
|
|
{"cvmx_tra_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1165, 12, 2513},
|
|
{"cvmx_tra_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 1166, 3, 2525},
|
|
{"cvmx_tra_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1167, 2, 2528},
|
|
{"cvmx_tra_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 1168, 2, 2530},
|
|
{"cvmx_tra_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1169, 17, 2532},
|
|
{"cvmx_tra_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 1170, 12, 2549},
|
|
{"cvmx_tra_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 1171, 6, 2561},
|
|
{"cvmx_tra_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1172, 5, 2567},
|
|
{"cvmx_tra_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1173, 1, 2572},
|
|
{"cvmx_tra_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1174, 2, 2573},
|
|
{"cvmx_tra_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 1175, 2, 2575},
|
|
{"cvmx_tra_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1176, 17, 2577},
|
|
{"cvmx_tra_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 1177, 12, 2594},
|
|
{"cvmx_tra_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 1178, 6, 2606},
|
|
{"cvmx_tra_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1179, 2, 2612},
|
|
{"cvmx_tra_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 1180, 2, 2614},
|
|
{"cvmx_tra_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1181, 17, 2616},
|
|
{"cvmx_tra_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 1182, 12, 2633},
|
|
{"cvmx_tra_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 1183, 6, 2645},
|
|
{"cvmx_usbc#_daint" , CVMX_CSR_DB_TYPE_NCB, 32, 1184, 2, 2651},
|
|
{"cvmx_usbc#_daintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1185, 2, 2653},
|
|
{"cvmx_usbc#_dcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1186, 8, 2655},
|
|
{"cvmx_usbc#_dctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1187, 11, 2663},
|
|
{"cvmx_usbc#_diepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 1188, 15, 2674},
|
|
{"cvmx_usbc#_diepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1193, 8, 2689},
|
|
{"cvmx_usbc#_diepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1198, 8, 2697},
|
|
{"cvmx_usbc#_dieptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1199, 4, 2705},
|
|
{"cvmx_usbc#_doepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 1204, 15, 2709},
|
|
{"cvmx_usbc#_doepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1209, 6, 2724},
|
|
{"cvmx_usbc#_doepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1214, 6, 2730},
|
|
{"cvmx_usbc#_doeptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1215, 4, 2736},
|
|
{"cvmx_usbc#_dptxfsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1220, 2, 2740},
|
|
{"cvmx_usbc#_dsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1224, 6, 2742},
|
|
{"cvmx_usbc#_dtknqr1" , CVMX_CSR_DB_TYPE_NCB, 32, 1225, 4, 2748},
|
|
{"cvmx_usbc#_dtknqr2" , CVMX_CSR_DB_TYPE_NCB, 32, 1226, 1, 2752},
|
|
{"cvmx_usbc#_dtknqr3" , CVMX_CSR_DB_TYPE_NCB, 32, 1227, 1, 2753},
|
|
{"cvmx_usbc#_dtknqr4" , CVMX_CSR_DB_TYPE_NCB, 32, 1228, 1, 2754},
|
|
{"cvmx_usbc#_gahbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1229, 7, 2755},
|
|
{"cvmx_usbc#_ghwcfg1" , CVMX_CSR_DB_TYPE_NCB, 32, 1230, 1, 2762},
|
|
{"cvmx_usbc#_ghwcfg2" , CVMX_CSR_DB_TYPE_NCB, 32, 1231, 14, 2763},
|
|
{"cvmx_usbc#_ghwcfg3" , CVMX_CSR_DB_TYPE_NCB, 32, 1232, 10, 2777},
|
|
{"cvmx_usbc#_ghwcfg4" , CVMX_CSR_DB_TYPE_NCB, 32, 1233, 12, 2787},
|
|
{"cvmx_usbc#_gintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1234, 32, 2799},
|
|
{"cvmx_usbc#_gintsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1235, 32, 2831},
|
|
{"cvmx_usbc#_gnptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1236, 2, 2863},
|
|
{"cvmx_usbc#_gnptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1237, 4, 2865},
|
|
{"cvmx_usbc#_gotgctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1238, 13, 2869},
|
|
{"cvmx_usbc#_gotgint" , CVMX_CSR_DB_TYPE_NCB, 32, 1239, 10, 2882},
|
|
{"cvmx_usbc#_grstctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1240, 10, 2892},
|
|
{"cvmx_usbc#_grxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1241, 2, 2902},
|
|
{"cvmx_usbc#_grxstspd" , CVMX_CSR_DB_TYPE_NCB, 32, 1242, 6, 2904},
|
|
{"cvmx_usbc#_grxstsph" , CVMX_CSR_DB_TYPE_NCB, 32, 1243, 5, 2910},
|
|
{"cvmx_usbc#_grxstsrd" , CVMX_CSR_DB_TYPE_NCB, 32, 1244, 6, 2915},
|
|
{"cvmx_usbc#_grxstsrh" , CVMX_CSR_DB_TYPE_NCB, 32, 1245, 5, 2921},
|
|
{"cvmx_usbc#_gsnpsid" , CVMX_CSR_DB_TYPE_NCB, 32, 1246, 1, 2926},
|
|
{"cvmx_usbc#_gusbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1247, 13, 2927},
|
|
{"cvmx_usbc#_haint" , CVMX_CSR_DB_TYPE_NCB, 32, 1248, 2, 2940},
|
|
{"cvmx_usbc#_haintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1249, 2, 2942},
|
|
{"cvmx_usbc#_hcchar#" , CVMX_CSR_DB_TYPE_NCB, 32, 1250, 11, 2944},
|
|
{"cvmx_usbc#_hcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1258, 3, 2955},
|
|
{"cvmx_usbc#_hcint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1259, 12, 2958},
|
|
{"cvmx_usbc#_hcintmsk#" , CVMX_CSR_DB_TYPE_NCB, 32, 1267, 12, 2970},
|
|
{"cvmx_usbc#_hcsplt#" , CVMX_CSR_DB_TYPE_NCB, 32, 1275, 6, 2982},
|
|
{"cvmx_usbc#_hctsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1283, 4, 2988},
|
|
{"cvmx_usbc#_hfir" , CVMX_CSR_DB_TYPE_NCB, 32, 1291, 2, 2992},
|
|
{"cvmx_usbc#_hfnum" , CVMX_CSR_DB_TYPE_NCB, 32, 1292, 2, 2994},
|
|
{"cvmx_usbc#_hprt" , CVMX_CSR_DB_TYPE_NCB, 32, 1293, 15, 2996},
|
|
{"cvmx_usbc#_hptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1294, 2, 3011},
|
|
{"cvmx_usbc#_hptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1295, 3, 3013},
|
|
{"cvmx_usbc#_nptxdfifo#" , CVMX_CSR_DB_TYPE_NCB, 32, 1296, 1, 3016},
|
|
{"cvmx_usbc#_pcgcctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1304, 6, 3017},
|
|
{"cvmx_usbn#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1305, 4, 3023},
|
|
{"cvmx_usbn#_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1306, 15, 3027},
|
|
{"cvmx_usbn#_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1307, 6, 3042},
|
|
{"cvmx_usbn#_dma0_inb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 1308, 2, 3048},
|
|
{"cvmx_usbn#_dma0_inb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 1309, 2, 3050},
|
|
{"cvmx_usbn#_dma0_inb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 1310, 2, 3052},
|
|
{"cvmx_usbn#_dma0_inb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 1311, 2, 3054},
|
|
{"cvmx_usbn#_dma0_inb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 1312, 2, 3056},
|
|
{"cvmx_usbn#_dma0_inb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 1313, 2, 3058},
|
|
{"cvmx_usbn#_dma0_inb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 1314, 2, 3060},
|
|
{"cvmx_usbn#_dma0_inb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 1315, 2, 3062},
|
|
{"cvmx_usbn#_dma0_outb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 1316, 2, 3064},
|
|
{"cvmx_usbn#_dma0_outb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 1317, 2, 3066},
|
|
{"cvmx_usbn#_dma0_outb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 1318, 2, 3068},
|
|
{"cvmx_usbn#_dma0_outb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 1319, 2, 3070},
|
|
{"cvmx_usbn#_dma0_outb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 1320, 2, 3072},
|
|
{"cvmx_usbn#_dma0_outb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 1321, 2, 3074},
|
|
{"cvmx_usbn#_dma0_outb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 1322, 2, 3076},
|
|
{"cvmx_usbn#_dma0_outb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 1323, 2, 3078},
|
|
{"cvmx_usbn#_dma_test" , CVMX_CSR_DB_TYPE_NCB, 64, 1324, 7, 3080},
|
|
{"cvmx_usbn#_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1325, 39, 3087},
|
|
{"cvmx_usbn#_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1326, 39, 3126},
|
|
{"cvmx_usbn#_usbp_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1327, 22, 3165},
|
|
{"cvmx_zip_cmd_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1328, 3, 3187},
|
|
{"cvmx_zip_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 1329, 5, 3190},
|
|
{"cvmx_zip_cmd_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1330, 3, 3195},
|
|
{"cvmx_zip_constants" , CVMX_CSR_DB_TYPE_RSL, 64, 1331, 6, 3198},
|
|
{"cvmx_zip_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1332, 2, 3204},
|
|
{"cvmx_zip_error" , CVMX_CSR_DB_TYPE_RSL, 64, 1333, 2, 3206},
|
|
{"cvmx_zip_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1334, 2, 3208},
|
|
{NULL,0,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
|
|
/* name , --------------address, ---------------type, bits, csr offset */
|
|
{"ASX0_GMII_RX_CLK_SET" , 0x11800B0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
|
|
{"ASX0_GMII_RX_DAT_SET" , 0x11800B0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
|
|
{"ASX0_INT_EN" , 0x11800B0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
|
|
{"ASX0_INT_REG" , 0x11800B0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
|
|
{"ASX0_PRT_LOOP" , 0x11800B0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
|
|
{"ASX0_RX_CLK_SET000" , 0x11800B0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
|
|
{"ASX0_RX_CLK_SET001" , 0x11800B0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
|
|
{"ASX0_RX_CLK_SET002" , 0x11800B0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
|
|
{"ASX0_RX_PRT_EN" , 0x11800B0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
|
|
{"ASX0_TX_CLK_SET000" , 0x11800B0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
|
|
{"ASX0_TX_CLK_SET001" , 0x11800B0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
|
|
{"ASX0_TX_CLK_SET002" , 0x11800B0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
|
|
{"ASX0_TX_COMP_BYP" , 0x11800B0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
|
|
{"ASX0_TX_HI_WATER000" , 0x11800B0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
|
|
{"ASX0_TX_HI_WATER001" , 0x11800B0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
|
|
{"ASX0_TX_HI_WATER002" , 0x11800B0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
|
|
{"ASX0_TX_PRT_EN" , 0x11800B0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
|
|
{"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 11},
|
|
{"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 12},
|
|
{"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 13},
|
|
{"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 14},
|
|
{"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 15},
|
|
{"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 15},
|
|
{"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 15},
|
|
{"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 15},
|
|
{"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 15},
|
|
{"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
|
|
{"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
|
|
{"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
|
|
{"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
|
|
{"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
|
|
{"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
|
|
{"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
|
|
{"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
|
|
{"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
|
|
{"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
|
|
{"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 18},
|
|
{"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 19},
|
|
{"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 19},
|
|
{"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
|
|
{"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
|
|
{"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 21},
|
|
{"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 22},
|
|
{"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 23},
|
|
{"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"DBG_DATA" , 0x11F00000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"DFA_BST0" , 0x11800300007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
|
|
{"DFA_BST1" , 0x11800300007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
|
|
{"DFA_DBELL" , 0x1370000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"DFA_DDR2_ADDR" , 0x1180030000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
|
|
{"DFA_DDR2_BUS" , 0x1180030000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
|
|
{"DFA_DDR2_CFG" , 0x1180030000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
|
|
{"DFA_DDR2_COMP" , 0x1180030000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
|
|
{"DFA_DDR2_EMRS" , 0x1180030000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
|
|
{"DFA_DDR2_FCNT" , 0x1180030000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
|
|
{"DFA_DDR2_MRS" , 0x1180030000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
|
|
{"DFA_DDR2_OPT" , 0x1180030000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
|
|
{"DFA_DDR2_PLL" , 0x1180030000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
|
|
{"DFA_DDR2_TMG" , 0x1180030000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
|
|
{"DFA_DIFCTL" , 0x1370600000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 45},
|
|
{"DFA_DIFRDPTR" , 0x1370200000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 46},
|
|
{"DFA_ECLKCFG" , 0x1180030000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
|
|
{"DFA_ERR" , 0x1180030000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
|
|
{"DFA_MEMFADR" , 0x1180030000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
|
|
{"DFA_SBD_DBG0" , 0x1180030000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
|
|
{"DFA_SBD_DBG1" , 0x1180030000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
|
|
{"DFA_SBD_DBG2" , 0x1180030000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
|
|
{"DFA_SBD_DBG3" , 0x1180030000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
|
|
{"FPA_BIST_STATUS" , 0x11800280000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
|
|
{"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
|
|
{"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
|
|
{"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
|
|
{"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
|
|
{"FPA_QUE1_AVAILABLE" , 0x11800280000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
|
|
{"FPA_QUE2_AVAILABLE" , 0x11800280000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
|
|
{"FPA_QUE3_AVAILABLE" , 0x11800280000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
|
|
{"FPA_QUE4_AVAILABLE" , 0x11800280000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
|
|
{"FPA_QUE5_AVAILABLE" , 0x11800280000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
|
|
{"FPA_QUE6_AVAILABLE" , 0x11800280000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
|
|
{"FPA_QUE7_AVAILABLE" , 0x11800280000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
|
|
{"FPA_QUE0_PAGE_INDEX" , 0x11800280000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
|
|
{"FPA_QUE1_PAGE_INDEX" , 0x11800280000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
|
|
{"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
|
|
{"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
|
|
{"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
|
|
{"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
|
|
{"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
|
|
{"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
|
|
{"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
|
|
{"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
|
|
{"FPA_WART_CTL" , 0x11800280000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
|
|
{"FPA_WART_STATUS" , 0x11800280000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
|
|
{"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
|
|
{"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
|
|
{"GMX0_INF_MODE" , 0x11800080007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
|
|
{"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
|
|
{"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
|
|
{"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
|
|
{"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
|
|
{"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
|
|
{"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
|
|
{"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
|
|
{"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
|
|
{"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
|
|
{"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
|
|
{"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
|
|
{"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"GMX0_RX000_ADR_CAM4" , 0x11800080001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"GMX0_RX001_ADR_CAM4" , 0x11800080009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"GMX0_RX002_ADR_CAM4" , 0x11800080011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"GMX0_RX000_ADR_CAM5" , 0x11800080001A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
|
|
{"GMX0_RX001_ADR_CAM5" , 0x11800080009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
|
|
{"GMX0_RX002_ADR_CAM5" , 0x11800080011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
|
|
{"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
|
|
{"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
|
|
{"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
|
|
{"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
|
|
{"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
|
|
{"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
|
|
{"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
|
|
{"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
|
|
{"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
|
|
{"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
|
|
{"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
|
|
{"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
|
|
{"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
|
|
{"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
|
|
{"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
|
|
{"GMX0_RX000_FRM_MAX" , 0x1180008000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
|
|
{"GMX0_RX001_FRM_MAX" , 0x1180008000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
|
|
{"GMX0_RX002_FRM_MAX" , 0x1180008001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
|
|
{"GMX0_RX000_FRM_MIN" , 0x1180008000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
|
|
{"GMX0_RX001_FRM_MIN" , 0x1180008000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
|
|
{"GMX0_RX002_FRM_MIN" , 0x1180008001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
|
|
{"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX0_RX000_RX_INBND" , 0x1180008000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX0_RX001_RX_INBND" , 0x1180008000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX0_RX002_RX_INBND" , 0x1180008001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_RX_PRT_INFO" , 0x11800080004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX0_RX_TX_STATUS" , 0x11800080007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_SMAC001" , 0x1180008000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_TX001_APPEND" , 0x1180008000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_TX001_BURST" , 0x1180008000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_TX000_CLK" , 0x1180008000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX0_TX001_CLK" , 0x1180008000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX0_TX002_CLK" , 0x1180008001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_TX001_CTL" , 0x1180008000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX0_TX001_MIN_PKT" , 0x1180008000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX0_TX001_PAUSE_TOGO" , 0x1180008000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_TX001_PAUSE_ZERO" , 0x1180008000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX0_TX001_SLOT" , 0x1180008000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_TX001_SOFT_PAUSE" , 0x1180008000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX0_TX001_STAT0" , 0x1180008000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX0_TX001_STAT1" , 0x1180008000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_TX001_STAT2" , 0x1180008000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX0_TX001_STAT3" , 0x1180008000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX0_TX000_STAT4" , 0x11800080002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_TX001_STAT4" , 0x1180008000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_TX002_STAT4" , 0x11800080012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_TX000_STAT5" , 0x11800080002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_TX001_STAT5" , 0x1180008000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_TX002_STAT5" , 0x11800080012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_TX000_STAT6" , 0x11800080002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_TX001_STAT6" , 0x1180008000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_TX002_STAT6" , 0x11800080012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_TX000_STAT7" , 0x11800080002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_TX001_STAT7" , 0x1180008000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_TX002_STAT7" , 0x11800080012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_TX000_STAT8" , 0x11800080002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_TX001_STAT8" , 0x1180008000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_TX002_STAT8" , 0x11800080012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_TX000_STAT9" , 0x11800080002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_TX001_STAT9" , 0x1180008000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_TX002_STAT9" , 0x11800080012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_TX001_STATS_CTL" , 0x1180008000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_TX001_THRESH" , 0x1180008000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_TX_BP" , 0x11800080004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_TX_CORRUPT" , 0x11800080004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_TX_LFSR" , 0x11800080004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_TX_OVR_BP" , 0x11800080004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
|
|
{"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
|
|
{"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
|
|
{"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
|
|
{"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
|
|
{"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
|
|
{"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
|
|
{"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
|
|
{"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
|
|
{"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
|
|
{"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
|
|
{"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
|
|
{"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
|
|
{"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
|
|
{"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
|
|
{"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 141},
|
|
{"GPIO_BOOT_ENA" , 0x10700000008A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 142},
|
|
{"GPIO_DBG_ENA" , 0x10700000008A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
|
|
{"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
|
|
{"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
|
|
{"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
|
|
{"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
|
|
{"GPIO_XBIT_CFG16" , 0x1070000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
|
|
{"GPIO_XBIT_CFG17" , 0x1070000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
|
|
{"GPIO_XBIT_CFG18" , 0x1070000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
|
|
{"GPIO_XBIT_CFG19" , 0x1070000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
|
|
{"GPIO_XBIT_CFG20" , 0x1070000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
|
|
{"GPIO_XBIT_CFG21" , 0x1070000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
|
|
{"GPIO_XBIT_CFG22" , 0x1070000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
|
|
{"GPIO_XBIT_CFG23" , 0x1070000000938ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
|
|
{"IOB_BIST_STATUS" , 0x11800F00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"IOB_CTL_STATUS" , 0x11800F0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"IOB_FAU_TIMEOUT" , 0x11800F0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"IOB_INB_CONTROL_MATCH" , 0x11800F0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"IOB_INB_CONTROL_MATCH_ENB" , 0x11800F0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"IOB_INB_DATA_MATCH" , 0x11800F0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"IOB_INB_DATA_MATCH_ENB" , 0x11800F0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"IOB_INT_ENB" , 0x11800F0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"IOB_INT_SUM" , 0x11800F0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"IOB_OUTB_CONTROL_MATCH" , 0x11800F0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
|
|
{"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800F00000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"IOB_OUTB_DATA_MATCH" , 0x11800F0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
|
|
{"IOB_OUTB_DATA_MATCH_ENB" , 0x11800F00000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
|
|
{"IOB_PKT_ERR" , 0x11800F0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
|
|
{"IPD_1ST_MBUFF_SKIP" , 0x14F0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
|
|
{"IPD_1ST_NEXT_PTR_BACK" , 0x14F0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
|
|
{"IPD_2ND_NEXT_PTR_BACK" , 0x14F0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
|
|
{"IPD_BIST_STATUS" , 0x14F00000007F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
|
|
{"IPD_BP_PRT_RED_END" , 0x14F0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
|
|
{"IPD_CLK_COUNT" , 0x14F0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
|
|
{"IPD_CTL_STATUS" , 0x14F0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
|
|
{"IPD_INT_ENB" , 0x14F0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
|
|
{"IPD_INT_SUM" , 0x14F0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
|
|
{"IPD_NOT_1ST_MBUFF_SKIP" , 0x14F0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
|
|
{"IPD_PACKET_MBUFF_SIZE" , 0x14F0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
|
|
{"IPD_PKT_PTR_VALID" , 0x14F0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 174},
|
|
{"IPD_PORT0_BP_PAGE_CNT" , 0x14F0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
|
|
{"IPD_PORT1_BP_PAGE_CNT" , 0x14F0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
|
|
{"IPD_PORT2_BP_PAGE_CNT" , 0x14F0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
|
|
{"IPD_PORT32_BP_PAGE_CNT" , 0x14F0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
|
|
{"IPD_PORT33_BP_PAGE_CNT" , 0x14F0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 175},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14F00000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14F00000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14F00000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14F00000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR33" , 0x14F00000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 176},
|
|
{"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14F0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 177},
|
|
{"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14F0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 178},
|
|
{"IPD_PTR_COUNT" , 0x14F0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 179},
|
|
{"IPD_PWP_PTR_FIFO_CTL" , 0x14F0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 180},
|
|
{"IPD_QOS0_RED_MARKS" , 0x14F0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
|
|
{"IPD_QOS1_RED_MARKS" , 0x14F0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
|
|
{"IPD_QOS2_RED_MARKS" , 0x14F0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
|
|
{"IPD_QOS3_RED_MARKS" , 0x14F0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
|
|
{"IPD_QOS4_RED_MARKS" , 0x14F0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
|
|
{"IPD_QOS5_RED_MARKS" , 0x14F00000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
|
|
{"IPD_QOS6_RED_MARKS" , 0x14F00000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
|
|
{"IPD_QOS7_RED_MARKS" , 0x14F00000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 181},
|
|
{"IPD_QUE0_FREE_PAGE_CNT" , 0x14F0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 182},
|
|
{"IPD_RED_PORT_ENABLE" , 0x14F00000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 183},
|
|
{"IPD_RED_QUE0_PARAM" , 0x14F00000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
|
|
{"IPD_RED_QUE1_PARAM" , 0x14F00000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
|
|
{"IPD_RED_QUE2_PARAM" , 0x14F00000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
|
|
{"IPD_RED_QUE3_PARAM" , 0x14F00000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
|
|
{"IPD_RED_QUE4_PARAM" , 0x14F0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
|
|
{"IPD_RED_QUE5_PARAM" , 0x14F0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
|
|
{"IPD_RED_QUE6_PARAM" , 0x14F0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
|
|
{"IPD_RED_QUE7_PARAM" , 0x14F0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 184},
|
|
{"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14F0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 185},
|
|
{"IPD_SUB_PORT_FCS" , 0x14F0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 186},
|
|
{"IPD_WQE_FPA_QUEUE" , 0x14F0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 187},
|
|
{"IPD_WQE_PTR_VALID" , 0x14F0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
|
|
{"L2C_BST0" , 0x11800800007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
|
|
{"L2C_BST1" , 0x11800800007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
|
|
{"L2C_BST2" , 0x11800800007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 191},
|
|
{"L2C_CFG" , 0x1180080000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 192},
|
|
{"L2C_DBG" , 0x1180080000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 193},
|
|
{"L2C_DUT" , 0x1180080000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 194},
|
|
{"L2C_LCKBASE" , 0x1180080000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 195},
|
|
{"L2C_LCKOFF" , 0x1180080000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
|
|
{"L2C_LFB0" , 0x1180080000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
|
|
{"L2C_LFB1" , 0x1180080000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
|
|
{"L2C_LFB2" , 0x1180080000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
|
|
{"L2C_LFB3" , 0x11800800000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
|
|
{"L2C_PFC0" , 0x1180080000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
|
|
{"L2C_PFC1" , 0x11800800000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
|
|
{"L2C_PFC2" , 0x11800800000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
|
|
{"L2C_PFC3" , 0x11800800000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
|
|
{"L2C_PFCTL" , 0x1180080000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
|
|
{"L2C_SPAR0" , 0x1180080000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
|
|
{"L2C_SPAR4" , 0x1180080000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
|
|
{"L2D_BST0" , 0x1180080000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 205},
|
|
{"L2D_BST1" , 0x1180080000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 206},
|
|
{"L2D_BST2" , 0x1180080000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 207},
|
|
{"L2D_BST3" , 0x1180080000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 208},
|
|
{"L2D_ERR" , 0x1180080000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 209},
|
|
{"L2D_FADR" , 0x1180080000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 210},
|
|
{"L2D_FSYN0" , 0x1180080000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
|
|
{"L2D_FSYN1" , 0x1180080000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
|
|
{"L2D_FUS0" , 0x11800800007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
|
|
{"L2D_FUS1" , 0x11800800007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
|
|
{"L2D_FUS2" , 0x11800800007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
|
|
{"L2D_FUS3" , 0x11800800007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
|
|
{"L2T_ERR" , 0x1180080000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
|
|
{"LMC0_COMP_CTL" , 0x1180088000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
|
|
{"LMC0_CTL" , 0x1180088000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
|
|
{"LMC0_DCLK_CNT_HI" , 0x1180088000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
|
|
{"LMC0_DCLK_CNT_LO" , 0x1180088000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
|
|
{"LMC0_DDR2_CTL" , 0x1180088000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
|
|
{"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
|
|
{"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
|
|
{"LMC0_IFB_CNT_HI" , 0x1180088000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
|
|
{"LMC0_IFB_CNT_LO" , 0x1180088000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
|
|
{"LMC0_MEM_CFG0" , 0x1180088000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
|
|
{"LMC0_MEM_CFG1" , 0x1180088000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
|
|
{"LMC0_OPS_CNT_HI" , 0x1180088000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
|
|
{"LMC0_OPS_CNT_LO" , 0x1180088000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
|
|
{"LMC0_PLL_BWCTL" , 0x1180088000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
|
|
{"LMC0_RODT_CTL" , 0x1180088000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
|
|
{"LMC0_WODT_CTL0" , 0x1180088000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
|
|
{"LMC0_WODT_CTL1" , 0x1180088000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
|
|
{"MIO_BOOT_BIST_STAT" , 0x11800000000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
|
|
{"MIO_BOOT_ERR" , 0x11800000000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
|
|
{"MIO_BOOT_INT" , 0x11800000000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
|
|
{"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
|
|
{"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
|
|
{"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
|
|
{"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
|
|
{"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
|
|
{"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
|
|
{"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
|
|
{"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
|
|
{"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
|
|
{"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
|
|
{"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
|
|
{"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
|
|
{"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
|
|
{"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
|
|
{"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
|
|
{"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
|
|
{"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
|
|
{"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
|
|
{"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
|
|
{"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
|
|
{"MIO_BOOT_THR" , 0x11800000000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
|
|
{"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
|
|
{"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
|
|
{"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
|
|
{"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
|
|
{"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
|
|
{"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
|
|
{"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
|
|
{"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
|
|
{"MIO_FUS_UNLOCK" , 0x1180000001578ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
|
|
{"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
|
|
{"MIO_PLL_CTL" , 0x1180000001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
|
|
{"MIO_PLL_SETTING" , 0x1180000001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
|
|
{"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
|
|
{"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
|
|
{"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
|
|
{"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
|
|
{"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
|
|
{"MIO_UART1_DLH" , 0x1180000000C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
|
|
{"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
|
|
{"MIO_UART1_DLL" , 0x1180000000C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
|
|
{"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
|
|
{"MIO_UART1_FAR" , 0x1180000000D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
|
|
{"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
|
|
{"MIO_UART1_FCR" , 0x1180000000C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
|
|
{"MIO_UART0_HTX" , 0x1180000000B08ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
|
|
{"MIO_UART1_HTX" , 0x1180000000F08ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
|
|
{"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
|
|
{"MIO_UART1_IER" , 0x1180000000C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
|
|
{"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
|
|
{"MIO_UART1_IIR" , 0x1180000000C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
|
|
{"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
|
|
{"MIO_UART1_LCR" , 0x1180000000C18ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
|
|
{"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
|
|
{"MIO_UART1_LSR" , 0x1180000000C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
|
|
{"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
|
|
{"MIO_UART1_MCR" , 0x1180000000C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
|
|
{"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
|
|
{"MIO_UART1_MSR" , 0x1180000000C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
|
|
{"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
|
|
{"MIO_UART1_RBR" , 0x1180000000C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
|
|
{"MIO_UART0_RFL" , 0x1180000000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
|
|
{"MIO_UART1_RFL" , 0x1180000000E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
|
|
{"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
|
|
{"MIO_UART1_RFW" , 0x1180000000D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
|
|
{"MIO_UART0_SBCR" , 0x1180000000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
|
|
{"MIO_UART1_SBCR" , 0x1180000000E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
|
|
{"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
|
|
{"MIO_UART1_SCR" , 0x1180000000C38ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
|
|
{"MIO_UART0_SFE" , 0x1180000000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
|
|
{"MIO_UART1_SFE" , 0x1180000000E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
|
|
{"MIO_UART0_SRR" , 0x1180000000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
|
|
{"MIO_UART1_SRR" , 0x1180000000E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
|
|
{"MIO_UART0_SRT" , 0x1180000000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
|
|
{"MIO_UART1_SRT" , 0x1180000000E38ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
|
|
{"MIO_UART0_SRTS" , 0x1180000000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
|
|
{"MIO_UART1_SRTS" , 0x1180000000E18ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
|
|
{"MIO_UART0_STT" , 0x1180000000B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
|
|
{"MIO_UART1_STT" , 0x1180000000F00ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
|
|
{"MIO_UART0_TFL" , 0x1180000000A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
|
|
{"MIO_UART1_TFL" , 0x1180000000E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
|
|
{"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
|
|
{"MIO_UART1_TFR" , 0x1180000000D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
|
|
{"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
|
|
{"MIO_UART1_THR" , 0x1180000000C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
|
|
{"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
|
|
{"MIO_UART1_USR" , 0x1180000000D38ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
|
|
{"MPI_CFG" , 0x1070000001000ull, CVMX_CSR_DB_TYPE_NCB, 64, 285},
|
|
{"MPI_DAT0" , 0x1070000001080ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
|
|
{"MPI_DAT1" , 0x1070000001088ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
|
|
{"MPI_DAT2" , 0x1070000001090ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
|
|
{"MPI_DAT3" , 0x1070000001098ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
|
|
{"MPI_DAT4" , 0x10700000010A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
|
|
{"MPI_DAT5" , 0x10700000010A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
|
|
{"MPI_DAT6" , 0x10700000010B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
|
|
{"MPI_DAT7" , 0x10700000010B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
|
|
{"MPI_DAT8" , 0x10700000010C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
|
|
{"MPI_STS" , 0x1070000001008ull, CVMX_CSR_DB_TYPE_NCB, 64, 287},
|
|
{"MPI_TX" , 0x1070000001010ull, CVMX_CSR_DB_TYPE_NCB, 64, 288},
|
|
{"NPI_BASE_ADDR_INPUT0" , 0x11F0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 289},
|
|
{"NPI_BASE_ADDR_INPUT1" , 0x11F0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 289},
|
|
{"NPI_BASE_ADDR_OUTPUT0" , 0x11F00000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
|
|
{"NPI_BASE_ADDR_OUTPUT1" , 0x11F00000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
|
|
{"NPI_BIST_STATUS" , 0x11F00000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 291},
|
|
{"NPI_BUFF_SIZE_OUTPUT0" , 0x11F00000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
|
|
{"NPI_BUFF_SIZE_OUTPUT1" , 0x11F00000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
|
|
{"NPI_CTL_STATUS" , 0x11F0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 293},
|
|
{"NPI_DBG_SELECT" , 0x11F0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 294},
|
|
{"NPI_DMA_CONTROL" , 0x11F0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
|
|
{"NPI_DMA_HIGHP_COUNTS" , 0x11F0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 296},
|
|
{"NPI_DMA_HIGHP_NADDR" , 0x11F0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 297},
|
|
{"NPI_DMA_LOWP_COUNTS" , 0x11F0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 298},
|
|
{"NPI_DMA_LOWP_NADDR" , 0x11F0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 299},
|
|
{"NPI_HIGHP_DBELL" , 0x11F0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 300},
|
|
{"NPI_HIGHP_IBUFF_SADDR" , 0x11F0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 301},
|
|
{"NPI_INPUT_CONTROL" , 0x11F0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 302},
|
|
{"NPI_INT_ENB" , 0x11F0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 303},
|
|
{"NPI_INT_SUM" , 0x11F0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 304},
|
|
{"NPI_LOWP_DBELL" , 0x11F0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 305},
|
|
{"NPI_LOWP_IBUFF_SADDR" , 0x11F0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 306},
|
|
{"NPI_MEM_ACCESS_SUBID3" , 0x11F0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 307},
|
|
{"NPI_MEM_ACCESS_SUBID4" , 0x11F0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 307},
|
|
{"NPI_MEM_ACCESS_SUBID5" , 0x11F0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 307},
|
|
{"NPI_MEM_ACCESS_SUBID6" , 0x11F0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 307},
|
|
{"NPI_MSI_RCV" , 0x11F0000001190ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 308},
|
|
{"NPI_NUM_DESC_OUTPUT0" , 0x11F0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 309},
|
|
{"NPI_NUM_DESC_OUTPUT1" , 0x11F0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 309},
|
|
{"NPI_OUTPUT_CONTROL" , 0x11F0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 310},
|
|
{"NPI_P0_DBPAIR_ADDR" , 0x11F0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 311},
|
|
{"NPI_P1_DBPAIR_ADDR" , 0x11F0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 311},
|
|
{"NPI_P0_INSTR_ADDR" , 0x11F00000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 312},
|
|
{"NPI_P1_INSTR_ADDR" , 0x11F00000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 312},
|
|
{"NPI_P0_INSTR_CNTS" , 0x11F00000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 313},
|
|
{"NPI_P1_INSTR_CNTS" , 0x11F00000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 313},
|
|
{"NPI_P0_PAIR_CNTS" , 0x11F0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 314},
|
|
{"NPI_P1_PAIR_CNTS" , 0x11F0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 314},
|
|
{"NPI_PCI_BURST_SIZE" , 0x11F00000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 315},
|
|
{"NPI_PCI_INT_ARB_CFG" , 0x11F0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 316},
|
|
{"NPI_PCI_READ_CMD" , 0x11F0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 317},
|
|
{"NPI_PORT32_INSTR_HDR" , 0x11F00000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 318},
|
|
{"NPI_PORT33_INSTR_HDR" , 0x11F0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 319},
|
|
{"NPI_PORT_BP_CONTROL" , 0x11F00000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 320},
|
|
{"NPI_RSL_INT_BLOCKS" , 0x11F0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 321},
|
|
{"NPI_SIZE_INPUT0" , 0x11F0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
|
|
{"NPI_SIZE_INPUT1" , 0x11F0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 322},
|
|
{"NPI_WIN_READ_TO" , 0x11F00000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 323},
|
|
{"PCI_BAR1_INDEX0" , 0x11F0000001100ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX1" , 0x11F0000001104ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX2" , 0x11F0000001108ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX3" , 0x11F000000110Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX4" , 0x11F0000001110ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX5" , 0x11F0000001114ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX6" , 0x11F0000001118ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX7" , 0x11F000000111Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX8" , 0x11F0000001120ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX9" , 0x11F0000001124ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX10" , 0x11F0000001128ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX11" , 0x11F000000112Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX12" , 0x11F0000001130ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX13" , 0x11F0000001134ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX14" , 0x11F0000001138ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX15" , 0x11F000000113Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX16" , 0x11F0000001140ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX17" , 0x11F0000001144ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX18" , 0x11F0000001148ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX19" , 0x11F000000114Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX20" , 0x11F0000001150ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX21" , 0x11F0000001154ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX22" , 0x11F0000001158ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX23" , 0x11F000000115Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX24" , 0x11F0000001160ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX25" , 0x11F0000001164ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX26" , 0x11F0000001168ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX27" , 0x11F000000116Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX28" , 0x11F0000001170ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX29" , 0x11F0000001174ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX30" , 0x11F0000001178ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_BAR1_INDEX31" , 0x11F000000117Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 324},
|
|
{"PCI_CFG00" , 0x11F0000001800ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 325},
|
|
{"PCI_CFG01" , 0x11F0000001804ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 326},
|
|
{"PCI_CFG02" , 0x11F0000001808ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 327},
|
|
{"PCI_CFG03" , 0x11F000000180Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 328},
|
|
{"PCI_CFG04" , 0x11F0000001810ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 329},
|
|
{"PCI_CFG05" , 0x11F0000001814ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 330},
|
|
{"PCI_CFG06" , 0x11F0000001818ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 331},
|
|
{"PCI_CFG07" , 0x11F000000181Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 332},
|
|
{"PCI_CFG08" , 0x11F0000001820ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 333},
|
|
{"PCI_CFG09" , 0x11F0000001824ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 334},
|
|
{"PCI_CFG10" , 0x11F0000001828ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 335},
|
|
{"PCI_CFG11" , 0x11F000000182Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 336},
|
|
{"PCI_CFG12" , 0x11F0000001830ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 337},
|
|
{"PCI_CFG13" , 0x11F0000001834ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 338},
|
|
{"PCI_CFG15" , 0x11F000000183Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 339},
|
|
{"PCI_CFG16" , 0x11F0000001840ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 340},
|
|
{"PCI_CFG17" , 0x11F0000001844ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 341},
|
|
{"PCI_CFG18" , 0x11F0000001848ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 342},
|
|
{"PCI_CFG19" , 0x11F000000184Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 343},
|
|
{"PCI_CFG20" , 0x11F0000001850ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 344},
|
|
{"PCI_CFG21" , 0x11F0000001854ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 345},
|
|
{"PCI_CFG22" , 0x11F0000001858ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 346},
|
|
{"PCI_CFG56" , 0x11F00000018E0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 347},
|
|
{"PCI_CFG57" , 0x11F00000018E4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 348},
|
|
{"PCI_CFG58" , 0x11F00000018E8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 349},
|
|
{"PCI_CFG59" , 0x11F00000018ECull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 350},
|
|
{"PCI_CFG60" , 0x11F00000018F0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 351},
|
|
{"PCI_CFG61" , 0x11F00000018F4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 352},
|
|
{"PCI_CFG62" , 0x11F00000018F8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 353},
|
|
{"PCI_CFG63" , 0x11F00000018FCull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 354},
|
|
{"PCI_CTL_STATUS_2" , 0x11F000000118Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 355},
|
|
{"PCI_DBELL0" , 0x80ull, CVMX_CSR_DB_TYPE_PCI, 32, 356},
|
|
{"PCI_DBELL1" , 0x88ull, CVMX_CSR_DB_TYPE_PCI, 32, 356},
|
|
{"PCI_DMA_CNT0" , 0xA0ull, CVMX_CSR_DB_TYPE_PCI, 32, 357},
|
|
{"PCI_DMA_CNT1" , 0xA8ull, CVMX_CSR_DB_TYPE_PCI, 32, 357},
|
|
{"PCI_DMA_INT_LEV0" , 0xA4ull, CVMX_CSR_DB_TYPE_PCI, 32, 358},
|
|
{"PCI_DMA_INT_LEV1" , 0xACull, CVMX_CSR_DB_TYPE_PCI, 32, 358},
|
|
{"PCI_DMA_TIME0" , 0xB0ull, CVMX_CSR_DB_TYPE_PCI, 32, 359},
|
|
{"PCI_DMA_TIME1" , 0xB4ull, CVMX_CSR_DB_TYPE_PCI, 32, 359},
|
|
{"PCI_INSTR_COUNT0" , 0x84ull, CVMX_CSR_DB_TYPE_PCI, 32, 360},
|
|
{"PCI_INSTR_COUNT1" , 0x8Cull, CVMX_CSR_DB_TYPE_PCI, 32, 360},
|
|
{"PCI_INT_ENB" , 0x38ull, CVMX_CSR_DB_TYPE_PCI, 64, 361},
|
|
{"PCI_INT_ENB2" , 0x11F00000011A0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 362},
|
|
{"PCI_INT_SUM" , 0x30ull, CVMX_CSR_DB_TYPE_PCI, 64, 363},
|
|
{"PCI_INT_SUM2" , 0x11F0000001198ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 364},
|
|
{"PCI_MSI_RCV" , 0xF0ull, CVMX_CSR_DB_TYPE_PCI, 32, 365},
|
|
{"PCI_PKT_CREDITS0" , 0x44ull, CVMX_CSR_DB_TYPE_PCI, 32, 366},
|
|
{"PCI_PKT_CREDITS1" , 0x54ull, CVMX_CSR_DB_TYPE_PCI, 32, 366},
|
|
{"PCI_PKTS_SENT0" , 0x40ull, CVMX_CSR_DB_TYPE_PCI, 32, 367},
|
|
{"PCI_PKTS_SENT1" , 0x50ull, CVMX_CSR_DB_TYPE_PCI, 32, 367},
|
|
{"PCI_PKTS_SENT_INT_LEV0" , 0x48ull, CVMX_CSR_DB_TYPE_PCI, 32, 368},
|
|
{"PCI_PKTS_SENT_INT_LEV1" , 0x58ull, CVMX_CSR_DB_TYPE_PCI, 32, 368},
|
|
{"PCI_PKTS_SENT_TIME0" , 0x4Cull, CVMX_CSR_DB_TYPE_PCI, 32, 369},
|
|
{"PCI_PKTS_SENT_TIME1" , 0x5Cull, CVMX_CSR_DB_TYPE_PCI, 32, 369},
|
|
{"PCI_READ_CMD_6" , 0x11F0000001180ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 370},
|
|
{"PCI_READ_CMD_C" , 0x11F0000001184ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 371},
|
|
{"PCI_READ_CMD_E" , 0x11F0000001188ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 372},
|
|
{"PCI_READ_TIMEOUT" , 0x11F00000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 373},
|
|
{"PCI_SCM_REG" , 0x11F00000011A8ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 374},
|
|
{"PCI_TSR_REG" , 0x11F00000011B0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 375},
|
|
{"PCI_WIN_RD_ADDR" , 0x8ull, CVMX_CSR_DB_TYPE_PCI, 64, 376},
|
|
{"PCI_WIN_RD_DATA" , 0x20ull, CVMX_CSR_DB_TYPE_PCI, 64, 377},
|
|
{"PCI_WIN_WR_ADDR" , 0x0ull, CVMX_CSR_DB_TYPE_PCI, 64, 378},
|
|
{"PCI_WIN_WR_DATA" , 0x10ull, CVMX_CSR_DB_TYPE_PCI, 64, 379},
|
|
{"PCI_WIN_WR_MASK" , 0x18ull, CVMX_CSR_DB_TYPE_PCI, 64, 380},
|
|
{"PCM0_DMA_CFG" , 0x1070000010018ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
|
|
{"PCM1_DMA_CFG" , 0x1070000014018ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
|
|
{"PCM2_DMA_CFG" , 0x1070000018018ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
|
|
{"PCM3_DMA_CFG" , 0x107000001C018ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
|
|
{"PCM0_INT_ENA" , 0x1070000010020ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
|
|
{"PCM1_INT_ENA" , 0x1070000014020ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
|
|
{"PCM2_INT_ENA" , 0x1070000018020ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
|
|
{"PCM3_INT_ENA" , 0x107000001C020ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
|
|
{"PCM0_INT_SUM" , 0x1070000010028ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
|
|
{"PCM1_INT_SUM" , 0x1070000014028ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
|
|
{"PCM2_INT_SUM" , 0x1070000018028ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
|
|
{"PCM3_INT_SUM" , 0x107000001C028ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
|
|
{"PCM0_RXADDR" , 0x1070000010068ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
|
|
{"PCM1_RXADDR" , 0x1070000014068ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
|
|
{"PCM2_RXADDR" , 0x1070000018068ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
|
|
{"PCM3_RXADDR" , 0x107000001C068ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
|
|
{"PCM0_RXCNT" , 0x1070000010060ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
|
|
{"PCM1_RXCNT" , 0x1070000014060ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
|
|
{"PCM2_RXCNT" , 0x1070000018060ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
|
|
{"PCM3_RXCNT" , 0x107000001C060ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
|
|
{"PCM0_RXMSK0" , 0x10700000100C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
|
|
{"PCM1_RXMSK0" , 0x10700000140C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
|
|
{"PCM2_RXMSK0" , 0x10700000180C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
|
|
{"PCM3_RXMSK0" , 0x107000001C0C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
|
|
{"PCM0_RXMSK1" , 0x10700000100C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
|
|
{"PCM1_RXMSK1" , 0x10700000140C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
|
|
{"PCM2_RXMSK1" , 0x10700000180C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
|
|
{"PCM3_RXMSK1" , 0x107000001C0C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
|
|
{"PCM0_RXMSK2" , 0x10700000100D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
|
|
{"PCM1_RXMSK2" , 0x10700000140D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
|
|
{"PCM2_RXMSK2" , 0x10700000180D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
|
|
{"PCM3_RXMSK2" , 0x107000001C0D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
|
|
{"PCM0_RXMSK3" , 0x10700000100D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
|
|
{"PCM1_RXMSK3" , 0x10700000140D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
|
|
{"PCM2_RXMSK3" , 0x10700000180D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
|
|
{"PCM3_RXMSK3" , 0x107000001C0D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
|
|
{"PCM0_RXMSK4" , 0x10700000100E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
|
|
{"PCM1_RXMSK4" , 0x10700000140E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
|
|
{"PCM2_RXMSK4" , 0x10700000180E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
|
|
{"PCM3_RXMSK4" , 0x107000001C0E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
|
|
{"PCM0_RXMSK5" , 0x10700000100E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
|
|
{"PCM1_RXMSK5" , 0x10700000140E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
|
|
{"PCM2_RXMSK5" , 0x10700000180E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
|
|
{"PCM3_RXMSK5" , 0x107000001C0E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
|
|
{"PCM0_RXMSK6" , 0x10700000100F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 392},
|
|
{"PCM1_RXMSK6" , 0x10700000140F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 392},
|
|
{"PCM2_RXMSK6" , 0x10700000180F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 392},
|
|
{"PCM3_RXMSK6" , 0x107000001C0F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 392},
|
|
{"PCM0_RXMSK7" , 0x10700000100F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 393},
|
|
{"PCM1_RXMSK7" , 0x10700000140F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 393},
|
|
{"PCM2_RXMSK7" , 0x10700000180F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 393},
|
|
{"PCM3_RXMSK7" , 0x107000001C0F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 393},
|
|
{"PCM0_RXSTART" , 0x1070000010058ull, CVMX_CSR_DB_TYPE_NCB, 64, 394},
|
|
{"PCM1_RXSTART" , 0x1070000014058ull, CVMX_CSR_DB_TYPE_NCB, 64, 394},
|
|
{"PCM2_RXSTART" , 0x1070000018058ull, CVMX_CSR_DB_TYPE_NCB, 64, 394},
|
|
{"PCM3_RXSTART" , 0x107000001C058ull, CVMX_CSR_DB_TYPE_NCB, 64, 394},
|
|
{"PCM0_TDM_CFG" , 0x1070000010010ull, CVMX_CSR_DB_TYPE_NCB, 64, 395},
|
|
{"PCM1_TDM_CFG" , 0x1070000014010ull, CVMX_CSR_DB_TYPE_NCB, 64, 395},
|
|
{"PCM2_TDM_CFG" , 0x1070000018010ull, CVMX_CSR_DB_TYPE_NCB, 64, 395},
|
|
{"PCM3_TDM_CFG" , 0x107000001C010ull, CVMX_CSR_DB_TYPE_NCB, 64, 395},
|
|
{"PCM0_TDM_DBG" , 0x1070000010030ull, CVMX_CSR_DB_TYPE_NCB, 64, 396},
|
|
{"PCM1_TDM_DBG" , 0x1070000014030ull, CVMX_CSR_DB_TYPE_NCB, 64, 396},
|
|
{"PCM2_TDM_DBG" , 0x1070000018030ull, CVMX_CSR_DB_TYPE_NCB, 64, 396},
|
|
{"PCM3_TDM_DBG" , 0x107000001C030ull, CVMX_CSR_DB_TYPE_NCB, 64, 396},
|
|
{"PCM0_TXADDR" , 0x1070000010050ull, CVMX_CSR_DB_TYPE_NCB, 64, 397},
|
|
{"PCM1_TXADDR" , 0x1070000014050ull, CVMX_CSR_DB_TYPE_NCB, 64, 397},
|
|
{"PCM2_TXADDR" , 0x1070000018050ull, CVMX_CSR_DB_TYPE_NCB, 64, 397},
|
|
{"PCM3_TXADDR" , 0x107000001C050ull, CVMX_CSR_DB_TYPE_NCB, 64, 397},
|
|
{"PCM0_TXCNT" , 0x1070000010048ull, CVMX_CSR_DB_TYPE_NCB, 64, 398},
|
|
{"PCM1_TXCNT" , 0x1070000014048ull, CVMX_CSR_DB_TYPE_NCB, 64, 398},
|
|
{"PCM2_TXCNT" , 0x1070000018048ull, CVMX_CSR_DB_TYPE_NCB, 64, 398},
|
|
{"PCM3_TXCNT" , 0x107000001C048ull, CVMX_CSR_DB_TYPE_NCB, 64, 398},
|
|
{"PCM0_TXMSK0" , 0x1070000010080ull, CVMX_CSR_DB_TYPE_NCB, 64, 399},
|
|
{"PCM1_TXMSK0" , 0x1070000014080ull, CVMX_CSR_DB_TYPE_NCB, 64, 399},
|
|
{"PCM2_TXMSK0" , 0x1070000018080ull, CVMX_CSR_DB_TYPE_NCB, 64, 399},
|
|
{"PCM3_TXMSK0" , 0x107000001C080ull, CVMX_CSR_DB_TYPE_NCB, 64, 399},
|
|
{"PCM0_TXMSK1" , 0x1070000010088ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
|
|
{"PCM1_TXMSK1" , 0x1070000014088ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
|
|
{"PCM2_TXMSK1" , 0x1070000018088ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
|
|
{"PCM3_TXMSK1" , 0x107000001C088ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
|
|
{"PCM0_TXMSK2" , 0x1070000010090ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
|
|
{"PCM1_TXMSK2" , 0x1070000014090ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
|
|
{"PCM2_TXMSK2" , 0x1070000018090ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
|
|
{"PCM3_TXMSK2" , 0x107000001C090ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
|
|
{"PCM0_TXMSK3" , 0x1070000010098ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
|
|
{"PCM1_TXMSK3" , 0x1070000014098ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
|
|
{"PCM2_TXMSK3" , 0x1070000018098ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
|
|
{"PCM3_TXMSK3" , 0x107000001C098ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
|
|
{"PCM0_TXMSK4" , 0x10700000100A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
|
|
{"PCM1_TXMSK4" , 0x10700000140A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
|
|
{"PCM2_TXMSK4" , 0x10700000180A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
|
|
{"PCM3_TXMSK4" , 0x107000001C0A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
|
|
{"PCM0_TXMSK5" , 0x10700000100A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 404},
|
|
{"PCM1_TXMSK5" , 0x10700000140A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 404},
|
|
{"PCM2_TXMSK5" , 0x10700000180A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 404},
|
|
{"PCM3_TXMSK5" , 0x107000001C0A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 404},
|
|
{"PCM0_TXMSK6" , 0x10700000100B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 405},
|
|
{"PCM1_TXMSK6" , 0x10700000140B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 405},
|
|
{"PCM2_TXMSK6" , 0x10700000180B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 405},
|
|
{"PCM3_TXMSK6" , 0x107000001C0B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 405},
|
|
{"PCM0_TXMSK7" , 0x10700000100B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 406},
|
|
{"PCM1_TXMSK7" , 0x10700000140B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 406},
|
|
{"PCM2_TXMSK7" , 0x10700000180B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 406},
|
|
{"PCM3_TXMSK7" , 0x107000001C0B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 406},
|
|
{"PCM0_TXSTART" , 0x1070000010040ull, CVMX_CSR_DB_TYPE_NCB, 64, 407},
|
|
{"PCM1_TXSTART" , 0x1070000014040ull, CVMX_CSR_DB_TYPE_NCB, 64, 407},
|
|
{"PCM2_TXSTART" , 0x1070000018040ull, CVMX_CSR_DB_TYPE_NCB, 64, 407},
|
|
{"PCM3_TXSTART" , 0x107000001C040ull, CVMX_CSR_DB_TYPE_NCB, 64, 407},
|
|
{"PCM_CLK0_CFG" , 0x1070000010000ull, CVMX_CSR_DB_TYPE_NCB, 64, 408},
|
|
{"PCM_CLK1_CFG" , 0x1070000014000ull, CVMX_CSR_DB_TYPE_NCB, 64, 408},
|
|
{"PCM_CLK0_DBG" , 0x1070000010038ull, CVMX_CSR_DB_TYPE_NCB, 64, 409},
|
|
{"PCM_CLK1_DBG" , 0x1070000014038ull, CVMX_CSR_DB_TYPE_NCB, 64, 409},
|
|
{"PCM_CLK0_GEN" , 0x1070000010008ull, CVMX_CSR_DB_TYPE_NCB, 64, 410},
|
|
{"PCM_CLK1_GEN" , 0x1070000014008ull, CVMX_CSR_DB_TYPE_NCB, 64, 410},
|
|
{"PIP_BIST_STATUS" , 0x11800A0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
|
|
{"PIP_DEC_IPSEC0" , 0x11800A0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
|
|
{"PIP_DEC_IPSEC1" , 0x11800A0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
|
|
{"PIP_DEC_IPSEC2" , 0x11800A0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
|
|
{"PIP_DEC_IPSEC3" , 0x11800A0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
|
|
{"PIP_GBL_CFG" , 0x11800A0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
|
|
{"PIP_GBL_CTL" , 0x11800A0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
|
|
{"PIP_INT_EN" , 0x11800A0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_INT_REG" , 0x11800A0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
|
|
{"PIP_IP_OFFSET" , 0x11800A0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
|
|
{"PIP_PRT_CFG0" , 0x11800A0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
|
|
{"PIP_PRT_CFG1" , 0x11800A0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
|
|
{"PIP_PRT_CFG2" , 0x11800A0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
|
|
{"PIP_PRT_CFG32" , 0x11800A0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
|
|
{"PIP_PRT_CFG33" , 0x11800A0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
|
|
{"PIP_PRT_TAG0" , 0x11800A0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
|
|
{"PIP_PRT_TAG1" , 0x11800A0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
|
|
{"PIP_PRT_TAG2" , 0x11800A0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
|
|
{"PIP_PRT_TAG32" , 0x11800A0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
|
|
{"PIP_PRT_TAG33" , 0x11800A0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
|
|
{"PIP_QOS_DIFF0" , 0x11800A0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF1" , 0x11800A0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF2" , 0x11800A0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF3" , 0x11800A0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF4" , 0x11800A0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF5" , 0x11800A0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF6" , 0x11800A0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF7" , 0x11800A0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF8" , 0x11800A0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF9" , 0x11800A0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF10" , 0x11800A0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF11" , 0x11800A0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF12" , 0x11800A0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF13" , 0x11800A0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF14" , 0x11800A0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF15" , 0x11800A0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF16" , 0x11800A0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF17" , 0x11800A0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF18" , 0x11800A0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF19" , 0x11800A0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF20" , 0x11800A00006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF21" , 0x11800A00006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF22" , 0x11800A00006B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF23" , 0x11800A00006B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF24" , 0x11800A00006C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF25" , 0x11800A00006C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF26" , 0x11800A00006D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF27" , 0x11800A00006D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF28" , 0x11800A00006E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF29" , 0x11800A00006E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF30" , 0x11800A00006F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF31" , 0x11800A00006F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF32" , 0x11800A0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF33" , 0x11800A0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF34" , 0x11800A0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF35" , 0x11800A0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF36" , 0x11800A0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF37" , 0x11800A0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF38" , 0x11800A0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF39" , 0x11800A0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF40" , 0x11800A0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF41" , 0x11800A0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF42" , 0x11800A0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF43" , 0x11800A0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF44" , 0x11800A0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF45" , 0x11800A0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF46" , 0x11800A0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF47" , 0x11800A0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF48" , 0x11800A0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF49" , 0x11800A0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF50" , 0x11800A0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF51" , 0x11800A0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF52" , 0x11800A00007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF53" , 0x11800A00007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF54" , 0x11800A00007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF55" , 0x11800A00007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF56" , 0x11800A00007C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF57" , 0x11800A00007C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF58" , 0x11800A00007D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF59" , 0x11800A00007D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF60" , 0x11800A00007E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF61" , 0x11800A00007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF62" , 0x11800A00007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_DIFF63" , 0x11800A00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_QOS_VLAN0" , 0x11800A00000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_QOS_VLAN1" , 0x11800A00000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_QOS_VLAN2" , 0x11800A00000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_QOS_VLAN3" , 0x11800A00000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_QOS_VLAN4" , 0x11800A00000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_QOS_VLAN5" , 0x11800A00000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_QOS_VLAN6" , 0x11800A00000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_QOS_VLAN7" , 0x11800A00000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_QOS_WATCH0" , 0x11800A0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_WATCH1" , 0x11800A0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_WATCH2" , 0x11800A0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_QOS_WATCH3" , 0x11800A0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_RAW_WORD" , 0x11800A00000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
|
|
{"PIP_SFT_RST" , 0x11800A0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
|
|
{"PIP_STAT0_PRT0" , 0x11800A0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
|
|
{"PIP_STAT0_PRT1" , 0x11800A0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
|
|
{"PIP_STAT0_PRT2" , 0x11800A00008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
|
|
{"PIP_STAT0_PRT32" , 0x11800A0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
|
|
{"PIP_STAT0_PRT33" , 0x11800A0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
|
|
{"PIP_STAT1_PRT0" , 0x11800A0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT1_PRT1" , 0x11800A0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT1_PRT2" , 0x11800A00008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT1_PRT32" , 0x11800A0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT1_PRT33" , 0x11800A0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT2_PRT0" , 0x11800A0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT2_PRT1" , 0x11800A0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT2_PRT2" , 0x11800A00008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT2_PRT32" , 0x11800A0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT2_PRT33" , 0x11800A0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT3_PRT0" , 0x11800A0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT3_PRT1" , 0x11800A0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT3_PRT2" , 0x11800A00008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT3_PRT32" , 0x11800A0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT3_PRT33" , 0x11800A0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT4_PRT0" , 0x11800A0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT4_PRT1" , 0x11800A0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT4_PRT2" , 0x11800A00008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT4_PRT32" , 0x11800A0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT4_PRT33" , 0x11800A0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT5_PRT0" , 0x11800A0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT5_PRT1" , 0x11800A0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT5_PRT2" , 0x11800A00008C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT5_PRT32" , 0x11800A0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT5_PRT33" , 0x11800A0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT6_PRT0" , 0x11800A0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT6_PRT1" , 0x11800A0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT6_PRT2" , 0x11800A00008D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT6_PRT32" , 0x11800A0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT6_PRT33" , 0x11800A0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT7_PRT0" , 0x11800A0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT7_PRT1" , 0x11800A0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT7_PRT2" , 0x11800A00008D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT7_PRT32" , 0x11800A0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT7_PRT33" , 0x11800A0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT8_PRT0" , 0x11800A0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT8_PRT1" , 0x11800A0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT8_PRT2" , 0x11800A00008E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT8_PRT32" , 0x11800A0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT8_PRT33" , 0x11800A0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT9_PRT0" , 0x11800A0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT9_PRT1" , 0x11800A0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT9_PRT2" , 0x11800A00008E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT9_PRT32" , 0x11800A0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT9_PRT33" , 0x11800A0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_STAT_CTL" , 0x11800A0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_STAT_INB_ERRS0" , 0x11800A0001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
|
|
{"PIP_STAT_INB_ERRS1" , 0x11800A0001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
|
|
{"PIP_STAT_INB_ERRS2" , 0x11800A0001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
|
|
{"PIP_STAT_INB_ERRS32" , 0x11800A0001E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
|
|
{"PIP_STAT_INB_ERRS33" , 0x11800A0001E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
|
|
{"PIP_STAT_INB_OCTS0" , 0x11800A0001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_OCTS1" , 0x11800A0001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_OCTS2" , 0x11800A0001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_OCTS32" , 0x11800A0001E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_OCTS33" , 0x11800A0001E28ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT_INB_PKTS0" , 0x11800A0001A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_PKTS1" , 0x11800A0001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_PKTS2" , 0x11800A0001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_PKTS32" , 0x11800A0001E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT_INB_PKTS33" , 0x11800A0001E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_TAG_INC0" , 0x11800A0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC1" , 0x11800A0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC2" , 0x11800A0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC3" , 0x11800A0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC4" , 0x11800A0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC5" , 0x11800A0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC6" , 0x11800A0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC7" , 0x11800A0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC8" , 0x11800A0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC9" , 0x11800A0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC10" , 0x11800A0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC11" , 0x11800A0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC12" , 0x11800A0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC13" , 0x11800A0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC14" , 0x11800A0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC15" , 0x11800A0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC16" , 0x11800A0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC17" , 0x11800A0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC18" , 0x11800A0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC19" , 0x11800A0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC20" , 0x11800A00018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC21" , 0x11800A00018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC22" , 0x11800A00018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC23" , 0x11800A00018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC24" , 0x11800A00018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC25" , 0x11800A00018C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC26" , 0x11800A00018D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC27" , 0x11800A00018D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC28" , 0x11800A00018E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC29" , 0x11800A00018E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC30" , 0x11800A00018F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC31" , 0x11800A00018F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC32" , 0x11800A0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC33" , 0x11800A0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC34" , 0x11800A0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC35" , 0x11800A0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC36" , 0x11800A0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC37" , 0x11800A0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC38" , 0x11800A0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC39" , 0x11800A0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC40" , 0x11800A0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC41" , 0x11800A0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC42" , 0x11800A0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC43" , 0x11800A0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC44" , 0x11800A0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC45" , 0x11800A0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC46" , 0x11800A0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC47" , 0x11800A0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC48" , 0x11800A0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC49" , 0x11800A0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC50" , 0x11800A0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC51" , 0x11800A0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC52" , 0x11800A00019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC53" , 0x11800A00019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC54" , 0x11800A00019B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC55" , 0x11800A00019B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC56" , 0x11800A00019C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC57" , 0x11800A00019C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC58" , 0x11800A00019D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC59" , 0x11800A00019D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC60" , 0x11800A00019E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC61" , 0x11800A00019E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC62" , 0x11800A00019F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_INC63" , 0x11800A00019F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_TAG_MASK" , 0x11800A0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_TAG_SECRET" , 0x11800A0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_TODO_ENTRY" , 0x11800A0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
|
|
{"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PKO_MEM_DEBUG14" , 0x1180050001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 468},
|
|
{"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"POW_BIST_STAT" , 0x16700000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 471},
|
|
{"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 472},
|
|
{"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 473},
|
|
{"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 474},
|
|
{"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
|
|
{"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
|
|
{"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
|
|
{"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
|
|
{"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
|
|
{"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
|
|
{"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
|
|
{"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
|
|
{"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 476},
|
|
{"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 477},
|
|
{"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 478},
|
|
{"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
|
|
{"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
|
|
{"POW_QOS_RND0" , 0x16700000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
|
|
{"POW_QOS_RND1" , 0x16700000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
|
|
{"POW_QOS_RND2" , 0x16700000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
|
|
{"POW_QOS_RND3" , 0x16700000001D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
|
|
{"POW_QOS_RND4" , 0x16700000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
|
|
{"POW_QOS_RND5" , 0x16700000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
|
|
{"POW_QOS_RND6" , 0x16700000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
|
|
{"POW_QOS_RND7" , 0x16700000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
|
|
{"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
|
|
{"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
|
|
{"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
|
|
{"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
|
|
{"POW_QOS_THR4" , 0x16700000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
|
|
{"POW_QOS_THR5" , 0x16700000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
|
|
{"POW_QOS_THR6" , 0x16700000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
|
|
{"POW_QOS_THR7" , 0x16700000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
|
|
{"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 482},
|
|
{"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
|
|
{"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
|
|
{"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
|
|
{"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
|
|
{"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
|
|
{"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
|
|
{"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
|
|
{"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
|
|
{"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
|
|
{"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
|
|
{"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
|
|
{"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
|
|
{"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
|
|
{"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
|
|
{"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
|
|
{"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
|
|
{"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
|
|
{"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
|
|
{"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
|
|
{"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
|
|
{"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
|
|
{"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
|
|
{"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
|
|
{"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
|
|
{"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
|
|
{"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WQ_INT_THR4" , 0x16700000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WQ_INT_THR5" , 0x16700000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WQ_INT_THR6" , 0x16700000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WQ_INT_THR7" , 0x16700000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WQ_INT_THR8" , 0x16700000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WQ_INT_THR9" , 0x16700000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WQ_INT_THR10" , 0x16700000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WQ_INT_THR11" , 0x16700000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WQ_INT_THR12" , 0x16700000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WQ_INT_THR13" , 0x16700000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WQ_INT_THR14" , 0x16700000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WQ_INT_THR15" , 0x16700000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
|
|
{"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
|
|
{"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
|
|
{"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
|
|
{"POW_WS_PC4" , 0x16700000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
|
|
{"POW_WS_PC5" , 0x16700000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
|
|
{"POW_WS_PC6" , 0x16700000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
|
|
{"POW_WS_PC7" , 0x16700000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
|
|
{"POW_WS_PC8" , 0x16700000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
|
|
{"POW_WS_PC9" , 0x16700000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
|
|
{"POW_WS_PC10" , 0x16700000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
|
|
{"POW_WS_PC11" , 0x16700000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
|
|
{"POW_WS_PC12" , 0x16700000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
|
|
{"POW_WS_PC13" , 0x16700000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
|
|
{"POW_WS_PC14" , 0x16700000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
|
|
{"POW_WS_PC15" , 0x16700000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
|
|
{"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 490},
|
|
{"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 491},
|
|
{"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 492},
|
|
{"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 493},
|
|
{"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 494},
|
|
{"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 495},
|
|
{"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
|
|
{"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
|
|
{"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
|
|
{"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
|
|
{"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
|
|
{"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
|
|
{"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
|
|
{"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
|
|
{"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
|
|
{"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
|
|
{"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
|
|
{"TRA_BIST_STATUS" , 0x11800A8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
|
|
{"TRA_CTL" , 0x11800A8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
|
|
{"TRA_CYCLES_SINCE" , 0x11800A8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
|
|
{"TRA_FILT_ADR_ADR" , 0x11800A8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
|
|
{"TRA_FILT_ADR_MSK" , 0x11800A8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
|
|
{"TRA_FILT_CMD" , 0x11800A8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
|
|
{"TRA_FILT_DID" , 0x11800A8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
|
|
{"TRA_FILT_SID" , 0x11800A8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
|
|
{"TRA_INT_STATUS" , 0x11800A8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 515},
|
|
{"TRA_READ_DAT" , 0x11800A8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 516},
|
|
{"TRA_TRIG0_ADR_ADR" , 0x11800A8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 517},
|
|
{"TRA_TRIG0_ADR_MSK" , 0x11800A80000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 518},
|
|
{"TRA_TRIG0_CMD" , 0x11800A8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 519},
|
|
{"TRA_TRIG0_DID" , 0x11800A8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 520},
|
|
{"TRA_TRIG0_SID" , 0x11800A8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"TRA_TRIG1_ADR_ADR" , 0x11800A80000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 522},
|
|
{"TRA_TRIG1_ADR_MSK" , 0x11800A80000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 523},
|
|
{"TRA_TRIG1_CMD" , 0x11800A80000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 524},
|
|
{"TRA_TRIG1_DID" , 0x11800A80000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
|
|
{"TRA_TRIG1_SID" , 0x11800A80000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 526},
|
|
{"USBC0_DAINT" , 0x16F0010000818ull, CVMX_CSR_DB_TYPE_NCB, 32, 527},
|
|
{"USBC0_DAINTMSK" , 0x16F001000081Cull, CVMX_CSR_DB_TYPE_NCB, 32, 528},
|
|
{"USBC0_DCFG" , 0x16F0010000800ull, CVMX_CSR_DB_TYPE_NCB, 32, 529},
|
|
{"USBC0_DCTL" , 0x16F0010000804ull, CVMX_CSR_DB_TYPE_NCB, 32, 530},
|
|
{"USBC0_DIEPCTL000" , 0x16F0010000900ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
|
|
{"USBC0_DIEPCTL001" , 0x16F0010000920ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
|
|
{"USBC0_DIEPCTL002" , 0x16F0010000940ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
|
|
{"USBC0_DIEPCTL003" , 0x16F0010000960ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
|
|
{"USBC0_DIEPCTL004" , 0x16F0010000980ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
|
|
{"USBC0_DIEPINT000" , 0x16F0010000908ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
|
|
{"USBC0_DIEPINT001" , 0x16F0010000928ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
|
|
{"USBC0_DIEPINT002" , 0x16F0010000948ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
|
|
{"USBC0_DIEPINT003" , 0x16F0010000968ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
|
|
{"USBC0_DIEPINT004" , 0x16F0010000988ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
|
|
{"USBC0_DIEPMSK" , 0x16F0010000810ull, CVMX_CSR_DB_TYPE_NCB, 32, 533},
|
|
{"USBC0_DIEPTSIZ000" , 0x16F0010000910ull, CVMX_CSR_DB_TYPE_NCB, 32, 534},
|
|
{"USBC0_DIEPTSIZ001" , 0x16F0010000930ull, CVMX_CSR_DB_TYPE_NCB, 32, 534},
|
|
{"USBC0_DIEPTSIZ002" , 0x16F0010000950ull, CVMX_CSR_DB_TYPE_NCB, 32, 534},
|
|
{"USBC0_DIEPTSIZ003" , 0x16F0010000970ull, CVMX_CSR_DB_TYPE_NCB, 32, 534},
|
|
{"USBC0_DIEPTSIZ004" , 0x16F0010000990ull, CVMX_CSR_DB_TYPE_NCB, 32, 534},
|
|
{"USBC0_DOEPCTL000" , 0x16F0010000B00ull, CVMX_CSR_DB_TYPE_NCB, 32, 535},
|
|
{"USBC0_DOEPCTL001" , 0x16F0010000B20ull, CVMX_CSR_DB_TYPE_NCB, 32, 535},
|
|
{"USBC0_DOEPCTL002" , 0x16F0010000B40ull, CVMX_CSR_DB_TYPE_NCB, 32, 535},
|
|
{"USBC0_DOEPCTL003" , 0x16F0010000B60ull, CVMX_CSR_DB_TYPE_NCB, 32, 535},
|
|
{"USBC0_DOEPCTL004" , 0x16F0010000B80ull, CVMX_CSR_DB_TYPE_NCB, 32, 535},
|
|
{"USBC0_DOEPINT000" , 0x16F0010000B08ull, CVMX_CSR_DB_TYPE_NCB, 32, 536},
|
|
{"USBC0_DOEPINT001" , 0x16F0010000B28ull, CVMX_CSR_DB_TYPE_NCB, 32, 536},
|
|
{"USBC0_DOEPINT002" , 0x16F0010000B48ull, CVMX_CSR_DB_TYPE_NCB, 32, 536},
|
|
{"USBC0_DOEPINT003" , 0x16F0010000B68ull, CVMX_CSR_DB_TYPE_NCB, 32, 536},
|
|
{"USBC0_DOEPINT004" , 0x16F0010000B88ull, CVMX_CSR_DB_TYPE_NCB, 32, 536},
|
|
{"USBC0_DOEPMSK" , 0x16F0010000814ull, CVMX_CSR_DB_TYPE_NCB, 32, 537},
|
|
{"USBC0_DOEPTSIZ000" , 0x16F0010000B10ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
|
|
{"USBC0_DOEPTSIZ001" , 0x16F0010000B30ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
|
|
{"USBC0_DOEPTSIZ002" , 0x16F0010000B50ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
|
|
{"USBC0_DOEPTSIZ003" , 0x16F0010000B70ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
|
|
{"USBC0_DOEPTSIZ004" , 0x16F0010000B90ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
|
|
{"USBC0_DPTXFSIZ001" , 0x16F0010000104ull, CVMX_CSR_DB_TYPE_NCB, 32, 539},
|
|
{"USBC0_DPTXFSIZ002" , 0x16F0010000108ull, CVMX_CSR_DB_TYPE_NCB, 32, 539},
|
|
{"USBC0_DPTXFSIZ003" , 0x16F001000010Cull, CVMX_CSR_DB_TYPE_NCB, 32, 539},
|
|
{"USBC0_DPTXFSIZ004" , 0x16F0010000110ull, CVMX_CSR_DB_TYPE_NCB, 32, 539},
|
|
{"USBC0_DSTS" , 0x16F0010000808ull, CVMX_CSR_DB_TYPE_NCB, 32, 540},
|
|
{"USBC0_DTKNQR1" , 0x16F0010000820ull, CVMX_CSR_DB_TYPE_NCB, 32, 541},
|
|
{"USBC0_DTKNQR2" , 0x16F0010000824ull, CVMX_CSR_DB_TYPE_NCB, 32, 542},
|
|
{"USBC0_DTKNQR3" , 0x16F0010000830ull, CVMX_CSR_DB_TYPE_NCB, 32, 543},
|
|
{"USBC0_DTKNQR4" , 0x16F0010000834ull, CVMX_CSR_DB_TYPE_NCB, 32, 544},
|
|
{"USBC0_GAHBCFG" , 0x16F0010000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 545},
|
|
{"USBC0_GHWCFG1" , 0x16F0010000044ull, CVMX_CSR_DB_TYPE_NCB, 32, 546},
|
|
{"USBC0_GHWCFG2" , 0x16F0010000048ull, CVMX_CSR_DB_TYPE_NCB, 32, 547},
|
|
{"USBC0_GHWCFG3" , 0x16F001000004Cull, CVMX_CSR_DB_TYPE_NCB, 32, 548},
|
|
{"USBC0_GHWCFG4" , 0x16F0010000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 549},
|
|
{"USBC0_GINTMSK" , 0x16F0010000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 550},
|
|
{"USBC0_GINTSTS" , 0x16F0010000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 551},
|
|
{"USBC0_GNPTXFSIZ" , 0x16F0010000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 552},
|
|
{"USBC0_GNPTXSTS" , 0x16F001000002Cull, CVMX_CSR_DB_TYPE_NCB, 32, 553},
|
|
{"USBC0_GOTGCTL" , 0x16F0010000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 554},
|
|
{"USBC0_GOTGINT" , 0x16F0010000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 555},
|
|
{"USBC0_GRSTCTL" , 0x16F0010000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 556},
|
|
{"USBC0_GRXFSIZ" , 0x16F0010000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 557},
|
|
{"USBC0_GRXSTSPD" , 0x16F0010040020ull, CVMX_CSR_DB_TYPE_NCB, 32, 558},
|
|
{"USBC0_GRXSTSPH" , 0x16F0010000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 559},
|
|
{"USBC0_GRXSTSRD" , 0x16F001004001Cull, CVMX_CSR_DB_TYPE_NCB, 32, 560},
|
|
{"USBC0_GRXSTSRH" , 0x16F001000001Cull, CVMX_CSR_DB_TYPE_NCB, 32, 561},
|
|
{"USBC0_GSNPSID" , 0x16F0010000040ull, CVMX_CSR_DB_TYPE_NCB, 32, 562},
|
|
{"USBC0_GUSBCFG" , 0x16F001000000Cull, CVMX_CSR_DB_TYPE_NCB, 32, 563},
|
|
{"USBC0_HAINT" , 0x16F0010000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 564},
|
|
{"USBC0_HAINTMSK" , 0x16F0010000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 565},
|
|
{"USBC0_HCCHAR000" , 0x16F0010000500ull, CVMX_CSR_DB_TYPE_NCB, 32, 566},
|
|
{"USBC0_HCCHAR001" , 0x16F0010000520ull, CVMX_CSR_DB_TYPE_NCB, 32, 566},
|
|
{"USBC0_HCCHAR002" , 0x16F0010000540ull, CVMX_CSR_DB_TYPE_NCB, 32, 566},
|
|
{"USBC0_HCCHAR003" , 0x16F0010000560ull, CVMX_CSR_DB_TYPE_NCB, 32, 566},
|
|
{"USBC0_HCCHAR004" , 0x16F0010000580ull, CVMX_CSR_DB_TYPE_NCB, 32, 566},
|
|
{"USBC0_HCCHAR005" , 0x16F00100005A0ull, CVMX_CSR_DB_TYPE_NCB, 32, 566},
|
|
{"USBC0_HCCHAR006" , 0x16F00100005C0ull, CVMX_CSR_DB_TYPE_NCB, 32, 566},
|
|
{"USBC0_HCCHAR007" , 0x16F00100005E0ull, CVMX_CSR_DB_TYPE_NCB, 32, 566},
|
|
{"USBC0_HCFG" , 0x16F0010000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 567},
|
|
{"USBC0_HCINT000" , 0x16F0010000508ull, CVMX_CSR_DB_TYPE_NCB, 32, 568},
|
|
{"USBC0_HCINT001" , 0x16F0010000528ull, CVMX_CSR_DB_TYPE_NCB, 32, 568},
|
|
{"USBC0_HCINT002" , 0x16F0010000548ull, CVMX_CSR_DB_TYPE_NCB, 32, 568},
|
|
{"USBC0_HCINT003" , 0x16F0010000568ull, CVMX_CSR_DB_TYPE_NCB, 32, 568},
|
|
{"USBC0_HCINT004" , 0x16F0010000588ull, CVMX_CSR_DB_TYPE_NCB, 32, 568},
|
|
{"USBC0_HCINT005" , 0x16F00100005A8ull, CVMX_CSR_DB_TYPE_NCB, 32, 568},
|
|
{"USBC0_HCINT006" , 0x16F00100005C8ull, CVMX_CSR_DB_TYPE_NCB, 32, 568},
|
|
{"USBC0_HCINT007" , 0x16F00100005E8ull, CVMX_CSR_DB_TYPE_NCB, 32, 568},
|
|
{"USBC0_HCINTMSK000" , 0x16F001000050Cull, CVMX_CSR_DB_TYPE_NCB, 32, 569},
|
|
{"USBC0_HCINTMSK001" , 0x16F001000052Cull, CVMX_CSR_DB_TYPE_NCB, 32, 569},
|
|
{"USBC0_HCINTMSK002" , 0x16F001000054Cull, CVMX_CSR_DB_TYPE_NCB, 32, 569},
|
|
{"USBC0_HCINTMSK003" , 0x16F001000056Cull, CVMX_CSR_DB_TYPE_NCB, 32, 569},
|
|
{"USBC0_HCINTMSK004" , 0x16F001000058Cull, CVMX_CSR_DB_TYPE_NCB, 32, 569},
|
|
{"USBC0_HCINTMSK005" , 0x16F00100005ACull, CVMX_CSR_DB_TYPE_NCB, 32, 569},
|
|
{"USBC0_HCINTMSK006" , 0x16F00100005CCull, CVMX_CSR_DB_TYPE_NCB, 32, 569},
|
|
{"USBC0_HCINTMSK007" , 0x16F00100005ECull, CVMX_CSR_DB_TYPE_NCB, 32, 569},
|
|
{"USBC0_HCSPLT000" , 0x16F0010000504ull, CVMX_CSR_DB_TYPE_NCB, 32, 570},
|
|
{"USBC0_HCSPLT001" , 0x16F0010000524ull, CVMX_CSR_DB_TYPE_NCB, 32, 570},
|
|
{"USBC0_HCSPLT002" , 0x16F0010000544ull, CVMX_CSR_DB_TYPE_NCB, 32, 570},
|
|
{"USBC0_HCSPLT003" , 0x16F0010000564ull, CVMX_CSR_DB_TYPE_NCB, 32, 570},
|
|
{"USBC0_HCSPLT004" , 0x16F0010000584ull, CVMX_CSR_DB_TYPE_NCB, 32, 570},
|
|
{"USBC0_HCSPLT005" , 0x16F00100005A4ull, CVMX_CSR_DB_TYPE_NCB, 32, 570},
|
|
{"USBC0_HCSPLT006" , 0x16F00100005C4ull, CVMX_CSR_DB_TYPE_NCB, 32, 570},
|
|
{"USBC0_HCSPLT007" , 0x16F00100005E4ull, CVMX_CSR_DB_TYPE_NCB, 32, 570},
|
|
{"USBC0_HCTSIZ000" , 0x16F0010000510ull, CVMX_CSR_DB_TYPE_NCB, 32, 571},
|
|
{"USBC0_HCTSIZ001" , 0x16F0010000530ull, CVMX_CSR_DB_TYPE_NCB, 32, 571},
|
|
{"USBC0_HCTSIZ002" , 0x16F0010000550ull, CVMX_CSR_DB_TYPE_NCB, 32, 571},
|
|
{"USBC0_HCTSIZ003" , 0x16F0010000570ull, CVMX_CSR_DB_TYPE_NCB, 32, 571},
|
|
{"USBC0_HCTSIZ004" , 0x16F0010000590ull, CVMX_CSR_DB_TYPE_NCB, 32, 571},
|
|
{"USBC0_HCTSIZ005" , 0x16F00100005B0ull, CVMX_CSR_DB_TYPE_NCB, 32, 571},
|
|
{"USBC0_HCTSIZ006" , 0x16F00100005D0ull, CVMX_CSR_DB_TYPE_NCB, 32, 571},
|
|
{"USBC0_HCTSIZ007" , 0x16F00100005F0ull, CVMX_CSR_DB_TYPE_NCB, 32, 571},
|
|
{"USBC0_HFIR" , 0x16F0010000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 572},
|
|
{"USBC0_HFNUM" , 0x16F0010000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 573},
|
|
{"USBC0_HPRT" , 0x16F0010000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 574},
|
|
{"USBC0_HPTXFSIZ" , 0x16F0010000100ull, CVMX_CSR_DB_TYPE_NCB, 32, 575},
|
|
{"USBC0_HPTXSTS" , 0x16F0010000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 576},
|
|
{"USBC0_NPTXDFIFO000" , 0x16F0010001000ull, CVMX_CSR_DB_TYPE_NCB, 32, 577},
|
|
{"USBC0_NPTXDFIFO001" , 0x16F0010002000ull, CVMX_CSR_DB_TYPE_NCB, 32, 577},
|
|
{"USBC0_NPTXDFIFO002" , 0x16F0010003000ull, CVMX_CSR_DB_TYPE_NCB, 32, 577},
|
|
{"USBC0_NPTXDFIFO003" , 0x16F0010004000ull, CVMX_CSR_DB_TYPE_NCB, 32, 577},
|
|
{"USBC0_NPTXDFIFO004" , 0x16F0010005000ull, CVMX_CSR_DB_TYPE_NCB, 32, 577},
|
|
{"USBC0_NPTXDFIFO005" , 0x16F0010006000ull, CVMX_CSR_DB_TYPE_NCB, 32, 577},
|
|
{"USBC0_NPTXDFIFO006" , 0x16F0010007000ull, CVMX_CSR_DB_TYPE_NCB, 32, 577},
|
|
{"USBC0_NPTXDFIFO007" , 0x16F0010008000ull, CVMX_CSR_DB_TYPE_NCB, 32, 577},
|
|
{"USBC0_PCGCCTL" , 0x16F0010000E00ull, CVMX_CSR_DB_TYPE_NCB, 32, 578},
|
|
{"USBN0_BIST_STATUS" , 0x11800680007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 579},
|
|
{"USBN0_CLK_CTL" , 0x1180068000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 580},
|
|
{"USBN0_CTL_STATUS" , 0x16F0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 581},
|
|
{"USBN0_DMA0_INB_CHN0" , 0x16F0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 582},
|
|
{"USBN0_DMA0_INB_CHN1" , 0x16F0000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 583},
|
|
{"USBN0_DMA0_INB_CHN2" , 0x16F0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 584},
|
|
{"USBN0_DMA0_INB_CHN3" , 0x16F0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 585},
|
|
{"USBN0_DMA0_INB_CHN4" , 0x16F0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 586},
|
|
{"USBN0_DMA0_INB_CHN5" , 0x16F0000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 587},
|
|
{"USBN0_DMA0_INB_CHN6" , 0x16F0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 588},
|
|
{"USBN0_DMA0_INB_CHN7" , 0x16F0000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 589},
|
|
{"USBN0_DMA0_OUTB_CHN0" , 0x16F0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 590},
|
|
{"USBN0_DMA0_OUTB_CHN1" , 0x16F0000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 591},
|
|
{"USBN0_DMA0_OUTB_CHN2" , 0x16F0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 592},
|
|
{"USBN0_DMA0_OUTB_CHN3" , 0x16F0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 593},
|
|
{"USBN0_DMA0_OUTB_CHN4" , 0x16F0000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 594},
|
|
{"USBN0_DMA0_OUTB_CHN5" , 0x16F0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 595},
|
|
{"USBN0_DMA0_OUTB_CHN6" , 0x16F0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 596},
|
|
{"USBN0_DMA0_OUTB_CHN7" , 0x16F0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 597},
|
|
{"USBN0_DMA_TEST" , 0x16F0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 598},
|
|
{"USBN0_INT_ENB" , 0x1180068000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 599},
|
|
{"USBN0_INT_SUM" , 0x1180068000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 600},
|
|
{"USBN0_USBP_CTL_STATUS" , 0x1180068000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 601},
|
|
{"ZIP_CMD_BIST_RESULT" , 0x1180038000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 602},
|
|
{"ZIP_CMD_BUF" , 0x1180038000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 603},
|
|
{"ZIP_CMD_CTL" , 0x1180038000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 604},
|
|
{"ZIP_CONSTANTS" , 0x11800380000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
|
|
{"ZIP_DEBUG0" , 0x1180038000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 606},
|
|
{"ZIP_ERROR" , 0x1180038000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
|
|
{"ZIP_INT_MASK" , 0x1180038000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 608},
|
|
{NULL,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn31xx[] = {
|
|
/* name , bit, width, csr, type, rst un, typ un, reset, typical */
|
|
{"SETTING" , 0, 5, 0, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 0, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 1, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 1, "RAZ", 1, 1, 0, 0},
|
|
{"OVRFLW" , 0, 3, 2, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_3_3" , 3, 1, 2, "RAZ", 1, 1, 0, 0},
|
|
{"TXPOP" , 4, 3, 2, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_7_7" , 7, 1, 2, "RAZ", 1, 1, 0, 0},
|
|
{"TXPSH" , 8, 3, 2, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_11_63" , 11, 53, 2, "RAZ", 1, 1, 0, 0},
|
|
{"OVRFLW" , 0, 3, 3, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 3, "RAZ", 1, 1, 0, 0},
|
|
{"TXPOP" , 4, 3, 3, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 3, "RAZ", 1, 1, 0, 0},
|
|
{"TXPSH" , 8, 3, 3, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 3, "RAZ", 1, 1, 0, 0},
|
|
{"INT_LOOP" , 0, 3, 4, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 4, "RAZ", 1, 1, 0, 0},
|
|
{"EXT_LOOP" , 4, 3, 4, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 4, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 5, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_5_63" , 5, 59, 5, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_EN" , 0, 3, 6, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_3_63" , 3, 61, 6, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 7, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_5_63" , 5, 59, 7, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 4, 8, "R/W", 0, 0, 8ull, 8ull},
|
|
{"PCTL" , 4, 4, 8, "R/W", 0, 0, 8ull, 8ull},
|
|
{"BYPASS" , 8, 1, 8, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 8, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 3, 9, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 9, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_EN" , 0, 3, 10, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_3_63" , 3, 61, 10, "RAZ", 1, 1, 0, 0},
|
|
{"BIST" , 0, 4, 11, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 11, "RAZ", 1, 1, 0, 0},
|
|
{"DINT" , 0, 2, 12, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 12, "RAZ", 1, 1, 0, 0},
|
|
{"FUSE" , 0, 2, 13, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_2_63" , 2, 62, 13, "RAZ", 1, 1, 0, 0},
|
|
{"GSTOP" , 0, 1, 14, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 14, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWSI" , 45, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_49" , 49, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_51_51" , 51, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCM" , 57, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MPI" , 58, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_59_63" , 59, 5, 15, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 2, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 16, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 17, "RO", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 17, "RO", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 17, "RO", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 17, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 17, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 17, "RO", 0, 0, 0ull, 0ull},
|
|
{"WDOG_SUM" , 44, 1, 17, "RO", 0, 0, 0ull, 0ull},
|
|
{"TWSI" , 45, 1, 17, "RO", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 17, "RO", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 17, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 1, 17, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_49" , 49, 1, 17, "RAZ", 1, 1, 0, 0},
|
|
{"IPD_DRP" , 50, 1, 17, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_51_51" , 51, 1, 17, "RAZ", 1, 1, 0, 0},
|
|
{"TIMER" , 52, 4, 17, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 17, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCM" , 57, 1, 17, "RO", 0, 0, 0ull, 0ull},
|
|
{"MPI" , 58, 1, 17, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_59_63" , 59, 5, 17, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 2, 18, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 18, "RAZ", 1, 1, 0, 0},
|
|
{"BITS" , 0, 32, 19, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 19, "RAZ", 1, 1, 0, 0},
|
|
{"BITS" , 0, 32, 20, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 20, "RAZ", 1, 1, 0, 0},
|
|
{"NMI" , 0, 2, 21, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 21, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 0, 2, 22, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 22, "RAZ", 1, 1, 0, 0},
|
|
{"PPDBG" , 0, 2, 23, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 23, "RAZ", 1, 1, 0, 0},
|
|
{"POKE" , 0, 64, 24, "RAZ", 1, 1, 0, 0},
|
|
{"RST0" , 0, 1, 25, "R/W", 1, 1, 0, 0},
|
|
{"RST" , 1, 1, 25, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 25, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_BIST" , 0, 1, 26, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 26, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_PRST" , 0, 1, 27, "R/W", 0, 0, 1ull, 0ull},
|
|
{"NPI" , 1, 1, 27, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HOST64" , 2, 1, 27, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 27, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_RST" , 0, 1, 28, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 28, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 36, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ONE_SHOT" , 36, 1, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 29, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 0, 2, 30, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STATE" , 2, 2, 30, "RO", 0, 0, 0ull, 0ull},
|
|
{"LEN" , 4, 16, 30, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 20, 24, 30, "RO", 0, 0, 0ull, 0ull},
|
|
{"DSTOP" , 44, 1, 30, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GSTOPEN" , 45, 1, 30, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_46_63" , 46, 18, 30, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 17, 31, "RO", 0, 1, 0ull, 0},
|
|
{"DSEL_EXT" , 17, 1, 31, "R/W", 0, 0, 1ull, 0ull},
|
|
{"C_MUL" , 18, 5, 31, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_23_27" , 23, 5, 31, "RAZ", 1, 1, 0, 0},
|
|
{"PLL_MUL" , 28, 3, 31, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_31_63" , 31, 33, 31, "RAZ", 1, 1, 0, 0},
|
|
{"PDF" , 0, 16, 32, "RO", 0, 0, 0ull, 0ull},
|
|
{"RDF" , 16, 16, 32, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 32, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_17" , 0, 18, 33, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CRF" , 18, 1, 33, "RO", 0, 0, 0ull, 0ull},
|
|
{"DRF" , 19, 1, 33, "RO", 0, 0, 0ull, 0ull},
|
|
{"GFU" , 20, 1, 33, "RO", 0, 0, 0ull, 0ull},
|
|
{"IFU" , 21, 1, 33, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRQ" , 22, 1, 33, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 33, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DBELL" , 0, 20, 34, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_63" , 20, 44, 34, "RAZ", 1, 1, 0, 0},
|
|
{"NUM_COLS" , 0, 2, 35, "R/W", 0, 0, 1ull, 1ull},
|
|
{"NUM_COLROWS" , 2, 3, 35, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RNK_LO" , 5, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NUM_RNKS" , 6, 2, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RDIMM_ENA" , 8, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 35, "RAZ", 1, 1, 0, 0},
|
|
{"BUS_CNT" , 0, 47, 36, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_47_63" , 47, 17, 36, "RAZ", 1, 1, 0, 0},
|
|
{"PRTENA" , 0, 1, 37, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INIT" , 1, 1, 37, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FPRCH" , 2, 1, 37, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BPRCH" , 3, 1, 37, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SIL_LAT" , 4, 2, 37, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SILO_HC" , 6, 1, 37, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SILO_QC" , 7, 1, 37, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNK_MSK" , 8, 4, 37, "R/W", 0, 0, 0ull, 15ull},
|
|
{"TSKW" , 12, 2, 37, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_15" , 14, 2, 37, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"REF_INT" , 16, 13, 37, "R/W", 0, 0, 780ull, 780ull},
|
|
{"RESERVED_29_31" , 29, 3, 37, "RAZ", 1, 1, 0, 0},
|
|
{"FPIP" , 32, 3, 37, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRS_PGM" , 35, 1, 37, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRFC" , 36, 5, 37, "R/W", 0, 0, 9ull, 9ull},
|
|
{"RESERVED_41_63" , 41, 23, 37, "RAZ", 1, 1, 0, 0},
|
|
{"COMP_BYPASS" , 0, 1, 38, "R/W", 0, 0, 0ull, 1ull},
|
|
{"NCTL_CSR" , 1, 4, 38, "R/W", 0, 1, 13ull, 0},
|
|
{"PCTL_CSR" , 5, 4, 38, "R/W", 0, 1, 13ull, 0},
|
|
{"RESERVED_9_55" , 9, 47, 38, "RAZ", 1, 1, 0, 0},
|
|
{"DFA__NCTL" , 56, 4, 38, "RO", 1, 1, 0, 0},
|
|
{"DFA__PCTL" , 60, 4, 38, "RO", 1, 1, 0, 0},
|
|
{"EMRS1" , 0, 15, 39, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_15" , 15, 1, 39, "RAZ", 1, 1, 0, 0},
|
|
{"EMRS1_OCD" , 16, 15, 39, "R/W", 0, 0, 896ull, 896ull},
|
|
{"RESERVED_31_63" , 31, 33, 39, "RAZ", 1, 1, 0, 0},
|
|
{"FCYC_CNT" , 0, 47, 40, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_47_63" , 47, 17, 40, "RAZ", 1, 1, 0, 0},
|
|
{"MRS_DLL" , 0, 15, 41, "R/W", 0, 0, 1858ull, 1858ull},
|
|
{"RESERVED_15_15" , 15, 1, 41, "RAZ", 1, 1, 0, 0},
|
|
{"MRS" , 16, 15, 41, "R/W", 0, 0, 1602ull, 1602ull},
|
|
{"RESERVED_31_63" , 31, 33, 41, "RAZ", 1, 1, 0, 0},
|
|
{"MAX_WRITE_BATCH" , 0, 5, 42, "R/W", 0, 0, 31ull, 31ull},
|
|
{"MAX_READ_BATCH" , 5, 5, 42, "R/W", 0, 0, 31ull, 31ull},
|
|
{"RESERVED_10_63" , 10, 54, 42, "RAZ", 1, 1, 0, 0},
|
|
{"PLL_INIT" , 0, 1, 43, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PLL_BYPASS" , 1, 1, 43, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PLL_RATIO" , 2, 5, 43, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_7" , 7, 1, 43, "RAZ", 1, 1, 0, 0},
|
|
{"PLL_DIV2" , 8, 1, 43, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BW_UPD" , 9, 1, 43, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BW_CTL" , 10, 4, 43, "R/W", 0, 1, 0ull, 0},
|
|
{"QDLL_ENA" , 14, 1, 43, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DLL_BYP" , 15, 1, 43, "R/W", 0, 1, 0ull, 0},
|
|
{"DLL_SETTING" , 16, 5, 43, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_21_26" , 21, 6, 43, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING90" , 27, 5, 43, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_46" , 32, 15, 43, "RAZ", 1, 1, 0, 0},
|
|
{"PLL_SETTING" , 47, 17, 43, "RO", 0, 0, 0ull, 0ull},
|
|
{"DDR2T" , 0, 1, 44, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TMRD" , 1, 2, 44, "R/W", 0, 0, 2ull, 2ull},
|
|
{"CASLAT" , 3, 3, 44, "R/W", 0, 0, 4ull, 4ull},
|
|
{"POCAS" , 6, 1, 44, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDLAT" , 7, 3, 44, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRCD" , 10, 4, 44, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TRRD" , 14, 3, 44, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TRAS" , 17, 5, 44, "R/W", 0, 0, 10ull, 10ull},
|
|
{"TRP" , 22, 4, 44, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TWR" , 26, 3, 44, "R/W", 0, 0, 3ull, 3ull},
|
|
{"TWTR" , 29, 4, 44, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TFAW" , 33, 5, 44, "R/W", 0, 0, 9ull, 9ull},
|
|
{"R2R_SLOT" , 38, 1, 44, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DIC" , 39, 1, 44, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DQSN_ENA" , 40, 1, 44, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ODT_RTT" , 41, 2, 44, "R/W", 0, 0, 2ull, 2ull},
|
|
{"CTR_RST" , 43, 1, 44, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAVMIPO" , 44, 1, 44, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_CLR" , 45, 1, 44, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCNT_MODE" , 46, 1, 44, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_47_63" , 47, 17, 44, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 0, 9, 45, "R/W", 0, 1, 3ull, 0},
|
|
{"POOL" , 9, 3, 45, "R/W", 0, 1, 0ull, 0},
|
|
{"DWBCNT" , 12, 8, 45, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_20_63" , 20, 44, 45, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_4" , 0, 5, 46, "RAZ", 1, 1, 0, 0},
|
|
{"RDPTR" , 5, 31, 46, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 46, "RAZ", 1, 1, 0, 0},
|
|
{"DFA_FRSTN" , 0, 1, 47, "R/W", 0, 0, 0ull, 1ull},
|
|
{"MAXBNK" , 1, 1, 47, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DTECLKDIS" , 2, 1, 47, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_7" , 3, 5, 47, "RAZ", 0, 0, 0ull, 9ull},
|
|
{"SARB" , 8, 1, 47, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IMODE" , 9, 1, 47, "R/W", 0, 0, 1ull, 1ull},
|
|
{"QMODE" , 10, 1, 47, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PMODE" , 11, 1, 47, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DTMODE" , 12, 1, 47, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DCMODE" , 13, 1, 47, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SBDLCK" , 14, 1, 47, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_15" , 15, 1, 47, "RAZ", 1, 1, 0, 0},
|
|
{"SBDNUM" , 16, 3, 47, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 47, "RAZ", 1, 1, 0, 0},
|
|
{"CP2ECCENA" , 0, 1, 48, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2SBE" , 1, 1, 48, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CP2DBE" , 2, 1, 48, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CP2SBINA" , 3, 1, 48, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2DBINA" , 4, 1, 48, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2SYN" , 5, 8, 48, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTEECCENA" , 13, 1, 48, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DTESBE" , 14, 1, 48, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTEDBE" , 15, 1, 48, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTESBINA" , 16, 1, 48, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DTEDBINA" , 17, 1, 48, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DTESYN" , 18, 7, 48, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTEPARENA" , 25, 1, 48, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DTEPERR" , 26, 1, 48, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTEPINA" , 27, 1, 48, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2PARENA" , 28, 1, 48, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2PERR" , 29, 1, 48, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CP2PINA" , 30, 1, 48, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DBLOVF" , 31, 1, 48, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DBLINA" , 32, 1, 48, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_33_63" , 33, 31, 48, "RAZ", 1, 1, 0, 0},
|
|
{"MADDR" , 0, 25, 49, "RO", 0, 0, 0ull, 0ull},
|
|
{"BNUM" , 25, 3, 49, "RO", 0, 0, 0ull, 0ull},
|
|
{"PNUM" , 28, 1, 49, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSRC" , 29, 2, 49, "RO", 0, 0, 0ull, 0ull},
|
|
{"FDST" , 31, 9, 49, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 49, "RAZ", 1, 1, 0, 0},
|
|
{"SBD0" , 0, 64, 50, "RO", 1, 1, 0, 0},
|
|
{"SBD1" , 0, 64, 51, "RO", 1, 1, 0, 0},
|
|
{"SBD2" , 0, 64, 52, "RO", 1, 1, 0, 0},
|
|
{"SBD3" , 0, 64, 53, "RO", 1, 1, 0, 0},
|
|
{"FDR" , 0, 1, 54, "RO", 0, 0, 0ull, 0ull},
|
|
{"FFR" , 1, 1, 54, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPF1" , 2, 1, 54, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPF0" , 3, 1, 54, "RO", 0, 0, 0ull, 0ull},
|
|
{"FRD" , 4, 1, 54, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 54, "RAZ", 1, 1, 0, 0},
|
|
{"MEM0_ERR" , 0, 7, 55, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM1_ERR" , 7, 7, 55, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 14, 1, 55, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USE_STT" , 15, 1, 55, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USE_LDT" , 16, 1, 55, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 17, 1, 55, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 55, "RAZ", 1, 1, 0, 0},
|
|
{"FED0_SBE" , 0, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED0_DBE" , 1, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED1_SBE" , 2, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED1_DBE" , 3, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_UND" , 4, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_COFF" , 5, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_PERR" , 6, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_UND" , 7, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_COFF" , 8, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_PERR" , 9, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_UND" , 10, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_COFF" , 11, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_PERR" , 12, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_UND" , 13, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_COFF" , 14, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_PERR" , 15, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_UND" , 16, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_COFF" , 17, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_PERR" , 18, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_UND" , 19, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_COFF" , 20, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_PERR" , 21, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_UND" , 22, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_COFF" , 23, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_PERR" , 24, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_UND" , 25, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_COFF" , 26, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_PERR" , 27, 1, 56, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 56, "RAZ", 1, 1, 0, 0},
|
|
{"FED0_SBE" , 0, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED0_DBE" , 1, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED1_SBE" , 2, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED1_DBE" , 3, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_UND" , 4, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_COFF" , 5, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_PERR" , 6, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_UND" , 7, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_COFF" , 8, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_PERR" , 9, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_UND" , 10, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_COFF" , 11, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_PERR" , 12, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_UND" , 13, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_COFF" , 14, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_PERR" , 15, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_UND" , 16, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_COFF" , 17, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_PERR" , 18, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_UND" , 19, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_COFF" , 20, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_PERR" , 21, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_UND" , 22, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_COFF" , 23, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_PERR" , 24, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_UND" , 25, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_COFF" , 26, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_PERR" , 27, 1, 57, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 57, "RAZ", 1, 1, 0, 0},
|
|
{"QUE_SIZ" , 0, 29, 58, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 58, "RAZ", 1, 1, 0, 0},
|
|
{"PG_NUM" , 0, 25, 59, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 59, "RAZ", 1, 1, 0, 0},
|
|
{"ACT_INDX" , 0, 26, 60, "RO", 0, 1, 0ull, 0},
|
|
{"ACT_QUE" , 26, 3, 60, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 60, "RAZ", 0, 0, 0ull, 7ull},
|
|
{"EXP_INDX" , 0, 26, 61, "RO", 0, 1, 0ull, 0},
|
|
{"EXP_QUE" , 26, 3, 61, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 61, "RAZ", 0, 0, 0ull, 7ull},
|
|
{"CTL" , 0, 16, 62, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 62, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 32, 63, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 63, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 64, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OUT_OVR" , 2, 3, 64, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_21" , 5, 17, 64, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LOSTSTAT" , 22, 3, 64, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_25" , 25, 1, 64, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STATOVR" , 26, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INB_NXA" , 27, 4, 64, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 64, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 10, 65, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 65, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 1, 66, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 1, 1, 66, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 66, "RAZ", 1, 1, 0, 0},
|
|
{"PRT" , 0, 6, 67, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 67, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 68, "R/W", 0, 1, 0ull, 0},
|
|
{"SPEED" , 1, 1, 68, "R/W", 0, 1, 1ull, 0},
|
|
{"DUPLEX" , 2, 1, 68, "R/W", 0, 1, 1ull, 0},
|
|
{"SLOTTIME" , 3, 1, 68, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 68, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 64, 69, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 70, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 71, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 72, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 73, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 74, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 0, 8, 75, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 75, "RAZ", 1, 1, 0, 0},
|
|
{"BCST" , 0, 1, 76, "R/W", 0, 1, 1ull, 0},
|
|
{"MCST" , 1, 2, 76, "R/W", 0, 1, 0ull, 0},
|
|
{"CAM_MODE" , 3, 1, 76, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 76, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 5, 77, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_5_63" , 5, 59, 77, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 78, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CAREXT" , 1, 1, 78, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MAXERR" , 2, 1, 78, "R/W", 0, 0, 1ull, 1ull},
|
|
{"JABBER" , 3, 1, 78, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCSERR" , 4, 1, 78, "R/W", 0, 0, 1ull, 1ull},
|
|
{"ALNERR" , 5, 1, 78, "R/W", 0, 0, 1ull, 1ull},
|
|
{"LENERR" , 6, 1, 78, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RCVERR" , 7, 1, 78, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SKPERR" , 8, 1, 78, "R/W", 0, 0, 1ull, 1ull},
|
|
{"NIBERR" , 9, 1, 78, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_10_63" , 10, 54, 78, "RAZ", 1, 1, 0, 0},
|
|
{"PRE_CHK" , 0, 1, 79, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PRE_STRP" , 1, 1, 79, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_DRP" , 2, 1, 79, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_BCK" , 3, 1, 79, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_MCST" , 4, 1, 79, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_SMAC" , 5, 1, 79, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PRE_FREE" , 6, 1, 79, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VLAN_LEN" , 7, 1, 79, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 79, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 16, 80, "R/W", 0, 0, 1536ull, 1536ull},
|
|
{"RESERVED_16_63" , 16, 48, 80, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 16, 81, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_16_63" , 16, 48, 81, "RAZ", 1, 1, 0, 0},
|
|
{"IFG" , 0, 4, 82, "R/W", 0, 0, 12ull, 12ull},
|
|
{"RESERVED_4_63" , 4, 60, 82, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 83, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAREXT" , 1, 1, 83, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 2, 1, 83, "R/W", 0, 0, 0ull, 0ull},
|
|
{"JABBER" , 3, 1, 83, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 83, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ALNERR" , 5, 1, 83, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 6, 1, 83, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RCVERR" , 7, 1, 83, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 83, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NIBERR" , 9, 1, 83, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OVRERR" , 10, 1, 83, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 83, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 83, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 83, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 83, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 83, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHY_LINK" , 16, 1, 83, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHY_SPD" , 17, 1, 83, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHY_DUPX" , 18, 1, 83, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 83, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CAREXT" , 1, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 2, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"JABBER" , 3, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ALNERR" , 5, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 6, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RCVERR" , 7, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NIBERR" , 9, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OVRERR" , 10, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PHY_LINK" , 16, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PHY_SPD" , 17, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PHY_DUPX" , 18, 1, 84, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 84, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 85, "R/W", 0, 0, 10240ull, 10240ull},
|
|
{"RESERVED_16_63" , 16, 48, 85, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 1, 86, "RO", 0, 1, 0ull, 0},
|
|
{"SPEED" , 1, 2, 86, "RO", 0, 1, 0ull, 0},
|
|
{"DUPLEX" , 3, 1, 86, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 86, "RAZ", 1, 1, 0, 0},
|
|
{"RD_CLR" , 0, 1, 87, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 87, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 88, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 88, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 89, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 89, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 90, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 90, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 91, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 91, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 92, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 92, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 93, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 93, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 94, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 94, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 95, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 95, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 96, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 96, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 7, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 97, "RAZ", 1, 1, 0, 0},
|
|
{"FCSSEL" , 8, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 97, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 98, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_6_63" , 6, 58, 98, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 99, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_6_63" , 6, 58, 99, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 9, 100, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_9_63" , 9, 55, 100, "RAZ", 1, 1, 0, 0},
|
|
{"COMMIT" , 0, 3, 101, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_15" , 3, 13, 101, "RAZ", 1, 1, 0, 0},
|
|
{"DROP" , 16, 3, 101, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 101, "RAZ", 1, 1, 0, 0},
|
|
{"PRTS" , 0, 3, 102, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_3_63" , 3, 61, 102, "RAZ", 1, 1, 0, 0},
|
|
{"RX" , 0, 3, 103, "RC", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 103, "RAZ", 1, 1, 0, 0},
|
|
{"TX" , 4, 3, 103, "RC", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 103, "RAZ", 1, 1, 0, 0},
|
|
{"SMAC" , 0, 48, 104, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 104, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP" , 16, 1, 105, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 105, "RAZ", 1, 1, 0, 0},
|
|
{"PREAMBLE" , 0, 1, 106, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PAD" , 1, 1, 106, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCS" , 2, 1, 106, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FORCE_FCS" , 3, 1, 106, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 106, "RAZ", 1, 1, 0, 0},
|
|
{"BURST" , 0, 16, 107, "R/W", 0, 0, 8192ull, 8192ull},
|
|
{"RESERVED_16_63" , 16, 48, 107, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_CNT" , 0, 6, 108, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_63" , 6, 58, 108, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL_EN" , 0, 1, 109, "R/W", 0, 0, 1ull, 1ull},
|
|
{"XSDEF_EN" , 1, 1, 109, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 109, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_SIZE" , 0, 8, 110, "R/W", 0, 0, 59ull, 59ull},
|
|
{"RESERVED_8_63" , 8, 56, 110, "RAZ", 1, 1, 0, 0},
|
|
{"INTERVAL" , 0, 16, 111, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 111, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 112, "R/W", 0, 1, 96ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 112, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 113, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_16_63" , 16, 48, 113, "RAZ", 1, 1, 0, 0},
|
|
{"SEND" , 0, 1, 114, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 114, "RAZ", 1, 1, 0, 0},
|
|
{"SLOT" , 0, 10, 115, "R/W", 0, 0, 512ull, 512ull},
|
|
{"RESERVED_10_63" , 10, 54, 115, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 116, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 116, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL" , 0, 32, 117, "RC/W", 0, 1, 0ull, 0},
|
|
{"XSDEF" , 32, 32, 117, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCOL" , 0, 32, 118, "RC/W", 0, 1, 0ull, 0},
|
|
{"SCOL" , 32, 32, 118, "RC/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 119, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 119, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 120, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 120, "RAZ", 1, 1, 0, 0},
|
|
{"HIST0" , 0, 32, 121, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST1" , 32, 32, 121, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST2" , 0, 32, 122, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST3" , 32, 32, 122, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST4" , 0, 32, 123, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST5" , 32, 32, 123, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST6" , 0, 32, 124, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST7" , 32, 32, 124, "RC/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 0, 32, 125, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 32, 32, 125, "RC/W", 0, 1, 0ull, 0},
|
|
{"CTL" , 0, 32, 126, "RC/W", 0, 1, 0ull, 0},
|
|
{"UNDFLW" , 32, 32, 126, "RC/W", 0, 1, 0ull, 0},
|
|
{"RD_CLR" , 0, 1, 127, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 127, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 7, 128, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_7_63" , 7, 57, 128, "RAZ", 1, 1, 0, 0},
|
|
{"BP" , 0, 3, 129, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 129, "RAZ", 1, 1, 0, 0},
|
|
{"LIMIT" , 0, 5, 130, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_5_63" , 5, 59, 130, "RAZ", 1, 1, 0, 0},
|
|
{"CORRUPT" , 0, 3, 131, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_3_63" , 3, 61, 131, "RAZ", 1, 1, 0, 0},
|
|
{"IFG1" , 0, 4, 132, "R/W", 0, 1, 8ull, 0},
|
|
{"IFG2" , 4, 4, 132, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 132, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 133, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 133, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 3, 133, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_7" , 5, 3, 133, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 3, 133, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_11" , 11, 1, 133, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 3, 133, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 133, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PKO_NXA" , 0, 1, 134, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 134, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 3, 134, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_7" , 5, 3, 134, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 3, 134, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_11" , 11, 1, 134, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 3, 134, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 134, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"JAM" , 0, 8, 135, "R/W", 0, 1, 238ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 135, "RAZ", 1, 1, 0, 0},
|
|
{"LFSR" , 0, 16, 136, "R/W", 0, 1, 65535ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 136, "RAZ", 1, 1, 0, 0},
|
|
{"IGN_FULL" , 0, 3, 137, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 137, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"BP" , 4, 3, 137, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 137, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EN" , 8, 3, 137, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 137, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DMAC" , 0, 48, 138, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
|
|
{"RESERVED_48_63" , 48, 16, 138, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 139, "R/W", 0, 0, 34824ull, 34824ull},
|
|
{"RESERVED_16_63" , 16, 48, 139, "RAZ", 1, 1, 0, 0},
|
|
{"PRTS" , 0, 5, 140, "R/W", 0, 1, 3ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 140, "RAZ", 1, 1, 0, 0},
|
|
{"TX_OE" , 0, 1, 141, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RX_XOR" , 1, 1, 141, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_EN" , 2, 1, 141, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_TYPE" , 3, 1, 141, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_CNT" , 4, 4, 141, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_SEL" , 8, 4, 141, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 141, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 142, "RAZ", 1, 1, 0, 0},
|
|
{"BOOT_ENA" , 8, 4, 142, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_12_63" , 12, 52, 142, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_ENA" , 0, 21, 143, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_63" , 21, 43, 143, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 144, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 144, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 24, 145, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 145, "RAZ", 1, 1, 0, 0},
|
|
{"CLR" , 0, 24, 146, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 146, "RAZ", 1, 1, 0, 0},
|
|
{"SET" , 0, 24, 147, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 147, "RAZ", 1, 1, 0, 0},
|
|
{"TX_OE" , 0, 1, 148, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RX_XOR" , 1, 1, 148, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_3" , 2, 2, 148, "RAZ", 1, 1, 0, 0},
|
|
{"FIL_CNT" , 4, 4, 148, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_SEL" , 8, 4, 148, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 148, "RAZ", 1, 1, 0, 0},
|
|
{"ICD" , 0, 1, 149, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBD" , 1, 1, 149, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRP1" , 2, 1, 149, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRP0" , 3, 1, 149, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRN1" , 4, 1, 149, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRN0" , 5, 1, 149, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBRQ1" , 6, 1, 149, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBRQ0" , 7, 1, 149, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNRT" , 8, 1, 149, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBR1" , 9, 1, 149, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBR0" , 10, 1, 149, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBDR1" , 11, 1, 149, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBDR0" , 12, 1, 149, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNR0" , 13, 1, 149, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNR1" , 14, 1, 149, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICR1" , 15, 1, 149, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICR0" , 16, 1, 149, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNRCB" , 17, 1, 149, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 149, "RAZ", 1, 1, 0, 0},
|
|
{"FAU_END" , 0, 1, 150, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB_ENB" , 1, 1, 150, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PKO_ENB" , 2, 1, 150, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INB_MAT" , 3, 1, 150, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OUTB_MAT" , 4, 1, 150, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 150, "RAZ", 1, 1, 0, 0},
|
|
{"TOUT_VAL" , 0, 12, 151, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TOUT_ENB" , 12, 1, 151, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 151, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 8, 152, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 8, 9, 152, "R/W", 0, 1, 0ull, 0},
|
|
{"OPC" , 17, 4, 152, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 21, 8, 152, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 152, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 8, 153, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 8, 9, 153, "R/W", 0, 1, 0ull, 0},
|
|
{"OPC" , 17, 4, 153, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 21, 8, 153, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 153, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 154, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 155, "R/W", 0, 1, 0ull, 0},
|
|
{"NP_SOP" , 0, 1, 156, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NP_EOP" , 1, 1, 156, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_SOP" , 2, 1, 156, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_EOP" , 3, 1, 156, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 156, "RAZ", 1, 1, 0, 0},
|
|
{"NP_SOP" , 0, 1, 157, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NP_EOP" , 1, 1, 157, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_SOP" , 2, 1, 157, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_EOP" , 3, 1, 157, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 157, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 9, 158, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 9, 8, 158, "R/W", 0, 1, 0ull, 0},
|
|
{"EOT" , 17, 1, 158, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 18, 8, 158, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_26_63" , 26, 38, 158, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 9, 159, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 9, 8, 159, "R/W", 0, 1, 0ull, 0},
|
|
{"EOT" , 17, 1, 159, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 18, 8, 159, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_26_63" , 26, 38, 159, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 160, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 161, "R/W", 0, 1, 0ull, 0},
|
|
{"PORT" , 0, 6, 162, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 162, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP_SZ" , 0, 6, 163, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 163, "RAZ", 1, 1, 0, 0},
|
|
{"BACK" , 0, 4, 164, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 164, "RAZ", 1, 1, 0, 0},
|
|
{"BACK" , 0, 4, 165, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 165, "RAZ", 1, 1, 0, 0},
|
|
{"PWP" , 0, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_NEW" , 1, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_OLD" , 2, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRC_OFF" , 3, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ0" , 4, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ1" , 5, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM_WORD" , 6, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM0" , 7, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM1" , 8, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM2" , 9, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM3" , 10, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPQ_PBE0" , 11, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPQ_PBE1" , 12, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_POW" , 13, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_WP1" , 14, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_WQED" , 15, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 166, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_ENB" , 0, 36, 167, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 167, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_CNT" , 0, 64, 168, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_EN" , 0, 1, 169, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OPC_MODE" , 1, 2, 169, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PBP_EN" , 3, 1, 169, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WQE_LEND" , 4, 1, 169, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKT_LEND" , 5, 1, 169, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NADDBUF" , 6, 1, 169, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDPKT" , 7, 1, 169, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 8, 1, 169, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LEN_M8" , 9, 1, 169, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_10_63" , 10, 54, 169, "RAZ", 1, 1, 0, 0},
|
|
{"PRC_PAR0" , 0, 1, 170, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR1" , 1, 1, 170, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR2" , 2, 1, 170, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR3" , 3, 1, 170, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_SUB" , 4, 1, 170, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 170, "RAZ", 1, 1, 0, 0},
|
|
{"PRC_PAR0" , 0, 1, 171, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR1" , 1, 1, 171, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR2" , 2, 1, 171, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR3" , 3, 1, 171, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP_SUB" , 4, 1, 171, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 171, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP_SZ" , 0, 6, 172, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 172, "RAZ", 1, 1, 0, 0},
|
|
{"MB_SIZE" , 0, 12, 173, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_12_63" , 12, 52, 173, "RAZ", 1, 1, 0, 0},
|
|
{"PTR" , 0, 29, 174, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 174, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 17, 175, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_ENB" , 17, 1, 175, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 175, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 25, 176, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 176, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 3, 177, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 3, 1, 177, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 4, 29, 177, "RO", 1, 1, 0, 0},
|
|
{"PRADDR" , 33, 3, 177, "RO", 1, 1, 0, 0},
|
|
{"MAX_PKT" , 36, 3, 177, "RO", 0, 0, 5ull, 5ull},
|
|
{"RESERVED_39_63" , 39, 25, 177, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 7, 178, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 7, 1, 178, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 8, 29, 178, "RO", 1, 1, 0, 0},
|
|
{"MAX_PKT" , 37, 7, 178, "RO", 0, 0, 5ull, 5ull},
|
|
{"RESERVED_44_63" , 44, 20, 178, "RAZ", 1, 1, 0, 0},
|
|
{"WQE_PCNT" , 0, 7, 179, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_PCNT" , 7, 7, 179, "RO", 0, 0, 0ull, 0ull},
|
|
{"PFIF_CNT" , 14, 3, 179, "RO", 0, 0, 0ull, 0ull},
|
|
{"WQEV_CNT" , 17, 1, 179, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTV_CNT" , 18, 1, 179, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 179, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 8, 180, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 8, 1, 180, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 9, 29, 180, "RO", 1, 1, 0, 0},
|
|
{"PRADDR" , 38, 8, 180, "RO", 1, 1, 0, 0},
|
|
{"WRADDR" , 46, 8, 180, "RO", 1, 1, 0, 0},
|
|
{"MAX_CNTS" , 54, 7, 180, "RO", 0, 0, 8ull, 8ull},
|
|
{"RESERVED_61_63" , 61, 3, 180, "RAZ", 1, 1, 0, 0},
|
|
{"PASS" , 0, 32, 181, "R/W", 0, 1, 0ull, 0},
|
|
{"DROP" , 32, 32, 181, "R/W", 0, 1, 0ull, 0},
|
|
{"Q0_PCNT" , 0, 32, 182, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 182, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_ENB" , 0, 36, 183, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AVG_DLY" , 36, 14, 183, "R/W", 0, 1, 0ull, 0},
|
|
{"PRB_DLY" , 50, 14, 183, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRB_CON" , 0, 32, 184, "R/W", 0, 1, 0ull, 0},
|
|
{"AVG_CON" , 32, 8, 184, "R/W", 0, 1, 0ull, 0},
|
|
{"NEW_CON" , 40, 8, 184, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_PCNT" , 48, 1, 184, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 184, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 25, 185, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT" , 25, 6, 185, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 185, "RAZ", 1, 1, 0, 0},
|
|
{"PORT_BIT" , 0, 3, 186, "R/W", 0, 0, 7ull, 7ull},
|
|
{"RESERVED_3_63" , 3, 61, 186, "RAZ", 1, 1, 0, 0},
|
|
{"WQE_POOL" , 0, 3, 187, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_3_63" , 3, 61, 187, "RAZ", 1, 1, 0, 0},
|
|
{"PTR" , 0, 29, 188, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 188, "RAZ", 1, 1, 0, 0},
|
|
{"WLB_DAT" , 0, 4, 189, "RO", 0, 0, 0ull, 0ull},
|
|
{"STIN_MSK" , 4, 1, 189, "RO", 0, 0, 0ull, 0ull},
|
|
{"DT" , 5, 1, 189, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTCNT" , 6, 10, 189, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_18" , 16, 3, 189, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WLB_MSK" , 19, 4, 189, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 189, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"L2T" , 0, 5, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_8" , 5, 4, 190, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VAB_VWCF" , 9, 1, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"LRF" , 10, 2, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"VWDF" , 12, 4, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 190, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XRDDAT" , 0, 1, 191, "RO", 0, 0, 0ull, 0ull},
|
|
{"XRDMSK" , 1, 1, 191, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 191, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IPCBST" , 3, 1, 191, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 191, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RMDF" , 8, 4, 191, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRB" , 12, 4, 191, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 191, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LRF_ARB_MODE" , 0, 1, 192, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RFB_ARB_MODE" , 1, 1, 192, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RSP_ARB_MODE" , 2, 1, 192, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MWF_CRD" , 3, 4, 192, "R/W", 0, 0, 2ull, 2ull},
|
|
{"IDXALIAS" , 7, 1, 192, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPEN" , 8, 1, 192, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FPEMPTY" , 9, 1, 192, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FPEXP" , 10, 4, 192, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 192, "RAZ", 1, 1, 0, 0},
|
|
{"L2T" , 0, 1, 193, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2D" , 1, 1, 193, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FINV" , 2, 1, 193, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SET" , 3, 2, 193, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_5" , 5, 1, 193, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PPNUM" , 6, 1, 193, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_9" , 7, 3, 193, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_DMP" , 10, 1, 193, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LFB_ENUM" , 11, 3, 193, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 193, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DT_TAG" , 0, 29, 194, "RO", 0, 0, 0ull, 0ull},
|
|
{"DT_VLD" , 29, 1, 194, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_30" , 30, 1, 194, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DTENA" , 31, 1, 194, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 194, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_ENA" , 0, 1, 195, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_3" , 1, 3, 195, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_BASE" , 4, 27, 195, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 195, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_OFFSET" , 0, 10, 196, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 196, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VLD" , 0, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"CMD" , 1, 4, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"SID" , 5, 9, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"VABNUM" , 14, 3, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_17" , 17, 1, 197, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SET" , 18, 2, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 197, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IHD" , 21, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"ITL" , 22, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"INXT" , 23, 3, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_26" , 26, 1, 197, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VAM" , 27, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"STCFL" , 28, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"STINV" , 29, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"STPND" , 30, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"STCPND" , 31, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 197, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VLD" , 0, 1, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTPRB" , 1, 1, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRBRTY" , 2, 1, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTMFL" , 3, 1, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTVTM" , 4, 1, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTRSC" , 5, 1, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTRSP" , 6, 1, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTDT" , 7, 1, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTRDA" , 8, 1, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTM" , 9, 1, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWRM" , 10, 1, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWHF" , 11, 1, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWHP" , 12, 1, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTDQ" , 13, 1, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTDW" , 14, 1, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTRSP" , 15, 1, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"BID" , 16, 2, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"DSGOING" , 18, 1, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 198, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_IDX" , 0, 10, 199, "RO", 0, 0, 0ull, 0ull},
|
|
{"LFB_TAG" , 10, 17, 199, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_63" , 27, 37, 199, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_HWM" , 0, 3, 200, "R/W", 0, 0, 7ull, 7ull},
|
|
{"RESERVED_3_3" , 3, 1, 200, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STPARTDIS" , 4, 1, 200, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 200, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PFCNT0" , 0, 36, 201, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 201, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT0SEL" , 0, 6, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0CLR" , 6, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0ENA" , 7, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1SEL" , 8, 6, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1CLR" , 14, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1ENA" , 15, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2SEL" , 16, 6, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2CLR" , 22, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2ENA" , 23, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3SEL" , 24, 6, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3CLR" , 30, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3ENA" , 31, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0RDCLR" , 32, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1RDCLR" , 33, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2RDCLR" , 34, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3RDCLR" , 35, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 202, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK0" , 0, 4, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 203, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK1" , 8, 4, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 203, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSKIOB" , 0, 4, 204, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 204, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q0STAT" , 0, 34, 205, "RO", 0, 0, 0ull, 0ull},
|
|
{"FTL" , 34, 1, 205, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_35_63" , 35, 29, 205, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q1STAT" , 0, 34, 206, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 206, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q2STAT" , 0, 34, 207, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 207, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q3STAT" , 0, 34, 208, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 208, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 0, 1, 209, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_INTENA" , 1, 1, 209, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DED_INTENA" , 2, 1, 209, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 3, 1, 209, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 4, 1, 209, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BMHCLSEL" , 5, 1, 209, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 209, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 0, 10, 210, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_10" , 10, 1, 210, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSET" , 11, 2, 210, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_13" , 13, 1, 210, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FOWMSK" , 14, 4, 210, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 210, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW0" , 0, 10, 211, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW1" , 10, 10, 211, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 211, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW2" , 0, 10, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW3" , 10, 10, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 212, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q0FUS" , 0, 34, 213, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 213, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q1FUS" , 0, 34, 214, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 214, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q2FUS" , 0, 34, 215, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 215, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q3FUS" , 0, 34, 216, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRIP_128K" , 34, 1, 216, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_35_63" , 35, 29, 216, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 0, 1, 217, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_INTENA" , 1, 1, 217, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DED_INTENA" , 2, 1, 217, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 3, 1, 217, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 4, 1, 217, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FSYN" , 5, 6, 217, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 11, 9, 217, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 217, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSET" , 21, 2, 217, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 217, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCKERR" , 24, 1, 217, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK_INTENA" , 25, 1, 217, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LCKERR2" , 26, 1, 217, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK_INTENA2" , 27, 1, 217, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_28_63" , 28, 36, 217, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PCTL_DAT" , 0, 4, 218, "R/W", 0, 1, 0ull, 0},
|
|
{"PCTL_CMD" , 4, 4, 218, "R/W", 0, 1, 0ull, 0},
|
|
{"PCTL_CLK" , 8, 4, 218, "R/W", 0, 1, 0ull, 0},
|
|
{"PCTL_CSR" , 12, 4, 218, "R/W", 0, 1, 15ull, 0},
|
|
{"NCTL_DAT" , 16, 4, 218, "R/W", 0, 1, 0ull, 0},
|
|
{"NCTL_CMD" , 20, 4, 218, "R/W", 0, 1, 0ull, 0},
|
|
{"NCTL_CLK" , 24, 4, 218, "R/W", 0, 1, 0ull, 0},
|
|
{"NCTL_CSR" , 28, 4, 218, "R/W", 0, 1, 15ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 218, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DIC" , 0, 2, 219, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QS_DIC" , 2, 2, 219, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TSKW" , 4, 2, 219, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SIL_LAT" , 6, 2, 219, "R/W", 0, 0, 1ull, 1ull},
|
|
{"BPRCH" , 8, 1, 219, "R/W", 0, 1, 0ull, 0},
|
|
{"FPRCH2" , 9, 1, 219, "R/W", 0, 0, 0ull, 1ull},
|
|
{"MODE32B" , 10, 1, 219, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRESET" , 11, 1, 219, "R/W", 0, 0, 1ull, 0ull},
|
|
{"INORDER_MRF" , 12, 1, 219, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INORDER_MWF" , 13, 1, 219, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"R2R_SLOT" , 14, 1, 219, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RDIMM_ENA" , 15, 1, 219, "R/W", 0, 1, 0ull, 0},
|
|
{"PLL_BYPASS" , 16, 1, 219, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PLL_DIV2" , 17, 1, 219, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAX_WRITE_BATCH" , 18, 4, 219, "R/W", 0, 0, 8ull, 8ull},
|
|
{"XOR_BANK" , 22, 1, 219, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SLOW_SCF" , 23, 1, 219, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DDR__PCTL" , 24, 4, 219, "RO", 1, 1, 0, 0},
|
|
{"DDR__NCTL" , 28, 4, 219, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 219, "RAZ", 1, 1, 0, 0},
|
|
{"DCLKCNT_HI" , 0, 32, 220, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 220, "RAZ", 1, 1, 0, 0},
|
|
{"DCLKCNT_LO" , 0, 32, 221, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 221, "RAZ", 1, 1, 0, 0},
|
|
{"DDR2" , 0, 1, 222, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_1" , 1, 1, 222, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DLL90_BYP" , 2, 1, 222, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLL90_VLU" , 3, 5, 222, "R/W", 0, 1, 0ull, 0},
|
|
{"QDLL_ENA" , 8, 1, 222, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ODT_ENA" , 9, 1, 222, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DDR2T" , 10, 1, 222, "R/W", 0, 1, 0ull, 0},
|
|
{"CRIP_MODE" , 11, 1, 222, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TFAW" , 12, 5, 222, "R/W", 0, 0, 0ull, 9ull},
|
|
{"DDR_EOF" , 17, 4, 222, "R/W", 0, 0, 2ull, 2ull},
|
|
{"SILO_HC" , 21, 1, 222, "R/W", 0, 1, 1ull, 0},
|
|
{"TWR" , 22, 3, 222, "R/W", 0, 0, 3ull, 1ull},
|
|
{"BWCNT" , 25, 1, 222, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POCAS" , 26, 1, 222, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDLAT" , 27, 3, 222, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BURST8" , 30, 1, 222, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BANK8" , 31, 1, 222, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 222, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN0" , 0, 8, 223, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN1" , 8, 8, 223, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN2" , 16, 8, 223, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN3" , 24, 8, 223, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 223, "RAZ", 1, 1, 0, 0},
|
|
{"FCOL" , 0, 12, 224, "RO", 0, 0, 0ull, 0ull},
|
|
{"FROW" , 12, 14, 224, "RO", 0, 0, 0ull, 0ull},
|
|
{"FBANK" , 26, 3, 224, "RO", 0, 0, 0ull, 0ull},
|
|
{"FBUNK" , 29, 1, 224, "RO", 0, 0, 0ull, 0ull},
|
|
{"FDIMM" , 30, 2, 224, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 224, "RAZ", 1, 1, 0, 0},
|
|
{"IFBCNT_HI" , 0, 32, 225, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 225, "RAZ", 1, 1, 0, 0},
|
|
{"IFBCNT_LO" , 0, 32, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 226, "RAZ", 1, 1, 0, 0},
|
|
{"INIT_START" , 0, 1, 227, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 1, 1, 227, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ROW_LSB" , 2, 3, 227, "R/W", 0, 1, 3ull, 0},
|
|
{"PBANK_LSB" , 5, 4, 227, "R/W", 0, 1, 5ull, 0},
|
|
{"REF_INT" , 9, 6, 227, "R/W", 0, 0, 1ull, 2ull},
|
|
{"TCL" , 15, 4, 227, "R/W", 0, 1, 3ull, 0},
|
|
{"INTR_SEC_ENA" , 19, 1, 227, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INTR_DED_ENA" , 20, 1, 227, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 21, 4, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 25, 4, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BUNK_ENA" , 29, 1, 227, "R/W", 0, 1, 0ull, 0},
|
|
{"SILO_QC" , 30, 1, 227, "R/W", 0, 1, 0ull, 0},
|
|
{"RESET" , 31, 1, 227, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 227, "RAZ", 1, 1, 0, 0},
|
|
{"TRAS" , 0, 5, 228, "R/W", 0, 0, 12ull, 12ull},
|
|
{"TRCD" , 5, 4, 228, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TWTR" , 9, 4, 228, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TRP" , 13, 4, 228, "R/W", 0, 0, 5ull, 4ull},
|
|
{"TRFC" , 17, 5, 228, "R/W", 0, 0, 6ull, 7ull},
|
|
{"TMRD" , 22, 3, 228, "R/W", 0, 0, 2ull, 2ull},
|
|
{"CASLAT" , 25, 3, 228, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TRRD" , 28, 3, 228, "R/W", 0, 0, 2ull, 2ull},
|
|
{"COMP_BYPASS" , 31, 1, 228, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 228, "RAZ", 1, 1, 0, 0},
|
|
{"OPSCNT_HI" , 0, 32, 229, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 229, "RAZ", 1, 1, 0, 0},
|
|
{"OPSCNT_LO" , 0, 32, 230, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 230, "RAZ", 1, 1, 0, 0},
|
|
{"BWCTL" , 0, 4, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BWUPD" , 4, 1, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 231, "RAZ", 1, 1, 0, 0},
|
|
{"RODT_LO0" , 0, 4, 232, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_LO1" , 4, 4, 232, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_LO2" , 8, 4, 232, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_LO3" , 12, 4, 232, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI0" , 16, 4, 232, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI1" , 20, 4, 232, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI2" , 24, 4, 232, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI3" , 28, 4, 232, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_32_63" , 32, 32, 232, "RAZ", 1, 1, 0, 0},
|
|
{"WODT_D0_R0" , 0, 8, 233, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D0_R1" , 8, 8, 233, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D1_R0" , 16, 8, 233, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D1_R1" , 24, 8, 233, "R/W", 0, 0, 255ull, 255ull},
|
|
{"RESERVED_32_63" , 32, 32, 233, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WODT_D2_R0" , 0, 8, 234, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D2_R1" , 8, 8, 234, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D3_R0" , 16, 8, 234, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D3_R1" , 24, 8, 234, "R/W", 0, 0, 255ull, 255ull},
|
|
{"RESERVED_32_63" , 32, 32, 234, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"NCBI" , 0, 1, 235, "RO", 0, 0, 0ull, 0ull},
|
|
{"LOC" , 1, 1, 235, "RO", 0, 0, 0ull, 0ull},
|
|
{"NCBO_0" , 2, 1, 235, "RO", 0, 0, 0ull, 0ull},
|
|
{"NCBO_1" , 3, 1, 235, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 235, "RAZ", 1, 1, 0, 0},
|
|
{"ADR_ERR" , 0, 1, 236, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WAIT_ERR" , 1, 1, 236, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 236, "RAZ", 1, 1, 0, 0},
|
|
{"ADR_INT" , 0, 1, 237, "R/W", 0, 1, 0ull, 0},
|
|
{"WAIT_INT" , 1, 1, 237, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 237, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 238, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 3, 5, 238, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 238, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 239, "RAZ", 1, 1, 0, 0},
|
|
{"BASE" , 3, 25, 239, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_30" , 28, 3, 239, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 31, 1, 239, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 239, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 240, "R/W", 1, 1, 0, 0},
|
|
{"BASE" , 0, 16, 241, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 16, 12, 241, "R/W", 0, 1, 0ull, 0},
|
|
{"WIDTH" , 28, 1, 241, "R/W", 0, 1, 0ull, 0},
|
|
{"ALE" , 29, 1, 241, "R/W", 0, 1, 0ull, 0},
|
|
{"ORBIT" , 30, 1, 241, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 31, 1, 241, "R/W", 0, 1, 0ull, 0},
|
|
{"OE_EXT" , 32, 2, 241, "R/W", 0, 1, 0ull, 0},
|
|
{"WE_EXT" , 34, 2, 241, "R/W", 0, 1, 0ull, 0},
|
|
{"SAM" , 36, 1, 241, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_37_63" , 37, 27, 241, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 6, 242, "R/W", 0, 1, 63ull, 0},
|
|
{"CE" , 6, 6, 242, "R/W", 0, 1, 63ull, 0},
|
|
{"OE" , 12, 6, 242, "R/W", 0, 1, 63ull, 0},
|
|
{"WE" , 18, 6, 242, "R/W", 0, 1, 63ull, 0},
|
|
{"RD_HLD" , 24, 6, 242, "R/W", 0, 1, 63ull, 0},
|
|
{"WR_HLD" , 30, 6, 242, "R/W", 0, 1, 63ull, 0},
|
|
{"PAUSE" , 36, 6, 242, "R/W", 0, 1, 63ull, 0},
|
|
{"WAIT" , 42, 6, 242, "R/W", 0, 1, 63ull, 0},
|
|
{"PAGE" , 48, 6, 242, "R/W", 0, 1, 63ull, 0},
|
|
{"ALE" , 54, 6, 242, "R/W", 0, 1, 63ull, 0},
|
|
{"PAGES" , 60, 2, 242, "R/W", 0, 1, 0ull, 0},
|
|
{"WAITM" , 62, 1, 242, "R/W", 0, 1, 0ull, 0},
|
|
{"PAGEM" , 63, 1, 242, "R/W", 0, 1, 0ull, 0},
|
|
{"FIF_THR" , 0, 6, 243, "R/W", 0, 0, 26ull, 26ull},
|
|
{"RESERVED_6_7" , 6, 2, 243, "RAZ", 1, 1, 0, 0},
|
|
{"FIF_CNT" , 8, 6, 243, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_63" , 14, 50, 243, "RAZ", 1, 1, 0, 0},
|
|
{"MAN_INFO" , 0, 32, 244, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 244, "RAZ", 1, 1, 0, 0},
|
|
{"MAN_INFO" , 0, 32, 245, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 245, "RAZ", 1, 1, 0, 0},
|
|
{"PP_DIS" , 0, 2, 246, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_2_11" , 2, 10, 246, "RAZ", 1, 1, 0, 0},
|
|
{"PLL_OFF" , 12, 4, 246, "RO", 1, 1, 0, 0},
|
|
{"CHIP_ID" , 16, 8, 246, "RO", 1, 1, 0, 0},
|
|
{"BIST_DIS" , 24, 1, 246, "RO", 1, 1, 0, 0},
|
|
{"RST_SHT" , 25, 1, 246, "RO", 1, 1, 0, 0},
|
|
{"NOCRYPTO" , 26, 1, 246, "RO", 1, 1, 0, 0},
|
|
{"NOMUL" , 27, 1, 246, "RO", 1, 1, 0, 0},
|
|
{"NODFA_CP2" , 28, 1, 246, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 246, "RAZ", 1, 1, 0, 0},
|
|
{"ICACHE" , 0, 24, 247, "RO", 1, 1, 0, 0},
|
|
{"NODFA_DTE" , 24, 1, 247, "RO", 1, 1, 0, 0},
|
|
{"NOZIP" , 25, 1, 247, "RO", 1, 1, 0, 0},
|
|
{"EFUS_IGN" , 26, 1, 247, "RO", 1, 1, 0, 0},
|
|
{"EFUS_LCK" , 27, 1, 247, "RO", 1, 1, 0, 0},
|
|
{"BAR2_EN" , 28, 1, 247, "RO", 1, 1, 0, 0},
|
|
{"ZIP_CRIP" , 29, 2, 247, "RO", 1, 1, 0, 0},
|
|
{"PLL_DIV4" , 31, 1, 247, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 247, "RAZ", 1, 1, 0, 0},
|
|
{"PROG" , 0, 1, 248, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_1_63" , 1, 63, 248, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 7, 249, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 249, "RAZ", 1, 1, 0, 0},
|
|
{"EFUSE" , 8, 1, 249, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 249, "RAZ", 1, 1, 0, 0},
|
|
{"PEND" , 12, 1, 249, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 249, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 16, 8, 249, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_24_63" , 24, 40, 249, "RAZ", 1, 1, 0, 0},
|
|
{"REPAIR0" , 0, 14, 250, "RO", 0, 0, 0ull, 0ull},
|
|
{"REPAIR1" , 14, 14, 250, "RO", 0, 0, 0ull, 0ull},
|
|
{"REPAIR2" , 28, 14, 250, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_42_63" , 42, 22, 250, "RAZ", 1, 1, 0, 0},
|
|
{"TOO_MANY" , 0, 1, 251, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 251, "RAZ", 1, 1, 0, 0},
|
|
{"KEY" , 0, 24, 252, "R/W", 0, 0, 0ull, 5071723ull},
|
|
{"RESERVED_24_63" , 24, 40, 252, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 10, 253, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_10_63" , 10, 54, 253, "RAZ", 1, 1, 0, 0},
|
|
{"BW_CTL" , 0, 5, 254, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 254, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SETTING" , 0, 17, 255, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_17_63" , 17, 47, 255, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ST_INT" , 0, 1, 256, "R/W1C", 0, 1, 0ull, 0},
|
|
{"TS_INT" , 1, 1, 256, "R/W1C", 0, 1, 0ull, 0},
|
|
{"CORE_INT" , 2, 1, 256, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_3" , 3, 1, 256, "RAZ", 1, 1, 0, 0},
|
|
{"ST_EN" , 4, 1, 256, "R/W", 0, 1, 0ull, 0},
|
|
{"TS_EN" , 5, 1, 256, "R/W", 0, 1, 0ull, 0},
|
|
{"CORE_EN" , 6, 1, 256, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_7" , 7, 1, 256, "RAZ", 1, 1, 0, 0},
|
|
{"SDA_OVR" , 8, 1, 256, "R/W", 0, 1, 0ull, 0},
|
|
{"SCL_OVR" , 9, 1, 256, "R/W", 0, 1, 0ull, 0},
|
|
{"SDA" , 10, 1, 256, "RO", 1, 1, 0, 0},
|
|
{"SCL" , 11, 1, 256, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_12_63" , 12, 52, 256, "RAZ", 1, 1, 0, 0},
|
|
{"D" , 0, 32, 257, "R/W", 0, 1, 0ull, 0},
|
|
{"EOP_IA" , 32, 3, 257, "R/W", 0, 1, 0ull, 0},
|
|
{"IA" , 35, 5, 257, "R/W", 0, 1, 0ull, 0},
|
|
{"A" , 40, 10, 257, "R/W", 0, 1, 0ull, 0},
|
|
{"SCR" , 50, 2, 257, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 52, 3, 257, "R/W", 0, 1, 0ull, 0},
|
|
{"SOVR" , 55, 1, 257, "R/W", 0, 1, 0ull, 0},
|
|
{"R" , 56, 1, 257, "R/W", 0, 1, 0ull, 0},
|
|
{"OP" , 57, 4, 257, "R/W", 0, 1, 0ull, 0},
|
|
{"EIA" , 61, 1, 257, "R/W", 0, 1, 0ull, 0},
|
|
{"SLONLY" , 62, 1, 257, "R/W", 0, 1, 0ull, 0},
|
|
{"V" , 63, 1, 257, "RC/W", 0, 1, 0ull, 0},
|
|
{"D" , 0, 32, 258, "R/W", 0, 1, 0ull, 0},
|
|
{"IA" , 32, 8, 258, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_40_63" , 40, 24, 258, "RAZ", 1, 1, 0, 0},
|
|
{"D" , 0, 32, 259, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_32_61" , 32, 30, 259, "RAZ", 1, 1, 0, 0},
|
|
{"V" , 62, 2, 259, "RC/W", 0, 1, 0ull, 0},
|
|
{"DLH" , 0, 8, 260, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 260, "RAZ", 1, 1, 0, 0},
|
|
{"DLL" , 0, 8, 261, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 261, "RAZ", 1, 1, 0, 0},
|
|
{"FAR" , 0, 1, 262, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 262, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 263, "WO", 0, 1, 0ull, 0},
|
|
{"RXFR" , 1, 1, 263, "WO", 0, 1, 0ull, 0},
|
|
{"TXFR" , 2, 1, 263, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_3" , 3, 1, 263, "RAZ", 0, 1, 0ull, 0},
|
|
{"TXTRIG" , 4, 2, 263, "WO", 0, 1, 0ull, 0},
|
|
{"RXTRIG" , 6, 2, 263, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 263, "RAZ", 1, 1, 0, 0},
|
|
{"HTX" , 0, 1, 264, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 264, "RAZ", 1, 1, 0, 0},
|
|
{"ERBFI" , 0, 1, 265, "R/W", 0, 1, 0ull, 0},
|
|
{"ETBEI" , 1, 1, 265, "R/W", 0, 1, 0ull, 0},
|
|
{"ELSI" , 2, 1, 265, "R/W", 0, 1, 0ull, 0},
|
|
{"EDSSI" , 3, 1, 265, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_6" , 4, 3, 265, "RAZ", 0, 1, 0ull, 0},
|
|
{"PTIME" , 7, 1, 265, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 265, "RAZ", 1, 1, 0, 0},
|
|
{"IID" , 0, 4, 266, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_4_5" , 4, 2, 266, "RAZ", 0, 1, 0ull, 0},
|
|
{"FEN" , 6, 2, 266, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 266, "RAZ", 1, 1, 0, 0},
|
|
{"CLS" , 0, 2, 267, "R/W", 0, 1, 0ull, 0},
|
|
{"STOP" , 2, 1, 267, "R/W", 0, 1, 0ull, 0},
|
|
{"PEN" , 3, 1, 267, "R/W", 0, 1, 0ull, 0},
|
|
{"EPS" , 4, 1, 267, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_5" , 5, 1, 267, "RAZ", 0, 1, 0ull, 0},
|
|
{"BRK" , 6, 1, 267, "R/W", 0, 1, 0ull, 0},
|
|
{"DLAB" , 7, 1, 267, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 267, "RAZ", 1, 1, 0, 0},
|
|
{"DR" , 0, 1, 268, "RO", 0, 1, 0ull, 0},
|
|
{"OE" , 1, 1, 268, "RC", 0, 1, 0ull, 0},
|
|
{"PE" , 2, 1, 268, "RC", 0, 1, 0ull, 0},
|
|
{"FE" , 3, 1, 268, "RC", 0, 1, 0ull, 0},
|
|
{"BI" , 4, 1, 268, "RC", 0, 1, 0ull, 0},
|
|
{"THRE" , 5, 1, 268, "RO", 0, 1, 1ull, 0},
|
|
{"TEMT" , 6, 1, 268, "RO", 0, 1, 1ull, 0},
|
|
{"FERR" , 7, 1, 268, "RC", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 268, "RAZ", 1, 1, 0, 0},
|
|
{"DTR" , 0, 1, 269, "R/W", 0, 1, 0ull, 0},
|
|
{"RTS" , 1, 1, 269, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT1" , 2, 1, 269, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT2" , 3, 1, 269, "R/W", 0, 1, 0ull, 0},
|
|
{"LOOP" , 4, 1, 269, "R/W", 0, 1, 0ull, 0},
|
|
{"AFCE" , 5, 1, 269, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 269, "RAZ", 0, 1, 0ull, 0},
|
|
{"DCTS" , 0, 1, 270, "RC", 0, 1, 0ull, 0},
|
|
{"DDSR" , 1, 1, 270, "RC", 0, 1, 0ull, 0},
|
|
{"TERI" , 2, 1, 270, "RC", 0, 1, 0ull, 0},
|
|
{"DDCD" , 3, 1, 270, "RC", 0, 1, 0ull, 0},
|
|
{"CTS" , 4, 1, 270, "RO", 1, 1, 0, 0},
|
|
{"DSR" , 5, 1, 270, "RO", 0, 1, 0ull, 0},
|
|
{"RI" , 6, 1, 270, "RO", 0, 1, 0ull, 0},
|
|
{"DCD" , 7, 1, 270, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 270, "RAZ", 1, 1, 0, 0},
|
|
{"RBR" , 0, 8, 271, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 271, "RAZ", 1, 1, 0, 0},
|
|
{"RFL" , 0, 7, 272, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 272, "RAZ", 1, 1, 0, 0},
|
|
{"RFWD" , 0, 8, 273, "WO", 0, 1, 0ull, 0},
|
|
{"RFPE" , 8, 1, 273, "WO", 0, 1, 0ull, 0},
|
|
{"RFFE" , 9, 1, 273, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_10_63" , 10, 54, 273, "RAZ", 1, 1, 0, 0},
|
|
{"SBCR" , 0, 1, 274, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 274, "RAZ", 1, 1, 0, 0},
|
|
{"SCR" , 0, 8, 275, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 275, "RAZ", 1, 1, 0, 0},
|
|
{"SFE" , 0, 1, 276, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 276, "RAZ", 1, 1, 0, 0},
|
|
{"USR" , 0, 1, 277, "WO", 0, 1, 0ull, 0},
|
|
{"SRFR" , 1, 1, 277, "WO", 0, 1, 0ull, 0},
|
|
{"STFR" , 2, 1, 277, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_63" , 3, 61, 277, "RAZ", 1, 1, 0, 0},
|
|
{"SRT" , 0, 2, 278, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 278, "RAZ", 1, 1, 0, 0},
|
|
{"SRTS" , 0, 1, 279, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 279, "RAZ", 1, 1, 0, 0},
|
|
{"STT" , 0, 2, 280, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 280, "RAZ", 1, 1, 0, 0},
|
|
{"TFL" , 0, 7, 281, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 281, "RAZ", 1, 1, 0, 0},
|
|
{"TFR" , 0, 8, 282, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 282, "RAZ", 1, 1, 0, 0},
|
|
{"THR" , 0, 8, 283, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 283, "RAZ", 1, 1, 0, 0},
|
|
{"BUSY" , 0, 1, 284, "RO", 0, 1, 0ull, 0},
|
|
{"TFNF" , 1, 1, 284, "RO", 0, 1, 1ull, 0},
|
|
{"TFE" , 2, 1, 284, "RO", 0, 1, 1ull, 0},
|
|
{"RFNE" , 3, 1, 284, "RO", 0, 1, 0ull, 0},
|
|
{"RFF" , 4, 1, 284, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 284, "RAZ", 1, 1, 0, 0},
|
|
{"ENABLE" , 0, 1, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDLELO" , 1, 1, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLK_CONT" , 2, 1, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WIREOR" , 3, 1, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LSBFIRST" , 4, 1, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_ENA" , 5, 1, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CSENA" , 6, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CSHI" , 7, 1, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDLECLKS" , 8, 2, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRITX" , 10, 1, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_15" , 11, 5, 285, "RAZ", 1, 1, 0, 0},
|
|
{"CLKDIV" , 16, 13, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 285, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 8, 286, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_8_63" , 8, 56, 286, "RAZ", 1, 1, 0, 0},
|
|
{"BUSY" , 0, 1, 287, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_7" , 1, 7, 287, "RAZ", 1, 1, 0, 0},
|
|
{"RXNUM" , 8, 5, 287, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 287, "RAZ", 1, 1, 0, 0},
|
|
{"TOTNUM" , 0, 5, 288, "WO", 1, 0, 0, 2ull},
|
|
{"RESERVED_5_7" , 5, 3, 288, "RAZ", 1, 1, 0, 0},
|
|
{"TXNUM" , 8, 5, 288, "WO", 1, 0, 0, 1ull},
|
|
{"RESERVED_13_15" , 13, 3, 288, "RAZ", 1, 1, 0, 0},
|
|
{"LEAVECS" , 16, 1, 288, "WO", 1, 0, 0, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 288, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 289, "RAZ", 1, 1, 0, 0},
|
|
{"BADDR" , 3, 61, 289, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_0_2" , 0, 3, 290, "RAZ", 1, 1, 0, 0},
|
|
{"BADDR" , 3, 61, 290, "R/W", 0, 1, 0ull, 0},
|
|
{"DPI_BS" , 0, 1, 291, "RO", 0, 0, 0ull, 0ull},
|
|
{"PDF_BS" , 1, 1, 291, "RO", 0, 0, 0ull, 0ull},
|
|
{"DOB_BS" , 2, 1, 291, "RO", 0, 0, 0ull, 0ull},
|
|
{"NUS_BS" , 3, 1, 291, "RO", 0, 0, 0ull, 0ull},
|
|
{"POS_BS" , 4, 1, 291, "RO", 0, 0, 0ull, 0ull},
|
|
{"POF3_BS" , 5, 1, 291, "RO", 0, 0, 0ull, 0ull},
|
|
{"POF2_BS" , 6, 1, 291, "RO", 0, 0, 0ull, 0ull},
|
|
{"POF1_BS" , 7, 1, 291, "RO", 0, 0, 0ull, 0ull},
|
|
{"POF0_BS" , 8, 1, 291, "RO", 0, 0, 0ull, 0ull},
|
|
{"PIG_BS" , 9, 1, 291, "RO", 0, 0, 0ull, 0ull},
|
|
{"PGF_BS" , 10, 1, 291, "RO", 0, 0, 0ull, 0ull},
|
|
{"RDNL_BS" , 11, 1, 291, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCAD_BS" , 12, 1, 291, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCAC_BS" , 13, 1, 291, "RO", 0, 0, 0ull, 0ull},
|
|
{"RDN_BS" , 14, 1, 291, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCN_BS" , 15, 1, 291, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCNC_BS" , 16, 1, 291, "RO", 0, 0, 0ull, 0ull},
|
|
{"RDP_BS" , 17, 1, 291, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF_BS" , 18, 1, 291, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSR_BS" , 19, 1, 291, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 291, "RAZ", 1, 1, 0, 0},
|
|
{"BSIZE" , 0, 16, 292, "R/W", 0, 1, 1024ull, 0},
|
|
{"ISIZE" , 16, 7, 292, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_23_63" , 23, 41, 292, "RAZ", 1, 1, 0, 0},
|
|
{"TIMER" , 0, 10, 293, "R/W", 0, 0, 0ull, 50ull},
|
|
{"RESERVED_10_31" , 10, 22, 293, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX_WORD" , 32, 5, 293, "R/W", 0, 0, 2ull, 0ull},
|
|
{"RESERVED_37_39" , 37, 3, 293, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WAIT_COM" , 40, 1, 293, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCI_WDIS" , 41, 1, 293, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INS0_64B" , 42, 1, 293, "R/W", 0, 1, 0ull, 0},
|
|
{"INS1_64B" , 43, 1, 293, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_45" , 44, 2, 293, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"INS0_ENB" , 46, 1, 293, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INS1_ENB" , 47, 1, 293, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_48_49" , 48, 2, 293, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OUT0_ENB" , 50, 1, 293, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OUT1_ENB" , 51, 1, 293, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_52_53" , 52, 2, 293, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DIS_PNIW" , 54, 1, 293, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CHIP_REV" , 55, 8, 293, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_63_63" , 63, 1, 293, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_SEL" , 0, 16, 294, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 294, "RAZ", 1, 1, 0, 0},
|
|
{"CSIZE" , 0, 14, 295, "R/W", 0, 1, 0ull, 0},
|
|
{"LP_ENB" , 14, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"HP_ENB" , 15, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O_MODE" , 16, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O_ES" , 17, 2, 295, "R/W", 0, 1, 0ull, 0},
|
|
{"O_NS" , 19, 1, 295, "R/W", 0, 1, 0ull, 0},
|
|
{"O_RO" , 20, 1, 295, "R/W", 0, 1, 0ull, 0},
|
|
{"O_ADD1" , 21, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA_QUE" , 22, 3, 295, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB_ICHK" , 25, 9, 295, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB_DENB" , 34, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"B0_LEND" , 35, 1, 295, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 295, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 32, 296, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 7, 296, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_39_63" , 39, 25, 296, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 297, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 36, 4, 297, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 297, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 32, 298, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 7, 298, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_39_63" , 39, 25, 298, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 299, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 36, 4, 299, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 299, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 16, 300, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 300, "RAZ", 1, 1, 0, 0},
|
|
{"SADDR" , 0, 36, 301, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 301, "RAZ", 1, 1, 0, 0},
|
|
{"ROR" , 0, 1, 302, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR" , 1, 2, 302, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR" , 3, 1, 302, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_CSR" , 4, 1, 302, "R/W", 0, 0, 0ull, 1ull},
|
|
{"D_ROR" , 5, 1, 302, "R/W", 0, 1, 0ull, 0},
|
|
{"D_ESR" , 6, 2, 302, "R/W", 0, 1, 0ull, 0},
|
|
{"D_NSR" , 8, 1, 302, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP_DHI" , 9, 13, 302, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_22_63" , 22, 42, 302, "RAZ", 1, 1, 0, 0},
|
|
{"RML_RTO" , 0, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RML_WTO" , 1, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCI_RSL" , 2, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PO0_2SML" , 3, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PO1_2SML" , 4, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_5_6" , 5, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"I0_RTOUT" , 7, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I1_RTOUT" , 8, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_9_10" , 9, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"I0_OVERF" , 11, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I1_OVERF" , 12, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_13_14" , 13, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"P0_RTOUT" , 15, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_RTOUT" , 16, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_17_18" , 17, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"P0_PERR" , 19, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_PERR" , 20, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_21_22" , 21, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"G0_RTOUT" , 23, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"G1_RTOUT" , 24, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_25_26" , 25, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"P0_PPERR" , 27, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_PPERR" , 28, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_29_30" , 29, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"P0_PTOUT" , 31, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_PTOUT" , 32, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_33_34" , 33, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"I0_PPERR" , 35, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I1_PPERR" , 36, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_37_38" , 37, 2, 303, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"WIN_RTO" , 39, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P_DPERR" , 40, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 41, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FCR_S_E" , 42, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FCR_A_F" , 43, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCR_S_E" , 44, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCR_A_F" , 45, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q2_S_E" , 46, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q2_A_F" , 47, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q3_S_E" , 48, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q3_A_F" , 49, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"COM_S_E" , 50, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"COM_A_F" , 51, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PNC_S_E" , 52, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PNC_A_F" , 53, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RWX_S_E" , 54, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RDX_S_E" , 55, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCF_P_E" , 56, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCF_P_F" , 57, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PDF_P_E" , 58, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PDF_P_F" , 59, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q1_S_E" , 60, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q1_A_F" , 61, 1, 303, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_62_63" , 62, 2, 303, "RAZ", 1, 1, 0, 0},
|
|
{"RML_RTO" , 0, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RML_WTO" , 1, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCI_RSL" , 2, 1, 304, "RO", 0, 0, 0ull, 0ull},
|
|
{"PO0_2SML" , 3, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PO1_2SML" , 4, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_6" , 5, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"I0_RTOUT" , 7, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I1_RTOUT" , 8, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_10" , 9, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"I0_OVERF" , 11, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I1_OVERF" , 12, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_14" , 13, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"P0_RTOUT" , 15, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_RTOUT" , 16, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_18" , 17, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"P0_PERR" , 19, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_PERR" , 20, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_22" , 21, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"G0_RTOUT" , 23, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"G1_RTOUT" , 24, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_26" , 25, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"P0_PPERR" , 27, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_PPERR" , 28, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_30" , 29, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"P0_PTOUT" , 31, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_PTOUT" , 32, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_33_34" , 33, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"I0_PPERR" , 35, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I1_PPERR" , 36, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_38" , 37, 2, 304, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WIN_RTO" , 39, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_DPERR" , 40, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IOBDMA" , 41, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCR_S_E" , 42, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCR_A_F" , 43, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCR_S_E" , 44, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCR_A_F" , 45, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_S_E" , 46, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_A_F" , 47, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_S_E" , 48, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_A_F" , 49, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COM_S_E" , 50, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COM_A_F" , 51, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PNC_S_E" , 52, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PNC_A_F" , 53, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RWX_S_E" , 54, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RDX_S_E" , 55, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCF_P_E" , 56, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCF_P_F" , 57, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PDF_P_E" , 58, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PDF_P_F" , 59, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_S_E" , 60, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_A_F" , 61, 1, 304, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_62_63" , 62, 2, 304, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 16, 305, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 305, "RAZ", 1, 1, 0, 0},
|
|
{"SADDR" , 0, 36, 306, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 306, "RAZ", 1, 1, 0, 0},
|
|
{"BA" , 0, 28, 307, "R/W", 0, 1, 0ull, 0},
|
|
{"ROW" , 28, 1, 307, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR" , 29, 1, 307, "R/W", 0, 1, 0ull, 0},
|
|
{"NSW" , 30, 1, 307, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR" , 31, 1, 307, "R/W", 0, 1, 0ull, 0},
|
|
{"ESW" , 32, 2, 307, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR" , 34, 2, 307, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 307, "RAZ", 1, 1, 0, 0},
|
|
{"INT_VEC" , 0, 64, 308, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 0, 32, 309, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 309, "RAZ", 1, 1, 0, 0},
|
|
{"ROR_SL0" , 0, 1, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR_SL0" , 1, 1, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR_SL0" , 2, 2, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR_SL1" , 4, 1, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR_SL1" , 5, 1, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR_SL1" , 6, 2, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_15" , 8, 8, 310, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IPTR_O0" , 16, 1, 310, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IPTR_O1" , 17, 1, 310, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_18_23" , 18, 6, 310, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"O0_CSRM" , 24, 1, 310, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O1_CSRM" , 25, 1, 310, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_26_27" , 26, 2, 310, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"O0_RO" , 28, 1, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"O0_NS" , 29, 1, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"O0_ES" , 30, 2, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"O1_RO" , 32, 1, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"O1_NS" , 33, 1, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"O1_ES" , 34, 2, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_43" , 36, 8, 310, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"P0_BMODE" , 44, 1, 310, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P1_BMODE" , 45, 1, 310, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_46_63" , 46, 18, 310, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"NADDR" , 0, 61, 311, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 61, 2, 311, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_63_63" , 63, 1, 311, "RAZ", 1, 1, 0, 0},
|
|
{"NADDR" , 0, 61, 312, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 61, 3, 312, "RO", 0, 0, 0ull, 0ull},
|
|
{"AVAIL" , 0, 32, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 6, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 313, "RAZ", 1, 1, 0, 0},
|
|
{"AVAIL" , 0, 32, 314, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 5, 314, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 314, "RAZ", 1, 1, 0, 0},
|
|
{"RD_BRST" , 0, 7, 315, "R/W", 0, 0, 17ull, 64ull},
|
|
{"WR_BRST" , 7, 7, 315, "R/W", 0, 0, 16ull, 64ull},
|
|
{"RESERVED_14_63" , 14, 50, 315, "RAZ", 1, 1, 0, 0},
|
|
{"PARK_DEV" , 0, 3, 316, "R/W", 0, 1, 0ull, 0},
|
|
{"PARK_MOD" , 3, 1, 316, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 4, 1, 316, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 316, "RAZ", 1, 1, 0, 0},
|
|
{"CMD_SIZE" , 0, 11, 317, "R/W", 0, 0, 9ull, 9ull},
|
|
{"RESERVED_11_63" , 11, 53, 317, "RAZ", 1, 1, 0, 0},
|
|
{"RSV_A" , 0, 6, 318, "R/W", 0, 1, 0ull, 0},
|
|
{"SKP_LEN" , 6, 7, 318, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_B" , 13, 1, 318, "R/W", 0, 1, 0ull, 0},
|
|
{"PAR_MODE" , 14, 2, 318, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_C" , 16, 5, 318, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_IHDR" , 21, 1, 318, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_D" , 22, 6, 318, "R/W", 0, 1, 0ull, 0},
|
|
{"RSKP_LEN" , 28, 7, 318, "R/W", 0, 1, 8ull, 0},
|
|
{"RSV_E" , 35, 1, 318, "R/W", 0, 1, 0ull, 0},
|
|
{"RPARMODE" , 36, 2, 318, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_F" , 38, 5, 318, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP" , 43, 1, 318, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 318, "RAZ", 1, 1, 0, 0},
|
|
{"RSV_A" , 0, 6, 319, "R/W", 0, 1, 0ull, 0},
|
|
{"SKP_LEN" , 6, 7, 319, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_B" , 13, 1, 319, "R/W", 0, 1, 0ull, 0},
|
|
{"PAR_MODE" , 14, 2, 319, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_C" , 16, 5, 319, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_IHDR" , 21, 1, 319, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_D" , 22, 6, 319, "R/W", 0, 1, 0ull, 0},
|
|
{"RSKP_LEN" , 28, 7, 319, "R/W", 0, 1, 8ull, 0},
|
|
{"RSV_E" , 35, 1, 319, "R/W", 0, 1, 0ull, 0},
|
|
{"RPARMODE" , 36, 2, 319, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_F" , 38, 5, 319, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP" , 43, 1, 319, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 319, "RAZ", 1, 1, 0, 0},
|
|
{"ENB" , 0, 4, 320, "R/W", 0, 0, 15ull, 15ull},
|
|
{"BP_ON" , 4, 4, 320, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 320, "RAZ", 1, 1, 0, 0},
|
|
{"MIO" , 0, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX0" , 1, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX1" , 2, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPI" , 3, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"KEY" , 4, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPA" , 5, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"DFA" , 6, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"ZIP" , 7, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_8" , 8, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD" , 9, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 10, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"TIM" , 11, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"POW" , 12, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"USB" , 13, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_14" , 14, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_15" , 15, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"L2C" , 16, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"LMC" , 17, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"SPX0" , 18, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"SPX1" , 19, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"PIP" , 20, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_21" , 21, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASX0" , 22, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASX1" , 23, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_24" , 24, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_25" , 25, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_26" , 26, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_27" , 27, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_28" , 28, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_29" , 29, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"IOB" , 30, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_31" , 31, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 321, "RAZ", 1, 1, 0, 0},
|
|
{"SIZE" , 0, 32, 322, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 322, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 32, 323, "R/W", 0, 0, 0ull, 131072ull},
|
|
{"RESERVED_32_63" , 32, 32, 323, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR_V" , 0, 1, 324, "R/W", 0, 1, 0ull, 0},
|
|
{"END_SWP" , 1, 2, 324, "R/W", 0, 1, 0ull, 0},
|
|
{"CA" , 3, 1, 324, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDR_IDX" , 4, 14, 324, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_31" , 18, 14, 324, "RAZ", 1, 1, 0, 0},
|
|
{"VENDID" , 0, 16, 325, "RO", 0, 0, 6013ull, 6013ull},
|
|
{"DEVID" , 16, 16, 325, "RO", 0, 0, 32ull, 32ull},
|
|
{"ISAE" , 0, 1, 326, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSAE" , 1, 1, 326, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ME" , 2, 1, 326, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SCSE" , 3, 1, 326, "RO", 0, 0, 0ull, 0ull},
|
|
{"MWICE" , 4, 1, 326, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VPS" , 5, 1, 326, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEE" , 6, 1, 326, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ADS" , 7, 1, 326, "RO", 0, 0, 0ull, 0ull},
|
|
{"SEE" , 8, 1, 326, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FBBE" , 9, 1, 326, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I_DIS" , 10, 1, 326, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_18" , 11, 8, 326, "RAZ", 1, 1, 0, 0},
|
|
{"I_STAT" , 19, 1, 326, "RO", 0, 0, 0ull, 0ull},
|
|
{"CLE" , 20, 1, 326, "RO", 0, 0, 1ull, 1ull},
|
|
{"M66" , 21, 1, 326, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_22_22" , 22, 1, 326, "RAZ", 1, 1, 0, 0},
|
|
{"FBB" , 23, 1, 326, "RO", 0, 1, 1ull, 0},
|
|
{"MDPE" , 24, 1, 326, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DEVT" , 25, 2, 326, "RO", 0, 0, 1ull, 1ull},
|
|
{"STA" , 27, 1, 326, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTA" , 28, 1, 326, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RMA" , 29, 1, 326, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SSE" , 30, 1, 326, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPE" , 31, 1, 326, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RID" , 0, 8, 327, "RO", 0, 0, 0ull, 0ull},
|
|
{"CC" , 8, 24, 327, "RO", 0, 0, 1048576ull, 1048576ull},
|
|
{"CLS" , 0, 8, 328, "R/W", 0, 1, 0ull, 0},
|
|
{"LT" , 8, 8, 328, "R/W", 0, 0, 0ull, 64ull},
|
|
{"HT" , 16, 8, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCOD" , 24, 4, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_29" , 28, 2, 328, "RAZ", 1, 1, 0, 0},
|
|
{"BRB" , 30, 1, 328, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BCAP" , 31, 1, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSPC" , 0, 1, 329, "RO", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 329, "RO", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 329, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBASEZ" , 4, 8, 329, "RO", 0, 0, 0ull, 0ull},
|
|
{"LBASE" , 12, 20, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"HBASE" , 0, 32, 330, "R/W", 0, 1, 0ull, 0},
|
|
{"MSPC" , 0, 1, 331, "RO", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 331, "RO", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 331, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBASEZ" , 4, 23, 331, "RO", 0, 0, 0ull, 0ull},
|
|
{"LBASE" , 27, 5, 331, "R/W", 0, 1, 0ull, 0},
|
|
{"HBASE" , 0, 32, 332, "R/W", 0, 1, 0ull, 0},
|
|
{"MSPC" , 0, 1, 333, "RO", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 333, "RO", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 333, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBASEZ" , 4, 28, 333, "RO", 0, 0, 0ull, 0ull},
|
|
{"HBASEZ" , 0, 7, 334, "RO", 0, 0, 0ull, 0ull},
|
|
{"HBASE" , 7, 25, 334, "R/W", 0, 1, 0ull, 0},
|
|
{"CISP" , 0, 32, 335, "RO", 0, 0, 0ull, 0ull},
|
|
{"SSVID" , 0, 16, 336, "RO", 0, 0, 6013ull, 6013ull},
|
|
{"SSID" , 16, 16, 336, "RO", 0, 0, 1ull, 1ull},
|
|
{"ERBAR_EN" , 0, 1, 337, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_10" , 1, 10, 337, "RAZ", 1, 1, 0, 0},
|
|
{"ERBARZ" , 11, 5, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"ERBAR" , 16, 16, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"CP" , 0, 8, 338, "RO", 0, 0, 224ull, 224ull},
|
|
{"RESERVED_8_31" , 8, 24, 338, "RAZ", 1, 1, 0, 0},
|
|
{"IL" , 0, 8, 339, "R/W", 0, 1, 0ull, 0},
|
|
{"INTA" , 8, 8, 339, "RO", 0, 0, 1ull, 1ull},
|
|
{"MG" , 16, 8, 339, "RO", 0, 0, 64ull, 64ull},
|
|
{"ML" , 24, 8, 339, "RO", 0, 0, 64ull, 64ull},
|
|
{"MLTD" , 0, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TSWC" , 1, 1, 340, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 340, "RAZ", 1, 1, 0, 0},
|
|
{"DPPMR" , 3, 1, 340, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PBE" , 4, 12, 340, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TILT" , 16, 4, 340, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TSLTE" , 20, 3, 340, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TMAE" , 23, 1, 340, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWTAE" , 24, 1, 340, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWSEN" , 25, 1, 340, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWSEI" , 26, 1, 340, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRTAE" , 27, 1, 340, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRDRS" , 28, 1, 340, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RDSATI" , 29, 1, 340, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRDARD" , 30, 1, 340, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TRDNPR" , 31, 1, 340, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TSCME" , 0, 32, 341, "R/W1C", 0, 1, 0ull, 0},
|
|
{"TDSRPS" , 0, 32, 342, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TDOMC" , 0, 5, 343, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TIDOMC" , 5, 1, 343, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_6" , 6, 1, 343, "RAZ", 1, 1, 0, 0},
|
|
{"TIBDE" , 7, 1, 343, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIBCD" , 8, 1, 343, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_10" , 9, 2, 343, "RAZ", 1, 1, 0, 0},
|
|
{"TMAPES" , 11, 1, 343, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TMDPES" , 12, 1, 343, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TMSE" , 13, 1, 343, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TMEI" , 14, 1, 343, "RO", 0, 0, 0ull, 0ull},
|
|
{"TECI" , 15, 1, 343, "RO", 0, 0, 0ull, 0ull},
|
|
{"TMES" , 16, 8, 343, "RO", 0, 0, 0ull, 0ull},
|
|
{"MDRRMC" , 24, 3, 343, "R/W", 0, 0, 2ull, 2ull},
|
|
{"MDRIMC" , 27, 1, 343, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MDRE" , 28, 1, 343, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MDWE" , 29, 1, 343, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRBCI" , 30, 1, 343, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRBCM" , 31, 1, 343, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MDSP" , 0, 32, 344, "R/W1C", 0, 1, 0ull, 0},
|
|
{"SCMRE" , 0, 32, 345, "R/W1C", 0, 1, 0ull, 0},
|
|
{"MTTV" , 0, 8, 346, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRV" , 8, 8, 346, "R/W", 0, 0, 0ull, 255ull},
|
|
{"MTTA" , 16, 1, 346, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRA" , 17, 1, 346, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FLUSH" , 18, 1, 346, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_19_24" , 19, 6, 346, "RAZ", 1, 1, 0, 0},
|
|
{"MAC" , 25, 7, 346, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PXCID" , 0, 8, 347, "RO", 0, 0, 7ull, 7ull},
|
|
{"NCP" , 8, 8, 347, "RO", 0, 0, 232ull, 232ull},
|
|
{"DPERE" , 16, 1, 347, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROE" , 17, 1, 347, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MMBC" , 18, 2, 347, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MOST" , 20, 3, 347, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_23_31" , 23, 9, 347, "RAZ", 1, 1, 0, 0},
|
|
{"FN" , 0, 3, 348, "RO", 0, 0, 0ull, 0ull},
|
|
{"DN" , 3, 5, 348, "RO", 0, 0, 31ull, 31ull},
|
|
{"BN" , 8, 8, 348, "RO", 0, 1, 17ull, 0},
|
|
{"W64" , 16, 1, 348, "RO", 0, 0, 1ull, 1ull},
|
|
{"M133" , 17, 1, 348, "RO", 0, 0, 1ull, 1ull},
|
|
{"SCD" , 18, 1, 348, "R/W1C", 0, 1, 0ull, 0},
|
|
{"USC" , 19, 1, 348, "R/W1C", 0, 1, 0ull, 0},
|
|
{"DC" , 20, 1, 348, "RO", 0, 0, 0ull, 0ull},
|
|
{"MMRBCD" , 21, 2, 348, "RO", 0, 0, 2ull, 2ull},
|
|
{"MOSTD" , 23, 3, 348, "RO", 0, 0, 3ull, 3ull},
|
|
{"MCRSD" , 26, 3, 348, "RO", 0, 0, 7ull, 7ull},
|
|
{"SCEMR" , 29, 1, 348, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_30_31" , 30, 2, 348, "RAZ", 1, 1, 0, 0},
|
|
{"PMCID" , 0, 8, 349, "RO", 0, 0, 1ull, 1ull},
|
|
{"NCP" , 8, 8, 349, "RO", 0, 0, 240ull, 240ull},
|
|
{"PCIMIV" , 16, 3, 349, "RO", 0, 0, 2ull, 2ull},
|
|
{"PMEC" , 19, 1, 349, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 349, "RAZ", 1, 1, 0, 0},
|
|
{"DSI" , 21, 1, 349, "RO", 0, 0, 0ull, 0ull},
|
|
{"AUXC" , 22, 3, 349, "RO", 0, 0, 0ull, 0ull},
|
|
{"D1S" , 25, 1, 349, "RO", 0, 0, 0ull, 0ull},
|
|
{"D2S" , 26, 1, 349, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMES" , 27, 5, 349, "RO", 0, 0, 0ull, 0ull},
|
|
{"PS" , 0, 2, 350, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_7" , 2, 6, 350, "RAZ", 1, 1, 0, 0},
|
|
{"PMEENS" , 8, 1, 350, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMDS" , 9, 4, 350, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMEDSIA" , 13, 2, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMESS" , 15, 1, 350, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_21" , 16, 6, 350, "RAZ", 1, 1, 0, 0},
|
|
{"BD3H" , 22, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"BPCCEN" , 23, 1, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMDIA" , 24, 8, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSICID" , 0, 8, 351, "RO", 0, 0, 5ull, 5ull},
|
|
{"NCP" , 8, 8, 351, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSIEN" , 16, 1, 351, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MMC" , 17, 3, 351, "RO", 0, 0, 0ull, 0ull},
|
|
{"MME" , 20, 3, 351, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M64" , 23, 1, 351, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_24_31" , 24, 8, 351, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 352, "RAZ", 1, 1, 0, 0},
|
|
{"MSI31T2" , 2, 30, 352, "R/W", 0, 1, 0ull, 0},
|
|
{"MSI" , 0, 32, 353, "R/W", 0, 1, 0ull, 0},
|
|
{"MSIMD" , 0, 16, 354, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_31" , 16, 16, 354, "RAZ", 1, 1, 0, 0},
|
|
{"BAR2_CAX" , 0, 1, 355, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAR2_ESX" , 1, 2, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"BAR2_ENB" , 3, 1, 355, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TSR_HWM" , 4, 3, 355, "R/W", 0, 1, 1ull, 0},
|
|
{"PMO_FPC" , 7, 3, 355, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMO_AMOD" , 10, 1, 355, "R/W", 0, 0, 0ull, 0ull},
|
|
{"B12_BIST" , 11, 1, 355, "RO", 0, 0, 0ull, 0ull},
|
|
{"AP_64AD" , 12, 1, 355, "RO", 0, 1, 0ull, 0},
|
|
{"AP_PCIX" , 13, 1, 355, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_14" , 14, 1, 355, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EN_WFILT" , 15, 1, 355, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SCM" , 16, 1, 355, "RO", 0, 1, 0ull, 0},
|
|
{"SCMTYP" , 17, 1, 355, "RO", 0, 1, 0ull, 0},
|
|
{"BAR2PRES" , 18, 1, 355, "R/W", 1, 1, 0, 0},
|
|
{"ERST_N" , 19, 1, 355, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_20_31" , 20, 12, 355, "RAZ", 1, 1, 0, 0},
|
|
{"INC_VAL" , 0, 16, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_31" , 16, 16, 356, "RAZ", 1, 1, 0, 0},
|
|
{"DMA_CNT" , 0, 32, 357, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKT_CNT" , 0, 32, 358, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA_TIME" , 0, 32, 359, "R/W", 0, 1, 0ull, 0},
|
|
{"ICNT" , 0, 32, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"ITR_WABT" , 0, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_WABT" , 1, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_WTTO" , 2, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"ITR_ABT" , 3, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_ABT" , 4, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_TTO" , 5, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSI_PER" , 6, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSI_TABT" , 7, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSI_MABT" , 8, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSC_MSG" , 9, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"ITSR_ABT" , 10, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"ISERR" , 11, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"IAPERR" , 12, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"IDPERR" , 13, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RWR" , 14, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RRD" , 15, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"IRSL_INT" , 16, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"IPCNT0" , 17, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"IPCNT1" , 18, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_19_20" , 19, 2, 361, "RAZ", 0, 1, 0ull, 0},
|
|
{"IPTIME0" , 21, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"IPTIME1" , 22, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_23_24" , 23, 2, 361, "RAZ", 0, 1, 0ull, 0},
|
|
{"IDCNT0" , 25, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"IDCNT1" , 26, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"IDTIME0" , 27, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"IDTIME1" , 28, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA0_FI" , 29, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA1_FI" , 30, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"WIN_WR" , 31, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_WR" , 32, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RD" , 33, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_34_63" , 34, 30, 361, "RAZ", 1, 1, 0, 0},
|
|
{"RTR_WABT" , 0, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_WABT" , 1, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_WTTO" , 2, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RTR_ABT" , 3, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_ABT" , 4, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_TTO" , 5, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSI_PER" , 6, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSI_TABT" , 7, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSI_MABT" , 8, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSC_MSG" , 9, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RTSR_ABT" , 10, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RSERR" , 11, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RAPERR" , 12, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RDPERR" , 13, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RWR" , 14, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RRD" , 15, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RRSL_INT" , 16, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RPCNT0" , 17, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RPCNT1" , 18, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_19_20" , 19, 2, 362, "RAZ", 0, 1, 0ull, 0},
|
|
{"RPTIME0" , 21, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RPTIME1" , 22, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_23_24" , 23, 2, 362, "RAZ", 0, 1, 0ull, 0},
|
|
{"RDCNT0" , 25, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RDCNT1" , 26, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RDTIME0" , 27, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RDTIME1" , 28, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA0_FI" , 29, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA1_FI" , 30, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"WIN_WR" , 31, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_WR" , 32, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RD" , 33, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_34_63" , 34, 30, 362, "RAZ", 1, 1, 0, 0},
|
|
{"TR_WABT" , 0, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WABT" , 1, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WTTO" , 2, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TR_ABT" , 3, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_ABT" , 4, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_TTO" , 5, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_PER" , 6, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_TABT" , 7, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_MABT" , 8, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSC_MSG" , 9, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TSR_ABT" , 10, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SERR" , 11, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"APERR" , 12, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPERR" , 13, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RWR" , 14, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RRD" , 15, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSL_INT" , 16, 1, 363, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCNT0" , 17, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT1" , 18, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_20" , 19, 2, 363, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PTIME0" , 21, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME1" , 22, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_24" , 23, 2, 363, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DCNT0" , 25, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT1" , 26, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME0" , 27, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME1" , 28, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA0_FI" , 29, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1_FI" , 30, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WIN_WR" , 31, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_WR" , 32, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RD" , 33, 1, 363, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 363, "RAZ", 1, 1, 0, 0},
|
|
{"TR_WABT" , 0, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WABT" , 1, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WTTO" , 2, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TR_ABT" , 3, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_ABT" , 4, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_TTO" , 5, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_PER" , 6, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_TABT" , 7, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_MABT" , 8, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSC_MSG" , 9, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TSR_ABT" , 10, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SERR" , 11, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"APERR" , 12, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPERR" , 13, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RWR" , 14, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RRD" , 15, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSL_INT" , 16, 1, 364, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCNT0" , 17, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT1" , 18, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_20" , 19, 2, 364, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PTIME0" , 21, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME1" , 22, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_24" , 23, 2, 364, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DCNT0" , 25, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT1" , 26, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME0" , 27, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME1" , 28, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA0_FI" , 29, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1_FI" , 30, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WIN_WR" , 31, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_WR" , 32, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RD" , 33, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 364, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 0, 6, 365, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_31" , 6, 26, 365, "R/W", 1, 1, 0, 0},
|
|
{"PTR_CNT" , 0, 16, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_CNT" , 16, 16, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_CNT" , 0, 32, 367, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_CNT" , 0, 32, 368, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_TIME" , 0, 32, 369, "R/W", 0, 1, 0ull, 0},
|
|
{"PREFETCH" , 0, 3, 370, "R/W", 0, 0, 0ull, 2ull},
|
|
{"MIN_DATA" , 3, 6, 370, "R/W", 0, 0, 0ull, 4ull},
|
|
{"RESERVED_9_31" , 9, 23, 370, "RAZ", 1, 1, 0, 0},
|
|
{"PREFETCH" , 0, 3, 371, "R/W", 0, 0, 0ull, 3ull},
|
|
{"MIN_DATA" , 3, 6, 371, "R/W", 0, 0, 0ull, 6ull},
|
|
{"RESERVED_9_31" , 9, 23, 371, "RAZ", 1, 1, 0, 0},
|
|
{"PREFETCH" , 0, 3, 372, "R/W", 0, 0, 0ull, 3ull},
|
|
{"MIN_DATA" , 3, 6, 372, "R/W", 0, 0, 0ull, 6ull},
|
|
{"RESERVED_9_31" , 9, 23, 372, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 31, 373, "R/W", 0, 0, 10000ull, 10000ull},
|
|
{"ENB" , 31, 1, 373, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_32_63" , 32, 32, 373, "RAZ", 1, 1, 0, 0},
|
|
{"SCM" , 0, 32, 374, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 374, "RAZ", 1, 1, 0, 0},
|
|
{"TSR" , 0, 36, 375, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 375, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 376, "RAZ", 1, 1, 0, 0},
|
|
{"RD_ADDR" , 2, 46, 376, "R/W", 0, 1, 0ull, 0},
|
|
{"IOBIT" , 48, 1, 376, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 376, "RAZ", 1, 1, 0, 0},
|
|
{"RD_DATA" , 0, 64, 377, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_0_2" , 0, 3, 378, "RAZ", 1, 1, 0, 0},
|
|
{"WR_ADDR" , 3, 45, 378, "R/W", 0, 1, 0ull, 0},
|
|
{"IOBIT" , 48, 1, 378, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 378, "RAZ", 1, 1, 0, 0},
|
|
{"WR_DATA" , 0, 64, 379, "R/W", 0, 1, 0ull, 0},
|
|
{"WR_MASK" , 0, 8, 380, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 380, "RAZ", 1, 1, 0, 0},
|
|
{"THRESH" , 0, 4, 381, "R/W", 0, 0, 0ull, 8ull},
|
|
{"FETCHSIZ" , 4, 4, 381, "R/W", 0, 0, 0ull, 7ull},
|
|
{"TXRD" , 8, 10, 381, "R/W", 0, 0, 0ull, 1ull},
|
|
{"USELDT" , 18, 1, 381, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_19" , 19, 1, 381, "RAZ", 1, 1, 0, 0},
|
|
{"RXST" , 20, 10, 381, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_30_31" , 30, 2, 381, "RAZ", 1, 1, 0, 0},
|
|
{"TXSLOTS" , 32, 10, 381, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_42_43" , 42, 2, 381, "RAZ", 1, 1, 0, 0},
|
|
{"RXSLOTS" , 44, 10, 381, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_54_62" , 54, 9, 381, "RAZ", 1, 1, 0, 0},
|
|
{"RDPEND" , 63, 1, 381, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYNCMISSED" , 0, 1, 382, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FSYNCEXTRA" , 1, 1, 382, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXWRAP" , 2, 1, 382, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXST" , 3, 1, 382, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXWRAP" , 4, 1, 382, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXRD" , 5, 1, 382, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXEMPTY" , 6, 1, 382, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXOVF" , 7, 1, 382, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_8_63" , 8, 56, 382, "RAZ", 1, 1, 0, 0},
|
|
{"FSYNCMISSED" , 0, 1, 383, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FSYNCEXTRA" , 1, 1, 383, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXWRAP" , 2, 1, 383, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXST" , 3, 1, 383, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXWRAP" , 4, 1, 383, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXRD" , 5, 1, 383, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXEMPTY" , 6, 1, 383, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXOVF" , 7, 1, 383, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 383, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 384, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_36_63" , 36, 28, 384, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 385, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_16_63" , 16, 48, 385, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 386, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 387, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 388, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 389, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 390, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 391, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 392, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 393, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 394, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 3, 33, 394, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_36_63" , 36, 28, 394, "RAZ", 1, 1, 0, 0},
|
|
{"ENABLE" , 0, 1, 395, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USECLK1" , 1, 1, 395, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LSBFIRST" , 2, 1, 395, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_31" , 3, 29, 395, "RAZ", 1, 1, 0, 0},
|
|
{"SAMPPT" , 32, 16, 395, "R/W", 0, 1, 0ull, 0},
|
|
{"DRVTIM" , 48, 16, 395, "R/W", 0, 1, 0ull, 0},
|
|
{"DEBUGINFO" , 0, 64, 396, "RO", 1, 1, 0, 0},
|
|
{"FRAM" , 0, 3, 397, "R/W", 1, 1, 0, 0},
|
|
{"ADDR" , 3, 33, 397, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_36_63" , 36, 28, 397, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 398, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_16_63" , 16, 48, 398, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 399, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 400, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 401, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 402, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 403, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 404, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 405, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 406, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 407, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 3, 33, 407, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_36_63" , 36, 28, 407, "RAZ", 1, 1, 0, 0},
|
|
{"ENA" , 0, 1, 408, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSYNCPOL" , 1, 1, 408, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BCLKPOL" , 2, 1, 408, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BITLEN" , 3, 2, 408, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EXTRABIT" , 5, 1, 408, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NUMSLOTS" , 6, 10, 408, "R/W", 0, 1, 0ull, 0},
|
|
{"FSYNCLOC" , 16, 5, 408, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSYNCLEN" , 21, 5, 408, "R/W", 0, 0, 0ull, 2ull},
|
|
{"RESERVED_26_31" , 26, 6, 408, "RAZ", 1, 1, 0, 0},
|
|
{"FSYNCSAMP" , 32, 16, 408, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_62" , 48, 15, 408, "RAZ", 1, 1, 0, 0},
|
|
{"FSYNCGOOD" , 63, 1, 408, "RO", 0, 0, 0ull, 1ull},
|
|
{"DEBUGINFO" , 0, 64, 409, "RO", 1, 1, 0, 0},
|
|
{"N" , 0, 32, 410, "R/W", 0, 1, 0ull, 0},
|
|
{"NUMSAMP" , 32, 16, 410, "R/W", 0, 1, 0ull, 0},
|
|
{"DELTASAMP" , 48, 16, 410, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BIST" , 0, 18, 411, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 411, "RAZ", 1, 1, 0, 0},
|
|
{"DPRT" , 0, 16, 412, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UDP" , 16, 1, 412, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP" , 17, 1, 412, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 412, "RAZ", 1, 1, 0, 0},
|
|
{"NIP_SHF" , 0, 3, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_7" , 3, 5, 413, "RAZ", 1, 1, 0, 0},
|
|
{"RAW_SHF" , 8, 3, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_15" , 11, 5, 413, "RAZ", 1, 1, 0, 0},
|
|
{"MAX_L2" , 16, 1, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_UDP" , 17, 1, 413, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TAG_SYN" , 18, 1, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 413, "RAZ", 1, 1, 0, 0},
|
|
{"IP_CHK" , 0, 1, 414, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP_MAL" , 1, 1, 414, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP_HOP" , 2, 1, 414, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP4_OPTS" , 3, 1, 414, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP6_EEXT" , 4, 2, 414, "R/W", 0, 0, 1ull, 3ull},
|
|
{"RESERVED_6_7" , 6, 2, 414, "RAZ", 0, 1, 0ull, 0},
|
|
{"L4_MAL" , 8, 1, 414, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_PRT" , 9, 1, 414, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_CHK" , 10, 1, 414, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_LEN" , 11, 1, 414, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TCP_FLAG" , 12, 1, 414, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L2_MAL" , 13, 1, 414, "R/W", 0, 0, 1ull, 1ull},
|
|
{"VS_QOS" , 14, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VS_WQE" , 15, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IGNRS" , 16, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 414, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PKTDRP" , 0, 1, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CRCERR" , 1, 1, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BCKPRS" , 2, 1, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 3, 1, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BADTAG" , 4, 1, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPRUNT" , 5, 1, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TODOOVR" , 6, 1, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FEPERR" , 7, 1, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BEPERR" , 8, 1, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 415, "RAZ", 1, 1, 0, 0},
|
|
{"PKTDRP" , 0, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CRCERR" , 1, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BCKPRS" , 2, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 3, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BADTAG" , 4, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPRUNT" , 5, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TODOOVR" , 6, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FEPERR" , 7, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BEPERR" , 8, 1, 416, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 416, "RAZ", 1, 1, 0, 0},
|
|
{"OFFSET" , 0, 3, 417, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 417, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP" , 0, 7, 418, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 418, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 8, 2, 418, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_15" , 10, 6, 418, "RAZ", 1, 1, 0, 0},
|
|
{"QOS_VLAN" , 16, 1, 418, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS_DIFF" , 17, 1, 418, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_19" , 18, 2, 418, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"QOS_WAT" , 20, 4, 418, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS" , 24, 3, 418, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 418, "RAZ", 1, 1, 0, 0},
|
|
{"GRP_WAT" , 28, 4, 418, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INST_HDR" , 32, 1, 418, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DYN_RS" , 33, 1, 418, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TAG_INC" , 34, 2, 418, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RAWDRP" , 36, 1, 418, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 418, "RAZ", 1, 1, 0, 0},
|
|
{"GRP" , 0, 4, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NON_TAG_TYPE" , 4, 2, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_TAG_TYPE" , 6, 2, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_TAG_TYPE" , 8, 2, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP4_TAG_TYPE" , 10, 2, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP6_TAG_TYPE" , 12, 2, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_SRC_FLAG" , 14, 1, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_SRC_FLAG" , 15, 1, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_DST_FLAG" , 16, 1, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_DST_FLAG" , 17, 1, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_PCTL_FLAG" , 18, 1, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_NXTH_FLAG" , 19, 1, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_SPRT_FLAG" , 20, 1, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_SPRT_FLAG" , 21, 1, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_DPRT_FLAG" , 22, 1, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_DPRT_FLAG" , 23, 1, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_PRT_FLAG" , 24, 1, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_VLAN" , 25, 1, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_VS" , 26, 2, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TAG_MODE" , 28, 2, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_30" , 30, 1, 419, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"GRPTAG" , 31, 1, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAGMASK" , 32, 4, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAGBASE" , 36, 4, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 419, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 0, 3, 420, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 420, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 0, 3, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 421, "RAZ", 1, 1, 0, 0},
|
|
{"MATCH_VALUE" , 0, 16, 422, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MATCH_TYPE" , 16, 2, 422, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_19" , 18, 2, 422, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 20, 3, 422, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 422, "RAZ", 1, 1, 0, 0},
|
|
{"GRP" , 24, 4, 422, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_31" , 28, 4, 422, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 32, 16, 422, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 422, "RAZ", 1, 1, 0, 0},
|
|
{"WORD" , 0, 56, 423, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 423, "RAZ", 1, 1, 0, 0},
|
|
{"RST" , 0, 1, 424, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 424, "RAZ", 1, 1, 0, 0},
|
|
{"DRP_OCTS" , 0, 32, 425, "R/W", 0, 1, 0ull, 0},
|
|
{"DRP_PKTS" , 32, 32, 425, "R/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 426, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 426, "RAZ", 1, 1, 0, 0},
|
|
{"RAW" , 0, 32, 427, "R/W", 0, 1, 0ull, 0},
|
|
{"PKTS" , 32, 32, 427, "R/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 0, 32, 428, "R/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 32, 32, 428, "R/W", 0, 1, 0ull, 0},
|
|
{"H64" , 0, 32, 429, "R/W", 0, 1, 0ull, 0},
|
|
{"H65TO127" , 32, 32, 429, "R/W", 0, 1, 0ull, 0},
|
|
{"H128TO255" , 0, 32, 430, "R/W", 0, 1, 0ull, 0},
|
|
{"H256TO511" , 32, 32, 430, "R/W", 0, 1, 0ull, 0},
|
|
{"H512TO1023" , 0, 32, 431, "R/W", 0, 1, 0ull, 0},
|
|
{"H1024TO1518" , 32, 32, 431, "R/W", 0, 1, 0ull, 0},
|
|
{"H1519" , 0, 32, 432, "R/W", 0, 1, 0ull, 0},
|
|
{"FCS" , 32, 32, 432, "R/W", 0, 1, 0ull, 0},
|
|
{"UNDERSZ" , 0, 32, 433, "R/W", 0, 1, 0ull, 0},
|
|
{"FRAG" , 32, 32, 433, "R/W", 0, 1, 0ull, 0},
|
|
{"OVERSZ" , 0, 32, 434, "R/W", 0, 1, 0ull, 0},
|
|
{"JABBER" , 32, 32, 434, "R/W", 0, 1, 0ull, 0},
|
|
{"RDCLR" , 0, 1, 435, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 435, "RAZ", 1, 1, 0, 0},
|
|
{"ERRS" , 0, 16, 436, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 436, "RAZ", 1, 1, 0, 0},
|
|
{"OCTS" , 0, 48, 437, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 437, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 438, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 438, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 8, 439, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 439, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 0, 16, 440, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 440, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 16, 441, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DST" , 16, 16, 441, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 441, "RAZ", 1, 1, 0, 0},
|
|
{"ENTRY" , 0, 62, 442, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_62_62" , 62, 1, 442, "RAZ", 1, 1, 0, 0},
|
|
{"VAL" , 63, 1, 442, "RO", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 32, 443, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 443, "RAZ", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 48, 444, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 444, "RAZ", 1, 1, 0, 0},
|
|
{"SIZE" , 0, 16, 445, "RO", 1, 0, 0, 0ull},
|
|
{"SEGS" , 16, 6, 445, "RO", 1, 0, 0, 0ull},
|
|
{"CMD" , 22, 14, 445, "RO", 1, 0, 0, 0ull},
|
|
{"FAU" , 36, 28, 445, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 446, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 446, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 446, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 446, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 446, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 16, 447, "RO", 1, 0, 0, 0ull},
|
|
{"SEGS" , 16, 6, 447, "RO", 1, 0, 0, 0ull},
|
|
{"CMD" , 22, 14, 447, "RO", 1, 0, 0, 0ull},
|
|
{"FAU" , 36, 28, 447, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 448, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 448, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 448, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 448, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 448, "RO", 1, 0, 0, 0ull},
|
|
{"DATA" , 0, 64, 449, "RO", 1, 0, 0, 0ull},
|
|
{"WIDX2" , 0, 17, 450, "RO", 1, 0, 0, 0ull},
|
|
{"RIDX2" , 17, 17, 450, "RO", 1, 0, 0, 0ull},
|
|
{"WIDX" , 34, 17, 450, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_51_63" , 51, 13, 450, "RAZ", 1, 0, 0, 0ull},
|
|
{"RIDX" , 0, 17, 451, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 451, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 452, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 452, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 452, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 452, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 452, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 453, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 453, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 453, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 453, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 453, "RO", 1, 0, 0, 0ull},
|
|
{"DATA" , 0, 64, 454, "RO", 1, 0, 0, 0ull},
|
|
{"MAJOR" , 0, 4, 455, "RO", 1, 0, 0, 0ull},
|
|
{"MINOR" , 4, 2, 455, "RO", 1, 0, 0, 0ull},
|
|
{"WAIT" , 6, 1, 455, "RO", 1, 0, 0, 0ull},
|
|
{"QID_BASE" , 7, 7, 455, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFF" , 14, 3, 455, "RO", 1, 0, 0, 0ull},
|
|
{"QCB_RIDX" , 17, 5, 455, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 22, 3, 455, "RO", 1, 0, 0, 0ull},
|
|
{"ACTIVE" , 25, 1, 455, "RO", 1, 0, 0, 0ull},
|
|
{"CHK_MODE" , 26, 1, 455, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 455, "RAZ", 1, 0, 0, 0ull},
|
|
{"CBUF_FRE" , 28, 1, 455, "RO", 1, 0, 0, 0ull},
|
|
{"XFER_DWR" , 29, 1, 455, "RO", 1, 0, 0, 0ull},
|
|
{"XFER_WOR" , 30, 1, 455, "RO", 1, 0, 0, 0ull},
|
|
{"UID" , 31, 1, 455, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_SIZ" , 32, 16, 455, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_CNT" , 48, 13, 455, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_LEN" , 61, 1, 455, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_SOP" , 62, 1, 455, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_MOD" , 63, 1, 455, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_MOD" , 0, 2, 456, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_UID" , 2, 1, 456, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_CHK" , 3, 1, 456, "RO", 1, 0, 0, 0ull},
|
|
{"WORK_MIN" , 4, 3, 456, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 7, 1, 456, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFFM" , 8, 3, 456, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 456, "RAZ", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 16, 457, "RO", 1, 0, 0, 0ull},
|
|
{"START" , 16, 33, 457, "RO", 1, 0, 0, 0ull},
|
|
{"DWB" , 49, 9, 457, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_58_63" , 58, 6, 457, "RAZ", 1, 0, 0, 0ull},
|
|
{"QCB_RIDX" , 0, 6, 458, "RO", 1, 0, 0, 0ull},
|
|
{"QCB_WIDX" , 6, 6, 458, "RO", 1, 0, 0, 0ull},
|
|
{"BUF_PTR" , 12, 33, 458, "RO", 1, 0, 0, 0ull},
|
|
{"BUF_SIZ" , 45, 13, 458, "RO", 1, 0, 0, 0ull},
|
|
{"TAIL" , 58, 1, 458, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 59, 5, 458, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 0, 3, 459, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_Q" , 3, 1, 459, "RO", 1, 0, 0, 0ull},
|
|
{"S_TAIL" , 4, 1, 459, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_5_7" , 5, 3, 459, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 8, 20, 459, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 459, "RAZ", 1, 0, 0, 0ull},
|
|
{"QUEUE" , 0, 7, 460, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT" , 7, 6, 460, "WR0", 1, 0, 0, 0ull},
|
|
{"INDEX" , 13, 3, 460, "WR0", 1, 0, 0, 0ull},
|
|
{"TAIL" , 16, 1, 460, "R/W", 1, 0, 0, 0ull},
|
|
{"BUF_PTR" , 17, 36, 460, "R/W", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 460, "R/W", 1, 0, 0, 0ull},
|
|
{"STATIC_Q" , 61, 1, 460, "WR0", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 62, 1, 460, "WR0", 1, 0, 0, 0ull},
|
|
{"S_TAIL" , 63, 1, 460, "WR0", 1, 0, 0, 0ull},
|
|
{"QID" , 0, 7, 461, "R/W", 1, 0, 0, 0ull},
|
|
{"PID" , 7, 6, 461, "WR0", 1, 0, 0, 0ull},
|
|
{"RESERVED_13_52" , 13, 40, 461, "RAZ", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 461, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_61_63" , 61, 3, 461, "RAZ", 1, 0, 0, 0ull},
|
|
{"PSB" , 0, 7, 462, "RO", 1, 0, 0, 0ull},
|
|
{"PDB" , 7, 4, 462, "RO", 1, 0, 0, 0ull},
|
|
{"QCB" , 11, 2, 462, "RO", 1, 0, 0, 0ull},
|
|
{"QSB" , 13, 2, 462, "RO", 1, 0, 0, 0ull},
|
|
{"CHK" , 15, 1, 462, "RO", 1, 0, 0, 0ull},
|
|
{"CRC" , 16, 1, 462, "RO", 1, 0, 0, 0ull},
|
|
{"OUT" , 17, 1, 462, "RO", 1, 0, 0, 0ull},
|
|
{"NCB" , 18, 1, 462, "RO", 1, 0, 0, 0ull},
|
|
{"WIF" , 19, 1, 462, "RO", 1, 0, 0, 0ull},
|
|
{"RIF" , 20, 1, 462, "RO", 1, 0, 0, 0ull},
|
|
{"COUNT" , 21, 1, 462, "RO", 1, 0, 0, 0ull},
|
|
{"PSB2" , 22, 5, 462, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_27_63" , 27, 37, 462, "RAZ", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 13, 463, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_19" , 13, 7, 463, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 20, 3, 463, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 463, "RAZ", 1, 0, 0, 0ull},
|
|
{"ASSERTS" , 0, 17, 464, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 464, "RAZ", 1, 0, 0, 0ull},
|
|
{"PARITY" , 0, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 1, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 465, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENA_PKO" , 0, 1, 466, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENA_DWB" , 1, 1, 466, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STORE_BE" , 2, 1, 466, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 3, 1, 466, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 466, "RAZ", 1, 0, 0, 0ull},
|
|
{"MODE0" , 0, 3, 467, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MODE1" , 3, 3, 467, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 467, "RAZ", 1, 0, 0, 0ull},
|
|
{"PARITY" , 0, 1, 468, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 1, 1, 468, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 468, "RAZ", 1, 0, 0, 0ull},
|
|
{"MODE" , 0, 2, 469, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 469, "RAZ", 1, 0, 0, 0ull},
|
|
{"INDEX" , 0, 8, 470, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 8, 8, 470, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 470, "RAZ", 1, 0, 0, 0ull},
|
|
{"ADR" , 0, 1, 471, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEND" , 1, 1, 471, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBR0" , 2, 1, 471, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBR1" , 3, 1, 471, "RO", 0, 0, 0ull, 0ull},
|
|
{"FIDX" , 4, 1, 471, "RO", 0, 0, 0ull, 0ull},
|
|
{"INDEX" , 5, 1, 471, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBT0" , 6, 1, 471, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBT1" , 7, 1, 471, "RO", 0, 0, 0ull, 0ull},
|
|
{"CAM" , 8, 1, 471, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_15" , 9, 7, 471, "RAZ", 1, 1, 0, 0},
|
|
{"PP" , 16, 2, 471, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 471, "RAZ", 1, 1, 0, 0},
|
|
{"DS_PC" , 0, 32, 472, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 472, "RAZ", 1, 1, 0, 0},
|
|
{"SBE" , 0, 1, 473, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DBE" , 1, 1, 473, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SBE_IE" , 2, 1, 473, "R/W", 0, 1, 0ull, 0},
|
|
{"DBE_IE" , 3, 1, 473, "R/W", 0, 1, 0ull, 0},
|
|
{"SYN" , 4, 5, 473, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_9_11" , 9, 3, 473, "RAZ", 1, 1, 0, 0},
|
|
{"RPE" , 12, 1, 473, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPE_IE" , 13, 1, 473, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_63" , 14, 50, 473, "RAZ", 1, 1, 0, 0},
|
|
{"NBR_THR" , 0, 5, 474, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PFR_DIS" , 5, 1, 474, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 474, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 32, 475, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 475, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 32, 476, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 476, "RAZ", 1, 1, 0, 0},
|
|
{"NOS_CNT" , 0, 9, 477, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_9_63" , 9, 55, 477, "RAZ", 1, 1, 0, 0},
|
|
{"NW_TIM" , 0, 10, 478, "R/W", 0, 0, 0ull, 1023ull},
|
|
{"RESERVED_10_63" , 10, 54, 478, "RAZ", 1, 1, 0, 0},
|
|
{"GRP_MSK" , 0, 16, 479, "R/W", 0, 0, 65535ull, 65535ull},
|
|
{"RESERVED_16_63" , 16, 48, 479, "RAZ", 1, 1, 0, 0},
|
|
{"RND" , 0, 8, 480, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P1" , 8, 8, 480, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P2" , 16, 8, 480, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P3" , 24, 8, 480, "R/W", 0, 1, 255ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 480, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_THR" , 0, 8, 481, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_11" , 8, 4, 481, "RAZ", 1, 1, 0, 0},
|
|
{"MAX_THR" , 12, 8, 481, "R/W", 0, 1, 255ull, 0},
|
|
{"RESERVED_20_23" , 20, 4, 481, "RAZ", 1, 1, 0, 0},
|
|
{"FREE_CNT" , 24, 9, 481, "RO", 0, 1, 249ull, 0},
|
|
{"RESERVED_33_35" , 33, 3, 481, "RAZ", 1, 1, 0, 0},
|
|
{"BUF_CNT" , 36, 9, 481, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_45_47" , 45, 3, 481, "RAZ", 1, 1, 0, 0},
|
|
{"DES_CNT" , 48, 9, 481, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_57_63" , 57, 7, 481, "RAZ", 1, 1, 0, 0},
|
|
{"TS_PC" , 0, 32, 482, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 482, "RAZ", 1, 1, 0, 0},
|
|
{"WA_PC" , 0, 32, 483, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 483, "RAZ", 1, 1, 0, 0},
|
|
{"WA_PC" , 0, 32, 484, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 484, "RAZ", 1, 1, 0, 0},
|
|
{"WQ_INT" , 0, 16, 485, "R/W1C", 0, 1, 0ull, 0},
|
|
{"IQ_DIS" , 16, 16, 485, "R/W1", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 485, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 9, 486, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_9_11" , 9, 3, 486, "RAZ", 1, 1, 0, 0},
|
|
{"DS_CNT" , 12, 9, 486, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_21_23" , 21, 3, 486, "RAZ", 1, 1, 0, 0},
|
|
{"TC_CNT" , 24, 4, 486, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_63" , 28, 36, 486, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 487, "RAZ", 1, 1, 0, 0},
|
|
{"PC_THR" , 8, 20, 487, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_31" , 28, 4, 487, "RAZ", 1, 1, 0, 0},
|
|
{"PC" , 32, 28, 487, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 487, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_THR" , 0, 8, 488, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_11" , 8, 4, 488, "RAZ", 1, 1, 0, 0},
|
|
{"DS_THR" , 12, 8, 488, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_23" , 20, 4, 488, "RAZ", 1, 1, 0, 0},
|
|
{"TC_THR" , 24, 4, 488, "R/W", 0, 1, 0ull, 0},
|
|
{"TC_EN" , 28, 1, 488, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 488, "RAZ", 1, 1, 0, 0},
|
|
{"WS_PC" , 0, 32, 489, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 489, "RAZ", 1, 1, 0, 0},
|
|
{"MEM" , 0, 1, 490, "RO", 0, 0, 0ull, 0ull},
|
|
{"RRC" , 1, 1, 490, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 490, "RAZ", 1, 1, 0, 0},
|
|
{"ENT_EN" , 0, 1, 491, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNG_EN" , 1, 1, 491, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNM_RST" , 2, 1, 491, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNG_RST" , 3, 1, 491, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 491, "RAZ", 1, 1, 0, 0},
|
|
{"PHASE" , 0, 8, 492, "R/W", 0, 0, 100ull, 100ull},
|
|
{"SAMPLE" , 8, 4, 492, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PREAMBLE" , 12, 1, 492, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CLK_IDLE" , 13, 1, 492, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_14" , 14, 1, 492, "RAZ", 1, 1, 0, 0},
|
|
{"SAMPLE_MODE" , 15, 1, 492, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SAMPLE_HI" , 16, 5, 492, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_63" , 21, 43, 492, "RAZ", 1, 1, 0, 0},
|
|
{"REG_ADR" , 0, 5, 493, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 493, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_ADR" , 8, 5, 493, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_13_15" , 13, 3, 493, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_OP" , 16, 1, 493, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_17_63" , 17, 47, 493, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 494, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 494, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 495, "RO", 0, 1, 0ull, 0},
|
|
{"VAL" , 16, 1, 495, "RO", 0, 1, 0ull, 0},
|
|
{"PENDING" , 17, 1, 495, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 495, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 496, "R/W", 0, 1, 0ull, 0},
|
|
{"VAL" , 16, 1, 496, "RO", 0, 1, 0ull, 0},
|
|
{"PENDING" , 17, 1, 496, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 496, "RAZ", 1, 1, 0, 0},
|
|
{"INTERVAL" , 0, 22, 497, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 497, "RAZ", 1, 0, 0, 0ull},
|
|
{"COUNT" , 24, 22, 497, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_46_46" , 46, 1, 497, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENA" , 47, 1, 497, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 497, "RAZ", 1, 0, 0, 0ull},
|
|
{"BSIZE" , 0, 20, 498, "RO", 1, 0, 0, 0ull},
|
|
{"BASE" , 20, 31, 498, "RO", 1, 0, 0, 0ull},
|
|
{"BUCKET" , 51, 13, 498, "RO", 1, 0, 0, 0ull},
|
|
{"BUCKET" , 0, 7, 499, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 499, "RAZ", 1, 0, 0, 0ull},
|
|
{"CSIZE" , 8, 13, 499, "RO", 1, 0, 0, 0ull},
|
|
{"CPOOL" , 21, 3, 499, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 499, "RAZ", 1, 0, 0, 0ull},
|
|
{"RING" , 0, 4, 500, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NUM_BUCKETS" , 4, 20, 500, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIRST_BUCKET" , 24, 31, 500, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_55_63" , 55, 9, 500, "RAZ", 1, 0, 0, 0ull},
|
|
{"RING" , 0, 4, 501, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTERVAL" , 4, 22, 501, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WORDS_PER_CHUNK" , 26, 13, 501, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 39, 3, 501, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENABLE" , 42, 1, 501, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_43_63" , 43, 21, 501, "RAZ", 1, 0, 0, 0ull},
|
|
{"CTL" , 0, 1, 502, "RO", 1, 0, 0, 0ull},
|
|
{"NCB" , 1, 1, 502, "RO", 1, 0, 0, 0ull},
|
|
{"STA" , 2, 2, 502, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 502, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 16, 503, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 503, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENABLE_TIMERS" , 0, 1, 504, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENABLE_DWB" , 1, 1, 504, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 2, 1, 504, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 504, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 16, 505, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 505, "RAZ", 1, 0, 0, 0ull},
|
|
{"INDEX" , 0, 8, 506, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 8, 8, 506, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 506, "RAZ", 1, 0, 0, 0ull},
|
|
{"TDF0" , 0, 1, 507, "RO", 0, 0, 0ull, 0ull},
|
|
{"TDF1" , 1, 1, 507, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCF" , 2, 1, 507, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 507, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ENA" , 0, 1, 508, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WRAP" , 1, 1, 508, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRIG_CTL" , 2, 2, 508, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIME_GRN" , 4, 3, 508, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FULL_THR" , 7, 2, 508, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CIU_TRG" , 9, 1, 508, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CIU_THR" , 10, 1, 508, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_TRG" , 11, 1, 508, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_THR" , 12, 1, 508, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_ENA" , 13, 1, 508, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IGNORE_O" , 14, 1, 508, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 508, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WPTR" , 0, 8, 509, "RO", 0, 0, 0ull, 0ull},
|
|
{"RPTR" , 8, 8, 509, "RO", 0, 0, 0ull, 0ull},
|
|
{"CYCLES" , 16, 48, 509, "RO", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 510, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 510, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 511, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 512, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 512, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 512, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 512, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 512, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 512, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 512, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 512, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 512, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 512, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 512, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 512, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 512, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 512, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 512, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 512, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_16_63" , 16, 48, 512, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 513, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 513, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 513, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 513, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 513, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 513, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 513, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 513, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 513, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 513, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 513, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 513, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 514, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 514, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 514, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 514, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 514, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 514, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CIU_TRG" , 0, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CIU_THR" , 1, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MCD0_TRG" , 2, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MCD0_THR" , 3, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 515, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DATA" , 0, 64, 516, "RO", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 517, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 517, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 518, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 518, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 519, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 519, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 519, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 519, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 519, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 519, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 519, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 519, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 519, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 519, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 519, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 519, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 519, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 519, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 519, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 519, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_16_63" , 16, 48, 519, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 520, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 520, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 520, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 520, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 520, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 520, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 520, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 520, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 520, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 520, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 520, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 520, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 521, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 521, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 521, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 521, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 521, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 521, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 522, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 522, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 523, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 523, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 524, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 524, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 524, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 524, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 524, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 524, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 524, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 524, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 524, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 524, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 524, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 524, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 524, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 524, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 524, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 524, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_16_63" , 16, 48, 524, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 525, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 525, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 525, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 525, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 525, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 525, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 525, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 525, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 525, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 525, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 525, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 525, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 526, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 526, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 526, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 526, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 526, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 526, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"INEPINT" , 0, 16, 527, "RO", 0, 0, 0ull, 0ull},
|
|
{"OUTEPINT" , 16, 16, 527, "RO", 0, 0, 0ull, 0ull},
|
|
{"INEPMSK" , 0, 16, 528, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OUTEPMSK" , 16, 16, 528, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DEVSPD" , 0, 2, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NZSTSOUTHSHK" , 2, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 529, "RAZ", 1, 1, 0, 0},
|
|
{"DEVADDR" , 4, 7, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PERFRINT" , 11, 2, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_17" , 13, 5, 529, "RAZ", 1, 1, 0, 0},
|
|
{"EPMISCNT" , 18, 5, 529, "R/W", 0, 0, 8ull, 0ull},
|
|
{"RESERVED_23_31" , 23, 9, 529, "RAZ", 1, 1, 0, 0},
|
|
{"RMTWKUPSIG" , 0, 1, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SFTDISCON" , 1, 1, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GNPINNAKSTS" , 2, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"GOUTNAKSTS" , 3, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"TSTCTL" , 4, 3, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SGNPINNAK" , 7, 1, 530, "WO", 0, 0, 0ull, 0ull},
|
|
{"CGNPINNAK" , 8, 1, 530, "WO", 0, 0, 0ull, 0ull},
|
|
{"SGOUTNAK" , 9, 1, 530, "WO", 0, 0, 0ull, 0ull},
|
|
{"CGOUTNAK" , 10, 1, 530, "WO", 0, 0, 0ull, 0ull},
|
|
{"PWRONPRGDONE" , 11, 1, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_31" , 12, 20, 530, "RAZ", 1, 1, 0, 0},
|
|
{"MPS" , 0, 11, 531, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NEXTEP" , 11, 4, 531, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBACTEP" , 15, 1, 531, "R/W", 0, 0, 1ull, 0ull},
|
|
{"DPID" , 16, 1, 531, "RO", 0, 0, 0ull, 0ull},
|
|
{"NAKSTS" , 17, 1, 531, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTYPE" , 18, 2, 531, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 531, "RAZ", 1, 1, 0, 0},
|
|
{"STALL" , 21, 1, 531, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFNUM" , 22, 4, 531, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNAK" , 26, 1, 531, "WO", 0, 0, 0ull, 0ull},
|
|
{"SNAK" , 27, 1, 531, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD0PID" , 28, 1, 531, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD1PID" , 29, 1, 531, "WO", 0, 0, 0ull, 0ull},
|
|
{"EPDIS" , 30, 1, 531, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPENA" , 31, 1, 531, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XFERCOMPL" , 0, 1, 532, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLD" , 1, 1, 532, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AHBERR" , 2, 1, 532, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TIMEOUT" , 3, 1, 532, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTKNTXFEMP" , 4, 1, 532, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTKNEPMIS" , 5, 1, 532, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INEPNAKEFF" , 6, 1, 532, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_31" , 7, 25, 532, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPLMSK" , 0, 1, 533, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLDMSK" , 1, 1, 533, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AHBERRMSK" , 2, 1, 533, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMEOUTMSK" , 3, 1, 533, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTKNTXFEMPMSK" , 4, 1, 533, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTKNEPMISMSK" , 5, 1, 533, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INEPNAKEFFMSK" , 6, 1, 533, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_31" , 7, 25, 533, "RAZ", 1, 1, 0, 0},
|
|
{"XFERSIZE" , 0, 19, 534, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKTCNT" , 19, 10, 534, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MC" , 29, 2, 534, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_31" , 31, 1, 534, "RAZ", 1, 1, 0, 0},
|
|
{"MPS" , 0, 11, 535, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_14" , 11, 4, 535, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"USBACTEP" , 15, 1, 535, "R/W", 0, 0, 1ull, 0ull},
|
|
{"DPID" , 16, 1, 535, "RO", 0, 0, 0ull, 0ull},
|
|
{"NAKSTS" , 17, 1, 535, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTYPE" , 18, 2, 535, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SNP" , 20, 1, 535, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STALL" , 21, 1, 535, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_25" , 22, 4, 535, "RAZ", 1, 1, 0, 0},
|
|
{"CNAK" , 26, 1, 535, "WO", 0, 0, 0ull, 0ull},
|
|
{"SNAK" , 27, 1, 535, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD0PID" , 28, 1, 535, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD1PID" , 29, 1, 535, "WO", 0, 0, 0ull, 0ull},
|
|
{"EPDIS" , 30, 1, 535, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPENA" , 31, 1, 535, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XFERCOMPL" , 0, 1, 536, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLD" , 1, 1, 536, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AHBERR" , 2, 1, 536, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SETUP" , 3, 1, 536, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OUTTKNEPDIS" , 4, 1, 536, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 536, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPLMSK" , 0, 1, 537, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLDMSK" , 1, 1, 537, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AHBERRMSK" , 2, 1, 537, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SETUPMSK" , 3, 1, 537, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OUTTKNEPDISMSK" , 4, 1, 537, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 537, "RAZ", 1, 1, 0, 0},
|
|
{"XFERSIZE" , 0, 19, 538, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKTCNT" , 19, 10, 538, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MC" , 29, 2, 538, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_31" , 31, 1, 538, "RAZ", 1, 1, 0, 0},
|
|
{"DPTXFSTADDR" , 0, 16, 539, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPTXFSIZE" , 16, 16, 539, "RO", 0, 0, 1896ull, 1896ull},
|
|
{"SUSPSTS" , 0, 1, 540, "RO", 0, 0, 0ull, 0ull},
|
|
{"ENUMSPD" , 1, 2, 540, "RO", 0, 0, 0ull, 0ull},
|
|
{"ERRTICERR" , 3, 1, 540, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 540, "RAZ", 1, 1, 0, 0},
|
|
{"SOFFN" , 8, 14, 540, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_31" , 22, 10, 540, "RAZ", 1, 1, 0, 0},
|
|
{"INTKNWPTR" , 0, 5, 541, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_6" , 5, 2, 541, "RAZ", 1, 1, 0, 0},
|
|
{"WRAPBIT" , 7, 1, 541, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 8, 24, 541, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 0, 32, 542, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 0, 32, 543, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 0, 32, 544, "RO", 0, 0, 0ull, 0ull},
|
|
{"GLBLINTRMSK" , 0, 1, 545, "R/W", 0, 0, 0ull, 1ull},
|
|
{"HBSTLEN" , 1, 4, 545, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMAEN" , 5, 1, 545, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_6" , 6, 1, 545, "RAZ", 1, 1, 0, 0},
|
|
{"NPTXFEMPLVL" , 7, 1, 545, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PTXFEMPLVL" , 8, 1, 545, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_9_31" , 9, 23, 545, "RAZ", 1, 1, 0, 0},
|
|
{"EPDIR" , 0, 32, 546, "RO", 0, 0, 0ull, 0ull},
|
|
{"OTGMODE" , 0, 3, 547, "RO", 0, 0, 2ull, 2ull},
|
|
{"OTGARCH" , 3, 2, 547, "RO", 0, 0, 1ull, 1ull},
|
|
{"SINGPNT" , 5, 1, 547, "RO", 0, 0, 0ull, 0ull},
|
|
{"HSPHYTYPE" , 6, 2, 547, "RO", 0, 0, 1ull, 1ull},
|
|
{"FSPHYTYPE" , 8, 2, 547, "RO", 0, 0, 0ull, 0ull},
|
|
{"NUMDEVEPS" , 10, 4, 547, "RO", 0, 0, 4ull, 4ull},
|
|
{"NUMHSTCHNL" , 14, 4, 547, "RO", 0, 0, 7ull, 7ull},
|
|
{"PERIOSUPPORT" , 18, 1, 547, "RO", 0, 0, 1ull, 1ull},
|
|
{"DYNFIFOSIZING" , 19, 1, 547, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_20_21" , 20, 2, 547, "RAZ", 1, 1, 0, 0},
|
|
{"NPTXQDEPTH" , 22, 2, 547, "RO", 0, 0, 2ull, 2ull},
|
|
{"PTXQDEPTH" , 24, 2, 547, "RO", 0, 0, 2ull, 2ull},
|
|
{"TKNQDEPTH" , 26, 5, 547, "RO", 0, 0, 30ull, 30ull},
|
|
{"RESERVED_31_31" , 31, 1, 547, "RAZ", 1, 1, 0, 0},
|
|
{"XFERSIZEWIDTH" , 0, 4, 548, "RO", 0, 0, 8ull, 8ull},
|
|
{"PKTSIZEWIDTH" , 4, 3, 548, "RO", 0, 0, 6ull, 6ull},
|
|
{"OTGEN" , 7, 1, 548, "RO", 0, 0, 1ull, 1ull},
|
|
{"I2C_SELECTION" , 8, 1, 548, "RO", 0, 0, 0ull, 0ull},
|
|
{"VENDOR_CONTROL_INTERFACE_SUPPORT", 9, 1, 548, "RO", 0, 0, 0ull, 0ull},
|
|
{"OPTFEATURE" , 10, 1, 548, "RO", 0, 0, 1ull, 1ull},
|
|
{"RSTTYPE" , 11, 1, 548, "RO", 0, 0, 1ull, 1ull},
|
|
{"AHBPHYSYNC" , 12, 1, 548, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 548, "RAZ", 1, 1, 0, 0},
|
|
{"DFIFODEPTH" , 16, 16, 548, "RO", 0, 0, 1824ull, 1824ull},
|
|
{"NUMDEVPERIOEPS" , 0, 4, 549, "RO", 0, 0, 4ull, 4ull},
|
|
{"ENABLEPWROPT" , 4, 1, 549, "RO", 0, 0, 0ull, 0ull},
|
|
{"AHBFREQ" , 5, 1, 549, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_13" , 6, 8, 549, "RAZ", 1, 1, 0, 0},
|
|
{"PHYDATAWIDTH" , 14, 2, 549, "RO", 0, 0, 1ull, 1ull},
|
|
{"NUMCTLEPS" , 16, 4, 549, "RO", 0, 0, 4ull, 4ull},
|
|
{"IDDGFLTR" , 20, 1, 549, "RO", 0, 0, 0ull, 0ull},
|
|
{"VBUSVALIDFLTR" , 21, 1, 549, "RO", 0, 0, 0ull, 0ull},
|
|
{"AVALIDFLTR" , 22, 1, 549, "RO", 0, 0, 1ull, 1ull},
|
|
{"BVALIDFLTR" , 23, 1, 549, "RO", 0, 0, 1ull, 1ull},
|
|
{"SESSENDFLTR" , 24, 1, 549, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_25_31" , 25, 7, 549, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 550, "RAZ", 1, 1, 0, 0},
|
|
{"MODEMISMSK" , 1, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OTGINTMSK" , 2, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SOFMSK" , 3, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RXFLVLMSK" , 4, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NPTXFEMPMSK" , 5, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GINNAKEFFMSK" , 6, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GOUTNAKEFFMSK" , 7, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ULPICKINTMSK" , 8, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"I2CINT" , 9, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ERLYSUSPMSK" , 10, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBSUSPMSK" , 11, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBRSTMSK" , 12, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENUMDONEMSK" , 13, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ISOOUTDROPMSK" , 14, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EOPFMSK" , 15, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 550, "RAZ", 1, 1, 0, 0},
|
|
{"EPMISMSK" , 17, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INEPINTMSK" , 18, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OEPINTMSK" , 19, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INCOMPISOINMSK" , 20, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INCOMPLPMSK" , 21, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FETSUSPMSK" , 22, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 550, "RAZ", 1, 1, 0, 0},
|
|
{"PRTINTMSK" , 24, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HCHINTMSK" , 25, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PTXFEMPMSK" , 26, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 550, "RAZ", 1, 1, 0, 0},
|
|
{"CONIDSTSCHNGMSK" , 28, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DISCONNINTMSK" , 29, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SESSREQINTMSK" , 30, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WKUPINTMSK" , 31, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CURMOD" , 0, 1, 551, "RO", 0, 0, 0ull, 0ull},
|
|
{"MODEMIS" , 1, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OTGINT" , 2, 1, 551, "RO", 0, 0, 0ull, 0ull},
|
|
{"SOF" , 3, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXFLVL" , 4, 1, 551, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPTXFEMP" , 5, 1, 551, "RO", 0, 0, 0ull, 0ull},
|
|
{"GINNAKEFF" , 6, 1, 551, "RO", 0, 0, 0ull, 0ull},
|
|
{"GOUTNAKEFF" , 7, 1, 551, "RO", 0, 0, 0ull, 0ull},
|
|
{"ULPICKINT" , 8, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I2CINT" , 9, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ERLYSUSP" , 10, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USBSUSP" , 11, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USBRST" , 12, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ENUMDONE" , 13, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ISOOUTDROP" , 14, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EOPF" , 15, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 551, "RAZ", 1, 1, 0, 0},
|
|
{"EPMIS" , 17, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IEPINT" , 18, 1, 551, "RO", 0, 0, 0ull, 0ull},
|
|
{"OEPINT" , 19, 1, 551, "RO", 0, 0, 0ull, 0ull},
|
|
{"INCOMPISOIN" , 20, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INCOMPLP" , 21, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FETSUSP" , 22, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 551, "RAZ", 1, 1, 0, 0},
|
|
{"PRTINT" , 24, 1, 551, "RO", 0, 0, 0ull, 0ull},
|
|
{"HCHINT" , 25, 1, 551, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTXFEMP" , 26, 1, 551, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 551, "RAZ", 1, 1, 0, 0},
|
|
{"CONIDSTSCHNG" , 28, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DISCONNINT" , 29, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SESSREQINT" , 30, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WKUPINT" , 31, 1, 551, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NPTXFSTADDR" , 0, 16, 552, "R/W", 0, 0, 1824ull, 456ull},
|
|
{"NPTXFDEP" , 16, 16, 552, "R/W", 0, 0, 1824ull, 912ull},
|
|
{"NPTXFSPCAVAIL" , 0, 16, 553, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPTXQSPCAVAIL" , 16, 8, 553, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPTXQTOP" , 24, 7, 553, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_31" , 31, 1, 553, "RAZ", 1, 1, 0, 0},
|
|
{"SESREQSCS" , 0, 1, 554, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SESREQ" , 1, 1, 554, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_7" , 2, 6, 554, "RAZ", 1, 1, 0, 0},
|
|
{"HSTNEGSCS" , 8, 1, 554, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HNPREQ" , 9, 1, 554, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HSTSETHNPEN" , 10, 1, 554, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DEVHNPEN" , 11, 1, 554, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_15" , 12, 4, 554, "RAZ", 1, 1, 0, 0},
|
|
{"CONIDSTS" , 16, 1, 554, "RO", 1, 1, 0, 0},
|
|
{"DBNCTIME" , 17, 1, 554, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASESVLD" , 18, 1, 554, "RO", 1, 1, 0, 0},
|
|
{"BSESVLD" , 19, 1, 554, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_20_31" , 20, 12, 554, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 555, "RAZ", 1, 1, 0, 0},
|
|
{"SESENDDET" , 2, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_7" , 3, 5, 555, "RAZ", 1, 1, 0, 0},
|
|
{"SESREQSUCSTSCHNG" , 8, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"HSTNEGSUCSTSCHNG" , 9, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_16" , 10, 7, 555, "RAZ", 1, 1, 0, 0},
|
|
{"HSTNEGDET" , 17, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ADEVTOUTCHG" , 18, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DBNCEDONE" , 19, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 555, "RAZ", 1, 1, 0, 0},
|
|
{"CSFTRST" , 0, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HSFTRST" , 1, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMCNTRRST" , 2, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTKNQFLSH" , 3, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RXFFLSH" , 4, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFFLSH" , 5, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFNUM" , 6, 5, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_29" , 11, 19, 556, "RAZ", 1, 1, 0, 0},
|
|
{"DMAREQ" , 30, 1, 556, "RO", 0, 0, 0ull, 0ull},
|
|
{"AHBIDLE" , 31, 1, 556, "RO", 0, 0, 1ull, 1ull},
|
|
{"RXFDEP" , 0, 16, 557, "R/W", 0, 0, 1824ull, 456ull},
|
|
{"RESERVED_16_31" , 16, 16, 557, "RAZ", 1, 1, 0, 0},
|
|
{"EPNUM" , 0, 4, 558, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 558, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 558, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 558, "RO", 0, 0, 0ull, 0ull},
|
|
{"FN" , 21, 4, 558, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_31" , 25, 7, 558, "RAZ", 1, 1, 0, 0},
|
|
{"CHNUM" , 0, 4, 559, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 559, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 559, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 559, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 559, "RAZ", 1, 1, 0, 0},
|
|
{"EPNUM" , 0, 4, 560, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 560, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 560, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 560, "RO", 0, 0, 0ull, 0ull},
|
|
{"FN" , 21, 4, 560, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_31" , 25, 7, 560, "RAZ", 1, 1, 0, 0},
|
|
{"CHNUM" , 0, 4, 561, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 561, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 561, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 561, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 561, "RAZ", 1, 1, 0, 0},
|
|
{"SYNOPSYSID" , 0, 32, 562, "RO", 1, 1, 0, 0},
|
|
{"TOUTCAL" , 0, 3, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHYIF" , 3, 1, 563, "RO", 0, 0, 1ull, 1ull},
|
|
{"ULPI_UTMI_SEL" , 4, 1, 563, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSINTF" , 5, 1, 563, "WO", 0, 0, 0ull, 0ull},
|
|
{"PHYSEL" , 6, 1, 563, "WO", 0, 0, 0ull, 0ull},
|
|
{"DDRSEL" , 7, 1, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SRPCAP" , 8, 1, 563, "RO", 0, 0, 0ull, 0ull},
|
|
{"HNPCAP" , 9, 1, 563, "RO", 0, 0, 0ull, 0ull},
|
|
{"USBTRDTIM" , 10, 4, 563, "R/W", 0, 0, 5ull, 5ull},
|
|
{"RESERVED_14_14" , 14, 1, 563, "RAZ", 1, 1, 0, 0},
|
|
{"PHYLPWRCLKSEL" , 15, 1, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OTGI2CSEL" , 16, 1, 563, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 563, "RAZ", 1, 1, 0, 0},
|
|
{"HAINT" , 0, 16, 564, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_31" , 16, 16, 564, "RAZ", 1, 1, 0, 0},
|
|
{"HAINTMSK" , 0, 16, 565, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_31" , 16, 16, 565, "RAZ", 1, 1, 0, 0},
|
|
{"MPS" , 0, 11, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPNUM" , 11, 4, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPDIR" , 15, 1, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 566, "RAZ", 1, 1, 0, 0},
|
|
{"LSPDDEV" , 17, 1, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPTYPE" , 18, 2, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EC" , 20, 2, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DEVADDR" , 22, 7, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ODDFRM" , 29, 1, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHDIS" , 30, 1, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHENA" , 31, 1, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSLSPCLKSEL" , 0, 2, 567, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSLSSUPP" , 2, 1, 567, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_31" , 3, 29, 567, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPL" , 0, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CHHLTD" , 1, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AHBERR" , 2, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"STALL" , 3, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NAK" , 4, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ACK" , 5, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NYET" , 6, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"XACTERR" , 7, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BBLERR" , 8, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FRMOVRUN" , 9, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DATATGLERR" , 10, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_31" , 11, 21, 568, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPLMSK" , 0, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHHLTDMSK" , 1, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AHBERRMSK" , 2, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STALLMSK" , 3, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NAKMSK" , 4, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ACKMSK" , 5, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NYETMSK" , 6, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XACTERRMSK" , 7, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BBLERRMSK" , 8, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMOVRUNMSK" , 9, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DATATGLERRMSK" , 10, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_31" , 11, 21, 569, "RAZ", 1, 1, 0, 0},
|
|
{"PRTADDR" , 0, 7, 570, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HUBADDR" , 7, 7, 570, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XACTPOS" , 14, 2, 570, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COMPSPLT" , 16, 1, 570, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_30" , 17, 14, 570, "RAZ", 1, 1, 0, 0},
|
|
{"SPLTENA" , 31, 1, 570, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XFERSIZE" , 0, 19, 571, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKTCNT" , 19, 10, 571, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PID" , 29, 2, 571, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DOPNG" , 31, 1, 571, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRINT" , 0, 16, 572, "R/W", 0, 0, 2959ull, 3750ull},
|
|
{"RESERVED_16_31" , 16, 16, 572, "RAZ", 1, 1, 0, 0},
|
|
{"FRNUM" , 0, 16, 573, "RO", 0, 0, 16383ull, 0ull},
|
|
{"FRREM" , 16, 16, 573, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTCONNSTS" , 0, 1, 574, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTCONNDET" , 1, 1, 574, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTENA" , 2, 1, 574, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTENCHNG" , 3, 1, 574, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTOVRCURRACT" , 4, 1, 574, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTOVRCURRCHNG" , 5, 1, 574, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTRES" , 6, 1, 574, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTSUSP" , 7, 1, 574, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTRST" , 8, 1, 574, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 574, "RAZ", 1, 1, 0, 0},
|
|
{"PRTLNSTS" , 10, 2, 574, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTPWR" , 12, 1, 574, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTTSTCTL" , 13, 4, 574, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTSPD" , 17, 2, 574, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_31" , 19, 13, 574, "RAZ", 1, 1, 0, 0},
|
|
{"PTXFSTADDR" , 0, 16, 575, "R/W", 0, 0, 3648ull, 912ull},
|
|
{"PTXFSIZE" , 16, 16, 575, "R/W", 0, 0, 1824ull, 456ull},
|
|
{"PTXFSPCAVAIL" , 0, 16, 576, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTXQSPCAVAIL" , 16, 8, 576, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTXQTOP" , 24, 8, 576, "RO", 0, 0, 0ull, 0ull},
|
|
{"DATA" , 0, 32, 577, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STOPPCLK" , 0, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GATEHCLK" , 1, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PWRCLMP" , 2, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSTPDWNMODULE" , 3, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHYSUSPENDED" , 4, 1, 578, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 578, "RAZ", 1, 1, 0, 0},
|
|
{"NOF_BIS" , 0, 1, 579, "RO", 0, 0, 0ull, 0ull},
|
|
{"NIF_BIS" , 1, 1, 579, "RO", 0, 0, 0ull, 0ull},
|
|
{"USBC_BIS" , 2, 1, 579, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 579, "RAZ", 1, 1, 0, 0},
|
|
{"DIVIDE" , 0, 3, 580, "R/W", 0, 0, 4ull, 4ull},
|
|
{"HRST" , 3, 1, 580, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PRST" , 4, 1, 580, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ENABLE" , 5, 1, 580, "R/W", 0, 0, 1ull, 1ull},
|
|
{"POR" , 6, 1, 580, "R/W", 0, 0, 1ull, 0ull},
|
|
{"S_BIST" , 7, 1, 580, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SD_MODE" , 8, 2, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CDIV_BYP" , 10, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_C_SEL" , 11, 2, 580, "R/W", 0, 0, 2ull, 2ull},
|
|
{"P_COM_ON" , 13, 1, 580, "R/W", 0, 0, 1ull, 1ull},
|
|
{"P_XENBN" , 14, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_RCLK" , 15, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_X_ON" , 16, 1, 580, "R/W", 0, 0, 1ull, 1ull},
|
|
{"HCLK_RST" , 17, 1, 580, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_18_63" , 18, 46, 580, "RAZ", 1, 1, 0, 0},
|
|
{"L2C_EMOD" , 0, 2, 581, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INV_A2" , 2, 1, 581, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_TEST" , 3, 1, 581, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_STT" , 4, 1, 581, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_0PAG" , 5, 1, 581, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 581, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 582, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 582, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 583, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 583, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 584, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 584, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 585, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 585, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 586, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 586, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 587, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 587, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 588, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 588, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 589, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 589, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 590, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 590, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 591, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 591, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 592, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 592, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 593, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 593, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 594, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 594, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 595, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 595, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 596, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 596, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 597, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 597, "RAZ", 1, 1, 0, 0},
|
|
{"BURST" , 0, 4, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHANNEL" , 4, 5, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COUNT" , 9, 11, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"F_ADDR" , 20, 18, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"REQ" , 38, 1, 598, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DONE" , 39, 1, 598, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 598, "RAZ", 1, 1, 0, 0},
|
|
{"PR_PO_E" , 0, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PR_PU_F" , 1, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NR_PO_E" , 2, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NR_PU_F" , 3, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LR_PO_E" , 4, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LR_PU_F" , 5, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PT_PO_E" , 6, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PT_PU_F" , 7, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NT_PO_E" , 8, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NT_PU_F" , 9, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LT_PO_E" , 10, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LT_PU_F" , 11, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DCRED_E" , 12, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DCRED_F" , 13, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2C_S_E" , 14, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2C_A_F" , 15, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2_FI_E" , 16, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2_FI_F" , 17, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_E" , 18, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_F" , 19, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_F" , 20, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_E" , 21, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_F" , 22, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_E" , 23, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UOD_PE" , 24, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UOD_PF" , 25, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"N2U_PF" , 26, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"N2U_PE" , 27, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"U2N_D_PE" , 28, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"U2N_D_PF" , 29, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"U2N_C_PF" , 30, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"U2N_C_PE" , 31, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LTL_F_PE" , 32, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LTL_F_PF" , 33, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_RPE" , 34, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_RPF" , 35, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_DPE" , 36, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_DPF" , 37, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 599, "RAZ", 1, 1, 0, 0},
|
|
{"PR_PO_E" , 0, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PR_PU_F" , 1, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NR_PO_E" , 2, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NR_PU_F" , 3, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LR_PO_E" , 4, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LR_PU_F" , 5, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PT_PO_E" , 6, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PT_PU_F" , 7, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NT_PO_E" , 8, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NT_PU_F" , 9, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LT_PO_E" , 10, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LT_PU_F" , 11, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCRED_E" , 12, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCRED_F" , 13, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"L2C_S_E" , 14, 1, 600, "R/W1C", 1, 0, 0, 0ull},
|
|
{"L2C_A_F" , 15, 1, 600, "R/W1C", 1, 0, 0, 0ull},
|
|
{"LT_FI_E" , 16, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LT_FI_F" , 17, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_E" , 18, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_F" , 19, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_F" , 20, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_E" , 21, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_F" , 22, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_E" , 23, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UOD_PE" , 24, 1, 600, "R/W1C", 1, 0, 0, 0ull},
|
|
{"UOD_PF" , 25, 1, 600, "R/W1C", 1, 0, 0, 0ull},
|
|
{"N2U_PF" , 26, 1, 600, "R/W1C", 1, 0, 0, 0ull},
|
|
{"N2U_PE" , 27, 1, 600, "R/W1C", 1, 0, 0, 0ull},
|
|
{"U2N_D_PE" , 28, 1, 600, "R/W1C", 1, 0, 0, 0ull},
|
|
{"U2N_D_PF" , 29, 1, 600, "R/W1C", 1, 0, 0, 0ull},
|
|
{"U2N_C_PF" , 30, 1, 600, "R/W1C", 1, 0, 0, 0ull},
|
|
{"U2N_C_PE" , 31, 1, 600, "R/W1C", 1, 0, 0, 0ull},
|
|
{"LTL_F_PE" , 32, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LTL_F_PF" , 33, 1, 600, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ND4O_RPE" , 34, 1, 600, "R/W1C", 1, 0, 0, 0ull},
|
|
{"ND4O_RPF" , 35, 1, 600, "R/W1C", 1, 0, 0, 0ull},
|
|
{"ND4O_DPE" , 36, 1, 600, "R/W1C", 1, 0, 0, 0ull},
|
|
{"ND4O_DPF" , 37, 1, 600, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 600, "RAZ", 1, 1, 0, 0},
|
|
{"ATE_RESET" , 0, 1, 601, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TDATA_IN" , 1, 8, 601, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TADDR_IN" , 9, 4, 601, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TDATA_SEL" , 13, 1, 601, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BIST_ENB" , 14, 1, 601, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VTEST_ENB" , 15, 1, 601, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LOOP_ENB" , 16, 1, 601, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TX_BS_EN" , 17, 1, 601, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TX_BS_ENH" , 18, 1, 601, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TUNING" , 19, 4, 601, "R/W", 0, 0, 9ull, 0ull},
|
|
{"HST_MODE" , 23, 1, 601, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DM_PULLD" , 24, 1, 601, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DP_PULLD" , 25, 1, 601, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TCLK" , 26, 1, 601, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBP_BIST" , 27, 1, 601, "R/W", 0, 0, 1ull, 1ull},
|
|
{"USBC_END" , 28, 1, 601, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_BMODE" , 29, 1, 601, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_31" , 30, 2, 601, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TDATA_OUT" , 32, 4, 601, "RO", 1, 1, 0, 0},
|
|
{"BIST_ERR" , 36, 1, 601, "RO", 0, 0, 0ull, 0ull},
|
|
{"BIST_DONE" , 37, 1, 601, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 601, "RAZ", 1, 1, 0, 0},
|
|
{"ZIP_CTL" , 0, 4, 602, "RO", 1, 0, 0, 0ull},
|
|
{"ZIP_CORE" , 4, 27, 602, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 602, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 33, 603, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 33, 13, 603, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 46, 3, 603, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 49, 9, 603, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_58_63" , 58, 6, 603, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 0, 1, 604, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FORCECLK" , 1, 1, 604, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 604, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DISABLED" , 0, 1, 605, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_7" , 1, 7, 605, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CTXSIZE" , 8, 12, 605, "RO", 0, 0, 1536ull, 1536ull},
|
|
{"ONFSIZE" , 20, 12, 605, "RO", 0, 0, 512ull, 512ull},
|
|
{"DEPTH" , 32, 16, 605, "RO", 0, 0, 31744ull, 31744ull},
|
|
{"RESERVED_48_63" , 48, 16, 605, "RAZ", 1, 0, 0, 0ull},
|
|
{"ASSERTS" , 0, 14, 606, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 606, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 0, 1, 607, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 607, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 0, 1, 608, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 608, "RAZ", 1, 0, 0, 0ull},
|
|
{NULL,0,0,0,0,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn30xx[] = {
|
|
/* name , ---------------type, bits, off, #field, fld of */
|
|
{"cvmx_asx#_gmii_rx_clk_set" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 2, 0},
|
|
{"cvmx_asx#_gmii_rx_dat_set" , CVMX_CSR_DB_TYPE_RSL, 64, 1, 2, 2},
|
|
{"cvmx_asx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 6, 4},
|
|
{"cvmx_asx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 3, 6, 10},
|
|
{"cvmx_asx#_mii_rx_dat_set" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 2, 16},
|
|
{"cvmx_asx#_prt_loop" , CVMX_CSR_DB_TYPE_RSL, 64, 5, 4, 18},
|
|
{"cvmx_asx#_rx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 2, 22},
|
|
{"cvmx_asx#_rx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 9, 2, 24},
|
|
{"cvmx_asx#_tx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 2, 26},
|
|
{"cvmx_asx#_tx_comp_byp" , CVMX_CSR_DB_TYPE_RSL, 64, 13, 4, 28},
|
|
{"cvmx_asx#_tx_hi_water#" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 2, 32},
|
|
{"cvmx_asx#_tx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 17, 2, 34},
|
|
{"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 18, 2, 36},
|
|
{"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 19, 2, 38},
|
|
{"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 20, 2, 40},
|
|
{"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 21, 2, 42},
|
|
{"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 22, 19, 44},
|
|
{"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 25, 2, 63},
|
|
{"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 28, 19, 65},
|
|
{"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 31, 2, 84},
|
|
{"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 32, 2, 86},
|
|
{"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 33, 2, 88},
|
|
{"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 34, 2, 90},
|
|
{"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 35, 2, 92},
|
|
{"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 36, 2, 94},
|
|
{"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 37, 1, 96},
|
|
{"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 38, 2, 97},
|
|
{"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 39, 2, 99},
|
|
{"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 40, 4, 101},
|
|
{"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 41, 2, 105},
|
|
{"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 42, 3, 107},
|
|
{"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 46, 7, 110},
|
|
{"cvmx_dbg_data" , CVMX_CSR_DB_TYPE_NCB, 64, 47, 6, 117},
|
|
{"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 48, 6, 123},
|
|
{"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 49, 7, 129},
|
|
{"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 50, 29, 136},
|
|
{"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 51, 29, 165},
|
|
{"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 2, 194},
|
|
{"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 60, 2, 196},
|
|
{"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 68, 3, 198},
|
|
{"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 69, 3, 201},
|
|
{"cvmx_fpa_wart_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 70, 2, 204},
|
|
{"cvmx_fpa_wart_status" , CVMX_CSR_DB_TYPE_RSL, 64, 71, 2, 206},
|
|
{"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 72, 8, 208},
|
|
{"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 73, 2, 216},
|
|
{"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 74, 4, 218},
|
|
{"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 75, 2, 222},
|
|
{"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 76, 5, 224},
|
|
{"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 79, 1, 229},
|
|
{"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 82, 1, 230},
|
|
{"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 85, 1, 231},
|
|
{"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 88, 1, 232},
|
|
{"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 91, 1, 233},
|
|
{"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 94, 1, 234},
|
|
{"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 97, 2, 235},
|
|
{"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 100, 4, 237},
|
|
{"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 103, 2, 241},
|
|
{"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 106, 11, 243},
|
|
{"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 109, 10, 254},
|
|
{"cvmx_gmx#_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 112, 2, 264},
|
|
{"cvmx_gmx#_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 115, 2, 266},
|
|
{"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 118, 2, 268},
|
|
{"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 121, 20, 270},
|
|
{"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 124, 20, 290},
|
|
{"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 127, 2, 310},
|
|
{"cvmx_gmx#_rx#_rx_inbnd" , CVMX_CSR_DB_TYPE_RSL, 64, 130, 4, 312},
|
|
{"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 133, 2, 316},
|
|
{"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 136, 2, 318},
|
|
{"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 139, 2, 320},
|
|
{"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 142, 2, 322},
|
|
{"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 145, 2, 324},
|
|
{"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 148, 2, 326},
|
|
{"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 151, 2, 328},
|
|
{"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 154, 2, 330},
|
|
{"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 157, 2, 332},
|
|
{"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 160, 2, 334},
|
|
{"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 163, 4, 336},
|
|
{"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 166, 2, 340},
|
|
{"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 169, 2, 342},
|
|
{"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 172, 2, 344},
|
|
{"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 175, 4, 346},
|
|
{"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 176, 2, 350},
|
|
{"cvmx_gmx#_rx_tx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 177, 4, 352},
|
|
{"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 178, 2, 356},
|
|
{"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 181, 3, 358},
|
|
{"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 182, 5, 361},
|
|
{"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 185, 2, 366},
|
|
{"cvmx_gmx#_tx#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 188, 2, 368},
|
|
{"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 191, 3, 370},
|
|
{"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 194, 2, 373},
|
|
{"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 197, 2, 375},
|
|
{"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 200, 2, 377},
|
|
{"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 203, 2, 379},
|
|
{"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 206, 2, 381},
|
|
{"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 209, 2, 383},
|
|
{"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 212, 2, 385},
|
|
{"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 215, 2, 387},
|
|
{"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 218, 2, 389},
|
|
{"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 221, 2, 391},
|
|
{"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 224, 2, 393},
|
|
{"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 227, 2, 395},
|
|
{"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 230, 2, 397},
|
|
{"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 233, 2, 399},
|
|
{"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 236, 2, 401},
|
|
{"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 239, 2, 403},
|
|
{"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 242, 2, 405},
|
|
{"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 245, 2, 407},
|
|
{"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 248, 2, 409},
|
|
{"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 251, 2, 411},
|
|
{"cvmx_gmx#_tx_clk_msk#" , CVMX_CSR_DB_TYPE_RSL, 64, 252, 2, 413},
|
|
{"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 254, 2, 415},
|
|
{"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 255, 2, 417},
|
|
{"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 256, 3, 419},
|
|
{"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 257, 10, 422},
|
|
{"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 258, 10, 432},
|
|
{"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 259, 2, 442},
|
|
{"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 260, 2, 444},
|
|
{"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 261, 6, 446},
|
|
{"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 262, 2, 452},
|
|
{"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 263, 2, 454},
|
|
{"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 264, 2, 456},
|
|
{"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 265, 7, 458},
|
|
{"cvmx_gpio_boot_ena" , CVMX_CSR_DB_TYPE_NCB, 64, 281, 3, 465},
|
|
{"cvmx_gpio_dbg_ena" , CVMX_CSR_DB_TYPE_NCB, 64, 282, 2, 468},
|
|
{"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 283, 2, 470},
|
|
{"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 284, 2, 472},
|
|
{"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 285, 2, 474},
|
|
{"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 286, 2, 476},
|
|
{"cvmx_gpio_xbit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 287, 6, 478},
|
|
{"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 295, 19, 484},
|
|
{"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 296, 6, 503},
|
|
{"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 297, 3, 509},
|
|
{"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 298, 5, 512},
|
|
{"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 299, 5, 517},
|
|
{"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 300, 1, 522},
|
|
{"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 301, 1, 523},
|
|
{"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 302, 5, 524},
|
|
{"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 303, 5, 529},
|
|
{"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 304, 5, 534},
|
|
{"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 305, 5, 539},
|
|
{"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 306, 1, 544},
|
|
{"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 307, 1, 545},
|
|
{"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 308, 2, 546},
|
|
{"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 309, 2, 548},
|
|
{"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 310, 2, 550},
|
|
{"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 311, 2, 552},
|
|
{"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 312, 17, 554},
|
|
{"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 313, 2, 571},
|
|
{"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 314, 1, 573},
|
|
{"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 315, 10, 574},
|
|
{"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 316, 6, 584},
|
|
{"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 317, 6, 590},
|
|
{"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 318, 2, 596},
|
|
{"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 319, 2, 598},
|
|
{"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 320, 2, 600},
|
|
{"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 321, 3, 602},
|
|
{"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 325, 2, 605},
|
|
{"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 329, 6, 607},
|
|
{"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 330, 5, 613},
|
|
{"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 331, 6, 618},
|
|
{"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 332, 7, 624},
|
|
{"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 333, 2, 631},
|
|
{"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 341, 2, 633},
|
|
{"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 342, 3, 635},
|
|
{"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 343, 5, 638},
|
|
{"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 351, 3, 643},
|
|
{"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 352, 2, 646},
|
|
{"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 353, 2, 648},
|
|
{"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 354, 2, 650},
|
|
{"cvmx_l2c_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 355, 7, 652},
|
|
{"cvmx_l2c_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 356, 6, 659},
|
|
{"cvmx_l2c_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 357, 8, 665},
|
|
{"cvmx_l2c_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 358, 9, 673},
|
|
{"cvmx_l2c_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 359, 10, 682},
|
|
{"cvmx_l2c_dut" , CVMX_CSR_DB_TYPE_RSL, 64, 360, 5, 692},
|
|
{"cvmx_l2c_lckbase" , CVMX_CSR_DB_TYPE_RSL, 64, 361, 4, 697},
|
|
{"cvmx_l2c_lckoff" , CVMX_CSR_DB_TYPE_RSL, 64, 362, 2, 701},
|
|
{"cvmx_l2c_lfb0" , CVMX_CSR_DB_TYPE_RSL, 64, 363, 17, 703},
|
|
{"cvmx_l2c_lfb1" , CVMX_CSR_DB_TYPE_RSL, 64, 364, 19, 720},
|
|
{"cvmx_l2c_lfb2" , CVMX_CSR_DB_TYPE_RSL, 64, 365, 3, 739},
|
|
{"cvmx_l2c_lfb3" , CVMX_CSR_DB_TYPE_RSL, 64, 366, 4, 742},
|
|
{"cvmx_l2c_pfc#" , CVMX_CSR_DB_TYPE_RSL, 64, 367, 2, 746},
|
|
{"cvmx_l2c_pfctl" , CVMX_CSR_DB_TYPE_RSL, 64, 371, 17, 748},
|
|
{"cvmx_l2c_spar0" , CVMX_CSR_DB_TYPE_RSL, 64, 372, 2, 765},
|
|
{"cvmx_l2c_spar4" , CVMX_CSR_DB_TYPE_RSL, 64, 373, 2, 767},
|
|
{"cvmx_l2d_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 374, 3, 769},
|
|
{"cvmx_l2d_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 375, 2, 772},
|
|
{"cvmx_l2d_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 376, 2, 774},
|
|
{"cvmx_l2d_bst3" , CVMX_CSR_DB_TYPE_RSL, 64, 377, 2, 776},
|
|
{"cvmx_l2d_err" , CVMX_CSR_DB_TYPE_RSL, 64, 378, 7, 778},
|
|
{"cvmx_l2d_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 379, 6, 785},
|
|
{"cvmx_l2d_fsyn0" , CVMX_CSR_DB_TYPE_RSL, 64, 380, 3, 791},
|
|
{"cvmx_l2d_fsyn1" , CVMX_CSR_DB_TYPE_RSL, 64, 381, 3, 794},
|
|
{"cvmx_l2d_fus0" , CVMX_CSR_DB_TYPE_RSL, 64, 382, 2, 797},
|
|
{"cvmx_l2d_fus1" , CVMX_CSR_DB_TYPE_RSL, 64, 383, 2, 799},
|
|
{"cvmx_l2d_fus2" , CVMX_CSR_DB_TYPE_RSL, 64, 384, 2, 801},
|
|
{"cvmx_l2d_fus3" , CVMX_CSR_DB_TYPE_RSL, 64, 385, 3, 803},
|
|
{"cvmx_l2t_err" , CVMX_CSR_DB_TYPE_RSL, 64, 386, 15, 806},
|
|
{"cvmx_lmc#_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 387, 9, 821},
|
|
{"cvmx_lmc#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 388, 20, 830},
|
|
{"cvmx_lmc#_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 389, 2, 850},
|
|
{"cvmx_lmc#_dclk_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 390, 2, 852},
|
|
{"cvmx_lmc#_dclk_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 391, 2, 854},
|
|
{"cvmx_lmc#_ddr2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 392, 18, 856},
|
|
{"cvmx_lmc#_delay_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 393, 4, 874},
|
|
{"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 394, 5, 878},
|
|
{"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 395, 6, 883},
|
|
{"cvmx_lmc#_ifb_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 396, 2, 889},
|
|
{"cvmx_lmc#_ifb_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 397, 2, 891},
|
|
{"cvmx_lmc#_mem_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 398, 14, 893},
|
|
{"cvmx_lmc#_mem_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 399, 10, 907},
|
|
{"cvmx_lmc#_ops_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 400, 2, 917},
|
|
{"cvmx_lmc#_ops_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 401, 2, 919},
|
|
{"cvmx_lmc#_pll_bwctl" , CVMX_CSR_DB_TYPE_RSL, 64, 402, 3, 921},
|
|
{"cvmx_lmc#_rodt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 403, 9, 924},
|
|
{"cvmx_lmc#_wodt_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 404, 5, 933},
|
|
{"cvmx_lmc#_wodt_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 405, 5, 938},
|
|
{"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 406, 5, 943},
|
|
{"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 407, 3, 948},
|
|
{"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 408, 3, 951},
|
|
{"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 409, 3, 954},
|
|
{"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 410, 5, 957},
|
|
{"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 412, 1, 962},
|
|
{"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 413, 10, 963},
|
|
{"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 421, 13, 973},
|
|
{"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 429, 4, 986},
|
|
{"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 430, 2, 990},
|
|
{"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 431, 2, 992},
|
|
{"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 432, 10, 994},
|
|
{"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 433, 9, 1004},
|
|
{"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 434, 2, 1013},
|
|
{"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 435, 8, 1015},
|
|
{"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 436, 4, 1023},
|
|
{"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 437, 2, 1027},
|
|
{"cvmx_mio_fus_unlock" , CVMX_CSR_DB_TYPE_RSL, 64, 438, 2, 1029},
|
|
{"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 439, 2, 1031},
|
|
{"cvmx_mio_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 440, 2, 1033},
|
|
{"cvmx_mio_pll_setting" , CVMX_CSR_DB_TYPE_RSL, 64, 441, 2, 1035},
|
|
{"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 442, 13, 1037},
|
|
{"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 443, 12, 1050},
|
|
{"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 444, 3, 1062},
|
|
{"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 445, 3, 1065},
|
|
{"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 446, 2, 1068},
|
|
{"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 448, 2, 1070},
|
|
{"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 450, 2, 1072},
|
|
{"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 452, 7, 1074},
|
|
{"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 454, 2, 1081},
|
|
{"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 456, 7, 1083},
|
|
{"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 458, 4, 1090},
|
|
{"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 460, 8, 1094},
|
|
{"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 462, 9, 1102},
|
|
{"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 464, 7, 1111},
|
|
{"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 466, 9, 1118},
|
|
{"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 468, 2, 1127},
|
|
{"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 470, 2, 1129},
|
|
{"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 472, 4, 1131},
|
|
{"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 474, 2, 1135},
|
|
{"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 476, 2, 1137},
|
|
{"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 478, 2, 1139},
|
|
{"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 480, 4, 1141},
|
|
{"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 482, 2, 1145},
|
|
{"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 484, 2, 1147},
|
|
{"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 486, 2, 1149},
|
|
{"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 488, 2, 1151},
|
|
{"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 490, 2, 1153},
|
|
{"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 492, 2, 1155},
|
|
{"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 494, 6, 1157},
|
|
{"cvmx_mpi_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 496, 14, 1163},
|
|
{"cvmx_mpi_dat#" , CVMX_CSR_DB_TYPE_NCB, 64, 497, 2, 1177},
|
|
{"cvmx_mpi_sts" , CVMX_CSR_DB_TYPE_NCB, 64, 506, 4, 1179},
|
|
{"cvmx_mpi_tx" , CVMX_CSR_DB_TYPE_NCB, 64, 507, 6, 1183},
|
|
{"cvmx_npi_base_addr_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 508, 2, 1189},
|
|
{"cvmx_npi_base_addr_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 509, 2, 1191},
|
|
{"cvmx_npi_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 510, 19, 1193},
|
|
{"cvmx_npi_buff_size_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 511, 3, 1212},
|
|
{"cvmx_npi_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 512, 15, 1215},
|
|
{"cvmx_npi_dbg_select" , CVMX_CSR_DB_TYPE_NCB, 64, 513, 2, 1230},
|
|
{"cvmx_npi_dma_control" , CVMX_CSR_DB_TYPE_NCB, 64, 514, 13, 1232},
|
|
{"cvmx_npi_dma_highp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 515, 3, 1245},
|
|
{"cvmx_npi_dma_highp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 516, 3, 1248},
|
|
{"cvmx_npi_dma_lowp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 517, 3, 1251},
|
|
{"cvmx_npi_dma_lowp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 518, 3, 1254},
|
|
{"cvmx_npi_highp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 519, 2, 1257},
|
|
{"cvmx_npi_highp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 520, 2, 1259},
|
|
{"cvmx_npi_input_control" , CVMX_CSR_DB_TYPE_NCB, 64, 521, 9, 1261},
|
|
{"cvmx_npi_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 522, 45, 1270},
|
|
{"cvmx_npi_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 523, 45, 1315},
|
|
{"cvmx_npi_lowp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 524, 2, 1360},
|
|
{"cvmx_npi_lowp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 525, 2, 1362},
|
|
{"cvmx_npi_mem_access_subid#" , CVMX_CSR_DB_TYPE_NCB, 64, 526, 10, 1364},
|
|
{"cvmx_npi_msi_rcv" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 530, 1, 1374},
|
|
{"cvmx_npi_num_desc_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 531, 2, 1375},
|
|
{"cvmx_npi_output_control" , CVMX_CSR_DB_TYPE_NCB, 64, 532, 14, 1377},
|
|
{"cvmx_npi_p#_dbpair_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 533, 3, 1391},
|
|
{"cvmx_npi_p#_instr_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 534, 2, 1394},
|
|
{"cvmx_npi_p#_instr_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 535, 3, 1396},
|
|
{"cvmx_npi_p#_pair_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 536, 3, 1399},
|
|
{"cvmx_npi_pci_burst_size" , CVMX_CSR_DB_TYPE_NCB, 64, 537, 3, 1402},
|
|
{"cvmx_npi_pci_int_arb_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 538, 4, 1405},
|
|
{"cvmx_npi_pci_read_cmd" , CVMX_CSR_DB_TYPE_NCB, 64, 539, 2, 1409},
|
|
{"cvmx_npi_port32_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 540, 13, 1411},
|
|
{"cvmx_npi_port_bp_control" , CVMX_CSR_DB_TYPE_NCB, 64, 541, 3, 1424},
|
|
{"cvmx_npi_rsl_int_blocks" , CVMX_CSR_DB_TYPE_NCB, 64, 542, 33, 1427},
|
|
{"cvmx_npi_size_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 543, 2, 1460},
|
|
{"cvmx_npi_win_read_to" , CVMX_CSR_DB_TYPE_NCB, 64, 544, 2, 1462},
|
|
{"cvmx_pci_bar1_index#" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 545, 5, 1464},
|
|
{"cvmx_pci_cfg00" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 577, 2, 1469},
|
|
{"cvmx_pci_cfg01" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 578, 24, 1471},
|
|
{"cvmx_pci_cfg02" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 579, 2, 1495},
|
|
{"cvmx_pci_cfg03" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 580, 7, 1497},
|
|
{"cvmx_pci_cfg04" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 581, 5, 1504},
|
|
{"cvmx_pci_cfg05" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 582, 1, 1509},
|
|
{"cvmx_pci_cfg06" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 583, 5, 1510},
|
|
{"cvmx_pci_cfg07" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 584, 1, 1515},
|
|
{"cvmx_pci_cfg08" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 585, 4, 1516},
|
|
{"cvmx_pci_cfg09" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 586, 2, 1520},
|
|
{"cvmx_pci_cfg10" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 587, 1, 1522},
|
|
{"cvmx_pci_cfg11" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 588, 2, 1523},
|
|
{"cvmx_pci_cfg12" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 589, 4, 1525},
|
|
{"cvmx_pci_cfg13" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 590, 2, 1529},
|
|
{"cvmx_pci_cfg15" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 591, 4, 1531},
|
|
{"cvmx_pci_cfg16" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 592, 16, 1535},
|
|
{"cvmx_pci_cfg17" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 593, 1, 1551},
|
|
{"cvmx_pci_cfg18" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 594, 1, 1552},
|
|
{"cvmx_pci_cfg19" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 595, 18, 1553},
|
|
{"cvmx_pci_cfg20" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 596, 1, 1571},
|
|
{"cvmx_pci_cfg21" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 597, 1, 1572},
|
|
{"cvmx_pci_cfg22" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 598, 7, 1573},
|
|
{"cvmx_pci_cfg56" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 599, 7, 1580},
|
|
{"cvmx_pci_cfg57" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 600, 13, 1587},
|
|
{"cvmx_pci_cfg58" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 601, 10, 1600},
|
|
{"cvmx_pci_cfg59" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 602, 10, 1610},
|
|
{"cvmx_pci_cfg60" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 603, 7, 1620},
|
|
{"cvmx_pci_cfg61" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 604, 2, 1627},
|
|
{"cvmx_pci_cfg62" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 605, 1, 1629},
|
|
{"cvmx_pci_cfg63" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 606, 2, 1630},
|
|
{"cvmx_pci_ctl_status_2" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 607, 22, 1632},
|
|
{"cvmx_pci_dbell#" , CVMX_CSR_DB_TYPE_PCI, 32, 608, 2, 1654},
|
|
{"cvmx_pci_dma_cnt#" , CVMX_CSR_DB_TYPE_PCI, 32, 609, 1, 1656},
|
|
{"cvmx_pci_dma_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 611, 1, 1657},
|
|
{"cvmx_pci_dma_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 613, 1, 1658},
|
|
{"cvmx_pci_instr_count#" , CVMX_CSR_DB_TYPE_PCI, 32, 615, 1, 1659},
|
|
{"cvmx_pci_int_enb" , CVMX_CSR_DB_TYPE_PCI, 64, 616, 31, 1660},
|
|
{"cvmx_pci_int_enb2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 617, 31, 1691},
|
|
{"cvmx_pci_int_sum" , CVMX_CSR_DB_TYPE_PCI, 64, 618, 31, 1722},
|
|
{"cvmx_pci_int_sum2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 619, 31, 1753},
|
|
{"cvmx_pci_msi_rcv" , CVMX_CSR_DB_TYPE_PCI, 32, 620, 2, 1784},
|
|
{"cvmx_pci_pkt_credits#" , CVMX_CSR_DB_TYPE_PCI, 32, 621, 2, 1786},
|
|
{"cvmx_pci_pkts_sent#" , CVMX_CSR_DB_TYPE_PCI, 32, 622, 1, 1788},
|
|
{"cvmx_pci_pkts_sent_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 623, 1, 1789},
|
|
{"cvmx_pci_pkts_sent_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 624, 1, 1790},
|
|
{"cvmx_pci_read_cmd_6" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 625, 3, 1791},
|
|
{"cvmx_pci_read_cmd_c" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 626, 3, 1794},
|
|
{"cvmx_pci_read_cmd_e" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 627, 3, 1797},
|
|
{"cvmx_pci_read_timeout" , CVMX_CSR_DB_TYPE_NCB, 64, 628, 3, 1800},
|
|
{"cvmx_pci_scm_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 629, 2, 1803},
|
|
{"cvmx_pci_tsr_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 630, 2, 1805},
|
|
{"cvmx_pci_win_rd_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 631, 4, 1807},
|
|
{"cvmx_pci_win_rd_data" , CVMX_CSR_DB_TYPE_PCI, 64, 632, 1, 1811},
|
|
{"cvmx_pci_win_wr_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 633, 4, 1812},
|
|
{"cvmx_pci_win_wr_data" , CVMX_CSR_DB_TYPE_PCI, 64, 634, 1, 1816},
|
|
{"cvmx_pci_win_wr_mask" , CVMX_CSR_DB_TYPE_PCI, 64, 635, 2, 1817},
|
|
{"cvmx_pcm#_dma_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 636, 12, 1819},
|
|
{"cvmx_pcm#_int_ena" , CVMX_CSR_DB_TYPE_NCB, 64, 640, 9, 1831},
|
|
{"cvmx_pcm#_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 644, 9, 1840},
|
|
{"cvmx_pcm#_rxaddr" , CVMX_CSR_DB_TYPE_NCB, 64, 648, 2, 1849},
|
|
{"cvmx_pcm#_rxcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 652, 2, 1851},
|
|
{"cvmx_pcm#_rxmsk0" , CVMX_CSR_DB_TYPE_NCB, 64, 656, 1, 1853},
|
|
{"cvmx_pcm#_rxmsk1" , CVMX_CSR_DB_TYPE_NCB, 64, 660, 1, 1854},
|
|
{"cvmx_pcm#_rxmsk2" , CVMX_CSR_DB_TYPE_NCB, 64, 664, 1, 1855},
|
|
{"cvmx_pcm#_rxmsk3" , CVMX_CSR_DB_TYPE_NCB, 64, 668, 1, 1856},
|
|
{"cvmx_pcm#_rxmsk4" , CVMX_CSR_DB_TYPE_NCB, 64, 672, 1, 1857},
|
|
{"cvmx_pcm#_rxmsk5" , CVMX_CSR_DB_TYPE_NCB, 64, 676, 1, 1858},
|
|
{"cvmx_pcm#_rxmsk6" , CVMX_CSR_DB_TYPE_NCB, 64, 680, 1, 1859},
|
|
{"cvmx_pcm#_rxmsk7" , CVMX_CSR_DB_TYPE_NCB, 64, 684, 1, 1860},
|
|
{"cvmx_pcm#_rxstart" , CVMX_CSR_DB_TYPE_NCB, 64, 688, 3, 1861},
|
|
{"cvmx_pcm#_tdm_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 692, 6, 1864},
|
|
{"cvmx_pcm#_tdm_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 696, 1, 1870},
|
|
{"cvmx_pcm#_txaddr" , CVMX_CSR_DB_TYPE_NCB, 64, 700, 3, 1871},
|
|
{"cvmx_pcm#_txcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 704, 2, 1874},
|
|
{"cvmx_pcm#_txmsk0" , CVMX_CSR_DB_TYPE_NCB, 64, 708, 1, 1876},
|
|
{"cvmx_pcm#_txmsk1" , CVMX_CSR_DB_TYPE_NCB, 64, 712, 1, 1877},
|
|
{"cvmx_pcm#_txmsk2" , CVMX_CSR_DB_TYPE_NCB, 64, 716, 1, 1878},
|
|
{"cvmx_pcm#_txmsk3" , CVMX_CSR_DB_TYPE_NCB, 64, 720, 1, 1879},
|
|
{"cvmx_pcm#_txmsk4" , CVMX_CSR_DB_TYPE_NCB, 64, 724, 1, 1880},
|
|
{"cvmx_pcm#_txmsk5" , CVMX_CSR_DB_TYPE_NCB, 64, 728, 1, 1881},
|
|
{"cvmx_pcm#_txmsk6" , CVMX_CSR_DB_TYPE_NCB, 64, 732, 1, 1882},
|
|
{"cvmx_pcm#_txmsk7" , CVMX_CSR_DB_TYPE_NCB, 64, 736, 1, 1883},
|
|
{"cvmx_pcm#_txstart" , CVMX_CSR_DB_TYPE_NCB, 64, 740, 3, 1884},
|
|
{"cvmx_pcm_clk#_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 744, 12, 1887},
|
|
{"cvmx_pcm_clk#_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 746, 1, 1899},
|
|
{"cvmx_pcm_clk#_gen" , CVMX_CSR_DB_TYPE_NCB, 64, 748, 3, 1900},
|
|
{"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 750, 2, 1903},
|
|
{"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 751, 4, 1905},
|
|
{"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 755, 8, 1909},
|
|
{"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 756, 16, 1917},
|
|
{"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 757, 10, 1933},
|
|
{"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 758, 10, 1943},
|
|
{"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 759, 2, 1953},
|
|
{"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 760, 16, 1955},
|
|
{"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 765, 25, 1971},
|
|
{"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 770, 2, 1996},
|
|
{"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 834, 2, 1998},
|
|
{"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 842, 9, 2000},
|
|
{"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 846, 2, 2009},
|
|
{"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 847, 2, 2011},
|
|
{"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 848, 2, 2013},
|
|
{"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 853, 2, 2015},
|
|
{"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 858, 2, 2017},
|
|
{"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 863, 2, 2019},
|
|
{"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 868, 2, 2021},
|
|
{"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 873, 2, 2023},
|
|
{"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 878, 2, 2025},
|
|
{"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 883, 2, 2027},
|
|
{"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 888, 2, 2029},
|
|
{"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 893, 2, 2031},
|
|
{"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 898, 2, 2033},
|
|
{"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 899, 2, 2035},
|
|
{"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 904, 2, 2037},
|
|
{"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 909, 2, 2039},
|
|
{"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 914, 2, 2041},
|
|
{"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 978, 2, 2043},
|
|
{"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 979, 3, 2045},
|
|
{"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 980, 3, 2048},
|
|
{"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 981, 2, 2051},
|
|
{"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 982, 2, 2053},
|
|
{"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 983, 4, 2055},
|
|
{"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 984, 5, 2059},
|
|
{"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 985, 4, 2064},
|
|
{"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 986, 5, 2068},
|
|
{"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 987, 1, 2073},
|
|
{"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 988, 4, 2074},
|
|
{"cvmx_pko_mem_debug14" , CVMX_CSR_DB_TYPE_RSL, 64, 989, 2, 2078},
|
|
{"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 990, 5, 2080},
|
|
{"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 991, 5, 2085},
|
|
{"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 992, 1, 2090},
|
|
{"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 993, 19, 2091},
|
|
{"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 994, 7, 2110},
|
|
{"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 995, 4, 2117},
|
|
{"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 996, 6, 2121},
|
|
{"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 997, 6, 2127},
|
|
{"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 998, 9, 2133},
|
|
{"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 999, 5, 2142},
|
|
{"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1000, 13, 2147},
|
|
{"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 1001, 4, 2160},
|
|
{"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1002, 2, 2164},
|
|
{"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 1003, 3, 2166},
|
|
{"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 1004, 5, 2169},
|
|
{"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 1005, 3, 2174},
|
|
{"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1006, 3, 2177},
|
|
{"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 1007, 2, 2180},
|
|
{"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 1008, 3, 2182},
|
|
{"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 1009, 12, 2185},
|
|
{"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1010, 2, 2197},
|
|
{"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 1011, 13, 2199},
|
|
{"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1012, 3, 2212},
|
|
{"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 1013, 2, 2215},
|
|
{"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1021, 2, 2217},
|
|
{"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1022, 2, 2219},
|
|
{"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 1023, 2, 2221},
|
|
{"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 1024, 2, 2223},
|
|
{"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 1025, 5, 2225},
|
|
{"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 1033, 10, 2230},
|
|
{"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1041, 2, 2240},
|
|
{"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1042, 2, 2242},
|
|
{"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 1043, 2, 2244},
|
|
{"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 1051, 3, 2246},
|
|
{"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 1052, 6, 2249},
|
|
{"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1068, 5, 2255},
|
|
{"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 1069, 7, 2260},
|
|
{"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 1085, 2, 2267},
|
|
{"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1101, 3, 2269},
|
|
{"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1102, 5, 2272},
|
|
{"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 1103, 8, 2277},
|
|
{"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1104, 6, 2285},
|
|
{"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1105, 2, 2291},
|
|
{"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1106, 4, 2293},
|
|
{"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1107, 4, 2297},
|
|
{"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1108, 6, 2301},
|
|
{"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 1109, 3, 2307},
|
|
{"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 1110, 5, 2310},
|
|
{"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 1111, 4, 2315},
|
|
{"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 1112, 6, 2319},
|
|
{"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1113, 4, 2325},
|
|
{"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 1114, 2, 2329},
|
|
{"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 1115, 4, 2331},
|
|
{"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1116, 2, 2335},
|
|
{"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 1117, 3, 2337},
|
|
{"cvmx_usbc#_daint" , CVMX_CSR_DB_TYPE_NCB, 32, 1118, 2, 2340},
|
|
{"cvmx_usbc#_daintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1119, 2, 2342},
|
|
{"cvmx_usbc#_dcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1120, 8, 2344},
|
|
{"cvmx_usbc#_dctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1121, 11, 2352},
|
|
{"cvmx_usbc#_diepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 1122, 15, 2363},
|
|
{"cvmx_usbc#_diepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1127, 8, 2378},
|
|
{"cvmx_usbc#_diepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1132, 8, 2386},
|
|
{"cvmx_usbc#_dieptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1133, 4, 2394},
|
|
{"cvmx_usbc#_doepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 1138, 15, 2398},
|
|
{"cvmx_usbc#_doepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1143, 6, 2413},
|
|
{"cvmx_usbc#_doepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1148, 6, 2419},
|
|
{"cvmx_usbc#_doeptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1149, 4, 2425},
|
|
{"cvmx_usbc#_dptxfsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1154, 2, 2429},
|
|
{"cvmx_usbc#_dsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1158, 6, 2431},
|
|
{"cvmx_usbc#_dtknqr1" , CVMX_CSR_DB_TYPE_NCB, 32, 1159, 4, 2437},
|
|
{"cvmx_usbc#_dtknqr2" , CVMX_CSR_DB_TYPE_NCB, 32, 1160, 1, 2441},
|
|
{"cvmx_usbc#_dtknqr3" , CVMX_CSR_DB_TYPE_NCB, 32, 1161, 1, 2442},
|
|
{"cvmx_usbc#_dtknqr4" , CVMX_CSR_DB_TYPE_NCB, 32, 1162, 1, 2443},
|
|
{"cvmx_usbc#_gahbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1163, 7, 2444},
|
|
{"cvmx_usbc#_ghwcfg1" , CVMX_CSR_DB_TYPE_NCB, 32, 1164, 1, 2451},
|
|
{"cvmx_usbc#_ghwcfg2" , CVMX_CSR_DB_TYPE_NCB, 32, 1165, 14, 2452},
|
|
{"cvmx_usbc#_ghwcfg3" , CVMX_CSR_DB_TYPE_NCB, 32, 1166, 10, 2466},
|
|
{"cvmx_usbc#_ghwcfg4" , CVMX_CSR_DB_TYPE_NCB, 32, 1167, 12, 2476},
|
|
{"cvmx_usbc#_gintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1168, 32, 2488},
|
|
{"cvmx_usbc#_gintsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1169, 32, 2520},
|
|
{"cvmx_usbc#_gnptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1170, 2, 2552},
|
|
{"cvmx_usbc#_gnptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1171, 4, 2554},
|
|
{"cvmx_usbc#_gotgctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1172, 13, 2558},
|
|
{"cvmx_usbc#_gotgint" , CVMX_CSR_DB_TYPE_NCB, 32, 1173, 10, 2571},
|
|
{"cvmx_usbc#_grstctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1174, 10, 2581},
|
|
{"cvmx_usbc#_grxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1175, 2, 2591},
|
|
{"cvmx_usbc#_grxstspd" , CVMX_CSR_DB_TYPE_NCB, 32, 1176, 6, 2593},
|
|
{"cvmx_usbc#_grxstsph" , CVMX_CSR_DB_TYPE_NCB, 32, 1177, 5, 2599},
|
|
{"cvmx_usbc#_grxstsrd" , CVMX_CSR_DB_TYPE_NCB, 32, 1178, 6, 2604},
|
|
{"cvmx_usbc#_grxstsrh" , CVMX_CSR_DB_TYPE_NCB, 32, 1179, 5, 2610},
|
|
{"cvmx_usbc#_gsnpsid" , CVMX_CSR_DB_TYPE_NCB, 32, 1180, 1, 2615},
|
|
{"cvmx_usbc#_gusbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1181, 13, 2616},
|
|
{"cvmx_usbc#_haint" , CVMX_CSR_DB_TYPE_NCB, 32, 1182, 2, 2629},
|
|
{"cvmx_usbc#_haintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1183, 2, 2631},
|
|
{"cvmx_usbc#_hcchar#" , CVMX_CSR_DB_TYPE_NCB, 32, 1184, 11, 2633},
|
|
{"cvmx_usbc#_hcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1192, 3, 2644},
|
|
{"cvmx_usbc#_hcint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1193, 12, 2647},
|
|
{"cvmx_usbc#_hcintmsk#" , CVMX_CSR_DB_TYPE_NCB, 32, 1201, 12, 2659},
|
|
{"cvmx_usbc#_hcsplt#" , CVMX_CSR_DB_TYPE_NCB, 32, 1209, 6, 2671},
|
|
{"cvmx_usbc#_hctsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1217, 4, 2677},
|
|
{"cvmx_usbc#_hfir" , CVMX_CSR_DB_TYPE_NCB, 32, 1225, 2, 2681},
|
|
{"cvmx_usbc#_hfnum" , CVMX_CSR_DB_TYPE_NCB, 32, 1226, 2, 2683},
|
|
{"cvmx_usbc#_hprt" , CVMX_CSR_DB_TYPE_NCB, 32, 1227, 15, 2685},
|
|
{"cvmx_usbc#_hptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1228, 2, 2700},
|
|
{"cvmx_usbc#_hptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1229, 3, 2702},
|
|
{"cvmx_usbc#_nptxdfifo#" , CVMX_CSR_DB_TYPE_NCB, 32, 1230, 1, 2705},
|
|
{"cvmx_usbc#_pcgcctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1238, 6, 2706},
|
|
{"cvmx_usbn#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1239, 4, 2712},
|
|
{"cvmx_usbn#_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1240, 15, 2716},
|
|
{"cvmx_usbn#_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1241, 6, 2731},
|
|
{"cvmx_usbn#_dma0_inb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 1242, 2, 2737},
|
|
{"cvmx_usbn#_dma0_inb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 1243, 2, 2739},
|
|
{"cvmx_usbn#_dma0_inb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 1244, 2, 2741},
|
|
{"cvmx_usbn#_dma0_inb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 1245, 2, 2743},
|
|
{"cvmx_usbn#_dma0_inb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 1246, 2, 2745},
|
|
{"cvmx_usbn#_dma0_inb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 1247, 2, 2747},
|
|
{"cvmx_usbn#_dma0_inb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 1248, 2, 2749},
|
|
{"cvmx_usbn#_dma0_inb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 1249, 2, 2751},
|
|
{"cvmx_usbn#_dma0_outb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 1250, 2, 2753},
|
|
{"cvmx_usbn#_dma0_outb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 1251, 2, 2755},
|
|
{"cvmx_usbn#_dma0_outb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 1252, 2, 2757},
|
|
{"cvmx_usbn#_dma0_outb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 1253, 2, 2759},
|
|
{"cvmx_usbn#_dma0_outb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 1254, 2, 2761},
|
|
{"cvmx_usbn#_dma0_outb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 1255, 2, 2763},
|
|
{"cvmx_usbn#_dma0_outb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 1256, 2, 2765},
|
|
{"cvmx_usbn#_dma0_outb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 1257, 2, 2767},
|
|
{"cvmx_usbn#_dma_test" , CVMX_CSR_DB_TYPE_NCB, 64, 1258, 7, 2769},
|
|
{"cvmx_usbn#_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1259, 39, 2776},
|
|
{"cvmx_usbn#_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1260, 39, 2815},
|
|
{"cvmx_usbn#_usbp_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1261, 22, 2854},
|
|
{NULL,0,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn30xx[] = {
|
|
/* name , --------------address, ---------------type, bits, csr offset */
|
|
{"ASX0_GMII_RX_CLK_SET" , 0x11800B0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
|
|
{"ASX0_GMII_RX_DAT_SET" , 0x11800B0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
|
|
{"ASX0_INT_EN" , 0x11800B0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
|
|
{"ASX0_INT_REG" , 0x11800B0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
|
|
{"ASX0_MII_RX_DAT_SET" , 0x11800B0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
|
|
{"ASX0_PRT_LOOP" , 0x11800B0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
|
|
{"ASX0_RX_CLK_SET000" , 0x11800B0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
|
|
{"ASX0_RX_CLK_SET001" , 0x11800B0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
|
|
{"ASX0_RX_CLK_SET002" , 0x11800B0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
|
|
{"ASX0_RX_PRT_EN" , 0x11800B0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
|
|
{"ASX0_TX_CLK_SET000" , 0x11800B0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
|
|
{"ASX0_TX_CLK_SET001" , 0x11800B0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
|
|
{"ASX0_TX_CLK_SET002" , 0x11800B0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
|
|
{"ASX0_TX_COMP_BYP" , 0x11800B0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
|
|
{"ASX0_TX_HI_WATER000" , 0x11800B0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
|
|
{"ASX0_TX_HI_WATER001" , 0x11800B0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
|
|
{"ASX0_TX_HI_WATER002" , 0x11800B0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
|
|
{"ASX0_TX_PRT_EN" , 0x11800B0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
|
|
{"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 12},
|
|
{"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 13},
|
|
{"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 14},
|
|
{"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 15},
|
|
{"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
|
|
{"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
|
|
{"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
|
|
{"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
|
|
{"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
|
|
{"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
|
|
{"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 18},
|
|
{"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 18},
|
|
{"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 18},
|
|
{"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 19},
|
|
{"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
|
|
{"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 21},
|
|
{"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 22},
|
|
{"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 23},
|
|
{"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"DBG_DATA" , 0x11F00000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"FPA_BIST_STATUS" , 0x11800280000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
|
|
{"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 34},
|
|
{"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
|
|
{"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
|
|
{"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
|
|
{"FPA_QUE1_AVAILABLE" , 0x11800280000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
|
|
{"FPA_QUE2_AVAILABLE" , 0x11800280000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
|
|
{"FPA_QUE3_AVAILABLE" , 0x11800280000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
|
|
{"FPA_QUE4_AVAILABLE" , 0x11800280000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
|
|
{"FPA_QUE5_AVAILABLE" , 0x11800280000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
|
|
{"FPA_QUE6_AVAILABLE" , 0x11800280000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
|
|
{"FPA_QUE7_AVAILABLE" , 0x11800280000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
|
|
{"FPA_QUE0_PAGE_INDEX" , 0x11800280000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
|
|
{"FPA_QUE1_PAGE_INDEX" , 0x11800280000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
|
|
{"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
|
|
{"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
|
|
{"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
|
|
{"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
|
|
{"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
|
|
{"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
|
|
{"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
|
|
{"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
|
|
{"FPA_WART_CTL" , 0x11800280000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
|
|
{"FPA_WART_STATUS" , 0x11800280000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
|
|
{"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
|
|
{"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
|
|
{"GMX0_INF_MODE" , 0x11800080007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
|
|
{"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
|
|
{"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
|
|
{"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
|
|
{"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
|
|
{"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
|
|
{"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
|
|
{"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
|
|
{"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
|
|
{"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
|
|
{"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
|
|
{"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
|
|
{"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
|
|
{"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
|
|
{"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
|
|
{"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
|
|
{"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
|
|
{"GMX0_RX000_ADR_CAM4" , 0x11800080001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
|
|
{"GMX0_RX001_ADR_CAM4" , 0x11800080009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
|
|
{"GMX0_RX002_ADR_CAM4" , 0x11800080011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
|
|
{"GMX0_RX000_ADR_CAM5" , 0x11800080001A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
|
|
{"GMX0_RX001_ADR_CAM5" , 0x11800080009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
|
|
{"GMX0_RX002_ADR_CAM5" , 0x11800080011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
|
|
{"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
|
|
{"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
|
|
{"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
|
|
{"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
|
|
{"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
|
|
{"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
|
|
{"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
|
|
{"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
|
|
{"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
|
|
{"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
|
|
{"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
|
|
{"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
|
|
{"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
|
|
{"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
|
|
{"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
|
|
{"GMX0_RX000_FRM_MAX" , 0x1180008000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
|
|
{"GMX0_RX001_FRM_MAX" , 0x1180008000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
|
|
{"GMX0_RX002_FRM_MAX" , 0x1180008001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
|
|
{"GMX0_RX000_FRM_MIN" , 0x1180008000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
|
|
{"GMX0_RX001_FRM_MIN" , 0x1180008000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
|
|
{"GMX0_RX002_FRM_MIN" , 0x1180008001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
|
|
{"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
|
|
{"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
|
|
{"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
|
|
{"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
|
|
{"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
|
|
{"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
|
|
{"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
|
|
{"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
|
|
{"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
|
|
{"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
|
|
{"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
|
|
{"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
|
|
{"GMX0_RX000_RX_INBND" , 0x1180008000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
|
|
{"GMX0_RX001_RX_INBND" , 0x1180008000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
|
|
{"GMX0_RX002_RX_INBND" , 0x1180008001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
|
|
{"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
|
|
{"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
|
|
{"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
|
|
{"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
|
|
{"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
|
|
{"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
|
|
{"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
|
|
{"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
|
|
{"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
|
|
{"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
|
|
{"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
|
|
{"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
|
|
{"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
|
|
{"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
|
|
{"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
|
|
{"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
|
|
{"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
|
|
{"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
|
|
{"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
|
|
{"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
|
|
{"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
|
|
{"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
|
|
{"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
|
|
{"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
|
|
{"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
|
|
{"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
|
|
{"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
|
|
{"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
|
|
{"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
|
|
{"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
|
|
{"GMX0_RX_PRT_INFO" , 0x11800080004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
|
|
{"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
|
|
{"GMX0_RX_TX_STATUS" , 0x11800080007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX0_SMAC001" , 0x1180008000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX0_TX001_APPEND" , 0x1180008000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX0_TX001_BURST" , 0x1180008000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX0_TX000_CLK" , 0x1180008000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX0_TX001_CLK" , 0x1180008000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX0_TX002_CLK" , 0x1180008001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX0_TX001_CTL" , 0x1180008000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_TX001_MIN_PKT" , 0x1180008000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_TX001_PAUSE_TOGO" , 0x1180008000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_TX001_PAUSE_ZERO" , 0x1180008000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_TX001_SLOT" , 0x1180008000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_TX001_SOFT_PAUSE" , 0x1180008000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_TX001_STAT0" , 0x1180008000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_TX001_STAT1" , 0x1180008000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_TX001_STAT2" , 0x1180008000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_TX001_STAT3" , 0x1180008000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_TX000_STAT4" , 0x11800080002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_TX001_STAT4" , 0x1180008000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_TX002_STAT4" , 0x11800080012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_TX000_STAT5" , 0x11800080002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX0_TX001_STAT5" , 0x1180008000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX0_TX002_STAT5" , 0x11800080012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX0_TX000_STAT6" , 0x11800080002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX0_TX001_STAT6" , 0x1180008000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX0_TX002_STAT6" , 0x11800080012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX0_TX000_STAT7" , 0x11800080002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX0_TX001_STAT7" , 0x1180008000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX0_TX002_STAT7" , 0x11800080012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX0_TX000_STAT8" , 0x11800080002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_TX001_STAT8" , 0x1180008000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_TX002_STAT8" , 0x11800080012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_TX000_STAT9" , 0x11800080002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX0_TX001_STAT9" , 0x1180008000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX0_TX002_STAT9" , 0x11800080012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_TX001_STATS_CTL" , 0x1180008000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_TX001_THRESH" , 0x1180008000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_TX_BP" , 0x11800080004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX0_TX_CLK_MSK000" , 0x1180008000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_TX_CLK_MSK001" , 0x1180008000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX0_TX_CORRUPT" , 0x11800080004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX0_TX_LFSR" , 0x11800080004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_TX_OVR_BP" , 0x11800080004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
|
|
{"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
|
|
{"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
|
|
{"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
|
|
{"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
|
|
{"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
|
|
{"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
|
|
{"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
|
|
{"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
|
|
{"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
|
|
{"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
|
|
{"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
|
|
{"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
|
|
{"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
|
|
{"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
|
|
{"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 121},
|
|
{"GPIO_BOOT_ENA" , 0x10700000008A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 122},
|
|
{"GPIO_DBG_ENA" , 0x10700000008A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
|
|
{"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
|
|
{"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
|
|
{"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
|
|
{"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
|
|
{"GPIO_XBIT_CFG16" , 0x1070000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
|
|
{"GPIO_XBIT_CFG17" , 0x1070000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
|
|
{"GPIO_XBIT_CFG18" , 0x1070000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
|
|
{"GPIO_XBIT_CFG19" , 0x1070000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
|
|
{"GPIO_XBIT_CFG20" , 0x1070000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
|
|
{"GPIO_XBIT_CFG21" , 0x1070000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
|
|
{"GPIO_XBIT_CFG22" , 0x1070000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
|
|
{"GPIO_XBIT_CFG23" , 0x1070000000938ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
|
|
{"IOB_BIST_STATUS" , 0x11800F00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"IOB_CTL_STATUS" , 0x11800F0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"IOB_FAU_TIMEOUT" , 0x11800F0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"IOB_INB_CONTROL_MATCH" , 0x11800F0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"IOB_INB_CONTROL_MATCH_ENB" , 0x11800F0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"IOB_INB_DATA_MATCH" , 0x11800F0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"IOB_INB_DATA_MATCH_ENB" , 0x11800F0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"IOB_INT_ENB" , 0x11800F0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"IOB_INT_SUM" , 0x11800F0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"IOB_OUTB_CONTROL_MATCH" , 0x11800F0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800F00000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"IOB_OUTB_DATA_MATCH" , 0x11800F0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"IOB_OUTB_DATA_MATCH_ENB" , 0x11800F00000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"IOB_PKT_ERR" , 0x11800F0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"IPD_1ST_MBUFF_SKIP" , 0x14F0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 143},
|
|
{"IPD_1ST_NEXT_PTR_BACK" , 0x14F0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 144},
|
|
{"IPD_2ND_NEXT_PTR_BACK" , 0x14F0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
|
|
{"IPD_BIST_STATUS" , 0x14F00000007F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
|
|
{"IPD_BP_PRT_RED_END" , 0x14F0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
|
|
{"IPD_CLK_COUNT" , 0x14F0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
|
|
{"IPD_CTL_STATUS" , 0x14F0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
|
|
{"IPD_INT_ENB" , 0x14F0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
|
|
{"IPD_INT_SUM" , 0x14F0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
|
|
{"IPD_NOT_1ST_MBUFF_SKIP" , 0x14F0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
|
|
{"IPD_PACKET_MBUFF_SIZE" , 0x14F0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
|
|
{"IPD_PKT_PTR_VALID" , 0x14F0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
|
|
{"IPD_PORT0_BP_PAGE_CNT" , 0x14F0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
|
|
{"IPD_PORT1_BP_PAGE_CNT" , 0x14F0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
|
|
{"IPD_PORT2_BP_PAGE_CNT" , 0x14F0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
|
|
{"IPD_PORT32_BP_PAGE_CNT" , 0x14F0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14F00000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14F00000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14F00000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14F00000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
|
|
{"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14F0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
|
|
{"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14F0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
|
|
{"IPD_PTR_COUNT" , 0x14F0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
|
|
{"IPD_PWP_PTR_FIFO_CTL" , 0x14F0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
|
|
{"IPD_QOS0_RED_MARKS" , 0x14F0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"IPD_QOS1_RED_MARKS" , 0x14F0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"IPD_QOS2_RED_MARKS" , 0x14F0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"IPD_QOS3_RED_MARKS" , 0x14F0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"IPD_QOS4_RED_MARKS" , 0x14F0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"IPD_QOS5_RED_MARKS" , 0x14F00000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"IPD_QOS6_RED_MARKS" , 0x14F00000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"IPD_QOS7_RED_MARKS" , 0x14F00000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"IPD_QUE0_FREE_PAGE_CNT" , 0x14F0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
|
|
{"IPD_RED_PORT_ENABLE" , 0x14F00000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
|
|
{"IPD_RED_QUE0_PARAM" , 0x14F00000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
|
|
{"IPD_RED_QUE1_PARAM" , 0x14F00000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
|
|
{"IPD_RED_QUE2_PARAM" , 0x14F00000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
|
|
{"IPD_RED_QUE3_PARAM" , 0x14F00000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
|
|
{"IPD_RED_QUE4_PARAM" , 0x14F0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
|
|
{"IPD_RED_QUE5_PARAM" , 0x14F0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
|
|
{"IPD_RED_QUE6_PARAM" , 0x14F0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
|
|
{"IPD_RED_QUE7_PARAM" , 0x14F0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
|
|
{"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14F0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
|
|
{"IPD_SUB_PORT_FCS" , 0x14F0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
|
|
{"IPD_WQE_FPA_QUEUE" , 0x14F0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
|
|
{"IPD_WQE_PTR_VALID" , 0x14F0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
|
|
{"L2C_BST0" , 0x11800800007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"L2C_BST1" , 0x11800800007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"L2C_BST2" , 0x11800800007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"L2C_CFG" , 0x1180080000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"L2C_DBG" , 0x1180080000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"L2C_DUT" , 0x1180080000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"L2C_LCKBASE" , 0x1180080000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"L2C_LCKOFF" , 0x1180080000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"L2C_LFB0" , 0x1180080000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
|
|
{"L2C_LFB1" , 0x1180080000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
|
|
{"L2C_LFB2" , 0x1180080000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
|
|
{"L2C_LFB3" , 0x11800800000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
|
|
{"L2C_PFC0" , 0x1180080000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
|
|
{"L2C_PFC1" , 0x11800800000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
|
|
{"L2C_PFC2" , 0x11800800000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
|
|
{"L2C_PFC3" , 0x11800800000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
|
|
{"L2C_PFCTL" , 0x1180080000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
|
|
{"L2C_SPAR0" , 0x1180080000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
|
|
{"L2C_SPAR4" , 0x1180080000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
|
|
{"L2D_BST0" , 0x1180080000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
|
|
{"L2D_BST1" , 0x1180080000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
|
|
{"L2D_BST2" , 0x1180080000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
|
|
{"L2D_BST3" , 0x1180080000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
|
|
{"L2D_ERR" , 0x1180080000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
|
|
{"L2D_FADR" , 0x1180080000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
|
|
{"L2D_FSYN0" , 0x1180080000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 191},
|
|
{"L2D_FSYN1" , 0x1180080000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 192},
|
|
{"L2D_FUS0" , 0x11800800007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 193},
|
|
{"L2D_FUS1" , 0x11800800007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 194},
|
|
{"L2D_FUS2" , 0x11800800007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 195},
|
|
{"L2D_FUS3" , 0x11800800007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
|
|
{"L2T_ERR" , 0x1180080000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
|
|
{"LMC0_COMP_CTL" , 0x1180088000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
|
|
{"LMC0_CTL" , 0x1180088000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
|
|
{"LMC0_CTL1" , 0x1180088000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
|
|
{"LMC0_DCLK_CNT_HI" , 0x1180088000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
|
|
{"LMC0_DCLK_CNT_LO" , 0x1180088000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
|
|
{"LMC0_DDR2_CTL" , 0x1180088000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
|
|
{"LMC0_DELAY_CFG" , 0x1180088000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
|
|
{"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 205},
|
|
{"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 206},
|
|
{"LMC0_IFB_CNT_HI" , 0x1180088000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 207},
|
|
{"LMC0_IFB_CNT_LO" , 0x1180088000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 208},
|
|
{"LMC0_MEM_CFG0" , 0x1180088000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 209},
|
|
{"LMC0_MEM_CFG1" , 0x1180088000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 210},
|
|
{"LMC0_OPS_CNT_HI" , 0x1180088000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
|
|
{"LMC0_OPS_CNT_LO" , 0x1180088000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
|
|
{"LMC0_PLL_BWCTL" , 0x1180088000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
|
|
{"LMC0_RODT_CTL" , 0x1180088000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
|
|
{"LMC0_WODT_CTL0" , 0x1180088000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
|
|
{"LMC0_WODT_CTL1" , 0x1180088000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
|
|
{"MIO_BOOT_BIST_STAT" , 0x11800000000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
|
|
{"MIO_BOOT_ERR" , 0x11800000000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
|
|
{"MIO_BOOT_INT" , 0x11800000000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
|
|
{"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
|
|
{"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
|
|
{"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
|
|
{"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
|
|
{"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
|
|
{"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
|
|
{"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
|
|
{"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
|
|
{"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
|
|
{"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
|
|
{"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
|
|
{"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
|
|
{"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
|
|
{"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
|
|
{"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
|
|
{"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
|
|
{"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
|
|
{"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
|
|
{"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
|
|
{"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
|
|
{"MIO_BOOT_THR" , 0x11800000000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
|
|
{"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
|
|
{"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
|
|
{"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
|
|
{"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
|
|
{"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
|
|
{"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
|
|
{"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
|
|
{"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
|
|
{"MIO_FUS_UNLOCK" , 0x1180000001578ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
|
|
{"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
|
|
{"MIO_PLL_CTL" , 0x1180000001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
|
|
{"MIO_PLL_SETTING" , 0x1180000001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
|
|
{"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
|
|
{"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
|
|
{"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
|
|
{"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
|
|
{"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
|
|
{"MIO_UART1_DLH" , 0x1180000000C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
|
|
{"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
|
|
{"MIO_UART1_DLL" , 0x1180000000C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
|
|
{"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
|
|
{"MIO_UART1_FAR" , 0x1180000000D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
|
|
{"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
|
|
{"MIO_UART1_FCR" , 0x1180000000C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
|
|
{"MIO_UART0_HTX" , 0x1180000000B08ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
|
|
{"MIO_UART1_HTX" , 0x1180000000F08ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
|
|
{"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
|
|
{"MIO_UART1_IER" , 0x1180000000C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
|
|
{"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
|
|
{"MIO_UART1_IIR" , 0x1180000000C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
|
|
{"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
|
|
{"MIO_UART1_LCR" , 0x1180000000C18ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
|
|
{"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
|
|
{"MIO_UART1_LSR" , 0x1180000000C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
|
|
{"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
|
|
{"MIO_UART1_MCR" , 0x1180000000C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
|
|
{"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
|
|
{"MIO_UART1_MSR" , 0x1180000000C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
|
|
{"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
|
|
{"MIO_UART1_RBR" , 0x1180000000C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
|
|
{"MIO_UART0_RFL" , 0x1180000000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
|
|
{"MIO_UART1_RFL" , 0x1180000000E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
|
|
{"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
|
|
{"MIO_UART1_RFW" , 0x1180000000D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
|
|
{"MIO_UART0_SBCR" , 0x1180000000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
|
|
{"MIO_UART1_SBCR" , 0x1180000000E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
|
|
{"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
|
|
{"MIO_UART1_SCR" , 0x1180000000C38ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
|
|
{"MIO_UART0_SFE" , 0x1180000000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
|
|
{"MIO_UART1_SFE" , 0x1180000000E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
|
|
{"MIO_UART0_SRR" , 0x1180000000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
|
|
{"MIO_UART1_SRR" , 0x1180000000E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
|
|
{"MIO_UART0_SRT" , 0x1180000000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
|
|
{"MIO_UART1_SRT" , 0x1180000000E38ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
|
|
{"MIO_UART0_SRTS" , 0x1180000000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
|
|
{"MIO_UART1_SRTS" , 0x1180000000E18ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
|
|
{"MIO_UART0_STT" , 0x1180000000B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
|
|
{"MIO_UART1_STT" , 0x1180000000F00ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
|
|
{"MIO_UART0_TFL" , 0x1180000000A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
|
|
{"MIO_UART1_TFL" , 0x1180000000E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
|
|
{"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
|
|
{"MIO_UART1_TFR" , 0x1180000000D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
|
|
{"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
|
|
{"MIO_UART1_THR" , 0x1180000000C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
|
|
{"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
|
|
{"MIO_UART1_USR" , 0x1180000000D38ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
|
|
{"MPI_CFG" , 0x1070000001000ull, CVMX_CSR_DB_TYPE_NCB, 64, 267},
|
|
{"MPI_DAT0" , 0x1070000001080ull, CVMX_CSR_DB_TYPE_NCB, 64, 268},
|
|
{"MPI_DAT1" , 0x1070000001088ull, CVMX_CSR_DB_TYPE_NCB, 64, 268},
|
|
{"MPI_DAT2" , 0x1070000001090ull, CVMX_CSR_DB_TYPE_NCB, 64, 268},
|
|
{"MPI_DAT3" , 0x1070000001098ull, CVMX_CSR_DB_TYPE_NCB, 64, 268},
|
|
{"MPI_DAT4" , 0x10700000010A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 268},
|
|
{"MPI_DAT5" , 0x10700000010A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 268},
|
|
{"MPI_DAT6" , 0x10700000010B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 268},
|
|
{"MPI_DAT7" , 0x10700000010B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 268},
|
|
{"MPI_DAT8" , 0x10700000010C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 268},
|
|
{"MPI_STS" , 0x1070000001008ull, CVMX_CSR_DB_TYPE_NCB, 64, 269},
|
|
{"MPI_TX" , 0x1070000001010ull, CVMX_CSR_DB_TYPE_NCB, 64, 270},
|
|
{"NPI_BASE_ADDR_INPUT0" , 0x11F0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 271},
|
|
{"NPI_BASE_ADDR_OUTPUT0" , 0x11F00000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 272},
|
|
{"NPI_BIST_STATUS" , 0x11F00000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 273},
|
|
{"NPI_BUFF_SIZE_OUTPUT0" , 0x11F00000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 274},
|
|
{"NPI_CTL_STATUS" , 0x11F0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 275},
|
|
{"NPI_DBG_SELECT" , 0x11F0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
|
|
{"NPI_DMA_CONTROL" , 0x11F0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 277},
|
|
{"NPI_DMA_HIGHP_COUNTS" , 0x11F0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 278},
|
|
{"NPI_DMA_HIGHP_NADDR" , 0x11F0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 279},
|
|
{"NPI_DMA_LOWP_COUNTS" , 0x11F0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 280},
|
|
{"NPI_DMA_LOWP_NADDR" , 0x11F0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 281},
|
|
{"NPI_HIGHP_DBELL" , 0x11F0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 282},
|
|
{"NPI_HIGHP_IBUFF_SADDR" , 0x11F0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 283},
|
|
{"NPI_INPUT_CONTROL" , 0x11F0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 284},
|
|
{"NPI_INT_ENB" , 0x11F0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 285},
|
|
{"NPI_INT_SUM" , 0x11F0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
|
|
{"NPI_LOWP_DBELL" , 0x11F0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 287},
|
|
{"NPI_LOWP_IBUFF_SADDR" , 0x11F0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 288},
|
|
{"NPI_MEM_ACCESS_SUBID3" , 0x11F0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 289},
|
|
{"NPI_MEM_ACCESS_SUBID4" , 0x11F0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 289},
|
|
{"NPI_MEM_ACCESS_SUBID5" , 0x11F0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 289},
|
|
{"NPI_MEM_ACCESS_SUBID6" , 0x11F0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 289},
|
|
{"NPI_MSI_RCV" , 0x11F0000001190ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 290},
|
|
{"NPI_NUM_DESC_OUTPUT0" , 0x11F0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 291},
|
|
{"NPI_OUTPUT_CONTROL" , 0x11F0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
|
|
{"NPI_P0_DBPAIR_ADDR" , 0x11F0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 293},
|
|
{"NPI_P0_INSTR_ADDR" , 0x11F00000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 294},
|
|
{"NPI_P0_INSTR_CNTS" , 0x11F00000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
|
|
{"NPI_P0_PAIR_CNTS" , 0x11F0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 296},
|
|
{"NPI_PCI_BURST_SIZE" , 0x11F00000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 297},
|
|
{"NPI_PCI_INT_ARB_CFG" , 0x11F0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 298},
|
|
{"NPI_PCI_READ_CMD" , 0x11F0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 299},
|
|
{"NPI_PORT32_INSTR_HDR" , 0x11F00000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 300},
|
|
{"NPI_PORT_BP_CONTROL" , 0x11F00000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 301},
|
|
{"NPI_RSL_INT_BLOCKS" , 0x11F0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 302},
|
|
{"NPI_SIZE_INPUT0" , 0x11F0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 303},
|
|
{"NPI_WIN_READ_TO" , 0x11F00000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 304},
|
|
{"PCI_BAR1_INDEX0" , 0x11F0000001100ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX1" , 0x11F0000001104ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX2" , 0x11F0000001108ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX3" , 0x11F000000110Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX4" , 0x11F0000001110ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX5" , 0x11F0000001114ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX6" , 0x11F0000001118ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX7" , 0x11F000000111Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX8" , 0x11F0000001120ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX9" , 0x11F0000001124ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX10" , 0x11F0000001128ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX11" , 0x11F000000112Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX12" , 0x11F0000001130ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX13" , 0x11F0000001134ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX14" , 0x11F0000001138ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX15" , 0x11F000000113Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX16" , 0x11F0000001140ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX17" , 0x11F0000001144ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX18" , 0x11F0000001148ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX19" , 0x11F000000114Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX20" , 0x11F0000001150ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX21" , 0x11F0000001154ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX22" , 0x11F0000001158ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX23" , 0x11F000000115Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX24" , 0x11F0000001160ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX25" , 0x11F0000001164ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX26" , 0x11F0000001168ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX27" , 0x11F000000116Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX28" , 0x11F0000001170ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX29" , 0x11F0000001174ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX30" , 0x11F0000001178ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_BAR1_INDEX31" , 0x11F000000117Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 305},
|
|
{"PCI_CFG00" , 0x11F0000001800ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 306},
|
|
{"PCI_CFG01" , 0x11F0000001804ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 307},
|
|
{"PCI_CFG02" , 0x11F0000001808ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 308},
|
|
{"PCI_CFG03" , 0x11F000000180Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 309},
|
|
{"PCI_CFG04" , 0x11F0000001810ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 310},
|
|
{"PCI_CFG05" , 0x11F0000001814ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 311},
|
|
{"PCI_CFG06" , 0x11F0000001818ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 312},
|
|
{"PCI_CFG07" , 0x11F000000181Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 313},
|
|
{"PCI_CFG08" , 0x11F0000001820ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 314},
|
|
{"PCI_CFG09" , 0x11F0000001824ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 315},
|
|
{"PCI_CFG10" , 0x11F0000001828ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 316},
|
|
{"PCI_CFG11" , 0x11F000000182Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 317},
|
|
{"PCI_CFG12" , 0x11F0000001830ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 318},
|
|
{"PCI_CFG13" , 0x11F0000001834ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 319},
|
|
{"PCI_CFG15" , 0x11F000000183Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 320},
|
|
{"PCI_CFG16" , 0x11F0000001840ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 321},
|
|
{"PCI_CFG17" , 0x11F0000001844ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 322},
|
|
{"PCI_CFG18" , 0x11F0000001848ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 323},
|
|
{"PCI_CFG19" , 0x11F000000184Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 324},
|
|
{"PCI_CFG20" , 0x11F0000001850ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 325},
|
|
{"PCI_CFG21" , 0x11F0000001854ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 326},
|
|
{"PCI_CFG22" , 0x11F0000001858ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 327},
|
|
{"PCI_CFG56" , 0x11F00000018E0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 328},
|
|
{"PCI_CFG57" , 0x11F00000018E4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 329},
|
|
{"PCI_CFG58" , 0x11F00000018E8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 330},
|
|
{"PCI_CFG59" , 0x11F00000018ECull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 331},
|
|
{"PCI_CFG60" , 0x11F00000018F0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 332},
|
|
{"PCI_CFG61" , 0x11F00000018F4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 333},
|
|
{"PCI_CFG62" , 0x11F00000018F8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 334},
|
|
{"PCI_CFG63" , 0x11F00000018FCull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 335},
|
|
{"PCI_CTL_STATUS_2" , 0x11F000000118Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 336},
|
|
{"PCI_DBELL0" , 0x80ull, CVMX_CSR_DB_TYPE_PCI, 32, 337},
|
|
{"PCI_DMA_CNT0" , 0xA0ull, CVMX_CSR_DB_TYPE_PCI, 32, 338},
|
|
{"PCI_DMA_CNT1" , 0xA8ull, CVMX_CSR_DB_TYPE_PCI, 32, 338},
|
|
{"PCI_DMA_INT_LEV0" , 0xA4ull, CVMX_CSR_DB_TYPE_PCI, 32, 339},
|
|
{"PCI_DMA_INT_LEV1" , 0xACull, CVMX_CSR_DB_TYPE_PCI, 32, 339},
|
|
{"PCI_DMA_TIME0" , 0xB0ull, CVMX_CSR_DB_TYPE_PCI, 32, 340},
|
|
{"PCI_DMA_TIME1" , 0xB4ull, CVMX_CSR_DB_TYPE_PCI, 32, 340},
|
|
{"PCI_INSTR_COUNT0" , 0x84ull, CVMX_CSR_DB_TYPE_PCI, 32, 341},
|
|
{"PCI_INT_ENB" , 0x38ull, CVMX_CSR_DB_TYPE_PCI, 64, 342},
|
|
{"PCI_INT_ENB2" , 0x11F00000011A0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 343},
|
|
{"PCI_INT_SUM" , 0x30ull, CVMX_CSR_DB_TYPE_PCI, 64, 344},
|
|
{"PCI_INT_SUM2" , 0x11F0000001198ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 345},
|
|
{"PCI_MSI_RCV" , 0xF0ull, CVMX_CSR_DB_TYPE_PCI, 32, 346},
|
|
{"PCI_PKT_CREDITS0" , 0x44ull, CVMX_CSR_DB_TYPE_PCI, 32, 347},
|
|
{"PCI_PKTS_SENT0" , 0x40ull, CVMX_CSR_DB_TYPE_PCI, 32, 348},
|
|
{"PCI_PKTS_SENT_INT_LEV0" , 0x48ull, CVMX_CSR_DB_TYPE_PCI, 32, 349},
|
|
{"PCI_PKTS_SENT_TIME0" , 0x4Cull, CVMX_CSR_DB_TYPE_PCI, 32, 350},
|
|
{"PCI_READ_CMD_6" , 0x11F0000001180ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 351},
|
|
{"PCI_READ_CMD_C" , 0x11F0000001184ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 352},
|
|
{"PCI_READ_CMD_E" , 0x11F0000001188ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 353},
|
|
{"PCI_READ_TIMEOUT" , 0x11F00000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
|
|
{"PCI_SCM_REG" , 0x11F00000011A8ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 355},
|
|
{"PCI_TSR_REG" , 0x11F00000011B0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 356},
|
|
{"PCI_WIN_RD_ADDR" , 0x8ull, CVMX_CSR_DB_TYPE_PCI, 64, 357},
|
|
{"PCI_WIN_RD_DATA" , 0x20ull, CVMX_CSR_DB_TYPE_PCI, 64, 358},
|
|
{"PCI_WIN_WR_ADDR" , 0x0ull, CVMX_CSR_DB_TYPE_PCI, 64, 359},
|
|
{"PCI_WIN_WR_DATA" , 0x10ull, CVMX_CSR_DB_TYPE_PCI, 64, 360},
|
|
{"PCI_WIN_WR_MASK" , 0x18ull, CVMX_CSR_DB_TYPE_PCI, 64, 361},
|
|
{"PCM0_DMA_CFG" , 0x1070000010018ull, CVMX_CSR_DB_TYPE_NCB, 64, 362},
|
|
{"PCM1_DMA_CFG" , 0x1070000014018ull, CVMX_CSR_DB_TYPE_NCB, 64, 362},
|
|
{"PCM2_DMA_CFG" , 0x1070000018018ull, CVMX_CSR_DB_TYPE_NCB, 64, 362},
|
|
{"PCM3_DMA_CFG" , 0x107000001C018ull, CVMX_CSR_DB_TYPE_NCB, 64, 362},
|
|
{"PCM0_INT_ENA" , 0x1070000010020ull, CVMX_CSR_DB_TYPE_NCB, 64, 363},
|
|
{"PCM1_INT_ENA" , 0x1070000014020ull, CVMX_CSR_DB_TYPE_NCB, 64, 363},
|
|
{"PCM2_INT_ENA" , 0x1070000018020ull, CVMX_CSR_DB_TYPE_NCB, 64, 363},
|
|
{"PCM3_INT_ENA" , 0x107000001C020ull, CVMX_CSR_DB_TYPE_NCB, 64, 363},
|
|
{"PCM0_INT_SUM" , 0x1070000010028ull, CVMX_CSR_DB_TYPE_NCB, 64, 364},
|
|
{"PCM1_INT_SUM" , 0x1070000014028ull, CVMX_CSR_DB_TYPE_NCB, 64, 364},
|
|
{"PCM2_INT_SUM" , 0x1070000018028ull, CVMX_CSR_DB_TYPE_NCB, 64, 364},
|
|
{"PCM3_INT_SUM" , 0x107000001C028ull, CVMX_CSR_DB_TYPE_NCB, 64, 364},
|
|
{"PCM0_RXADDR" , 0x1070000010068ull, CVMX_CSR_DB_TYPE_NCB, 64, 365},
|
|
{"PCM1_RXADDR" , 0x1070000014068ull, CVMX_CSR_DB_TYPE_NCB, 64, 365},
|
|
{"PCM2_RXADDR" , 0x1070000018068ull, CVMX_CSR_DB_TYPE_NCB, 64, 365},
|
|
{"PCM3_RXADDR" , 0x107000001C068ull, CVMX_CSR_DB_TYPE_NCB, 64, 365},
|
|
{"PCM0_RXCNT" , 0x1070000010060ull, CVMX_CSR_DB_TYPE_NCB, 64, 366},
|
|
{"PCM1_RXCNT" , 0x1070000014060ull, CVMX_CSR_DB_TYPE_NCB, 64, 366},
|
|
{"PCM2_RXCNT" , 0x1070000018060ull, CVMX_CSR_DB_TYPE_NCB, 64, 366},
|
|
{"PCM3_RXCNT" , 0x107000001C060ull, CVMX_CSR_DB_TYPE_NCB, 64, 366},
|
|
{"PCM0_RXMSK0" , 0x10700000100C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 367},
|
|
{"PCM1_RXMSK0" , 0x10700000140C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 367},
|
|
{"PCM2_RXMSK0" , 0x10700000180C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 367},
|
|
{"PCM3_RXMSK0" , 0x107000001C0C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 367},
|
|
{"PCM0_RXMSK1" , 0x10700000100C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 368},
|
|
{"PCM1_RXMSK1" , 0x10700000140C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 368},
|
|
{"PCM2_RXMSK1" , 0x10700000180C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 368},
|
|
{"PCM3_RXMSK1" , 0x107000001C0C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 368},
|
|
{"PCM0_RXMSK2" , 0x10700000100D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 369},
|
|
{"PCM1_RXMSK2" , 0x10700000140D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 369},
|
|
{"PCM2_RXMSK2" , 0x10700000180D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 369},
|
|
{"PCM3_RXMSK2" , 0x107000001C0D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 369},
|
|
{"PCM0_RXMSK3" , 0x10700000100D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 370},
|
|
{"PCM1_RXMSK3" , 0x10700000140D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 370},
|
|
{"PCM2_RXMSK3" , 0x10700000180D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 370},
|
|
{"PCM3_RXMSK3" , 0x107000001C0D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 370},
|
|
{"PCM0_RXMSK4" , 0x10700000100E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
|
|
{"PCM1_RXMSK4" , 0x10700000140E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
|
|
{"PCM2_RXMSK4" , 0x10700000180E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
|
|
{"PCM3_RXMSK4" , 0x107000001C0E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
|
|
{"PCM0_RXMSK5" , 0x10700000100E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 372},
|
|
{"PCM1_RXMSK5" , 0x10700000140E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 372},
|
|
{"PCM2_RXMSK5" , 0x10700000180E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 372},
|
|
{"PCM3_RXMSK5" , 0x107000001C0E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 372},
|
|
{"PCM0_RXMSK6" , 0x10700000100F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 373},
|
|
{"PCM1_RXMSK6" , 0x10700000140F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 373},
|
|
{"PCM2_RXMSK6" , 0x10700000180F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 373},
|
|
{"PCM3_RXMSK6" , 0x107000001C0F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 373},
|
|
{"PCM0_RXMSK7" , 0x10700000100F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 374},
|
|
{"PCM1_RXMSK7" , 0x10700000140F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 374},
|
|
{"PCM2_RXMSK7" , 0x10700000180F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 374},
|
|
{"PCM3_RXMSK7" , 0x107000001C0F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 374},
|
|
{"PCM0_RXSTART" , 0x1070000010058ull, CVMX_CSR_DB_TYPE_NCB, 64, 375},
|
|
{"PCM1_RXSTART" , 0x1070000014058ull, CVMX_CSR_DB_TYPE_NCB, 64, 375},
|
|
{"PCM2_RXSTART" , 0x1070000018058ull, CVMX_CSR_DB_TYPE_NCB, 64, 375},
|
|
{"PCM3_RXSTART" , 0x107000001C058ull, CVMX_CSR_DB_TYPE_NCB, 64, 375},
|
|
{"PCM0_TDM_CFG" , 0x1070000010010ull, CVMX_CSR_DB_TYPE_NCB, 64, 376},
|
|
{"PCM1_TDM_CFG" , 0x1070000014010ull, CVMX_CSR_DB_TYPE_NCB, 64, 376},
|
|
{"PCM2_TDM_CFG" , 0x1070000018010ull, CVMX_CSR_DB_TYPE_NCB, 64, 376},
|
|
{"PCM3_TDM_CFG" , 0x107000001C010ull, CVMX_CSR_DB_TYPE_NCB, 64, 376},
|
|
{"PCM0_TDM_DBG" , 0x1070000010030ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
|
|
{"PCM1_TDM_DBG" , 0x1070000014030ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
|
|
{"PCM2_TDM_DBG" , 0x1070000018030ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
|
|
{"PCM3_TDM_DBG" , 0x107000001C030ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
|
|
{"PCM0_TXADDR" , 0x1070000010050ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
|
|
{"PCM1_TXADDR" , 0x1070000014050ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
|
|
{"PCM2_TXADDR" , 0x1070000018050ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
|
|
{"PCM3_TXADDR" , 0x107000001C050ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
|
|
{"PCM0_TXCNT" , 0x1070000010048ull, CVMX_CSR_DB_TYPE_NCB, 64, 379},
|
|
{"PCM1_TXCNT" , 0x1070000014048ull, CVMX_CSR_DB_TYPE_NCB, 64, 379},
|
|
{"PCM2_TXCNT" , 0x1070000018048ull, CVMX_CSR_DB_TYPE_NCB, 64, 379},
|
|
{"PCM3_TXCNT" , 0x107000001C048ull, CVMX_CSR_DB_TYPE_NCB, 64, 379},
|
|
{"PCM0_TXMSK0" , 0x1070000010080ull, CVMX_CSR_DB_TYPE_NCB, 64, 380},
|
|
{"PCM1_TXMSK0" , 0x1070000014080ull, CVMX_CSR_DB_TYPE_NCB, 64, 380},
|
|
{"PCM2_TXMSK0" , 0x1070000018080ull, CVMX_CSR_DB_TYPE_NCB, 64, 380},
|
|
{"PCM3_TXMSK0" , 0x107000001C080ull, CVMX_CSR_DB_TYPE_NCB, 64, 380},
|
|
{"PCM0_TXMSK1" , 0x1070000010088ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
|
|
{"PCM1_TXMSK1" , 0x1070000014088ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
|
|
{"PCM2_TXMSK1" , 0x1070000018088ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
|
|
{"PCM3_TXMSK1" , 0x107000001C088ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
|
|
{"PCM0_TXMSK2" , 0x1070000010090ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
|
|
{"PCM1_TXMSK2" , 0x1070000014090ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
|
|
{"PCM2_TXMSK2" , 0x1070000018090ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
|
|
{"PCM3_TXMSK2" , 0x107000001C090ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
|
|
{"PCM0_TXMSK3" , 0x1070000010098ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
|
|
{"PCM1_TXMSK3" , 0x1070000014098ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
|
|
{"PCM2_TXMSK3" , 0x1070000018098ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
|
|
{"PCM3_TXMSK3" , 0x107000001C098ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
|
|
{"PCM0_TXMSK4" , 0x10700000100A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
|
|
{"PCM1_TXMSK4" , 0x10700000140A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
|
|
{"PCM2_TXMSK4" , 0x10700000180A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
|
|
{"PCM3_TXMSK4" , 0x107000001C0A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
|
|
{"PCM0_TXMSK5" , 0x10700000100A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
|
|
{"PCM1_TXMSK5" , 0x10700000140A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
|
|
{"PCM2_TXMSK5" , 0x10700000180A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
|
|
{"PCM3_TXMSK5" , 0x107000001C0A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
|
|
{"PCM0_TXMSK6" , 0x10700000100B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
|
|
{"PCM1_TXMSK6" , 0x10700000140B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
|
|
{"PCM2_TXMSK6" , 0x10700000180B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
|
|
{"PCM3_TXMSK6" , 0x107000001C0B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
|
|
{"PCM0_TXMSK7" , 0x10700000100B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
|
|
{"PCM1_TXMSK7" , 0x10700000140B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
|
|
{"PCM2_TXMSK7" , 0x10700000180B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
|
|
{"PCM3_TXMSK7" , 0x107000001C0B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
|
|
{"PCM0_TXSTART" , 0x1070000010040ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
|
|
{"PCM1_TXSTART" , 0x1070000014040ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
|
|
{"PCM2_TXSTART" , 0x1070000018040ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
|
|
{"PCM3_TXSTART" , 0x107000001C040ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
|
|
{"PCM_CLK0_CFG" , 0x1070000010000ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
|
|
{"PCM_CLK1_CFG" , 0x1070000014000ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
|
|
{"PCM_CLK0_DBG" , 0x1070000010038ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
|
|
{"PCM_CLK1_DBG" , 0x1070000014038ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
|
|
{"PCM_CLK0_GEN" , 0x1070000010008ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
|
|
{"PCM_CLK1_GEN" , 0x1070000014008ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
|
|
{"PIP_BIST_STATUS" , 0x11800A0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
|
|
{"PIP_DEC_IPSEC0" , 0x11800A0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
|
|
{"PIP_DEC_IPSEC1" , 0x11800A0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
|
|
{"PIP_DEC_IPSEC2" , 0x11800A0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
|
|
{"PIP_DEC_IPSEC3" , 0x11800A0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
|
|
{"PIP_GBL_CFG" , 0x11800A0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
|
|
{"PIP_GBL_CTL" , 0x11800A0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
|
|
{"PIP_INT_EN" , 0x11800A0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
|
|
{"PIP_INT_REG" , 0x11800A0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
|
|
{"PIP_IP_OFFSET" , 0x11800A0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
|
|
{"PIP_PRT_CFG0" , 0x11800A0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
|
|
{"PIP_PRT_CFG1" , 0x11800A0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
|
|
{"PIP_PRT_CFG2" , 0x11800A0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
|
|
{"PIP_PRT_CFG32" , 0x11800A0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
|
|
{"PIP_PRT_CFG33" , 0x11800A0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
|
|
{"PIP_PRT_TAG0" , 0x11800A0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
|
|
{"PIP_PRT_TAG1" , 0x11800A0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
|
|
{"PIP_PRT_TAG2" , 0x11800A0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
|
|
{"PIP_PRT_TAG32" , 0x11800A0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
|
|
{"PIP_PRT_TAG33" , 0x11800A0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
|
|
{"PIP_QOS_DIFF0" , 0x11800A0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF1" , 0x11800A0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF2" , 0x11800A0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF3" , 0x11800A0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF4" , 0x11800A0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF5" , 0x11800A0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF6" , 0x11800A0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF7" , 0x11800A0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF8" , 0x11800A0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF9" , 0x11800A0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF10" , 0x11800A0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF11" , 0x11800A0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF12" , 0x11800A0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF13" , 0x11800A0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF14" , 0x11800A0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF15" , 0x11800A0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF16" , 0x11800A0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF17" , 0x11800A0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF18" , 0x11800A0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF19" , 0x11800A0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF20" , 0x11800A00006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF21" , 0x11800A00006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF22" , 0x11800A00006B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF23" , 0x11800A00006B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF24" , 0x11800A00006C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF25" , 0x11800A00006C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF26" , 0x11800A00006D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF27" , 0x11800A00006D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF28" , 0x11800A00006E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF29" , 0x11800A00006E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF30" , 0x11800A00006F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF31" , 0x11800A00006F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF32" , 0x11800A0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF33" , 0x11800A0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF34" , 0x11800A0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF35" , 0x11800A0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF36" , 0x11800A0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF37" , 0x11800A0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF38" , 0x11800A0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF39" , 0x11800A0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF40" , 0x11800A0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF41" , 0x11800A0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF42" , 0x11800A0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF43" , 0x11800A0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF44" , 0x11800A0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF45" , 0x11800A0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF46" , 0x11800A0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF47" , 0x11800A0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF48" , 0x11800A0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF49" , 0x11800A0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF50" , 0x11800A0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF51" , 0x11800A0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF52" , 0x11800A00007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF53" , 0x11800A00007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF54" , 0x11800A00007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF55" , 0x11800A00007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF56" , 0x11800A00007C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF57" , 0x11800A00007C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF58" , 0x11800A00007D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF59" , 0x11800A00007D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF60" , 0x11800A00007E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF61" , 0x11800A00007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF62" , 0x11800A00007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_DIFF63" , 0x11800A00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"PIP_QOS_VLAN0" , 0x11800A00000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
|
|
{"PIP_QOS_VLAN1" , 0x11800A00000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
|
|
{"PIP_QOS_VLAN2" , 0x11800A00000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
|
|
{"PIP_QOS_VLAN3" , 0x11800A00000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
|
|
{"PIP_QOS_VLAN4" , 0x11800A00000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
|
|
{"PIP_QOS_VLAN5" , 0x11800A00000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
|
|
{"PIP_QOS_VLAN6" , 0x11800A00000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
|
|
{"PIP_QOS_VLAN7" , 0x11800A00000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
|
|
{"PIP_QOS_WATCH0" , 0x11800A0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
|
|
{"PIP_QOS_WATCH1" , 0x11800A0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
|
|
{"PIP_QOS_WATCH2" , 0x11800A0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
|
|
{"PIP_QOS_WATCH3" , 0x11800A0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
|
|
{"PIP_RAW_WORD" , 0x11800A00000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
|
|
{"PIP_SFT_RST" , 0x11800A0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
|
|
{"PIP_STAT0_PRT0" , 0x11800A0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
|
|
{"PIP_STAT0_PRT1" , 0x11800A0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
|
|
{"PIP_STAT0_PRT2" , 0x11800A00008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
|
|
{"PIP_STAT0_PRT32" , 0x11800A0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
|
|
{"PIP_STAT0_PRT33" , 0x11800A0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
|
|
{"PIP_STAT1_PRT0" , 0x11800A0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
|
|
{"PIP_STAT1_PRT1" , 0x11800A0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
|
|
{"PIP_STAT1_PRT2" , 0x11800A00008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
|
|
{"PIP_STAT1_PRT32" , 0x11800A0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
|
|
{"PIP_STAT1_PRT33" , 0x11800A0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
|
|
{"PIP_STAT2_PRT0" , 0x11800A0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
|
|
{"PIP_STAT2_PRT1" , 0x11800A0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
|
|
{"PIP_STAT2_PRT2" , 0x11800A00008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
|
|
{"PIP_STAT2_PRT32" , 0x11800A0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
|
|
{"PIP_STAT2_PRT33" , 0x11800A0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
|
|
{"PIP_STAT3_PRT0" , 0x11800A0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
|
|
{"PIP_STAT3_PRT1" , 0x11800A0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
|
|
{"PIP_STAT3_PRT2" , 0x11800A00008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
|
|
{"PIP_STAT3_PRT32" , 0x11800A0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
|
|
{"PIP_STAT3_PRT33" , 0x11800A0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
|
|
{"PIP_STAT4_PRT0" , 0x11800A0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
|
|
{"PIP_STAT4_PRT1" , 0x11800A0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
|
|
{"PIP_STAT4_PRT2" , 0x11800A00008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
|
|
{"PIP_STAT4_PRT32" , 0x11800A0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
|
|
{"PIP_STAT4_PRT33" , 0x11800A0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
|
|
{"PIP_STAT5_PRT0" , 0x11800A0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
|
|
{"PIP_STAT5_PRT1" , 0x11800A0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
|
|
{"PIP_STAT5_PRT2" , 0x11800A00008C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
|
|
{"PIP_STAT5_PRT32" , 0x11800A0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
|
|
{"PIP_STAT5_PRT33" , 0x11800A0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
|
|
{"PIP_STAT6_PRT0" , 0x11800A0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
|
|
{"PIP_STAT6_PRT1" , 0x11800A0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
|
|
{"PIP_STAT6_PRT2" , 0x11800A00008D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
|
|
{"PIP_STAT6_PRT32" , 0x11800A0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
|
|
{"PIP_STAT6_PRT33" , 0x11800A0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
|
|
{"PIP_STAT7_PRT0" , 0x11800A0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
|
|
{"PIP_STAT7_PRT1" , 0x11800A0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
|
|
{"PIP_STAT7_PRT2" , 0x11800A00008D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
|
|
{"PIP_STAT7_PRT32" , 0x11800A0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
|
|
{"PIP_STAT7_PRT33" , 0x11800A0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
|
|
{"PIP_STAT8_PRT0" , 0x11800A0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
|
|
{"PIP_STAT8_PRT1" , 0x11800A0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
|
|
{"PIP_STAT8_PRT2" , 0x11800A00008E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
|
|
{"PIP_STAT8_PRT32" , 0x11800A0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
|
|
{"PIP_STAT8_PRT33" , 0x11800A0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
|
|
{"PIP_STAT9_PRT0" , 0x11800A0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_STAT9_PRT1" , 0x11800A0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_STAT9_PRT2" , 0x11800A00008E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_STAT9_PRT32" , 0x11800A0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_STAT9_PRT33" , 0x11800A0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_STAT_CTL" , 0x11800A0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
|
|
{"PIP_STAT_INB_ERRS0" , 0x11800A0001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
|
|
{"PIP_STAT_INB_ERRS1" , 0x11800A0001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
|
|
{"PIP_STAT_INB_ERRS2" , 0x11800A0001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
|
|
{"PIP_STAT_INB_ERRS32" , 0x11800A0001E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
|
|
{"PIP_STAT_INB_ERRS33" , 0x11800A0001E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
|
|
{"PIP_STAT_INB_OCTS0" , 0x11800A0001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
|
|
{"PIP_STAT_INB_OCTS1" , 0x11800A0001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
|
|
{"PIP_STAT_INB_OCTS2" , 0x11800A0001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
|
|
{"PIP_STAT_INB_OCTS32" , 0x11800A0001E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
|
|
{"PIP_STAT_INB_OCTS33" , 0x11800A0001E28ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
|
|
{"PIP_STAT_INB_PKTS0" , 0x11800A0001A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
|
|
{"PIP_STAT_INB_PKTS1" , 0x11800A0001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
|
|
{"PIP_STAT_INB_PKTS2" , 0x11800A0001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
|
|
{"PIP_STAT_INB_PKTS32" , 0x11800A0001E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
|
|
{"PIP_STAT_INB_PKTS33" , 0x11800A0001E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
|
|
{"PIP_TAG_INC0" , 0x11800A0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC1" , 0x11800A0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC2" , 0x11800A0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC3" , 0x11800A0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC4" , 0x11800A0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC5" , 0x11800A0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC6" , 0x11800A0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC7" , 0x11800A0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC8" , 0x11800A0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC9" , 0x11800A0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC10" , 0x11800A0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC11" , 0x11800A0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC12" , 0x11800A0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC13" , 0x11800A0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC14" , 0x11800A0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC15" , 0x11800A0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC16" , 0x11800A0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC17" , 0x11800A0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC18" , 0x11800A0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC19" , 0x11800A0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC20" , 0x11800A00018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC21" , 0x11800A00018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC22" , 0x11800A00018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC23" , 0x11800A00018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC24" , 0x11800A00018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC25" , 0x11800A00018C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC26" , 0x11800A00018D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC27" , 0x11800A00018D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC28" , 0x11800A00018E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC29" , 0x11800A00018E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC30" , 0x11800A00018F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC31" , 0x11800A00018F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC32" , 0x11800A0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC33" , 0x11800A0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC34" , 0x11800A0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC35" , 0x11800A0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC36" , 0x11800A0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC37" , 0x11800A0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC38" , 0x11800A0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC39" , 0x11800A0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC40" , 0x11800A0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC41" , 0x11800A0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC42" , 0x11800A0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC43" , 0x11800A0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC44" , 0x11800A0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC45" , 0x11800A0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC46" , 0x11800A0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC47" , 0x11800A0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC48" , 0x11800A0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC49" , 0x11800A0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC50" , 0x11800A0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC51" , 0x11800A0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC52" , 0x11800A00019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC53" , 0x11800A00019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC54" , 0x11800A00019B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC55" , 0x11800A00019B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC56" , 0x11800A00019C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC57" , 0x11800A00019C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC58" , 0x11800A00019D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC59" , 0x11800A00019D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC60" , 0x11800A00019E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC61" , 0x11800A00019E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC62" , 0x11800A00019F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_INC63" , 0x11800A00019F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_TAG_MASK" , 0x11800A0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_TAG_SECRET" , 0x11800A0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_TODO_ENTRY" , 0x11800A0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
|
|
{"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
|
|
{"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
|
|
{"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PKO_MEM_DEBUG14" , 0x1180050001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
|
|
{"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
|
|
{"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"POW_BIST_STAT" , 0x16700000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 452},
|
|
{"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 453},
|
|
{"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 454},
|
|
{"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 455},
|
|
{"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 456},
|
|
{"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 456},
|
|
{"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 456},
|
|
{"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 456},
|
|
{"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 456},
|
|
{"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 456},
|
|
{"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 456},
|
|
{"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 456},
|
|
{"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 457},
|
|
{"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 458},
|
|
{"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 459},
|
|
{"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 460},
|
|
{"POW_QOS_RND0" , 0x16700000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
|
|
{"POW_QOS_RND1" , 0x16700000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
|
|
{"POW_QOS_RND2" , 0x16700000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
|
|
{"POW_QOS_RND3" , 0x16700000001D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
|
|
{"POW_QOS_RND4" , 0x16700000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
|
|
{"POW_QOS_RND5" , 0x16700000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
|
|
{"POW_QOS_RND6" , 0x16700000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
|
|
{"POW_QOS_RND7" , 0x16700000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 461},
|
|
{"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 462},
|
|
{"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 462},
|
|
{"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 462},
|
|
{"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 462},
|
|
{"POW_QOS_THR4" , 0x16700000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 462},
|
|
{"POW_QOS_THR5" , 0x16700000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 462},
|
|
{"POW_QOS_THR6" , 0x16700000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 462},
|
|
{"POW_QOS_THR7" , 0x16700000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 462},
|
|
{"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 463},
|
|
{"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 464},
|
|
{"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 465},
|
|
{"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 465},
|
|
{"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 465},
|
|
{"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 465},
|
|
{"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 465},
|
|
{"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 465},
|
|
{"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 465},
|
|
{"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 465},
|
|
{"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 466},
|
|
{"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
|
|
{"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
|
|
{"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
|
|
{"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
|
|
{"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
|
|
{"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
|
|
{"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
|
|
{"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
|
|
{"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
|
|
{"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
|
|
{"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
|
|
{"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
|
|
{"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
|
|
{"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
|
|
{"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
|
|
{"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 467},
|
|
{"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 468},
|
|
{"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
|
|
{"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
|
|
{"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
|
|
{"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
|
|
{"POW_WQ_INT_THR4" , 0x16700000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
|
|
{"POW_WQ_INT_THR5" , 0x16700000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
|
|
{"POW_WQ_INT_THR6" , 0x16700000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
|
|
{"POW_WQ_INT_THR7" , 0x16700000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
|
|
{"POW_WQ_INT_THR8" , 0x16700000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
|
|
{"POW_WQ_INT_THR9" , 0x16700000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
|
|
{"POW_WQ_INT_THR10" , 0x16700000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
|
|
{"POW_WQ_INT_THR11" , 0x16700000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
|
|
{"POW_WQ_INT_THR12" , 0x16700000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
|
|
{"POW_WQ_INT_THR13" , 0x16700000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
|
|
{"POW_WQ_INT_THR14" , 0x16700000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
|
|
{"POW_WQ_INT_THR15" , 0x16700000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
|
|
{"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
|
|
{"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
|
|
{"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
|
|
{"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
|
|
{"POW_WS_PC4" , 0x16700000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
|
|
{"POW_WS_PC5" , 0x16700000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
|
|
{"POW_WS_PC6" , 0x16700000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
|
|
{"POW_WS_PC7" , 0x16700000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
|
|
{"POW_WS_PC8" , 0x16700000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
|
|
{"POW_WS_PC9" , 0x16700000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
|
|
{"POW_WS_PC10" , 0x16700000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
|
|
{"POW_WS_PC11" , 0x16700000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
|
|
{"POW_WS_PC12" , 0x16700000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
|
|
{"POW_WS_PC13" , 0x16700000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
|
|
{"POW_WS_PC14" , 0x16700000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
|
|
{"POW_WS_PC15" , 0x16700000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
|
|
{"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 473},
|
|
{"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 474},
|
|
{"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 475},
|
|
{"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 476},
|
|
{"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 477},
|
|
{"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 478},
|
|
{"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
|
|
{"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 480},
|
|
{"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
|
|
{"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 482},
|
|
{"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 483},
|
|
{"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 484},
|
|
{"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 485},
|
|
{"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 486},
|
|
{"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 487},
|
|
{"USBC0_DAINT" , 0x16F0010000818ull, CVMX_CSR_DB_TYPE_NCB, 32, 488},
|
|
{"USBC0_DAINTMSK" , 0x16F001000081Cull, CVMX_CSR_DB_TYPE_NCB, 32, 489},
|
|
{"USBC0_DCFG" , 0x16F0010000800ull, CVMX_CSR_DB_TYPE_NCB, 32, 490},
|
|
{"USBC0_DCTL" , 0x16F0010000804ull, CVMX_CSR_DB_TYPE_NCB, 32, 491},
|
|
{"USBC0_DIEPCTL000" , 0x16F0010000900ull, CVMX_CSR_DB_TYPE_NCB, 32, 492},
|
|
{"USBC0_DIEPCTL001" , 0x16F0010000920ull, CVMX_CSR_DB_TYPE_NCB, 32, 492},
|
|
{"USBC0_DIEPCTL002" , 0x16F0010000940ull, CVMX_CSR_DB_TYPE_NCB, 32, 492},
|
|
{"USBC0_DIEPCTL003" , 0x16F0010000960ull, CVMX_CSR_DB_TYPE_NCB, 32, 492},
|
|
{"USBC0_DIEPCTL004" , 0x16F0010000980ull, CVMX_CSR_DB_TYPE_NCB, 32, 492},
|
|
{"USBC0_DIEPINT000" , 0x16F0010000908ull, CVMX_CSR_DB_TYPE_NCB, 32, 493},
|
|
{"USBC0_DIEPINT001" , 0x16F0010000928ull, CVMX_CSR_DB_TYPE_NCB, 32, 493},
|
|
{"USBC0_DIEPINT002" , 0x16F0010000948ull, CVMX_CSR_DB_TYPE_NCB, 32, 493},
|
|
{"USBC0_DIEPINT003" , 0x16F0010000968ull, CVMX_CSR_DB_TYPE_NCB, 32, 493},
|
|
{"USBC0_DIEPINT004" , 0x16F0010000988ull, CVMX_CSR_DB_TYPE_NCB, 32, 493},
|
|
{"USBC0_DIEPMSK" , 0x16F0010000810ull, CVMX_CSR_DB_TYPE_NCB, 32, 494},
|
|
{"USBC0_DIEPTSIZ000" , 0x16F0010000910ull, CVMX_CSR_DB_TYPE_NCB, 32, 495},
|
|
{"USBC0_DIEPTSIZ001" , 0x16F0010000930ull, CVMX_CSR_DB_TYPE_NCB, 32, 495},
|
|
{"USBC0_DIEPTSIZ002" , 0x16F0010000950ull, CVMX_CSR_DB_TYPE_NCB, 32, 495},
|
|
{"USBC0_DIEPTSIZ003" , 0x16F0010000970ull, CVMX_CSR_DB_TYPE_NCB, 32, 495},
|
|
{"USBC0_DIEPTSIZ004" , 0x16F0010000990ull, CVMX_CSR_DB_TYPE_NCB, 32, 495},
|
|
{"USBC0_DOEPCTL000" , 0x16F0010000B00ull, CVMX_CSR_DB_TYPE_NCB, 32, 496},
|
|
{"USBC0_DOEPCTL001" , 0x16F0010000B20ull, CVMX_CSR_DB_TYPE_NCB, 32, 496},
|
|
{"USBC0_DOEPCTL002" , 0x16F0010000B40ull, CVMX_CSR_DB_TYPE_NCB, 32, 496},
|
|
{"USBC0_DOEPCTL003" , 0x16F0010000B60ull, CVMX_CSR_DB_TYPE_NCB, 32, 496},
|
|
{"USBC0_DOEPCTL004" , 0x16F0010000B80ull, CVMX_CSR_DB_TYPE_NCB, 32, 496},
|
|
{"USBC0_DOEPINT000" , 0x16F0010000B08ull, CVMX_CSR_DB_TYPE_NCB, 32, 497},
|
|
{"USBC0_DOEPINT001" , 0x16F0010000B28ull, CVMX_CSR_DB_TYPE_NCB, 32, 497},
|
|
{"USBC0_DOEPINT002" , 0x16F0010000B48ull, CVMX_CSR_DB_TYPE_NCB, 32, 497},
|
|
{"USBC0_DOEPINT003" , 0x16F0010000B68ull, CVMX_CSR_DB_TYPE_NCB, 32, 497},
|
|
{"USBC0_DOEPINT004" , 0x16F0010000B88ull, CVMX_CSR_DB_TYPE_NCB, 32, 497},
|
|
{"USBC0_DOEPMSK" , 0x16F0010000814ull, CVMX_CSR_DB_TYPE_NCB, 32, 498},
|
|
{"USBC0_DOEPTSIZ000" , 0x16F0010000B10ull, CVMX_CSR_DB_TYPE_NCB, 32, 499},
|
|
{"USBC0_DOEPTSIZ001" , 0x16F0010000B30ull, CVMX_CSR_DB_TYPE_NCB, 32, 499},
|
|
{"USBC0_DOEPTSIZ002" , 0x16F0010000B50ull, CVMX_CSR_DB_TYPE_NCB, 32, 499},
|
|
{"USBC0_DOEPTSIZ003" , 0x16F0010000B70ull, CVMX_CSR_DB_TYPE_NCB, 32, 499},
|
|
{"USBC0_DOEPTSIZ004" , 0x16F0010000B90ull, CVMX_CSR_DB_TYPE_NCB, 32, 499},
|
|
{"USBC0_DPTXFSIZ001" , 0x16F0010000104ull, CVMX_CSR_DB_TYPE_NCB, 32, 500},
|
|
{"USBC0_DPTXFSIZ002" , 0x16F0010000108ull, CVMX_CSR_DB_TYPE_NCB, 32, 500},
|
|
{"USBC0_DPTXFSIZ003" , 0x16F001000010Cull, CVMX_CSR_DB_TYPE_NCB, 32, 500},
|
|
{"USBC0_DPTXFSIZ004" , 0x16F0010000110ull, CVMX_CSR_DB_TYPE_NCB, 32, 500},
|
|
{"USBC0_DSTS" , 0x16F0010000808ull, CVMX_CSR_DB_TYPE_NCB, 32, 501},
|
|
{"USBC0_DTKNQR1" , 0x16F0010000820ull, CVMX_CSR_DB_TYPE_NCB, 32, 502},
|
|
{"USBC0_DTKNQR2" , 0x16F0010000824ull, CVMX_CSR_DB_TYPE_NCB, 32, 503},
|
|
{"USBC0_DTKNQR3" , 0x16F0010000830ull, CVMX_CSR_DB_TYPE_NCB, 32, 504},
|
|
{"USBC0_DTKNQR4" , 0x16F0010000834ull, CVMX_CSR_DB_TYPE_NCB, 32, 505},
|
|
{"USBC0_GAHBCFG" , 0x16F0010000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 506},
|
|
{"USBC0_GHWCFG1" , 0x16F0010000044ull, CVMX_CSR_DB_TYPE_NCB, 32, 507},
|
|
{"USBC0_GHWCFG2" , 0x16F0010000048ull, CVMX_CSR_DB_TYPE_NCB, 32, 508},
|
|
{"USBC0_GHWCFG3" , 0x16F001000004Cull, CVMX_CSR_DB_TYPE_NCB, 32, 509},
|
|
{"USBC0_GHWCFG4" , 0x16F0010000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 510},
|
|
{"USBC0_GINTMSK" , 0x16F0010000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 511},
|
|
{"USBC0_GINTSTS" , 0x16F0010000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 512},
|
|
{"USBC0_GNPTXFSIZ" , 0x16F0010000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 513},
|
|
{"USBC0_GNPTXSTS" , 0x16F001000002Cull, CVMX_CSR_DB_TYPE_NCB, 32, 514},
|
|
{"USBC0_GOTGCTL" , 0x16F0010000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 515},
|
|
{"USBC0_GOTGINT" , 0x16F0010000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 516},
|
|
{"USBC0_GRSTCTL" , 0x16F0010000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 517},
|
|
{"USBC0_GRXFSIZ" , 0x16F0010000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 518},
|
|
{"USBC0_GRXSTSPD" , 0x16F0010040020ull, CVMX_CSR_DB_TYPE_NCB, 32, 519},
|
|
{"USBC0_GRXSTSPH" , 0x16F0010000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 520},
|
|
{"USBC0_GRXSTSRD" , 0x16F001004001Cull, CVMX_CSR_DB_TYPE_NCB, 32, 521},
|
|
{"USBC0_GRXSTSRH" , 0x16F001000001Cull, CVMX_CSR_DB_TYPE_NCB, 32, 522},
|
|
{"USBC0_GSNPSID" , 0x16F0010000040ull, CVMX_CSR_DB_TYPE_NCB, 32, 523},
|
|
{"USBC0_GUSBCFG" , 0x16F001000000Cull, CVMX_CSR_DB_TYPE_NCB, 32, 524},
|
|
{"USBC0_HAINT" , 0x16F0010000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 525},
|
|
{"USBC0_HAINTMSK" , 0x16F0010000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 526},
|
|
{"USBC0_HCCHAR000" , 0x16F0010000500ull, CVMX_CSR_DB_TYPE_NCB, 32, 527},
|
|
{"USBC0_HCCHAR001" , 0x16F0010000520ull, CVMX_CSR_DB_TYPE_NCB, 32, 527},
|
|
{"USBC0_HCCHAR002" , 0x16F0010000540ull, CVMX_CSR_DB_TYPE_NCB, 32, 527},
|
|
{"USBC0_HCCHAR003" , 0x16F0010000560ull, CVMX_CSR_DB_TYPE_NCB, 32, 527},
|
|
{"USBC0_HCCHAR004" , 0x16F0010000580ull, CVMX_CSR_DB_TYPE_NCB, 32, 527},
|
|
{"USBC0_HCCHAR005" , 0x16F00100005A0ull, CVMX_CSR_DB_TYPE_NCB, 32, 527},
|
|
{"USBC0_HCCHAR006" , 0x16F00100005C0ull, CVMX_CSR_DB_TYPE_NCB, 32, 527},
|
|
{"USBC0_HCCHAR007" , 0x16F00100005E0ull, CVMX_CSR_DB_TYPE_NCB, 32, 527},
|
|
{"USBC0_HCFG" , 0x16F0010000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 528},
|
|
{"USBC0_HCINT000" , 0x16F0010000508ull, CVMX_CSR_DB_TYPE_NCB, 32, 529},
|
|
{"USBC0_HCINT001" , 0x16F0010000528ull, CVMX_CSR_DB_TYPE_NCB, 32, 529},
|
|
{"USBC0_HCINT002" , 0x16F0010000548ull, CVMX_CSR_DB_TYPE_NCB, 32, 529},
|
|
{"USBC0_HCINT003" , 0x16F0010000568ull, CVMX_CSR_DB_TYPE_NCB, 32, 529},
|
|
{"USBC0_HCINT004" , 0x16F0010000588ull, CVMX_CSR_DB_TYPE_NCB, 32, 529},
|
|
{"USBC0_HCINT005" , 0x16F00100005A8ull, CVMX_CSR_DB_TYPE_NCB, 32, 529},
|
|
{"USBC0_HCINT006" , 0x16F00100005C8ull, CVMX_CSR_DB_TYPE_NCB, 32, 529},
|
|
{"USBC0_HCINT007" , 0x16F00100005E8ull, CVMX_CSR_DB_TYPE_NCB, 32, 529},
|
|
{"USBC0_HCINTMSK000" , 0x16F001000050Cull, CVMX_CSR_DB_TYPE_NCB, 32, 530},
|
|
{"USBC0_HCINTMSK001" , 0x16F001000052Cull, CVMX_CSR_DB_TYPE_NCB, 32, 530},
|
|
{"USBC0_HCINTMSK002" , 0x16F001000054Cull, CVMX_CSR_DB_TYPE_NCB, 32, 530},
|
|
{"USBC0_HCINTMSK003" , 0x16F001000056Cull, CVMX_CSR_DB_TYPE_NCB, 32, 530},
|
|
{"USBC0_HCINTMSK004" , 0x16F001000058Cull, CVMX_CSR_DB_TYPE_NCB, 32, 530},
|
|
{"USBC0_HCINTMSK005" , 0x16F00100005ACull, CVMX_CSR_DB_TYPE_NCB, 32, 530},
|
|
{"USBC0_HCINTMSK006" , 0x16F00100005CCull, CVMX_CSR_DB_TYPE_NCB, 32, 530},
|
|
{"USBC0_HCINTMSK007" , 0x16F00100005ECull, CVMX_CSR_DB_TYPE_NCB, 32, 530},
|
|
{"USBC0_HCSPLT000" , 0x16F0010000504ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
|
|
{"USBC0_HCSPLT001" , 0x16F0010000524ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
|
|
{"USBC0_HCSPLT002" , 0x16F0010000544ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
|
|
{"USBC0_HCSPLT003" , 0x16F0010000564ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
|
|
{"USBC0_HCSPLT004" , 0x16F0010000584ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
|
|
{"USBC0_HCSPLT005" , 0x16F00100005A4ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
|
|
{"USBC0_HCSPLT006" , 0x16F00100005C4ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
|
|
{"USBC0_HCSPLT007" , 0x16F00100005E4ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
|
|
{"USBC0_HCTSIZ000" , 0x16F0010000510ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
|
|
{"USBC0_HCTSIZ001" , 0x16F0010000530ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
|
|
{"USBC0_HCTSIZ002" , 0x16F0010000550ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
|
|
{"USBC0_HCTSIZ003" , 0x16F0010000570ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
|
|
{"USBC0_HCTSIZ004" , 0x16F0010000590ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
|
|
{"USBC0_HCTSIZ005" , 0x16F00100005B0ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
|
|
{"USBC0_HCTSIZ006" , 0x16F00100005D0ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
|
|
{"USBC0_HCTSIZ007" , 0x16F00100005F0ull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
|
|
{"USBC0_HFIR" , 0x16F0010000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 533},
|
|
{"USBC0_HFNUM" , 0x16F0010000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 534},
|
|
{"USBC0_HPRT" , 0x16F0010000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 535},
|
|
{"USBC0_HPTXFSIZ" , 0x16F0010000100ull, CVMX_CSR_DB_TYPE_NCB, 32, 536},
|
|
{"USBC0_HPTXSTS" , 0x16F0010000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 537},
|
|
{"USBC0_NPTXDFIFO000" , 0x16F0010001000ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
|
|
{"USBC0_NPTXDFIFO001" , 0x16F0010002000ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
|
|
{"USBC0_NPTXDFIFO002" , 0x16F0010003000ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
|
|
{"USBC0_NPTXDFIFO003" , 0x16F0010004000ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
|
|
{"USBC0_NPTXDFIFO004" , 0x16F0010005000ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
|
|
{"USBC0_NPTXDFIFO005" , 0x16F0010006000ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
|
|
{"USBC0_NPTXDFIFO006" , 0x16F0010007000ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
|
|
{"USBC0_NPTXDFIFO007" , 0x16F0010008000ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
|
|
{"USBC0_PCGCCTL" , 0x16F0010000E00ull, CVMX_CSR_DB_TYPE_NCB, 32, 539},
|
|
{"USBN0_BIST_STATUS" , 0x11800680007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
|
|
{"USBN0_CLK_CTL" , 0x1180068000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 541},
|
|
{"USBN0_CTL_STATUS" , 0x16F0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 542},
|
|
{"USBN0_DMA0_INB_CHN0" , 0x16F0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 543},
|
|
{"USBN0_DMA0_INB_CHN1" , 0x16F0000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 544},
|
|
{"USBN0_DMA0_INB_CHN2" , 0x16F0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 545},
|
|
{"USBN0_DMA0_INB_CHN3" , 0x16F0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 546},
|
|
{"USBN0_DMA0_INB_CHN4" , 0x16F0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 547},
|
|
{"USBN0_DMA0_INB_CHN5" , 0x16F0000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 548},
|
|
{"USBN0_DMA0_INB_CHN6" , 0x16F0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 549},
|
|
{"USBN0_DMA0_INB_CHN7" , 0x16F0000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 550},
|
|
{"USBN0_DMA0_OUTB_CHN0" , 0x16F0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 551},
|
|
{"USBN0_DMA0_OUTB_CHN1" , 0x16F0000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 552},
|
|
{"USBN0_DMA0_OUTB_CHN2" , 0x16F0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 553},
|
|
{"USBN0_DMA0_OUTB_CHN3" , 0x16F0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 554},
|
|
{"USBN0_DMA0_OUTB_CHN4" , 0x16F0000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 555},
|
|
{"USBN0_DMA0_OUTB_CHN5" , 0x16F0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 556},
|
|
{"USBN0_DMA0_OUTB_CHN6" , 0x16F0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 557},
|
|
{"USBN0_DMA0_OUTB_CHN7" , 0x16F0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 558},
|
|
{"USBN0_DMA_TEST" , 0x16F0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 559},
|
|
{"USBN0_INT_ENB" , 0x1180068000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 560},
|
|
{"USBN0_INT_SUM" , 0x1180068000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 561},
|
|
{"USBN0_USBP_CTL_STATUS" , 0x1180068000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 562},
|
|
{NULL,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn30xx[] = {
|
|
/* name , bit, width, csr, type, rst un, typ un, reset, typical */
|
|
{"SETTING" , 0, 5, 0, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 0, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 1, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 1, "RAZ", 1, 1, 0, 0},
|
|
{"OVRFLW" , 0, 3, 2, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_3_3" , 3, 1, 2, "RAZ", 1, 1, 0, 0},
|
|
{"TXPOP" , 4, 3, 2, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_7_7" , 7, 1, 2, "RAZ", 1, 1, 0, 0},
|
|
{"TXPSH" , 8, 3, 2, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_11_63" , 11, 53, 2, "RAZ", 1, 1, 0, 0},
|
|
{"OVRFLW" , 0, 3, 3, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 3, "RAZ", 1, 1, 0, 0},
|
|
{"TXPOP" , 4, 3, 3, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 3, "RAZ", 1, 1, 0, 0},
|
|
{"TXPSH" , 8, 3, 3, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 3, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 4, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 4, "RAZ", 1, 1, 0, 0},
|
|
{"INT_LOOP" , 0, 3, 5, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 5, "RAZ", 1, 1, 0, 0},
|
|
{"EXT_LOOP" , 4, 3, 5, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 5, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 6, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_5_63" , 5, 59, 6, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_EN" , 0, 3, 7, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_3_63" , 3, 61, 7, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 8, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_5_63" , 5, 59, 8, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 4, 9, "R/W", 0, 0, 8ull, 8ull},
|
|
{"PCTL" , 4, 4, 9, "R/W", 0, 0, 8ull, 8ull},
|
|
{"BYPASS" , 8, 1, 9, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 9, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 3, 10, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 10, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_EN" , 0, 3, 11, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_3_63" , 3, 61, 11, "RAZ", 1, 1, 0, 0},
|
|
{"BIST" , 0, 4, 12, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 12, "RAZ", 1, 1, 0, 0},
|
|
{"DINT" , 0, 1, 13, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 13, "RAZ", 1, 1, 0, 0},
|
|
{"FUSE" , 0, 1, 14, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_1_63" , 1, 63, 14, "RAZ", 1, 1, 0, 0},
|
|
{"GSTOP" , 0, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 15, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWSI" , 45, 1, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_47_47" , 47, 1, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 1, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_49" , 49, 1, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_51_51" , 51, 1, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCM" , 57, 1, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MPI" , 58, 1, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_59_63" , 59, 5, 16, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 1, 17, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 17, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 18, "RO", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 18, "RO", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 18, "RO", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 18, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 18, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 18, "RO", 0, 0, 0ull, 0ull},
|
|
{"WDOG_SUM" , 44, 1, 18, "RO", 0, 0, 0ull, 0ull},
|
|
{"TWSI" , 45, 1, 18, "RO", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 18, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_47_47" , 47, 1, 18, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_49" , 49, 1, 18, "RAZ", 1, 1, 0, 0},
|
|
{"IPD_DRP" , 50, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_51_51" , 51, 1, 18, "RAZ", 1, 1, 0, 0},
|
|
{"TIMER" , 52, 4, 18, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 18, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCM" , 57, 1, 18, "RO", 0, 0, 0ull, 0ull},
|
|
{"MPI" , 58, 1, 18, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_59_63" , 59, 5, 18, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 1, 19, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 19, "RAZ", 1, 1, 0, 0},
|
|
{"BITS" , 0, 32, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 20, "RAZ", 1, 1, 0, 0},
|
|
{"BITS" , 0, 32, 21, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 21, "RAZ", 1, 1, 0, 0},
|
|
{"NMI" , 0, 1, 22, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 22, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 0, 2, 23, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 23, "RAZ", 1, 1, 0, 0},
|
|
{"PPDBG" , 0, 1, 24, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 24, "RAZ", 1, 1, 0, 0},
|
|
{"POKE" , 0, 64, 25, "RAZ", 1, 1, 0, 0},
|
|
{"RST0" , 0, 1, 26, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_1_63" , 1, 63, 26, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_BIST" , 0, 1, 27, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 27, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_PRST" , 0, 1, 28, "R/W", 0, 0, 1ull, 0ull},
|
|
{"NPI" , 1, 1, 28, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HOST64" , 2, 1, 28, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 28, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_RST" , 0, 1, 29, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 29, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 36, 30, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ONE_SHOT" , 36, 1, 30, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 30, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 0, 2, 31, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STATE" , 2, 2, 31, "RO", 0, 0, 0ull, 0ull},
|
|
{"LEN" , 4, 16, 31, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 20, 24, 31, "RO", 0, 0, 0ull, 0ull},
|
|
{"DSTOP" , 44, 1, 31, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GSTOPEN" , 45, 1, 31, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_46_63" , 46, 18, 31, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 17, 32, "RO", 0, 1, 0ull, 0},
|
|
{"DSEL_EXT" , 17, 1, 32, "R/W", 0, 0, 1ull, 0ull},
|
|
{"C_MUL" , 18, 5, 32, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_23_27" , 23, 5, 32, "RAZ", 1, 1, 0, 0},
|
|
{"PLL_MUL" , 28, 3, 32, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_31_63" , 31, 33, 32, "RAZ", 1, 1, 0, 0},
|
|
{"FDR" , 0, 1, 33, "RO", 0, 0, 0ull, 0ull},
|
|
{"FFR" , 1, 1, 33, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPF1" , 2, 1, 33, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPF0" , 3, 1, 33, "RO", 0, 0, 0ull, 0ull},
|
|
{"FRD" , 4, 1, 33, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 33, "RAZ", 1, 1, 0, 0},
|
|
{"MEM0_ERR" , 0, 7, 34, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM1_ERR" , 7, 7, 34, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 14, 1, 34, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USE_STT" , 15, 1, 34, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USE_LDT" , 16, 1, 34, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 17, 1, 34, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 34, "RAZ", 1, 1, 0, 0},
|
|
{"FED0_SBE" , 0, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED0_DBE" , 1, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED1_SBE" , 2, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED1_DBE" , 3, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_UND" , 4, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_COFF" , 5, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_PERR" , 6, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_UND" , 7, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_COFF" , 8, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_PERR" , 9, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_UND" , 10, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_COFF" , 11, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_PERR" , 12, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_UND" , 13, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_COFF" , 14, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_PERR" , 15, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_UND" , 16, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_COFF" , 17, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_PERR" , 18, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_UND" , 19, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_COFF" , 20, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_PERR" , 21, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_UND" , 22, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_COFF" , 23, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_PERR" , 24, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_UND" , 25, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_COFF" , 26, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_PERR" , 27, 1, 35, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 35, "RAZ", 1, 1, 0, 0},
|
|
{"FED0_SBE" , 0, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED0_DBE" , 1, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED1_SBE" , 2, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED1_DBE" , 3, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_UND" , 4, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_COFF" , 5, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_PERR" , 6, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_UND" , 7, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_COFF" , 8, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_PERR" , 9, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_UND" , 10, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_COFF" , 11, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_PERR" , 12, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_UND" , 13, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_COFF" , 14, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_PERR" , 15, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_UND" , 16, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_COFF" , 17, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_PERR" , 18, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_UND" , 19, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_COFF" , 20, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_PERR" , 21, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_UND" , 22, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_COFF" , 23, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_PERR" , 24, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_UND" , 25, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_COFF" , 26, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_PERR" , 27, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 36, "RAZ", 1, 1, 0, 0},
|
|
{"QUE_SIZ" , 0, 29, 37, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 37, "RAZ", 1, 1, 0, 0},
|
|
{"PG_NUM" , 0, 25, 38, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 38, "RAZ", 1, 1, 0, 0},
|
|
{"ACT_INDX" , 0, 26, 39, "RO", 0, 1, 0ull, 0},
|
|
{"ACT_QUE" , 26, 3, 39, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 39, "RAZ", 0, 0, 0ull, 7ull},
|
|
{"EXP_INDX" , 0, 26, 40, "RO", 0, 1, 0ull, 0},
|
|
{"EXP_QUE" , 26, 3, 40, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 40, "RAZ", 0, 0, 0ull, 7ull},
|
|
{"CTL" , 0, 16, 41, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 41, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 32, 42, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 42, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 43, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OUT_OVR" , 2, 3, 43, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_21" , 5, 17, 43, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LOSTSTAT" , 22, 3, 43, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_25" , 25, 1, 43, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STATOVR" , 26, 1, 43, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INB_NXA" , 27, 4, 43, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 43, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 10, 44, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 44, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 1, 45, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 1, 1, 45, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P0MII" , 2, 1, 45, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_63" , 3, 61, 45, "RAZ", 1, 1, 0, 0},
|
|
{"PRT" , 0, 6, 46, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 46, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 47, "R/W", 0, 1, 0ull, 0},
|
|
{"SPEED" , 1, 1, 47, "R/W", 0, 1, 1ull, 0},
|
|
{"DUPLEX" , 2, 1, 47, "R/W", 0, 1, 1ull, 0},
|
|
{"SLOTTIME" , 3, 1, 47, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 47, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 64, 48, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 49, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 50, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 51, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 52, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 53, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 0, 8, 54, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 54, "RAZ", 1, 1, 0, 0},
|
|
{"BCST" , 0, 1, 55, "R/W", 0, 1, 1ull, 0},
|
|
{"MCST" , 1, 2, 55, "R/W", 0, 1, 0ull, 0},
|
|
{"CAM_MODE" , 3, 1, 55, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 55, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 5, 56, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_5_63" , 5, 59, 56, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 57, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CAREXT" , 1, 1, 57, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MAXERR" , 2, 1, 57, "R/W", 0, 0, 1ull, 1ull},
|
|
{"JABBER" , 3, 1, 57, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCSERR" , 4, 1, 57, "R/W", 0, 0, 1ull, 1ull},
|
|
{"ALNERR" , 5, 1, 57, "R/W", 0, 0, 1ull, 1ull},
|
|
{"LENERR" , 6, 1, 57, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RCVERR" , 7, 1, 57, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SKPERR" , 8, 1, 57, "R/W", 0, 0, 1ull, 1ull},
|
|
{"NIBERR" , 9, 1, 57, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_10_63" , 10, 54, 57, "RAZ", 1, 1, 0, 0},
|
|
{"PRE_CHK" , 0, 1, 58, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PRE_STRP" , 1, 1, 58, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_DRP" , 2, 1, 58, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_BCK" , 3, 1, 58, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_MCST" , 4, 1, 58, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_SMAC" , 5, 1, 58, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PRE_FREE" , 6, 1, 58, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VLAN_LEN" , 7, 1, 58, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PAD_LEN" , 8, 1, 58, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 58, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 16, 59, "R/W", 0, 0, 1536ull, 1536ull},
|
|
{"RESERVED_16_63" , 16, 48, 59, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 16, 60, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_16_63" , 16, 48, 60, "RAZ", 1, 1, 0, 0},
|
|
{"IFG" , 0, 4, 61, "R/W", 0, 0, 12ull, 12ull},
|
|
{"RESERVED_4_63" , 4, 60, 61, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 62, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAREXT" , 1, 1, 62, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 2, 1, 62, "R/W", 0, 0, 0ull, 0ull},
|
|
{"JABBER" , 3, 1, 62, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 62, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ALNERR" , 5, 1, 62, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 6, 1, 62, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RCVERR" , 7, 1, 62, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 62, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NIBERR" , 9, 1, 62, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OVRERR" , 10, 1, 62, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 62, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 62, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 62, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 62, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 62, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHY_LINK" , 16, 1, 62, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHY_SPD" , 17, 1, 62, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHY_DUPX" , 18, 1, 62, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 62, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CAREXT" , 1, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 2, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"JABBER" , 3, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ALNERR" , 5, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 6, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RCVERR" , 7, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NIBERR" , 9, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OVRERR" , 10, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PHY_LINK" , 16, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PHY_SPD" , 17, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PHY_DUPX" , 18, 1, 63, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 63, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 64, "R/W", 0, 0, 10240ull, 10240ull},
|
|
{"RESERVED_16_63" , 16, 48, 64, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 1, 65, "RO", 0, 1, 0ull, 0},
|
|
{"SPEED" , 1, 2, 65, "RO", 0, 1, 0ull, 0},
|
|
{"DUPLEX" , 3, 1, 65, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 65, "RAZ", 1, 1, 0, 0},
|
|
{"RD_CLR" , 0, 1, 66, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 66, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 67, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 67, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 68, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 68, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 69, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 69, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 70, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 70, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 71, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 71, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 72, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 72, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 73, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 73, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 74, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 74, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 75, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 75, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 7, 76, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 76, "RAZ", 1, 1, 0, 0},
|
|
{"FCSSEL" , 8, 1, 76, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 76, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 77, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_6_63" , 6, 58, 77, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 78, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_6_63" , 6, 58, 78, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 9, 79, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_9_63" , 9, 55, 79, "RAZ", 1, 1, 0, 0},
|
|
{"COMMIT" , 0, 3, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_15" , 3, 13, 80, "RAZ", 1, 1, 0, 0},
|
|
{"DROP" , 16, 3, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 80, "RAZ", 1, 1, 0, 0},
|
|
{"PRTS" , 0, 3, 81, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_3_63" , 3, 61, 81, "RAZ", 1, 1, 0, 0},
|
|
{"RX" , 0, 3, 82, "RC", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 82, "RAZ", 1, 1, 0, 0},
|
|
{"TX" , 4, 3, 82, "RC", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 82, "RAZ", 1, 1, 0, 0},
|
|
{"SMAC" , 0, 48, 83, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 83, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 84, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP" , 16, 1, 84, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 84, "RAZ", 1, 1, 0, 0},
|
|
{"PREAMBLE" , 0, 1, 85, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PAD" , 1, 1, 85, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCS" , 2, 1, 85, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FORCE_FCS" , 3, 1, 85, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 85, "RAZ", 1, 1, 0, 0},
|
|
{"BURST" , 0, 16, 86, "R/W", 0, 0, 8192ull, 8192ull},
|
|
{"RESERVED_16_63" , 16, 48, 86, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_CNT" , 0, 6, 87, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_63" , 6, 58, 87, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL_EN" , 0, 1, 88, "R/W", 0, 0, 1ull, 1ull},
|
|
{"XSDEF_EN" , 1, 1, 88, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 88, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_SIZE" , 0, 8, 89, "R/W", 0, 0, 59ull, 59ull},
|
|
{"RESERVED_8_63" , 8, 56, 89, "RAZ", 1, 1, 0, 0},
|
|
{"INTERVAL" , 0, 16, 90, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 90, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 91, "R/W", 0, 1, 96ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 91, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 92, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_16_63" , 16, 48, 92, "RAZ", 1, 1, 0, 0},
|
|
{"SEND" , 0, 1, 93, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 93, "RAZ", 1, 1, 0, 0},
|
|
{"SLOT" , 0, 10, 94, "R/W", 0, 0, 512ull, 512ull},
|
|
{"RESERVED_10_63" , 10, 54, 94, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 95, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 95, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL" , 0, 32, 96, "RC/W", 0, 1, 0ull, 0},
|
|
{"XSDEF" , 32, 32, 96, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCOL" , 0, 32, 97, "RC/W", 0, 1, 0ull, 0},
|
|
{"SCOL" , 32, 32, 97, "RC/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 98, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 98, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 99, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 99, "RAZ", 1, 1, 0, 0},
|
|
{"HIST0" , 0, 32, 100, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST1" , 32, 32, 100, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST2" , 0, 32, 101, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST3" , 32, 32, 101, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST4" , 0, 32, 102, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST5" , 32, 32, 102, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST6" , 0, 32, 103, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST7" , 32, 32, 103, "RC/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 0, 32, 104, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 32, 32, 104, "RC/W", 0, 1, 0ull, 0},
|
|
{"CTL" , 0, 32, 105, "RC/W", 0, 1, 0ull, 0},
|
|
{"UNDFLW" , 32, 32, 105, "RC/W", 0, 1, 0ull, 0},
|
|
{"RD_CLR" , 0, 1, 106, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 106, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 7, 107, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_7_63" , 7, 57, 107, "RAZ", 1, 1, 0, 0},
|
|
{"BP" , 0, 3, 108, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 108, "RAZ", 1, 1, 0, 0},
|
|
{"MSK" , 0, 1, 109, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 109, "RAZ", 1, 1, 0, 0},
|
|
{"LIMIT" , 0, 5, 110, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_5_63" , 5, 59, 110, "RAZ", 1, 1, 0, 0},
|
|
{"CORRUPT" , 0, 3, 111, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_3_63" , 3, 61, 111, "RAZ", 1, 1, 0, 0},
|
|
{"IFG1" , 0, 4, 112, "R/W", 0, 1, 8ull, 0},
|
|
{"IFG2" , 4, 4, 112, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 112, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 113, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 113, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 3, 113, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_7" , 5, 3, 113, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 3, 113, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_11" , 11, 1, 113, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 3, 113, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_15" , 15, 1, 113, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LATE_COL" , 16, 3, 113, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 113, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PKO_NXA" , 0, 1, 114, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 114, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 3, 114, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_7" , 5, 3, 114, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 3, 114, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_11" , 11, 1, 114, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 3, 114, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_15" , 15, 1, 114, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LATE_COL" , 16, 3, 114, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 114, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"JAM" , 0, 8, 115, "R/W", 0, 1, 238ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 115, "RAZ", 1, 1, 0, 0},
|
|
{"LFSR" , 0, 16, 116, "R/W", 0, 1, 65535ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 116, "RAZ", 1, 1, 0, 0},
|
|
{"IGN_FULL" , 0, 3, 117, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 117, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"BP" , 4, 3, 117, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 117, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EN" , 8, 3, 117, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 117, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DMAC" , 0, 48, 118, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
|
|
{"RESERVED_48_63" , 48, 16, 118, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 119, "R/W", 0, 0, 34824ull, 34824ull},
|
|
{"RESERVED_16_63" , 16, 48, 119, "RAZ", 1, 1, 0, 0},
|
|
{"PRTS" , 0, 5, 120, "R/W", 0, 1, 3ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 120, "RAZ", 1, 1, 0, 0},
|
|
{"TX_OE" , 0, 1, 121, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RX_XOR" , 1, 1, 121, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_EN" , 2, 1, 121, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_TYPE" , 3, 1, 121, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_CNT" , 4, 4, 121, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_SEL" , 8, 4, 121, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 121, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 122, "RAZ", 1, 1, 0, 0},
|
|
{"BOOT_ENA" , 8, 4, 122, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_12_63" , 12, 52, 122, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_ENA" , 0, 21, 123, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_63" , 21, 43, 123, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 124, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 124, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 24, 125, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 125, "RAZ", 1, 1, 0, 0},
|
|
{"CLR" , 0, 24, 126, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 126, "RAZ", 1, 1, 0, 0},
|
|
{"SET" , 0, 24, 127, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 127, "RAZ", 1, 1, 0, 0},
|
|
{"TX_OE" , 0, 1, 128, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RX_XOR" , 1, 1, 128, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_3" , 2, 2, 128, "RAZ", 1, 1, 0, 0},
|
|
{"FIL_CNT" , 4, 4, 128, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_SEL" , 8, 4, 128, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 128, "RAZ", 1, 1, 0, 0},
|
|
{"ICD" , 0, 1, 129, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBD" , 1, 1, 129, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRP1" , 2, 1, 129, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRP0" , 3, 1, 129, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRN1" , 4, 1, 129, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRN0" , 5, 1, 129, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBRQ1" , 6, 1, 129, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBRQ0" , 7, 1, 129, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNRT" , 8, 1, 129, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBR1" , 9, 1, 129, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBR0" , 10, 1, 129, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBDR1" , 11, 1, 129, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBDR0" , 12, 1, 129, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNR0" , 13, 1, 129, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNR1" , 14, 1, 129, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICR1" , 15, 1, 129, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICR0" , 16, 1, 129, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNRCB" , 17, 1, 129, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 129, "RAZ", 1, 1, 0, 0},
|
|
{"FAU_END" , 0, 1, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB_ENB" , 1, 1, 130, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PKO_ENB" , 2, 1, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INB_MAT" , 3, 1, 130, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OUTB_MAT" , 4, 1, 130, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 130, "RAZ", 1, 1, 0, 0},
|
|
{"TOUT_VAL" , 0, 12, 131, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TOUT_ENB" , 12, 1, 131, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 131, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 8, 132, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 8, 9, 132, "R/W", 0, 1, 0ull, 0},
|
|
{"OPC" , 17, 4, 132, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 21, 8, 132, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 132, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 8, 133, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 8, 9, 133, "R/W", 0, 1, 0ull, 0},
|
|
{"OPC" , 17, 4, 133, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 21, 8, 133, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 133, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 134, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 135, "R/W", 0, 1, 0ull, 0},
|
|
{"NP_SOP" , 0, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NP_EOP" , 1, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_SOP" , 2, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_EOP" , 3, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 136, "RAZ", 1, 1, 0, 0},
|
|
{"NP_SOP" , 0, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NP_EOP" , 1, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_SOP" , 2, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_EOP" , 3, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 137, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 9, 138, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 9, 8, 138, "R/W", 0, 1, 0ull, 0},
|
|
{"EOT" , 17, 1, 138, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 18, 8, 138, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_26_63" , 26, 38, 138, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 9, 139, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 9, 8, 139, "R/W", 0, 1, 0ull, 0},
|
|
{"EOT" , 17, 1, 139, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 18, 8, 139, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_26_63" , 26, 38, 139, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 140, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 141, "R/W", 0, 1, 0ull, 0},
|
|
{"PORT" , 0, 6, 142, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 142, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP_SZ" , 0, 6, 143, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 143, "RAZ", 1, 1, 0, 0},
|
|
{"BACK" , 0, 4, 144, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 144, "RAZ", 1, 1, 0, 0},
|
|
{"BACK" , 0, 4, 145, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 145, "RAZ", 1, 1, 0, 0},
|
|
{"PWP" , 0, 1, 146, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_NEW" , 1, 1, 146, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_OLD" , 2, 1, 146, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRC_OFF" , 3, 1, 146, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ0" , 4, 1, 146, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ1" , 5, 1, 146, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM_WORD" , 6, 1, 146, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM0" , 7, 1, 146, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM1" , 8, 1, 146, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM2" , 9, 1, 146, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM3" , 10, 1, 146, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPQ_PBE0" , 11, 1, 146, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPQ_PBE1" , 12, 1, 146, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_POW" , 13, 1, 146, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_WP1" , 14, 1, 146, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_WQED" , 15, 1, 146, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 146, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_ENB" , 0, 36, 147, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 147, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_CNT" , 0, 64, 148, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_EN" , 0, 1, 149, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OPC_MODE" , 1, 2, 149, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PBP_EN" , 3, 1, 149, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WQE_LEND" , 4, 1, 149, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKT_LEND" , 5, 1, 149, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NADDBUF" , 6, 1, 149, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDPKT" , 7, 1, 149, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 8, 1, 149, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LEN_M8" , 9, 1, 149, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_10_63" , 10, 54, 149, "RAZ", 1, 1, 0, 0},
|
|
{"PRC_PAR0" , 0, 1, 150, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR1" , 1, 1, 150, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR2" , 2, 1, 150, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR3" , 3, 1, 150, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_SUB" , 4, 1, 150, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 150, "RAZ", 1, 1, 0, 0},
|
|
{"PRC_PAR0" , 0, 1, 151, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR1" , 1, 1, 151, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR2" , 2, 1, 151, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR3" , 3, 1, 151, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP_SUB" , 4, 1, 151, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 151, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP_SZ" , 0, 6, 152, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 152, "RAZ", 1, 1, 0, 0},
|
|
{"MB_SIZE" , 0, 12, 153, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_12_63" , 12, 52, 153, "RAZ", 1, 1, 0, 0},
|
|
{"PTR" , 0, 29, 154, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 154, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 17, 155, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_ENB" , 17, 1, 155, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 155, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 25, 156, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 156, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 3, 157, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 3, 1, 157, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 4, 29, 157, "RO", 1, 1, 0, 0},
|
|
{"PRADDR" , 33, 3, 157, "RO", 1, 1, 0, 0},
|
|
{"MAX_PKT" , 36, 3, 157, "RO", 0, 0, 5ull, 5ull},
|
|
{"RESERVED_39_63" , 39, 25, 157, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 7, 158, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 7, 1, 158, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 8, 29, 158, "RO", 1, 1, 0, 0},
|
|
{"MAX_PKT" , 37, 7, 158, "RO", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_44_63" , 44, 20, 158, "RAZ", 1, 1, 0, 0},
|
|
{"WQE_PCNT" , 0, 7, 159, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_PCNT" , 7, 7, 159, "RO", 0, 0, 0ull, 0ull},
|
|
{"PFIF_CNT" , 14, 3, 159, "RO", 0, 0, 0ull, 0ull},
|
|
{"WQEV_CNT" , 17, 1, 159, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTV_CNT" , 18, 1, 159, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 159, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 8, 160, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 8, 1, 160, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 9, 29, 160, "RO", 1, 1, 0, 0},
|
|
{"PRADDR" , 38, 8, 160, "RO", 1, 1, 0, 0},
|
|
{"WRADDR" , 46, 8, 160, "RO", 1, 1, 0, 0},
|
|
{"MAX_CNTS" , 54, 7, 160, "RO", 0, 0, 8ull, 8ull},
|
|
{"RESERVED_61_63" , 61, 3, 160, "RAZ", 1, 1, 0, 0},
|
|
{"PASS" , 0, 32, 161, "R/W", 0, 1, 0ull, 0},
|
|
{"DROP" , 32, 32, 161, "R/W", 0, 1, 0ull, 0},
|
|
{"Q0_PCNT" , 0, 32, 162, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 162, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_ENB" , 0, 36, 163, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AVG_DLY" , 36, 14, 163, "R/W", 0, 1, 0ull, 0},
|
|
{"PRB_DLY" , 50, 14, 163, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRB_CON" , 0, 32, 164, "R/W", 0, 1, 0ull, 0},
|
|
{"AVG_CON" , 32, 8, 164, "R/W", 0, 1, 0ull, 0},
|
|
{"NEW_CON" , 40, 8, 164, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_PCNT" , 48, 1, 164, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 164, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 25, 165, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT" , 25, 6, 165, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 165, "RAZ", 1, 1, 0, 0},
|
|
{"PORT_BIT" , 0, 3, 166, "R/W", 0, 0, 7ull, 7ull},
|
|
{"RESERVED_3_63" , 3, 61, 166, "RAZ", 1, 1, 0, 0},
|
|
{"WQE_POOL" , 0, 3, 167, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_3_63" , 3, 61, 167, "RAZ", 1, 1, 0, 0},
|
|
{"PTR" , 0, 29, 168, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 168, "RAZ", 1, 1, 0, 0},
|
|
{"WLB_DAT" , 0, 4, 169, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_4" , 4, 1, 169, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DT" , 5, 1, 169, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTCNT" , 6, 9, 169, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_18" , 15, 4, 169, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WLB_MSK" , 19, 4, 169, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 169, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"L2T" , 0, 5, 170, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_8" , 5, 4, 170, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VAB_VWCF" , 9, 1, 170, "RO", 0, 0, 0ull, 0ull},
|
|
{"LRF" , 10, 2, 170, "RO", 0, 0, 0ull, 0ull},
|
|
{"VWDF" , 12, 4, 170, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 170, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XRDDAT" , 0, 1, 171, "RO", 0, 0, 0ull, 0ull},
|
|
{"XRDMSK" , 1, 1, 171, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 171, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IPCBST" , 3, 1, 171, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 171, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RMDF" , 8, 4, 171, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRB" , 12, 4, 171, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 171, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LRF_ARB_MODE" , 0, 1, 172, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RFB_ARB_MODE" , 1, 1, 172, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RSP_ARB_MODE" , 2, 1, 172, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MWF_CRD" , 3, 4, 172, "R/W", 0, 0, 2ull, 2ull},
|
|
{"IDXALIAS" , 7, 1, 172, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPEN" , 8, 1, 172, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FPEMPTY" , 9, 1, 172, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FPEXP" , 10, 4, 172, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 172, "RAZ", 1, 1, 0, 0},
|
|
{"L2T" , 0, 1, 173, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2D" , 1, 1, 173, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FINV" , 2, 1, 173, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SET" , 3, 2, 173, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_5" , 5, 1, 173, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PPNUM" , 6, 1, 173, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_9" , 7, 3, 173, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_DMP" , 10, 1, 173, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LFB_ENUM" , 11, 2, 173, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 173, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DT_TAG" , 0, 29, 174, "RO", 0, 0, 0ull, 0ull},
|
|
{"DT_VLD" , 29, 1, 174, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_30" , 30, 1, 174, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DTENA" , 31, 1, 174, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 174, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_ENA" , 0, 1, 175, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_3" , 1, 3, 175, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_BASE" , 4, 27, 175, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 175, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_OFFSET" , 0, 10, 176, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 176, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VLD" , 0, 1, 177, "RO", 0, 0, 0ull, 0ull},
|
|
{"CMD" , 1, 4, 177, "RO", 0, 0, 0ull, 0ull},
|
|
{"SID" , 5, 9, 177, "RO", 0, 0, 0ull, 0ull},
|
|
{"VABNUM" , 14, 2, 177, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_17" , 16, 2, 177, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SET" , 18, 2, 177, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 177, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IHD" , 21, 1, 177, "RO", 0, 0, 0ull, 0ull},
|
|
{"ITL" , 22, 1, 177, "RO", 0, 0, 0ull, 0ull},
|
|
{"INXT" , 23, 2, 177, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_26" , 25, 2, 177, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VAM" , 27, 1, 177, "RO", 0, 0, 0ull, 0ull},
|
|
{"STCFL" , 28, 1, 177, "RO", 0, 0, 0ull, 0ull},
|
|
{"STINV" , 29, 1, 177, "RO", 0, 0, 0ull, 0ull},
|
|
{"STPND" , 30, 1, 177, "RO", 0, 0, 0ull, 0ull},
|
|
{"STCPND" , 31, 1, 177, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 177, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VLD" , 0, 1, 178, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTPRB" , 1, 1, 178, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRBRTY" , 2, 1, 178, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTMFL" , 3, 1, 178, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTVTM" , 4, 1, 178, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTRSC" , 5, 1, 178, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTRSP" , 6, 1, 178, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTDT" , 7, 1, 178, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTRDA" , 8, 1, 178, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTM" , 9, 1, 178, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWRM" , 10, 1, 178, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWHF" , 11, 1, 178, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWHP" , 12, 1, 178, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTDQ" , 13, 1, 178, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTDW" , 14, 1, 178, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTRSP" , 15, 1, 178, "RO", 0, 0, 0ull, 0ull},
|
|
{"BID" , 16, 2, 178, "RO", 0, 0, 0ull, 0ull},
|
|
{"DSGOING" , 18, 1, 178, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 178, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_IDX" , 0, 8, 179, "RO", 0, 0, 0ull, 0ull},
|
|
{"LFB_TAG" , 8, 19, 179, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_63" , 27, 37, 179, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_HWM" , 0, 2, 180, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_2_3" , 2, 2, 180, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STPARTDIS" , 4, 1, 180, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 180, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PFCNT0" , 0, 36, 181, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 181, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT0SEL" , 0, 6, 182, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0CLR" , 6, 1, 182, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0ENA" , 7, 1, 182, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1SEL" , 8, 6, 182, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1CLR" , 14, 1, 182, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1ENA" , 15, 1, 182, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2SEL" , 16, 6, 182, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2CLR" , 22, 1, 182, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2ENA" , 23, 1, 182, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3SEL" , 24, 6, 182, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3CLR" , 30, 1, 182, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3ENA" , 31, 1, 182, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0RDCLR" , 32, 1, 182, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1RDCLR" , 33, 1, 182, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2RDCLR" , 34, 1, 182, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3RDCLR" , 35, 1, 182, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 182, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK0" , 0, 4, 183, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 183, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSKIOB" , 0, 4, 184, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 184, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q0STAT" , 0, 34, 185, "RO", 0, 0, 0ull, 0ull},
|
|
{"FTL" , 34, 1, 185, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_35_63" , 35, 29, 185, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q1STAT" , 0, 34, 186, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 186, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q2STAT" , 0, 34, 187, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 187, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q3STAT" , 0, 34, 188, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 188, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 0, 1, 189, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_INTENA" , 1, 1, 189, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DED_INTENA" , 2, 1, 189, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 3, 1, 189, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 4, 1, 189, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BMHCLSEL" , 5, 1, 189, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 189, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 0, 9, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_10" , 9, 2, 190, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSET" , 11, 2, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_13" , 13, 1, 190, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FOWMSK" , 14, 4, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 190, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW0" , 0, 10, 191, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW1" , 10, 10, 191, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 191, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW2" , 0, 10, 192, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW3" , 10, 10, 192, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 192, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q0FUS" , 0, 34, 193, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 193, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q1FUS" , 0, 34, 194, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 194, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q2FUS" , 0, 34, 195, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 195, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q3FUS" , 0, 34, 196, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRIP_64K" , 34, 1, 196, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_35_63" , 35, 29, 196, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 0, 1, 197, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_INTENA" , 1, 1, 197, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DED_INTENA" , 2, 1, 197, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 3, 1, 197, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 4, 1, 197, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FSYN" , 5, 6, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 11, 8, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_20" , 19, 2, 197, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSET" , 21, 2, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 197, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCKERR" , 24, 1, 197, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK_INTENA" , 25, 1, 197, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LCKERR2" , 26, 1, 197, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK_INTENA2" , 27, 1, 197, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_28_63" , 28, 36, 197, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PCTL_DAT" , 0, 4, 198, "R/W", 0, 1, 0ull, 0},
|
|
{"PCTL_CMD" , 4, 4, 198, "R/W", 0, 1, 0ull, 0},
|
|
{"PCTL_CLK" , 8, 4, 198, "R/W", 0, 1, 0ull, 0},
|
|
{"PCTL_CSR" , 12, 4, 198, "R/W", 0, 1, 15ull, 0},
|
|
{"NCTL_DAT" , 16, 4, 198, "R/W", 0, 1, 0ull, 0},
|
|
{"NCTL_CMD" , 20, 4, 198, "R/W", 0, 1, 0ull, 0},
|
|
{"NCTL_CLK" , 24, 4, 198, "R/W", 0, 1, 0ull, 0},
|
|
{"NCTL_CSR" , 28, 4, 198, "R/W", 0, 1, 15ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 198, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DIC" , 0, 2, 199, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QS_DIC" , 2, 2, 199, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TSKW" , 4, 2, 199, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SIL_LAT" , 6, 2, 199, "R/W", 0, 0, 1ull, 1ull},
|
|
{"BPRCH" , 8, 1, 199, "R/W", 0, 1, 0ull, 0},
|
|
{"FPRCH2" , 9, 1, 199, "R/W", 0, 0, 0ull, 1ull},
|
|
{"MODE32B" , 10, 1, 199, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRESET" , 11, 1, 199, "R/W", 0, 0, 1ull, 0ull},
|
|
{"INORDER_MRF" , 12, 1, 199, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INORDER_MWF" , 13, 1, 199, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"R2R_SLOT" , 14, 1, 199, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RDIMM_ENA" , 15, 1, 199, "R/W", 0, 1, 0ull, 0},
|
|
{"PLL_BYPASS" , 16, 1, 199, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PLL_DIV2" , 17, 1, 199, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAX_WRITE_BATCH" , 18, 4, 199, "R/W", 0, 0, 8ull, 8ull},
|
|
{"XOR_BANK" , 22, 1, 199, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SLOW_SCF" , 23, 1, 199, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DDR__PCTL" , 24, 4, 199, "RO", 1, 1, 0, 0},
|
|
{"DDR__NCTL" , 28, 4, 199, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 199, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_LAYOUT" , 0, 2, 200, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 200, "RAZ", 1, 1, 0, 0},
|
|
{"DCLKCNT_HI" , 0, 32, 201, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 201, "RAZ", 1, 1, 0, 0},
|
|
{"DCLKCNT_LO" , 0, 32, 202, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 202, "RAZ", 1, 1, 0, 0},
|
|
{"DDR2" , 0, 1, 203, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_1" , 1, 1, 203, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DLL90_BYP" , 2, 1, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLL90_VLU" , 3, 5, 203, "R/W", 0, 1, 0ull, 0},
|
|
{"QDLL_ENA" , 8, 1, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ODT_ENA" , 9, 1, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DDR2T" , 10, 1, 203, "R/W", 0, 1, 0ull, 0},
|
|
{"CRIP_MODE" , 11, 1, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TFAW" , 12, 5, 203, "R/W", 0, 0, 0ull, 9ull},
|
|
{"DDR_EOF" , 17, 4, 203, "R/W", 0, 0, 2ull, 2ull},
|
|
{"SILO_HC" , 21, 1, 203, "R/W", 0, 1, 1ull, 0},
|
|
{"TWR" , 22, 3, 203, "R/W", 0, 0, 3ull, 1ull},
|
|
{"BWCNT" , 25, 1, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POCAS" , 26, 1, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDLAT" , 27, 3, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BURST8" , 30, 1, 203, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BANK8" , 31, 1, 203, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 203, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CLK" , 0, 5, 204, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CMD" , 5, 5, 204, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DQ" , 10, 5, 204, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 204, "RAZ", 1, 1, 0, 0},
|
|
{"MRDSYN0" , 0, 8, 205, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN1" , 8, 8, 205, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN2" , 16, 8, 205, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN3" , 24, 8, 205, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 205, "RAZ", 1, 1, 0, 0},
|
|
{"FCOL" , 0, 12, 206, "RO", 0, 0, 0ull, 0ull},
|
|
{"FROW" , 12, 14, 206, "RO", 0, 0, 0ull, 0ull},
|
|
{"FBANK" , 26, 3, 206, "RO", 0, 0, 0ull, 0ull},
|
|
{"FBUNK" , 29, 1, 206, "RO", 0, 0, 0ull, 0ull},
|
|
{"FDIMM" , 30, 2, 206, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 206, "RAZ", 1, 1, 0, 0},
|
|
{"IFBCNT_HI" , 0, 32, 207, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 207, "RAZ", 1, 1, 0, 0},
|
|
{"IFBCNT_LO" , 0, 32, 208, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 208, "RAZ", 1, 1, 0, 0},
|
|
{"INIT_START" , 0, 1, 209, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 1, 1, 209, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ROW_LSB" , 2, 3, 209, "R/W", 0, 1, 3ull, 0},
|
|
{"PBANK_LSB" , 5, 4, 209, "R/W", 0, 1, 5ull, 0},
|
|
{"REF_INT" , 9, 6, 209, "R/W", 0, 0, 1ull, 2ull},
|
|
{"TCL" , 15, 4, 209, "R/W", 0, 1, 3ull, 0},
|
|
{"INTR_SEC_ENA" , 19, 1, 209, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INTR_DED_ENA" , 20, 1, 209, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 21, 4, 209, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 25, 4, 209, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BUNK_ENA" , 29, 1, 209, "R/W", 0, 1, 0ull, 0},
|
|
{"SILO_QC" , 30, 1, 209, "R/W", 0, 1, 0ull, 0},
|
|
{"RESET" , 31, 1, 209, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 209, "RAZ", 1, 1, 0, 0},
|
|
{"TRAS" , 0, 5, 210, "R/W", 0, 0, 12ull, 12ull},
|
|
{"TRCD" , 5, 4, 210, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TWTR" , 9, 4, 210, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TRP" , 13, 4, 210, "R/W", 0, 0, 5ull, 4ull},
|
|
{"TRFC" , 17, 5, 210, "R/W", 0, 0, 6ull, 7ull},
|
|
{"TMRD" , 22, 3, 210, "R/W", 0, 0, 2ull, 2ull},
|
|
{"CASLAT" , 25, 3, 210, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TRRD" , 28, 3, 210, "R/W", 0, 0, 2ull, 2ull},
|
|
{"COMP_BYPASS" , 31, 1, 210, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 210, "RAZ", 1, 1, 0, 0},
|
|
{"OPSCNT_HI" , 0, 32, 211, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 211, "RAZ", 1, 1, 0, 0},
|
|
{"OPSCNT_LO" , 0, 32, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 212, "RAZ", 1, 1, 0, 0},
|
|
{"BWCTL" , 0, 4, 213, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BWUPD" , 4, 1, 213, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 213, "RAZ", 1, 1, 0, 0},
|
|
{"RODT_LO0" , 0, 4, 214, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_LO1" , 4, 4, 214, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_LO2" , 8, 4, 214, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_LO3" , 12, 4, 214, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI0" , 16, 4, 214, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI1" , 20, 4, 214, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI2" , 24, 4, 214, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI3" , 28, 4, 214, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_32_63" , 32, 32, 214, "RAZ", 1, 1, 0, 0},
|
|
{"WODT_D0_R0" , 0, 8, 215, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D0_R1" , 8, 8, 215, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D1_R0" , 16, 8, 215, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D1_R1" , 24, 8, 215, "R/W", 0, 0, 255ull, 255ull},
|
|
{"RESERVED_32_63" , 32, 32, 215, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WODT_D2_R0" , 0, 8, 216, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D2_R1" , 8, 8, 216, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D3_R0" , 16, 8, 216, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D3_R1" , 24, 8, 216, "R/W", 0, 0, 255ull, 255ull},
|
|
{"RESERVED_32_63" , 32, 32, 216, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"NCBI" , 0, 1, 217, "RO", 0, 0, 0ull, 0ull},
|
|
{"LOC" , 1, 1, 217, "RO", 0, 0, 0ull, 0ull},
|
|
{"NCBO_0" , 2, 1, 217, "RO", 0, 0, 0ull, 0ull},
|
|
{"NCBO_1" , 3, 1, 217, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 217, "RAZ", 1, 1, 0, 0},
|
|
{"ADR_ERR" , 0, 1, 218, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WAIT_ERR" , 1, 1, 218, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 218, "RAZ", 1, 1, 0, 0},
|
|
{"ADR_INT" , 0, 1, 219, "R/W", 0, 1, 0ull, 0},
|
|
{"WAIT_INT" , 1, 1, 219, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 219, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 220, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 3, 5, 220, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 220, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 221, "RAZ", 1, 1, 0, 0},
|
|
{"BASE" , 3, 25, 221, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_30" , 28, 3, 221, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 31, 1, 221, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 221, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 222, "R/W", 1, 1, 0, 0},
|
|
{"BASE" , 0, 16, 223, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 16, 12, 223, "R/W", 0, 1, 0ull, 0},
|
|
{"WIDTH" , 28, 1, 223, "R/W", 0, 1, 0ull, 0},
|
|
{"ALE" , 29, 1, 223, "R/W", 0, 1, 0ull, 0},
|
|
{"ORBIT" , 30, 1, 223, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 31, 1, 223, "R/W", 0, 1, 0ull, 0},
|
|
{"OE_EXT" , 32, 2, 223, "R/W", 0, 1, 0ull, 0},
|
|
{"WE_EXT" , 34, 2, 223, "R/W", 0, 1, 0ull, 0},
|
|
{"SAM" , 36, 1, 223, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_37_63" , 37, 27, 223, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 6, 224, "R/W", 0, 1, 63ull, 0},
|
|
{"CE" , 6, 6, 224, "R/W", 0, 1, 63ull, 0},
|
|
{"OE" , 12, 6, 224, "R/W", 0, 1, 63ull, 0},
|
|
{"WE" , 18, 6, 224, "R/W", 0, 1, 63ull, 0},
|
|
{"RD_HLD" , 24, 6, 224, "R/W", 0, 1, 63ull, 0},
|
|
{"WR_HLD" , 30, 6, 224, "R/W", 0, 1, 63ull, 0},
|
|
{"PAUSE" , 36, 6, 224, "R/W", 0, 1, 63ull, 0},
|
|
{"WAIT" , 42, 6, 224, "R/W", 0, 1, 63ull, 0},
|
|
{"PAGE" , 48, 6, 224, "R/W", 0, 1, 63ull, 0},
|
|
{"ALE" , 54, 6, 224, "R/W", 0, 1, 63ull, 0},
|
|
{"PAGES" , 60, 2, 224, "R/W", 0, 1, 0ull, 0},
|
|
{"WAITM" , 62, 1, 224, "R/W", 0, 1, 0ull, 0},
|
|
{"PAGEM" , 63, 1, 224, "R/W", 0, 1, 0ull, 0},
|
|
{"FIF_THR" , 0, 6, 225, "R/W", 0, 0, 26ull, 26ull},
|
|
{"RESERVED_6_7" , 6, 2, 225, "RAZ", 1, 1, 0, 0},
|
|
{"FIF_CNT" , 8, 6, 225, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_63" , 14, 50, 225, "RAZ", 1, 1, 0, 0},
|
|
{"MAN_INFO" , 0, 32, 226, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 226, "RAZ", 1, 1, 0, 0},
|
|
{"MAN_INFO" , 0, 32, 227, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 227, "RAZ", 1, 1, 0, 0},
|
|
{"PP_DIS" , 0, 1, 228, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_1_11" , 1, 11, 228, "RAZ", 1, 1, 0, 0},
|
|
{"PLL_OFF" , 12, 4, 228, "RO", 1, 1, 0, 0},
|
|
{"CHIP_ID" , 16, 8, 228, "RO", 1, 1, 0, 0},
|
|
{"BIST_DIS" , 24, 1, 228, "RO", 1, 1, 0, 0},
|
|
{"RST_SHT" , 25, 1, 228, "RO", 1, 1, 0, 0},
|
|
{"NOCRYPTO" , 26, 1, 228, "RO", 1, 1, 0, 0},
|
|
{"NOMUL" , 27, 1, 228, "RO", 1, 1, 0, 0},
|
|
{"NODFA_CP2" , 28, 1, 228, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 228, "RAZ", 1, 1, 0, 0},
|
|
{"ICACHE" , 0, 24, 229, "RO", 1, 1, 0, 0},
|
|
{"NODFA_DTE" , 24, 1, 229, "RO", 1, 1, 0, 0},
|
|
{"NOZIP" , 25, 1, 229, "RO", 1, 1, 0, 0},
|
|
{"EFUS_IGN" , 26, 1, 229, "RO", 1, 1, 0, 0},
|
|
{"EFUS_LCK" , 27, 1, 229, "RO", 1, 1, 0, 0},
|
|
{"BAR2_EN" , 28, 1, 229, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_30" , 29, 2, 229, "RAZ", 1, 1, 0, 0},
|
|
{"PLL_DIV4" , 31, 1, 229, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 229, "RAZ", 1, 1, 0, 0},
|
|
{"PROG" , 0, 1, 230, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_1_63" , 1, 63, 230, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 7, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 231, "RAZ", 1, 1, 0, 0},
|
|
{"EFUSE" , 8, 1, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 231, "RAZ", 1, 1, 0, 0},
|
|
{"PEND" , 12, 1, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 231, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 16, 8, 231, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_24_63" , 24, 40, 231, "RAZ", 1, 1, 0, 0},
|
|
{"REPAIR0" , 0, 14, 232, "RO", 0, 0, 0ull, 0ull},
|
|
{"REPAIR1" , 14, 14, 232, "RO", 0, 0, 0ull, 0ull},
|
|
{"REPAIR2" , 28, 14, 232, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_42_63" , 42, 22, 232, "RAZ", 1, 1, 0, 0},
|
|
{"TOO_MANY" , 0, 1, 233, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 233, "RAZ", 1, 1, 0, 0},
|
|
{"KEY" , 0, 24, 234, "R/W", 0, 0, 0ull, 5071723ull},
|
|
{"RESERVED_24_63" , 24, 40, 234, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 10, 235, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_10_63" , 10, 54, 235, "RAZ", 1, 1, 0, 0},
|
|
{"BW_CTL" , 0, 5, 236, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 236, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SETTING" , 0, 17, 237, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_17_63" , 17, 47, 237, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ST_INT" , 0, 1, 238, "R/W1C", 0, 1, 0ull, 0},
|
|
{"TS_INT" , 1, 1, 238, "R/W1C", 0, 1, 0ull, 0},
|
|
{"CORE_INT" , 2, 1, 238, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_3" , 3, 1, 238, "RAZ", 1, 1, 0, 0},
|
|
{"ST_EN" , 4, 1, 238, "R/W", 0, 1, 0ull, 0},
|
|
{"TS_EN" , 5, 1, 238, "R/W", 0, 1, 0ull, 0},
|
|
{"CORE_EN" , 6, 1, 238, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_7" , 7, 1, 238, "RAZ", 1, 1, 0, 0},
|
|
{"SDA_OVR" , 8, 1, 238, "R/W", 0, 1, 0ull, 0},
|
|
{"SCL_OVR" , 9, 1, 238, "R/W", 0, 1, 0ull, 0},
|
|
{"SDA" , 10, 1, 238, "RO", 1, 1, 0, 0},
|
|
{"SCL" , 11, 1, 238, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_12_63" , 12, 52, 238, "RAZ", 1, 1, 0, 0},
|
|
{"D" , 0, 32, 239, "R/W", 0, 1, 0ull, 0},
|
|
{"EOP_IA" , 32, 3, 239, "R/W", 0, 1, 0ull, 0},
|
|
{"IA" , 35, 5, 239, "R/W", 0, 1, 0ull, 0},
|
|
{"A" , 40, 10, 239, "R/W", 0, 1, 0ull, 0},
|
|
{"SCR" , 50, 2, 239, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 52, 3, 239, "R/W", 0, 1, 0ull, 0},
|
|
{"SOVR" , 55, 1, 239, "R/W", 0, 1, 0ull, 0},
|
|
{"R" , 56, 1, 239, "R/W", 0, 1, 0ull, 0},
|
|
{"OP" , 57, 4, 239, "R/W", 0, 1, 0ull, 0},
|
|
{"EIA" , 61, 1, 239, "R/W", 0, 1, 0ull, 0},
|
|
{"SLONLY" , 62, 1, 239, "R/W", 0, 1, 0ull, 0},
|
|
{"V" , 63, 1, 239, "RC/W", 0, 1, 0ull, 0},
|
|
{"D" , 0, 32, 240, "R/W", 0, 1, 0ull, 0},
|
|
{"IA" , 32, 8, 240, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_40_63" , 40, 24, 240, "RAZ", 1, 1, 0, 0},
|
|
{"D" , 0, 32, 241, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_32_61" , 32, 30, 241, "RAZ", 1, 1, 0, 0},
|
|
{"V" , 62, 2, 241, "RC/W", 0, 1, 0ull, 0},
|
|
{"DLH" , 0, 8, 242, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 242, "RAZ", 1, 1, 0, 0},
|
|
{"DLL" , 0, 8, 243, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 243, "RAZ", 1, 1, 0, 0},
|
|
{"FAR" , 0, 1, 244, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 244, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 245, "WO", 0, 1, 0ull, 0},
|
|
{"RXFR" , 1, 1, 245, "WO", 0, 1, 0ull, 0},
|
|
{"TXFR" , 2, 1, 245, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_3" , 3, 1, 245, "RAZ", 0, 1, 0ull, 0},
|
|
{"TXTRIG" , 4, 2, 245, "WO", 0, 1, 0ull, 0},
|
|
{"RXTRIG" , 6, 2, 245, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 245, "RAZ", 1, 1, 0, 0},
|
|
{"HTX" , 0, 1, 246, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 246, "RAZ", 1, 1, 0, 0},
|
|
{"ERBFI" , 0, 1, 247, "R/W", 0, 1, 0ull, 0},
|
|
{"ETBEI" , 1, 1, 247, "R/W", 0, 1, 0ull, 0},
|
|
{"ELSI" , 2, 1, 247, "R/W", 0, 1, 0ull, 0},
|
|
{"EDSSI" , 3, 1, 247, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_6" , 4, 3, 247, "RAZ", 0, 1, 0ull, 0},
|
|
{"PTIME" , 7, 1, 247, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 247, "RAZ", 1, 1, 0, 0},
|
|
{"IID" , 0, 4, 248, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_4_5" , 4, 2, 248, "RAZ", 0, 1, 0ull, 0},
|
|
{"FEN" , 6, 2, 248, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 248, "RAZ", 1, 1, 0, 0},
|
|
{"CLS" , 0, 2, 249, "R/W", 0, 1, 0ull, 0},
|
|
{"STOP" , 2, 1, 249, "R/W", 0, 1, 0ull, 0},
|
|
{"PEN" , 3, 1, 249, "R/W", 0, 1, 0ull, 0},
|
|
{"EPS" , 4, 1, 249, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_5" , 5, 1, 249, "RAZ", 0, 1, 0ull, 0},
|
|
{"BRK" , 6, 1, 249, "R/W", 0, 1, 0ull, 0},
|
|
{"DLAB" , 7, 1, 249, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 249, "RAZ", 1, 1, 0, 0},
|
|
{"DR" , 0, 1, 250, "RO", 0, 1, 0ull, 0},
|
|
{"OE" , 1, 1, 250, "RC", 0, 1, 0ull, 0},
|
|
{"PE" , 2, 1, 250, "RC", 0, 1, 0ull, 0},
|
|
{"FE" , 3, 1, 250, "RC", 0, 1, 0ull, 0},
|
|
{"BI" , 4, 1, 250, "RC", 0, 1, 0ull, 0},
|
|
{"THRE" , 5, 1, 250, "RO", 0, 1, 1ull, 0},
|
|
{"TEMT" , 6, 1, 250, "RO", 0, 1, 1ull, 0},
|
|
{"FERR" , 7, 1, 250, "RC", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 250, "RAZ", 1, 1, 0, 0},
|
|
{"DTR" , 0, 1, 251, "R/W", 0, 1, 0ull, 0},
|
|
{"RTS" , 1, 1, 251, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT1" , 2, 1, 251, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT2" , 3, 1, 251, "R/W", 0, 1, 0ull, 0},
|
|
{"LOOP" , 4, 1, 251, "R/W", 0, 1, 0ull, 0},
|
|
{"AFCE" , 5, 1, 251, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 251, "RAZ", 0, 1, 0ull, 0},
|
|
{"DCTS" , 0, 1, 252, "RC", 0, 1, 0ull, 0},
|
|
{"DDSR" , 1, 1, 252, "RC", 0, 1, 0ull, 0},
|
|
{"TERI" , 2, 1, 252, "RC", 0, 1, 0ull, 0},
|
|
{"DDCD" , 3, 1, 252, "RC", 0, 1, 0ull, 0},
|
|
{"CTS" , 4, 1, 252, "RO", 1, 1, 0, 0},
|
|
{"DSR" , 5, 1, 252, "RO", 0, 1, 0ull, 0},
|
|
{"RI" , 6, 1, 252, "RO", 0, 1, 0ull, 0},
|
|
{"DCD" , 7, 1, 252, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 252, "RAZ", 1, 1, 0, 0},
|
|
{"RBR" , 0, 8, 253, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 253, "RAZ", 1, 1, 0, 0},
|
|
{"RFL" , 0, 7, 254, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 254, "RAZ", 1, 1, 0, 0},
|
|
{"RFWD" , 0, 8, 255, "WO", 0, 1, 0ull, 0},
|
|
{"RFPE" , 8, 1, 255, "WO", 0, 1, 0ull, 0},
|
|
{"RFFE" , 9, 1, 255, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_10_63" , 10, 54, 255, "RAZ", 1, 1, 0, 0},
|
|
{"SBCR" , 0, 1, 256, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 256, "RAZ", 1, 1, 0, 0},
|
|
{"SCR" , 0, 8, 257, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 257, "RAZ", 1, 1, 0, 0},
|
|
{"SFE" , 0, 1, 258, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 258, "RAZ", 1, 1, 0, 0},
|
|
{"USR" , 0, 1, 259, "WO", 0, 1, 0ull, 0},
|
|
{"SRFR" , 1, 1, 259, "WO", 0, 1, 0ull, 0},
|
|
{"STFR" , 2, 1, 259, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_63" , 3, 61, 259, "RAZ", 1, 1, 0, 0},
|
|
{"SRT" , 0, 2, 260, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 260, "RAZ", 1, 1, 0, 0},
|
|
{"SRTS" , 0, 1, 261, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 261, "RAZ", 1, 1, 0, 0},
|
|
{"STT" , 0, 2, 262, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 262, "RAZ", 1, 1, 0, 0},
|
|
{"TFL" , 0, 7, 263, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 263, "RAZ", 1, 1, 0, 0},
|
|
{"TFR" , 0, 8, 264, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 264, "RAZ", 1, 1, 0, 0},
|
|
{"THR" , 0, 8, 265, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 265, "RAZ", 1, 1, 0, 0},
|
|
{"BUSY" , 0, 1, 266, "RO", 0, 1, 0ull, 0},
|
|
{"TFNF" , 1, 1, 266, "RO", 0, 1, 1ull, 0},
|
|
{"TFE" , 2, 1, 266, "RO", 0, 1, 1ull, 0},
|
|
{"RFNE" , 3, 1, 266, "RO", 0, 1, 0ull, 0},
|
|
{"RFF" , 4, 1, 266, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 266, "RAZ", 1, 1, 0, 0},
|
|
{"ENABLE" , 0, 1, 267, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDLELO" , 1, 1, 267, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLK_CONT" , 2, 1, 267, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WIREOR" , 3, 1, 267, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LSBFIRST" , 4, 1, 267, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_ENA" , 5, 1, 267, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CSENA" , 6, 1, 267, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CSHI" , 7, 1, 267, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDLECLKS" , 8, 2, 267, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRITX" , 10, 1, 267, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CSLATE" , 11, 1, 267, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_15" , 12, 4, 267, "RAZ", 1, 1, 0, 0},
|
|
{"CLKDIV" , 16, 13, 267, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 267, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 8, 268, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_8_63" , 8, 56, 268, "RAZ", 1, 1, 0, 0},
|
|
{"BUSY" , 0, 1, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_7" , 1, 7, 269, "RAZ", 1, 1, 0, 0},
|
|
{"RXNUM" , 8, 5, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 269, "RAZ", 1, 1, 0, 0},
|
|
{"TOTNUM" , 0, 5, 270, "WO", 1, 0, 0, 2ull},
|
|
{"RESERVED_5_7" , 5, 3, 270, "RAZ", 1, 1, 0, 0},
|
|
{"TXNUM" , 8, 5, 270, "WO", 1, 0, 0, 1ull},
|
|
{"RESERVED_13_15" , 13, 3, 270, "RAZ", 1, 1, 0, 0},
|
|
{"LEAVECS" , 16, 1, 270, "WO", 1, 0, 0, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 270, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 271, "RAZ", 1, 1, 0, 0},
|
|
{"BADDR" , 3, 61, 271, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_0_2" , 0, 3, 272, "RAZ", 1, 1, 0, 0},
|
|
{"BADDR" , 3, 61, 272, "R/W", 0, 1, 0ull, 0},
|
|
{"DPI_BS" , 0, 1, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"PDF_BS" , 1, 1, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"DOB_BS" , 2, 1, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"NUS_BS" , 3, 1, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"POS_BS" , 4, 1, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_7" , 5, 3, 273, "RAZ", 1, 1, 0, 0},
|
|
{"POF0_BS" , 8, 1, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"PIG_BS" , 9, 1, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"PGF_BS" , 10, 1, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"RDNL_BS" , 11, 1, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCAD_BS" , 12, 1, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCAC_BS" , 13, 1, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"RDN_BS" , 14, 1, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCN_BS" , 15, 1, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCNC_BS" , 16, 1, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"RDP_BS" , 17, 1, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF_BS" , 18, 1, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSR_BS" , 19, 1, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 273, "RAZ", 1, 1, 0, 0},
|
|
{"BSIZE" , 0, 16, 274, "R/W", 0, 1, 1024ull, 0},
|
|
{"ISIZE" , 16, 7, 274, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_23_63" , 23, 41, 274, "RAZ", 1, 1, 0, 0},
|
|
{"TIMER" , 0, 10, 275, "R/W", 0, 0, 0ull, 50ull},
|
|
{"RESERVED_10_31" , 10, 22, 275, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX_WORD" , 32, 5, 275, "R/W", 0, 0, 2ull, 0ull},
|
|
{"RESERVED_37_39" , 37, 3, 275, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WAIT_COM" , 40, 1, 275, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCI_WDIS" , 41, 1, 275, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INS0_64B" , 42, 1, 275, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_43_45" , 43, 3, 275, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"INS0_ENB" , 46, 1, 275, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_47_49" , 47, 3, 275, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OUT0_ENB" , 50, 1, 275, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_51_53" , 51, 3, 275, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DIS_PNIW" , 54, 1, 275, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CHIP_REV" , 55, 8, 275, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_63_63" , 63, 1, 275, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_SEL" , 0, 16, 276, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 276, "RAZ", 1, 1, 0, 0},
|
|
{"CSIZE" , 0, 14, 277, "R/W", 0, 1, 0ull, 0},
|
|
{"LP_ENB" , 14, 1, 277, "R/W", 0, 0, 0ull, 1ull},
|
|
{"HP_ENB" , 15, 1, 277, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O_MODE" , 16, 1, 277, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O_ES" , 17, 2, 277, "R/W", 0, 1, 0ull, 0},
|
|
{"O_NS" , 19, 1, 277, "R/W", 0, 1, 0ull, 0},
|
|
{"O_RO" , 20, 1, 277, "R/W", 0, 1, 0ull, 0},
|
|
{"O_ADD1" , 21, 1, 277, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA_QUE" , 22, 3, 277, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB_ICHK" , 25, 9, 277, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB_DENB" , 34, 1, 277, "R/W", 0, 0, 0ull, 1ull},
|
|
{"B0_LEND" , 35, 1, 277, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 277, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 32, 278, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 7, 278, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_39_63" , 39, 25, 278, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 279, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 36, 4, 279, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 279, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 32, 280, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 7, 280, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_39_63" , 39, 25, 280, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 281, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 36, 4, 281, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 281, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 16, 282, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 282, "RAZ", 1, 1, 0, 0},
|
|
{"SADDR" , 0, 36, 283, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 283, "RAZ", 1, 1, 0, 0},
|
|
{"ROR" , 0, 1, 284, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR" , 1, 2, 284, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR" , 3, 1, 284, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_CSR" , 4, 1, 284, "R/W", 0, 0, 0ull, 1ull},
|
|
{"D_ROR" , 5, 1, 284, "R/W", 0, 1, 0ull, 0},
|
|
{"D_ESR" , 6, 2, 284, "R/W", 0, 1, 0ull, 0},
|
|
{"D_NSR" , 8, 1, 284, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP_DHI" , 9, 13, 284, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_22_63" , 22, 42, 284, "RAZ", 1, 1, 0, 0},
|
|
{"RML_RTO" , 0, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RML_WTO" , 1, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCI_RSL" , 2, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PO0_2SML" , 3, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_4_6" , 4, 3, 285, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"I0_RTOUT" , 7, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_8_10" , 8, 3, 285, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"I0_OVERF" , 11, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_12_14" , 12, 3, 285, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"P0_RTOUT" , 15, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_16_18" , 16, 3, 285, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"P0_PERR" , 19, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_20_22" , 20, 3, 285, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"G0_RTOUT" , 23, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_24_26" , 24, 3, 285, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"P0_PPERR" , 27, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_28_30" , 28, 3, 285, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"P0_PTOUT" , 31, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_32_34" , 32, 3, 285, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"I0_PPERR" , 35, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_36_38" , 36, 3, 285, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"WIN_RTO" , 39, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P_DPERR" , 40, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 41, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FCR_S_E" , 42, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FCR_A_F" , 43, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCR_S_E" , 44, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCR_A_F" , 45, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q2_S_E" , 46, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q2_A_F" , 47, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q3_S_E" , 48, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q3_A_F" , 49, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"COM_S_E" , 50, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"COM_A_F" , 51, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PNC_S_E" , 52, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PNC_A_F" , 53, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RWX_S_E" , 54, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RDX_S_E" , 55, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCF_P_E" , 56, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCF_P_F" , 57, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PDF_P_E" , 58, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PDF_P_F" , 59, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q1_S_E" , 60, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q1_A_F" , 61, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_62_63" , 62, 2, 285, "RAZ", 1, 1, 0, 0},
|
|
{"RML_RTO" , 0, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RML_WTO" , 1, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCI_RSL" , 2, 1, 286, "RO", 0, 0, 0ull, 0ull},
|
|
{"PO0_2SML" , 3, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_6" , 4, 3, 286, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"I0_RTOUT" , 7, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_10" , 8, 3, 286, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"I0_OVERF" , 11, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_14" , 12, 3, 286, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"P0_RTOUT" , 15, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_18" , 16, 3, 286, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"P0_PERR" , 19, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_22" , 20, 3, 286, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"G0_RTOUT" , 23, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_26" , 24, 3, 286, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"P0_PPERR" , 27, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_30" , 28, 3, 286, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"P0_PTOUT" , 31, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_34" , 32, 3, 286, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"I0_PPERR" , 35, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_38" , 36, 3, 286, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WIN_RTO" , 39, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_DPERR" , 40, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IOBDMA" , 41, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCR_S_E" , 42, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCR_A_F" , 43, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCR_S_E" , 44, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCR_A_F" , 45, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_S_E" , 46, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_A_F" , 47, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_S_E" , 48, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_A_F" , 49, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COM_S_E" , 50, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COM_A_F" , 51, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PNC_S_E" , 52, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PNC_A_F" , 53, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RWX_S_E" , 54, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RDX_S_E" , 55, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCF_P_E" , 56, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCF_P_F" , 57, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PDF_P_E" , 58, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PDF_P_F" , 59, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_S_E" , 60, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_A_F" , 61, 1, 286, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_62_63" , 62, 2, 286, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 16, 287, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 287, "RAZ", 1, 1, 0, 0},
|
|
{"SADDR" , 0, 36, 288, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 288, "RAZ", 1, 1, 0, 0},
|
|
{"BA" , 0, 28, 289, "R/W", 0, 1, 0ull, 0},
|
|
{"ROW" , 28, 1, 289, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR" , 29, 1, 289, "R/W", 0, 1, 0ull, 0},
|
|
{"NSW" , 30, 1, 289, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR" , 31, 1, 289, "R/W", 0, 1, 0ull, 0},
|
|
{"ESW" , 32, 2, 289, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR" , 34, 2, 289, "R/W", 0, 1, 0ull, 0},
|
|
{"NMERGE" , 36, 1, 289, "R/W", 0, 1, 0ull, 0},
|
|
{"SHORTL" , 37, 1, 289, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_38_63" , 38, 26, 289, "RAZ", 1, 1, 0, 0},
|
|
{"INT_VEC" , 0, 64, 290, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 0, 32, 291, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 291, "RAZ", 1, 1, 0, 0},
|
|
{"ROR_SL0" , 0, 1, 292, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR_SL0" , 1, 1, 292, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR_SL0" , 2, 2, 292, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_15" , 4, 12, 292, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IPTR_O0" , 16, 1, 292, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_17_23" , 17, 7, 292, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"O0_CSRM" , 24, 1, 292, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_25_27" , 25, 3, 292, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"O0_RO" , 28, 1, 292, "R/W", 0, 1, 0ull, 0},
|
|
{"O0_NS" , 29, 1, 292, "R/W", 0, 1, 0ull, 0},
|
|
{"O0_ES" , 30, 2, 292, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_43" , 32, 12, 292, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"P0_BMODE" , 44, 1, 292, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_45_63" , 45, 19, 292, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"NADDR" , 0, 61, 293, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 61, 2, 293, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_63_63" , 63, 1, 293, "RAZ", 1, 1, 0, 0},
|
|
{"NADDR" , 0, 61, 294, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 61, 3, 294, "RO", 0, 0, 0ull, 0ull},
|
|
{"AVAIL" , 0, 32, 295, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 6, 295, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 295, "RAZ", 1, 1, 0, 0},
|
|
{"AVAIL" , 0, 32, 296, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 5, 296, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 296, "RAZ", 1, 1, 0, 0},
|
|
{"RD_BRST" , 0, 7, 297, "R/W", 0, 0, 17ull, 64ull},
|
|
{"WR_BRST" , 7, 7, 297, "R/W", 0, 0, 16ull, 64ull},
|
|
{"RESERVED_14_63" , 14, 50, 297, "RAZ", 1, 1, 0, 0},
|
|
{"PARK_DEV" , 0, 3, 298, "R/W", 0, 1, 0ull, 0},
|
|
{"PARK_MOD" , 3, 1, 298, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 4, 1, 298, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 298, "RAZ", 1, 1, 0, 0},
|
|
{"CMD_SIZE" , 0, 11, 299, "R/W", 0, 0, 9ull, 9ull},
|
|
{"RESERVED_11_63" , 11, 53, 299, "RAZ", 1, 1, 0, 0},
|
|
{"RSV_A" , 0, 6, 300, "R/W", 0, 1, 0ull, 0},
|
|
{"SKP_LEN" , 6, 7, 300, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_B" , 13, 1, 300, "R/W", 0, 1, 0ull, 0},
|
|
{"PAR_MODE" , 14, 2, 300, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_C" , 16, 5, 300, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_IHDR" , 21, 1, 300, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_D" , 22, 6, 300, "R/W", 0, 1, 0ull, 0},
|
|
{"RSKP_LEN" , 28, 7, 300, "R/W", 0, 1, 8ull, 0},
|
|
{"RSV_E" , 35, 1, 300, "R/W", 0, 1, 0ull, 0},
|
|
{"RPARMODE" , 36, 2, 300, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_F" , 38, 5, 300, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP" , 43, 1, 300, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 300, "RAZ", 1, 1, 0, 0},
|
|
{"ENB" , 0, 4, 301, "R/W", 0, 0, 15ull, 15ull},
|
|
{"BP_ON" , 4, 4, 301, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 301, "RAZ", 1, 1, 0, 0},
|
|
{"MIO" , 0, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX0" , 1, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX1" , 2, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPI" , 3, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"KEY" , 4, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPA" , 5, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"DFA" , 6, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"ZIP" , 7, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_8" , 8, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD" , 9, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 10, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"TIM" , 11, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"POW" , 12, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"USB" , 13, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_14" , 14, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_15" , 15, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"L2C" , 16, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"LMC" , 17, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"SPX0" , 18, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"SPX1" , 19, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"PIP" , 20, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_21" , 21, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASX0" , 22, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASX1" , 23, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_24" , 24, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_25" , 25, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_26" , 26, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_27" , 27, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_28" , 28, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_29" , 29, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"IOB" , 30, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_31" , 31, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 302, "RAZ", 1, 1, 0, 0},
|
|
{"SIZE" , 0, 32, 303, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 303, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 32, 304, "R/W", 0, 0, 0ull, 131072ull},
|
|
{"RESERVED_32_63" , 32, 32, 304, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR_V" , 0, 1, 305, "R/W", 0, 1, 0ull, 0},
|
|
{"END_SWP" , 1, 2, 305, "R/W", 0, 1, 0ull, 0},
|
|
{"CA" , 3, 1, 305, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDR_IDX" , 4, 14, 305, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_31" , 18, 14, 305, "RAZ", 1, 1, 0, 0},
|
|
{"VENDID" , 0, 16, 306, "RO", 0, 0, 6013ull, 6013ull},
|
|
{"DEVID" , 16, 16, 306, "RO", 0, 0, 48ull, 48ull},
|
|
{"ISAE" , 0, 1, 307, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSAE" , 1, 1, 307, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ME" , 2, 1, 307, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SCSE" , 3, 1, 307, "RO", 0, 0, 0ull, 0ull},
|
|
{"MWICE" , 4, 1, 307, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VPS" , 5, 1, 307, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEE" , 6, 1, 307, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ADS" , 7, 1, 307, "RO", 0, 0, 0ull, 0ull},
|
|
{"SEE" , 8, 1, 307, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FBBE" , 9, 1, 307, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I_DIS" , 10, 1, 307, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_18" , 11, 8, 307, "RAZ", 1, 1, 0, 0},
|
|
{"I_STAT" , 19, 1, 307, "RO", 0, 0, 0ull, 0ull},
|
|
{"CLE" , 20, 1, 307, "RO", 0, 0, 1ull, 1ull},
|
|
{"M66" , 21, 1, 307, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_22_22" , 22, 1, 307, "RAZ", 1, 1, 0, 0},
|
|
{"FBB" , 23, 1, 307, "RO", 0, 1, 1ull, 0},
|
|
{"MDPE" , 24, 1, 307, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DEVT" , 25, 2, 307, "RO", 0, 0, 1ull, 1ull},
|
|
{"STA" , 27, 1, 307, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTA" , 28, 1, 307, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RMA" , 29, 1, 307, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SSE" , 30, 1, 307, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPE" , 31, 1, 307, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RID" , 0, 8, 308, "RO", 0, 0, 0ull, 0ull},
|
|
{"CC" , 8, 24, 308, "RO", 0, 0, 733184ull, 733184ull},
|
|
{"CLS" , 0, 8, 309, "R/W", 0, 1, 0ull, 0},
|
|
{"LT" , 8, 8, 309, "R/W", 0, 0, 0ull, 64ull},
|
|
{"HT" , 16, 8, 309, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCOD" , 24, 4, 309, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_29" , 28, 2, 309, "RAZ", 1, 1, 0, 0},
|
|
{"BRB" , 30, 1, 309, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BCAP" , 31, 1, 309, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSPC" , 0, 1, 310, "RO", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 310, "RO", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 310, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBASEZ" , 4, 8, 310, "RO", 0, 0, 0ull, 0ull},
|
|
{"LBASE" , 12, 20, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"HBASE" , 0, 32, 311, "R/W", 0, 1, 0ull, 0},
|
|
{"MSPC" , 0, 1, 312, "RO", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 312, "RO", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 312, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBASEZ" , 4, 23, 312, "RO", 0, 0, 0ull, 0ull},
|
|
{"LBASE" , 27, 5, 312, "R/W", 0, 1, 0ull, 0},
|
|
{"HBASE" , 0, 32, 313, "R/W", 0, 1, 0ull, 0},
|
|
{"MSPC" , 0, 1, 314, "RO", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 314, "RO", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 314, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBASEZ" , 4, 28, 314, "RO", 0, 0, 0ull, 0ull},
|
|
{"HBASEZ" , 0, 7, 315, "RO", 0, 0, 0ull, 0ull},
|
|
{"HBASE" , 7, 25, 315, "R/W", 0, 1, 0ull, 0},
|
|
{"CISP" , 0, 32, 316, "RO", 0, 0, 0ull, 0ull},
|
|
{"SSVID" , 0, 16, 317, "RO", 0, 0, 6013ull, 6013ull},
|
|
{"SSID" , 16, 16, 317, "RO", 0, 0, 1ull, 1ull},
|
|
{"ERBAR_EN" , 0, 1, 318, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_10" , 1, 10, 318, "RAZ", 1, 1, 0, 0},
|
|
{"ERBARZ" , 11, 5, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"ERBAR" , 16, 16, 318, "R/W", 0, 1, 0ull, 0},
|
|
{"CP" , 0, 8, 319, "RO", 0, 0, 224ull, 224ull},
|
|
{"RESERVED_8_31" , 8, 24, 319, "RAZ", 1, 1, 0, 0},
|
|
{"IL" , 0, 8, 320, "R/W", 0, 1, 0ull, 0},
|
|
{"INTA" , 8, 8, 320, "RO", 0, 0, 1ull, 1ull},
|
|
{"MG" , 16, 8, 320, "RO", 0, 0, 64ull, 64ull},
|
|
{"ML" , 24, 8, 320, "RO", 0, 0, 64ull, 64ull},
|
|
{"MLTD" , 0, 1, 321, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TSWC" , 1, 1, 321, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 321, "RAZ", 1, 1, 0, 0},
|
|
{"DPPMR" , 3, 1, 321, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PBE" , 4, 12, 321, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TILT" , 16, 4, 321, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TSLTE" , 20, 3, 321, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TMAE" , 23, 1, 321, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWTAE" , 24, 1, 321, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWSEN" , 25, 1, 321, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWSEI" , 26, 1, 321, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRTAE" , 27, 1, 321, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRDRS" , 28, 1, 321, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RDSATI" , 29, 1, 321, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRDARD" , 30, 1, 321, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TRDNPR" , 31, 1, 321, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TSCME" , 0, 32, 322, "R/W1C", 0, 1, 0ull, 0},
|
|
{"TDSRPS" , 0, 32, 323, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TDOMC" , 0, 5, 324, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TIDOMC" , 5, 1, 324, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_6" , 6, 1, 324, "RAZ", 1, 1, 0, 0},
|
|
{"TIBDE" , 7, 1, 324, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIBCD" , 8, 1, 324, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_10" , 9, 2, 324, "RAZ", 1, 1, 0, 0},
|
|
{"TMAPES" , 11, 1, 324, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TMDPES" , 12, 1, 324, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TMSE" , 13, 1, 324, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TMEI" , 14, 1, 324, "RO", 0, 0, 0ull, 0ull},
|
|
{"TECI" , 15, 1, 324, "RO", 0, 0, 0ull, 0ull},
|
|
{"TMES" , 16, 8, 324, "RO", 0, 0, 0ull, 0ull},
|
|
{"MDRRMC" , 24, 3, 324, "R/W", 0, 0, 2ull, 2ull},
|
|
{"MDRIMC" , 27, 1, 324, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MDRE" , 28, 1, 324, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MDWE" , 29, 1, 324, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRBCI" , 30, 1, 324, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRBCM" , 31, 1, 324, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MDSP" , 0, 32, 325, "R/W1C", 0, 1, 0ull, 0},
|
|
{"SCMRE" , 0, 32, 326, "R/W1C", 0, 1, 0ull, 0},
|
|
{"MTTV" , 0, 8, 327, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRV" , 8, 8, 327, "R/W", 0, 0, 0ull, 255ull},
|
|
{"MTTA" , 16, 1, 327, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRA" , 17, 1, 327, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FLUSH" , 18, 1, 327, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_19_24" , 19, 6, 327, "RAZ", 1, 1, 0, 0},
|
|
{"MAC" , 25, 7, 327, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PXCID" , 0, 8, 328, "RO", 0, 0, 7ull, 7ull},
|
|
{"NCP" , 8, 8, 328, "RO", 0, 0, 232ull, 232ull},
|
|
{"DPERE" , 16, 1, 328, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROE" , 17, 1, 328, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MMBC" , 18, 2, 328, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MOST" , 20, 3, 328, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_23_31" , 23, 9, 328, "RAZ", 1, 1, 0, 0},
|
|
{"FN" , 0, 3, 329, "RO", 0, 0, 0ull, 0ull},
|
|
{"DN" , 3, 5, 329, "RO", 0, 0, 31ull, 31ull},
|
|
{"BN" , 8, 8, 329, "RO", 0, 1, 17ull, 0},
|
|
{"W64" , 16, 1, 329, "RO", 0, 0, 1ull, 1ull},
|
|
{"M133" , 17, 1, 329, "RO", 0, 0, 1ull, 1ull},
|
|
{"SCD" , 18, 1, 329, "R/W1C", 0, 1, 0ull, 0},
|
|
{"USC" , 19, 1, 329, "R/W1C", 0, 1, 0ull, 0},
|
|
{"DC" , 20, 1, 329, "RO", 0, 0, 0ull, 0ull},
|
|
{"MMRBCD" , 21, 2, 329, "RO", 0, 0, 2ull, 2ull},
|
|
{"MOSTD" , 23, 3, 329, "RO", 0, 0, 3ull, 3ull},
|
|
{"MCRSD" , 26, 3, 329, "RO", 0, 0, 7ull, 7ull},
|
|
{"SCEMR" , 29, 1, 329, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_30_31" , 30, 2, 329, "RAZ", 1, 1, 0, 0},
|
|
{"PMCID" , 0, 8, 330, "RO", 0, 0, 1ull, 1ull},
|
|
{"NCP" , 8, 8, 330, "RO", 0, 0, 240ull, 240ull},
|
|
{"PCIMIV" , 16, 3, 330, "RO", 0, 0, 2ull, 2ull},
|
|
{"PMEC" , 19, 1, 330, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 330, "RAZ", 1, 1, 0, 0},
|
|
{"DSI" , 21, 1, 330, "RO", 0, 0, 0ull, 0ull},
|
|
{"AUXC" , 22, 3, 330, "RO", 0, 0, 0ull, 0ull},
|
|
{"D1S" , 25, 1, 330, "RO", 0, 0, 0ull, 0ull},
|
|
{"D2S" , 26, 1, 330, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMES" , 27, 5, 330, "RO", 0, 0, 0ull, 0ull},
|
|
{"PS" , 0, 2, 331, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_7" , 2, 6, 331, "RAZ", 1, 1, 0, 0},
|
|
{"PMEENS" , 8, 1, 331, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMDS" , 9, 4, 331, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMEDSIA" , 13, 2, 331, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMESS" , 15, 1, 331, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_21" , 16, 6, 331, "RAZ", 1, 1, 0, 0},
|
|
{"BD3H" , 22, 1, 331, "RO", 0, 0, 0ull, 0ull},
|
|
{"BPCCEN" , 23, 1, 331, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMDIA" , 24, 8, 331, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSICID" , 0, 8, 332, "RO", 0, 0, 5ull, 5ull},
|
|
{"NCP" , 8, 8, 332, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSIEN" , 16, 1, 332, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MMC" , 17, 3, 332, "RO", 0, 0, 0ull, 0ull},
|
|
{"MME" , 20, 3, 332, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M64" , 23, 1, 332, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_24_31" , 24, 8, 332, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 333, "RAZ", 1, 1, 0, 0},
|
|
{"MSI31T2" , 2, 30, 333, "R/W", 0, 1, 0ull, 0},
|
|
{"MSI" , 0, 32, 334, "R/W", 0, 1, 0ull, 0},
|
|
{"MSIMD" , 0, 16, 335, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_31" , 16, 16, 335, "RAZ", 1, 1, 0, 0},
|
|
{"BAR2_CAX" , 0, 1, 336, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAR2_ESX" , 1, 2, 336, "R/W", 0, 1, 0ull, 0},
|
|
{"BAR2_ENB" , 3, 1, 336, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TSR_HWM" , 4, 3, 336, "R/W", 0, 1, 1ull, 0},
|
|
{"PMO_FPC" , 7, 3, 336, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMO_AMOD" , 10, 1, 336, "R/W", 0, 0, 0ull, 0ull},
|
|
{"B12_BIST" , 11, 1, 336, "RO", 0, 0, 0ull, 0ull},
|
|
{"AP_64AD" , 12, 1, 336, "RO", 0, 1, 0ull, 0},
|
|
{"AP_PCIX" , 13, 1, 336, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_14" , 14, 1, 336, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EN_WFILT" , 15, 1, 336, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SCM" , 16, 1, 336, "RO", 0, 1, 0ull, 0},
|
|
{"SCMTYP" , 17, 1, 336, "RO", 0, 1, 0ull, 0},
|
|
{"BAR2PRES" , 18, 1, 336, "R/W", 1, 1, 0, 0},
|
|
{"ERST_N" , 19, 1, 336, "RO", 0, 0, 1ull, 1ull},
|
|
{"BB0" , 20, 1, 336, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB1" , 21, 1, 336, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB_ES" , 22, 2, 336, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB_CA" , 24, 1, 336, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB1_SIZ" , 25, 1, 336, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB1_HOLE" , 26, 3, 336, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_31" , 29, 3, 336, "RAZ", 1, 1, 0, 0},
|
|
{"INC_VAL" , 0, 16, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_31" , 16, 16, 337, "RAZ", 1, 1, 0, 0},
|
|
{"DMA_CNT" , 0, 32, 338, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKT_CNT" , 0, 32, 339, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA_TIME" , 0, 32, 340, "R/W", 0, 1, 0ull, 0},
|
|
{"ICNT" , 0, 32, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ITR_WABT" , 0, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_WABT" , 1, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_WTTO" , 2, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"ITR_ABT" , 3, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_ABT" , 4, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_TTO" , 5, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSI_PER" , 6, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSI_TABT" , 7, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSI_MABT" , 8, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSC_MSG" , 9, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"ITSR_ABT" , 10, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"ISERR" , 11, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"IAPERR" , 12, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"IDPERR" , 13, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RWR" , 14, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RRD" , 15, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"IRSL_INT" , 16, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"IPCNT0" , 17, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_20" , 18, 3, 342, "RAZ", 0, 1, 0ull, 0},
|
|
{"IPTIME0" , 21, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_22_24" , 22, 3, 342, "RAZ", 0, 1, 0ull, 0},
|
|
{"IDCNT0" , 25, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"IDCNT1" , 26, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"IDTIME0" , 27, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"IDTIME1" , 28, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA0_FI" , 29, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA1_FI" , 30, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"WIN_WR" , 31, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_WR" , 32, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RD" , 33, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_34_63" , 34, 30, 342, "RAZ", 1, 1, 0, 0},
|
|
{"RTR_WABT" , 0, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_WABT" , 1, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_WTTO" , 2, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RTR_ABT" , 3, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_ABT" , 4, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_TTO" , 5, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSI_PER" , 6, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSI_TABT" , 7, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSI_MABT" , 8, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSC_MSG" , 9, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RTSR_ABT" , 10, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RSERR" , 11, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RAPERR" , 12, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RDPERR" , 13, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RWR" , 14, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RRD" , 15, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RRSL_INT" , 16, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RPCNT0" , 17, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_20" , 18, 3, 343, "RAZ", 0, 1, 0ull, 0},
|
|
{"RPTIME0" , 21, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_22_24" , 22, 3, 343, "RAZ", 0, 1, 0ull, 0},
|
|
{"RDCNT0" , 25, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RDCNT1" , 26, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RDTIME0" , 27, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RDTIME1" , 28, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA0_FI" , 29, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA1_FI" , 30, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"WIN_WR" , 31, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_WR" , 32, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RD" , 33, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_34_63" , 34, 30, 343, "RAZ", 1, 1, 0, 0},
|
|
{"TR_WABT" , 0, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WABT" , 1, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WTTO" , 2, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TR_ABT" , 3, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_ABT" , 4, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_TTO" , 5, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_PER" , 6, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_TABT" , 7, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_MABT" , 8, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSC_MSG" , 9, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TSR_ABT" , 10, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SERR" , 11, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"APERR" , 12, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPERR" , 13, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RWR" , 14, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RRD" , 15, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSL_INT" , 16, 1, 344, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCNT0" , 17, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_20" , 18, 3, 344, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PTIME0" , 21, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_24" , 22, 3, 344, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DCNT0" , 25, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT1" , 26, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME0" , 27, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME1" , 28, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA0_FI" , 29, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1_FI" , 30, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WIN_WR" , 31, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_WR" , 32, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RD" , 33, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 344, "RAZ", 1, 1, 0, 0},
|
|
{"TR_WABT" , 0, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WABT" , 1, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WTTO" , 2, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TR_ABT" , 3, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_ABT" , 4, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_TTO" , 5, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_PER" , 6, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_TABT" , 7, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_MABT" , 8, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSC_MSG" , 9, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TSR_ABT" , 10, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SERR" , 11, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"APERR" , 12, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPERR" , 13, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RWR" , 14, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RRD" , 15, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSL_INT" , 16, 1, 345, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCNT0" , 17, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_20" , 18, 3, 345, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PTIME0" , 21, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_24" , 22, 3, 345, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DCNT0" , 25, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT1" , 26, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME0" , 27, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME1" , 28, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA0_FI" , 29, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1_FI" , 30, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WIN_WR" , 31, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_WR" , 32, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RD" , 33, 1, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 345, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 0, 6, 346, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_31" , 6, 26, 346, "R/W", 1, 1, 0, 0},
|
|
{"PTR_CNT" , 0, 16, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_CNT" , 16, 16, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_CNT" , 0, 32, 348, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_CNT" , 0, 32, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_TIME" , 0, 32, 350, "R/W", 0, 1, 0ull, 0},
|
|
{"PREFETCH" , 0, 3, 351, "R/W", 0, 0, 0ull, 2ull},
|
|
{"MIN_DATA" , 3, 6, 351, "R/W", 0, 0, 0ull, 4ull},
|
|
{"RESERVED_9_31" , 9, 23, 351, "RAZ", 1, 1, 0, 0},
|
|
{"PREFETCH" , 0, 3, 352, "R/W", 0, 0, 0ull, 3ull},
|
|
{"MIN_DATA" , 3, 6, 352, "R/W", 0, 0, 0ull, 6ull},
|
|
{"RESERVED_9_31" , 9, 23, 352, "RAZ", 1, 1, 0, 0},
|
|
{"PREFETCH" , 0, 3, 353, "R/W", 0, 0, 0ull, 3ull},
|
|
{"MIN_DATA" , 3, 6, 353, "R/W", 0, 0, 0ull, 6ull},
|
|
{"RESERVED_9_31" , 9, 23, 353, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 31, 354, "R/W", 0, 0, 10000ull, 10000ull},
|
|
{"ENB" , 31, 1, 354, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_32_63" , 32, 32, 354, "RAZ", 1, 1, 0, 0},
|
|
{"SCM" , 0, 32, 355, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 355, "RAZ", 1, 1, 0, 0},
|
|
{"TSR" , 0, 36, 356, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 356, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 357, "RAZ", 1, 1, 0, 0},
|
|
{"RD_ADDR" , 2, 46, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"IOBIT" , 48, 1, 357, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 357, "RAZ", 1, 1, 0, 0},
|
|
{"RD_DATA" , 0, 64, 358, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_0_2" , 0, 3, 359, "RAZ", 1, 1, 0, 0},
|
|
{"WR_ADDR" , 3, 45, 359, "R/W", 0, 1, 0ull, 0},
|
|
{"IOBIT" , 48, 1, 359, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 359, "RAZ", 1, 1, 0, 0},
|
|
{"WR_DATA" , 0, 64, 360, "R/W", 0, 1, 0ull, 0},
|
|
{"WR_MASK" , 0, 8, 361, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 361, "RAZ", 1, 1, 0, 0},
|
|
{"THRESH" , 0, 4, 362, "R/W", 0, 0, 0ull, 8ull},
|
|
{"FETCHSIZ" , 4, 4, 362, "R/W", 0, 0, 0ull, 7ull},
|
|
{"TXRD" , 8, 10, 362, "R/W", 0, 0, 0ull, 1ull},
|
|
{"USELDT" , 18, 1, 362, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_19" , 19, 1, 362, "RAZ", 1, 1, 0, 0},
|
|
{"RXST" , 20, 10, 362, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_30_31" , 30, 2, 362, "RAZ", 1, 1, 0, 0},
|
|
{"TXSLOTS" , 32, 10, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_42_43" , 42, 2, 362, "RAZ", 1, 1, 0, 0},
|
|
{"RXSLOTS" , 44, 10, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_54_62" , 54, 9, 362, "RAZ", 1, 1, 0, 0},
|
|
{"RDPEND" , 63, 1, 362, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYNCMISSED" , 0, 1, 363, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FSYNCEXTRA" , 1, 1, 363, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXWRAP" , 2, 1, 363, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXST" , 3, 1, 363, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXWRAP" , 4, 1, 363, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXRD" , 5, 1, 363, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXEMPTY" , 6, 1, 363, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXOVF" , 7, 1, 363, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_8_63" , 8, 56, 363, "RAZ", 1, 1, 0, 0},
|
|
{"FSYNCMISSED" , 0, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FSYNCEXTRA" , 1, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXWRAP" , 2, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXST" , 3, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXWRAP" , 4, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXRD" , 5, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXEMPTY" , 6, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXOVF" , 7, 1, 364, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 364, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 365, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_36_63" , 36, 28, 365, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 366, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_16_63" , 16, 48, 366, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 367, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 368, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 369, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 370, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 371, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 372, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 373, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 374, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 375, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 3, 33, 375, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_36_63" , 36, 28, 375, "RAZ", 1, 1, 0, 0},
|
|
{"ENABLE" , 0, 1, 376, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USECLK1" , 1, 1, 376, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LSBFIRST" , 2, 1, 376, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_31" , 3, 29, 376, "RAZ", 1, 1, 0, 0},
|
|
{"SAMPPT" , 32, 16, 376, "R/W", 0, 1, 0ull, 0},
|
|
{"DRVTIM" , 48, 16, 376, "R/W", 0, 1, 0ull, 0},
|
|
{"DEBUGINFO" , 0, 64, 377, "RO", 1, 1, 0, 0},
|
|
{"FRAM" , 0, 3, 378, "R/W", 1, 1, 0, 0},
|
|
{"ADDR" , 3, 33, 378, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_36_63" , 36, 28, 378, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 379, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_16_63" , 16, 48, 379, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 380, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 381, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 382, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 383, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 384, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 385, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 386, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 387, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 388, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 3, 33, 388, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_36_63" , 36, 28, 388, "RAZ", 1, 1, 0, 0},
|
|
{"ENA" , 0, 1, 389, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSYNCPOL" , 1, 1, 389, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BCLKPOL" , 2, 1, 389, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BITLEN" , 3, 2, 389, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EXTRABIT" , 5, 1, 389, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NUMSLOTS" , 6, 10, 389, "R/W", 0, 1, 0ull, 0},
|
|
{"FSYNCLOC" , 16, 5, 389, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSYNCLEN" , 21, 5, 389, "R/W", 0, 0, 0ull, 2ull},
|
|
{"RESERVED_26_31" , 26, 6, 389, "RAZ", 1, 1, 0, 0},
|
|
{"FSYNCSAMP" , 32, 16, 389, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_62" , 48, 15, 389, "RAZ", 1, 1, 0, 0},
|
|
{"FSYNCGOOD" , 63, 1, 389, "RO", 0, 0, 0ull, 1ull},
|
|
{"DEBUGINFO" , 0, 64, 390, "RO", 1, 1, 0, 0},
|
|
{"N" , 0, 32, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"NUMSAMP" , 32, 16, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"DELTASAMP" , 48, 16, 391, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BIST" , 0, 18, 392, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 392, "RAZ", 1, 1, 0, 0},
|
|
{"DPRT" , 0, 16, 393, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UDP" , 16, 1, 393, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP" , 17, 1, 393, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 393, "RAZ", 1, 1, 0, 0},
|
|
{"NIP_SHF" , 0, 3, 394, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_7" , 3, 5, 394, "RAZ", 1, 1, 0, 0},
|
|
{"RAW_SHF" , 8, 3, 394, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_15" , 11, 5, 394, "RAZ", 1, 1, 0, 0},
|
|
{"MAX_L2" , 16, 1, 394, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_UDP" , 17, 1, 394, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TAG_SYN" , 18, 1, 394, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 394, "RAZ", 1, 1, 0, 0},
|
|
{"IP_CHK" , 0, 1, 395, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP_MAL" , 1, 1, 395, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP_HOP" , 2, 1, 395, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP4_OPTS" , 3, 1, 395, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP6_EEXT" , 4, 2, 395, "R/W", 0, 0, 1ull, 3ull},
|
|
{"RESERVED_6_7" , 6, 2, 395, "RAZ", 0, 1, 0ull, 0},
|
|
{"L4_MAL" , 8, 1, 395, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_PRT" , 9, 1, 395, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_CHK" , 10, 1, 395, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_LEN" , 11, 1, 395, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TCP_FLAG" , 12, 1, 395, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L2_MAL" , 13, 1, 395, "R/W", 0, 0, 1ull, 1ull},
|
|
{"VS_QOS" , 14, 1, 395, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VS_WQE" , 15, 1, 395, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IGNRS" , 16, 1, 395, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 395, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PKTDRP" , 0, 1, 396, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CRCERR" , 1, 1, 396, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BCKPRS" , 2, 1, 396, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 3, 1, 396, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BADTAG" , 4, 1, 396, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPRUNT" , 5, 1, 396, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TODOOVR" , 6, 1, 396, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FEPERR" , 7, 1, 396, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BEPERR" , 8, 1, 396, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 396, "RAZ", 1, 1, 0, 0},
|
|
{"PKTDRP" , 0, 1, 397, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CRCERR" , 1, 1, 397, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BCKPRS" , 2, 1, 397, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 3, 1, 397, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BADTAG" , 4, 1, 397, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPRUNT" , 5, 1, 397, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TODOOVR" , 6, 1, 397, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FEPERR" , 7, 1, 397, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BEPERR" , 8, 1, 397, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 397, "RAZ", 1, 1, 0, 0},
|
|
{"OFFSET" , 0, 3, 398, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 398, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP" , 0, 7, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 399, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 8, 2, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_15" , 10, 6, 399, "RAZ", 1, 1, 0, 0},
|
|
{"QOS_VLAN" , 16, 1, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS_DIFF" , 17, 1, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_19" , 18, 2, 399, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"QOS_WAT" , 20, 4, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS" , 24, 3, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 399, "RAZ", 1, 1, 0, 0},
|
|
{"GRP_WAT" , 28, 4, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INST_HDR" , 32, 1, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DYN_RS" , 33, 1, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TAG_INC" , 34, 2, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RAWDRP" , 36, 1, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 399, "RAZ", 1, 1, 0, 0},
|
|
{"GRP" , 0, 4, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NON_TAG_TYPE" , 4, 2, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_TAG_TYPE" , 6, 2, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_TAG_TYPE" , 8, 2, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP4_TAG_TYPE" , 10, 2, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP6_TAG_TYPE" , 12, 2, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_SRC_FLAG" , 14, 1, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_SRC_FLAG" , 15, 1, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_DST_FLAG" , 16, 1, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_DST_FLAG" , 17, 1, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_PCTL_FLAG" , 18, 1, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_NXTH_FLAG" , 19, 1, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_SPRT_FLAG" , 20, 1, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_SPRT_FLAG" , 21, 1, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_DPRT_FLAG" , 22, 1, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_DPRT_FLAG" , 23, 1, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_PRT_FLAG" , 24, 1, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_VLAN" , 25, 1, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_VS" , 26, 2, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TAG_MODE" , 28, 2, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_30" , 30, 1, 400, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"GRPTAG" , 31, 1, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAGMASK" , 32, 4, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAGBASE" , 36, 4, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 400, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 0, 3, 401, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 401, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 0, 3, 402, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 402, "RAZ", 1, 1, 0, 0},
|
|
{"MATCH_VALUE" , 0, 16, 403, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MATCH_TYPE" , 16, 2, 403, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_19" , 18, 2, 403, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 20, 3, 403, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 403, "RAZ", 1, 1, 0, 0},
|
|
{"GRP" , 24, 4, 403, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_31" , 28, 4, 403, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 32, 16, 403, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 403, "RAZ", 1, 1, 0, 0},
|
|
{"WORD" , 0, 56, 404, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 404, "RAZ", 1, 1, 0, 0},
|
|
{"RST" , 0, 1, 405, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 405, "RAZ", 1, 1, 0, 0},
|
|
{"DRP_OCTS" , 0, 32, 406, "R/W", 0, 1, 0ull, 0},
|
|
{"DRP_PKTS" , 32, 32, 406, "R/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 407, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 407, "RAZ", 1, 1, 0, 0},
|
|
{"RAW" , 0, 32, 408, "R/W", 0, 1, 0ull, 0},
|
|
{"PKTS" , 32, 32, 408, "R/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 0, 32, 409, "R/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 32, 32, 409, "R/W", 0, 1, 0ull, 0},
|
|
{"H64" , 0, 32, 410, "R/W", 0, 1, 0ull, 0},
|
|
{"H65TO127" , 32, 32, 410, "R/W", 0, 1, 0ull, 0},
|
|
{"H128TO255" , 0, 32, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"H256TO511" , 32, 32, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"H512TO1023" , 0, 32, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"H1024TO1518" , 32, 32, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"H1519" , 0, 32, 413, "R/W", 0, 1, 0ull, 0},
|
|
{"FCS" , 32, 32, 413, "R/W", 0, 1, 0ull, 0},
|
|
{"UNDERSZ" , 0, 32, 414, "R/W", 0, 1, 0ull, 0},
|
|
{"FRAG" , 32, 32, 414, "R/W", 0, 1, 0ull, 0},
|
|
{"OVERSZ" , 0, 32, 415, "R/W", 0, 1, 0ull, 0},
|
|
{"JABBER" , 32, 32, 415, "R/W", 0, 1, 0ull, 0},
|
|
{"RDCLR" , 0, 1, 416, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 416, "RAZ", 1, 1, 0, 0},
|
|
{"ERRS" , 0, 16, 417, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 417, "RAZ", 1, 1, 0, 0},
|
|
{"OCTS" , 0, 48, 418, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 418, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 419, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 419, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 8, 420, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 420, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 0, 16, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 421, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 16, 422, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DST" , 16, 16, 422, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 422, "RAZ", 1, 1, 0, 0},
|
|
{"ENTRY" , 0, 62, 423, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_62_62" , 62, 1, 423, "RAZ", 1, 1, 0, 0},
|
|
{"VAL" , 63, 1, 423, "RO", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 32, 424, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 424, "RAZ", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 48, 425, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 425, "RAZ", 1, 1, 0, 0},
|
|
{"SIZE" , 0, 16, 426, "RO", 1, 0, 0, 0ull},
|
|
{"SEGS" , 16, 6, 426, "RO", 1, 0, 0, 0ull},
|
|
{"CMD" , 22, 14, 426, "RO", 1, 0, 0, 0ull},
|
|
{"FAU" , 36, 28, 426, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 427, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 427, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 427, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 427, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 427, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 16, 428, "RO", 1, 0, 0, 0ull},
|
|
{"SEGS" , 16, 6, 428, "RO", 1, 0, 0, 0ull},
|
|
{"CMD" , 22, 14, 428, "RO", 1, 0, 0, 0ull},
|
|
{"FAU" , 36, 28, 428, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 429, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 429, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 429, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 429, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 429, "RO", 1, 0, 0, 0ull},
|
|
{"DATA" , 0, 64, 430, "RO", 1, 0, 0, 0ull},
|
|
{"WIDX2" , 0, 17, 431, "RO", 1, 0, 0, 0ull},
|
|
{"RIDX2" , 17, 17, 431, "RO", 1, 0, 0, 0ull},
|
|
{"WIDX" , 34, 17, 431, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_51_63" , 51, 13, 431, "RAZ", 1, 0, 0, 0ull},
|
|
{"RIDX" , 0, 17, 432, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 432, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 433, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 433, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 433, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 433, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 433, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 434, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 434, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 434, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 434, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 434, "RO", 1, 0, 0, 0ull},
|
|
{"DATA" , 0, 64, 435, "RO", 1, 0, 0, 0ull},
|
|
{"MAJOR" , 0, 4, 436, "RO", 1, 0, 0, 0ull},
|
|
{"MINOR" , 4, 2, 436, "RO", 1, 0, 0, 0ull},
|
|
{"WAIT" , 6, 1, 436, "RO", 1, 0, 0, 0ull},
|
|
{"QID_BASE" , 7, 7, 436, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFF" , 14, 3, 436, "RO", 1, 0, 0, 0ull},
|
|
{"QCB_RIDX" , 17, 5, 436, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 22, 3, 436, "RO", 1, 0, 0, 0ull},
|
|
{"ACTIVE" , 25, 1, 436, "RO", 1, 0, 0, 0ull},
|
|
{"CHK_MODE" , 26, 1, 436, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 436, "RAZ", 1, 0, 0, 0ull},
|
|
{"CBUF_FRE" , 28, 1, 436, "RO", 1, 0, 0, 0ull},
|
|
{"XFER_DWR" , 29, 1, 436, "RO", 1, 0, 0, 0ull},
|
|
{"XFER_WOR" , 30, 1, 436, "RO", 1, 0, 0, 0ull},
|
|
{"UID" , 31, 1, 436, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_SIZ" , 32, 16, 436, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_CNT" , 48, 13, 436, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_LEN" , 61, 1, 436, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_SOP" , 62, 1, 436, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_MOD" , 63, 1, 436, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_MOD" , 0, 2, 437, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_UID" , 2, 1, 437, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_CHK" , 3, 1, 437, "RO", 1, 0, 0, 0ull},
|
|
{"WORK_MIN" , 4, 3, 437, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 7, 1, 437, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFFM" , 8, 3, 437, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 437, "RAZ", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 16, 438, "RO", 1, 0, 0, 0ull},
|
|
{"START" , 16, 33, 438, "RO", 1, 0, 0, 0ull},
|
|
{"DWB" , 49, 9, 438, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_58_63" , 58, 6, 438, "RAZ", 1, 0, 0, 0ull},
|
|
{"QCB_RIDX" , 0, 6, 439, "RO", 1, 0, 0, 0ull},
|
|
{"QCB_WIDX" , 6, 6, 439, "RO", 1, 0, 0, 0ull},
|
|
{"BUF_PTR" , 12, 33, 439, "RO", 1, 0, 0, 0ull},
|
|
{"BUF_SIZ" , 45, 13, 439, "RO", 1, 0, 0, 0ull},
|
|
{"TAIL" , 58, 1, 439, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 59, 5, 439, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 0, 3, 440, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_Q" , 3, 1, 440, "RO", 1, 0, 0, 0ull},
|
|
{"S_TAIL" , 4, 1, 440, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_5_7" , 5, 3, 440, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 8, 20, 440, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 440, "RAZ", 1, 0, 0, 0ull},
|
|
{"QUEUE" , 0, 7, 441, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT" , 7, 6, 441, "WR0", 1, 0, 0, 0ull},
|
|
{"INDEX" , 13, 3, 441, "WR0", 1, 0, 0, 0ull},
|
|
{"TAIL" , 16, 1, 441, "R/W", 1, 0, 0, 0ull},
|
|
{"BUF_PTR" , 17, 36, 441, "R/W", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 441, "R/W", 1, 0, 0, 0ull},
|
|
{"STATIC_Q" , 61, 1, 441, "WR0", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 62, 1, 441, "WR0", 1, 0, 0, 0ull},
|
|
{"S_TAIL" , 63, 1, 441, "WR0", 1, 0, 0, 0ull},
|
|
{"QID" , 0, 7, 442, "R/W", 1, 0, 0, 0ull},
|
|
{"PID" , 7, 6, 442, "WR0", 1, 0, 0, 0ull},
|
|
{"RESERVED_13_52" , 13, 40, 442, "RAZ", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 442, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_61_63" , 61, 3, 442, "RAZ", 1, 0, 0, 0ull},
|
|
{"PSB" , 0, 7, 443, "RO", 1, 0, 0, 0ull},
|
|
{"PDB" , 7, 4, 443, "RO", 1, 0, 0, 0ull},
|
|
{"QCB" , 11, 2, 443, "RO", 1, 0, 0, 0ull},
|
|
{"QSB" , 13, 2, 443, "RO", 1, 0, 0, 0ull},
|
|
{"CHK" , 15, 1, 443, "RO", 1, 0, 0, 0ull},
|
|
{"CRC" , 16, 1, 443, "RO", 1, 0, 0, 0ull},
|
|
{"OUT" , 17, 1, 443, "RO", 1, 0, 0, 0ull},
|
|
{"NCB" , 18, 1, 443, "RO", 1, 0, 0, 0ull},
|
|
{"WIF" , 19, 1, 443, "RO", 1, 0, 0, 0ull},
|
|
{"RIF" , 20, 1, 443, "RO", 1, 0, 0, 0ull},
|
|
{"COUNT" , 21, 1, 443, "RO", 1, 0, 0, 0ull},
|
|
{"PSB2" , 22, 5, 443, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_27_63" , 27, 37, 443, "RAZ", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 13, 444, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_19" , 13, 7, 444, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 20, 3, 444, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 444, "RAZ", 1, 0, 0, 0ull},
|
|
{"ASSERTS" , 0, 17, 445, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 445, "RAZ", 1, 0, 0, 0ull},
|
|
{"PARITY" , 0, 1, 446, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 1, 1, 446, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 446, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENA_PKO" , 0, 1, 447, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENA_DWB" , 1, 1, 447, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STORE_BE" , 2, 1, 447, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 3, 1, 447, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 447, "RAZ", 1, 0, 0, 0ull},
|
|
{"MODE0" , 0, 3, 448, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MODE1" , 3, 3, 448, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 448, "RAZ", 1, 0, 0, 0ull},
|
|
{"PARITY" , 0, 1, 449, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 1, 1, 449, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 449, "RAZ", 1, 0, 0, 0ull},
|
|
{"MODE" , 0, 2, 450, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 450, "RAZ", 1, 0, 0, 0ull},
|
|
{"INDEX" , 0, 8, 451, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 8, 8, 451, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 451, "RAZ", 1, 0, 0, 0ull},
|
|
{"ADR" , 0, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEND" , 1, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBR0" , 2, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBR1" , 3, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"FIDX" , 4, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"INDEX" , 5, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBT0" , 6, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBT1" , 7, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"CAM" , 8, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_15" , 9, 7, 452, "RAZ", 1, 1, 0, 0},
|
|
{"PP" , 16, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 452, "RAZ", 1, 1, 0, 0},
|
|
{"DS_PC" , 0, 32, 453, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 453, "RAZ", 1, 1, 0, 0},
|
|
{"SBE" , 0, 1, 454, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DBE" , 1, 1, 454, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SBE_IE" , 2, 1, 454, "R/W", 0, 1, 0ull, 0},
|
|
{"DBE_IE" , 3, 1, 454, "R/W", 0, 1, 0ull, 0},
|
|
{"SYN" , 4, 5, 454, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_9_11" , 9, 3, 454, "RAZ", 1, 1, 0, 0},
|
|
{"RPE" , 12, 1, 454, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPE_IE" , 13, 1, 454, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_15" , 14, 2, 454, "RAZ", 1, 1, 0, 0},
|
|
{"IOP" , 16, 13, 454, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_31" , 29, 3, 454, "RAZ", 1, 1, 0, 0},
|
|
{"IOP_IE" , 32, 13, 454, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_45_63" , 45, 19, 454, "RAZ", 1, 1, 0, 0},
|
|
{"NBR_THR" , 0, 5, 455, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PFR_DIS" , 5, 1, 455, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 455, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 32, 456, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 456, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 32, 457, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 457, "RAZ", 1, 1, 0, 0},
|
|
{"NOS_CNT" , 0, 7, 458, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 458, "RAZ", 1, 1, 0, 0},
|
|
{"NW_TIM" , 0, 10, 459, "R/W", 0, 0, 0ull, 1023ull},
|
|
{"RESERVED_10_63" , 10, 54, 459, "RAZ", 1, 1, 0, 0},
|
|
{"GRP_MSK" , 0, 16, 460, "R/W", 0, 0, 65535ull, 65535ull},
|
|
{"RESERVED_16_63" , 16, 48, 460, "RAZ", 1, 1, 0, 0},
|
|
{"RND" , 0, 8, 461, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P1" , 8, 8, 461, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P2" , 16, 8, 461, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P3" , 24, 8, 461, "R/W", 0, 1, 255ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 461, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_THR" , 0, 6, 462, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_11" , 6, 6, 462, "RAZ", 1, 1, 0, 0},
|
|
{"MAX_THR" , 12, 6, 462, "R/W", 0, 1, 63ull, 0},
|
|
{"RESERVED_18_23" , 18, 6, 462, "RAZ", 1, 1, 0, 0},
|
|
{"FREE_CNT" , 24, 7, 462, "RO", 0, 1, 58ull, 0},
|
|
{"RESERVED_31_35" , 31, 5, 462, "RAZ", 1, 1, 0, 0},
|
|
{"BUF_CNT" , 36, 7, 462, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_43_47" , 43, 5, 462, "RAZ", 1, 1, 0, 0},
|
|
{"DES_CNT" , 48, 7, 462, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_55_63" , 55, 9, 462, "RAZ", 1, 1, 0, 0},
|
|
{"TS_PC" , 0, 32, 463, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 463, "RAZ", 1, 1, 0, 0},
|
|
{"WA_PC" , 0, 32, 464, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 464, "RAZ", 1, 1, 0, 0},
|
|
{"WA_PC" , 0, 32, 465, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 465, "RAZ", 1, 1, 0, 0},
|
|
{"WQ_INT" , 0, 16, 466, "R/W1C", 0, 1, 0ull, 0},
|
|
{"IQ_DIS" , 16, 16, 466, "R/W1", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 466, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 7, 467, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_11" , 7, 5, 467, "RAZ", 1, 1, 0, 0},
|
|
{"DS_CNT" , 12, 7, 467, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_19_23" , 19, 5, 467, "RAZ", 1, 1, 0, 0},
|
|
{"TC_CNT" , 24, 4, 467, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_63" , 28, 36, 467, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 468, "RAZ", 1, 1, 0, 0},
|
|
{"PC_THR" , 8, 20, 468, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_31" , 28, 4, 468, "RAZ", 1, 1, 0, 0},
|
|
{"PC" , 32, 28, 468, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 468, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_THR" , 0, 6, 469, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_11" , 6, 6, 469, "RAZ", 1, 1, 0, 0},
|
|
{"DS_THR" , 12, 6, 469, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_23" , 18, 6, 469, "RAZ", 1, 1, 0, 0},
|
|
{"TC_THR" , 24, 4, 469, "R/W", 0, 1, 0ull, 0},
|
|
{"TC_EN" , 28, 1, 469, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 469, "RAZ", 1, 1, 0, 0},
|
|
{"WS_PC" , 0, 32, 470, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 470, "RAZ", 1, 1, 0, 0},
|
|
{"MEM" , 0, 1, 471, "RO", 0, 0, 0ull, 0ull},
|
|
{"RRC" , 1, 1, 471, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 471, "RAZ", 1, 1, 0, 0},
|
|
{"ENT_EN" , 0, 1, 472, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNG_EN" , 1, 1, 472, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNM_RST" , 2, 1, 472, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNG_RST" , 3, 1, 472, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 472, "RAZ", 1, 1, 0, 0},
|
|
{"PHASE" , 0, 8, 473, "R/W", 0, 0, 100ull, 100ull},
|
|
{"SAMPLE" , 8, 4, 473, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PREAMBLE" , 12, 1, 473, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CLK_IDLE" , 13, 1, 473, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_14" , 14, 1, 473, "RAZ", 1, 1, 0, 0},
|
|
{"SAMPLE_MODE" , 15, 1, 473, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SAMPLE_HI" , 16, 5, 473, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_63" , 21, 43, 473, "RAZ", 1, 1, 0, 0},
|
|
{"REG_ADR" , 0, 5, 474, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 474, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_ADR" , 8, 5, 474, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_13_15" , 13, 3, 474, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_OP" , 16, 1, 474, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_17_63" , 17, 47, 474, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 475, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 475, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 476, "RO", 0, 1, 0ull, 0},
|
|
{"VAL" , 16, 1, 476, "RO", 0, 1, 0ull, 0},
|
|
{"PENDING" , 17, 1, 476, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 476, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 477, "R/W", 0, 1, 0ull, 0},
|
|
{"VAL" , 16, 1, 477, "RO", 0, 1, 0ull, 0},
|
|
{"PENDING" , 17, 1, 477, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 477, "RAZ", 1, 1, 0, 0},
|
|
{"INTERVAL" , 0, 22, 478, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 478, "RAZ", 1, 0, 0, 0ull},
|
|
{"COUNT" , 24, 22, 478, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_46_46" , 46, 1, 478, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENA" , 47, 1, 478, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 478, "RAZ", 1, 0, 0, 0ull},
|
|
{"BSIZE" , 0, 20, 479, "RO", 1, 0, 0, 0ull},
|
|
{"BASE" , 20, 31, 479, "RO", 1, 0, 0, 0ull},
|
|
{"BUCKET" , 51, 13, 479, "RO", 1, 0, 0, 0ull},
|
|
{"BUCKET" , 0, 7, 480, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 480, "RAZ", 1, 0, 0, 0ull},
|
|
{"CSIZE" , 8, 13, 480, "RO", 1, 0, 0, 0ull},
|
|
{"CPOOL" , 21, 3, 480, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 480, "RAZ", 1, 0, 0, 0ull},
|
|
{"RING" , 0, 4, 481, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NUM_BUCKETS" , 4, 20, 481, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIRST_BUCKET" , 24, 31, 481, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_55_63" , 55, 9, 481, "RAZ", 1, 0, 0, 0ull},
|
|
{"RING" , 0, 4, 482, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTERVAL" , 4, 22, 482, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WORDS_PER_CHUNK" , 26, 13, 482, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 39, 3, 482, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENABLE" , 42, 1, 482, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_43_63" , 43, 21, 482, "RAZ", 1, 0, 0, 0ull},
|
|
{"CTL" , 0, 1, 483, "RO", 1, 0, 0, 0ull},
|
|
{"NCB" , 1, 1, 483, "RO", 1, 0, 0, 0ull},
|
|
{"STA" , 2, 2, 483, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 483, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 16, 484, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 484, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENABLE_TIMERS" , 0, 1, 485, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENABLE_DWB" , 1, 1, 485, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 2, 1, 485, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 485, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 16, 486, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 486, "RAZ", 1, 0, 0, 0ull},
|
|
{"INDEX" , 0, 8, 487, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 8, 8, 487, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 487, "RAZ", 1, 0, 0, 0ull},
|
|
{"INEPINT" , 0, 16, 488, "RO", 0, 0, 0ull, 0ull},
|
|
{"OUTEPINT" , 16, 16, 488, "RO", 0, 0, 0ull, 0ull},
|
|
{"INEPMSK" , 0, 16, 489, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OUTEPMSK" , 16, 16, 489, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DEVSPD" , 0, 2, 490, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NZSTSOUTHSHK" , 2, 1, 490, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 490, "RAZ", 1, 1, 0, 0},
|
|
{"DEVADDR" , 4, 7, 490, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PERFRINT" , 11, 2, 490, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_17" , 13, 5, 490, "RAZ", 1, 1, 0, 0},
|
|
{"EPMISCNT" , 18, 5, 490, "R/W", 0, 0, 8ull, 0ull},
|
|
{"RESERVED_23_31" , 23, 9, 490, "RAZ", 1, 1, 0, 0},
|
|
{"RMTWKUPSIG" , 0, 1, 491, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SFTDISCON" , 1, 1, 491, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GNPINNAKSTS" , 2, 1, 491, "RO", 0, 0, 0ull, 0ull},
|
|
{"GOUTNAKSTS" , 3, 1, 491, "RO", 0, 0, 0ull, 0ull},
|
|
{"TSTCTL" , 4, 3, 491, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SGNPINNAK" , 7, 1, 491, "WO", 0, 0, 0ull, 0ull},
|
|
{"CGNPINNAK" , 8, 1, 491, "WO", 0, 0, 0ull, 0ull},
|
|
{"SGOUTNAK" , 9, 1, 491, "WO", 0, 0, 0ull, 0ull},
|
|
{"CGOUTNAK" , 10, 1, 491, "WO", 0, 0, 0ull, 0ull},
|
|
{"PWRONPRGDONE" , 11, 1, 491, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_31" , 12, 20, 491, "RAZ", 1, 1, 0, 0},
|
|
{"MPS" , 0, 11, 492, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NEXTEP" , 11, 4, 492, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBACTEP" , 15, 1, 492, "R/W", 0, 0, 1ull, 0ull},
|
|
{"DPID" , 16, 1, 492, "RO", 0, 0, 0ull, 0ull},
|
|
{"NAKSTS" , 17, 1, 492, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTYPE" , 18, 2, 492, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 492, "RAZ", 1, 1, 0, 0},
|
|
{"STALL" , 21, 1, 492, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFNUM" , 22, 4, 492, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNAK" , 26, 1, 492, "WO", 0, 0, 0ull, 0ull},
|
|
{"SNAK" , 27, 1, 492, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD0PID" , 28, 1, 492, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD1PID" , 29, 1, 492, "WO", 0, 0, 0ull, 0ull},
|
|
{"EPDIS" , 30, 1, 492, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPENA" , 31, 1, 492, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XFERCOMPL" , 0, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLD" , 1, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AHBERR" , 2, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TIMEOUT" , 3, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTKNTXFEMP" , 4, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTKNEPMIS" , 5, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INEPNAKEFF" , 6, 1, 493, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_31" , 7, 25, 493, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPLMSK" , 0, 1, 494, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLDMSK" , 1, 1, 494, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AHBERRMSK" , 2, 1, 494, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMEOUTMSK" , 3, 1, 494, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTKNTXFEMPMSK" , 4, 1, 494, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTKNEPMISMSK" , 5, 1, 494, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INEPNAKEFFMSK" , 6, 1, 494, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_31" , 7, 25, 494, "RAZ", 1, 1, 0, 0},
|
|
{"XFERSIZE" , 0, 19, 495, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKTCNT" , 19, 10, 495, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MC" , 29, 2, 495, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_31" , 31, 1, 495, "RAZ", 1, 1, 0, 0},
|
|
{"MPS" , 0, 11, 496, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_14" , 11, 4, 496, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"USBACTEP" , 15, 1, 496, "R/W", 0, 0, 1ull, 0ull},
|
|
{"DPID" , 16, 1, 496, "RO", 0, 0, 0ull, 0ull},
|
|
{"NAKSTS" , 17, 1, 496, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTYPE" , 18, 2, 496, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SNP" , 20, 1, 496, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STALL" , 21, 1, 496, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_25" , 22, 4, 496, "RAZ", 1, 1, 0, 0},
|
|
{"CNAK" , 26, 1, 496, "WO", 0, 0, 0ull, 0ull},
|
|
{"SNAK" , 27, 1, 496, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD0PID" , 28, 1, 496, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD1PID" , 29, 1, 496, "WO", 0, 0, 0ull, 0ull},
|
|
{"EPDIS" , 30, 1, 496, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPENA" , 31, 1, 496, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XFERCOMPL" , 0, 1, 497, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLD" , 1, 1, 497, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AHBERR" , 2, 1, 497, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SETUP" , 3, 1, 497, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OUTTKNEPDIS" , 4, 1, 497, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 497, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPLMSK" , 0, 1, 498, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLDMSK" , 1, 1, 498, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AHBERRMSK" , 2, 1, 498, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SETUPMSK" , 3, 1, 498, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OUTTKNEPDISMSK" , 4, 1, 498, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 498, "RAZ", 1, 1, 0, 0},
|
|
{"XFERSIZE" , 0, 19, 499, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKTCNT" , 19, 10, 499, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MC" , 29, 2, 499, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_31" , 31, 1, 499, "RAZ", 1, 1, 0, 0},
|
|
{"DPTXFSTADDR" , 0, 16, 500, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPTXFSIZE" , 16, 16, 500, "RO", 0, 0, 1896ull, 1896ull},
|
|
{"SUSPSTS" , 0, 1, 501, "RO", 0, 0, 0ull, 0ull},
|
|
{"ENUMSPD" , 1, 2, 501, "RO", 0, 0, 0ull, 0ull},
|
|
{"ERRTICERR" , 3, 1, 501, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 501, "RAZ", 1, 1, 0, 0},
|
|
{"SOFFN" , 8, 14, 501, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_31" , 22, 10, 501, "RAZ", 1, 1, 0, 0},
|
|
{"INTKNWPTR" , 0, 5, 502, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_6" , 5, 2, 502, "RAZ", 1, 1, 0, 0},
|
|
{"WRAPBIT" , 7, 1, 502, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 8, 24, 502, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 0, 32, 503, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 0, 32, 504, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 0, 32, 505, "RO", 0, 0, 0ull, 0ull},
|
|
{"GLBLINTRMSK" , 0, 1, 506, "R/W", 0, 0, 0ull, 1ull},
|
|
{"HBSTLEN" , 1, 4, 506, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMAEN" , 5, 1, 506, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_6" , 6, 1, 506, "RAZ", 1, 1, 0, 0},
|
|
{"NPTXFEMPLVL" , 7, 1, 506, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PTXFEMPLVL" , 8, 1, 506, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_9_31" , 9, 23, 506, "RAZ", 1, 1, 0, 0},
|
|
{"EPDIR" , 0, 32, 507, "RO", 0, 0, 0ull, 0ull},
|
|
{"OTGMODE" , 0, 3, 508, "RO", 0, 0, 2ull, 2ull},
|
|
{"OTGARCH" , 3, 2, 508, "RO", 0, 0, 1ull, 1ull},
|
|
{"SINGPNT" , 5, 1, 508, "RO", 0, 0, 0ull, 0ull},
|
|
{"HSPHYTYPE" , 6, 2, 508, "RO", 0, 0, 1ull, 1ull},
|
|
{"FSPHYTYPE" , 8, 2, 508, "RO", 0, 0, 0ull, 0ull},
|
|
{"NUMDEVEPS" , 10, 4, 508, "RO", 0, 0, 4ull, 4ull},
|
|
{"NUMHSTCHNL" , 14, 4, 508, "RO", 0, 0, 7ull, 7ull},
|
|
{"PERIOSUPPORT" , 18, 1, 508, "RO", 0, 0, 1ull, 1ull},
|
|
{"DYNFIFOSIZING" , 19, 1, 508, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_20_21" , 20, 2, 508, "RAZ", 1, 1, 0, 0},
|
|
{"NPTXQDEPTH" , 22, 2, 508, "RO", 0, 0, 2ull, 2ull},
|
|
{"PTXQDEPTH" , 24, 2, 508, "RO", 0, 0, 2ull, 2ull},
|
|
{"TKNQDEPTH" , 26, 5, 508, "RO", 0, 0, 30ull, 30ull},
|
|
{"RESERVED_31_31" , 31, 1, 508, "RAZ", 1, 1, 0, 0},
|
|
{"XFERSIZEWIDTH" , 0, 4, 509, "RO", 0, 0, 8ull, 8ull},
|
|
{"PKTSIZEWIDTH" , 4, 3, 509, "RO", 0, 0, 6ull, 6ull},
|
|
{"OTGEN" , 7, 1, 509, "RO", 0, 0, 1ull, 1ull},
|
|
{"I2C_SELECTION" , 8, 1, 509, "RO", 0, 0, 0ull, 0ull},
|
|
{"VENDOR_CONTROL_INTERFACE_SUPPORT", 9, 1, 509, "RO", 0, 0, 0ull, 0ull},
|
|
{"OPTFEATURE" , 10, 1, 509, "RO", 0, 0, 1ull, 1ull},
|
|
{"RSTTYPE" , 11, 1, 509, "RO", 0, 0, 1ull, 1ull},
|
|
{"AHBPHYSYNC" , 12, 1, 509, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 509, "RAZ", 1, 1, 0, 0},
|
|
{"DFIFODEPTH" , 16, 16, 509, "RO", 0, 0, 1824ull, 1824ull},
|
|
{"NUMDEVPERIOEPS" , 0, 4, 510, "RO", 0, 0, 4ull, 4ull},
|
|
{"ENABLEPWROPT" , 4, 1, 510, "RO", 0, 0, 0ull, 0ull},
|
|
{"AHBFREQ" , 5, 1, 510, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_13" , 6, 8, 510, "RAZ", 1, 1, 0, 0},
|
|
{"PHYDATAWIDTH" , 14, 2, 510, "RO", 0, 0, 1ull, 1ull},
|
|
{"NUMCTLEPS" , 16, 4, 510, "RO", 0, 0, 4ull, 4ull},
|
|
{"IDDGFLTR" , 20, 1, 510, "RO", 0, 0, 0ull, 0ull},
|
|
{"VBUSVALIDFLTR" , 21, 1, 510, "RO", 0, 0, 0ull, 0ull},
|
|
{"AVALIDFLTR" , 22, 1, 510, "RO", 0, 0, 1ull, 1ull},
|
|
{"BVALIDFLTR" , 23, 1, 510, "RO", 0, 0, 1ull, 1ull},
|
|
{"SESSENDFLTR" , 24, 1, 510, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_25_31" , 25, 7, 510, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 511, "RAZ", 1, 1, 0, 0},
|
|
{"MODEMISMSK" , 1, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OTGINTMSK" , 2, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SOFMSK" , 3, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RXFLVLMSK" , 4, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NPTXFEMPMSK" , 5, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GINNAKEFFMSK" , 6, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GOUTNAKEFFMSK" , 7, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ULPICKINTMSK" , 8, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"I2CINT" , 9, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ERLYSUSPMSK" , 10, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBSUSPMSK" , 11, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBRSTMSK" , 12, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENUMDONEMSK" , 13, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ISOOUTDROPMSK" , 14, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EOPFMSK" , 15, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 511, "RAZ", 1, 1, 0, 0},
|
|
{"EPMISMSK" , 17, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INEPINTMSK" , 18, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OEPINTMSK" , 19, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INCOMPISOINMSK" , 20, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INCOMPLPMSK" , 21, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FETSUSPMSK" , 22, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 511, "RAZ", 1, 1, 0, 0},
|
|
{"PRTINTMSK" , 24, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HCHINTMSK" , 25, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PTXFEMPMSK" , 26, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 511, "RAZ", 1, 1, 0, 0},
|
|
{"CONIDSTSCHNGMSK" , 28, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DISCONNINTMSK" , 29, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SESSREQINTMSK" , 30, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WKUPINTMSK" , 31, 1, 511, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CURMOD" , 0, 1, 512, "RO", 0, 0, 0ull, 0ull},
|
|
{"MODEMIS" , 1, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OTGINT" , 2, 1, 512, "RO", 0, 0, 0ull, 0ull},
|
|
{"SOF" , 3, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXFLVL" , 4, 1, 512, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPTXFEMP" , 5, 1, 512, "RO", 0, 0, 0ull, 0ull},
|
|
{"GINNAKEFF" , 6, 1, 512, "RO", 0, 0, 0ull, 0ull},
|
|
{"GOUTNAKEFF" , 7, 1, 512, "RO", 0, 0, 0ull, 0ull},
|
|
{"ULPICKINT" , 8, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I2CINT" , 9, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ERLYSUSP" , 10, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USBSUSP" , 11, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USBRST" , 12, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ENUMDONE" , 13, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ISOOUTDROP" , 14, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EOPF" , 15, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 512, "RAZ", 1, 1, 0, 0},
|
|
{"EPMIS" , 17, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IEPINT" , 18, 1, 512, "RO", 0, 0, 0ull, 0ull},
|
|
{"OEPINT" , 19, 1, 512, "RO", 0, 0, 0ull, 0ull},
|
|
{"INCOMPISOIN" , 20, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INCOMPLP" , 21, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FETSUSP" , 22, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 512, "RAZ", 1, 1, 0, 0},
|
|
{"PRTINT" , 24, 1, 512, "RO", 0, 0, 0ull, 0ull},
|
|
{"HCHINT" , 25, 1, 512, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTXFEMP" , 26, 1, 512, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 512, "RAZ", 1, 1, 0, 0},
|
|
{"CONIDSTSCHNG" , 28, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DISCONNINT" , 29, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SESSREQINT" , 30, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WKUPINT" , 31, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NPTXFSTADDR" , 0, 16, 513, "R/W", 0, 0, 1824ull, 456ull},
|
|
{"NPTXFDEP" , 16, 16, 513, "R/W", 0, 0, 1824ull, 912ull},
|
|
{"NPTXFSPCAVAIL" , 0, 16, 514, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPTXQSPCAVAIL" , 16, 8, 514, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPTXQTOP" , 24, 7, 514, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_31" , 31, 1, 514, "RAZ", 1, 1, 0, 0},
|
|
{"SESREQSCS" , 0, 1, 515, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SESREQ" , 1, 1, 515, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_7" , 2, 6, 515, "RAZ", 1, 1, 0, 0},
|
|
{"HSTNEGSCS" , 8, 1, 515, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HNPREQ" , 9, 1, 515, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HSTSETHNPEN" , 10, 1, 515, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DEVHNPEN" , 11, 1, 515, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_15" , 12, 4, 515, "RAZ", 1, 1, 0, 0},
|
|
{"CONIDSTS" , 16, 1, 515, "RO", 1, 1, 0, 0},
|
|
{"DBNCTIME" , 17, 1, 515, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASESVLD" , 18, 1, 515, "RO", 1, 1, 0, 0},
|
|
{"BSESVLD" , 19, 1, 515, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_20_31" , 20, 12, 515, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 516, "RAZ", 1, 1, 0, 0},
|
|
{"SESENDDET" , 2, 1, 516, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_7" , 3, 5, 516, "RAZ", 1, 1, 0, 0},
|
|
{"SESREQSUCSTSCHNG" , 8, 1, 516, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"HSTNEGSUCSTSCHNG" , 9, 1, 516, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_16" , 10, 7, 516, "RAZ", 1, 1, 0, 0},
|
|
{"HSTNEGDET" , 17, 1, 516, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ADEVTOUTCHG" , 18, 1, 516, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DBNCEDONE" , 19, 1, 516, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 516, "RAZ", 1, 1, 0, 0},
|
|
{"CSFTRST" , 0, 1, 517, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HSFTRST" , 1, 1, 517, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMCNTRRST" , 2, 1, 517, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTKNQFLSH" , 3, 1, 517, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RXFFLSH" , 4, 1, 517, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFFLSH" , 5, 1, 517, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFNUM" , 6, 5, 517, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_29" , 11, 19, 517, "RAZ", 1, 1, 0, 0},
|
|
{"DMAREQ" , 30, 1, 517, "RO", 0, 0, 0ull, 0ull},
|
|
{"AHBIDLE" , 31, 1, 517, "RO", 0, 0, 1ull, 1ull},
|
|
{"RXFDEP" , 0, 16, 518, "R/W", 0, 0, 1824ull, 456ull},
|
|
{"RESERVED_16_31" , 16, 16, 518, "RAZ", 1, 1, 0, 0},
|
|
{"EPNUM" , 0, 4, 519, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 519, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 519, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 519, "RO", 0, 0, 0ull, 0ull},
|
|
{"FN" , 21, 4, 519, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_31" , 25, 7, 519, "RAZ", 1, 1, 0, 0},
|
|
{"CHNUM" , 0, 4, 520, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 520, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 520, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 520, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 520, "RAZ", 1, 1, 0, 0},
|
|
{"EPNUM" , 0, 4, 521, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 521, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 521, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 521, "RO", 0, 0, 0ull, 0ull},
|
|
{"FN" , 21, 4, 521, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_31" , 25, 7, 521, "RAZ", 1, 1, 0, 0},
|
|
{"CHNUM" , 0, 4, 522, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 522, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 522, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 522, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 522, "RAZ", 1, 1, 0, 0},
|
|
{"SYNOPSYSID" , 0, 32, 523, "RO", 1, 1, 0, 0},
|
|
{"TOUTCAL" , 0, 3, 524, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHYIF" , 3, 1, 524, "RO", 0, 0, 1ull, 1ull},
|
|
{"ULPI_UTMI_SEL" , 4, 1, 524, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSINTF" , 5, 1, 524, "WO", 0, 0, 0ull, 0ull},
|
|
{"PHYSEL" , 6, 1, 524, "WO", 0, 0, 0ull, 0ull},
|
|
{"DDRSEL" , 7, 1, 524, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SRPCAP" , 8, 1, 524, "RO", 0, 0, 0ull, 0ull},
|
|
{"HNPCAP" , 9, 1, 524, "RO", 0, 0, 0ull, 0ull},
|
|
{"USBTRDTIM" , 10, 4, 524, "R/W", 0, 0, 5ull, 5ull},
|
|
{"RESERVED_14_14" , 14, 1, 524, "RAZ", 1, 1, 0, 0},
|
|
{"PHYLPWRCLKSEL" , 15, 1, 524, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OTGI2CSEL" , 16, 1, 524, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 524, "RAZ", 1, 1, 0, 0},
|
|
{"HAINT" , 0, 16, 525, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_31" , 16, 16, 525, "RAZ", 1, 1, 0, 0},
|
|
{"HAINTMSK" , 0, 16, 526, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_31" , 16, 16, 526, "RAZ", 1, 1, 0, 0},
|
|
{"MPS" , 0, 11, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPNUM" , 11, 4, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPDIR" , 15, 1, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 527, "RAZ", 1, 1, 0, 0},
|
|
{"LSPDDEV" , 17, 1, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPTYPE" , 18, 2, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EC" , 20, 2, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DEVADDR" , 22, 7, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ODDFRM" , 29, 1, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHDIS" , 30, 1, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHENA" , 31, 1, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSLSPCLKSEL" , 0, 2, 528, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSLSSUPP" , 2, 1, 528, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_31" , 3, 29, 528, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPL" , 0, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CHHLTD" , 1, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AHBERR" , 2, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"STALL" , 3, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NAK" , 4, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ACK" , 5, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NYET" , 6, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"XACTERR" , 7, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BBLERR" , 8, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FRMOVRUN" , 9, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DATATGLERR" , 10, 1, 529, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_31" , 11, 21, 529, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPLMSK" , 0, 1, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHHLTDMSK" , 1, 1, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AHBERRMSK" , 2, 1, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STALLMSK" , 3, 1, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NAKMSK" , 4, 1, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ACKMSK" , 5, 1, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NYETMSK" , 6, 1, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XACTERRMSK" , 7, 1, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BBLERRMSK" , 8, 1, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMOVRUNMSK" , 9, 1, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DATATGLERRMSK" , 10, 1, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_31" , 11, 21, 530, "RAZ", 1, 1, 0, 0},
|
|
{"PRTADDR" , 0, 7, 531, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HUBADDR" , 7, 7, 531, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XACTPOS" , 14, 2, 531, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COMPSPLT" , 16, 1, 531, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_30" , 17, 14, 531, "RAZ", 1, 1, 0, 0},
|
|
{"SPLTENA" , 31, 1, 531, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XFERSIZE" , 0, 19, 532, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKTCNT" , 19, 10, 532, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PID" , 29, 2, 532, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DOPNG" , 31, 1, 532, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRINT" , 0, 16, 533, "R/W", 0, 0, 2959ull, 3750ull},
|
|
{"RESERVED_16_31" , 16, 16, 533, "RAZ", 1, 1, 0, 0},
|
|
{"FRNUM" , 0, 16, 534, "RO", 0, 0, 16383ull, 0ull},
|
|
{"FRREM" , 16, 16, 534, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTCONNSTS" , 0, 1, 535, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTCONNDET" , 1, 1, 535, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTENA" , 2, 1, 535, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTENCHNG" , 3, 1, 535, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTOVRCURRACT" , 4, 1, 535, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTOVRCURRCHNG" , 5, 1, 535, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTRES" , 6, 1, 535, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTSUSP" , 7, 1, 535, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTRST" , 8, 1, 535, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 535, "RAZ", 1, 1, 0, 0},
|
|
{"PRTLNSTS" , 10, 2, 535, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTPWR" , 12, 1, 535, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTTSTCTL" , 13, 4, 535, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTSPD" , 17, 2, 535, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_31" , 19, 13, 535, "RAZ", 1, 1, 0, 0},
|
|
{"PTXFSTADDR" , 0, 16, 536, "R/W", 0, 0, 3648ull, 912ull},
|
|
{"PTXFSIZE" , 16, 16, 536, "R/W", 0, 0, 1824ull, 456ull},
|
|
{"PTXFSPCAVAIL" , 0, 16, 537, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTXQSPCAVAIL" , 16, 8, 537, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTXQTOP" , 24, 8, 537, "RO", 0, 0, 0ull, 0ull},
|
|
{"DATA" , 0, 32, 538, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STOPPCLK" , 0, 1, 539, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GATEHCLK" , 1, 1, 539, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PWRCLMP" , 2, 1, 539, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSTPDWNMODULE" , 3, 1, 539, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHYSUSPENDED" , 4, 1, 539, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 539, "RAZ", 1, 1, 0, 0},
|
|
{"NOF_BIS" , 0, 1, 540, "RO", 0, 0, 0ull, 0ull},
|
|
{"NIF_BIS" , 1, 1, 540, "RO", 0, 0, 0ull, 0ull},
|
|
{"USBC_BIS" , 2, 1, 540, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 540, "RAZ", 1, 1, 0, 0},
|
|
{"DIVIDE" , 0, 3, 541, "R/W", 0, 0, 4ull, 4ull},
|
|
{"HRST" , 3, 1, 541, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PRST" , 4, 1, 541, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ENABLE" , 5, 1, 541, "R/W", 0, 0, 1ull, 1ull},
|
|
{"POR" , 6, 1, 541, "R/W", 0, 0, 1ull, 0ull},
|
|
{"S_BIST" , 7, 1, 541, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SD_MODE" , 8, 2, 541, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CDIV_BYP" , 10, 1, 541, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_C_SEL" , 11, 2, 541, "R/W", 0, 0, 2ull, 2ull},
|
|
{"P_COM_ON" , 13, 1, 541, "R/W", 0, 0, 1ull, 1ull},
|
|
{"P_XENBN" , 14, 1, 541, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_RCLK" , 15, 1, 541, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_X_ON" , 16, 1, 541, "R/W", 0, 0, 1ull, 1ull},
|
|
{"HCLK_RST" , 17, 1, 541, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_18_63" , 18, 46, 541, "RAZ", 1, 1, 0, 0},
|
|
{"L2C_EMOD" , 0, 2, 542, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INV_A2" , 2, 1, 542, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_TEST" , 3, 1, 542, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_STT" , 4, 1, 542, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_0PAG" , 5, 1, 542, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 542, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 543, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 543, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 544, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 544, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 545, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 545, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 546, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 546, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 547, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 547, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 548, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 548, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 549, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 549, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 550, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 550, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 551, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 551, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 552, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 552, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 553, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 553, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 554, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 554, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 555, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 555, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 556, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 556, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 557, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 557, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 558, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 558, "RAZ", 1, 1, 0, 0},
|
|
{"BURST" , 0, 4, 559, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHANNEL" , 4, 5, 559, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COUNT" , 9, 11, 559, "R/W", 0, 0, 0ull, 0ull},
|
|
{"F_ADDR" , 20, 18, 559, "R/W", 0, 0, 0ull, 0ull},
|
|
{"REQ" , 38, 1, 559, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DONE" , 39, 1, 559, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 559, "RAZ", 1, 1, 0, 0},
|
|
{"PR_PO_E" , 0, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PR_PU_F" , 1, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NR_PO_E" , 2, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NR_PU_F" , 3, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LR_PO_E" , 4, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LR_PU_F" , 5, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PT_PO_E" , 6, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PT_PU_F" , 7, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NT_PO_E" , 8, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NT_PU_F" , 9, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LT_PO_E" , 10, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LT_PU_F" , 11, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DCRED_E" , 12, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DCRED_F" , 13, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2C_S_E" , 14, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2C_A_F" , 15, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2_FI_E" , 16, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2_FI_F" , 17, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_E" , 18, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_F" , 19, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_F" , 20, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_E" , 21, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_F" , 22, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_E" , 23, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UOD_PE" , 24, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UOD_PF" , 25, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"N2U_PF" , 26, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"N2U_PE" , 27, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"U2N_D_PE" , 28, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"U2N_D_PF" , 29, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"U2N_C_PF" , 30, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"U2N_C_PE" , 31, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LTL_F_PE" , 32, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LTL_F_PF" , 33, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_RPE" , 34, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_RPF" , 35, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_DPE" , 36, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_DPF" , 37, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 560, "RAZ", 1, 1, 0, 0},
|
|
{"PR_PO_E" , 0, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PR_PU_F" , 1, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NR_PO_E" , 2, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NR_PU_F" , 3, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LR_PO_E" , 4, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LR_PU_F" , 5, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PT_PO_E" , 6, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PT_PU_F" , 7, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NT_PO_E" , 8, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NT_PU_F" , 9, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LT_PO_E" , 10, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LT_PU_F" , 11, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCRED_E" , 12, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCRED_F" , 13, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"L2C_S_E" , 14, 1, 561, "R/W1C", 1, 0, 0, 0ull},
|
|
{"L2C_A_F" , 15, 1, 561, "R/W1C", 1, 0, 0, 0ull},
|
|
{"LT_FI_E" , 16, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LT_FI_F" , 17, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_E" , 18, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_F" , 19, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_F" , 20, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_E" , 21, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_F" , 22, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_E" , 23, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UOD_PE" , 24, 1, 561, "R/W1C", 1, 0, 0, 0ull},
|
|
{"UOD_PF" , 25, 1, 561, "R/W1C", 1, 0, 0, 0ull},
|
|
{"N2U_PF" , 26, 1, 561, "R/W1C", 1, 0, 0, 0ull},
|
|
{"N2U_PE" , 27, 1, 561, "R/W1C", 1, 0, 0, 0ull},
|
|
{"U2N_D_PE" , 28, 1, 561, "R/W1C", 1, 0, 0, 0ull},
|
|
{"U2N_D_PF" , 29, 1, 561, "R/W1C", 1, 0, 0, 0ull},
|
|
{"U2N_C_PF" , 30, 1, 561, "R/W1C", 1, 0, 0, 0ull},
|
|
{"U2N_C_PE" , 31, 1, 561, "R/W1C", 1, 0, 0, 0ull},
|
|
{"LTL_F_PE" , 32, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LTL_F_PF" , 33, 1, 561, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ND4O_RPE" , 34, 1, 561, "R/W1C", 1, 0, 0, 0ull},
|
|
{"ND4O_RPF" , 35, 1, 561, "R/W1C", 1, 0, 0, 0ull},
|
|
{"ND4O_DPE" , 36, 1, 561, "R/W1C", 1, 0, 0, 0ull},
|
|
{"ND4O_DPF" , 37, 1, 561, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 561, "RAZ", 1, 1, 0, 0},
|
|
{"ATE_RESET" , 0, 1, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TDATA_IN" , 1, 8, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TADDR_IN" , 9, 4, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TDATA_SEL" , 13, 1, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BIST_ENB" , 14, 1, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VTEST_ENB" , 15, 1, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LOOP_ENB" , 16, 1, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TX_BS_EN" , 17, 1, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TX_BS_ENH" , 18, 1, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TUNING" , 19, 4, 562, "R/W", 0, 0, 9ull, 0ull},
|
|
{"HST_MODE" , 23, 1, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DM_PULLD" , 24, 1, 562, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DP_PULLD" , 25, 1, 562, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TCLK" , 26, 1, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBP_BIST" , 27, 1, 562, "R/W", 0, 0, 1ull, 1ull},
|
|
{"USBC_END" , 28, 1, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_BMODE" , 29, 1, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_31" , 30, 2, 562, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TDATA_OUT" , 32, 4, 562, "RO", 1, 1, 0, 0},
|
|
{"BIST_ERR" , 36, 1, 562, "RO", 0, 0, 0ull, 0ull},
|
|
{"BIST_DONE" , 37, 1, 562, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 562, "RAZ", 1, 1, 0, 0},
|
|
{NULL,0,0,0,0,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn38xx[] = {
|
|
/* name , ---------------type, bits, off, #field, fld of */
|
|
{"cvmx_asx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 4, 0},
|
|
{"cvmx_asx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 4, 4},
|
|
{"cvmx_asx#_prt_loop" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 3, 8},
|
|
{"cvmx_asx#_rld_bypass" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 2, 11},
|
|
{"cvmx_asx#_rld_bypass_setting", CVMX_CSR_DB_TYPE_RSL, 64, 8, 2, 13},
|
|
{"cvmx_asx#_rld_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 3, 15},
|
|
{"cvmx_asx#_rld_data_drv" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 3, 18},
|
|
{"cvmx_asx#_rld_fcram_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 2, 21},
|
|
{"cvmx_asx#_rld_nctl_strong" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 2, 23},
|
|
{"cvmx_asx#_rld_nctl_weak" , CVMX_CSR_DB_TYPE_RSL, 64, 18, 2, 25},
|
|
{"cvmx_asx#_rld_pctl_strong" , CVMX_CSR_DB_TYPE_RSL, 64, 20, 2, 27},
|
|
{"cvmx_asx#_rld_pctl_weak" , CVMX_CSR_DB_TYPE_RSL, 64, 22, 2, 29},
|
|
{"cvmx_asx#_rld_setting" , CVMX_CSR_DB_TYPE_RSL, 64, 24, 2, 31},
|
|
{"cvmx_asx#_rx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 26, 2, 33},
|
|
{"cvmx_asx#_rx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 34, 2, 35},
|
|
{"cvmx_asx#_rx_wol" , CVMX_CSR_DB_TYPE_RSL, 64, 36, 3, 37},
|
|
{"cvmx_asx#_rx_wol_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 38, 1, 40},
|
|
{"cvmx_asx#_rx_wol_powok" , CVMX_CSR_DB_TYPE_RSL, 64, 40, 2, 41},
|
|
{"cvmx_asx#_rx_wol_sig" , CVMX_CSR_DB_TYPE_RSL, 64, 42, 2, 43},
|
|
{"cvmx_asx#_tx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 44, 2, 45},
|
|
{"cvmx_asx#_tx_comp_byp" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 3, 47},
|
|
{"cvmx_asx#_tx_hi_water#" , CVMX_CSR_DB_TYPE_RSL, 64, 54, 2, 50},
|
|
{"cvmx_asx#_tx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 62, 2, 52},
|
|
{"cvmx_asx0_dbg_data_drv" , CVMX_CSR_DB_TYPE_RSL, 64, 64, 3, 54},
|
|
{"cvmx_asx0_dbg_data_enable" , CVMX_CSR_DB_TYPE_RSL, 64, 65, 2, 57},
|
|
{"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 66, 2, 59},
|
|
{"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 67, 2, 61},
|
|
{"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 68, 2, 63},
|
|
{"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 69, 2, 65},
|
|
{"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 70, 15, 67},
|
|
{"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 103, 2, 82},
|
|
{"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 136, 15, 84},
|
|
{"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 169, 2, 99},
|
|
{"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 170, 2, 101},
|
|
{"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 186, 2, 103},
|
|
{"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 202, 2, 105},
|
|
{"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 203, 2, 107},
|
|
{"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 204, 2, 109},
|
|
{"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 205, 1, 111},
|
|
{"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 221, 3, 112},
|
|
{"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 222, 2, 115},
|
|
{"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 223, 4, 117},
|
|
{"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 224, 2, 121},
|
|
{"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 225, 3, 123},
|
|
{"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 229, 7, 126},
|
|
{"cvmx_dbg_data" , CVMX_CSR_DB_TYPE_NCB, 64, 245, 7, 133},
|
|
{"cvmx_dfa_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 246, 3, 140},
|
|
{"cvmx_dfa_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 247, 10, 143},
|
|
{"cvmx_dfa_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 248, 5, 153},
|
|
{"cvmx_dfa_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 249, 2, 158},
|
|
{"cvmx_dfa_difctl" , CVMX_CSR_DB_TYPE_NCB, 64, 250, 4, 160},
|
|
{"cvmx_dfa_difrdptr" , CVMX_CSR_DB_TYPE_NCB, 64, 251, 3, 164},
|
|
{"cvmx_dfa_err" , CVMX_CSR_DB_TYPE_RSL, 64, 252, 21, 167},
|
|
{"cvmx_dfa_memcfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 253, 17, 188},
|
|
{"cvmx_dfa_memcfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 254, 11, 205},
|
|
{"cvmx_dfa_memcfg2" , CVMX_CSR_DB_TYPE_RSL, 64, 255, 8, 216},
|
|
{"cvmx_dfa_memfadr" , CVMX_CSR_DB_TYPE_RSL, 64, 256, 6, 224},
|
|
{"cvmx_dfa_memfcr" , CVMX_CSR_DB_TYPE_RSL, 64, 257, 6, 230},
|
|
{"cvmx_dfa_memrld" , CVMX_CSR_DB_TYPE_RSL, 64, 258, 2, 236},
|
|
{"cvmx_dfa_ncbctl" , CVMX_CSR_DB_TYPE_RSL, 64, 259, 8, 238},
|
|
{"cvmx_dfa_sbd_dbg0" , CVMX_CSR_DB_TYPE_RSL, 64, 260, 1, 246},
|
|
{"cvmx_dfa_sbd_dbg1" , CVMX_CSR_DB_TYPE_RSL, 64, 261, 1, 247},
|
|
{"cvmx_dfa_sbd_dbg2" , CVMX_CSR_DB_TYPE_RSL, 64, 262, 1, 248},
|
|
{"cvmx_dfa_sbd_dbg3" , CVMX_CSR_DB_TYPE_RSL, 64, 263, 1, 249},
|
|
{"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 264, 6, 250},
|
|
{"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 265, 7, 256},
|
|
{"cvmx_fpa_fpf#_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 266, 3, 263},
|
|
{"cvmx_fpa_fpf#_size" , CVMX_CSR_DB_TYPE_RSL, 64, 273, 2, 266},
|
|
{"cvmx_fpa_fpf0_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 280, 3, 268},
|
|
{"cvmx_fpa_fpf0_size" , CVMX_CSR_DB_TYPE_RSL, 64, 281, 2, 271},
|
|
{"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 282, 29, 273},
|
|
{"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 283, 29, 302},
|
|
{"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 284, 2, 331},
|
|
{"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 292, 2, 333},
|
|
{"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 300, 3, 335},
|
|
{"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 301, 3, 338},
|
|
{"cvmx_fpa_wart_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 302, 2, 341},
|
|
{"cvmx_fpa_wart_status" , CVMX_CSR_DB_TYPE_RSL, 64, 303, 2, 343},
|
|
{"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 304, 8, 345},
|
|
{"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 306, 2, 353},
|
|
{"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 308, 3, 355},
|
|
{"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 310, 2, 358},
|
|
{"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 312, 5, 360},
|
|
{"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 320, 1, 365},
|
|
{"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 328, 1, 366},
|
|
{"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 336, 1, 367},
|
|
{"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 344, 1, 368},
|
|
{"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 352, 1, 369},
|
|
{"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 360, 1, 370},
|
|
{"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 368, 2, 371},
|
|
{"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 376, 4, 373},
|
|
{"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 384, 2, 377},
|
|
{"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 392, 11, 379},
|
|
{"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 400, 10, 390},
|
|
{"cvmx_gmx#_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 408, 2, 400},
|
|
{"cvmx_gmx#_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 416, 2, 402},
|
|
{"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 424, 2, 404},
|
|
{"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 432, 20, 406},
|
|
{"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 440, 20, 426},
|
|
{"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 448, 2, 446},
|
|
{"cvmx_gmx#_rx#_rx_inbnd" , CVMX_CSR_DB_TYPE_RSL, 64, 456, 4, 448},
|
|
{"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 464, 2, 452},
|
|
{"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 472, 2, 454},
|
|
{"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 480, 2, 456},
|
|
{"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 488, 2, 458},
|
|
{"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 496, 2, 460},
|
|
{"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 504, 2, 462},
|
|
{"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 512, 2, 464},
|
|
{"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 520, 2, 466},
|
|
{"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 528, 2, 468},
|
|
{"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 536, 2, 470},
|
|
{"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 544, 4, 472},
|
|
{"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 552, 2, 476},
|
|
{"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 560, 2, 478},
|
|
{"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 568, 2, 480},
|
|
{"cvmx_gmx#_rx_pass_en" , CVMX_CSR_DB_TYPE_RSL, 64, 576, 2, 482},
|
|
{"cvmx_gmx#_rx_pass_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 578, 2, 484},
|
|
{"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 610, 3, 486},
|
|
{"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 612, 2, 489},
|
|
{"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 614, 2, 491},
|
|
{"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 622, 3, 493},
|
|
{"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 624, 5, 496},
|
|
{"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 632, 2, 501},
|
|
{"cvmx_gmx#_tx#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 640, 2, 503},
|
|
{"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 648, 3, 505},
|
|
{"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 656, 2, 508},
|
|
{"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 664, 2, 510},
|
|
{"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 672, 2, 512},
|
|
{"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 680, 2, 514},
|
|
{"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 688, 2, 516},
|
|
{"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 696, 2, 518},
|
|
{"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 704, 2, 520},
|
|
{"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 712, 2, 522},
|
|
{"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 720, 2, 524},
|
|
{"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 728, 2, 526},
|
|
{"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 736, 2, 528},
|
|
{"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 744, 2, 530},
|
|
{"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 752, 2, 532},
|
|
{"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 760, 2, 534},
|
|
{"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 768, 2, 536},
|
|
{"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 776, 2, 538},
|
|
{"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 784, 2, 540},
|
|
{"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 792, 2, 542},
|
|
{"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 800, 2, 544},
|
|
{"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 808, 2, 546},
|
|
{"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 810, 2, 548},
|
|
{"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 812, 2, 550},
|
|
{"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 814, 3, 552},
|
|
{"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 816, 8, 555},
|
|
{"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 818, 8, 563},
|
|
{"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 820, 2, 571},
|
|
{"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 822, 2, 573},
|
|
{"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 824, 4, 575},
|
|
{"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 826, 2, 579},
|
|
{"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 828, 2, 581},
|
|
{"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 830, 2, 583},
|
|
{"cvmx_gmx#_tx_spi_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 832, 3, 585},
|
|
{"cvmx_gmx#_tx_spi_drain" , CVMX_CSR_DB_TYPE_RSL, 64, 834, 2, 588},
|
|
{"cvmx_gmx#_tx_spi_max" , CVMX_CSR_DB_TYPE_RSL, 64, 836, 3, 590},
|
|
{"cvmx_gmx#_tx_spi_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 838, 2, 593},
|
|
{"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 840, 7, 595},
|
|
{"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 856, 2, 602},
|
|
{"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 857, 2, 604},
|
|
{"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 858, 2, 606},
|
|
{"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 859, 2, 608},
|
|
{"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 860, 19, 610},
|
|
{"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 861, 6, 629},
|
|
{"cvmx_iob_dwb_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 862, 3, 635},
|
|
{"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 863, 3, 638},
|
|
{"cvmx_iob_i2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 864, 3, 641},
|
|
{"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 865, 5, 644},
|
|
{"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 866, 5, 649},
|
|
{"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 867, 1, 654},
|
|
{"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 868, 1, 655},
|
|
{"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 869, 5, 656},
|
|
{"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 870, 5, 661},
|
|
{"cvmx_iob_n2c_l2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 871, 3, 666},
|
|
{"cvmx_iob_n2c_rsp_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 872, 3, 669},
|
|
{"cvmx_iob_outb_com_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 873, 3, 672},
|
|
{"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 874, 5, 675},
|
|
{"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 875, 5, 680},
|
|
{"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 876, 1, 685},
|
|
{"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 877, 1, 686},
|
|
{"cvmx_iob_outb_fpa_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 878, 3, 687},
|
|
{"cvmx_iob_outb_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 879, 3, 690},
|
|
{"cvmx_iob_p2c_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 880, 3, 693},
|
|
{"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 881, 2, 696},
|
|
{"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 882, 2, 698},
|
|
{"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 883, 2, 700},
|
|
{"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 884, 2, 702},
|
|
{"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 885, 17, 704},
|
|
{"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 886, 2, 721},
|
|
{"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 887, 1, 723},
|
|
{"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 888, 10, 724},
|
|
{"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 889, 11, 734},
|
|
{"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 890, 11, 745},
|
|
{"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 891, 2, 756},
|
|
{"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 892, 2, 758},
|
|
{"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 893, 2, 760},
|
|
{"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 894, 3, 762},
|
|
{"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 930, 2, 765},
|
|
{"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 966, 6, 767},
|
|
{"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 967, 5, 773},
|
|
{"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 968, 6, 778},
|
|
{"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 969, 7, 784},
|
|
{"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 970, 2, 791},
|
|
{"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 978, 2, 793},
|
|
{"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 979, 3, 795},
|
|
{"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 980, 5, 798},
|
|
{"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 988, 3, 803},
|
|
{"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 989, 2, 806},
|
|
{"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 990, 2, 808},
|
|
{"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 991, 2, 810},
|
|
{"cvmx_key_bist_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 992, 4, 812},
|
|
{"cvmx_key_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 993, 3, 816},
|
|
{"cvmx_key_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 994, 5, 819},
|
|
{"cvmx_key_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 995, 5, 824},
|
|
{"cvmx_l2c_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 996, 5, 829},
|
|
{"cvmx_l2c_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 997, 5, 834},
|
|
{"cvmx_l2c_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 998, 8, 839},
|
|
{"cvmx_l2c_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 999, 9, 847},
|
|
{"cvmx_l2c_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1000, 8, 856},
|
|
{"cvmx_l2c_dut" , CVMX_CSR_DB_TYPE_RSL, 64, 1001, 5, 864},
|
|
{"cvmx_l2c_lckbase" , CVMX_CSR_DB_TYPE_RSL, 64, 1002, 4, 869},
|
|
{"cvmx_l2c_lckoff" , CVMX_CSR_DB_TYPE_RSL, 64, 1003, 2, 873},
|
|
{"cvmx_l2c_lfb0" , CVMX_CSR_DB_TYPE_RSL, 64, 1004, 14, 875},
|
|
{"cvmx_l2c_lfb1" , CVMX_CSR_DB_TYPE_RSL, 64, 1005, 19, 889},
|
|
{"cvmx_l2c_lfb2" , CVMX_CSR_DB_TYPE_RSL, 64, 1006, 3, 908},
|
|
{"cvmx_l2c_lfb3" , CVMX_CSR_DB_TYPE_RSL, 64, 1007, 3, 911},
|
|
{"cvmx_l2c_pfc#" , CVMX_CSR_DB_TYPE_RSL, 64, 1008, 2, 914},
|
|
{"cvmx_l2c_pfctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1012, 17, 916},
|
|
{"cvmx_l2c_spar0" , CVMX_CSR_DB_TYPE_RSL, 64, 1013, 5, 933},
|
|
{"cvmx_l2c_spar1" , CVMX_CSR_DB_TYPE_RSL, 64, 1014, 5, 938},
|
|
{"cvmx_l2c_spar2" , CVMX_CSR_DB_TYPE_RSL, 64, 1015, 5, 943},
|
|
{"cvmx_l2c_spar3" , CVMX_CSR_DB_TYPE_RSL, 64, 1016, 5, 948},
|
|
{"cvmx_l2c_spar4" , CVMX_CSR_DB_TYPE_RSL, 64, 1017, 2, 953},
|
|
{"cvmx_l2d_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 1018, 3, 955},
|
|
{"cvmx_l2d_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 1019, 2, 958},
|
|
{"cvmx_l2d_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 1020, 2, 960},
|
|
{"cvmx_l2d_bst3" , CVMX_CSR_DB_TYPE_RSL, 64, 1021, 2, 962},
|
|
{"cvmx_l2d_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1022, 7, 964},
|
|
{"cvmx_l2d_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1023, 4, 971},
|
|
{"cvmx_l2d_fsyn0" , CVMX_CSR_DB_TYPE_RSL, 64, 1024, 3, 975},
|
|
{"cvmx_l2d_fsyn1" , CVMX_CSR_DB_TYPE_RSL, 64, 1025, 3, 978},
|
|
{"cvmx_l2d_fus0" , CVMX_CSR_DB_TYPE_RSL, 64, 1026, 2, 981},
|
|
{"cvmx_l2d_fus1" , CVMX_CSR_DB_TYPE_RSL, 64, 1027, 2, 983},
|
|
{"cvmx_l2d_fus2" , CVMX_CSR_DB_TYPE_RSL, 64, 1028, 2, 985},
|
|
{"cvmx_l2d_fus3" , CVMX_CSR_DB_TYPE_RSL, 64, 1029, 4, 987},
|
|
{"cvmx_l2t_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1030, 13, 991},
|
|
{"cvmx_led_blink" , CVMX_CSR_DB_TYPE_RSL, 64, 1031, 2, 1004},
|
|
{"cvmx_led_clk_phase" , CVMX_CSR_DB_TYPE_RSL, 64, 1032, 2, 1006},
|
|
{"cvmx_led_cylon" , CVMX_CSR_DB_TYPE_RSL, 64, 1033, 2, 1008},
|
|
{"cvmx_led_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1034, 2, 1010},
|
|
{"cvmx_led_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1035, 2, 1012},
|
|
{"cvmx_led_polarity" , CVMX_CSR_DB_TYPE_RSL, 64, 1036, 2, 1014},
|
|
{"cvmx_led_prt" , CVMX_CSR_DB_TYPE_RSL, 64, 1037, 2, 1016},
|
|
{"cvmx_led_prt_fmt" , CVMX_CSR_DB_TYPE_RSL, 64, 1038, 2, 1018},
|
|
{"cvmx_led_prt_status#" , CVMX_CSR_DB_TYPE_RSL, 64, 1039, 2, 1020},
|
|
{"cvmx_led_udd_cnt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1047, 2, 1022},
|
|
{"cvmx_led_udd_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 1049, 2, 1024},
|
|
{"cvmx_led_udd_dat_clr#" , CVMX_CSR_DB_TYPE_RSL, 64, 1051, 2, 1026},
|
|
{"cvmx_led_udd_dat_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 1053, 2, 1028},
|
|
{"cvmx_lmc#_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1055, 9, 1030},
|
|
{"cvmx_lmc#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1056, 19, 1039},
|
|
{"cvmx_lmc#_dclk_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1057, 2, 1058},
|
|
{"cvmx_lmc#_dclk_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1058, 2, 1060},
|
|
{"cvmx_lmc#_ddr2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1059, 18, 1062},
|
|
{"cvmx_lmc#_delay_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1060, 6, 1080},
|
|
{"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 1061, 5, 1086},
|
|
{"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1062, 6, 1091},
|
|
{"cvmx_lmc#_ifb_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1063, 2, 1097},
|
|
{"cvmx_lmc#_ifb_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1064, 2, 1099},
|
|
{"cvmx_lmc#_mem_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 1065, 14, 1101},
|
|
{"cvmx_lmc#_mem_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 1066, 9, 1115},
|
|
{"cvmx_lmc#_ops_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1067, 2, 1124},
|
|
{"cvmx_lmc#_ops_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1068, 2, 1126},
|
|
{"cvmx_lmc#_pll_bwctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1069, 3, 1128},
|
|
{"cvmx_lmc#_rodt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1070, 9, 1131},
|
|
{"cvmx_lmc#_wodt_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 1071, 9, 1140},
|
|
{"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 1072, 4, 1149},
|
|
{"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1073, 3, 1153},
|
|
{"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1074, 3, 1156},
|
|
{"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1075, 3, 1159},
|
|
{"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1076, 5, 1162},
|
|
{"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1078, 1, 1167},
|
|
{"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1079, 6, 1168},
|
|
{"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 1087, 13, 1174},
|
|
{"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1095, 4, 1187},
|
|
{"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 1096, 2, 1191},
|
|
{"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 1097, 2, 1193},
|
|
{"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 1098, 8, 1195},
|
|
{"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 1099, 8, 1203},
|
|
{"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 1100, 2, 1211},
|
|
{"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1101, 8, 1213},
|
|
{"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 1102, 4, 1221},
|
|
{"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1103, 2, 1225},
|
|
{"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1104, 2, 1227},
|
|
{"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1105, 13, 1229},
|
|
{"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 1106, 12, 1242},
|
|
{"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 1107, 3, 1254},
|
|
{"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 1108, 3, 1257},
|
|
{"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 1109, 2, 1260},
|
|
{"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 1111, 2, 1262},
|
|
{"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 1113, 2, 1264},
|
|
{"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1115, 7, 1266},
|
|
{"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 1117, 2, 1273},
|
|
{"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 1119, 7, 1275},
|
|
{"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 1121, 4, 1282},
|
|
{"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1123, 8, 1286},
|
|
{"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 1125, 9, 1294},
|
|
{"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1127, 7, 1303},
|
|
{"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 1129, 9, 1310},
|
|
{"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 1131, 2, 1319},
|
|
{"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1133, 2, 1321},
|
|
{"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 1135, 4, 1323},
|
|
{"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1137, 2, 1327},
|
|
{"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 1139, 2, 1329},
|
|
{"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 1141, 2, 1331},
|
|
{"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 1143, 4, 1333},
|
|
{"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 1145, 2, 1337},
|
|
{"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 1147, 2, 1339},
|
|
{"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 1149, 2, 1341},
|
|
{"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1151, 2, 1343},
|
|
{"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 1153, 2, 1345},
|
|
{"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1155, 2, 1347},
|
|
{"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 1157, 6, 1349},
|
|
{"cvmx_npi_base_addr_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 1159, 2, 1355},
|
|
{"cvmx_npi_base_addr_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1163, 2, 1357},
|
|
{"cvmx_npi_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1167, 21, 1359},
|
|
{"cvmx_npi_buff_size_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1168, 3, 1380},
|
|
{"cvmx_npi_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1172, 21, 1383},
|
|
{"cvmx_npi_dbg_select" , CVMX_CSR_DB_TYPE_NCB, 64, 1173, 2, 1404},
|
|
{"cvmx_npi_dma_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1174, 13, 1406},
|
|
{"cvmx_npi_dma_highp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 1175, 3, 1419},
|
|
{"cvmx_npi_dma_highp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1176, 3, 1422},
|
|
{"cvmx_npi_dma_lowp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 1177, 3, 1425},
|
|
{"cvmx_npi_dma_lowp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1178, 3, 1428},
|
|
{"cvmx_npi_highp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 1179, 2, 1431},
|
|
{"cvmx_npi_highp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1180, 2, 1433},
|
|
{"cvmx_npi_input_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1181, 10, 1435},
|
|
{"cvmx_npi_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 1182, 63, 1445},
|
|
{"cvmx_npi_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 1183, 63, 1508},
|
|
{"cvmx_npi_lowp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 1184, 2, 1571},
|
|
{"cvmx_npi_lowp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1185, 2, 1573},
|
|
{"cvmx_npi_mem_access_subid#" , CVMX_CSR_DB_TYPE_NCB, 64, 1186, 10, 1575},
|
|
{"cvmx_npi_msi_rcv" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1190, 1, 1585},
|
|
{"cvmx_npi_num_desc_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1191, 2, 1586},
|
|
{"cvmx_npi_output_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1195, 39, 1588},
|
|
{"cvmx_npi_p#_dbpair_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 1196, 3, 1627},
|
|
{"cvmx_npi_p#_instr_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 1200, 2, 1630},
|
|
{"cvmx_npi_p#_instr_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 1204, 3, 1632},
|
|
{"cvmx_npi_p#_pair_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 1208, 3, 1635},
|
|
{"cvmx_npi_pci_burst_size" , CVMX_CSR_DB_TYPE_NCB, 64, 1212, 3, 1638},
|
|
{"cvmx_npi_pci_int_arb_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 1213, 4, 1641},
|
|
{"cvmx_npi_pci_read_cmd" , CVMX_CSR_DB_TYPE_NCB, 64, 1214, 2, 1645},
|
|
{"cvmx_npi_port32_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1215, 13, 1647},
|
|
{"cvmx_npi_port33_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1216, 13, 1660},
|
|
{"cvmx_npi_port34_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1217, 13, 1673},
|
|
{"cvmx_npi_port35_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1218, 13, 1686},
|
|
{"cvmx_npi_port_bp_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1219, 3, 1699},
|
|
{"cvmx_npi_rsl_int_blocks" , CVMX_CSR_DB_TYPE_NCB, 64, 1220, 33, 1702},
|
|
{"cvmx_npi_size_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 1221, 2, 1735},
|
|
{"cvmx_npi_win_read_to" , CVMX_CSR_DB_TYPE_NCB, 64, 1225, 2, 1737},
|
|
{"cvmx_pci_bar1_index#" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1226, 5, 1739},
|
|
{"cvmx_pci_cfg00" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1258, 2, 1744},
|
|
{"cvmx_pci_cfg01" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1259, 24, 1746},
|
|
{"cvmx_pci_cfg02" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1260, 2, 1770},
|
|
{"cvmx_pci_cfg03" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1261, 7, 1772},
|
|
{"cvmx_pci_cfg04" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1262, 5, 1779},
|
|
{"cvmx_pci_cfg05" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1263, 1, 1784},
|
|
{"cvmx_pci_cfg06" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1264, 5, 1785},
|
|
{"cvmx_pci_cfg07" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1265, 1, 1790},
|
|
{"cvmx_pci_cfg08" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1266, 4, 1791},
|
|
{"cvmx_pci_cfg09" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1267, 2, 1795},
|
|
{"cvmx_pci_cfg10" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1268, 1, 1797},
|
|
{"cvmx_pci_cfg11" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1269, 2, 1798},
|
|
{"cvmx_pci_cfg12" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1270, 4, 1800},
|
|
{"cvmx_pci_cfg13" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1271, 2, 1804},
|
|
{"cvmx_pci_cfg15" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1272, 4, 1806},
|
|
{"cvmx_pci_cfg16" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1273, 16, 1810},
|
|
{"cvmx_pci_cfg17" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1274, 1, 1826},
|
|
{"cvmx_pci_cfg18" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1275, 1, 1827},
|
|
{"cvmx_pci_cfg19" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1276, 18, 1828},
|
|
{"cvmx_pci_cfg20" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1277, 1, 1846},
|
|
{"cvmx_pci_cfg21" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1278, 1, 1847},
|
|
{"cvmx_pci_cfg22" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1279, 7, 1848},
|
|
{"cvmx_pci_cfg56" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1280, 7, 1855},
|
|
{"cvmx_pci_cfg57" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1281, 13, 1862},
|
|
{"cvmx_pci_cfg58" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1282, 10, 1875},
|
|
{"cvmx_pci_cfg59" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1283, 10, 1885},
|
|
{"cvmx_pci_cfg60" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1284, 7, 1895},
|
|
{"cvmx_pci_cfg61" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1285, 2, 1902},
|
|
{"cvmx_pci_cfg62" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1286, 1, 1904},
|
|
{"cvmx_pci_cfg63" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1287, 2, 1905},
|
|
{"cvmx_pci_ctl_status_2" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1288, 22, 1907},
|
|
{"cvmx_pci_dbell#" , CVMX_CSR_DB_TYPE_PCI, 32, 1289, 2, 1929},
|
|
{"cvmx_pci_dma_cnt#" , CVMX_CSR_DB_TYPE_PCI, 32, 1293, 1, 1931},
|
|
{"cvmx_pci_dma_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 1295, 1, 1932},
|
|
{"cvmx_pci_dma_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 1297, 1, 1933},
|
|
{"cvmx_pci_instr_count#" , CVMX_CSR_DB_TYPE_PCI, 32, 1299, 1, 1934},
|
|
{"cvmx_pci_int_enb" , CVMX_CSR_DB_TYPE_PCI, 64, 1303, 35, 1935},
|
|
{"cvmx_pci_int_enb2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1304, 35, 1970},
|
|
{"cvmx_pci_int_sum" , CVMX_CSR_DB_TYPE_PCI, 64, 1305, 35, 2005},
|
|
{"cvmx_pci_int_sum2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1306, 35, 2040},
|
|
{"cvmx_pci_msi_rcv" , CVMX_CSR_DB_TYPE_PCI, 32, 1307, 2, 2075},
|
|
{"cvmx_pci_pkt_credits#" , CVMX_CSR_DB_TYPE_PCI, 32, 1308, 2, 2077},
|
|
{"cvmx_pci_pkts_sent#" , CVMX_CSR_DB_TYPE_PCI, 32, 1312, 1, 2079},
|
|
{"cvmx_pci_pkts_sent_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 1316, 1, 2080},
|
|
{"cvmx_pci_pkts_sent_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 1320, 1, 2081},
|
|
{"cvmx_pci_read_cmd_6" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1324, 3, 2082},
|
|
{"cvmx_pci_read_cmd_c" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1325, 3, 2085},
|
|
{"cvmx_pci_read_cmd_e" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1326, 3, 2088},
|
|
{"cvmx_pci_read_timeout" , CVMX_CSR_DB_TYPE_NCB, 64, 1327, 3, 2091},
|
|
{"cvmx_pci_scm_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1328, 2, 2094},
|
|
{"cvmx_pci_tsr_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1329, 2, 2096},
|
|
{"cvmx_pci_win_rd_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 1330, 4, 2098},
|
|
{"cvmx_pci_win_rd_data" , CVMX_CSR_DB_TYPE_PCI, 64, 1331, 1, 2102},
|
|
{"cvmx_pci_win_wr_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 1332, 4, 2103},
|
|
{"cvmx_pci_win_wr_data" , CVMX_CSR_DB_TYPE_PCI, 64, 1333, 1, 2107},
|
|
{"cvmx_pci_win_wr_mask" , CVMX_CSR_DB_TYPE_PCI, 64, 1334, 2, 2108},
|
|
{"cvmx_pip_bck_prs" , CVMX_CSR_DB_TYPE_RSL, 64, 1335, 5, 2110},
|
|
{"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1336, 2, 2115},
|
|
{"cvmx_pip_crc_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 1337, 3, 2117},
|
|
{"cvmx_pip_crc_iv#" , CVMX_CSR_DB_TYPE_RSL, 64, 1339, 2, 2120},
|
|
{"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 1341, 4, 2122},
|
|
{"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1345, 8, 2126},
|
|
{"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1346, 16, 2134},
|
|
{"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1347, 10, 2150},
|
|
{"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1348, 10, 2160},
|
|
{"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 1349, 2, 2170},
|
|
{"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1350, 18, 2172},
|
|
{"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 1386, 25, 2190},
|
|
{"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 1422, 2, 2215},
|
|
{"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 1486, 2, 2217},
|
|
{"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 1494, 9, 2219},
|
|
{"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 1498, 2, 2228},
|
|
{"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 1499, 2, 2230},
|
|
{"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1500, 2, 2232},
|
|
{"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1536, 2, 2234},
|
|
{"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1572, 2, 2236},
|
|
{"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1608, 2, 2238},
|
|
{"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1644, 2, 2240},
|
|
{"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1680, 2, 2242},
|
|
{"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1716, 2, 2244},
|
|
{"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1752, 2, 2246},
|
|
{"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1788, 2, 2248},
|
|
{"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1824, 2, 2250},
|
|
{"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1860, 2, 2252},
|
|
{"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 1861, 2, 2254},
|
|
{"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 1897, 2, 2256},
|
|
{"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 1933, 2, 2258},
|
|
{"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 1969, 2, 2260},
|
|
{"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2033, 2, 2262},
|
|
{"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 2034, 3, 2264},
|
|
{"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 2035, 3, 2267},
|
|
{"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 2036, 2, 2270},
|
|
{"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 2037, 2, 2272},
|
|
{"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2038, 4, 2274},
|
|
{"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2039, 5, 2278},
|
|
{"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 2040, 4, 2283},
|
|
{"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 2041, 5, 2287},
|
|
{"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 2042, 1, 2292},
|
|
{"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 2043, 4, 2293},
|
|
{"cvmx_pko_mem_debug14" , CVMX_CSR_DB_TYPE_RSL, 64, 2044, 2, 2297},
|
|
{"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2045, 5, 2299},
|
|
{"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2046, 5, 2304},
|
|
{"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 2047, 1, 2309},
|
|
{"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 2048, 19, 2310},
|
|
{"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 2049, 7, 2329},
|
|
{"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 2050, 4, 2336},
|
|
{"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 2051, 6, 2340},
|
|
{"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 2052, 7, 2346},
|
|
{"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 2053, 9, 2353},
|
|
{"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 2054, 5, 2362},
|
|
{"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2055, 13, 2367},
|
|
{"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2056, 4, 2380},
|
|
{"cvmx_pko_reg_crc_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 2057, 3, 2384},
|
|
{"cvmx_pko_reg_crc_enable" , CVMX_CSR_DB_TYPE_RSL, 64, 2059, 2, 2387},
|
|
{"cvmx_pko_reg_crc_iv#" , CVMX_CSR_DB_TYPE_RSL, 64, 2060, 2, 2389},
|
|
{"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2062, 2, 2391},
|
|
{"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2063, 3, 2393},
|
|
{"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2064, 5, 2396},
|
|
{"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2065, 3, 2401},
|
|
{"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2066, 3, 2404},
|
|
{"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2067, 2, 2407},
|
|
{"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2068, 3, 2409},
|
|
{"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 2069, 13, 2412},
|
|
{"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2070, 2, 2425},
|
|
{"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 2071, 13, 2427},
|
|
{"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 2072, 3, 2440},
|
|
{"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2073, 2, 2443},
|
|
{"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2081, 2, 2445},
|
|
{"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2082, 2, 2447},
|
|
{"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 2083, 2, 2449},
|
|
{"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 2084, 2, 2451},
|
|
{"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 2100, 5, 2453},
|
|
{"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2108, 8, 2458},
|
|
{"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2116, 2, 2466},
|
|
{"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2117, 2, 2468},
|
|
{"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2118, 2, 2470},
|
|
{"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 2126, 3, 2472},
|
|
{"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2127, 4, 2475},
|
|
{"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2143, 5, 2479},
|
|
{"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2144, 7, 2484},
|
|
{"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2160, 2, 2491},
|
|
{"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2176, 3, 2493},
|
|
{"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2177, 5, 2496},
|
|
{"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 2178, 8, 2501},
|
|
{"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2179, 6, 2509},
|
|
{"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2180, 2, 2515},
|
|
{"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2181, 4, 2517},
|
|
{"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2182, 4, 2521},
|
|
{"cvmx_spx#_bckprs_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2183, 2, 2525},
|
|
{"cvmx_spx#_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2185, 4, 2527},
|
|
{"cvmx_spx#_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2187, 11, 2531},
|
|
{"cvmx_spx#_clk_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2189, 9, 2542},
|
|
{"cvmx_spx#_dbg_deskew_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2191, 16, 2551},
|
|
{"cvmx_spx#_dbg_deskew_state" , CVMX_CSR_DB_TYPE_RSL, 64, 2193, 5, 2567},
|
|
{"cvmx_spx#_drv_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2195, 4, 2572},
|
|
{"cvmx_spx#_err_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2197, 6, 2576},
|
|
{"cvmx_spx#_int_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2199, 6, 2582},
|
|
{"cvmx_spx#_int_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2201, 12, 2588},
|
|
{"cvmx_spx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2203, 14, 2600},
|
|
{"cvmx_spx#_int_sync" , CVMX_CSR_DB_TYPE_RSL, 64, 2205, 12, 2614},
|
|
{"cvmx_spx#_tpa_acc" , CVMX_CSR_DB_TYPE_RSL, 64, 2207, 2, 2626},
|
|
{"cvmx_spx#_tpa_max" , CVMX_CSR_DB_TYPE_RSL, 64, 2209, 2, 2628},
|
|
{"cvmx_spx#_tpa_sel" , CVMX_CSR_DB_TYPE_RSL, 64, 2211, 2, 2630},
|
|
{"cvmx_spx#_trn4_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2213, 8, 2632},
|
|
{"cvmx_spx0_pll_bw_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2215, 2, 2640},
|
|
{"cvmx_spx0_pll_setting" , CVMX_CSR_DB_TYPE_RSL, 64, 2216, 2, 2642},
|
|
{"cvmx_srx#_com_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2217, 5, 2644},
|
|
{"cvmx_srx#_ign_rx_full" , CVMX_CSR_DB_TYPE_RSL, 64, 2219, 2, 2649},
|
|
{"cvmx_srx#_spi4_cal#" , CVMX_CSR_DB_TYPE_RSL, 64, 2221, 6, 2651},
|
|
{"cvmx_srx#_spi4_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2285, 4, 2657},
|
|
{"cvmx_srx#_sw_tick_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2287, 6, 2661},
|
|
{"cvmx_srx#_sw_tick_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2289, 1, 2667},
|
|
{"cvmx_stx#_arb_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2291, 5, 2668},
|
|
{"cvmx_stx#_bckprs_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2293, 2, 2673},
|
|
{"cvmx_stx#_com_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2295, 4, 2675},
|
|
{"cvmx_stx#_dip_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2297, 3, 2679},
|
|
{"cvmx_stx#_ign_cal" , CVMX_CSR_DB_TYPE_RSL, 64, 2299, 2, 2682},
|
|
{"cvmx_stx#_int_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2301, 9, 2684},
|
|
{"cvmx_stx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2303, 10, 2693},
|
|
{"cvmx_stx#_int_sync" , CVMX_CSR_DB_TYPE_RSL, 64, 2305, 9, 2703},
|
|
{"cvmx_stx#_min_bst" , CVMX_CSR_DB_TYPE_RSL, 64, 2307, 2, 2712},
|
|
{"cvmx_stx#_spi4_cal#" , CVMX_CSR_DB_TYPE_RSL, 64, 2309, 6, 2714},
|
|
{"cvmx_stx#_spi4_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2373, 3, 2720},
|
|
{"cvmx_stx#_spi4_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2375, 4, 2723},
|
|
{"cvmx_stx#_stat_bytes_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 2377, 2, 2727},
|
|
{"cvmx_stx#_stat_bytes_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 2379, 2, 2729},
|
|
{"cvmx_stx#_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2381, 3, 2731},
|
|
{"cvmx_stx#_stat_pkt_xmt" , CVMX_CSR_DB_TYPE_RSL, 64, 2383, 2, 2734},
|
|
{"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2385, 6, 2736},
|
|
{"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2386, 3, 2742},
|
|
{"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2387, 5, 2745},
|
|
{"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 2388, 4, 2750},
|
|
{"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 2389, 6, 2754},
|
|
{"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2390, 4, 2760},
|
|
{"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2391, 2, 2764},
|
|
{"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2392, 4, 2766},
|
|
{"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2393, 2, 2770},
|
|
{"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2394, 3, 2772},
|
|
{"cvmx_tra_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2395, 4, 2775},
|
|
{"cvmx_tra_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2396, 12, 2779},
|
|
{"cvmx_tra_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 2397, 3, 2791},
|
|
{"cvmx_tra_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2398, 2, 2794},
|
|
{"cvmx_tra_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2399, 2, 2796},
|
|
{"cvmx_tra_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2400, 17, 2798},
|
|
{"cvmx_tra_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2401, 12, 2815},
|
|
{"cvmx_tra_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2402, 6, 2827},
|
|
{"cvmx_tra_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2403, 5, 2833},
|
|
{"cvmx_tra_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2404, 1, 2838},
|
|
{"cvmx_tra_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2405, 2, 2839},
|
|
{"cvmx_tra_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2406, 2, 2841},
|
|
{"cvmx_tra_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2407, 17, 2843},
|
|
{"cvmx_tra_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2408, 12, 2860},
|
|
{"cvmx_tra_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2409, 6, 2872},
|
|
{"cvmx_tra_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2410, 2, 2878},
|
|
{"cvmx_tra_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2411, 2, 2880},
|
|
{"cvmx_tra_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2412, 17, 2882},
|
|
{"cvmx_tra_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2413, 12, 2899},
|
|
{"cvmx_tra_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2414, 6, 2911},
|
|
{"cvmx_zip_cmd_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2415, 3, 2917},
|
|
{"cvmx_zip_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2416, 5, 2920},
|
|
{"cvmx_zip_cmd_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2417, 3, 2925},
|
|
{"cvmx_zip_constants" , CVMX_CSR_DB_TYPE_RSL, 64, 2418, 6, 2928},
|
|
{"cvmx_zip_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2419, 2, 2934},
|
|
{"cvmx_zip_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2420, 2, 2936},
|
|
{"cvmx_zip_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2421, 2, 2938},
|
|
{NULL,0,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
|
|
/* name , --------------address, ---------------type, bits, csr offset */
|
|
{"ASX0_INT_EN" , 0x11800B0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
|
|
{"ASX1_INT_EN" , 0x11800B8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
|
|
{"ASX0_INT_REG" , 0x11800B0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
|
|
{"ASX1_INT_REG" , 0x11800B8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
|
|
{"ASX0_PRT_LOOP" , 0x11800B0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
|
|
{"ASX1_PRT_LOOP" , 0x11800B8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
|
|
{"ASX0_RLD_BYPASS" , 0x11800B0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
|
|
{"ASX1_RLD_BYPASS" , 0x11800B8000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
|
|
{"ASX0_RLD_BYPASS_SETTING" , 0x11800B0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
|
|
{"ASX1_RLD_BYPASS_SETTING" , 0x11800B8000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
|
|
{"ASX0_RLD_COMP" , 0x11800B0000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
|
|
{"ASX1_RLD_COMP" , 0x11800B8000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
|
|
{"ASX0_RLD_DATA_DRV" , 0x11800B0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
|
|
{"ASX1_RLD_DATA_DRV" , 0x11800B8000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
|
|
{"ASX0_RLD_FCRAM_MODE" , 0x11800B0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
|
|
{"ASX1_RLD_FCRAM_MODE" , 0x11800B8000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
|
|
{"ASX0_RLD_NCTL_STRONG" , 0x11800B0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
|
|
{"ASX1_RLD_NCTL_STRONG" , 0x11800B8000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
|
|
{"ASX0_RLD_NCTL_WEAK" , 0x11800B0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
|
|
{"ASX1_RLD_NCTL_WEAK" , 0x11800B8000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
|
|
{"ASX0_RLD_PCTL_STRONG" , 0x11800B0000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
|
|
{"ASX1_RLD_PCTL_STRONG" , 0x11800B8000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
|
|
{"ASX0_RLD_PCTL_WEAK" , 0x11800B0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
|
|
{"ASX1_RLD_PCTL_WEAK" , 0x11800B8000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
|
|
{"ASX0_RLD_SETTING" , 0x11800B0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"ASX1_RLD_SETTING" , 0x11800B8000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"ASX0_RX_CLK_SET000" , 0x11800B0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"ASX0_RX_CLK_SET001" , 0x11800B0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"ASX0_RX_CLK_SET002" , 0x11800B0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"ASX0_RX_CLK_SET003" , 0x11800B0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"ASX1_RX_CLK_SET000" , 0x11800B8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"ASX1_RX_CLK_SET001" , 0x11800B8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"ASX1_RX_CLK_SET002" , 0x11800B8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"ASX1_RX_CLK_SET003" , 0x11800B8000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"ASX0_RX_PRT_EN" , 0x11800B0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"ASX1_RX_PRT_EN" , 0x11800B8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"ASX0_RX_WOL" , 0x11800B0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
|
|
{"ASX1_RX_WOL" , 0x11800B8000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
|
|
{"ASX0_RX_WOL_MSK" , 0x11800B0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"ASX1_RX_WOL_MSK" , 0x11800B8000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"ASX0_RX_WOL_POWOK" , 0x11800B0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
|
|
{"ASX1_RX_WOL_POWOK" , 0x11800B8000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
|
|
{"ASX0_RX_WOL_SIG" , 0x11800B0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
|
|
{"ASX1_RX_WOL_SIG" , 0x11800B8000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
|
|
{"ASX0_TX_CLK_SET000" , 0x11800B0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
|
|
{"ASX0_TX_CLK_SET001" , 0x11800B0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
|
|
{"ASX0_TX_CLK_SET002" , 0x11800B0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
|
|
{"ASX0_TX_CLK_SET003" , 0x11800B0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
|
|
{"ASX1_TX_CLK_SET000" , 0x11800B8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
|
|
{"ASX1_TX_CLK_SET001" , 0x11800B8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
|
|
{"ASX1_TX_CLK_SET002" , 0x11800B8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
|
|
{"ASX1_TX_CLK_SET003" , 0x11800B8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
|
|
{"ASX0_TX_COMP_BYP" , 0x11800B0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
|
|
{"ASX1_TX_COMP_BYP" , 0x11800B8000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
|
|
{"ASX0_TX_HI_WATER000" , 0x11800B0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
|
|
{"ASX0_TX_HI_WATER001" , 0x11800B0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
|
|
{"ASX0_TX_HI_WATER002" , 0x11800B0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
|
|
{"ASX0_TX_HI_WATER003" , 0x11800B0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
|
|
{"ASX1_TX_HI_WATER000" , 0x11800B8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
|
|
{"ASX1_TX_HI_WATER001" , 0x11800B8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
|
|
{"ASX1_TX_HI_WATER002" , 0x11800B8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
|
|
{"ASX1_TX_HI_WATER003" , 0x11800B8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
|
|
{"ASX0_TX_PRT_EN" , 0x11800B0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
|
|
{"ASX1_TX_PRT_EN" , 0x11800B8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
|
|
{"ASX0_DBG_DATA_DRV" , 0x11800B0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
|
|
{"ASX0_DBG_DATA_ENABLE" , 0x11800B0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
|
|
{"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT4_EN0" , 0x1070000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT5_EN0" , 0x1070000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT6_EN0" , 0x1070000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT7_EN0" , 0x1070000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT8_EN0" , 0x1070000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT9_EN0" , 0x1070000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT10_EN0" , 0x10700000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT11_EN0" , 0x10700000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT12_EN0" , 0x10700000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT13_EN0" , 0x10700000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT14_EN0" , 0x10700000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT15_EN0" , 0x10700000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT16_EN0" , 0x1070000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT17_EN0" , 0x1070000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT18_EN0" , 0x1070000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT19_EN0" , 0x1070000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT20_EN0" , 0x1070000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT21_EN0" , 0x1070000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT22_EN0" , 0x1070000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT23_EN0" , 0x1070000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT24_EN0" , 0x1070000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT25_EN0" , 0x1070000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT26_EN0" , 0x10700000003A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT27_EN0" , 0x10700000003B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT28_EN0" , 0x10700000003C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT29_EN0" , 0x10700000003D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT30_EN0" , 0x10700000003E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT31_EN0" , 0x10700000003F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT4_EN1" , 0x1070000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT5_EN1" , 0x1070000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT6_EN1" , 0x1070000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT7_EN1" , 0x1070000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT8_EN1" , 0x1070000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT9_EN1" , 0x1070000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT10_EN1" , 0x10700000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT11_EN1" , 0x10700000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT12_EN1" , 0x10700000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT13_EN1" , 0x10700000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT14_EN1" , 0x10700000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT15_EN1" , 0x10700000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT16_EN1" , 0x1070000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT17_EN1" , 0x1070000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT18_EN1" , 0x1070000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT19_EN1" , 0x1070000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT20_EN1" , 0x1070000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT21_EN1" , 0x1070000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT22_EN1" , 0x1070000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT23_EN1" , 0x1070000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT24_EN1" , 0x1070000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT25_EN1" , 0x1070000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT26_EN1" , 0x10700000003A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT27_EN1" , 0x10700000003B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT28_EN1" , 0x10700000003C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT29_EN1" , 0x10700000003D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT30_EN1" , 0x10700000003E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT31_EN1" , 0x10700000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT4_SUM0" , 0x1070000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT5_SUM0" , 0x1070000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT6_SUM0" , 0x1070000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT7_SUM0" , 0x1070000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT8_SUM0" , 0x1070000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT9_SUM0" , 0x1070000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT10_SUM0" , 0x1070000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT11_SUM0" , 0x1070000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT12_SUM0" , 0x1070000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT13_SUM0" , 0x1070000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT14_SUM0" , 0x1070000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT15_SUM0" , 0x1070000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT16_SUM0" , 0x1070000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT17_SUM0" , 0x1070000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT18_SUM0" , 0x1070000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT19_SUM0" , 0x1070000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT20_SUM0" , 0x10700000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT21_SUM0" , 0x10700000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT22_SUM0" , 0x10700000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT23_SUM0" , 0x10700000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT24_SUM0" , 0x10700000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT25_SUM0" , 0x10700000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT26_SUM0" , 0x10700000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT27_SUM0" , 0x10700000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT28_SUM0" , 0x10700000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT29_SUM0" , 0x10700000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT30_SUM0" , 0x10700000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT31_SUM0" , 0x10700000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR2" , 0x1070000000690ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR3" , 0x1070000000698ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR4" , 0x10700000006A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR5" , 0x10700000006A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR6" , 0x10700000006B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR7" , 0x10700000006B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR8" , 0x10700000006C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR9" , 0x10700000006C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR10" , 0x10700000006D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR11" , 0x10700000006D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR12" , 0x10700000006E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR13" , 0x10700000006E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR14" , 0x10700000006F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_CLR15" , 0x10700000006F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET2" , 0x1070000000610ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET3" , 0x1070000000618ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET4" , 0x1070000000620ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET5" , 0x1070000000628ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET6" , 0x1070000000630ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET7" , 0x1070000000638ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET8" , 0x1070000000640ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET9" , 0x1070000000648ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET10" , 0x1070000000650ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET11" , 0x1070000000658ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET12" , 0x1070000000660ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET13" , 0x1070000000668ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET14" , 0x1070000000670ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_MBOX_SET15" , 0x1070000000678ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
|
|
{"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
|
|
{"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE2" , 0x1070000000590ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE3" , 0x1070000000598ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE4" , 0x10700000005A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE5" , 0x10700000005A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE6" , 0x10700000005B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE7" , 0x10700000005B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE8" , 0x10700000005C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE9" , 0x10700000005C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE10" , 0x10700000005D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE11" , 0x10700000005D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE12" , 0x10700000005E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE13" , 0x10700000005E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE14" , 0x10700000005F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_POKE15" , 0x10700000005F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
|
|
{"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
|
|
{"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 41},
|
|
{"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
|
|
{"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
|
|
{"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
|
|
{"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
|
|
{"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
|
|
{"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG2" , 0x1070000000510ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG3" , 0x1070000000518ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG4" , 0x1070000000520ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG5" , 0x1070000000528ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG6" , 0x1070000000530ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG7" , 0x1070000000538ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG8" , 0x1070000000540ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG9" , 0x1070000000548ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG10" , 0x1070000000550ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG11" , 0x1070000000558ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG12" , 0x1070000000560ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG13" , 0x1070000000568ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG14" , 0x1070000000570ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_WDOG15" , 0x1070000000578ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"DBG_DATA" , 0x11F00000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 45},
|
|
{"DFA_BST0" , 0x11800300007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
|
|
{"DFA_BST1" , 0x11800300007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
|
|
{"DFA_CFG" , 0x1180030000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
|
|
{"DFA_DBELL" , 0x1370000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 49},
|
|
{"DFA_DIFCTL" , 0x1370600000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
|
|
{"DFA_DIFRDPTR" , 0x1370200000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 51},
|
|
{"DFA_ERR" , 0x1180030000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
|
|
{"DFA_MEMCFG0" , 0x1180030000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
|
|
{"DFA_MEMCFG1" , 0x1180030000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
|
|
{"DFA_MEMCFG2" , 0x1180030000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
|
|
{"DFA_MEMFADR" , 0x1180030000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
|
|
{"DFA_MEMFCR" , 0x1180030000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
|
|
{"DFA_MEMRLD" , 0x1180030000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
|
|
{"DFA_NCBCTL" , 0x1180030000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
|
|
{"DFA_SBD_DBG0" , 0x1180030000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
|
|
{"DFA_SBD_DBG1" , 0x1180030000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
|
|
{"DFA_SBD_DBG2" , 0x1180030000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
|
|
{"DFA_SBD_DBG3" , 0x1180030000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
|
|
{"FPA_BIST_STATUS" , 0x11800280000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
|
|
{"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
|
|
{"FPA_FPF1_MARKS" , 0x1180028000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"FPA_FPF2_MARKS" , 0x1180028000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"FPA_FPF3_MARKS" , 0x1180028000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"FPA_FPF4_MARKS" , 0x1180028000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"FPA_FPF5_MARKS" , 0x1180028000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"FPA_FPF6_MARKS" , 0x1180028000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"FPA_FPF7_MARKS" , 0x1180028000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"FPA_FPF1_SIZE" , 0x1180028000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"FPA_FPF2_SIZE" , 0x1180028000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"FPA_FPF3_SIZE" , 0x1180028000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"FPA_FPF4_SIZE" , 0x1180028000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"FPA_FPF5_SIZE" , 0x1180028000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"FPA_FPF6_SIZE" , 0x1180028000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"FPA_FPF7_SIZE" , 0x1180028000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"FPA_FPF0_MARKS" , 0x1180028000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
|
|
{"FPA_FPF0_SIZE" , 0x1180028000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
|
|
{"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
|
|
{"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
|
|
{"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_QUE1_AVAILABLE" , 0x11800280000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_QUE2_AVAILABLE" , 0x11800280000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_QUE3_AVAILABLE" , 0x11800280000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_QUE4_AVAILABLE" , 0x11800280000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_QUE5_AVAILABLE" , 0x11800280000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_QUE6_AVAILABLE" , 0x11800280000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_QUE7_AVAILABLE" , 0x11800280000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_QUE0_PAGE_INDEX" , 0x11800280000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"FPA_QUE1_PAGE_INDEX" , 0x11800280000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
|
|
{"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
|
|
{"FPA_WART_CTL" , 0x11800280000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
|
|
{"FPA_WART_STATUS" , 0x11800280000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
|
|
{"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
|
|
{"GMX1_BAD_REG" , 0x1180010000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
|
|
{"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
|
|
{"GMX1_BIST" , 0x1180010000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
|
|
{"GMX0_INF_MODE" , 0x11800080007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
|
|
{"GMX1_INF_MODE" , 0x11800100007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
|
|
{"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
|
|
{"GMX1_NXA_ADR" , 0x1180010000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
|
|
{"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX0_PRT003_CFG" , 0x1180008001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX1_PRT000_CFG" , 0x1180010000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX1_PRT001_CFG" , 0x1180010000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX1_PRT002_CFG" , 0x1180010001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX1_PRT003_CFG" , 0x1180010001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX0_RX003_ADR_CAM0" , 0x1180008001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX1_RX000_ADR_CAM0" , 0x1180010000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX1_RX001_ADR_CAM0" , 0x1180010000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX1_RX002_ADR_CAM0" , 0x1180010001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX1_RX003_ADR_CAM0" , 0x1180010001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX0_RX003_ADR_CAM1" , 0x1180008001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX1_RX000_ADR_CAM1" , 0x1180010000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX1_RX001_ADR_CAM1" , 0x1180010000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX1_RX002_ADR_CAM1" , 0x1180010001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX1_RX003_ADR_CAM1" , 0x1180010001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX0_RX003_ADR_CAM2" , 0x1180008001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX1_RX000_ADR_CAM2" , 0x1180010000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX1_RX001_ADR_CAM2" , 0x1180010000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX1_RX002_ADR_CAM2" , 0x1180010001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX1_RX003_ADR_CAM2" , 0x1180010001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX0_RX003_ADR_CAM3" , 0x1180008001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX1_RX000_ADR_CAM3" , 0x1180010000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX1_RX001_ADR_CAM3" , 0x1180010000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX1_RX002_ADR_CAM3" , 0x1180010001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX1_RX003_ADR_CAM3" , 0x1180010001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX0_RX000_ADR_CAM4" , 0x11800080001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX0_RX001_ADR_CAM4" , 0x11800080009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX0_RX002_ADR_CAM4" , 0x11800080011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX0_RX003_ADR_CAM4" , 0x11800080019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX1_RX000_ADR_CAM4" , 0x11800100001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX1_RX001_ADR_CAM4" , 0x11800100009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX1_RX002_ADR_CAM4" , 0x11800100011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX1_RX003_ADR_CAM4" , 0x11800100019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX0_RX000_ADR_CAM5" , 0x11800080001A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX0_RX001_ADR_CAM5" , 0x11800080009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX0_RX002_ADR_CAM5" , 0x11800080011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX0_RX003_ADR_CAM5" , 0x11800080019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX1_RX000_ADR_CAM5" , 0x11800100001A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX1_RX001_ADR_CAM5" , 0x11800100009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX1_RX002_ADR_CAM5" , 0x11800100011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX1_RX003_ADR_CAM5" , 0x11800100019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_RX003_ADR_CAM_EN" , 0x1180008001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX1_RX000_ADR_CAM_EN" , 0x1180010000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX1_RX001_ADR_CAM_EN" , 0x1180010000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX1_RX002_ADR_CAM_EN" , 0x1180010001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX1_RX003_ADR_CAM_EN" , 0x1180010001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_RX003_ADR_CTL" , 0x1180008001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX1_RX000_ADR_CTL" , 0x1180010000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX1_RX001_ADR_CTL" , 0x1180010000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX1_RX002_ADR_CTL" , 0x1180010001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX1_RX003_ADR_CTL" , 0x1180010001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_RX003_DECISION" , 0x1180008001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX1_RX000_DECISION" , 0x1180010000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX1_RX001_DECISION" , 0x1180010000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX1_RX002_DECISION" , 0x1180010001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX1_RX003_DECISION" , 0x1180010001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_RX003_FRM_CHK" , 0x1180008001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX1_RX000_FRM_CHK" , 0x1180010000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX1_RX001_FRM_CHK" , 0x1180010000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX1_RX002_FRM_CHK" , 0x1180010001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX1_RX003_FRM_CHK" , 0x1180010001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_RX003_FRM_CTL" , 0x1180008001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX1_RX000_FRM_CTL" , 0x1180010000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX1_RX001_FRM_CTL" , 0x1180010000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX1_RX002_FRM_CTL" , 0x1180010001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX1_RX003_FRM_CTL" , 0x1180010001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_RX000_FRM_MAX" , 0x1180008000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_RX001_FRM_MAX" , 0x1180008000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_RX002_FRM_MAX" , 0x1180008001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_RX003_FRM_MAX" , 0x1180008001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX1_RX000_FRM_MAX" , 0x1180010000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX1_RX001_FRM_MAX" , 0x1180010000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX1_RX002_FRM_MAX" , 0x1180010001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX1_RX003_FRM_MAX" , 0x1180010001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_RX000_FRM_MIN" , 0x1180008000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_RX001_FRM_MIN" , 0x1180008000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_RX002_FRM_MIN" , 0x1180008001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_RX003_FRM_MIN" , 0x1180008001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX1_RX000_FRM_MIN" , 0x1180010000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX1_RX001_FRM_MIN" , 0x1180010000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX1_RX002_FRM_MIN" , 0x1180010001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX1_RX003_FRM_MIN" , 0x1180010001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_RX003_IFG" , 0x1180008001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX1_RX000_IFG" , 0x1180010000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX1_RX001_IFG" , 0x1180010000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX1_RX002_IFG" , 0x1180010001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX1_RX003_IFG" , 0x1180010001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_RX003_INT_EN" , 0x1180008001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX1_RX000_INT_EN" , 0x1180010000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX1_RX001_INT_EN" , 0x1180010000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX1_RX002_INT_EN" , 0x1180010001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX1_RX003_INT_EN" , 0x1180010001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_RX003_INT_REG" , 0x1180008001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX1_RX000_INT_REG" , 0x1180010000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX1_RX001_INT_REG" , 0x1180010000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX1_RX002_INT_REG" , 0x1180010001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX1_RX003_INT_REG" , 0x1180010001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_RX003_JABBER" , 0x1180008001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX1_RX000_JABBER" , 0x1180010000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX1_RX001_JABBER" , 0x1180010000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX1_RX002_JABBER" , 0x1180010001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX1_RX003_JABBER" , 0x1180010001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_RX000_RX_INBND" , 0x1180008000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_RX001_RX_INBND" , 0x1180008000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_RX002_RX_INBND" , 0x1180008001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_RX003_RX_INBND" , 0x1180008001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX1_RX000_RX_INBND" , 0x1180010000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX1_RX001_RX_INBND" , 0x1180010000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX1_RX002_RX_INBND" , 0x1180010001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX1_RX003_RX_INBND" , 0x1180010001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX0_RX003_STATS_CTL" , 0x1180008001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX1_RX000_STATS_CTL" , 0x1180010000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX1_RX001_STATS_CTL" , 0x1180010000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX1_RX002_STATS_CTL" , 0x1180010001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX1_RX003_STATS_CTL" , 0x1180010001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX0_RX003_STATS_OCTS" , 0x1180008001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX1_RX000_STATS_OCTS" , 0x1180010000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX1_RX001_STATS_OCTS" , 0x1180010000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX1_RX002_STATS_OCTS" , 0x1180010001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX1_RX003_STATS_OCTS" , 0x1180010001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX0_RX003_STATS_OCTS_CTL" , 0x1180008001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX1_RX000_STATS_OCTS_CTL" , 0x1180010000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX1_RX001_STATS_OCTS_CTL" , 0x1180010000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX1_RX002_STATS_OCTS_CTL" , 0x1180010001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX1_RX003_STATS_OCTS_CTL" , 0x1180010001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_RX003_STATS_OCTS_DMAC" , 0x11800080018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX1_RX000_STATS_OCTS_DMAC" , 0x11800100000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX1_RX001_STATS_OCTS_DMAC" , 0x11800100008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX1_RX002_STATS_OCTS_DMAC" , 0x11800100010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX1_RX003_STATS_OCTS_DMAC" , 0x11800100018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX0_RX003_STATS_OCTS_DRP" , 0x11800080018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX1_RX000_STATS_OCTS_DRP" , 0x11800100000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX1_RX001_STATS_OCTS_DRP" , 0x11800100008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX1_RX002_STATS_OCTS_DRP" , 0x11800100010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX1_RX003_STATS_OCTS_DRP" , 0x11800100018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_RX003_STATS_PKTS" , 0x1180008001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX1_RX000_STATS_PKTS" , 0x1180010000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX1_RX001_STATS_PKTS" , 0x1180010000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX1_RX002_STATS_PKTS" , 0x1180010001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX1_RX003_STATS_PKTS" , 0x1180010001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_RX003_STATS_PKTS_BAD" , 0x11800080018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX1_RX000_STATS_PKTS_BAD" , 0x11800100000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX1_RX001_STATS_PKTS_BAD" , 0x11800100008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX1_RX002_STATS_PKTS_BAD" , 0x11800100010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX1_RX003_STATS_PKTS_BAD" , 0x11800100018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX0_RX003_STATS_PKTS_CTL" , 0x1180008001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX1_RX000_STATS_PKTS_CTL" , 0x1180010000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX1_RX001_STATS_PKTS_CTL" , 0x1180010000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX1_RX002_STATS_PKTS_CTL" , 0x1180010001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX1_RX003_STATS_PKTS_CTL" , 0x1180010001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_RX003_STATS_PKTS_DMAC" , 0x11800080018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX1_RX000_STATS_PKTS_DMAC" , 0x11800100000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX1_RX001_STATS_PKTS_DMAC" , 0x11800100008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX1_RX002_STATS_PKTS_DMAC" , 0x11800100010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX1_RX003_STATS_PKTS_DMAC" , 0x11800100018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX0_RX003_STATS_PKTS_DRP" , 0x11800080018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX1_RX000_STATS_PKTS_DRP" , 0x11800100000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX1_RX001_STATS_PKTS_DRP" , 0x11800100008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX1_RX002_STATS_PKTS_DRP" , 0x11800100010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX1_RX003_STATS_PKTS_DRP" , 0x11800100018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX0_RX003_UDD_SKP" , 0x1180008001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX1_RX000_UDD_SKP" , 0x1180010000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX1_RX001_UDD_SKP" , 0x1180010000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX1_RX002_UDD_SKP" , 0x1180010001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX1_RX003_UDD_SKP" , 0x1180010001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX0_RX_BP_DROP003" , 0x1180008000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX1_RX_BP_DROP000" , 0x1180010000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX1_RX_BP_DROP001" , 0x1180010000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX1_RX_BP_DROP002" , 0x1180010000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX1_RX_BP_DROP003" , 0x1180010000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX0_RX_BP_OFF003" , 0x1180008000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX1_RX_BP_OFF000" , 0x1180010000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX1_RX_BP_OFF001" , 0x1180010000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX1_RX_BP_OFF002" , 0x1180010000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX1_RX_BP_OFF003" , 0x1180010000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_RX_BP_ON003" , 0x1180008000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX1_RX_BP_ON000" , 0x1180010000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX1_RX_BP_ON001" , 0x1180010000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX1_RX_BP_ON002" , 0x1180010000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX1_RX_BP_ON003" , 0x1180010000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_RX_PASS_EN" , 0x11800080005F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX1_RX_PASS_EN" , 0x11800100005F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX0_RX_PASS_MAP000" , 0x1180008000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP001" , 0x1180008000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP002" , 0x1180008000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP003" , 0x1180008000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP004" , 0x1180008000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP005" , 0x1180008000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP006" , 0x1180008000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP007" , 0x1180008000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP008" , 0x1180008000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP009" , 0x1180008000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP010" , 0x1180008000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP011" , 0x1180008000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP012" , 0x1180008000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP013" , 0x1180008000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP014" , 0x1180008000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP015" , 0x1180008000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP000" , 0x1180010000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP001" , 0x1180010000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP002" , 0x1180010000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP003" , 0x1180010000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP004" , 0x1180010000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP005" , 0x1180010000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP006" , 0x1180010000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP007" , 0x1180010000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP008" , 0x1180010000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP009" , 0x1180010000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP010" , 0x1180010000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP011" , 0x1180010000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP012" , 0x1180010000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP013" , 0x1180010000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP014" , 0x1180010000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP015" , 0x1180010000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PRT_INFO" , 0x11800080004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX1_RX_PRT_INFO" , 0x11800100004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX1_RX_PRTS" , 0x1180010000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_SMAC001" , 0x1180008000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_SMAC003" , 0x1180008001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX1_SMAC000" , 0x1180010000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX1_SMAC001" , 0x1180010000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX1_SMAC002" , 0x1180010001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX1_SMAC003" , 0x1180010001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX1_STAT_BP" , 0x1180010000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_TX001_APPEND" , 0x1180008000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_TX003_APPEND" , 0x1180008001A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX1_TX000_APPEND" , 0x1180010000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX1_TX001_APPEND" , 0x1180010000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX1_TX002_APPEND" , 0x1180010001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX1_TX003_APPEND" , 0x1180010001A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_TX001_BURST" , 0x1180008000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_TX003_BURST" , 0x1180008001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX1_TX000_BURST" , 0x1180010000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX1_TX001_BURST" , 0x1180010000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX1_TX002_BURST" , 0x1180010001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX1_TX003_BURST" , 0x1180010001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_TX000_CLK" , 0x1180008000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_TX001_CLK" , 0x1180008000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_TX002_CLK" , 0x1180008001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_TX003_CLK" , 0x1180008001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX1_TX000_CLK" , 0x1180010000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX1_TX001_CLK" , 0x1180010000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX1_TX002_CLK" , 0x1180010001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX1_TX003_CLK" , 0x1180010001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_TX001_CTL" , 0x1180008000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_TX003_CTL" , 0x1180008001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_TX000_CTL" , 0x1180010000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_TX001_CTL" , 0x1180010000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_TX002_CTL" , 0x1180010001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_TX003_CTL" , 0x1180010001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_TX001_MIN_PKT" , 0x1180008000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_TX003_MIN_PKT" , 0x1180008001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX1_TX000_MIN_PKT" , 0x1180010000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX1_TX001_MIN_PKT" , 0x1180010000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX1_TX002_MIN_PKT" , 0x1180010001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX1_TX003_MIN_PKT" , 0x1180010001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_TX003_PAUSE_PKT_INTERVAL", 0x1180008001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX1_TX000_PAUSE_PKT_INTERVAL", 0x1180010000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX1_TX001_PAUSE_PKT_INTERVAL", 0x1180010000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX1_TX002_PAUSE_PKT_INTERVAL", 0x1180010001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX1_TX003_PAUSE_PKT_INTERVAL", 0x1180010001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_TX003_PAUSE_PKT_TIME" , 0x1180008001A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX1_TX000_PAUSE_PKT_TIME" , 0x1180010000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX1_TX001_PAUSE_PKT_TIME" , 0x1180010000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX1_TX002_PAUSE_PKT_TIME" , 0x1180010001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX1_TX003_PAUSE_PKT_TIME" , 0x1180010001A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_TX001_PAUSE_TOGO" , 0x1180008000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_TX003_PAUSE_TOGO" , 0x1180008001A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX1_TX000_PAUSE_TOGO" , 0x1180010000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX1_TX001_PAUSE_TOGO" , 0x1180010000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX1_TX002_PAUSE_TOGO" , 0x1180010001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX1_TX003_PAUSE_TOGO" , 0x1180010001A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_TX001_PAUSE_ZERO" , 0x1180008000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_TX003_PAUSE_ZERO" , 0x1180008001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX1_TX000_PAUSE_ZERO" , 0x1180010000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX1_TX001_PAUSE_ZERO" , 0x1180010000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX1_TX002_PAUSE_ZERO" , 0x1180010001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX1_TX003_PAUSE_ZERO" , 0x1180010001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_TX001_SLOT" , 0x1180008000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_TX003_SLOT" , 0x1180008001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX1_TX000_SLOT" , 0x1180010000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX1_TX001_SLOT" , 0x1180010000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX1_TX002_SLOT" , 0x1180010001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX1_TX003_SLOT" , 0x1180010001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_TX001_SOFT_PAUSE" , 0x1180008000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_TX003_SOFT_PAUSE" , 0x1180008001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX1_TX000_SOFT_PAUSE" , 0x1180010000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX1_TX001_SOFT_PAUSE" , 0x1180010000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX1_TX002_SOFT_PAUSE" , 0x1180010001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX1_TX003_SOFT_PAUSE" , 0x1180010001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_TX001_STAT0" , 0x1180008000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_TX003_STAT0" , 0x1180008001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX1_TX000_STAT0" , 0x1180010000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX1_TX001_STAT0" , 0x1180010000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX1_TX002_STAT0" , 0x1180010001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX1_TX003_STAT0" , 0x1180010001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_TX001_STAT1" , 0x1180008000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_TX003_STAT1" , 0x1180008001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX1_TX000_STAT1" , 0x1180010000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX1_TX001_STAT1" , 0x1180010000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX1_TX002_STAT1" , 0x1180010001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX1_TX003_STAT1" , 0x1180010001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_TX001_STAT2" , 0x1180008000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_TX003_STAT2" , 0x1180008001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX1_TX000_STAT2" , 0x1180010000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX1_TX001_STAT2" , 0x1180010000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX1_TX002_STAT2" , 0x1180010001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX1_TX003_STAT2" , 0x1180010001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_TX001_STAT3" , 0x1180008000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_TX003_STAT3" , 0x1180008001A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX1_TX000_STAT3" , 0x1180010000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX1_TX001_STAT3" , 0x1180010000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX1_TX002_STAT3" , 0x1180010001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX1_TX003_STAT3" , 0x1180010001A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_TX000_STAT4" , 0x11800080002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_TX001_STAT4" , 0x1180008000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_TX002_STAT4" , 0x11800080012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_TX003_STAT4" , 0x1180008001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX1_TX000_STAT4" , 0x11800100002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX1_TX001_STAT4" , 0x1180010000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX1_TX002_STAT4" , 0x11800100012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX1_TX003_STAT4" , 0x1180010001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_TX000_STAT5" , 0x11800080002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_TX001_STAT5" , 0x1180008000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_TX002_STAT5" , 0x11800080012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_TX003_STAT5" , 0x1180008001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX1_TX000_STAT5" , 0x11800100002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX1_TX001_STAT5" , 0x1180010000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX1_TX002_STAT5" , 0x11800100012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX1_TX003_STAT5" , 0x1180010001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_TX000_STAT6" , 0x11800080002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_TX001_STAT6" , 0x1180008000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_TX002_STAT6" , 0x11800080012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_TX003_STAT6" , 0x1180008001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX1_TX000_STAT6" , 0x11800100002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX1_TX001_STAT6" , 0x1180010000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX1_TX002_STAT6" , 0x11800100012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX1_TX003_STAT6" , 0x1180010001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_TX000_STAT7" , 0x11800080002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_TX001_STAT7" , 0x1180008000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_TX002_STAT7" , 0x11800080012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_TX003_STAT7" , 0x1180008001AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX1_TX000_STAT7" , 0x11800100002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX1_TX001_STAT7" , 0x1180010000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX1_TX002_STAT7" , 0x11800100012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX1_TX003_STAT7" , 0x1180010001AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_TX000_STAT8" , 0x11800080002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_TX001_STAT8" , 0x1180008000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_TX002_STAT8" , 0x11800080012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_TX003_STAT8" , 0x1180008001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX1_TX000_STAT8" , 0x11800100002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX1_TX001_STAT8" , 0x1180010000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX1_TX002_STAT8" , 0x11800100012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX1_TX003_STAT8" , 0x1180010001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_TX000_STAT9" , 0x11800080002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_TX001_STAT9" , 0x1180008000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_TX002_STAT9" , 0x11800080012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_TX003_STAT9" , 0x1180008001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX1_TX000_STAT9" , 0x11800100002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX1_TX001_STAT9" , 0x1180010000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX1_TX002_STAT9" , 0x11800100012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX1_TX003_STAT9" , 0x1180010001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_TX001_STATS_CTL" , 0x1180008000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_TX003_STATS_CTL" , 0x1180008001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX1_TX000_STATS_CTL" , 0x1180010000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX1_TX001_STATS_CTL" , 0x1180010000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX1_TX002_STATS_CTL" , 0x1180010001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX1_TX003_STATS_CTL" , 0x1180010001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_TX001_THRESH" , 0x1180008000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_TX003_THRESH" , 0x1180008001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX1_TX000_THRESH" , 0x1180010000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX1_TX001_THRESH" , 0x1180010000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX1_TX002_THRESH" , 0x1180010001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX1_TX003_THRESH" , 0x1180010001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_TX_BP" , 0x11800080004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX1_TX_BP" , 0x11800100004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX1_TX_COL_ATTEMPT" , 0x1180010000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX0_TX_CORRUPT" , 0x11800080004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX1_TX_CORRUPT" , 0x11800100004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX1_TX_IFG" , 0x1180010000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX1_TX_INT_EN" , 0x1180010000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX1_TX_INT_REG" , 0x1180010000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX1_TX_JAM" , 0x1180010000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX0_TX_LFSR" , 0x11800080004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX1_TX_LFSR" , 0x11800100004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX0_TX_OVR_BP" , 0x11800080004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX1_TX_OVR_BP" , 0x11800100004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX1_TX_PAUSE_PKT_DMAC" , 0x11800100004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX1_TX_PAUSE_PKT_TYPE" , 0x11800100004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX1_TX_PRTS" , 0x1180010000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX0_TX_SPI_CTL" , 0x11800080004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX1_TX_SPI_CTL" , 0x11800100004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX0_TX_SPI_DRAIN" , 0x11800080004E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX1_TX_SPI_DRAIN" , 0x11800100004E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX0_TX_SPI_MAX" , 0x11800080004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
|
|
{"GMX1_TX_SPI_MAX" , 0x11800100004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
|
|
{"GMX0_TX_SPI_THRESH" , 0x11800080004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_THRESH" , 0x11800100004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
|
|
{"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
|
|
{"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
|
|
{"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
|
|
{"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
|
|
{"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
|
|
{"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
|
|
{"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
|
|
{"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
|
|
{"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
|
|
{"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
|
|
{"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
|
|
{"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
|
|
{"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
|
|
{"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
|
|
{"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
|
|
{"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
|
|
{"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
|
|
{"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
|
|
{"IOB_BIST_STATUS" , 0x11800F00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"IOB_CTL_STATUS" , 0x11800F0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"IOB_DWB_PRI_CNT" , 0x11800F0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"IOB_FAU_TIMEOUT" , 0x11800F0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
|
|
{"IOB_I2C_PRI_CNT" , 0x11800F0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"IOB_INB_CONTROL_MATCH" , 0x11800F0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"IOB_INB_CONTROL_MATCH_ENB" , 0x11800F0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"IOB_INB_DATA_MATCH" , 0x11800F0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"IOB_INB_DATA_MATCH_ENB" , 0x11800F0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"IOB_INT_ENB" , 0x11800F0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"IOB_INT_SUM" , 0x11800F0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"IOB_N2C_L2C_PRI_CNT" , 0x11800F0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"IOB_N2C_RSP_PRI_CNT" , 0x11800F0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
|
|
{"IOB_OUTB_COM_PRI_CNT" , 0x11800F0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
|
|
{"IOB_OUTB_CONTROL_MATCH" , 0x11800F0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
|
|
{"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800F00000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
|
|
{"IOB_OUTB_DATA_MATCH" , 0x11800F0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
|
|
{"IOB_OUTB_DATA_MATCH_ENB" , 0x11800F00000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
|
|
{"IOB_OUTB_FPA_PRI_CNT" , 0x11800F0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
|
|
{"IOB_OUTB_REQ_PRI_CNT" , 0x11800F0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
|
|
{"IOB_P2C_REQ_PRI_CNT" , 0x11800F0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
|
|
{"IOB_PKT_ERR" , 0x11800F0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
|
|
{"IPD_1ST_MBUFF_SKIP" , 0x14F0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 187},
|
|
{"IPD_1ST_NEXT_PTR_BACK" , 0x14F0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
|
|
{"IPD_2ND_NEXT_PTR_BACK" , 0x14F0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
|
|
{"IPD_BIST_STATUS" , 0x14F00000007F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
|
|
{"IPD_BP_PRT_RED_END" , 0x14F0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"IPD_CLK_COUNT" , 0x14F0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
|
|
{"IPD_CTL_STATUS" , 0x14F0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 193},
|
|
{"IPD_INT_ENB" , 0x14F0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 194},
|
|
{"IPD_INT_SUM" , 0x14F0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 195},
|
|
{"IPD_NOT_1ST_MBUFF_SKIP" , 0x14F0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_PACKET_MBUFF_SIZE" , 0x14F0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PKT_PTR_VALID" , 0x14F0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 198},
|
|
{"IPD_PORT0_BP_PAGE_CNT" , 0x14F0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT1_BP_PAGE_CNT" , 0x14F0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT2_BP_PAGE_CNT" , 0x14F0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT3_BP_PAGE_CNT" , 0x14F0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT4_BP_PAGE_CNT" , 0x14F0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT5_BP_PAGE_CNT" , 0x14F0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT6_BP_PAGE_CNT" , 0x14F0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT7_BP_PAGE_CNT" , 0x14F0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT8_BP_PAGE_CNT" , 0x14F0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT9_BP_PAGE_CNT" , 0x14F0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT10_BP_PAGE_CNT" , 0x14F0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT11_BP_PAGE_CNT" , 0x14F0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT12_BP_PAGE_CNT" , 0x14F0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT13_BP_PAGE_CNT" , 0x14F0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT14_BP_PAGE_CNT" , 0x14F0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT15_BP_PAGE_CNT" , 0x14F00000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT16_BP_PAGE_CNT" , 0x14F00000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT17_BP_PAGE_CNT" , 0x14F00000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT18_BP_PAGE_CNT" , 0x14F00000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT19_BP_PAGE_CNT" , 0x14F00000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT20_BP_PAGE_CNT" , 0x14F00000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT21_BP_PAGE_CNT" , 0x14F00000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT22_BP_PAGE_CNT" , 0x14F00000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT23_BP_PAGE_CNT" , 0x14F00000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT24_BP_PAGE_CNT" , 0x14F00000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT25_BP_PAGE_CNT" , 0x14F00000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT26_BP_PAGE_CNT" , 0x14F00000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT27_BP_PAGE_CNT" , 0x14F0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT28_BP_PAGE_CNT" , 0x14F0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT29_BP_PAGE_CNT" , 0x14F0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT30_BP_PAGE_CNT" , 0x14F0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT31_BP_PAGE_CNT" , 0x14F0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT32_BP_PAGE_CNT" , 0x14F0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT33_BP_PAGE_CNT" , 0x14F0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT34_BP_PAGE_CNT" , 0x14F0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT35_BP_PAGE_CNT" , 0x14F0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14F00000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14F00000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14F00000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR3" , 0x14F00000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR4" , 0x14F00000001D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR5" , 0x14F00000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR6" , 0x14F00000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR7" , 0x14F00000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR8" , 0x14F00000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR9" , 0x14F0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR10" , 0x14F0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR11" , 0x14F0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR12" , 0x14F0000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR13" , 0x14F0000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR14" , 0x14F0000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR15" , 0x14F0000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR16" , 0x14F0000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR17" , 0x14F0000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR18" , 0x14F0000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR19" , 0x14F0000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR20" , 0x14F0000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR21" , 0x14F0000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR22" , 0x14F0000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR23" , 0x14F0000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR24" , 0x14F0000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR25" , 0x14F0000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR26" , 0x14F0000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR27" , 0x14F0000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR28" , 0x14F0000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR29" , 0x14F00000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR30" , 0x14F00000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR31" , 0x14F00000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14F00000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR33" , 0x14F00000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR34" , 0x14F00000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR35" , 0x14F00000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14F0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14F0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"IPD_PTR_COUNT" , 0x14F0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
|
|
{"IPD_PWP_PTR_FIFO_CTL" , 0x14F0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
|
|
{"IPD_QOS0_RED_MARKS" , 0x14F0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
|
|
{"IPD_QOS1_RED_MARKS" , 0x14F0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
|
|
{"IPD_QOS2_RED_MARKS" , 0x14F0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
|
|
{"IPD_QOS3_RED_MARKS" , 0x14F0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
|
|
{"IPD_QOS4_RED_MARKS" , 0x14F0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
|
|
{"IPD_QOS5_RED_MARKS" , 0x14F00000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
|
|
{"IPD_QOS6_RED_MARKS" , 0x14F00000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
|
|
{"IPD_QOS7_RED_MARKS" , 0x14F00000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
|
|
{"IPD_QUE0_FREE_PAGE_CNT" , 0x14F0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"IPD_RED_PORT_ENABLE" , 0x14F00000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
|
|
{"IPD_RED_QUE0_PARAM" , 0x14F00000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_RED_QUE1_PARAM" , 0x14F00000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_RED_QUE2_PARAM" , 0x14F00000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_RED_QUE3_PARAM" , 0x14F00000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_RED_QUE4_PARAM" , 0x14F0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_RED_QUE5_PARAM" , 0x14F0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_RED_QUE6_PARAM" , 0x14F0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_RED_QUE7_PARAM" , 0x14F0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14F0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_SUB_PORT_FCS" , 0x14F0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
|
|
{"IPD_WQE_FPA_QUEUE" , 0x14F0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
|
|
{"IPD_WQE_PTR_VALID" , 0x14F0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
|
|
{"KEY_BIST_REG" , 0x1180020000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
|
|
{"KEY_CTL_STATUS" , 0x1180020000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
|
|
{"KEY_INT_ENB" , 0x1180020000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
|
|
{"KEY_INT_SUM" , 0x1180020000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
|
|
{"L2C_BST0" , 0x11800800007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
|
|
{"L2C_BST1" , 0x11800800007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
|
|
{"L2C_BST2" , 0x11800800007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
|
|
{"L2C_CFG" , 0x1180080000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
|
|
{"L2C_DBG" , 0x1180080000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
|
|
{"L2C_DUT" , 0x1180080000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
|
|
{"L2C_LCKBASE" , 0x1180080000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
|
|
{"L2C_LCKOFF" , 0x1180080000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
|
|
{"L2C_LFB0" , 0x1180080000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
|
|
{"L2C_LFB1" , 0x1180080000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
|
|
{"L2C_LFB2" , 0x1180080000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
|
|
{"L2C_LFB3" , 0x11800800000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
|
|
{"L2C_PFC0" , 0x1180080000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
|
|
{"L2C_PFC1" , 0x11800800000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
|
|
{"L2C_PFC2" , 0x11800800000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
|
|
{"L2C_PFC3" , 0x11800800000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
|
|
{"L2C_PFCTL" , 0x1180080000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
|
|
{"L2C_SPAR0" , 0x1180080000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
|
|
{"L2C_SPAR1" , 0x1180080000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
|
|
{"L2C_SPAR2" , 0x1180080000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
|
|
{"L2C_SPAR3" , 0x1180080000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
|
|
{"L2C_SPAR4" , 0x1180080000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
|
|
{"L2D_BST0" , 0x1180080000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
|
|
{"L2D_BST1" , 0x1180080000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
|
|
{"L2D_BST2" , 0x1180080000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
|
|
{"L2D_BST3" , 0x1180080000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
|
|
{"L2D_ERR" , 0x1180080000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
|
|
{"L2D_FADR" , 0x1180080000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
|
|
{"L2D_FSYN0" , 0x1180080000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
|
|
{"L2D_FSYN1" , 0x1180080000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
|
|
{"L2D_FUS0" , 0x11800800007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
|
|
{"L2D_FUS1" , 0x11800800007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
|
|
{"L2D_FUS2" , 0x11800800007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
|
|
{"L2D_FUS3" , 0x11800800007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
|
|
{"L2T_ERR" , 0x1180080000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
|
|
{"LED_BLINK" , 0x1180000001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
|
|
{"LED_CLK_PHASE" , 0x1180000001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
|
|
{"LED_CYLON" , 0x1180000001AF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
|
|
{"LED_DBG" , 0x1180000001A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
|
|
{"LED_EN" , 0x1180000001A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
|
|
{"LED_POLARITY" , 0x1180000001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
|
|
{"LED_PRT" , 0x1180000001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
|
|
{"LED_PRT_FMT" , 0x1180000001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
|
|
{"LED_PRT_STATUS0" , 0x1180000001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
|
|
{"LED_PRT_STATUS1" , 0x1180000001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
|
|
{"LED_PRT_STATUS2" , 0x1180000001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
|
|
{"LED_PRT_STATUS3" , 0x1180000001A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
|
|
{"LED_PRT_STATUS4" , 0x1180000001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
|
|
{"LED_PRT_STATUS5" , 0x1180000001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
|
|
{"LED_PRT_STATUS6" , 0x1180000001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
|
|
{"LED_PRT_STATUS7" , 0x1180000001AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
|
|
{"LED_UDD_CNT0" , 0x1180000001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
|
|
{"LED_UDD_CNT1" , 0x1180000001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
|
|
{"LED_UDD_DAT0" , 0x1180000001A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
|
|
{"LED_UDD_DAT1" , 0x1180000001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
|
|
{"LED_UDD_DAT_CLR0" , 0x1180000001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
|
|
{"LED_UDD_DAT_CLR1" , 0x1180000001AD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
|
|
{"LED_UDD_DAT_SET0" , 0x1180000001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
|
|
{"LED_UDD_DAT_SET1" , 0x1180000001AD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
|
|
{"LMC0_COMP_CTL" , 0x1180088000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
|
|
{"LMC0_CTL" , 0x1180088000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
|
|
{"LMC0_DCLK_CNT_HI" , 0x1180088000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
|
|
{"LMC0_DCLK_CNT_LO" , 0x1180088000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
|
|
{"LMC0_DDR2_CTL" , 0x1180088000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
|
|
{"LMC0_DELAY_CFG" , 0x1180088000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
|
|
{"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
|
|
{"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
|
|
{"LMC0_IFB_CNT_HI" , 0x1180088000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
|
|
{"LMC0_IFB_CNT_LO" , 0x1180088000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
|
|
{"LMC0_MEM_CFG0" , 0x1180088000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
|
|
{"LMC0_MEM_CFG1" , 0x1180088000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
|
|
{"LMC0_OPS_CNT_HI" , 0x1180088000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
|
|
{"LMC0_OPS_CNT_LO" , 0x1180088000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
|
|
{"LMC0_PLL_BWCTL" , 0x1180088000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
|
|
{"LMC0_RODT_CTL" , 0x1180088000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
|
|
{"LMC0_WODT_CTL0" , 0x1180088000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
|
|
{"MIO_BOOT_BIST_STAT" , 0x11800000000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
|
|
{"MIO_BOOT_ERR" , 0x11800000000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
|
|
{"MIO_BOOT_INT" , 0x11800000000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
|
|
{"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
|
|
{"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
|
|
{"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
|
|
{"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
|
|
{"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
|
|
{"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
|
|
{"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
|
|
{"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
|
|
{"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
|
|
{"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
|
|
{"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
|
|
{"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
|
|
{"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
|
|
{"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
|
|
{"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
|
|
{"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
|
|
{"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
|
|
{"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
|
|
{"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
|
|
{"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
|
|
{"MIO_BOOT_THR" , 0x11800000000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
|
|
{"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
|
|
{"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 289},
|
|
{"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
|
|
{"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
|
|
{"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
|
|
{"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
|
|
{"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
|
|
{"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
|
|
{"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
|
|
{"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
|
|
{"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
|
|
{"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
|
|
{"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
|
|
{"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
|
|
{"MIO_UART1_DLH" , 0x1180000000C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
|
|
{"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
|
|
{"MIO_UART1_DLL" , 0x1180000000C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
|
|
{"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
|
|
{"MIO_UART1_FAR" , 0x1180000000D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
|
|
{"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
|
|
{"MIO_UART1_FCR" , 0x1180000000C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
|
|
{"MIO_UART0_HTX" , 0x1180000000B08ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
|
|
{"MIO_UART1_HTX" , 0x1180000000F08ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
|
|
{"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
|
|
{"MIO_UART1_IER" , 0x1180000000C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
|
|
{"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
|
|
{"MIO_UART1_IIR" , 0x1180000000C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
|
|
{"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
|
|
{"MIO_UART1_LCR" , 0x1180000000C18ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
|
|
{"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
|
|
{"MIO_UART1_LSR" , 0x1180000000C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
|
|
{"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
|
|
{"MIO_UART1_MCR" , 0x1180000000C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
|
|
{"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
|
|
{"MIO_UART1_MSR" , 0x1180000000C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
|
|
{"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
|
|
{"MIO_UART1_RBR" , 0x1180000000C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
|
|
{"MIO_UART0_RFL" , 0x1180000000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
|
|
{"MIO_UART1_RFL" , 0x1180000000E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
|
|
{"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
|
|
{"MIO_UART1_RFW" , 0x1180000000D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
|
|
{"MIO_UART0_SBCR" , 0x1180000000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
|
|
{"MIO_UART1_SBCR" , 0x1180000000E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
|
|
{"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
|
|
{"MIO_UART1_SCR" , 0x1180000000C38ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
|
|
{"MIO_UART0_SFE" , 0x1180000000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
|
|
{"MIO_UART1_SFE" , 0x1180000000E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
|
|
{"MIO_UART0_SRR" , 0x1180000000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
|
|
{"MIO_UART1_SRR" , 0x1180000000E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
|
|
{"MIO_UART0_SRT" , 0x1180000000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
|
|
{"MIO_UART1_SRT" , 0x1180000000E38ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
|
|
{"MIO_UART0_SRTS" , 0x1180000000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
|
|
{"MIO_UART1_SRTS" , 0x1180000000E18ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
|
|
{"MIO_UART0_STT" , 0x1180000000B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
|
|
{"MIO_UART1_STT" , 0x1180000000F00ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
|
|
{"MIO_UART0_TFL" , 0x1180000000A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
|
|
{"MIO_UART1_TFL" , 0x1180000000E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
|
|
{"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
|
|
{"MIO_UART1_TFR" , 0x1180000000D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
|
|
{"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
|
|
{"MIO_UART1_THR" , 0x1180000000C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
|
|
{"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
|
|
{"MIO_UART1_USR" , 0x1180000000D38ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
|
|
{"NPI_BASE_ADDR_INPUT0" , 0x11F0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
|
|
{"NPI_BASE_ADDR_INPUT1" , 0x11F0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
|
|
{"NPI_BASE_ADDR_INPUT2" , 0x11F0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
|
|
{"NPI_BASE_ADDR_INPUT3" , 0x11F00000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 326},
|
|
{"NPI_BASE_ADDR_OUTPUT0" , 0x11F00000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
|
|
{"NPI_BASE_ADDR_OUTPUT1" , 0x11F00000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
|
|
{"NPI_BASE_ADDR_OUTPUT2" , 0x11F00000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
|
|
{"NPI_BASE_ADDR_OUTPUT3" , 0x11F00000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 327},
|
|
{"NPI_BIST_STATUS" , 0x11F00000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 328},
|
|
{"NPI_BUFF_SIZE_OUTPUT0" , 0x11F00000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 329},
|
|
{"NPI_BUFF_SIZE_OUTPUT1" , 0x11F00000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 329},
|
|
{"NPI_BUFF_SIZE_OUTPUT2" , 0x11F00000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 329},
|
|
{"NPI_BUFF_SIZE_OUTPUT3" , 0x11F00000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 329},
|
|
{"NPI_CTL_STATUS" , 0x11F0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 330},
|
|
{"NPI_DBG_SELECT" , 0x11F0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 331},
|
|
{"NPI_DMA_CONTROL" , 0x11F0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 332},
|
|
{"NPI_DMA_HIGHP_COUNTS" , 0x11F0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 333},
|
|
{"NPI_DMA_HIGHP_NADDR" , 0x11F0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 334},
|
|
{"NPI_DMA_LOWP_COUNTS" , 0x11F0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 335},
|
|
{"NPI_DMA_LOWP_NADDR" , 0x11F0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
|
|
{"NPI_HIGHP_DBELL" , 0x11F0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
|
|
{"NPI_HIGHP_IBUFF_SADDR" , 0x11F0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
|
|
{"NPI_INPUT_CONTROL" , 0x11F0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
|
|
{"NPI_INT_ENB" , 0x11F0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
|
|
{"NPI_INT_SUM" , 0x11F0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
|
|
{"NPI_LOWP_DBELL" , 0x11F0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
|
|
{"NPI_LOWP_IBUFF_SADDR" , 0x11F0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
|
|
{"NPI_MEM_ACCESS_SUBID3" , 0x11F0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 344},
|
|
{"NPI_MEM_ACCESS_SUBID4" , 0x11F0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 344},
|
|
{"NPI_MEM_ACCESS_SUBID5" , 0x11F0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 344},
|
|
{"NPI_MEM_ACCESS_SUBID6" , 0x11F0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 344},
|
|
{"NPI_MSI_RCV" , 0x11F0000001190ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 345},
|
|
{"NPI_NUM_DESC_OUTPUT0" , 0x11F0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 346},
|
|
{"NPI_NUM_DESC_OUTPUT1" , 0x11F0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 346},
|
|
{"NPI_NUM_DESC_OUTPUT2" , 0x11F0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 346},
|
|
{"NPI_NUM_DESC_OUTPUT3" , 0x11F0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 346},
|
|
{"NPI_OUTPUT_CONTROL" , 0x11F0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 347},
|
|
{"NPI_P0_DBPAIR_ADDR" , 0x11F0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 348},
|
|
{"NPI_P1_DBPAIR_ADDR" , 0x11F0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 348},
|
|
{"NPI_P2_DBPAIR_ADDR" , 0x11F0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 348},
|
|
{"NPI_P3_DBPAIR_ADDR" , 0x11F0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 348},
|
|
{"NPI_P0_INSTR_ADDR" , 0x11F00000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
|
|
{"NPI_P1_INSTR_ADDR" , 0x11F00000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
|
|
{"NPI_P2_INSTR_ADDR" , 0x11F00000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
|
|
{"NPI_P3_INSTR_ADDR" , 0x11F00000001D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
|
|
{"NPI_P0_INSTR_CNTS" , 0x11F00000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
|
|
{"NPI_P1_INSTR_CNTS" , 0x11F00000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
|
|
{"NPI_P2_INSTR_CNTS" , 0x11F00000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
|
|
{"NPI_P3_INSTR_CNTS" , 0x11F00000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
|
|
{"NPI_P0_PAIR_CNTS" , 0x11F0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
|
|
{"NPI_P1_PAIR_CNTS" , 0x11F0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
|
|
{"NPI_P2_PAIR_CNTS" , 0x11F0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
|
|
{"NPI_P3_PAIR_CNTS" , 0x11F0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
|
|
{"NPI_PCI_BURST_SIZE" , 0x11F00000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 352},
|
|
{"NPI_PCI_INT_ARB_CFG" , 0x11F0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 353},
|
|
{"NPI_PCI_READ_CMD" , 0x11F0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
|
|
{"NPI_PORT32_INSTR_HDR" , 0x11F00000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 355},
|
|
{"NPI_PORT33_INSTR_HDR" , 0x11F0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 356},
|
|
{"NPI_PORT34_INSTR_HDR" , 0x11F0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 357},
|
|
{"NPI_PORT35_INSTR_HDR" , 0x11F0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 358},
|
|
{"NPI_PORT_BP_CONTROL" , 0x11F00000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 359},
|
|
{"NPI_RSL_INT_BLOCKS" , 0x11F0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 360},
|
|
{"NPI_SIZE_INPUT0" , 0x11F0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 361},
|
|
{"NPI_SIZE_INPUT1" , 0x11F0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 361},
|
|
{"NPI_SIZE_INPUT2" , 0x11F0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 361},
|
|
{"NPI_SIZE_INPUT3" , 0x11F00000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 361},
|
|
{"NPI_WIN_READ_TO" , 0x11F00000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 362},
|
|
{"PCI_BAR1_INDEX0" , 0x11F0000001100ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX1" , 0x11F0000001104ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX2" , 0x11F0000001108ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX3" , 0x11F000000110Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX4" , 0x11F0000001110ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX5" , 0x11F0000001114ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX6" , 0x11F0000001118ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX7" , 0x11F000000111Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX8" , 0x11F0000001120ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX9" , 0x11F0000001124ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX10" , 0x11F0000001128ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX11" , 0x11F000000112Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX12" , 0x11F0000001130ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX13" , 0x11F0000001134ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX14" , 0x11F0000001138ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX15" , 0x11F000000113Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX16" , 0x11F0000001140ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX17" , 0x11F0000001144ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX18" , 0x11F0000001148ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX19" , 0x11F000000114Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX20" , 0x11F0000001150ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX21" , 0x11F0000001154ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX22" , 0x11F0000001158ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX23" , 0x11F000000115Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX24" , 0x11F0000001160ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX25" , 0x11F0000001164ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX26" , 0x11F0000001168ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX27" , 0x11F000000116Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX28" , 0x11F0000001170ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX29" , 0x11F0000001174ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX30" , 0x11F0000001178ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_BAR1_INDEX31" , 0x11F000000117Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 363},
|
|
{"PCI_CFG00" , 0x11F0000001800ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 364},
|
|
{"PCI_CFG01" , 0x11F0000001804ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 365},
|
|
{"PCI_CFG02" , 0x11F0000001808ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 366},
|
|
{"PCI_CFG03" , 0x11F000000180Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 367},
|
|
{"PCI_CFG04" , 0x11F0000001810ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 368},
|
|
{"PCI_CFG05" , 0x11F0000001814ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 369},
|
|
{"PCI_CFG06" , 0x11F0000001818ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 370},
|
|
{"PCI_CFG07" , 0x11F000000181Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 371},
|
|
{"PCI_CFG08" , 0x11F0000001820ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 372},
|
|
{"PCI_CFG09" , 0x11F0000001824ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 373},
|
|
{"PCI_CFG10" , 0x11F0000001828ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 374},
|
|
{"PCI_CFG11" , 0x11F000000182Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 375},
|
|
{"PCI_CFG12" , 0x11F0000001830ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 376},
|
|
{"PCI_CFG13" , 0x11F0000001834ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 377},
|
|
{"PCI_CFG15" , 0x11F000000183Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 378},
|
|
{"PCI_CFG16" , 0x11F0000001840ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 379},
|
|
{"PCI_CFG17" , 0x11F0000001844ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 380},
|
|
{"PCI_CFG18" , 0x11F0000001848ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 381},
|
|
{"PCI_CFG19" , 0x11F000000184Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 382},
|
|
{"PCI_CFG20" , 0x11F0000001850ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 383},
|
|
{"PCI_CFG21" , 0x11F0000001854ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 384},
|
|
{"PCI_CFG22" , 0x11F0000001858ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 385},
|
|
{"PCI_CFG56" , 0x11F00000018E0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 386},
|
|
{"PCI_CFG57" , 0x11F00000018E4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 387},
|
|
{"PCI_CFG58" , 0x11F00000018E8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 388},
|
|
{"PCI_CFG59" , 0x11F00000018ECull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 389},
|
|
{"PCI_CFG60" , 0x11F00000018F0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 390},
|
|
{"PCI_CFG61" , 0x11F00000018F4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 391},
|
|
{"PCI_CFG62" , 0x11F00000018F8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 392},
|
|
{"PCI_CFG63" , 0x11F00000018FCull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 393},
|
|
{"PCI_CTL_STATUS_2" , 0x11F000000118Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 394},
|
|
{"PCI_DBELL0" , 0x80ull, CVMX_CSR_DB_TYPE_PCI, 32, 395},
|
|
{"PCI_DBELL1" , 0x88ull, CVMX_CSR_DB_TYPE_PCI, 32, 395},
|
|
{"PCI_DBELL2" , 0x90ull, CVMX_CSR_DB_TYPE_PCI, 32, 395},
|
|
{"PCI_DBELL3" , 0x98ull, CVMX_CSR_DB_TYPE_PCI, 32, 395},
|
|
{"PCI_DMA_CNT0" , 0xA0ull, CVMX_CSR_DB_TYPE_PCI, 32, 396},
|
|
{"PCI_DMA_CNT1" , 0xA8ull, CVMX_CSR_DB_TYPE_PCI, 32, 396},
|
|
{"PCI_DMA_INT_LEV0" , 0xA4ull, CVMX_CSR_DB_TYPE_PCI, 32, 397},
|
|
{"PCI_DMA_INT_LEV1" , 0xACull, CVMX_CSR_DB_TYPE_PCI, 32, 397},
|
|
{"PCI_DMA_TIME0" , 0xB0ull, CVMX_CSR_DB_TYPE_PCI, 32, 398},
|
|
{"PCI_DMA_TIME1" , 0xB4ull, CVMX_CSR_DB_TYPE_PCI, 32, 398},
|
|
{"PCI_INSTR_COUNT0" , 0x84ull, CVMX_CSR_DB_TYPE_PCI, 32, 399},
|
|
{"PCI_INSTR_COUNT1" , 0x8Cull, CVMX_CSR_DB_TYPE_PCI, 32, 399},
|
|
{"PCI_INSTR_COUNT2" , 0x94ull, CVMX_CSR_DB_TYPE_PCI, 32, 399},
|
|
{"PCI_INSTR_COUNT3" , 0x9Cull, CVMX_CSR_DB_TYPE_PCI, 32, 399},
|
|
{"PCI_INT_ENB" , 0x38ull, CVMX_CSR_DB_TYPE_PCI, 64, 400},
|
|
{"PCI_INT_ENB2" , 0x11F00000011A0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 401},
|
|
{"PCI_INT_SUM" , 0x30ull, CVMX_CSR_DB_TYPE_PCI, 64, 402},
|
|
{"PCI_INT_SUM2" , 0x11F0000001198ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 403},
|
|
{"PCI_MSI_RCV" , 0xF0ull, CVMX_CSR_DB_TYPE_PCI, 32, 404},
|
|
{"PCI_PKT_CREDITS0" , 0x44ull, CVMX_CSR_DB_TYPE_PCI, 32, 405},
|
|
{"PCI_PKT_CREDITS1" , 0x54ull, CVMX_CSR_DB_TYPE_PCI, 32, 405},
|
|
{"PCI_PKT_CREDITS2" , 0x64ull, CVMX_CSR_DB_TYPE_PCI, 32, 405},
|
|
{"PCI_PKT_CREDITS3" , 0x74ull, CVMX_CSR_DB_TYPE_PCI, 32, 405},
|
|
{"PCI_PKTS_SENT0" , 0x40ull, CVMX_CSR_DB_TYPE_PCI, 32, 406},
|
|
{"PCI_PKTS_SENT1" , 0x50ull, CVMX_CSR_DB_TYPE_PCI, 32, 406},
|
|
{"PCI_PKTS_SENT2" , 0x60ull, CVMX_CSR_DB_TYPE_PCI, 32, 406},
|
|
{"PCI_PKTS_SENT3" , 0x70ull, CVMX_CSR_DB_TYPE_PCI, 32, 406},
|
|
{"PCI_PKTS_SENT_INT_LEV0" , 0x48ull, CVMX_CSR_DB_TYPE_PCI, 32, 407},
|
|
{"PCI_PKTS_SENT_INT_LEV1" , 0x58ull, CVMX_CSR_DB_TYPE_PCI, 32, 407},
|
|
{"PCI_PKTS_SENT_INT_LEV2" , 0x68ull, CVMX_CSR_DB_TYPE_PCI, 32, 407},
|
|
{"PCI_PKTS_SENT_INT_LEV3" , 0x78ull, CVMX_CSR_DB_TYPE_PCI, 32, 407},
|
|
{"PCI_PKTS_SENT_TIME0" , 0x4Cull, CVMX_CSR_DB_TYPE_PCI, 32, 408},
|
|
{"PCI_PKTS_SENT_TIME1" , 0x5Cull, CVMX_CSR_DB_TYPE_PCI, 32, 408},
|
|
{"PCI_PKTS_SENT_TIME2" , 0x6Cull, CVMX_CSR_DB_TYPE_PCI, 32, 408},
|
|
{"PCI_PKTS_SENT_TIME3" , 0x7Cull, CVMX_CSR_DB_TYPE_PCI, 32, 408},
|
|
{"PCI_READ_CMD_6" , 0x11F0000001180ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 409},
|
|
{"PCI_READ_CMD_C" , 0x11F0000001184ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 410},
|
|
{"PCI_READ_CMD_E" , 0x11F0000001188ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 411},
|
|
{"PCI_READ_TIMEOUT" , 0x11F00000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 412},
|
|
{"PCI_SCM_REG" , 0x11F00000011A8ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 413},
|
|
{"PCI_TSR_REG" , 0x11F00000011B0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 414},
|
|
{"PCI_WIN_RD_ADDR" , 0x8ull, CVMX_CSR_DB_TYPE_PCI, 64, 415},
|
|
{"PCI_WIN_RD_DATA" , 0x20ull, CVMX_CSR_DB_TYPE_PCI, 64, 416},
|
|
{"PCI_WIN_WR_ADDR" , 0x0ull, CVMX_CSR_DB_TYPE_PCI, 64, 417},
|
|
{"PCI_WIN_WR_DATA" , 0x10ull, CVMX_CSR_DB_TYPE_PCI, 64, 418},
|
|
{"PCI_WIN_WR_MASK" , 0x18ull, CVMX_CSR_DB_TYPE_PCI, 64, 419},
|
|
{"PIP_BCK_PRS" , 0x11800A0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_BIST_STATUS" , 0x11800A0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_CRC_CTL0" , 0x11800A0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_CRC_CTL1" , 0x11800A0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_CRC_IV0" , 0x11800A0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
|
|
{"PIP_CRC_IV1" , 0x11800A0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
|
|
{"PIP_DEC_IPSEC0" , 0x11800A0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
|
|
{"PIP_DEC_IPSEC1" , 0x11800A0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
|
|
{"PIP_DEC_IPSEC2" , 0x11800A0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
|
|
{"PIP_DEC_IPSEC3" , 0x11800A0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
|
|
{"PIP_GBL_CFG" , 0x11800A0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
|
|
{"PIP_GBL_CTL" , 0x11800A0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_INT_EN" , 0x11800A0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_INT_REG" , 0x11800A0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_IP_OFFSET" , 0x11800A0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_PRT_CFG0" , 0x11800A0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG1" , 0x11800A0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG2" , 0x11800A0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG3" , 0x11800A0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG4" , 0x11800A0000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG5" , 0x11800A0000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG6" , 0x11800A0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG7" , 0x11800A0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG8" , 0x11800A0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG9" , 0x11800A0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG10" , 0x11800A0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG11" , 0x11800A0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG12" , 0x11800A0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG13" , 0x11800A0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG14" , 0x11800A0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG15" , 0x11800A0000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG16" , 0x11800A0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG17" , 0x11800A0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG18" , 0x11800A0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG19" , 0x11800A0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG20" , 0x11800A00002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG21" , 0x11800A00002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG22" , 0x11800A00002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG23" , 0x11800A00002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG24" , 0x11800A00002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG25" , 0x11800A00002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG26" , 0x11800A00002D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG27" , 0x11800A00002D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG28" , 0x11800A00002E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG29" , 0x11800A00002E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG30" , 0x11800A00002F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG31" , 0x11800A00002F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG32" , 0x11800A0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG33" , 0x11800A0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG34" , 0x11800A0000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_CFG35" , 0x11800A0000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_PRT_TAG0" , 0x11800A0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG1" , 0x11800A0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG2" , 0x11800A0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG3" , 0x11800A0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG4" , 0x11800A0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG5" , 0x11800A0000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG6" , 0x11800A0000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG7" , 0x11800A0000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG8" , 0x11800A0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG9" , 0x11800A0000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG10" , 0x11800A0000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG11" , 0x11800A0000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG12" , 0x11800A0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG13" , 0x11800A0000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG14" , 0x11800A0000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG15" , 0x11800A0000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG16" , 0x11800A0000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG17" , 0x11800A0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG18" , 0x11800A0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG19" , 0x11800A0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG20" , 0x11800A00004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG21" , 0x11800A00004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG22" , 0x11800A00004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG23" , 0x11800A00004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG24" , 0x11800A00004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG25" , 0x11800A00004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG26" , 0x11800A00004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG27" , 0x11800A00004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG28" , 0x11800A00004E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG29" , 0x11800A00004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG30" , 0x11800A00004F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG31" , 0x11800A00004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG32" , 0x11800A0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG33" , 0x11800A0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG34" , 0x11800A0000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_PRT_TAG35" , 0x11800A0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_QOS_DIFF0" , 0x11800A0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF1" , 0x11800A0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF2" , 0x11800A0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF3" , 0x11800A0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF4" , 0x11800A0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF5" , 0x11800A0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF6" , 0x11800A0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF7" , 0x11800A0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF8" , 0x11800A0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF9" , 0x11800A0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF10" , 0x11800A0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF11" , 0x11800A0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF12" , 0x11800A0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF13" , 0x11800A0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF14" , 0x11800A0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF15" , 0x11800A0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF16" , 0x11800A0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF17" , 0x11800A0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF18" , 0x11800A0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF19" , 0x11800A0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF20" , 0x11800A00006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF21" , 0x11800A00006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF22" , 0x11800A00006B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF23" , 0x11800A00006B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF24" , 0x11800A00006C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF25" , 0x11800A00006C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF26" , 0x11800A00006D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF27" , 0x11800A00006D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF28" , 0x11800A00006E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF29" , 0x11800A00006E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF30" , 0x11800A00006F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF31" , 0x11800A00006F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF32" , 0x11800A0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF33" , 0x11800A0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF34" , 0x11800A0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF35" , 0x11800A0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF36" , 0x11800A0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF37" , 0x11800A0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF38" , 0x11800A0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF39" , 0x11800A0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF40" , 0x11800A0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF41" , 0x11800A0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF42" , 0x11800A0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF43" , 0x11800A0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF44" , 0x11800A0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF45" , 0x11800A0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF46" , 0x11800A0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF47" , 0x11800A0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF48" , 0x11800A0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF49" , 0x11800A0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF50" , 0x11800A0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF51" , 0x11800A0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF52" , 0x11800A00007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF53" , 0x11800A00007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF54" , 0x11800A00007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF55" , 0x11800A00007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF56" , 0x11800A00007C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF57" , 0x11800A00007C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF58" , 0x11800A00007D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF59" , 0x11800A00007D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF60" , 0x11800A00007E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF61" , 0x11800A00007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF62" , 0x11800A00007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_DIFF63" , 0x11800A00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_QOS_VLAN0" , 0x11800A00000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_QOS_VLAN1" , 0x11800A00000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_QOS_VLAN2" , 0x11800A00000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_QOS_VLAN3" , 0x11800A00000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_QOS_VLAN4" , 0x11800A00000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_QOS_VLAN5" , 0x11800A00000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_QOS_VLAN6" , 0x11800A00000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_QOS_VLAN7" , 0x11800A00000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_QOS_WATCH0" , 0x11800A0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_QOS_WATCH1" , 0x11800A0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_QOS_WATCH2" , 0x11800A0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_QOS_WATCH3" , 0x11800A0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_RAW_WORD" , 0x11800A00000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_SFT_RST" , 0x11800A0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
|
|
{"PIP_STAT0_PRT0" , 0x11800A0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT1" , 0x11800A0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT2" , 0x11800A00008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT3" , 0x11800A00008F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT4" , 0x11800A0000940ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT5" , 0x11800A0000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT6" , 0x11800A00009E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT7" , 0x11800A0000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT8" , 0x11800A0000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT9" , 0x11800A0000AD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT10" , 0x11800A0000B20ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT11" , 0x11800A0000B70ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT12" , 0x11800A0000BC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT13" , 0x11800A0000C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT14" , 0x11800A0000C60ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT15" , 0x11800A0000CB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT16" , 0x11800A0000D00ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT17" , 0x11800A0000D50ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT18" , 0x11800A0000DA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT19" , 0x11800A0000DF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT20" , 0x11800A0000E40ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT21" , 0x11800A0000E90ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT22" , 0x11800A0000EE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT23" , 0x11800A0000F30ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT24" , 0x11800A0000F80ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT25" , 0x11800A0000FD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT26" , 0x11800A0001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT27" , 0x11800A0001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT28" , 0x11800A00010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT29" , 0x11800A0001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT30" , 0x11800A0001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT31" , 0x11800A00011B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT32" , 0x11800A0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT33" , 0x11800A0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT34" , 0x11800A00012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT0_PRT35" , 0x11800A00012F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_STAT1_PRT0" , 0x11800A0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT1" , 0x11800A0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT2" , 0x11800A00008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT3" , 0x11800A00008F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT4" , 0x11800A0000948ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT5" , 0x11800A0000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT6" , 0x11800A00009E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT7" , 0x11800A0000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT8" , 0x11800A0000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT9" , 0x11800A0000AD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT10" , 0x11800A0000B28ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT11" , 0x11800A0000B78ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT12" , 0x11800A0000BC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT13" , 0x11800A0000C18ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT14" , 0x11800A0000C68ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT15" , 0x11800A0000CB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT16" , 0x11800A0000D08ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT17" , 0x11800A0000D58ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT18" , 0x11800A0000DA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT19" , 0x11800A0000DF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT20" , 0x11800A0000E48ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT21" , 0x11800A0000E98ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT22" , 0x11800A0000EE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT23" , 0x11800A0000F38ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT24" , 0x11800A0000F88ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT25" , 0x11800A0000FD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT26" , 0x11800A0001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT27" , 0x11800A0001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT28" , 0x11800A00010C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT29" , 0x11800A0001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT30" , 0x11800A0001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT31" , 0x11800A00011B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT32" , 0x11800A0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT33" , 0x11800A0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT34" , 0x11800A00012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT1_PRT35" , 0x11800A00012F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_STAT2_PRT0" , 0x11800A0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT1" , 0x11800A0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT2" , 0x11800A00008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT3" , 0x11800A0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT4" , 0x11800A0000950ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT5" , 0x11800A00009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT6" , 0x11800A00009F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT7" , 0x11800A0000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT8" , 0x11800A0000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT9" , 0x11800A0000AE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT10" , 0x11800A0000B30ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT11" , 0x11800A0000B80ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT12" , 0x11800A0000BD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT13" , 0x11800A0000C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT14" , 0x11800A0000C70ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT15" , 0x11800A0000CC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT16" , 0x11800A0000D10ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT17" , 0x11800A0000D60ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT18" , 0x11800A0000DB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT19" , 0x11800A0000E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT20" , 0x11800A0000E50ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT21" , 0x11800A0000EA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT22" , 0x11800A0000EF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT23" , 0x11800A0000F40ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT24" , 0x11800A0000F90ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT25" , 0x11800A0000FE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT26" , 0x11800A0001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT27" , 0x11800A0001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT28" , 0x11800A00010D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT29" , 0x11800A0001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT30" , 0x11800A0001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT31" , 0x11800A00011C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT32" , 0x11800A0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT33" , 0x11800A0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT34" , 0x11800A00012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT2_PRT35" , 0x11800A0001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_STAT3_PRT0" , 0x11800A0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT1" , 0x11800A0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT2" , 0x11800A00008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT3" , 0x11800A0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT4" , 0x11800A0000958ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT5" , 0x11800A00009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT6" , 0x11800A00009F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT7" , 0x11800A0000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT8" , 0x11800A0000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT9" , 0x11800A0000AE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT10" , 0x11800A0000B38ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT11" , 0x11800A0000B88ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT12" , 0x11800A0000BD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT13" , 0x11800A0000C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT14" , 0x11800A0000C78ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT15" , 0x11800A0000CC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT16" , 0x11800A0000D18ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT17" , 0x11800A0000D68ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT18" , 0x11800A0000DB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT19" , 0x11800A0000E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT20" , 0x11800A0000E58ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT21" , 0x11800A0000EA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT22" , 0x11800A0000EF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT23" , 0x11800A0000F48ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT24" , 0x11800A0000F98ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT25" , 0x11800A0000FE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT26" , 0x11800A0001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT27" , 0x11800A0001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT28" , 0x11800A00010D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT29" , 0x11800A0001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT30" , 0x11800A0001178ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT31" , 0x11800A00011C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT32" , 0x11800A0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT33" , 0x11800A0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT34" , 0x11800A00012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT3_PRT35" , 0x11800A0001308ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_STAT4_PRT0" , 0x11800A0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT1" , 0x11800A0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT2" , 0x11800A00008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT3" , 0x11800A0000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT4" , 0x11800A0000960ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT5" , 0x11800A00009B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT6" , 0x11800A0000A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT7" , 0x11800A0000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT8" , 0x11800A0000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT9" , 0x11800A0000AF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT10" , 0x11800A0000B40ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT11" , 0x11800A0000B90ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT12" , 0x11800A0000BE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT13" , 0x11800A0000C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT14" , 0x11800A0000C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT15" , 0x11800A0000CD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT16" , 0x11800A0000D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT17" , 0x11800A0000D70ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT18" , 0x11800A0000DC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT19" , 0x11800A0000E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT20" , 0x11800A0000E60ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT21" , 0x11800A0000EB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT22" , 0x11800A0000F00ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT23" , 0x11800A0000F50ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT24" , 0x11800A0000FA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT25" , 0x11800A0000FF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT26" , 0x11800A0001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT27" , 0x11800A0001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT28" , 0x11800A00010E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT29" , 0x11800A0001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT30" , 0x11800A0001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT31" , 0x11800A00011D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT32" , 0x11800A0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT33" , 0x11800A0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT34" , 0x11800A00012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT4_PRT35" , 0x11800A0001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_STAT5_PRT0" , 0x11800A0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT1" , 0x11800A0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT2" , 0x11800A00008C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT3" , 0x11800A0000918ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT4" , 0x11800A0000968ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT5" , 0x11800A00009B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT6" , 0x11800A0000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT7" , 0x11800A0000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT8" , 0x11800A0000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT9" , 0x11800A0000AF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT10" , 0x11800A0000B48ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT11" , 0x11800A0000B98ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT12" , 0x11800A0000BE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT13" , 0x11800A0000C38ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT14" , 0x11800A0000C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT15" , 0x11800A0000CD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT16" , 0x11800A0000D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT17" , 0x11800A0000D78ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT18" , 0x11800A0000DC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT19" , 0x11800A0000E18ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT20" , 0x11800A0000E68ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT21" , 0x11800A0000EB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT22" , 0x11800A0000F08ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT23" , 0x11800A0000F58ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT24" , 0x11800A0000FA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT25" , 0x11800A0000FF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT26" , 0x11800A0001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT27" , 0x11800A0001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT28" , 0x11800A00010E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT29" , 0x11800A0001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT30" , 0x11800A0001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT31" , 0x11800A00011D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT32" , 0x11800A0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT33" , 0x11800A0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT34" , 0x11800A00012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT5_PRT35" , 0x11800A0001318ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_STAT6_PRT0" , 0x11800A0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT1" , 0x11800A0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT2" , 0x11800A00008D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT3" , 0x11800A0000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT4" , 0x11800A0000970ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT5" , 0x11800A00009C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT6" , 0x11800A0000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT7" , 0x11800A0000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT8" , 0x11800A0000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT9" , 0x11800A0000B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT10" , 0x11800A0000B50ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT11" , 0x11800A0000BA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT12" , 0x11800A0000BF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT13" , 0x11800A0000C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT14" , 0x11800A0000C90ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT15" , 0x11800A0000CE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT16" , 0x11800A0000D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT17" , 0x11800A0000D80ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT18" , 0x11800A0000DD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT19" , 0x11800A0000E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT20" , 0x11800A0000E70ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT21" , 0x11800A0000EC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT22" , 0x11800A0000F10ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT23" , 0x11800A0000F60ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT24" , 0x11800A0000FB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT25" , 0x11800A0001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT26" , 0x11800A0001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT27" , 0x11800A00010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT28" , 0x11800A00010F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT29" , 0x11800A0001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT30" , 0x11800A0001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT31" , 0x11800A00011E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT32" , 0x11800A0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT33" , 0x11800A0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT34" , 0x11800A00012D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT6_PRT35" , 0x11800A0001320ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_STAT7_PRT0" , 0x11800A0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT1" , 0x11800A0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT2" , 0x11800A00008D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT3" , 0x11800A0000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT4" , 0x11800A0000978ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT5" , 0x11800A00009C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT6" , 0x11800A0000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT7" , 0x11800A0000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT8" , 0x11800A0000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT9" , 0x11800A0000B08ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT10" , 0x11800A0000B58ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT11" , 0x11800A0000BA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT12" , 0x11800A0000BF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT13" , 0x11800A0000C48ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT14" , 0x11800A0000C98ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT15" , 0x11800A0000CE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT16" , 0x11800A0000D38ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT17" , 0x11800A0000D88ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT18" , 0x11800A0000DD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT19" , 0x11800A0000E28ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT20" , 0x11800A0000E78ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT21" , 0x11800A0000EC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT22" , 0x11800A0000F18ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT23" , 0x11800A0000F68ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT24" , 0x11800A0000FB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT25" , 0x11800A0001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT26" , 0x11800A0001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT27" , 0x11800A00010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT28" , 0x11800A00010F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT29" , 0x11800A0001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT30" , 0x11800A0001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT31" , 0x11800A00011E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT32" , 0x11800A0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT33" , 0x11800A0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT34" , 0x11800A00012D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT7_PRT35" , 0x11800A0001328ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_STAT8_PRT0" , 0x11800A0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT1" , 0x11800A0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT2" , 0x11800A00008E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT3" , 0x11800A0000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT4" , 0x11800A0000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT5" , 0x11800A00009D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT6" , 0x11800A0000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT7" , 0x11800A0000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT8" , 0x11800A0000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT9" , 0x11800A0000B10ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT10" , 0x11800A0000B60ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT11" , 0x11800A0000BB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT12" , 0x11800A0000C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT13" , 0x11800A0000C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT14" , 0x11800A0000CA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT15" , 0x11800A0000CF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT16" , 0x11800A0000D40ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT17" , 0x11800A0000D90ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT18" , 0x11800A0000DE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT19" , 0x11800A0000E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT20" , 0x11800A0000E80ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT21" , 0x11800A0000ED0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT22" , 0x11800A0000F20ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT23" , 0x11800A0000F70ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT24" , 0x11800A0000FC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT25" , 0x11800A0001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT26" , 0x11800A0001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT27" , 0x11800A00010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT28" , 0x11800A0001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT29" , 0x11800A0001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT30" , 0x11800A00011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT31" , 0x11800A00011F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT32" , 0x11800A0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT33" , 0x11800A0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT34" , 0x11800A00012E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT8_PRT35" , 0x11800A0001330ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_STAT9_PRT0" , 0x11800A0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT1" , 0x11800A0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT2" , 0x11800A00008E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT3" , 0x11800A0000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT4" , 0x11800A0000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT5" , 0x11800A00009D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT6" , 0x11800A0000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT7" , 0x11800A0000A78ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT8" , 0x11800A0000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT9" , 0x11800A0000B18ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT10" , 0x11800A0000B68ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT11" , 0x11800A0000BB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT12" , 0x11800A0000C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT13" , 0x11800A0000C58ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT14" , 0x11800A0000CA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT15" , 0x11800A0000CF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT16" , 0x11800A0000D48ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT17" , 0x11800A0000D98ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT18" , 0x11800A0000DE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT19" , 0x11800A0000E38ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT20" , 0x11800A0000E88ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT21" , 0x11800A0000ED8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT22" , 0x11800A0000F28ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT23" , 0x11800A0000F78ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT24" , 0x11800A0000FC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT25" , 0x11800A0001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT26" , 0x11800A0001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT27" , 0x11800A00010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT28" , 0x11800A0001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT29" , 0x11800A0001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT30" , 0x11800A00011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT31" , 0x11800A00011F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT32" , 0x11800A0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT33" , 0x11800A0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT34" , 0x11800A00012E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT9_PRT35" , 0x11800A0001338ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_STAT_CTL" , 0x11800A0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
|
|
{"PIP_STAT_INB_ERRS0" , 0x11800A0001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS1" , 0x11800A0001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS2" , 0x11800A0001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS3" , 0x11800A0001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS4" , 0x11800A0001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS5" , 0x11800A0001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS6" , 0x11800A0001AD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS7" , 0x11800A0001AF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS8" , 0x11800A0001B10ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS9" , 0x11800A0001B30ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS10" , 0x11800A0001B50ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS11" , 0x11800A0001B70ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS12" , 0x11800A0001B90ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS13" , 0x11800A0001BB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS14" , 0x11800A0001BD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS15" , 0x11800A0001BF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS16" , 0x11800A0001C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS17" , 0x11800A0001C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS18" , 0x11800A0001C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS19" , 0x11800A0001C70ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS20" , 0x11800A0001C90ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS21" , 0x11800A0001CB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS22" , 0x11800A0001CD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS23" , 0x11800A0001CF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS24" , 0x11800A0001D10ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS25" , 0x11800A0001D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS26" , 0x11800A0001D50ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS27" , 0x11800A0001D70ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS28" , 0x11800A0001D90ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS29" , 0x11800A0001DB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS30" , 0x11800A0001DD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS31" , 0x11800A0001DF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS32" , 0x11800A0001E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS33" , 0x11800A0001E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS34" , 0x11800A0001E50ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_ERRS35" , 0x11800A0001E70ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT_INB_OCTS0" , 0x11800A0001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS1" , 0x11800A0001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS2" , 0x11800A0001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS3" , 0x11800A0001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS4" , 0x11800A0001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS5" , 0x11800A0001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS6" , 0x11800A0001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS7" , 0x11800A0001AE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS8" , 0x11800A0001B08ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS9" , 0x11800A0001B28ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS10" , 0x11800A0001B48ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS11" , 0x11800A0001B68ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS12" , 0x11800A0001B88ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS13" , 0x11800A0001BA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS14" , 0x11800A0001BC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS15" , 0x11800A0001BE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS16" , 0x11800A0001C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS17" , 0x11800A0001C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS18" , 0x11800A0001C48ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS19" , 0x11800A0001C68ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS20" , 0x11800A0001C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS21" , 0x11800A0001CA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS22" , 0x11800A0001CC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS23" , 0x11800A0001CE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS24" , 0x11800A0001D08ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS25" , 0x11800A0001D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS26" , 0x11800A0001D48ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS27" , 0x11800A0001D68ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS28" , 0x11800A0001D88ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS29" , 0x11800A0001DA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS30" , 0x11800A0001DC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS31" , 0x11800A0001DE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS32" , 0x11800A0001E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS33" , 0x11800A0001E28ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS34" , 0x11800A0001E48ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_OCTS35" , 0x11800A0001E68ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT_INB_PKTS0" , 0x11800A0001A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS1" , 0x11800A0001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS2" , 0x11800A0001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS3" , 0x11800A0001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS4" , 0x11800A0001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS5" , 0x11800A0001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS6" , 0x11800A0001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS7" , 0x11800A0001AE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS8" , 0x11800A0001B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS9" , 0x11800A0001B20ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS10" , 0x11800A0001B40ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS11" , 0x11800A0001B60ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS12" , 0x11800A0001B80ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS13" , 0x11800A0001BA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS14" , 0x11800A0001BC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS15" , 0x11800A0001BE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS16" , 0x11800A0001C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS17" , 0x11800A0001C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS18" , 0x11800A0001C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS19" , 0x11800A0001C60ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS20" , 0x11800A0001C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS21" , 0x11800A0001CA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS22" , 0x11800A0001CC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS23" , 0x11800A0001CE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS24" , 0x11800A0001D00ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS25" , 0x11800A0001D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS26" , 0x11800A0001D40ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS27" , 0x11800A0001D60ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS28" , 0x11800A0001D80ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS29" , 0x11800A0001DA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS30" , 0x11800A0001DC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS31" , 0x11800A0001DE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS32" , 0x11800A0001E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS33" , 0x11800A0001E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS34" , 0x11800A0001E40ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT_INB_PKTS35" , 0x11800A0001E60ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_TAG_INC0" , 0x11800A0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC1" , 0x11800A0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC2" , 0x11800A0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC3" , 0x11800A0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC4" , 0x11800A0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC5" , 0x11800A0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC6" , 0x11800A0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC7" , 0x11800A0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC8" , 0x11800A0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC9" , 0x11800A0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC10" , 0x11800A0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC11" , 0x11800A0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC12" , 0x11800A0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC13" , 0x11800A0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC14" , 0x11800A0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC15" , 0x11800A0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC16" , 0x11800A0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC17" , 0x11800A0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC18" , 0x11800A0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC19" , 0x11800A0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC20" , 0x11800A00018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC21" , 0x11800A00018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC22" , 0x11800A00018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC23" , 0x11800A00018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC24" , 0x11800A00018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC25" , 0x11800A00018C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC26" , 0x11800A00018D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC27" , 0x11800A00018D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC28" , 0x11800A00018E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC29" , 0x11800A00018E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC30" , 0x11800A00018F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC31" , 0x11800A00018F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC32" , 0x11800A0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC33" , 0x11800A0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC34" , 0x11800A0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC35" , 0x11800A0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC36" , 0x11800A0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC37" , 0x11800A0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC38" , 0x11800A0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC39" , 0x11800A0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC40" , 0x11800A0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC41" , 0x11800A0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC42" , 0x11800A0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC43" , 0x11800A0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC44" , 0x11800A0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC45" , 0x11800A0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC46" , 0x11800A0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC47" , 0x11800A0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC48" , 0x11800A0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC49" , 0x11800A0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC50" , 0x11800A0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC51" , 0x11800A0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC52" , 0x11800A00019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC53" , 0x11800A00019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC54" , 0x11800A00019B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC55" , 0x11800A00019B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC56" , 0x11800A00019C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC57" , 0x11800A00019C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC58" , 0x11800A00019D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC59" , 0x11800A00019D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC60" , 0x11800A00019E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC61" , 0x11800A00019E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC62" , 0x11800A00019F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_INC63" , 0x11800A00019F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_TAG_MASK" , 0x11800A0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_TAG_SECRET" , 0x11800A0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_TODO_ENTRY" , 0x11800A0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PKO_MEM_DEBUG14" , 0x1180050001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 468},
|
|
{"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 473},
|
|
{"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 474},
|
|
{"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 475},
|
|
{"PKO_REG_CRC_CTL0" , 0x1180050000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 476},
|
|
{"PKO_REG_CRC_CTL1" , 0x1180050000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 476},
|
|
{"PKO_REG_CRC_ENABLE" , 0x1180050000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 477},
|
|
{"PKO_REG_CRC_IV0" , 0x1180050000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 478},
|
|
{"PKO_REG_CRC_IV1" , 0x1180050000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 478},
|
|
{"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
|
|
{"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 480},
|
|
{"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
|
|
{"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 482},
|
|
{"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 483},
|
|
{"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 484},
|
|
{"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 485},
|
|
{"POW_BIST_STAT" , 0x16700000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
|
|
{"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
|
|
{"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 489},
|
|
{"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
|
|
{"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
|
|
{"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
|
|
{"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
|
|
{"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
|
|
{"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
|
|
{"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
|
|
{"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 490},
|
|
{"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 491},
|
|
{"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 492},
|
|
{"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 493},
|
|
{"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
|
|
{"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
|
|
{"POW_PP_GRP_MSK2" , 0x1670000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
|
|
{"POW_PP_GRP_MSK3" , 0x1670000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
|
|
{"POW_PP_GRP_MSK4" , 0x1670000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
|
|
{"POW_PP_GRP_MSK5" , 0x1670000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
|
|
{"POW_PP_GRP_MSK6" , 0x1670000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
|
|
{"POW_PP_GRP_MSK7" , 0x1670000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
|
|
{"POW_PP_GRP_MSK8" , 0x1670000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
|
|
{"POW_PP_GRP_MSK9" , 0x1670000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
|
|
{"POW_PP_GRP_MSK10" , 0x1670000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
|
|
{"POW_PP_GRP_MSK11" , 0x1670000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
|
|
{"POW_PP_GRP_MSK12" , 0x1670000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
|
|
{"POW_PP_GRP_MSK13" , 0x1670000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
|
|
{"POW_PP_GRP_MSK14" , 0x1670000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
|
|
{"POW_PP_GRP_MSK15" , 0x1670000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 494},
|
|
{"POW_QOS_RND0" , 0x16700000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 495},
|
|
{"POW_QOS_RND1" , 0x16700000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 495},
|
|
{"POW_QOS_RND2" , 0x16700000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 495},
|
|
{"POW_QOS_RND3" , 0x16700000001D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 495},
|
|
{"POW_QOS_RND4" , 0x16700000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 495},
|
|
{"POW_QOS_RND5" , 0x16700000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 495},
|
|
{"POW_QOS_RND6" , 0x16700000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 495},
|
|
{"POW_QOS_RND7" , 0x16700000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 495},
|
|
{"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 496},
|
|
{"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 496},
|
|
{"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 496},
|
|
{"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 496},
|
|
{"POW_QOS_THR4" , 0x16700000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 496},
|
|
{"POW_QOS_THR5" , 0x16700000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 496},
|
|
{"POW_QOS_THR6" , 0x16700000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 496},
|
|
{"POW_QOS_THR7" , 0x16700000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 496},
|
|
{"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 497},
|
|
{"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 498},
|
|
{"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 499},
|
|
{"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 499},
|
|
{"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 499},
|
|
{"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 499},
|
|
{"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 499},
|
|
{"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 499},
|
|
{"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 499},
|
|
{"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 499},
|
|
{"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 500},
|
|
{"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
|
|
{"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
|
|
{"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
|
|
{"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
|
|
{"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
|
|
{"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
|
|
{"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
|
|
{"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
|
|
{"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
|
|
{"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
|
|
{"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
|
|
{"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
|
|
{"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
|
|
{"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
|
|
{"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
|
|
{"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
|
|
{"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 502},
|
|
{"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
|
|
{"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
|
|
{"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
|
|
{"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
|
|
{"POW_WQ_INT_THR4" , 0x16700000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
|
|
{"POW_WQ_INT_THR5" , 0x16700000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
|
|
{"POW_WQ_INT_THR6" , 0x16700000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
|
|
{"POW_WQ_INT_THR7" , 0x16700000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
|
|
{"POW_WQ_INT_THR8" , 0x16700000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
|
|
{"POW_WQ_INT_THR9" , 0x16700000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
|
|
{"POW_WQ_INT_THR10" , 0x16700000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
|
|
{"POW_WQ_INT_THR11" , 0x16700000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
|
|
{"POW_WQ_INT_THR12" , 0x16700000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
|
|
{"POW_WQ_INT_THR13" , 0x16700000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
|
|
{"POW_WQ_INT_THR14" , 0x16700000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
|
|
{"POW_WQ_INT_THR15" , 0x16700000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
|
|
{"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
|
|
{"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
|
|
{"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
|
|
{"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
|
|
{"POW_WS_PC4" , 0x16700000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
|
|
{"POW_WS_PC5" , 0x16700000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
|
|
{"POW_WS_PC6" , 0x16700000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
|
|
{"POW_WS_PC7" , 0x16700000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
|
|
{"POW_WS_PC8" , 0x16700000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
|
|
{"POW_WS_PC9" , 0x16700000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
|
|
{"POW_WS_PC10" , 0x16700000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
|
|
{"POW_WS_PC11" , 0x16700000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
|
|
{"POW_WS_PC12" , 0x16700000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
|
|
{"POW_WS_PC13" , 0x16700000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
|
|
{"POW_WS_PC14" , 0x16700000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
|
|
{"POW_WS_PC15" , 0x16700000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
|
|
{"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
|
|
{"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
|
|
{"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
|
|
{"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
|
|
{"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
|
|
{"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 510},
|
|
{"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 511},
|
|
{"SPX0_BCKPRS_CNT" , 0x1180090000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
|
|
{"SPX1_BCKPRS_CNT" , 0x1180098000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 512},
|
|
{"SPX0_BIST_STAT" , 0x11800900007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
|
|
{"SPX1_BIST_STAT" , 0x11800980007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 513},
|
|
{"SPX0_CLK_CTL" , 0x1180090000348ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
|
|
{"SPX1_CLK_CTL" , 0x1180098000348ull, CVMX_CSR_DB_TYPE_RSL, 64, 514},
|
|
{"SPX0_CLK_STAT" , 0x1180090000350ull, CVMX_CSR_DB_TYPE_RSL, 64, 515},
|
|
{"SPX1_CLK_STAT" , 0x1180098000350ull, CVMX_CSR_DB_TYPE_RSL, 64, 515},
|
|
{"SPX0_DBG_DESKEW_CTL" , 0x1180090000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 516},
|
|
{"SPX1_DBG_DESKEW_CTL" , 0x1180098000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 516},
|
|
{"SPX0_DBG_DESKEW_STATE" , 0x1180090000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 517},
|
|
{"SPX1_DBG_DESKEW_STATE" , 0x1180098000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 517},
|
|
{"SPX0_DRV_CTL" , 0x1180090000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 518},
|
|
{"SPX1_DRV_CTL" , 0x1180098000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 518},
|
|
{"SPX0_ERR_CTL" , 0x1180090000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 519},
|
|
{"SPX1_ERR_CTL" , 0x1180098000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 519},
|
|
{"SPX0_INT_DAT" , 0x1180090000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 520},
|
|
{"SPX1_INT_DAT" , 0x1180098000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 520},
|
|
{"SPX0_INT_MSK" , 0x1180090000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SPX1_INT_MSK" , 0x1180098000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SPX0_INT_REG" , 0x1180090000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 522},
|
|
{"SPX1_INT_REG" , 0x1180098000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 522},
|
|
{"SPX0_INT_SYNC" , 0x1180090000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 523},
|
|
{"SPX1_INT_SYNC" , 0x1180098000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 523},
|
|
{"SPX0_TPA_ACC" , 0x1180090000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 524},
|
|
{"SPX1_TPA_ACC" , 0x1180098000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 524},
|
|
{"SPX0_TPA_MAX" , 0x1180090000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
|
|
{"SPX1_TPA_MAX" , 0x1180098000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
|
|
{"SPX0_TPA_SEL" , 0x1180090000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 526},
|
|
{"SPX1_TPA_SEL" , 0x1180098000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 526},
|
|
{"SPX0_TRN4_CTL" , 0x1180090000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 527},
|
|
{"SPX1_TRN4_CTL" , 0x1180098000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 527},
|
|
{"SPX0_PLL_BW_CTL" , 0x1180090000388ull, CVMX_CSR_DB_TYPE_RSL, 64, 528},
|
|
{"SPX0_PLL_SETTING" , 0x1180090000380ull, CVMX_CSR_DB_TYPE_RSL, 64, 529},
|
|
{"SRX0_COM_CTL" , 0x1180090000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 530},
|
|
{"SRX1_COM_CTL" , 0x1180098000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 530},
|
|
{"SRX0_IGN_RX_FULL" , 0x1180090000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 531},
|
|
{"SRX1_IGN_RX_FULL" , 0x1180098000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 531},
|
|
{"SRX0_SPI4_CAL000" , 0x1180090000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL001" , 0x1180090000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL002" , 0x1180090000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL003" , 0x1180090000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL004" , 0x1180090000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL005" , 0x1180090000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL006" , 0x1180090000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL007" , 0x1180090000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL008" , 0x1180090000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL009" , 0x1180090000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL010" , 0x1180090000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL011" , 0x1180090000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL012" , 0x1180090000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL013" , 0x1180090000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL014" , 0x1180090000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL015" , 0x1180090000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL016" , 0x1180090000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL017" , 0x1180090000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL018" , 0x1180090000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL019" , 0x1180090000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL020" , 0x11800900000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL021" , 0x11800900000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL022" , 0x11800900000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL023" , 0x11800900000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL024" , 0x11800900000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL025" , 0x11800900000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL026" , 0x11800900000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL027" , 0x11800900000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL028" , 0x11800900000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL029" , 0x11800900000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL030" , 0x11800900000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_CAL031" , 0x11800900000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL000" , 0x1180098000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL001" , 0x1180098000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL002" , 0x1180098000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL003" , 0x1180098000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL004" , 0x1180098000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL005" , 0x1180098000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL006" , 0x1180098000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL007" , 0x1180098000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL008" , 0x1180098000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL009" , 0x1180098000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL010" , 0x1180098000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL011" , 0x1180098000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL012" , 0x1180098000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL013" , 0x1180098000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL014" , 0x1180098000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL015" , 0x1180098000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL016" , 0x1180098000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL017" , 0x1180098000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL018" , 0x1180098000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL019" , 0x1180098000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL020" , 0x11800980000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL021" , 0x11800980000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL022" , 0x11800980000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL023" , 0x11800980000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL024" , 0x11800980000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL025" , 0x11800980000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL026" , 0x11800980000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL027" , 0x11800980000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL028" , 0x11800980000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL029" , 0x11800980000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL030" , 0x11800980000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX1_SPI4_CAL031" , 0x11800980000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SRX0_SPI4_STAT" , 0x1180090000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 533},
|
|
{"SRX1_SPI4_STAT" , 0x1180098000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 533},
|
|
{"SRX0_SW_TICK_CTL" , 0x1180090000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 534},
|
|
{"SRX1_SW_TICK_CTL" , 0x1180098000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 534},
|
|
{"SRX0_SW_TICK_DAT" , 0x1180090000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 535},
|
|
{"SRX1_SW_TICK_DAT" , 0x1180098000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 535},
|
|
{"STX0_ARB_CTL" , 0x1180090000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 536},
|
|
{"STX1_ARB_CTL" , 0x1180098000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 536},
|
|
{"STX0_BCKPRS_CNT" , 0x1180090000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 537},
|
|
{"STX1_BCKPRS_CNT" , 0x1180098000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 537},
|
|
{"STX0_COM_CTL" , 0x1180090000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 538},
|
|
{"STX1_COM_CTL" , 0x1180098000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 538},
|
|
{"STX0_DIP_CNT" , 0x1180090000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 539},
|
|
{"STX1_DIP_CNT" , 0x1180098000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 539},
|
|
{"STX0_IGN_CAL" , 0x1180090000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
|
|
{"STX1_IGN_CAL" , 0x1180098000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
|
|
{"STX0_INT_MSK" , 0x11800900006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 541},
|
|
{"STX1_INT_MSK" , 0x11800980006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 541},
|
|
{"STX0_INT_REG" , 0x1180090000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 542},
|
|
{"STX1_INT_REG" , 0x1180098000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 542},
|
|
{"STX0_INT_SYNC" , 0x11800900006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 543},
|
|
{"STX1_INT_SYNC" , 0x11800980006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 543},
|
|
{"STX0_MIN_BST" , 0x1180090000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 544},
|
|
{"STX1_MIN_BST" , 0x1180098000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 544},
|
|
{"STX0_SPI4_CAL000" , 0x1180090000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL001" , 0x1180090000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL002" , 0x1180090000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL003" , 0x1180090000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL004" , 0x1180090000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL005" , 0x1180090000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL006" , 0x1180090000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL007" , 0x1180090000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL008" , 0x1180090000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL009" , 0x1180090000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL010" , 0x1180090000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL011" , 0x1180090000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL012" , 0x1180090000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL013" , 0x1180090000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL014" , 0x1180090000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL015" , 0x1180090000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL016" , 0x1180090000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL017" , 0x1180090000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL018" , 0x1180090000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL019" , 0x1180090000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL020" , 0x11800900004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL021" , 0x11800900004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL022" , 0x11800900004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL023" , 0x11800900004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL024" , 0x11800900004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL025" , 0x11800900004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL026" , 0x11800900004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL027" , 0x11800900004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL028" , 0x11800900004E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL029" , 0x11800900004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL030" , 0x11800900004F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_CAL031" , 0x11800900004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL000" , 0x1180098000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL001" , 0x1180098000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL002" , 0x1180098000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL003" , 0x1180098000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL004" , 0x1180098000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL005" , 0x1180098000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL006" , 0x1180098000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL007" , 0x1180098000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL008" , 0x1180098000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL009" , 0x1180098000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL010" , 0x1180098000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL011" , 0x1180098000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL012" , 0x1180098000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL013" , 0x1180098000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL014" , 0x1180098000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL015" , 0x1180098000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL016" , 0x1180098000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL017" , 0x1180098000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL018" , 0x1180098000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL019" , 0x1180098000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL020" , 0x11800980004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL021" , 0x11800980004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL022" , 0x11800980004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL023" , 0x11800980004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL024" , 0x11800980004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL025" , 0x11800980004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL026" , 0x11800980004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL027" , 0x11800980004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL028" , 0x11800980004E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL029" , 0x11800980004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL030" , 0x11800980004F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX1_SPI4_CAL031" , 0x11800980004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"STX0_SPI4_DAT" , 0x1180090000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 546},
|
|
{"STX1_SPI4_DAT" , 0x1180098000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 546},
|
|
{"STX0_SPI4_STAT" , 0x1180090000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 547},
|
|
{"STX1_SPI4_STAT" , 0x1180098000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 547},
|
|
{"STX0_STAT_BYTES_HI" , 0x1180090000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 548},
|
|
{"STX1_STAT_BYTES_HI" , 0x1180098000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 548},
|
|
{"STX0_STAT_BYTES_LO" , 0x1180090000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 549},
|
|
{"STX1_STAT_BYTES_LO" , 0x1180098000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 549},
|
|
{"STX0_STAT_CTL" , 0x1180090000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 550},
|
|
{"STX1_STAT_CTL" , 0x1180098000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 550},
|
|
{"STX0_STAT_PKT_XMT" , 0x1180090000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 551},
|
|
{"STX1_STAT_PKT_XMT" , 0x1180098000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 551},
|
|
{"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 552},
|
|
{"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 553},
|
|
{"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 554},
|
|
{"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 556},
|
|
{"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 557},
|
|
{"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 559},
|
|
{"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 560},
|
|
{"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 561},
|
|
{"TRA_BIST_STATUS" , 0x11800A8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 562},
|
|
{"TRA_CTL" , 0x11800A8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 563},
|
|
{"TRA_CYCLES_SINCE" , 0x11800A8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 564},
|
|
{"TRA_FILT_ADR_ADR" , 0x11800A8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 565},
|
|
{"TRA_FILT_ADR_MSK" , 0x11800A8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 566},
|
|
{"TRA_FILT_CMD" , 0x11800A8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 567},
|
|
{"TRA_FILT_DID" , 0x11800A8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"TRA_FILT_SID" , 0x11800A8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 569},
|
|
{"TRA_INT_STATUS" , 0x11800A8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 570},
|
|
{"TRA_READ_DAT" , 0x11800A8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 571},
|
|
{"TRA_TRIG0_ADR_ADR" , 0x11800A8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 572},
|
|
{"TRA_TRIG0_ADR_MSK" , 0x11800A80000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 573},
|
|
{"TRA_TRIG0_CMD" , 0x11800A8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 574},
|
|
{"TRA_TRIG0_DID" , 0x11800A8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 575},
|
|
{"TRA_TRIG0_SID" , 0x11800A8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 576},
|
|
{"TRA_TRIG1_ADR_ADR" , 0x11800A80000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 577},
|
|
{"TRA_TRIG1_ADR_MSK" , 0x11800A80000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 578},
|
|
{"TRA_TRIG1_CMD" , 0x11800A80000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 579},
|
|
{"TRA_TRIG1_DID" , 0x11800A80000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 580},
|
|
{"TRA_TRIG1_SID" , 0x11800A80000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 581},
|
|
{"ZIP_CMD_BIST_RESULT" , 0x1180038000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 582},
|
|
{"ZIP_CMD_BUF" , 0x1180038000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 583},
|
|
{"ZIP_CMD_CTL" , 0x1180038000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 584},
|
|
{"ZIP_CONSTANTS" , 0x11800380000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 585},
|
|
{"ZIP_DEBUG0" , 0x1180038000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 586},
|
|
{"ZIP_ERROR" , 0x1180038000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 587},
|
|
{"ZIP_INT_MASK" , 0x1180038000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 588},
|
|
{NULL,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xx[] = {
|
|
/* name , bit, width, csr, type, rst un, typ un, reset, typical */
|
|
{"OVRFLW" , 0, 4, 0, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXPOP" , 4, 4, 0, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXPSH" , 8, 4, 0, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_12_63" , 12, 52, 0, "RAZ", 1, 1, 0, 0},
|
|
{"OVRFLW" , 0, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXPOP" , 4, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXPSH" , 8, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 1, "RAZ", 1, 1, 0, 0},
|
|
{"INT_LOOP" , 0, 4, 2, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EXT_LOOP" , 4, 4, 2, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 2, "RAZ", 1, 1, 0, 0},
|
|
{"BYPASS" , 0, 1, 3, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 3, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 4, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 4, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 4, 5, "RO", 0, 1, 0ull, 0},
|
|
{"PCTL" , 4, 4, 5, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 5, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 4, 6, "R/W", 0, 1, 0ull, 0},
|
|
{"PCTL" , 4, 4, 6, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 6, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 0, 1, 7, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 7, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 5, 8, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 8, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 5, 9, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 9, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL" , 0, 5, 10, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 10, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL" , 0, 5, 11, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 11, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 12, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_5_63" , 5, 59, 12, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 13, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_5_63" , 5, 59, 13, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_EN" , 0, 4, 14, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 14, "RAZ", 1, 1, 0, 0},
|
|
{"ENABLE" , 0, 1, 15, "RO", 1, 1, 0, 0},
|
|
{"STATUS" , 1, 1, 15, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_2_63" , 2, 62, 15, "RAZ", 1, 1, 0, 0},
|
|
{"MSK" , 0, 64, 16, "R/W", 0, 1, 0ull, 0},
|
|
{"POWEROK" , 0, 1, 17, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 17, "RAZ", 1, 1, 0, 0},
|
|
{"SIG" , 0, 32, 18, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 18, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 19, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_5_63" , 5, 59, 19, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 4, 20, "R/W", 0, 0, 8ull, 8ull},
|
|
{"PCTL" , 4, 4, 20, "R/W", 0, 0, 8ull, 8ull},
|
|
{"RESERVED_8_63" , 8, 56, 20, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 4, 21, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 21, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_EN" , 0, 4, 22, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 22, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 4, 23, "R/W", 0, 1, 15ull, 0},
|
|
{"PCTL" , 4, 4, 23, "R/W", 0, 1, 15ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 23, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 24, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 24, "RAZ", 1, 1, 0, 0},
|
|
{"BIST" , 0, 4, 25, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 25, "RAZ", 1, 1, 0, 0},
|
|
{"DINT" , 0, 16, 26, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 26, "RAZ", 1, 1, 0, 0},
|
|
{"FUSE" , 0, 16, 27, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_16_63" , 16, 48, 27, "RAZ", 1, 1, 0, 0},
|
|
{"GSTOP" , 0, 1, 28, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 28, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 29, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 29, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 29, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 16, 30, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 30, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 31, "RO", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 31, "RO", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 31, "RO", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 31, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 31, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 31, "RO", 0, 0, 0ull, 0ull},
|
|
{"WDOG_SUM" , 44, 1, 31, "RO", 0, 0, 0ull, 0ull},
|
|
{"TWSI" , 45, 1, 31, "RO", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 31, "RO", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 31, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 31, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 31, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 31, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 31, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 31, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 16, 32, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 32, "RAZ", 1, 1, 0, 0},
|
|
{"BITS" , 0, 32, 33, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 33, "RAZ", 1, 1, 0, 0},
|
|
{"BITS" , 0, 32, 34, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 34, "RAZ", 1, 1, 0, 0},
|
|
{"NMI" , 0, 16, 35, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 35, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 0, 2, 36, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 36, "RAZ", 1, 1, 0, 0},
|
|
{"PPDBG" , 0, 16, 37, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 37, "RAZ", 1, 1, 0, 0},
|
|
{"POKE" , 0, 64, 38, "RAZ", 1, 1, 0, 0},
|
|
{"RST0" , 0, 1, 39, "R/W", 1, 1, 0, 0},
|
|
{"RST" , 1, 15, 39, "R/W", 0, 0, 32767ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 39, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_BIST" , 0, 1, 40, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 40, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_PRST" , 0, 1, 41, "R/W", 0, 0, 1ull, 0ull},
|
|
{"NPI" , 1, 1, 41, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HOST64" , 2, 1, 41, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_3_63" , 3, 61, 41, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_RST" , 0, 1, 42, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 42, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 36, 43, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ONE_SHOT" , 36, 1, 43, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 43, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 0, 2, 44, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STATE" , 2, 2, 44, "RO", 0, 0, 0ull, 0ull},
|
|
{"LEN" , 4, 16, 44, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 20, 24, 44, "RO", 0, 0, 0ull, 0ull},
|
|
{"DSTOP" , 44, 1, 44, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GSTOPEN" , 45, 1, 44, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_46_63" , 46, 18, 44, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 17, 45, "RO", 0, 1, 0ull, 0},
|
|
{"DSEL_EXT" , 17, 1, 45, "R/W", 0, 0, 1ull, 0ull},
|
|
{"C_MUL" , 18, 5, 45, "RO", 1, 1, 0, 0},
|
|
{"CCLK_DIV2" , 23, 1, 45, "RO", 1, 1, 0, 0},
|
|
{"DCLK_MUL2" , 24, 1, 45, "RO", 1, 1, 0, 0},
|
|
{"D_MUL" , 25, 4, 45, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 45, "RAZ", 1, 1, 0, 0},
|
|
{"PDF" , 0, 16, 46, "RO", 0, 0, 0ull, 0ull},
|
|
{"RDF" , 16, 16, 46, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 46, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"P1_BRF" , 0, 8, 47, "RO", 0, 0, 0ull, 0ull},
|
|
{"P0_BRF" , 8, 8, 47, "RO", 0, 0, 0ull, 0ull},
|
|
{"P1_BWB" , 16, 1, 47, "RO", 0, 0, 0ull, 0ull},
|
|
{"P0_BWB" , 17, 1, 47, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRF" , 18, 1, 47, "RO", 0, 0, 0ull, 0ull},
|
|
{"DRF" , 19, 1, 47, "RO", 0, 0, 0ull, 0ull},
|
|
{"GFU" , 20, 1, 47, "RO", 0, 0, 0ull, 0ull},
|
|
{"IFU" , 21, 1, 47, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRQ" , 22, 1, 47, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 47, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SARB" , 0, 1, 48, "R/W", 0, 0, 1ull, 1ull},
|
|
{"GXOR_ENA" , 1, 1, 48, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NXOR_ENA" , 2, 1, 48, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NRPL_ENA" , 3, 1, 48, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 48, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 20, 49, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_63" , 20, 44, 49, "RAZ", 1, 1, 0, 0},
|
|
{"SIZE" , 0, 9, 50, "R/W", 0, 1, 3ull, 0},
|
|
{"POOL" , 9, 3, 50, "R/W", 0, 1, 0ull, 0},
|
|
{"DWBCNT" , 12, 8, 50, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_20_63" , 20, 44, 50, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_4" , 0, 5, 51, "RAZ", 1, 1, 0, 0},
|
|
{"RDPTR" , 5, 31, 51, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 51, "RAZ", 1, 1, 0, 0},
|
|
{"CP2ECCENA" , 0, 1, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2SBE" , 1, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CP2DBE" , 2, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CP2SBINA" , 3, 1, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2DBINA" , 4, 1, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2SYN" , 5, 8, 52, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTEECCENA" , 13, 1, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DTESBE" , 14, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTEDBE" , 15, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTESBINA" , 16, 1, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DTEDBINA" , 17, 1, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DTESYN" , 18, 7, 52, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTEPARENA" , 25, 1, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DTEPERR" , 26, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTEPINA" , 27, 1, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2PARENA" , 28, 1, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2PERR" , 29, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CP2PINA" , 30, 1, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DBLOVF" , 31, 1, 52, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DBLINA" , 32, 1, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_33_63" , 33, 31, 52, "RAZ", 1, 1, 0, 0},
|
|
{"ENA_P1" , 0, 1, 53, "R/W", 0, 0, 1ull, 1ull},
|
|
{"ENA_P0" , 1, 1, 53, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_2" , 2, 1, 53, "RAZ", 1, 1, 0, 0},
|
|
{"MTYPE" , 3, 1, 53, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SIL_LAT" , 4, 2, 53, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RW_DLY" , 6, 4, 53, "R/W", 0, 0, 1ull, 1ull},
|
|
{"WR_DLY" , 10, 4, 53, "R/W", 0, 0, 2ull, 2ull},
|
|
{"FPRCH" , 14, 2, 53, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BPRCH" , 16, 2, 53, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BLEN" , 18, 1, 53, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PBUNK" , 19, 3, 53, "R/W", 0, 0, 2ull, 2ull},
|
|
{"R2R_PBUNK" , 22, 1, 53, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INIT_P1" , 23, 1, 53, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INIT_P0" , 24, 1, 53, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BUNK_INIT" , 25, 2, 53, "R/W", 0, 0, 3ull, 3ull},
|
|
{"LPP_ENA" , 27, 1, 53, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 53, "RAZ", 1, 1, 0, 0},
|
|
{"REF_INT" , 0, 4, 54, "R/W", 0, 0, 3ull, 3ull},
|
|
{"TSKW" , 4, 2, 54, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 54, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TRL" , 8, 4, 54, "R/W", 0, 0, 6ull, 6ull},
|
|
{"TWL" , 12, 4, 54, "R/W", 0, 0, 7ull, 7ull},
|
|
{"TRC" , 16, 4, 54, "R/W", 0, 0, 6ull, 6ull},
|
|
{"TMRSC" , 20, 3, 54, "R/W", 0, 0, 6ull, 6ull},
|
|
{"MRS_ENA" , 23, 1, 54, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AREF_ENA" , 24, 1, 54, "R/W", 0, 0, 0ull, 0ull},
|
|
{"REF_INTLO" , 25, 9, 54, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 54, "RAZ", 1, 1, 0, 0},
|
|
{"FCRAM2P" , 0, 1, 55, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAXBNK" , 1, 1, 55, "R/W", 0, 0, 1ull, 1ull},
|
|
{"UA_START" , 2, 2, 55, "R/W", 0, 0, 1ull, 1ull},
|
|
{"REFSHORT" , 4, 1, 55, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRFC" , 5, 5, 55, "R/W", 0, 0, 9ull, 9ull},
|
|
{"SILRST" , 10, 1, 55, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DTECLKDIS" , 11, 1, 55, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 55, "RAZ", 1, 1, 0, 0},
|
|
{"MADDR" , 0, 24, 56, "RO", 0, 0, 0ull, 0ull},
|
|
{"BNUM" , 24, 3, 56, "RO", 0, 0, 0ull, 0ull},
|
|
{"PNUM" , 27, 1, 56, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSRC" , 28, 2, 56, "RO", 0, 0, 0ull, 0ull},
|
|
{"FDST" , 30, 9, 56, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_39_63" , 39, 25, 56, "RAZ", 1, 1, 0, 0},
|
|
{"MRS" , 0, 15, 57, "R/W", 0, 0, 66ull, 66ull},
|
|
{"RESERVED_15_15" , 15, 1, 57, "RAZ", 1, 1, 0, 0},
|
|
{"EMRS" , 16, 15, 57, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_31_31" , 31, 1, 57, "RAZ", 1, 1, 0, 0},
|
|
{"EMRS2" , 32, 15, 57, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_47_63" , 47, 17, 57, "RAZ", 1, 1, 0, 0},
|
|
{"MRSDAT" , 0, 23, 58, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_23_63" , 23, 41, 58, "RAZ", 1, 1, 0, 0},
|
|
{"IMODE" , 0, 1, 59, "R/W", 0, 0, 1ull, 1ull},
|
|
{"QMODE" , 1, 1, 59, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PMODE" , 2, 1, 59, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DTMODE" , 3, 1, 59, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DCMODE" , 4, 1, 59, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SBDLCK" , 5, 1, 59, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SBDNUM" , 6, 4, 59, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 59, "RAZ", 1, 1, 0, 0},
|
|
{"SBD0" , 0, 64, 60, "RO", 1, 1, 0, 0},
|
|
{"SBD1" , 0, 64, 61, "RO", 1, 1, 0, 0},
|
|
{"SBD2" , 0, 64, 62, "RO", 1, 1, 0, 0},
|
|
{"SBD3" , 0, 64, 63, "RO", 1, 1, 0, 0},
|
|
{"FDR" , 0, 1, 64, "RO", 0, 0, 0ull, 0ull},
|
|
{"FFR" , 1, 1, 64, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPF1" , 2, 1, 64, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPF0" , 3, 1, 64, "RO", 0, 0, 0ull, 0ull},
|
|
{"FRD" , 4, 1, 64, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 64, "RAZ", 1, 1, 0, 0},
|
|
{"MEM0_ERR" , 0, 7, 65, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM1_ERR" , 7, 7, 65, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 14, 1, 65, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USE_STT" , 15, 1, 65, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USE_LDT" , 16, 1, 65, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 17, 1, 65, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 65, "RAZ", 1, 1, 0, 0},
|
|
{"FPF_RD" , 0, 11, 66, "R/W", 0, 0, 64ull, 0ull},
|
|
{"FPF_WR" , 11, 11, 66, "R/W", 0, 0, 196ull, 0ull},
|
|
{"RESERVED_22_63" , 22, 42, 66, "RAZ", 1, 1, 0, 0},
|
|
{"FPF_SIZ" , 0, 11, 67, "R/W", 0, 0, 256ull, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 67, "RAZ", 1, 1, 0, 0},
|
|
{"FPF_RD" , 0, 12, 68, "R/W", 0, 0, 64ull, 0ull},
|
|
{"FPF_WR" , 12, 12, 68, "R/W", 0, 0, 196ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 68, "RAZ", 1, 1, 0, 0},
|
|
{"FPF_SIZ" , 0, 12, 69, "R/W", 0, 0, 256ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 69, "RAZ", 1, 1, 0, 0},
|
|
{"FED0_SBE" , 0, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED0_DBE" , 1, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED1_SBE" , 2, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED1_DBE" , 3, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_UND" , 4, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_COFF" , 5, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_PERR" , 6, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_UND" , 7, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_COFF" , 8, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_PERR" , 9, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_UND" , 10, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_COFF" , 11, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_PERR" , 12, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_UND" , 13, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_COFF" , 14, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_PERR" , 15, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_UND" , 16, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_COFF" , 17, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_PERR" , 18, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_UND" , 19, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_COFF" , 20, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_PERR" , 21, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_UND" , 22, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_COFF" , 23, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_PERR" , 24, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_UND" , 25, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_COFF" , 26, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_PERR" , 27, 1, 70, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 70, "RAZ", 1, 1, 0, 0},
|
|
{"FED0_SBE" , 0, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED0_DBE" , 1, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED1_SBE" , 2, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED1_DBE" , 3, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_UND" , 4, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_COFF" , 5, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_PERR" , 6, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_UND" , 7, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_COFF" , 8, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_PERR" , 9, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_UND" , 10, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_COFF" , 11, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_PERR" , 12, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_UND" , 13, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_COFF" , 14, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_PERR" , 15, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_UND" , 16, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_COFF" , 17, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_PERR" , 18, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_UND" , 19, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_COFF" , 20, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_PERR" , 21, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_UND" , 22, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_COFF" , 23, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_PERR" , 24, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_UND" , 25, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_COFF" , 26, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_PERR" , 27, 1, 71, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 71, "RAZ", 1, 1, 0, 0},
|
|
{"QUE_SIZ" , 0, 29, 72, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 72, "RAZ", 1, 1, 0, 0},
|
|
{"PG_NUM" , 0, 25, 73, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 73, "RAZ", 1, 1, 0, 0},
|
|
{"ACT_INDX" , 0, 26, 74, "RO", 0, 1, 0ull, 0},
|
|
{"ACT_QUE" , 26, 3, 74, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 74, "RAZ", 0, 0, 0ull, 7ull},
|
|
{"EXP_INDX" , 0, 26, 75, "RO", 0, 1, 0ull, 0},
|
|
{"EXP_QUE" , 26, 3, 75, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 75, "RAZ", 0, 0, 0ull, 7ull},
|
|
{"CTL" , 0, 16, 76, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 76, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 32, 77, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 77, "RAZ", 1, 1, 0, 0},
|
|
{"OUT_COL" , 0, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NCB_OVR" , 1, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OUT_OVR" , 2, 16, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_21" , 18, 4, 78, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LOSTSTAT" , 22, 4, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"STATOVR" , 26, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INB_NXA" , 27, 4, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 78, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 10, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 79, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 1, 80, "RO", 1, 1, 0, 0},
|
|
{"EN" , 1, 1, 80, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_2_63" , 2, 62, 80, "RAZ", 1, 1, 0, 0},
|
|
{"PRT" , 0, 6, 81, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 81, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 82, "R/W", 0, 1, 0ull, 0},
|
|
{"SPEED" , 1, 1, 82, "R/W", 0, 1, 1ull, 0},
|
|
{"DUPLEX" , 2, 1, 82, "R/W", 0, 1, 1ull, 0},
|
|
{"SLOTTIME" , 3, 1, 82, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 82, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 64, 83, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 84, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 85, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 86, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 87, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 88, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 0, 8, 89, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 89, "RAZ", 1, 1, 0, 0},
|
|
{"BCST" , 0, 1, 90, "R/W", 0, 1, 1ull, 0},
|
|
{"MCST" , 1, 2, 90, "R/W", 0, 1, 0ull, 0},
|
|
{"CAM_MODE" , 3, 1, 90, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 90, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 5, 91, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_5_63" , 5, 59, 91, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CAREXT" , 1, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MAXERR" , 2, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"JABBER" , 3, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCSERR" , 4, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"ALNERR" , 5, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"LENERR" , 6, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RCVERR" , 7, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SKPERR" , 8, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"NIBERR" , 9, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_10_63" , 10, 54, 92, "RAZ", 1, 1, 0, 0},
|
|
{"PRE_CHK" , 0, 1, 93, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PRE_STRP" , 1, 1, 93, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_DRP" , 2, 1, 93, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_BCK" , 3, 1, 93, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_MCST" , 4, 1, 93, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_SMAC" , 5, 1, 93, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PRE_FREE" , 6, 1, 93, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VLAN_LEN" , 7, 1, 93, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PAD_LEN" , 8, 1, 93, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 93, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 16, 94, "R/W", 0, 0, 1536ull, 1536ull},
|
|
{"RESERVED_16_63" , 16, 48, 94, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 16, 95, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_16_63" , 16, 48, 95, "RAZ", 1, 1, 0, 0},
|
|
{"IFG" , 0, 4, 96, "R/W", 0, 0, 12ull, 12ull},
|
|
{"RESERVED_4_63" , 4, 60, 96, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAREXT" , 1, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 2, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"JABBER" , 3, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ALNERR" , 5, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 6, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RCVERR" , 7, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NIBERR" , 9, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OVRERR" , 10, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHY_LINK" , 16, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHY_SPD" , 17, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHY_DUPX" , 18, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 97, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CAREXT" , 1, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 2, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"JABBER" , 3, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ALNERR" , 5, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 6, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RCVERR" , 7, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NIBERR" , 9, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OVRERR" , 10, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PHY_LINK" , 16, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PHY_SPD" , 17, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PHY_DUPX" , 18, 1, 98, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 98, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 99, "R/W", 0, 0, 10240ull, 10240ull},
|
|
{"RESERVED_16_63" , 16, 48, 99, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 1, 100, "RO", 0, 1, 0ull, 0},
|
|
{"SPEED" , 1, 2, 100, "RO", 0, 1, 0ull, 0},
|
|
{"DUPLEX" , 3, 1, 100, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 100, "RAZ", 1, 1, 0, 0},
|
|
{"RD_CLR" , 0, 1, 101, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 101, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 102, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 102, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 103, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 103, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 104, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 104, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 105, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 105, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 106, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 106, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 107, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 107, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 108, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 108, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 109, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 109, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 110, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 110, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 7, 111, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 111, "RAZ", 1, 1, 0, 0},
|
|
{"FCSSEL" , 8, 1, 111, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 111, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 112, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_6_63" , 6, 58, 112, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 113, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_6_63" , 6, 58, 113, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 9, 114, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_9_63" , 9, 55, 114, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 16, 115, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 115, "RAZ", 1, 1, 0, 0},
|
|
{"DPRT" , 0, 4, 116, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 116, "RAZ", 1, 1, 0, 0},
|
|
{"COMMIT" , 0, 16, 117, "RO", 0, 0, 0ull, 0ull},
|
|
{"DROP" , 16, 16, 117, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 117, "RAZ", 1, 1, 0, 0},
|
|
{"PRTS" , 0, 3, 118, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_3_63" , 3, 61, 118, "RAZ", 1, 1, 0, 0},
|
|
{"SMAC" , 0, 48, 119, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 119, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 120, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP" , 16, 1, 120, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 120, "RAZ", 1, 1, 0, 0},
|
|
{"PREAMBLE" , 0, 1, 121, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PAD" , 1, 1, 121, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCS" , 2, 1, 121, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FORCE_FCS" , 3, 1, 121, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 121, "RAZ", 1, 1, 0, 0},
|
|
{"BURST" , 0, 16, 122, "R/W", 0, 0, 8192ull, 8192ull},
|
|
{"RESERVED_16_63" , 16, 48, 122, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_CNT" , 0, 6, 123, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_63" , 6, 58, 123, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL_EN" , 0, 1, 124, "R/W", 0, 0, 1ull, 1ull},
|
|
{"XSDEF_EN" , 1, 1, 124, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 124, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_SIZE" , 0, 8, 125, "R/W", 0, 0, 59ull, 59ull},
|
|
{"RESERVED_8_63" , 8, 56, 125, "RAZ", 1, 1, 0, 0},
|
|
{"INTERVAL" , 0, 16, 126, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 126, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 127, "R/W", 0, 1, 96ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 127, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 128, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_16_63" , 16, 48, 128, "RAZ", 1, 1, 0, 0},
|
|
{"SEND" , 0, 1, 129, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 129, "RAZ", 1, 1, 0, 0},
|
|
{"SLOT" , 0, 10, 130, "R/W", 0, 0, 512ull, 512ull},
|
|
{"RESERVED_10_63" , 10, 54, 130, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 131, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 131, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL" , 0, 32, 132, "RC/W", 0, 1, 0ull, 0},
|
|
{"XSDEF" , 32, 32, 132, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCOL" , 0, 32, 133, "RC/W", 0, 1, 0ull, 0},
|
|
{"SCOL" , 32, 32, 133, "RC/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 134, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 134, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 135, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 135, "RAZ", 1, 1, 0, 0},
|
|
{"HIST0" , 0, 32, 136, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST1" , 32, 32, 136, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST2" , 0, 32, 137, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST3" , 32, 32, 137, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST4" , 0, 32, 138, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST5" , 32, 32, 138, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST6" , 0, 32, 139, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST7" , 32, 32, 139, "RC/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 0, 32, 140, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 32, 32, 140, "RC/W", 0, 1, 0ull, 0},
|
|
{"CTL" , 0, 32, 141, "RC/W", 0, 1, 0ull, 0},
|
|
{"UNDFLW" , 32, 32, 141, "RC/W", 0, 1, 0ull, 0},
|
|
{"RD_CLR" , 0, 1, 142, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 142, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 9, 143, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_9_63" , 9, 55, 143, "RAZ", 1, 1, 0, 0},
|
|
{"BP" , 0, 4, 144, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 144, "RAZ", 1, 1, 0, 0},
|
|
{"LIMIT" , 0, 5, 145, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_5_63" , 5, 59, 145, "RAZ", 1, 1, 0, 0},
|
|
{"CORRUPT" , 0, 4, 146, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_4_63" , 4, 60, 146, "RAZ", 1, 1, 0, 0},
|
|
{"IFG1" , 0, 4, 147, "R/W", 0, 1, 8ull, 0},
|
|
{"IFG2" , 4, 4, 147, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 147, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 148, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NCB_NXA" , 1, 1, 148, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 4, 148, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 148, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 4, 148, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 4, 148, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LATE_COL" , 16, 4, 148, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 148, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NCB_NXA" , 1, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 4, 149, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 149, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 4, 149, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 4, 149, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LATE_COL" , 16, 4, 149, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 149, "RAZ", 1, 1, 0, 0},
|
|
{"JAM" , 0, 8, 150, "R/W", 0, 1, 238ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 150, "RAZ", 1, 1, 0, 0},
|
|
{"LFSR" , 0, 16, 151, "R/W", 0, 1, 65535ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 151, "RAZ", 1, 1, 0, 0},
|
|
{"IGN_FULL" , 0, 4, 152, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP" , 4, 4, 152, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EN" , 8, 4, 152, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 152, "RAZ", 1, 1, 0, 0},
|
|
{"DMAC" , 0, 48, 153, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
|
|
{"RESERVED_48_63" , 48, 16, 153, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 154, "R/W", 0, 0, 34824ull, 34824ull},
|
|
{"RESERVED_16_63" , 16, 48, 154, "RAZ", 1, 1, 0, 0},
|
|
{"PRTS" , 0, 5, 155, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 155, "RAZ", 1, 1, 0, 0},
|
|
{"CONT_PKT" , 0, 1, 156, "R/W", 0, 1, 0ull, 0},
|
|
{"TPA_CLR" , 1, 1, 156, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 156, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DRAIN" , 0, 16, 157, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 157, "RAZ", 1, 1, 0, 0},
|
|
{"MAX1" , 0, 8, 158, "R/W", 0, 1, 8ull, 0},
|
|
{"MAX2" , 8, 8, 158, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 158, "RAZ", 1, 1, 0, 0},
|
|
{"THRESH" , 0, 6, 159, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 159, "RAZ", 1, 1, 0, 0},
|
|
{"TX_OE" , 0, 1, 160, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RX_XOR" , 1, 1, 160, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_EN" , 2, 1, 160, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_TYPE" , 3, 1, 160, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_CNT" , 4, 4, 160, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_SEL" , 8, 4, 160, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 160, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 161, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 161, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 162, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 162, "RAZ", 1, 1, 0, 0},
|
|
{"CLR" , 0, 16, 163, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 163, "RAZ", 1, 1, 0, 0},
|
|
{"SET" , 0, 16, 164, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 164, "RAZ", 1, 1, 0, 0},
|
|
{"ICD" , 0, 1, 165, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBD" , 1, 1, 165, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRP1" , 2, 1, 165, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRP0" , 3, 1, 165, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRN1" , 4, 1, 165, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRN0" , 5, 1, 165, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBRQ1" , 6, 1, 165, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBRQ0" , 7, 1, 165, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNRT" , 8, 1, 165, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBR1" , 9, 1, 165, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBR0" , 10, 1, 165, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBDR1" , 11, 1, 165, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBDR0" , 12, 1, 165, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNR0" , 13, 1, 165, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNR1" , 14, 1, 165, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICR1" , 15, 1, 165, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICR0" , 16, 1, 165, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNRCB" , 17, 1, 165, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 165, "RAZ", 1, 1, 0, 0},
|
|
{"FAU_END" , 0, 1, 166, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB_ENB" , 1, 1, 166, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PKO_ENB" , 2, 1, 166, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INB_MAT" , 3, 1, 166, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OUTB_MAT" , 4, 1, 166, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 166, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 167, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 167, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 167, "RAZ", 1, 1, 0, 0},
|
|
{"TOUT_VAL" , 0, 12, 168, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TOUT_ENB" , 12, 1, 168, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 168, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 169, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 169, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 169, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 8, 170, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 8, 9, 170, "R/W", 0, 1, 0ull, 0},
|
|
{"OPC" , 17, 4, 170, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 21, 8, 170, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 170, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 8, 171, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 8, 9, 171, "R/W", 0, 1, 0ull, 0},
|
|
{"OPC" , 17, 4, 171, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 21, 8, 171, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 171, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 172, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 173, "R/W", 0, 1, 0ull, 0},
|
|
{"NP_SOP" , 0, 1, 174, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NP_EOP" , 1, 1, 174, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_SOP" , 2, 1, 174, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_EOP" , 3, 1, 174, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 174, "RAZ", 1, 1, 0, 0},
|
|
{"NP_SOP" , 0, 1, 175, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NP_EOP" , 1, 1, 175, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_SOP" , 2, 1, 175, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_EOP" , 3, 1, 175, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 175, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 176, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 176, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 176, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 177, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 177, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 177, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 178, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 178, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 178, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 9, 179, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 9, 8, 179, "R/W", 0, 1, 0ull, 0},
|
|
{"EOT" , 17, 1, 179, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 18, 8, 179, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_26_63" , 26, 38, 179, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 9, 180, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 9, 8, 180, "R/W", 0, 1, 0ull, 0},
|
|
{"EOT" , 17, 1, 180, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 18, 8, 180, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_26_63" , 26, 38, 180, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 181, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 182, "R/W", 0, 1, 0ull, 0},
|
|
{"CNT_VAL" , 0, 15, 183, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 183, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 183, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 184, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 184, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 184, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 185, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 185, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 185, "RAZ", 1, 1, 0, 0},
|
|
{"PORT" , 0, 6, 186, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 186, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP_SZ" , 0, 6, 187, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 187, "RAZ", 1, 1, 0, 0},
|
|
{"BACK" , 0, 4, 188, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 188, "RAZ", 1, 1, 0, 0},
|
|
{"BACK" , 0, 4, 189, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 189, "RAZ", 1, 1, 0, 0},
|
|
{"PWP" , 0, 1, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_NEW" , 1, 1, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_OLD" , 2, 1, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRC_OFF" , 3, 1, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ0" , 4, 1, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ1" , 5, 1, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM_WORD" , 6, 1, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM0" , 7, 1, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM1" , 8, 1, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM2" , 9, 1, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM3" , 10, 1, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPQ_PBE0" , 11, 1, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPQ_PBE1" , 12, 1, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_POW" , 13, 1, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_WP1" , 14, 1, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_WQED" , 15, 1, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 190, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_ENB" , 0, 36, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 191, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_CNT" , 0, 64, 192, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_EN" , 0, 1, 193, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OPC_MODE" , 1, 2, 193, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PBP_EN" , 3, 1, 193, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WQE_LEND" , 4, 1, 193, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKT_LEND" , 5, 1, 193, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NADDBUF" , 6, 1, 193, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDPKT" , 7, 1, 193, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 8, 1, 193, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LEN_M8" , 9, 1, 193, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_10_63" , 10, 54, 193, "RAZ", 1, 1, 0, 0},
|
|
{"PRC_PAR0" , 0, 1, 194, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR1" , 1, 1, 194, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR2" , 2, 1, 194, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR3" , 3, 1, 194, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_SUB" , 4, 1, 194, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DC_OVR" , 5, 1, 194, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CC_OVR" , 6, 1, 194, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C_COLL" , 7, 1, 194, "R/W", 0, 0, 0ull, 0ull},
|
|
{"D_COLL" , 8, 1, 194, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BC_OVR" , 9, 1, 194, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 194, "RAZ", 1, 1, 0, 0},
|
|
{"PRC_PAR0" , 0, 1, 195, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR1" , 1, 1, 195, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR2" , 2, 1, 195, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR3" , 3, 1, 195, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP_SUB" , 4, 1, 195, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DC_OVR" , 5, 1, 195, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CC_OVR" , 6, 1, 195, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C_COLL" , 7, 1, 195, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"D_COLL" , 8, 1, 195, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BC_OVR" , 9, 1, 195, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 195, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP_SZ" , 0, 6, 196, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 196, "RAZ", 1, 1, 0, 0},
|
|
{"MB_SIZE" , 0, 12, 197, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_12_63" , 12, 52, 197, "RAZ", 1, 1, 0, 0},
|
|
{"PTR" , 0, 29, 198, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 198, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 17, 199, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_ENB" , 17, 1, 199, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 199, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 25, 200, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 200, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 3, 201, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 3, 1, 201, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 4, 29, 201, "RO", 1, 1, 0, 0},
|
|
{"PRADDR" , 33, 3, 201, "RO", 1, 1, 0, 0},
|
|
{"MAX_PKT" , 36, 3, 201, "RO", 0, 0, 5ull, 5ull},
|
|
{"RESERVED_39_63" , 39, 25, 201, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 7, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 7, 1, 202, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 8, 29, 202, "RO", 1, 1, 0, 0},
|
|
{"MAX_PKT" , 37, 7, 202, "RO", 0, 0, 36ull, 36ull},
|
|
{"RESERVED_44_63" , 44, 20, 202, "RAZ", 1, 1, 0, 0},
|
|
{"WQE_PCNT" , 0, 7, 203, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_PCNT" , 7, 7, 203, "RO", 0, 0, 0ull, 0ull},
|
|
{"PFIF_CNT" , 14, 3, 203, "RO", 0, 0, 0ull, 0ull},
|
|
{"WQEV_CNT" , 17, 1, 203, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTV_CNT" , 18, 1, 203, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 203, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 8, 204, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 8, 1, 204, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 9, 29, 204, "RO", 1, 1, 0, 0},
|
|
{"PRADDR" , 38, 8, 204, "RO", 1, 1, 0, 0},
|
|
{"WRADDR" , 46, 8, 204, "RO", 1, 1, 0, 0},
|
|
{"MAX_CNTS" , 54, 7, 204, "RO", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_61_63" , 61, 3, 204, "RAZ", 1, 1, 0, 0},
|
|
{"PASS" , 0, 32, 205, "R/W", 0, 1, 0ull, 0},
|
|
{"DROP" , 32, 32, 205, "R/W", 0, 1, 0ull, 0},
|
|
{"Q0_PCNT" , 0, 32, 206, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 206, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_ENB" , 0, 36, 207, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AVG_DLY" , 36, 14, 207, "R/W", 0, 1, 0ull, 0},
|
|
{"PRB_DLY" , 50, 14, 207, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRB_CON" , 0, 32, 208, "R/W", 0, 1, 0ull, 0},
|
|
{"AVG_CON" , 32, 8, 208, "R/W", 0, 1, 0ull, 0},
|
|
{"NEW_CON" , 40, 8, 208, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_PCNT" , 48, 1, 208, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 208, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 25, 209, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT" , 25, 6, 209, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 209, "RAZ", 1, 1, 0, 0},
|
|
{"PORT_BIT" , 0, 32, 210, "R/W", 0, 0, 4294967295ull, 4294967295ull},
|
|
{"RESERVED_32_63" , 32, 32, 210, "RAZ", 1, 1, 0, 0},
|
|
{"WQE_POOL" , 0, 3, 211, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_3_63" , 3, 61, 211, "RAZ", 1, 1, 0, 0},
|
|
{"PTR" , 0, 29, 212, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 212, "RAZ", 1, 1, 0, 0},
|
|
{"MEM0" , 0, 1, 213, "RO", 0, 0, 0ull, 0ull},
|
|
{"MEM1" , 1, 1, 213, "RO", 0, 0, 0ull, 0ull},
|
|
{"RRC" , 2, 1, 213, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 213, "RAZ", 1, 1, 0, 0},
|
|
{"MEM0_ERR" , 0, 7, 214, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM1_ERR" , 7, 7, 214, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 214, "RAZ", 1, 1, 0, 0},
|
|
{"KED0_SBE" , 0, 1, 215, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KED0_DBE" , 1, 1, 215, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KED1_SBE" , 2, 1, 215, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KED1_DBE" , 3, 1, 215, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 215, "RAZ", 1, 1, 0, 0},
|
|
{"KED0_SBE" , 0, 1, 216, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KED0_DBE" , 1, 1, 216, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KED1_SBE" , 2, 1, 216, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KED1_DBE" , 3, 1, 216, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 216, "RAZ", 1, 1, 0, 0},
|
|
{"WLB_DAT" , 0, 4, 217, "RO", 0, 0, 0ull, 0ull},
|
|
{"STIN_MSK" , 4, 1, 217, "RO", 0, 0, 0ull, 0ull},
|
|
{"DT" , 5, 1, 217, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTCNT" , 6, 13, 217, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 217, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"L2T" , 0, 9, 218, "RO", 0, 0, 0ull, 0ull},
|
|
{"VAB_VWCF" , 9, 1, 218, "RO", 0, 0, 0ull, 0ull},
|
|
{"LRF" , 10, 2, 218, "RO", 0, 0, 0ull, 0ull},
|
|
{"VWDF" , 12, 4, 218, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 218, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XRDDAT" , 0, 1, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"XRDMSK" , 1, 1, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"PICBST" , 2, 1, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPCBST" , 3, 1, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"RHDF" , 4, 4, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"RMDF" , 8, 4, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRB" , 12, 4, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 219, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LRF_ARB_MODE" , 0, 1, 220, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RFB_ARB_MODE" , 1, 1, 220, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RSP_ARB_MODE" , 2, 1, 220, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MWF_CRD" , 3, 4, 220, "R/W", 0, 0, 2ull, 2ull},
|
|
{"IDXALIAS" , 7, 1, 220, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPEN" , 8, 1, 220, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FPEMPTY" , 9, 1, 220, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FPEXP" , 10, 4, 220, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 220, "RAZ", 1, 1, 0, 0},
|
|
{"L2T" , 0, 1, 221, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2D" , 1, 1, 221, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FINV" , 2, 1, 221, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SET" , 3, 3, 221, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PPNUM" , 6, 4, 221, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LFB_DMP" , 10, 1, 221, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LFB_ENUM" , 11, 4, 221, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 221, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DT_TAG" , 0, 29, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"DT_VLD" , 29, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_30" , 30, 1, 222, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DTENA" , 31, 1, 222, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 222, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_ENA" , 0, 1, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_3" , 1, 3, 223, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_BASE" , 4, 27, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 223, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_OFFSET" , 0, 10, 224, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 224, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VLD" , 0, 1, 225, "RO", 0, 0, 0ull, 0ull},
|
|
{"CMD" , 1, 4, 225, "RO", 0, 0, 0ull, 0ull},
|
|
{"SID" , 5, 9, 225, "RO", 0, 0, 0ull, 0ull},
|
|
{"VABNUM" , 14, 4, 225, "RO", 0, 0, 0ull, 0ull},
|
|
{"SET" , 18, 3, 225, "RO", 0, 0, 0ull, 0ull},
|
|
{"IHD" , 21, 1, 225, "RO", 0, 0, 0ull, 0ull},
|
|
{"ITL" , 22, 1, 225, "RO", 0, 0, 0ull, 0ull},
|
|
{"INXT" , 23, 4, 225, "RO", 0, 0, 0ull, 0ull},
|
|
{"VAM" , 27, 1, 225, "RO", 0, 0, 0ull, 0ull},
|
|
{"STCFL" , 28, 1, 225, "RO", 0, 0, 0ull, 0ull},
|
|
{"STINV" , 29, 1, 225, "RO", 0, 0, 0ull, 0ull},
|
|
{"STPND" , 30, 1, 225, "RO", 0, 0, 0ull, 0ull},
|
|
{"STCPND" , 31, 1, 225, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 225, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VLD" , 0, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTPRB" , 1, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRBRTY" , 2, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTMFL" , 3, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTVTM" , 4, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTRSC" , 5, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTRSP" , 6, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTDT" , 7, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTRDA" , 8, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTM" , 9, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWRM" , 10, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWHF" , 11, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWHP" , 12, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTDQ" , 13, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTDW" , 14, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTRSP" , 15, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"BID" , 16, 2, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"DSGOING" , 18, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 226, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_IDX" , 0, 10, 227, "RO", 0, 0, 0ull, 0ull},
|
|
{"LFB_TAG" , 10, 17, 227, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_63" , 27, 37, 227, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_HWM" , 0, 4, 228, "R/W", 0, 0, 15ull, 15ull},
|
|
{"STPARTDIS" , 4, 1, 228, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 228, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PFCNT0" , 0, 36, 229, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 229, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT0SEL" , 0, 6, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0CLR" , 6, 1, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0ENA" , 7, 1, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1SEL" , 8, 6, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1CLR" , 14, 1, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1ENA" , 15, 1, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2SEL" , 16, 6, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2CLR" , 22, 1, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2ENA" , 23, 1, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3SEL" , 24, 6, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3CLR" , 30, 1, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3ENA" , 31, 1, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0RDCLR" , 32, 1, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1RDCLR" , 33, 1, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2RDCLR" , 34, 1, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3RDCLR" , 35, 1, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 230, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK0" , 0, 8, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK1" , 8, 8, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK2" , 16, 8, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK3" , 24, 8, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 231, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK4" , 0, 8, 232, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK5" , 8, 8, 232, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK6" , 16, 8, 232, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK7" , 24, 8, 232, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 232, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK8" , 0, 8, 233, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK9" , 8, 8, 233, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK10" , 16, 8, 233, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK11" , 24, 8, 233, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 233, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK12" , 0, 8, 234, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK13" , 8, 8, 234, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK14" , 16, 8, 234, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK15" , 24, 8, 234, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 234, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSKIOB" , 0, 8, 235, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 235, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q0STAT" , 0, 34, 236, "RO", 0, 0, 0ull, 0ull},
|
|
{"FTL" , 34, 1, 236, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_35_63" , 35, 29, 236, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q1STAT" , 0, 34, 237, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 237, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q2STAT" , 0, 34, 238, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 238, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q3STAT" , 0, 34, 239, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 239, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 0, 1, 240, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_INTENA" , 1, 1, 240, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DED_INTENA" , 2, 1, 240, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 3, 1, 240, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 4, 1, 240, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BMHCLSEL" , 5, 1, 240, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 240, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 0, 11, 241, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSET" , 11, 3, 241, "RO", 0, 0, 0ull, 0ull},
|
|
{"FOWMSK" , 14, 4, 241, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 241, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW0" , 0, 10, 242, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW1" , 10, 10, 242, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 242, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW2" , 0, 10, 243, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW3" , 10, 10, 243, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 243, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q0FUS" , 0, 34, 244, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 244, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q1FUS" , 0, 34, 245, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 245, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q2FUS" , 0, 34, 246, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 246, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q3FUS" , 0, 34, 247, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRIP_512K" , 34, 1, 247, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRIP_256K" , 35, 1, 247, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 247, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 0, 1, 248, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_INTENA" , 1, 1, 248, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DED_INTENA" , 2, 1, 248, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 3, 1, 248, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 4, 1, 248, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FSYN" , 5, 6, 248, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 11, 10, 248, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSET" , 21, 3, 248, "RO", 0, 0, 0ull, 0ull},
|
|
{"LCKERR" , 24, 1, 248, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK_INTENA" , 25, 1, 248, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LCKERR2" , 26, 1, 248, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK_INTENA2" , 27, 1, 248, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_28_63" , 28, 36, 248, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RATE" , 0, 8, 249, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_8_63" , 8, 56, 249, "RAZ", 1, 1, 0, 0},
|
|
{"PHASE" , 0, 7, 250, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_7_63" , 7, 57, 250, "RAZ", 1, 1, 0, 0},
|
|
{"RATE" , 0, 16, 251, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 251, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_EN" , 0, 1, 252, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 252, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 253, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 253, "RAZ", 1, 1, 0, 0},
|
|
{"POLARITY" , 0, 1, 254, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 254, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_EN" , 0, 8, 255, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 255, "RAZ", 1, 1, 0, 0},
|
|
{"FORMAT" , 0, 4, 256, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 256, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 6, 257, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 257, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 6, 258, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 258, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 32, 259, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 259, "RAZ", 1, 1, 0, 0},
|
|
{"CLR" , 0, 32, 260, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 260, "RAZ", 1, 1, 0, 0},
|
|
{"SET" , 0, 32, 261, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 261, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL_DAT" , 0, 4, 262, "R/W", 0, 1, 0ull, 0},
|
|
{"PCTL_CMD" , 4, 4, 262, "R/W", 0, 1, 0ull, 0},
|
|
{"PCTL_CLK" , 8, 4, 262, "R/W", 0, 1, 0ull, 0},
|
|
{"PCTL_CSR" , 12, 4, 262, "R/W", 0, 1, 15ull, 0},
|
|
{"NCTL_DAT" , 16, 4, 262, "R/W", 0, 1, 0ull, 0},
|
|
{"NCTL_CMD" , 20, 4, 262, "R/W", 0, 1, 0ull, 0},
|
|
{"NCTL_CLK" , 24, 4, 262, "R/W", 0, 1, 0ull, 0},
|
|
{"NCTL_CSR" , 28, 4, 262, "R/W", 0, 1, 15ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 262, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DIC" , 0, 2, 263, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QS_DIC" , 2, 2, 263, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TSKW" , 4, 2, 263, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SIL_LAT" , 6, 2, 263, "R/W", 0, 0, 1ull, 1ull},
|
|
{"BPRCH" , 8, 1, 263, "R/W", 0, 1, 0ull, 0},
|
|
{"FPRCH2" , 9, 1, 263, "R/W", 0, 0, 0ull, 1ull},
|
|
{"MODE128B" , 10, 1, 263, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SET_ZERO" , 11, 1, 263, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INORDER_MRF" , 12, 1, 263, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INORDER_MWF" , 13, 1, 263, "R/W", 0, 0, 0ull, 0ull},
|
|
{"R2R_SLOT" , 14, 1, 263, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RDIMM_ENA" , 15, 1, 263, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_17" , 16, 2, 263, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX_WRITE_BATCH" , 18, 4, 263, "R/W", 0, 0, 8ull, 8ull},
|
|
{"XOR_BANK" , 22, 1, 263, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SLOW_SCF" , 23, 1, 263, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DDR__PCTL" , 24, 4, 263, "RO", 1, 1, 0, 0},
|
|
{"DDR__NCTL" , 28, 4, 263, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 263, "RAZ", 1, 1, 0, 0},
|
|
{"DCLKCNT_HI" , 0, 32, 264, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 264, "RAZ", 1, 1, 0, 0},
|
|
{"DCLKCNT_LO" , 0, 32, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 265, "RAZ", 1, 1, 0, 0},
|
|
{"DDR2" , 0, 1, 266, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RDQS" , 1, 1, 266, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLL90_BYP" , 2, 1, 266, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLL90_VLU" , 3, 5, 266, "R/W", 0, 1, 0ull, 0},
|
|
{"QDLL_ENA" , 8, 1, 266, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ODT_ENA" , 9, 1, 266, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DDR2T" , 10, 1, 266, "R/W", 0, 1, 0ull, 0},
|
|
{"CRIP_MODE" , 11, 1, 266, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TFAW" , 12, 5, 266, "R/W", 0, 0, 0ull, 9ull},
|
|
{"DDR_EOF" , 17, 4, 266, "R/W", 0, 0, 2ull, 2ull},
|
|
{"SILO_HC" , 21, 1, 266, "R/W", 0, 1, 1ull, 0},
|
|
{"TWR" , 22, 3, 266, "R/W", 0, 0, 3ull, 1ull},
|
|
{"BWCNT" , 25, 1, 266, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POCAS" , 26, 1, 266, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDLAT" , 27, 3, 266, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BURST8" , 30, 1, 266, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BANK8" , 31, 1, 266, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 266, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CLK" , 0, 4, 267, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_4" , 4, 1, 267, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CMD" , 5, 4, 267, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 267, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DQ" , 10, 4, 267, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 267, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN0" , 0, 8, 268, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN1" , 8, 8, 268, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN2" , 16, 8, 268, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN3" , 24, 8, 268, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 268, "RAZ", 1, 1, 0, 0},
|
|
{"FCOL" , 0, 12, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"FROW" , 12, 14, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"FBANK" , 26, 3, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"FBUNK" , 29, 1, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"FDIMM" , 30, 2, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 269, "RAZ", 1, 1, 0, 0},
|
|
{"IFBCNT_HI" , 0, 32, 270, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 270, "RAZ", 1, 1, 0, 0},
|
|
{"IFBCNT_LO" , 0, 32, 271, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 271, "RAZ", 1, 1, 0, 0},
|
|
{"INIT_START" , 0, 1, 272, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 1, 1, 272, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ROW_LSB" , 2, 3, 272, "R/W", 0, 1, 3ull, 0},
|
|
{"PBANK_LSB" , 5, 4, 272, "R/W", 0, 1, 5ull, 0},
|
|
{"REF_INT" , 9, 6, 272, "R/W", 0, 0, 1ull, 2ull},
|
|
{"TCL" , 15, 4, 272, "R/W", 0, 1, 3ull, 0},
|
|
{"INTR_SEC_ENA" , 19, 1, 272, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INTR_DED_ENA" , 20, 1, 272, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 21, 4, 272, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 25, 4, 272, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BUNK_ENA" , 29, 1, 272, "R/W", 0, 1, 0ull, 0},
|
|
{"SILO_QC" , 30, 1, 272, "R/W", 0, 1, 0ull, 0},
|
|
{"RESET" , 31, 1, 272, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 272, "RAZ", 1, 1, 0, 0},
|
|
{"TRAS" , 0, 5, 273, "R/W", 0, 0, 12ull, 12ull},
|
|
{"TRCD" , 5, 4, 273, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TWTR" , 9, 4, 273, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TRP" , 13, 4, 273, "R/W", 0, 0, 5ull, 4ull},
|
|
{"TRFC" , 17, 5, 273, "R/W", 0, 0, 6ull, 7ull},
|
|
{"TMRD" , 22, 3, 273, "R/W", 0, 0, 2ull, 2ull},
|
|
{"CASLAT" , 25, 3, 273, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TRRD" , 28, 3, 273, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_31_63" , 31, 33, 273, "RAZ", 1, 1, 0, 0},
|
|
{"OPSCNT_HI" , 0, 32, 274, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 274, "RAZ", 1, 1, 0, 0},
|
|
{"OPSCNT_LO" , 0, 32, 275, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 275, "RAZ", 1, 1, 0, 0},
|
|
{"BWCTL" , 0, 4, 276, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BWUPD" , 4, 1, 276, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 276, "RAZ", 1, 1, 0, 0},
|
|
{"RODT_LO0" , 0, 4, 277, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_LO1" , 4, 4, 277, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_LO2" , 8, 4, 277, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_LO3" , 12, 4, 277, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI0" , 16, 4, 277, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI1" , 20, 4, 277, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI2" , 24, 4, 277, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI3" , 28, 4, 277, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_32_63" , 32, 32, 277, "RAZ", 1, 1, 0, 0},
|
|
{"WODT_LO0" , 0, 4, 278, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_LO1" , 4, 4, 278, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_LO2" , 8, 4, 278, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_LO3" , 12, 4, 278, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_HI0" , 16, 4, 278, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_HI1" , 20, 4, 278, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_HI2" , 24, 4, 278, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_HI3" , 28, 4, 278, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_32_63" , 32, 32, 278, "RAZ", 1, 1, 0, 0},
|
|
{"NCBI" , 0, 1, 279, "RO", 0, 0, 0ull, 0ull},
|
|
{"LOC" , 1, 1, 279, "RO", 0, 0, 0ull, 0ull},
|
|
{"NCBO_0" , 2, 1, 279, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 279, "RAZ", 1, 1, 0, 0},
|
|
{"ADR_ERR" , 0, 1, 280, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WAIT_ERR" , 1, 1, 280, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 280, "RAZ", 1, 1, 0, 0},
|
|
{"ADR_INT" , 0, 1, 281, "R/W", 0, 1, 0ull, 0},
|
|
{"WAIT_INT" , 1, 1, 281, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 281, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 282, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 3, 5, 282, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 282, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 283, "RAZ", 1, 1, 0, 0},
|
|
{"BASE" , 3, 25, 283, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_30" , 28, 3, 283, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 31, 1, 283, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 283, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 284, "R/W", 1, 1, 0, 0},
|
|
{"BASE" , 0, 16, 285, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 16, 12, 285, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_29" , 28, 2, 285, "RAZ", 1, 1, 0, 0},
|
|
{"ORBIT" , 30, 1, 285, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 31, 1, 285, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 285, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 6, 286, "R/W", 0, 1, 63ull, 0},
|
|
{"CE" , 6, 6, 286, "R/W", 0, 1, 63ull, 0},
|
|
{"OE" , 12, 6, 286, "R/W", 0, 1, 63ull, 0},
|
|
{"WE" , 18, 6, 286, "R/W", 0, 1, 63ull, 0},
|
|
{"RD_HLD" , 24, 6, 286, "R/W", 0, 1, 63ull, 0},
|
|
{"WR_HLD" , 30, 6, 286, "R/W", 0, 1, 63ull, 0},
|
|
{"PAUSE" , 36, 6, 286, "R/W", 0, 1, 63ull, 0},
|
|
{"WAIT" , 42, 6, 286, "R/W", 0, 1, 63ull, 0},
|
|
{"PAGE" , 48, 6, 286, "R/W", 0, 1, 63ull, 0},
|
|
{"RESERVED_54_59" , 54, 6, 286, "RAZ", 1, 1, 0, 0},
|
|
{"PAGES" , 60, 2, 286, "R/W", 0, 1, 0ull, 0},
|
|
{"WAITM" , 62, 1, 286, "R/W", 0, 1, 0ull, 0},
|
|
{"PAGEM" , 63, 1, 286, "R/W", 0, 1, 0ull, 0},
|
|
{"FIF_THR" , 0, 6, 287, "R/W", 0, 0, 26ull, 26ull},
|
|
{"RESERVED_6_7" , 6, 2, 287, "RAZ", 1, 1, 0, 0},
|
|
{"FIF_CNT" , 8, 6, 287, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_63" , 14, 50, 287, "RAZ", 1, 1, 0, 0},
|
|
{"MAN_INFO" , 0, 32, 288, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 288, "RAZ", 1, 1, 0, 0},
|
|
{"MAN_INFO" , 0, 32, 289, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 289, "RAZ", 1, 1, 0, 0},
|
|
{"PP_DIS" , 0, 16, 290, "RO", 1, 1, 0, 0},
|
|
{"CHIP_ID" , 16, 8, 290, "RO", 1, 1, 0, 0},
|
|
{"BIST_DIS" , 24, 1, 290, "RO", 1, 1, 0, 0},
|
|
{"RST_SHT" , 25, 1, 290, "RO", 1, 1, 0, 0},
|
|
{"NOCRYPTO" , 26, 1, 290, "RO", 1, 1, 0, 0},
|
|
{"NOMUL" , 27, 1, 290, "RO", 1, 1, 0, 0},
|
|
{"NODFA_CP2" , 28, 1, 290, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 290, "RAZ", 1, 1, 0, 0},
|
|
{"ICACHE" , 0, 24, 291, "RO", 1, 1, 0, 0},
|
|
{"NODFA_DTE" , 24, 1, 291, "RO", 1, 1, 0, 0},
|
|
{"NOZIP" , 25, 1, 291, "RO", 1, 1, 0, 0},
|
|
{"EFUS_IGN" , 26, 1, 291, "RO", 1, 1, 0, 0},
|
|
{"EFUS_LCK" , 27, 1, 291, "RO", 1, 1, 0, 0},
|
|
{"BAR2_EN" , 28, 1, 291, "RO", 1, 1, 0, 0},
|
|
{"ZIP_CRIP" , 29, 2, 291, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_31_63" , 31, 33, 291, "RAZ", 1, 1, 0, 0},
|
|
{"PROG" , 0, 1, 292, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_1_63" , 1, 63, 292, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 7, 293, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 293, "RAZ", 1, 1, 0, 0},
|
|
{"EFUSE" , 8, 1, 293, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 293, "RAZ", 1, 1, 0, 0},
|
|
{"PEND" , 12, 1, 293, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 293, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 16, 8, 293, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_24_63" , 24, 40, 293, "RAZ", 1, 1, 0, 0},
|
|
{"REPAIR0" , 0, 14, 294, "RO", 0, 0, 0ull, 0ull},
|
|
{"REPAIR1" , 14, 14, 294, "RO", 0, 0, 0ull, 0ull},
|
|
{"REPAIR2" , 28, 14, 294, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_42_63" , 42, 22, 294, "RAZ", 1, 1, 0, 0},
|
|
{"TOO_MANY" , 0, 1, 295, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 295, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 10, 296, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_10_63" , 10, 54, 296, "RAZ", 1, 1, 0, 0},
|
|
{"ST_INT" , 0, 1, 297, "R/W1C", 0, 1, 0ull, 0},
|
|
{"TS_INT" , 1, 1, 297, "R/W1C", 0, 1, 0ull, 0},
|
|
{"CORE_INT" , 2, 1, 297, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_3" , 3, 1, 297, "RAZ", 1, 1, 0, 0},
|
|
{"ST_EN" , 4, 1, 297, "R/W", 0, 1, 0ull, 0},
|
|
{"TS_EN" , 5, 1, 297, "R/W", 0, 1, 0ull, 0},
|
|
{"CORE_EN" , 6, 1, 297, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_7" , 7, 1, 297, "RAZ", 1, 1, 0, 0},
|
|
{"SDA_OVR" , 8, 1, 297, "R/W", 0, 1, 0ull, 0},
|
|
{"SCL_OVR" , 9, 1, 297, "R/W", 0, 1, 0ull, 0},
|
|
{"SDA" , 10, 1, 297, "RO", 1, 1, 0, 0},
|
|
{"SCL" , 11, 1, 297, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_12_63" , 12, 52, 297, "RAZ", 1, 1, 0, 0},
|
|
{"D" , 0, 32, 298, "R/W", 0, 1, 0ull, 0},
|
|
{"EOP_IA" , 32, 3, 298, "R/W", 0, 1, 0ull, 0},
|
|
{"IA" , 35, 5, 298, "R/W", 0, 1, 0ull, 0},
|
|
{"A" , 40, 10, 298, "R/W", 0, 1, 0ull, 0},
|
|
{"SCR" , 50, 2, 298, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 52, 3, 298, "R/W", 0, 1, 0ull, 0},
|
|
{"SOVR" , 55, 1, 298, "R/W", 0, 1, 0ull, 0},
|
|
{"R" , 56, 1, 298, "R/W", 0, 1, 0ull, 0},
|
|
{"OP" , 57, 4, 298, "R/W", 0, 1, 0ull, 0},
|
|
{"EIA" , 61, 1, 298, "R/W", 0, 1, 0ull, 0},
|
|
{"SLONLY" , 62, 1, 298, "R/W", 0, 1, 0ull, 0},
|
|
{"V" , 63, 1, 298, "RC/W", 0, 1, 0ull, 0},
|
|
{"D" , 0, 32, 299, "R/W", 0, 1, 0ull, 0},
|
|
{"IA" , 32, 8, 299, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_40_63" , 40, 24, 299, "RAZ", 1, 1, 0, 0},
|
|
{"D" , 0, 32, 300, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_32_61" , 32, 30, 300, "RAZ", 1, 1, 0, 0},
|
|
{"V" , 62, 2, 300, "RC/W", 0, 1, 0ull, 0},
|
|
{"DLH" , 0, 8, 301, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 301, "RAZ", 1, 1, 0, 0},
|
|
{"DLL" , 0, 8, 302, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 302, "RAZ", 1, 1, 0, 0},
|
|
{"FAR" , 0, 1, 303, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 303, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 304, "WO", 0, 1, 0ull, 0},
|
|
{"RXFR" , 1, 1, 304, "WO", 0, 1, 0ull, 0},
|
|
{"TXFR" , 2, 1, 304, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_3" , 3, 1, 304, "RAZ", 0, 1, 0ull, 0},
|
|
{"TXTRIG" , 4, 2, 304, "WO", 0, 1, 0ull, 0},
|
|
{"RXTRIG" , 6, 2, 304, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 304, "RAZ", 1, 1, 0, 0},
|
|
{"HTX" , 0, 1, 305, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 305, "RAZ", 1, 1, 0, 0},
|
|
{"ERBFI" , 0, 1, 306, "R/W", 0, 1, 0ull, 0},
|
|
{"ETBEI" , 1, 1, 306, "R/W", 0, 1, 0ull, 0},
|
|
{"ELSI" , 2, 1, 306, "R/W", 0, 1, 0ull, 0},
|
|
{"EDSSI" , 3, 1, 306, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_6" , 4, 3, 306, "RAZ", 0, 1, 0ull, 0},
|
|
{"PTIME" , 7, 1, 306, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 306, "RAZ", 1, 1, 0, 0},
|
|
{"IID" , 0, 4, 307, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_4_5" , 4, 2, 307, "RAZ", 0, 1, 0ull, 0},
|
|
{"FEN" , 6, 2, 307, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 307, "RAZ", 1, 1, 0, 0},
|
|
{"CLS" , 0, 2, 308, "R/W", 0, 1, 0ull, 0},
|
|
{"STOP" , 2, 1, 308, "R/W", 0, 1, 0ull, 0},
|
|
{"PEN" , 3, 1, 308, "R/W", 0, 1, 0ull, 0},
|
|
{"EPS" , 4, 1, 308, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_5" , 5, 1, 308, "RAZ", 0, 1, 0ull, 0},
|
|
{"BRK" , 6, 1, 308, "R/W", 0, 1, 0ull, 0},
|
|
{"DLAB" , 7, 1, 308, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 308, "RAZ", 1, 1, 0, 0},
|
|
{"DR" , 0, 1, 309, "RO", 0, 1, 0ull, 0},
|
|
{"OE" , 1, 1, 309, "RC", 0, 1, 0ull, 0},
|
|
{"PE" , 2, 1, 309, "RC", 0, 1, 0ull, 0},
|
|
{"FE" , 3, 1, 309, "RC", 0, 1, 0ull, 0},
|
|
{"BI" , 4, 1, 309, "RC", 0, 1, 0ull, 0},
|
|
{"THRE" , 5, 1, 309, "RO", 0, 1, 1ull, 0},
|
|
{"TEMT" , 6, 1, 309, "RO", 0, 1, 1ull, 0},
|
|
{"FERR" , 7, 1, 309, "RC", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 309, "RAZ", 1, 1, 0, 0},
|
|
{"DTR" , 0, 1, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"RTS" , 1, 1, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT1" , 2, 1, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT2" , 3, 1, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"LOOP" , 4, 1, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"AFCE" , 5, 1, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 310, "RAZ", 0, 1, 0ull, 0},
|
|
{"DCTS" , 0, 1, 311, "RC", 0, 1, 0ull, 0},
|
|
{"DDSR" , 1, 1, 311, "RC", 0, 1, 0ull, 0},
|
|
{"TERI" , 2, 1, 311, "RC", 0, 1, 0ull, 0},
|
|
{"DDCD" , 3, 1, 311, "RC", 0, 1, 0ull, 0},
|
|
{"CTS" , 4, 1, 311, "RO", 1, 1, 0, 0},
|
|
{"DSR" , 5, 1, 311, "RO", 0, 1, 0ull, 0},
|
|
{"RI" , 6, 1, 311, "RO", 0, 1, 0ull, 0},
|
|
{"DCD" , 7, 1, 311, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 311, "RAZ", 1, 1, 0, 0},
|
|
{"RBR" , 0, 8, 312, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 312, "RAZ", 1, 1, 0, 0},
|
|
{"RFL" , 0, 7, 313, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 313, "RAZ", 1, 1, 0, 0},
|
|
{"RFWD" , 0, 8, 314, "WO", 0, 1, 0ull, 0},
|
|
{"RFPE" , 8, 1, 314, "WO", 0, 1, 0ull, 0},
|
|
{"RFFE" , 9, 1, 314, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_10_63" , 10, 54, 314, "RAZ", 1, 1, 0, 0},
|
|
{"SBCR" , 0, 1, 315, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 315, "RAZ", 1, 1, 0, 0},
|
|
{"SCR" , 0, 8, 316, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 316, "RAZ", 1, 1, 0, 0},
|
|
{"SFE" , 0, 1, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 317, "RAZ", 1, 1, 0, 0},
|
|
{"USR" , 0, 1, 318, "WO", 0, 1, 0ull, 0},
|
|
{"SRFR" , 1, 1, 318, "WO", 0, 1, 0ull, 0},
|
|
{"STFR" , 2, 1, 318, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_63" , 3, 61, 318, "RAZ", 1, 1, 0, 0},
|
|
{"SRT" , 0, 2, 319, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 319, "RAZ", 1, 1, 0, 0},
|
|
{"SRTS" , 0, 1, 320, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 320, "RAZ", 1, 1, 0, 0},
|
|
{"STT" , 0, 2, 321, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 321, "RAZ", 1, 1, 0, 0},
|
|
{"TFL" , 0, 7, 322, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 322, "RAZ", 1, 1, 0, 0},
|
|
{"TFR" , 0, 8, 323, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 323, "RAZ", 1, 1, 0, 0},
|
|
{"THR" , 0, 8, 324, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 324, "RAZ", 1, 1, 0, 0},
|
|
{"BUSY" , 0, 1, 325, "RO", 0, 1, 0ull, 0},
|
|
{"TFNF" , 1, 1, 325, "RO", 0, 1, 1ull, 0},
|
|
{"TFE" , 2, 1, 325, "RO", 0, 1, 1ull, 0},
|
|
{"RFNE" , 3, 1, 325, "RO", 0, 1, 0ull, 0},
|
|
{"RFF" , 4, 1, 325, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 325, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 326, "RAZ", 1, 1, 0, 0},
|
|
{"BADDR" , 3, 61, 326, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_0_2" , 0, 3, 327, "RAZ", 1, 1, 0, 0},
|
|
{"BADDR" , 3, 61, 327, "R/W", 0, 1, 0ull, 0},
|
|
{"DPI_BS" , 0, 1, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"PDF_BS" , 1, 1, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"DOB_BS" , 2, 1, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"NUS_BS" , 3, 1, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"POS_BS" , 4, 1, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"POF3_BS" , 5, 1, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"POF2_BS" , 6, 1, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"POF1_BS" , 7, 1, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"POF0_BS" , 8, 1, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"PIG_BS" , 9, 1, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"PGF_BS" , 10, 1, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"RDNL_BS" , 11, 1, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCAD_BS" , 12, 1, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCAC_BS" , 13, 1, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"RDN_BS" , 14, 1, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCN_BS" , 15, 1, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCNC_BS" , 16, 1, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"RDP_BS" , 17, 1, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF_BS" , 18, 1, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSR_BS" , 19, 1, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 328, "RAZ", 1, 1, 0, 0},
|
|
{"BSIZE" , 0, 16, 329, "R/W", 0, 1, 1024ull, 0},
|
|
{"ISIZE" , 16, 7, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_23_63" , 23, 41, 329, "RAZ", 1, 1, 0, 0},
|
|
{"TIMER" , 0, 10, 330, "R/W", 0, 0, 0ull, 50ull},
|
|
{"RESERVED_10_31" , 10, 22, 330, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX_WORD" , 32, 5, 330, "R/W", 0, 0, 2ull, 0ull},
|
|
{"RESERVED_37_39" , 37, 3, 330, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WAIT_COM" , 40, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCI_WDIS" , 41, 1, 330, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INS0_64B" , 42, 1, 330, "R/W", 0, 1, 0ull, 0},
|
|
{"INS1_64B" , 43, 1, 330, "R/W", 0, 1, 0ull, 0},
|
|
{"INS2_64B" , 44, 1, 330, "R/W", 0, 1, 0ull, 0},
|
|
{"INS3_64B" , 45, 1, 330, "R/W", 0, 1, 0ull, 0},
|
|
{"INS0_ENB" , 46, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INS1_ENB" , 47, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INS2_ENB" , 48, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INS3_ENB" , 49, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OUT0_ENB" , 50, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OUT1_ENB" , 51, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OUT2_ENB" , 52, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OUT3_ENB" , 53, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DIS_PNIW" , 54, 1, 330, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CHIP_REV" , 55, 8, 330, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_63_63" , 63, 1, 330, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_SEL" , 0, 16, 331, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 331, "RAZ", 1, 1, 0, 0},
|
|
{"CSIZE" , 0, 14, 332, "R/W", 0, 1, 0ull, 0},
|
|
{"LP_ENB" , 14, 1, 332, "R/W", 0, 0, 0ull, 1ull},
|
|
{"HP_ENB" , 15, 1, 332, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O_MODE" , 16, 1, 332, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O_ES" , 17, 2, 332, "R/W", 0, 1, 0ull, 0},
|
|
{"O_NS" , 19, 1, 332, "R/W", 0, 1, 0ull, 0},
|
|
{"O_RO" , 20, 1, 332, "R/W", 0, 1, 0ull, 0},
|
|
{"O_ADD1" , 21, 1, 332, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA_QUE" , 22, 3, 332, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB_ICHK" , 25, 9, 332, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB_DENB" , 34, 1, 332, "R/W", 0, 0, 0ull, 1ull},
|
|
{"B0_LEND" , 35, 1, 332, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 332, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 32, 333, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 7, 333, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_39_63" , 39, 25, 333, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 334, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 36, 4, 334, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 334, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 32, 335, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 7, 335, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_39_63" , 39, 25, 335, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 336, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 36, 4, 336, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 336, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 16, 337, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 337, "RAZ", 1, 1, 0, 0},
|
|
{"SADDR" , 0, 36, 338, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 338, "RAZ", 1, 1, 0, 0},
|
|
{"ROR" , 0, 1, 339, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR" , 1, 2, 339, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR" , 3, 1, 339, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_CSR" , 4, 1, 339, "R/W", 0, 0, 0ull, 1ull},
|
|
{"D_ROR" , 5, 1, 339, "R/W", 0, 1, 0ull, 0},
|
|
{"D_ESR" , 6, 2, 339, "R/W", 0, 1, 0ull, 0},
|
|
{"D_NSR" , 8, 1, 339, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP_DHI" , 9, 13, 339, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_RR" , 22, 1, 339, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 339, "RAZ", 1, 1, 0, 0},
|
|
{"RML_RTO" , 0, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RML_WTO" , 1, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCI_RSL" , 2, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PO0_2SML" , 3, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PO1_2SML" , 4, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PO2_2SML" , 5, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PO3_2SML" , 6, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I0_RTOUT" , 7, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I1_RTOUT" , 8, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I2_RTOUT" , 9, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I3_RTOUT" , 10, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I0_OVERF" , 11, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I1_OVERF" , 12, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I2_OVERF" , 13, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I3_OVERF" , 14, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P0_RTOUT" , 15, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_RTOUT" , 16, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P2_RTOUT" , 17, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P3_RTOUT" , 18, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P0_PERR" , 19, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_PERR" , 20, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P2_PERR" , 21, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P3_PERR" , 22, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"G0_RTOUT" , 23, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"G1_RTOUT" , 24, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"G2_RTOUT" , 25, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"G3_RTOUT" , 26, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P0_PPERR" , 27, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_PPERR" , 28, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P2_PPERR" , 29, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P3_PPERR" , 30, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P0_PTOUT" , 31, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_PTOUT" , 32, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P2_PTOUT" , 33, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P3_PTOUT" , 34, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I0_PPERR" , 35, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I1_PPERR" , 36, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I2_PPERR" , 37, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I3_PPERR" , 38, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"WIN_RTO" , 39, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P_DPERR" , 40, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 41, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FCR_S_E" , 42, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FCR_A_F" , 43, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCR_S_E" , 44, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCR_A_F" , 45, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q2_S_E" , 46, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q2_A_F" , 47, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q3_S_E" , 48, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q3_A_F" , 49, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"COM_S_E" , 50, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"COM_A_F" , 51, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PNC_S_E" , 52, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PNC_A_F" , 53, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RWX_S_E" , 54, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RDX_S_E" , 55, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCF_P_E" , 56, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCF_P_F" , 57, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PDF_P_E" , 58, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PDF_P_F" , 59, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q1_S_E" , 60, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q1_A_F" , 61, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_62_63" , 62, 2, 340, "RAZ", 1, 1, 0, 0},
|
|
{"RML_RTO" , 0, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RML_WTO" , 1, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCI_RSL" , 2, 1, 341, "RO", 0, 0, 0ull, 0ull},
|
|
{"PO0_2SML" , 3, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PO1_2SML" , 4, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PO2_2SML" , 5, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PO3_2SML" , 6, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I0_RTOUT" , 7, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I1_RTOUT" , 8, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I2_RTOUT" , 9, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I3_RTOUT" , 10, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I0_OVERF" , 11, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I1_OVERF" , 12, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I2_OVERF" , 13, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I3_OVERF" , 14, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P0_RTOUT" , 15, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_RTOUT" , 16, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P2_RTOUT" , 17, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P3_RTOUT" , 18, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P0_PERR" , 19, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_PERR" , 20, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P2_PERR" , 21, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P3_PERR" , 22, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"G0_RTOUT" , 23, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"G1_RTOUT" , 24, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"G2_RTOUT" , 25, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"G3_RTOUT" , 26, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P0_PPERR" , 27, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_PPERR" , 28, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P2_PPERR" , 29, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P3_PPERR" , 30, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P0_PTOUT" , 31, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_PTOUT" , 32, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P2_PTOUT" , 33, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P3_PTOUT" , 34, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I0_PPERR" , 35, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I1_PPERR" , 36, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I2_PPERR" , 37, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I3_PPERR" , 38, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WIN_RTO" , 39, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_DPERR" , 40, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IOBDMA" , 41, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCR_S_E" , 42, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCR_A_F" , 43, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCR_S_E" , 44, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCR_A_F" , 45, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_S_E" , 46, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_A_F" , 47, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_S_E" , 48, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_A_F" , 49, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COM_S_E" , 50, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COM_A_F" , 51, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PNC_S_E" , 52, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PNC_A_F" , 53, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RWX_S_E" , 54, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RDX_S_E" , 55, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCF_P_E" , 56, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCF_P_F" , 57, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PDF_P_E" , 58, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PDF_P_F" , 59, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_S_E" , 60, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_A_F" , 61, 1, 341, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_62_63" , 62, 2, 341, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 16, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 342, "RAZ", 1, 1, 0, 0},
|
|
{"SADDR" , 0, 36, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 343, "RAZ", 1, 1, 0, 0},
|
|
{"BA" , 0, 28, 344, "R/W", 0, 1, 0ull, 0},
|
|
{"ROW" , 28, 1, 344, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR" , 29, 1, 344, "R/W", 0, 1, 0ull, 0},
|
|
{"NSW" , 30, 1, 344, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR" , 31, 1, 344, "R/W", 0, 1, 0ull, 0},
|
|
{"ESW" , 32, 2, 344, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR" , 34, 2, 344, "R/W", 0, 1, 0ull, 0},
|
|
{"NMERGE" , 36, 1, 344, "R/W", 0, 1, 0ull, 0},
|
|
{"SHORTL" , 37, 1, 344, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_38_63" , 38, 26, 344, "RAZ", 1, 1, 0, 0},
|
|
{"INT_VEC" , 0, 64, 345, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 0, 32, 346, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 346, "RAZ", 1, 1, 0, 0},
|
|
{"ROR_SL0" , 0, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR_SL0" , 1, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR_SL0" , 2, 2, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR_SL1" , 4, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR_SL1" , 5, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR_SL1" , 6, 2, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR_SL2" , 8, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR_SL2" , 9, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR_SL2" , 10, 2, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR_SL3" , 12, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR_SL3" , 13, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR_SL3" , 14, 2, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"IPTR_O0" , 16, 1, 347, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IPTR_O1" , 17, 1, 347, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IPTR_O2" , 18, 1, 347, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IPTR_O3" , 19, 1, 347, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_20_23" , 20, 4, 347, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"O0_CSRM" , 24, 1, 347, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O1_CSRM" , 25, 1, 347, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O2_CSRM" , 26, 1, 347, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O3_CSRM" , 27, 1, 347, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O0_RO" , 28, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"O0_NS" , 29, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"O0_ES" , 30, 2, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"O1_RO" , 32, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"O1_NS" , 33, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"O1_ES" , 34, 2, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"O2_RO" , 36, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"O2_NS" , 37, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"O2_ES" , 38, 2, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"O3_RO" , 40, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"O3_NS" , 41, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"O3_ES" , 42, 2, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"P0_BMODE" , 44, 1, 347, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P1_BMODE" , 45, 1, 347, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P2_BMODE" , 46, 1, 347, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P3_BMODE" , 47, 1, 347, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKT_RR" , 48, 1, 347, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 347, "RAZ", 1, 1, 0, 0},
|
|
{"NADDR" , 0, 61, 348, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 61, 2, 348, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_63_63" , 63, 1, 348, "RAZ", 1, 1, 0, 0},
|
|
{"NADDR" , 0, 61, 349, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 61, 3, 349, "RO", 0, 0, 0ull, 0ull},
|
|
{"AVAIL" , 0, 32, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 6, 350, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 350, "RAZ", 1, 1, 0, 0},
|
|
{"AVAIL" , 0, 32, 351, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 5, 351, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 351, "RAZ", 1, 1, 0, 0},
|
|
{"RD_BRST" , 0, 7, 352, "R/W", 0, 0, 17ull, 64ull},
|
|
{"WR_BRST" , 7, 7, 352, "R/W", 0, 0, 16ull, 64ull},
|
|
{"RESERVED_14_63" , 14, 50, 352, "RAZ", 1, 1, 0, 0},
|
|
{"PARK_DEV" , 0, 3, 353, "R/W", 0, 1, 0ull, 0},
|
|
{"PARK_MOD" , 3, 1, 353, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 4, 1, 353, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 353, "RAZ", 1, 1, 0, 0},
|
|
{"CMD_SIZE" , 0, 11, 354, "R/W", 0, 0, 9ull, 9ull},
|
|
{"RESERVED_11_63" , 11, 53, 354, "RAZ", 1, 1, 0, 0},
|
|
{"RSV_A" , 0, 6, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"SKP_LEN" , 6, 7, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_B" , 13, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"PAR_MODE" , 14, 2, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_C" , 16, 5, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_IHDR" , 21, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_D" , 22, 6, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"RSKP_LEN" , 28, 7, 355, "R/W", 0, 1, 8ull, 0},
|
|
{"RSV_E" , 35, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"RPARMODE" , 36, 2, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_F" , 38, 5, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP" , 43, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 355, "RAZ", 1, 1, 0, 0},
|
|
{"RSV_A" , 0, 6, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"SKP_LEN" , 6, 7, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_B" , 13, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"PAR_MODE" , 14, 2, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_C" , 16, 5, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_IHDR" , 21, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_D" , 22, 6, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RSKP_LEN" , 28, 7, 356, "R/W", 0, 1, 8ull, 0},
|
|
{"RSV_E" , 35, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RPARMODE" , 36, 2, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_F" , 38, 5, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP" , 43, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 356, "RAZ", 1, 1, 0, 0},
|
|
{"RSV_A" , 0, 6, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"SKP_LEN" , 6, 7, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_B" , 13, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"PAR_MODE" , 14, 2, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_C" , 16, 5, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_IHDR" , 21, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_D" , 22, 6, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"RSKP_LEN" , 28, 7, 357, "R/W", 0, 1, 8ull, 0},
|
|
{"RSV_E" , 35, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"RPARMODE" , 36, 2, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_F" , 38, 5, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP" , 43, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 357, "RAZ", 1, 1, 0, 0},
|
|
{"RSV_A" , 0, 6, 358, "R/W", 0, 1, 0ull, 0},
|
|
{"SKP_LEN" , 6, 7, 358, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_B" , 13, 1, 358, "R/W", 0, 1, 0ull, 0},
|
|
{"PAR_MODE" , 14, 2, 358, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_C" , 16, 5, 358, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_IHDR" , 21, 1, 358, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_D" , 22, 6, 358, "R/W", 0, 1, 0ull, 0},
|
|
{"RSKP_LEN" , 28, 7, 358, "R/W", 0, 1, 8ull, 0},
|
|
{"RSV_E" , 35, 1, 358, "R/W", 0, 1, 0ull, 0},
|
|
{"RPARMODE" , 36, 2, 358, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_F" , 38, 5, 358, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP" , 43, 1, 358, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 358, "RAZ", 1, 1, 0, 0},
|
|
{"ENB" , 0, 4, 359, "R/W", 0, 0, 15ull, 15ull},
|
|
{"BP_ON" , 4, 4, 359, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 359, "RAZ", 1, 1, 0, 0},
|
|
{"MIO" , 0, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX0" , 1, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX1" , 2, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPI" , 3, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"KEY" , 4, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPA" , 5, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"DFA" , 6, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"ZIP" , 7, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_8" , 8, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD" , 9, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 10, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"TIM" , 11, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"POW" , 12, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_13" , 13, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_14" , 14, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_15" , 15, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"L2C" , 16, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"LMC" , 17, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"SPX0" , 18, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"SPX1" , 19, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"PIP" , 20, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_21" , 21, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASX0" , 22, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASX1" , 23, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_24" , 24, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_25" , 25, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_26" , 26, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_27" , 27, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_28" , 28, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_29" , 29, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"IOB" , 30, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_31" , 31, 1, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 360, "RAZ", 1, 1, 0, 0},
|
|
{"SIZE" , 0, 32, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 361, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 32, 362, "R/W", 0, 0, 0ull, 131072ull},
|
|
{"RESERVED_32_63" , 32, 32, 362, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR_V" , 0, 1, 363, "R/W", 0, 1, 0ull, 0},
|
|
{"END_SWP" , 1, 2, 363, "R/W", 0, 1, 0ull, 0},
|
|
{"CA" , 3, 1, 363, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDR_IDX" , 4, 14, 363, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_31" , 18, 14, 363, "RAZ", 1, 1, 0, 0},
|
|
{"VENDID" , 0, 16, 364, "RO", 0, 0, 6013ull, 6013ull},
|
|
{"DEVID" , 16, 16, 364, "RO", 0, 0, 5ull, 5ull},
|
|
{"ISAE" , 0, 1, 365, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSAE" , 1, 1, 365, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ME" , 2, 1, 365, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SCSE" , 3, 1, 365, "RO", 0, 0, 0ull, 0ull},
|
|
{"MWICE" , 4, 1, 365, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VPS" , 5, 1, 365, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEE" , 6, 1, 365, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ADS" , 7, 1, 365, "RO", 0, 0, 0ull, 0ull},
|
|
{"SEE" , 8, 1, 365, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FBBE" , 9, 1, 365, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I_DIS" , 10, 1, 365, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_18" , 11, 8, 365, "RAZ", 1, 1, 0, 0},
|
|
{"I_STAT" , 19, 1, 365, "RO", 0, 0, 0ull, 0ull},
|
|
{"CLE" , 20, 1, 365, "RO", 0, 0, 1ull, 1ull},
|
|
{"M66" , 21, 1, 365, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_22_22" , 22, 1, 365, "RAZ", 1, 1, 0, 0},
|
|
{"FBB" , 23, 1, 365, "RO", 0, 1, 1ull, 0},
|
|
{"MDPE" , 24, 1, 365, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DEVT" , 25, 2, 365, "RO", 0, 0, 1ull, 1ull},
|
|
{"STA" , 27, 1, 365, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTA" , 28, 1, 365, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RMA" , 29, 1, 365, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SSE" , 30, 1, 365, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPE" , 31, 1, 365, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RID" , 0, 8, 366, "RO", 0, 0, 3ull, 3ull},
|
|
{"CC" , 8, 24, 366, "RO", 0, 0, 733184ull, 733184ull},
|
|
{"CLS" , 0, 8, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"LT" , 8, 8, 367, "R/W", 0, 0, 0ull, 64ull},
|
|
{"HT" , 16, 8, 367, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCOD" , 24, 4, 367, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_29" , 28, 2, 367, "RAZ", 1, 1, 0, 0},
|
|
{"BRB" , 30, 1, 367, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BCAP" , 31, 1, 367, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSPC" , 0, 1, 368, "RO", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 368, "RO", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 368, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBASEZ" , 4, 8, 368, "RO", 0, 0, 0ull, 0ull},
|
|
{"LBASE" , 12, 20, 368, "R/W", 0, 1, 0ull, 0},
|
|
{"HBASE" , 0, 32, 369, "R/W", 0, 1, 0ull, 0},
|
|
{"MSPC" , 0, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 370, "RO", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 370, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBASEZ" , 4, 23, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"LBASE" , 27, 5, 370, "R/W", 0, 1, 0ull, 0},
|
|
{"HBASE" , 0, 32, 371, "R/W", 0, 1, 0ull, 0},
|
|
{"MSPC" , 0, 1, 372, "RO", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 372, "RO", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 372, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBASEZ" , 4, 28, 372, "RO", 0, 0, 0ull, 0ull},
|
|
{"HBASEZ" , 0, 7, 373, "RO", 0, 0, 0ull, 0ull},
|
|
{"HBASE" , 7, 25, 373, "R/W", 0, 1, 0ull, 0},
|
|
{"CISP" , 0, 32, 374, "RO", 0, 0, 0ull, 0ull},
|
|
{"SSVID" , 0, 16, 375, "RO", 0, 0, 6013ull, 6013ull},
|
|
{"SSID" , 16, 16, 375, "RO", 0, 0, 1ull, 1ull},
|
|
{"ERBAR_EN" , 0, 1, 376, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_10" , 1, 10, 376, "RAZ", 1, 1, 0, 0},
|
|
{"ERBARZ" , 11, 5, 376, "RO", 0, 0, 0ull, 0ull},
|
|
{"ERBAR" , 16, 16, 376, "R/W", 0, 1, 0ull, 0},
|
|
{"CP" , 0, 8, 377, "RO", 0, 0, 224ull, 224ull},
|
|
{"RESERVED_8_31" , 8, 24, 377, "RAZ", 1, 1, 0, 0},
|
|
{"IL" , 0, 8, 378, "R/W", 0, 1, 0ull, 0},
|
|
{"INTA" , 8, 8, 378, "RO", 0, 0, 1ull, 1ull},
|
|
{"MG" , 16, 8, 378, "RO", 0, 0, 64ull, 64ull},
|
|
{"ML" , 24, 8, 378, "RO", 0, 0, 64ull, 64ull},
|
|
{"MLTD" , 0, 1, 379, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TSWC" , 1, 1, 379, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 379, "RAZ", 1, 1, 0, 0},
|
|
{"DPPMR" , 3, 1, 379, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PBE" , 4, 12, 379, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TILT" , 16, 4, 379, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TSLTE" , 20, 3, 379, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TMAE" , 23, 1, 379, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWTAE" , 24, 1, 379, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWSEN" , 25, 1, 379, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWSEI" , 26, 1, 379, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRTAE" , 27, 1, 379, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRDRS" , 28, 1, 379, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RDSATI" , 29, 1, 379, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRDARD" , 30, 1, 379, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TRDNPR" , 31, 1, 379, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TSCME" , 0, 32, 380, "R/W1C", 0, 1, 0ull, 0},
|
|
{"TDSRPS" , 0, 32, 381, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TDOMC" , 0, 5, 382, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TIDOMC" , 5, 1, 382, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_6" , 6, 1, 382, "RAZ", 1, 1, 0, 0},
|
|
{"TIBDE" , 7, 1, 382, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIBCD" , 8, 1, 382, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_10" , 9, 2, 382, "RAZ", 1, 1, 0, 0},
|
|
{"TMAPES" , 11, 1, 382, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TMDPES" , 12, 1, 382, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TMSE" , 13, 1, 382, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TMEI" , 14, 1, 382, "RO", 0, 0, 0ull, 0ull},
|
|
{"TECI" , 15, 1, 382, "RO", 0, 0, 0ull, 0ull},
|
|
{"TMES" , 16, 8, 382, "RO", 0, 0, 0ull, 0ull},
|
|
{"MDRRMC" , 24, 3, 382, "R/W", 0, 0, 2ull, 2ull},
|
|
{"MDRIMC" , 27, 1, 382, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MDRE" , 28, 1, 382, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MDWE" , 29, 1, 382, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRBCI" , 30, 1, 382, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRBCM" , 31, 1, 382, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MDSP" , 0, 32, 383, "R/W1C", 0, 1, 0ull, 0},
|
|
{"SCMRE" , 0, 32, 384, "R/W1C", 0, 1, 0ull, 0},
|
|
{"MTTV" , 0, 8, 385, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRV" , 8, 8, 385, "R/W", 0, 0, 0ull, 255ull},
|
|
{"MTTA" , 16, 1, 385, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRA" , 17, 1, 385, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FLUSH" , 18, 1, 385, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_19_24" , 19, 6, 385, "RAZ", 1, 1, 0, 0},
|
|
{"MAC" , 25, 7, 385, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PXCID" , 0, 8, 386, "RO", 0, 0, 7ull, 7ull},
|
|
{"NCP" , 8, 8, 386, "RO", 0, 0, 232ull, 232ull},
|
|
{"DPERE" , 16, 1, 386, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROE" , 17, 1, 386, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MMBC" , 18, 2, 386, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MOST" , 20, 3, 386, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_23_31" , 23, 9, 386, "RAZ", 1, 1, 0, 0},
|
|
{"FN" , 0, 3, 387, "RO", 0, 0, 0ull, 0ull},
|
|
{"DN" , 3, 5, 387, "RO", 0, 0, 31ull, 31ull},
|
|
{"BN" , 8, 8, 387, "RO", 0, 1, 17ull, 0},
|
|
{"W64" , 16, 1, 387, "RO", 0, 0, 1ull, 1ull},
|
|
{"M133" , 17, 1, 387, "RO", 0, 0, 1ull, 1ull},
|
|
{"SCD" , 18, 1, 387, "R/W1C", 0, 1, 0ull, 0},
|
|
{"USC" , 19, 1, 387, "R/W1C", 0, 1, 0ull, 0},
|
|
{"DC" , 20, 1, 387, "RO", 0, 0, 0ull, 0ull},
|
|
{"MMRBCD" , 21, 2, 387, "RO", 0, 0, 2ull, 2ull},
|
|
{"MOSTD" , 23, 3, 387, "RO", 0, 0, 3ull, 3ull},
|
|
{"MCRSD" , 26, 3, 387, "RO", 0, 0, 7ull, 7ull},
|
|
{"SCEMR" , 29, 1, 387, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_30_31" , 30, 2, 387, "RAZ", 1, 1, 0, 0},
|
|
{"PMCID" , 0, 8, 388, "RO", 0, 0, 1ull, 1ull},
|
|
{"NCP" , 8, 8, 388, "RO", 0, 0, 240ull, 240ull},
|
|
{"PCIMIV" , 16, 3, 388, "RO", 0, 0, 2ull, 2ull},
|
|
{"PMEC" , 19, 1, 388, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 388, "RAZ", 1, 1, 0, 0},
|
|
{"DSI" , 21, 1, 388, "RO", 0, 0, 0ull, 0ull},
|
|
{"AUXC" , 22, 3, 388, "RO", 0, 0, 0ull, 0ull},
|
|
{"D1S" , 25, 1, 388, "RO", 0, 0, 0ull, 0ull},
|
|
{"D2S" , 26, 1, 388, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMES" , 27, 5, 388, "RO", 0, 0, 0ull, 0ull},
|
|
{"PS" , 0, 2, 389, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_7" , 2, 6, 389, "RAZ", 1, 1, 0, 0},
|
|
{"PMEENS" , 8, 1, 389, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMDS" , 9, 4, 389, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMEDSIA" , 13, 2, 389, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMESS" , 15, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_21" , 16, 6, 389, "RAZ", 1, 1, 0, 0},
|
|
{"BD3H" , 22, 1, 389, "RO", 0, 0, 0ull, 0ull},
|
|
{"BPCCEN" , 23, 1, 389, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMDIA" , 24, 8, 389, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSICID" , 0, 8, 390, "RO", 0, 0, 5ull, 5ull},
|
|
{"NCP" , 8, 8, 390, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSIEN" , 16, 1, 390, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MMC" , 17, 3, 390, "RO", 0, 0, 0ull, 0ull},
|
|
{"MME" , 20, 3, 390, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M64" , 23, 1, 390, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_24_31" , 24, 8, 390, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 391, "RAZ", 1, 1, 0, 0},
|
|
{"MSI31T2" , 2, 30, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"MSI" , 0, 32, 392, "R/W", 0, 1, 0ull, 0},
|
|
{"MSIMD" , 0, 16, 393, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_31" , 16, 16, 393, "RAZ", 1, 1, 0, 0},
|
|
{"BAR2_CAX" , 0, 1, 394, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAR2_ESX" , 1, 2, 394, "R/W", 0, 1, 0ull, 0},
|
|
{"BAR2_ENB" , 3, 1, 394, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TSR_HWM" , 4, 3, 394, "R/W", 0, 1, 1ull, 0},
|
|
{"PMO_FPC" , 7, 3, 394, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMO_AMOD" , 10, 1, 394, "R/W", 0, 0, 0ull, 0ull},
|
|
{"B12_BIST" , 11, 1, 394, "RO", 0, 0, 0ull, 0ull},
|
|
{"AP_64AD" , 12, 1, 394, "RO", 1, 1, 0, 0},
|
|
{"AP_PCIX" , 13, 1, 394, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_14_14" , 14, 1, 394, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EN_WFILT" , 15, 1, 394, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SCM" , 16, 1, 394, "RO", 0, 1, 0ull, 0},
|
|
{"SCMTYP" , 17, 1, 394, "RO", 0, 1, 0ull, 0},
|
|
{"BAR2PRES" , 18, 1, 394, "R/W", 1, 1, 0, 0},
|
|
{"ERST_N" , 19, 1, 394, "RO", 0, 0, 1ull, 1ull},
|
|
{"BB0" , 20, 1, 394, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB1" , 21, 1, 394, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB_ES" , 22, 2, 394, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB_CA" , 24, 1, 394, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB1_SIZ" , 25, 1, 394, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB1_HOLE" , 26, 3, 394, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_31" , 29, 3, 394, "RAZ", 1, 1, 0, 0},
|
|
{"INC_VAL" , 0, 16, 395, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_31" , 16, 16, 395, "RAZ", 1, 1, 0, 0},
|
|
{"DMA_CNT" , 0, 32, 396, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKT_CNT" , 0, 32, 397, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA_TIME" , 0, 32, 398, "R/W", 0, 1, 0ull, 0},
|
|
{"ICNT" , 0, 32, 399, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ITR_WABT" , 0, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_WABT" , 1, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_WTTO" , 2, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"ITR_ABT" , 3, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_ABT" , 4, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_TTO" , 5, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSI_PER" , 6, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSI_TABT" , 7, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSI_MABT" , 8, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSC_MSG" , 9, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"ITSR_ABT" , 10, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"ISERR" , 11, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"IAPERR" , 12, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"IDPERR" , 13, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RWR" , 14, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RRD" , 15, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"IRSL_INT" , 16, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"IPCNT0" , 17, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"IPCNT1" , 18, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"IPCNT2" , 19, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"IPCNT3" , 20, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"IPTIME0" , 21, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"IPTIME1" , 22, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"IPTIME2" , 23, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"IPTIME3" , 24, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"IDCNT0" , 25, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"IDCNT1" , 26, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"IDTIME0" , 27, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"IDTIME1" , 28, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA0_FI" , 29, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA1_FI" , 30, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"WIN_WR" , 31, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_WR" , 32, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RD" , 33, 1, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_34_63" , 34, 30, 400, "RAZ", 1, 1, 0, 0},
|
|
{"RTR_WABT" , 0, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_WABT" , 1, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_WTTO" , 2, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RTR_ABT" , 3, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_ABT" , 4, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_TTO" , 5, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSI_PER" , 6, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSI_TABT" , 7, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSI_MABT" , 8, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSC_MSG" , 9, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RTSR_ABT" , 10, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RSERR" , 11, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RAPERR" , 12, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RDPERR" , 13, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RWR" , 14, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RRD" , 15, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RRSL_INT" , 16, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RPCNT0" , 17, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RPCNT1" , 18, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RPCNT2" , 19, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RPCNT3" , 20, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RPTIME0" , 21, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RPTIME1" , 22, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RPTIME2" , 23, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RPTIME3" , 24, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RDCNT0" , 25, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RDCNT1" , 26, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RDTIME0" , 27, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RDTIME1" , 28, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA0_FI" , 29, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA1_FI" , 30, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"WIN_WR" , 31, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_WR" , 32, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RD" , 33, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_34_63" , 34, 30, 401, "RAZ", 1, 1, 0, 0},
|
|
{"TR_WABT" , 0, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WABT" , 1, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WTTO" , 2, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TR_ABT" , 3, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_ABT" , 4, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_TTO" , 5, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_PER" , 6, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_TABT" , 7, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_MABT" , 8, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSC_MSG" , 9, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TSR_ABT" , 10, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SERR" , 11, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"APERR" , 12, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPERR" , 13, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RWR" , 14, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RRD" , 15, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSL_INT" , 16, 1, 402, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCNT0" , 17, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT1" , 18, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT2" , 19, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT3" , 20, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME0" , 21, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME1" , 22, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME2" , 23, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME3" , 24, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT0" , 25, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT1" , 26, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME0" , 27, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME1" , 28, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA0_FI" , 29, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1_FI" , 30, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WIN_WR" , 31, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_WR" , 32, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RD" , 33, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 402, "RAZ", 1, 1, 0, 0},
|
|
{"TR_WABT" , 0, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WABT" , 1, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WTTO" , 2, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TR_ABT" , 3, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_ABT" , 4, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_TTO" , 5, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_PER" , 6, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_TABT" , 7, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_MABT" , 8, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSC_MSG" , 9, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TSR_ABT" , 10, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SERR" , 11, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"APERR" , 12, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPERR" , 13, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RWR" , 14, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RRD" , 15, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSL_INT" , 16, 1, 403, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCNT0" , 17, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT1" , 18, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT2" , 19, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT3" , 20, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME0" , 21, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME1" , 22, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME2" , 23, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME3" , 24, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT0" , 25, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT1" , 26, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME0" , 27, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME1" , 28, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA0_FI" , 29, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1_FI" , 30, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WIN_WR" , 31, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_WR" , 32, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RD" , 33, 1, 403, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 403, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 0, 6, 404, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_31" , 6, 26, 404, "R/W", 1, 1, 0, 0},
|
|
{"PTR_CNT" , 0, 16, 405, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_CNT" , 16, 16, 405, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_CNT" , 0, 32, 406, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_CNT" , 0, 32, 407, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_TIME" , 0, 32, 408, "R/W", 0, 1, 0ull, 0},
|
|
{"PREFETCH" , 0, 3, 409, "R/W", 0, 0, 0ull, 2ull},
|
|
{"MIN_DATA" , 3, 6, 409, "R/W", 0, 0, 0ull, 4ull},
|
|
{"RESERVED_9_31" , 9, 23, 409, "RAZ", 1, 1, 0, 0},
|
|
{"PREFETCH" , 0, 3, 410, "R/W", 0, 0, 0ull, 3ull},
|
|
{"MIN_DATA" , 3, 6, 410, "R/W", 0, 0, 0ull, 6ull},
|
|
{"RESERVED_9_31" , 9, 23, 410, "RAZ", 1, 1, 0, 0},
|
|
{"PREFETCH" , 0, 3, 411, "R/W", 0, 0, 0ull, 3ull},
|
|
{"MIN_DATA" , 3, 6, 411, "R/W", 0, 0, 0ull, 6ull},
|
|
{"RESERVED_9_31" , 9, 23, 411, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 31, 412, "R/W", 0, 0, 10000ull, 10000ull},
|
|
{"ENB" , 31, 1, 412, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_32_63" , 32, 32, 412, "RAZ", 1, 1, 0, 0},
|
|
{"SCM" , 0, 32, 413, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 413, "RAZ", 1, 1, 0, 0},
|
|
{"TSR" , 0, 36, 414, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 414, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 415, "RAZ", 1, 1, 0, 0},
|
|
{"RD_ADDR" , 3, 45, 415, "R/W", 0, 1, 0ull, 0},
|
|
{"IOBIT" , 48, 1, 415, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 415, "RAZ", 1, 1, 0, 0},
|
|
{"RD_DATA" , 0, 64, 416, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_0_2" , 0, 3, 417, "RAZ", 1, 1, 0, 0},
|
|
{"WR_ADDR" , 3, 45, 417, "R/W", 0, 1, 0ull, 0},
|
|
{"IOBIT" , 48, 1, 417, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 417, "RAZ", 1, 1, 0, 0},
|
|
{"WR_DATA" , 0, 64, 418, "R/W", 0, 1, 0ull, 0},
|
|
{"WR_MASK" , 0, 8, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 419, "RAZ", 1, 1, 0, 0},
|
|
{"LOWATER" , 0, 5, 420, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_5_7" , 5, 3, 420, "RAZ", 0, 1, 0ull, 0},
|
|
{"HIWATER" , 8, 5, 420, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_13_62" , 13, 50, 420, "RAZ", 0, 1, 0ull, 0},
|
|
{"BCKPRS" , 63, 1, 420, "RO", 0, 0, 0ull, 0ull},
|
|
{"BIST" , 0, 18, 421, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 421, "RAZ", 1, 1, 0, 0},
|
|
{"REFLECT" , 0, 1, 422, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INVRES" , 1, 1, 422, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 422, "RAZ", 1, 1, 0, 0},
|
|
{"IV" , 0, 32, 423, "R/W", 0, 0, 1185899593ull, 1185899593ull},
|
|
{"RESERVED_32_63" , 32, 32, 423, "RAZ", 1, 1, 0, 0},
|
|
{"DPRT" , 0, 16, 424, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UDP" , 16, 1, 424, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP" , 17, 1, 424, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 424, "RAZ", 1, 1, 0, 0},
|
|
{"NIP_SHF" , 0, 3, 425, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_7" , 3, 5, 425, "RAZ", 1, 1, 0, 0},
|
|
{"RAW_SHF" , 8, 3, 425, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_15" , 11, 5, 425, "RAZ", 1, 1, 0, 0},
|
|
{"MAX_L2" , 16, 1, 425, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_UDP" , 17, 1, 425, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TAG_SYN" , 18, 1, 425, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 425, "RAZ", 1, 1, 0, 0},
|
|
{"IP_CHK" , 0, 1, 426, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP_MAL" , 1, 1, 426, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP_HOP" , 2, 1, 426, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP4_OPTS" , 3, 1, 426, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP6_EEXT" , 4, 2, 426, "R/W", 0, 0, 1ull, 3ull},
|
|
{"RESERVED_6_7" , 6, 2, 426, "RAZ", 0, 1, 0ull, 0},
|
|
{"L4_MAL" , 8, 1, 426, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_PRT" , 9, 1, 426, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_CHK" , 10, 1, 426, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_LEN" , 11, 1, 426, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TCP_FLAG" , 12, 1, 426, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L2_MAL" , 13, 1, 426, "R/W", 0, 0, 1ull, 1ull},
|
|
{"VS_QOS" , 14, 1, 426, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VS_WQE" , 15, 1, 426, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IGNRS" , 16, 1, 426, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 426, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PKTDRP" , 0, 1, 427, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CRCERR" , 1, 1, 427, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BCKPRS" , 2, 1, 427, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 3, 1, 427, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BADTAG" , 4, 1, 427, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPRUNT" , 5, 1, 427, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TODOOVR" , 6, 1, 427, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FEPERR" , 7, 1, 427, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BEPERR" , 8, 1, 427, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 427, "RAZ", 1, 1, 0, 0},
|
|
{"PKTDRP" , 0, 1, 428, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CRCERR" , 1, 1, 428, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BCKPRS" , 2, 1, 428, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 3, 1, 428, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BADTAG" , 4, 1, 428, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPRUNT" , 5, 1, 428, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TODOOVR" , 6, 1, 428, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FEPERR" , 7, 1, 428, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BEPERR" , 8, 1, 428, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 428, "RAZ", 1, 1, 0, 0},
|
|
{"OFFSET" , 0, 3, 429, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 429, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP" , 0, 7, 430, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 430, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 8, 2, 430, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_11" , 10, 2, 430, "RAZ", 1, 1, 0, 0},
|
|
{"CRC_EN" , 12, 1, 430, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_13_15" , 13, 3, 430, "RAZ", 1, 1, 0, 0},
|
|
{"QOS_VLAN" , 16, 1, 430, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS_DIFF" , 17, 1, 430, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_19" , 18, 2, 430, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"QOS_WAT" , 20, 4, 430, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS" , 24, 3, 430, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 430, "RAZ", 1, 1, 0, 0},
|
|
{"GRP_WAT" , 28, 4, 430, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INST_HDR" , 32, 1, 430, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DYN_RS" , 33, 1, 430, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TAG_INC" , 34, 2, 430, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RAWDRP" , 36, 1, 430, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 430, "RAZ", 1, 1, 0, 0},
|
|
{"GRP" , 0, 4, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NON_TAG_TYPE" , 4, 2, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_TAG_TYPE" , 6, 2, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_TAG_TYPE" , 8, 2, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP4_TAG_TYPE" , 10, 2, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP6_TAG_TYPE" , 12, 2, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_SRC_FLAG" , 14, 1, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_SRC_FLAG" , 15, 1, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_DST_FLAG" , 16, 1, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_DST_FLAG" , 17, 1, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_PCTL_FLAG" , 18, 1, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_NXTH_FLAG" , 19, 1, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_SPRT_FLAG" , 20, 1, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_SPRT_FLAG" , 21, 1, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_DPRT_FLAG" , 22, 1, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_DPRT_FLAG" , 23, 1, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_PRT_FLAG" , 24, 1, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_VLAN" , 25, 1, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_VS" , 26, 2, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TAG_MODE" , 28, 2, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_30" , 30, 1, 431, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"GRPTAG" , 31, 1, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAGMASK" , 32, 4, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAGBASE" , 36, 4, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 431, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 0, 3, 432, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 432, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 0, 3, 433, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 433, "RAZ", 1, 1, 0, 0},
|
|
{"MATCH_VALUE" , 0, 16, 434, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MATCH_TYPE" , 16, 2, 434, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_19" , 18, 2, 434, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 20, 3, 434, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 434, "RAZ", 1, 1, 0, 0},
|
|
{"GRP" , 24, 4, 434, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_31" , 28, 4, 434, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 32, 16, 434, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 434, "RAZ", 1, 1, 0, 0},
|
|
{"WORD" , 0, 56, 435, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 435, "RAZ", 1, 1, 0, 0},
|
|
{"RST" , 0, 1, 436, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 436, "RAZ", 1, 1, 0, 0},
|
|
{"DRP_OCTS" , 0, 32, 437, "R/W", 0, 1, 0ull, 0},
|
|
{"DRP_PKTS" , 32, 32, 437, "R/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 438, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 438, "RAZ", 1, 1, 0, 0},
|
|
{"RAW" , 0, 32, 439, "R/W", 0, 1, 0ull, 0},
|
|
{"PKTS" , 32, 32, 439, "R/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 0, 32, 440, "R/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 32, 32, 440, "R/W", 0, 1, 0ull, 0},
|
|
{"H64" , 0, 32, 441, "R/W", 0, 1, 0ull, 0},
|
|
{"H65TO127" , 32, 32, 441, "R/W", 0, 1, 0ull, 0},
|
|
{"H128TO255" , 0, 32, 442, "R/W", 0, 1, 0ull, 0},
|
|
{"H256TO511" , 32, 32, 442, "R/W", 0, 1, 0ull, 0},
|
|
{"H512TO1023" , 0, 32, 443, "R/W", 0, 1, 0ull, 0},
|
|
{"H1024TO1518" , 32, 32, 443, "R/W", 0, 1, 0ull, 0},
|
|
{"H1519" , 0, 32, 444, "R/W", 0, 1, 0ull, 0},
|
|
{"FCS" , 32, 32, 444, "R/W", 0, 1, 0ull, 0},
|
|
{"UNDERSZ" , 0, 32, 445, "R/W", 0, 1, 0ull, 0},
|
|
{"FRAG" , 32, 32, 445, "R/W", 0, 1, 0ull, 0},
|
|
{"OVERSZ" , 0, 32, 446, "R/W", 0, 1, 0ull, 0},
|
|
{"JABBER" , 32, 32, 446, "R/W", 0, 1, 0ull, 0},
|
|
{"RDCLR" , 0, 1, 447, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 447, "RAZ", 1, 1, 0, 0},
|
|
{"ERRS" , 0, 16, 448, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 448, "RAZ", 1, 1, 0, 0},
|
|
{"OCTS" , 0, 48, 449, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 449, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 450, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 450, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 8, 451, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 451, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 0, 16, 452, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 452, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 16, 453, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DST" , 16, 16, 453, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 453, "RAZ", 1, 1, 0, 0},
|
|
{"ENTRY" , 0, 62, 454, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_62_62" , 62, 1, 454, "RAZ", 1, 1, 0, 0},
|
|
{"VAL" , 63, 1, 454, "RO", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 32, 455, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 455, "RAZ", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 48, 456, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 456, "RAZ", 1, 1, 0, 0},
|
|
{"SIZE" , 0, 16, 457, "RO", 1, 0, 0, 0ull},
|
|
{"SEGS" , 16, 6, 457, "RO", 1, 0, 0, 0ull},
|
|
{"CMD" , 22, 14, 457, "RO", 1, 0, 0, 0ull},
|
|
{"FAU" , 36, 28, 457, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 458, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 458, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 458, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 458, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 458, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 16, 459, "RO", 1, 0, 0, 0ull},
|
|
{"SEGS" , 16, 6, 459, "RO", 1, 0, 0, 0ull},
|
|
{"CMD" , 22, 14, 459, "RO", 1, 0, 0, 0ull},
|
|
{"FAU" , 36, 28, 459, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 460, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 460, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 460, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 460, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 460, "RO", 1, 0, 0, 0ull},
|
|
{"DATA" , 0, 64, 461, "RO", 1, 0, 0, 0ull},
|
|
{"WIDX2" , 0, 17, 462, "RO", 1, 0, 0, 0ull},
|
|
{"RIDX2" , 17, 17, 462, "RO", 1, 0, 0, 0ull},
|
|
{"WIDX" , 34, 17, 462, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_51_63" , 51, 13, 462, "RAZ", 1, 0, 0, 0ull},
|
|
{"RIDX" , 0, 17, 463, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 463, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 464, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 464, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 464, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 464, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 464, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 465, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 465, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 465, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 465, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 465, "RO", 1, 0, 0, 0ull},
|
|
{"DATA" , 0, 64, 466, "RO", 1, 0, 0, 0ull},
|
|
{"MAJOR" , 0, 4, 467, "RO", 1, 0, 0, 0ull},
|
|
{"MINOR" , 4, 2, 467, "RO", 1, 0, 0, 0ull},
|
|
{"WAIT" , 6, 1, 467, "RO", 1, 0, 0, 0ull},
|
|
{"QID_BASE" , 7, 7, 467, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFF" , 14, 3, 467, "RO", 1, 0, 0, 0ull},
|
|
{"QCB_RIDX" , 17, 5, 467, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 22, 3, 467, "RO", 1, 0, 0, 0ull},
|
|
{"ACTIVE" , 25, 1, 467, "RO", 1, 0, 0, 0ull},
|
|
{"CHK_MODE" , 26, 1, 467, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 467, "RAZ", 1, 0, 0, 0ull},
|
|
{"CBUF_FRE" , 28, 1, 467, "RO", 1, 0, 0, 0ull},
|
|
{"XFER_DWR" , 29, 1, 467, "RO", 1, 0, 0, 0ull},
|
|
{"XFER_WOR" , 30, 1, 467, "RO", 1, 0, 0, 0ull},
|
|
{"UID" , 31, 1, 467, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_SIZ" , 32, 16, 467, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_CNT" , 48, 13, 467, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_LEN" , 61, 1, 467, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_SOP" , 62, 1, 467, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_MOD" , 63, 1, 467, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_MOD" , 0, 2, 468, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_UID" , 2, 1, 468, "RO", 1, 0, 0, 0ull},
|
|
{"DWRI_CHK" , 3, 1, 468, "RO", 1, 0, 0, 0ull},
|
|
{"WORK_MIN" , 4, 3, 468, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 7, 1, 468, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFFM" , 8, 3, 468, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 468, "RAZ", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 16, 469, "RO", 1, 0, 0, 0ull},
|
|
{"START" , 16, 33, 469, "RO", 1, 0, 0, 0ull},
|
|
{"DWB" , 49, 9, 469, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_58_63" , 58, 6, 469, "RAZ", 1, 0, 0, 0ull},
|
|
{"QCB_RIDX" , 0, 6, 470, "RO", 1, 0, 0, 0ull},
|
|
{"QCB_WIDX" , 6, 6, 470, "RO", 1, 0, 0, 0ull},
|
|
{"BUF_PTR" , 12, 33, 470, "RO", 1, 0, 0, 0ull},
|
|
{"BUF_SIZ" , 45, 13, 470, "RO", 1, 0, 0, 0ull},
|
|
{"TAIL" , 58, 1, 470, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 59, 5, 470, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 0, 3, 471, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_Q" , 3, 1, 471, "RO", 1, 0, 0, 0ull},
|
|
{"S_TAIL" , 4, 1, 471, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 5, 1, 471, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 471, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 8, 20, 471, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 471, "RAZ", 1, 0, 0, 0ull},
|
|
{"QUEUE" , 0, 7, 472, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT" , 7, 6, 472, "WR0", 1, 0, 0, 0ull},
|
|
{"INDEX" , 13, 3, 472, "WR0", 1, 0, 0, 0ull},
|
|
{"TAIL" , 16, 1, 472, "R/W", 1, 0, 0, 0ull},
|
|
{"BUF_PTR" , 17, 36, 472, "R/W", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 472, "R/W", 1, 0, 0, 0ull},
|
|
{"STATIC_Q" , 61, 1, 472, "R/W", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 62, 1, 472, "R/W", 1, 0, 0, 0ull},
|
|
{"S_TAIL" , 63, 1, 472, "R/W", 1, 0, 0, 0ull},
|
|
{"QID" , 0, 7, 473, "R/W", 1, 0, 0, 0ull},
|
|
{"PID" , 7, 6, 473, "WR0", 1, 0, 0, 0ull},
|
|
{"RESERVED_13_52" , 13, 40, 473, "RAZ", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 473, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_61_63" , 61, 3, 473, "RAZ", 1, 0, 0, 0ull},
|
|
{"PSB" , 0, 7, 474, "RO", 1, 0, 0, 0ull},
|
|
{"PDB" , 7, 4, 474, "RO", 1, 0, 0, 0ull},
|
|
{"QCB" , 11, 2, 474, "RO", 1, 0, 0, 0ull},
|
|
{"QSB" , 13, 2, 474, "RO", 1, 0, 0, 0ull},
|
|
{"CHK" , 15, 1, 474, "RO", 1, 0, 0, 0ull},
|
|
{"CRC" , 16, 1, 474, "RO", 1, 0, 0, 0ull},
|
|
{"OUT" , 17, 1, 474, "RO", 1, 0, 0, 0ull},
|
|
{"NCB" , 18, 1, 474, "RO", 1, 0, 0, 0ull},
|
|
{"WIF" , 19, 1, 474, "RO", 1, 0, 0, 0ull},
|
|
{"RIF" , 20, 1, 474, "RO", 1, 0, 0, 0ull},
|
|
{"COUNT" , 21, 1, 474, "RO", 1, 0, 0, 0ull},
|
|
{"PSB2" , 22, 5, 474, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_27_63" , 27, 37, 474, "RAZ", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 13, 475, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_19" , 13, 7, 475, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 20, 3, 475, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 475, "RAZ", 1, 0, 0, 0ull},
|
|
{"REFIN" , 0, 1, 476, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INVRES" , 1, 1, 476, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 476, "RAZ", 1, 1, 0, 0},
|
|
{"ENABLE" , 0, 32, 477, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 477, "RAZ", 1, 0, 0, 0ull},
|
|
{"IV" , 0, 32, 478, "R/W", 0, 0, 1185899593ull, 1185899593ull},
|
|
{"RESERVED_32_63" , 32, 32, 478, "RAZ", 1, 1, 0, 0},
|
|
{"ASSERTS" , 0, 17, 479, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 479, "RAZ", 1, 0, 0, 0ull},
|
|
{"PARITY" , 0, 1, 480, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 1, 1, 480, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 480, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENA_PKO" , 0, 1, 481, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENA_DWB" , 1, 1, 481, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STORE_BE" , 2, 1, 481, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 3, 1, 481, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 481, "RAZ", 1, 0, 0, 0ull},
|
|
{"MODE0" , 0, 3, 482, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MODE1" , 3, 3, 482, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 482, "RAZ", 1, 0, 0, 0ull},
|
|
{"PARITY" , 0, 1, 483, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 1, 1, 483, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 483, "RAZ", 1, 0, 0, 0ull},
|
|
{"MODE" , 0, 2, 484, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 484, "RAZ", 1, 0, 0, 0ull},
|
|
{"INDEX" , 0, 8, 485, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 8, 8, 485, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 485, "RAZ", 1, 0, 0, 0ull},
|
|
{"ADR0" , 0, 1, 486, "RO", 0, 0, 0ull, 0ull},
|
|
{"ADR1" , 1, 1, 486, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEND0" , 2, 1, 486, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEND1" , 3, 1, 486, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBR0" , 4, 1, 486, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBR1" , 5, 1, 486, "RO", 0, 0, 0ull, 0ull},
|
|
{"FIDX" , 6, 1, 486, "RO", 0, 0, 0ull, 0ull},
|
|
{"INDEX" , 7, 1, 486, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBT" , 8, 1, 486, "RO", 0, 0, 0ull, 0ull},
|
|
{"CAM" , 9, 1, 486, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_15" , 10, 6, 486, "RAZ", 1, 1, 0, 0},
|
|
{"PP" , 16, 16, 486, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 486, "RAZ", 1, 1, 0, 0},
|
|
{"DS_PC" , 0, 32, 487, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 487, "RAZ", 1, 1, 0, 0},
|
|
{"SBE" , 0, 1, 488, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DBE" , 1, 1, 488, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SBE_IE" , 2, 1, 488, "R/W", 0, 1, 0ull, 0},
|
|
{"DBE_IE" , 3, 1, 488, "R/W", 0, 1, 0ull, 0},
|
|
{"SYN" , 4, 5, 488, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_9_11" , 9, 3, 488, "RAZ", 1, 1, 0, 0},
|
|
{"RPE" , 12, 1, 488, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPE_IE" , 13, 1, 488, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_15" , 14, 2, 488, "RAZ", 1, 1, 0, 0},
|
|
{"IOP" , 16, 13, 488, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_31" , 29, 3, 488, "RAZ", 1, 1, 0, 0},
|
|
{"IOP_IE" , 32, 13, 488, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_45_63" , 45, 19, 488, "RAZ", 1, 1, 0, 0},
|
|
{"NBR_THR" , 0, 5, 489, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PFR_DIS" , 5, 1, 489, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 489, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 32, 490, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 490, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 32, 491, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 491, "RAZ", 1, 1, 0, 0},
|
|
{"NOS_CNT" , 0, 12, 492, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_12_63" , 12, 52, 492, "RAZ", 1, 1, 0, 0},
|
|
{"NW_TIM" , 0, 10, 493, "R/W", 0, 0, 0ull, 1023ull},
|
|
{"RESERVED_10_63" , 10, 54, 493, "RAZ", 1, 1, 0, 0},
|
|
{"GRP_MSK" , 0, 16, 494, "R/W", 0, 0, 65535ull, 65535ull},
|
|
{"RESERVED_16_63" , 16, 48, 494, "RAZ", 1, 1, 0, 0},
|
|
{"RND" , 0, 8, 495, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P1" , 8, 8, 495, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P2" , 16, 8, 495, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P3" , 24, 8, 495, "R/W", 0, 1, 255ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 495, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_THR" , 0, 11, 496, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_11_11" , 11, 1, 496, "RAZ", 1, 1, 0, 0},
|
|
{"MAX_THR" , 12, 11, 496, "R/W", 0, 1, 2047ull, 0},
|
|
{"RESERVED_23_23" , 23, 1, 496, "RAZ", 1, 1, 0, 0},
|
|
{"FREE_CNT" , 24, 12, 496, "RO", 0, 1, 2027ull, 0},
|
|
{"BUF_CNT" , 36, 12, 496, "RO", 0, 1, 0ull, 0},
|
|
{"DES_CNT" , 48, 12, 496, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 496, "RAZ", 1, 1, 0, 0},
|
|
{"TS_PC" , 0, 32, 497, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 497, "RAZ", 1, 1, 0, 0},
|
|
{"WA_PC" , 0, 32, 498, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 498, "RAZ", 1, 1, 0, 0},
|
|
{"WA_PC" , 0, 32, 499, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 499, "RAZ", 1, 1, 0, 0},
|
|
{"WQ_INT" , 0, 16, 500, "R/W1C", 0, 1, 0ull, 0},
|
|
{"IQ_DIS" , 16, 16, 500, "R/W1", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 500, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 12, 501, "RO", 0, 1, 0ull, 0},
|
|
{"DS_CNT" , 12, 12, 501, "RO", 0, 1, 0ull, 0},
|
|
{"TC_CNT" , 24, 4, 501, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_63" , 28, 36, 501, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 502, "RAZ", 1, 1, 0, 0},
|
|
{"PC_THR" , 8, 20, 502, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_31" , 28, 4, 502, "RAZ", 1, 1, 0, 0},
|
|
{"PC" , 32, 28, 502, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 502, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_THR" , 0, 11, 503, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_11_11" , 11, 1, 503, "RAZ", 1, 1, 0, 0},
|
|
{"DS_THR" , 12, 11, 503, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_23_23" , 23, 1, 503, "RAZ", 1, 1, 0, 0},
|
|
{"TC_THR" , 24, 4, 503, "R/W", 0, 1, 0ull, 0},
|
|
{"TC_EN" , 28, 1, 503, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 503, "RAZ", 1, 1, 0, 0},
|
|
{"WS_PC" , 0, 32, 504, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 504, "RAZ", 1, 1, 0, 0},
|
|
{"MEM" , 0, 1, 505, "RO", 0, 0, 0ull, 0ull},
|
|
{"RRC" , 1, 1, 505, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 505, "RAZ", 1, 1, 0, 0},
|
|
{"ENT_EN" , 0, 1, 506, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNG_EN" , 1, 1, 506, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNM_RST" , 2, 1, 506, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNG_RST" , 3, 1, 506, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 506, "RAZ", 1, 1, 0, 0},
|
|
{"PHASE" , 0, 8, 507, "R/W", 0, 0, 100ull, 100ull},
|
|
{"SAMPLE" , 8, 4, 507, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PREAMBLE" , 12, 1, 507, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CLK_IDLE" , 13, 1, 507, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_14" , 14, 1, 507, "RAZ", 1, 1, 0, 0},
|
|
{"SAMPLE_MODE" , 15, 1, 507, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SAMPLE_HI" , 16, 5, 507, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_63" , 21, 43, 507, "RAZ", 1, 1, 0, 0},
|
|
{"REG_ADR" , 0, 5, 508, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 508, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_ADR" , 8, 5, 508, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_13_15" , 13, 3, 508, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_OP" , 16, 1, 508, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_17_63" , 17, 47, 508, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 509, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 509, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 510, "RO", 0, 1, 0ull, 0},
|
|
{"VAL" , 16, 1, 510, "RO", 0, 1, 0ull, 0},
|
|
{"PENDING" , 17, 1, 510, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 510, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 511, "R/W", 0, 1, 0ull, 0},
|
|
{"VAL" , 16, 1, 511, "RO", 0, 1, 0ull, 0},
|
|
{"PENDING" , 17, 1, 511, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 511, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 512, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STAT0" , 0, 1, 513, "RO", 0, 0, 0ull, 0ull},
|
|
{"STAT1" , 1, 1, 513, "RO", 0, 0, 0ull, 0ull},
|
|
{"STAT2" , 2, 1, 513, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 513, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SRXDLCK" , 0, 1, 514, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RCVTRN" , 1, 1, 514, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DRPTRN" , 2, 1, 514, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SNDTRN" , 3, 1, 514, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STATRCV" , 4, 1, 514, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STATDRV" , 5, 1, 514, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RUNBIST" , 6, 1, 514, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLKDLY" , 7, 5, 514, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_12_15" , 12, 4, 514, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SEETRN" , 16, 1, 514, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 514, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_3" , 0, 4, 515, "RAZ", 0, 1, 0ull, 0},
|
|
{"D4CLK0" , 4, 1, 515, "R/W1C", 0, 1, 0ull, 0},
|
|
{"D4CLK1" , 5, 1, 515, "R/W1C", 0, 1, 0ull, 0},
|
|
{"S4CLK0" , 6, 1, 515, "R/W1C", 0, 1, 0ull, 0},
|
|
{"S4CLK1" , 7, 1, 515, "R/W1C", 0, 1, 0ull, 0},
|
|
{"SRXTRN" , 8, 1, 515, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_9_9" , 9, 1, 515, "RAZ", 0, 1, 0ull, 0},
|
|
{"STXCAL" , 10, 1, 515, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_11_63" , 11, 53, 515, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DLLDIS" , 0, 1, 516, "R/W", 1, 0, 0, 0ull},
|
|
{"DLLFRC" , 1, 1, 516, "WR0", 1, 0, 0, 0ull},
|
|
{"OFFDLY" , 2, 6, 516, "R/W", 1, 0, 0, 0ull},
|
|
{"BITSEL" , 8, 5, 516, "R/W", 1, 1, 0, 0},
|
|
{"OFFSET" , 13, 5, 516, "R/W", 1, 1, 0, 0},
|
|
{"MUX" , 18, 1, 516, "WR0", 1, 1, 0, 0},
|
|
{"INC" , 19, 1, 516, "WR0", 1, 1, 0, 0},
|
|
{"DEC" , 20, 1, 516, "WR0", 1, 1, 0, 0},
|
|
{"CLRDLY" , 21, 1, 516, "WR0", 1, 1, 0, 0},
|
|
{"RESERVED_22_23" , 22, 2, 516, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SSTEP" , 24, 1, 516, "R/W", 1, 0, 0, 0ull},
|
|
{"SSTEP_GO" , 25, 1, 516, "WR0", 1, 1, 0, 0},
|
|
{"RESERVED_26_27" , 26, 2, 516, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FALL8" , 28, 1, 516, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FALLNOP" , 29, 1, 516, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_63" , 30, 34, 516, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OFFSET" , 0, 5, 517, "RO", 0, 1, 0ull, 0},
|
|
{"MUXSEL" , 5, 2, 517, "RO", 0, 1, 0ull, 0},
|
|
{"UNXTERM" , 7, 1, 517, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TESTRES" , 8, 1, 517, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 517, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SRX4CMP" , 0, 8, 518, "R/W", 0, 1, 0ull, 0},
|
|
{"STX4PCMP" , 8, 4, 518, "R/W", 0, 1, 0ull, 0},
|
|
{"STX4NCMP" , 12, 4, 518, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 518, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ERRCNT" , 0, 4, 519, "R/W", 0, 0, 0ull, 3ull},
|
|
{"RESERVED_4_5" , 4, 2, 519, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DIPPAY" , 6, 1, 519, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DIPCLS" , 7, 1, 519, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 8, 1, 519, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 519, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRT" , 0, 8, 520, "RO", 0, 0, 0ull, 0ull},
|
|
{"RSVOP" , 8, 4, 520, "RO", 0, 0, 0ull, 0ull},
|
|
{"CALBNK" , 12, 2, 520, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_30" , 14, 17, 520, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MUL" , 31, 1, 520, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 520, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 0, 1, 521, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ABNORM" , 1, 1, 521, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_3" , 2, 2, 521, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SPIOVR" , 4, 1, 521, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLSERR" , 5, 1, 521, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRWNNG" , 6, 1, 521, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 7, 1, 521, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TPAOVR" , 8, 1, 521, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DIPERR" , 9, 1, 521, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SYNCERR" , 10, 1, 521, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CALERR" , 11, 1, 521, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 521, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 0, 1, 522, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ABNORM" , 1, 1, 522, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_3" , 2, 2, 522, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SPIOVR" , 4, 1, 522, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CLSERR" , 5, 1, 522, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DRWNNG" , 6, 1, 522, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 7, 1, 522, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TPAOVR" , 8, 1, 522, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DIPERR" , 9, 1, 522, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SYNCERR" , 10, 1, 522, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CALERR" , 11, 1, 522, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_30" , 12, 19, 522, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SPF" , 31, 1, 522, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 522, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 0, 1, 523, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ABNORM" , 1, 1, 523, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_3" , 2, 2, 523, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SPIOVR" , 4, 1, 523, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLSERR" , 5, 1, 523, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRWNNG" , 6, 1, 523, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 7, 1, 523, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TPAOVR" , 8, 1, 523, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DIPERR" , 9, 1, 523, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SYNCERR" , 10, 1, 523, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CALERR" , 11, 1, 523, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 523, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 0, 32, 524, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 524, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX" , 0, 32, 525, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 525, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRTSEL" , 0, 4, 526, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 526, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MUX_EN" , 0, 1, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MACRO_EN" , 1, 1, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAXDIST" , 2, 5, 527, "R/W", 0, 0, 0ull, 8ull},
|
|
{"SET_BOOT" , 7, 1, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLR_BOOT" , 8, 1, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"JITTER" , 9, 3, 527, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TRNTEST" , 12, 1, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 527, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"BW_CTL" , 0, 5, 528, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 528, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SETTING" , 0, 17, 529, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_17_63" , 17, 47, 529, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"INF_EN" , 0, 1, 530, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_2" , 1, 2, 530, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ST_EN" , 3, 1, 530, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PRTS" , 4, 4, 530, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 530, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IGNORE" , 0, 16, 531, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 531, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRT0" , 0, 4, 532, "R/W", 1, 1, 0, 0},
|
|
{"PRT1" , 4, 4, 532, "R/W", 1, 1, 0, 0},
|
|
{"PRT2" , 8, 4, 532, "R/W", 1, 1, 0, 0},
|
|
{"PRT3" , 12, 4, 532, "R/W", 1, 1, 0, 0},
|
|
{"ODDPAR" , 16, 1, 532, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_17_63" , 17, 47, 532, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LEN" , 0, 7, 533, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_7" , 7, 1, 533, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"M" , 8, 8, 533, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 533, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 4, 534, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OPC" , 4, 4, 534, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MOD" , 8, 4, 534, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SOP" , 12, 1, 534, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EOP" , 13, 1, 534, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 534, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DAT" , 0, 64, 535, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_2" , 0, 3, 536, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IGNTPA" , 3, 1, 536, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_4" , 4, 1, 536, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MINTRN" , 5, 1, 536, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 536, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 0, 32, 537, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 537, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"INF_EN" , 0, 1, 538, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_2" , 1, 2, 538, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ST_EN" , 3, 1, 538, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 538, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DIPMAX" , 0, 4, 539, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMMAX" , 4, 4, 539, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 539, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IGNTPA" , 0, 16, 540, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 540, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CALPAR0" , 0, 1, 541, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CALPAR1" , 1, 1, 541, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OVRBST" , 2, 1, 541, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DATOVR" , 3, 1, 541, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DIPERR" , 4, 1, 541, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NOSYNC" , 5, 1, 541, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UNXFRM" , 6, 1, 541, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMERR" , 7, 1, 541, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 541, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CALPAR0" , 0, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CALPAR1" , 1, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OVRBST" , 2, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DATOVR" , 3, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DIPERR" , 4, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NOSYNC" , 5, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UNXFRM" , 6, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FRMERR" , 7, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SYNCERR" , 8, 1, 542, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 542, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CALPAR0" , 0, 1, 543, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CALPAR1" , 1, 1, 543, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OVRBST" , 2, 1, 543, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DATOVR" , 3, 1, 543, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DIPERR" , 4, 1, 543, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NOSYNC" , 5, 1, 543, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UNXFRM" , 6, 1, 543, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMERR" , 7, 1, 543, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 543, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MINB" , 0, 9, 544, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 544, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRT0" , 0, 4, 545, "R/W", 1, 1, 0, 0},
|
|
{"PRT1" , 4, 4, 545, "R/W", 1, 1, 0, 0},
|
|
{"PRT2" , 8, 4, 545, "R/W", 1, 1, 0, 0},
|
|
{"PRT3" , 12, 4, 545, "R/W", 1, 1, 0, 0},
|
|
{"ODDPAR" , 16, 1, 545, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_17_63" , 17, 47, 545, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX_T" , 0, 16, 546, "R/W", 0, 1, 0ull, 0},
|
|
{"ALPHA" , 16, 16, 546, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 546, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LEN" , 0, 7, 547, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_7" , 7, 1, 547, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"M" , 8, 8, 547, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 547, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 0, 32, 548, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 548, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 0, 32, 549, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 549, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"BCKPRS" , 0, 4, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLR" , 4, 1, 550, "WR0", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 550, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 0, 32, 551, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 551, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"INTERVAL" , 0, 22, 552, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 552, "RAZ", 1, 0, 0, 0ull},
|
|
{"COUNT" , 24, 22, 552, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_46_46" , 46, 1, 552, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENA" , 47, 1, 552, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 552, "RAZ", 1, 0, 0, 0ull},
|
|
{"BSIZE" , 0, 20, 553, "RO", 1, 0, 0, 0ull},
|
|
{"BASE" , 20, 31, 553, "RO", 1, 0, 0, 0ull},
|
|
{"BUCKET" , 51, 13, 553, "RO", 1, 0, 0, 0ull},
|
|
{"BUCKET" , 0, 7, 554, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 554, "RAZ", 1, 0, 0, 0ull},
|
|
{"CSIZE" , 8, 13, 554, "RO", 1, 0, 0, 0ull},
|
|
{"CPOOL" , 21, 3, 554, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 554, "RAZ", 1, 0, 0, 0ull},
|
|
{"RING" , 0, 4, 555, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NUM_BUCKETS" , 4, 20, 555, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIRST_BUCKET" , 24, 31, 555, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_55_63" , 55, 9, 555, "RAZ", 1, 0, 0, 0ull},
|
|
{"RING" , 0, 4, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTERVAL" , 4, 22, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WORDS_PER_CHUNK" , 26, 13, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 39, 3, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENABLE" , 42, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_43_63" , 43, 21, 556, "RAZ", 1, 0, 0, 0ull},
|
|
{"CTL" , 0, 1, 557, "RO", 1, 0, 0, 0ull},
|
|
{"NCB" , 1, 1, 557, "RO", 1, 0, 0, 0ull},
|
|
{"STA" , 2, 2, 557, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 557, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 16, 558, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 558, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENABLE_TIMERS" , 0, 1, 559, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENABLE_DWB" , 1, 1, 559, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 2, 1, 559, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 559, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 16, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 560, "RAZ", 1, 0, 0, 0ull},
|
|
{"INDEX" , 0, 8, 561, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 8, 8, 561, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 561, "RAZ", 1, 0, 0, 0ull},
|
|
{"TDF0" , 0, 1, 562, "RO", 0, 0, 0ull, 0ull},
|
|
{"TDF1" , 1, 1, 562, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCF" , 2, 1, 562, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 562, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ENA" , 0, 1, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WRAP" , 1, 1, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRIG_CTL" , 2, 2, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIME_GRN" , 4, 3, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FULL_THR" , 7, 2, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CIU_TRG" , 9, 1, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CIU_THR" , 10, 1, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_TRG" , 11, 1, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_THR" , 12, 1, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_ENA" , 13, 1, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IGNORE_O" , 14, 1, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 563, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WPTR" , 0, 8, 564, "RO", 0, 0, 0ull, 0ull},
|
|
{"RPTR" , 8, 8, 564, "RO", 0, 0, 0ull, 0ull},
|
|
{"CYCLES" , 16, 48, 564, "RO", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 565, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 565, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 566, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 567, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 567, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 567, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 567, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 567, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 567, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 567, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 567, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 567, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 567, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 567, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 567, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 567, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 567, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 567, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 567, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_16_63" , 16, 48, 567, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 568, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 568, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 568, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 568, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 568, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 568, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 568, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 568, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 568, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 568, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 568, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 568, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 569, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CIU_TRG" , 0, 1, 570, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CIU_THR" , 1, 1, 570, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MCD0_TRG" , 2, 1, 570, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MCD0_THR" , 3, 1, 570, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 570, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DATA" , 0, 64, 571, "RO", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 572, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 572, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 573, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 573, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 574, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 574, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 574, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 574, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 574, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 574, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 574, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 574, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 574, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 574, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 574, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 574, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 574, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 574, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 574, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 574, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_16_63" , 16, 48, 574, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 575, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 575, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 575, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 575, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 575, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 575, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 575, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 575, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 575, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 575, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 575, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 575, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 576, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 576, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 576, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 576, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 576, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 576, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 577, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 577, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 578, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 579, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 579, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 579, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 579, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 579, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 579, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 579, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 579, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 579, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 579, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 579, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 579, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 579, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 579, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 579, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 579, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_16_63" , 16, 48, 579, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 580, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 580, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 580, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 580, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 580, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 580, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 580, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 580, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 580, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 580, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 580, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 580, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 581, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 581, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 581, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 581, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 581, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 581, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ZIP_CTL" , 0, 4, 582, "RO", 1, 0, 0, 0ull},
|
|
{"ZIP_CORE" , 4, 27, 582, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 582, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 33, 583, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 33, 13, 583, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 46, 3, 583, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 49, 9, 583, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_58_63" , 58, 6, 583, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 0, 1, 584, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FORCECLK" , 1, 1, 584, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 584, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DISABLED" , 0, 1, 585, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_7" , 1, 7, 585, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CTXSIZE" , 8, 12, 585, "RO", 0, 0, 1536ull, 1536ull},
|
|
{"ONFSIZE" , 20, 12, 585, "RO", 0, 0, 512ull, 512ull},
|
|
{"DEPTH" , 32, 16, 585, "RO", 0, 0, 31744ull, 31744ull},
|
|
{"RESERVED_48_63" , 48, 16, 585, "RAZ", 1, 0, 0, 0ull},
|
|
{"ASSERTS" , 0, 14, 586, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 586, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 0, 1, 587, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 587, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 0, 1, 588, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 588, "RAZ", 1, 0, 0, 0ull},
|
|
{NULL,0,0,0,0,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn58xxp1[] = {
|
|
/* name , ---------------type, bits, off, #field, fld of */
|
|
{"cvmx_asx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 4, 0},
|
|
{"cvmx_asx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 4, 4},
|
|
{"cvmx_asx#_prt_loop" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 3, 8},
|
|
{"cvmx_asx#_rld_bypass" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 2, 11},
|
|
{"cvmx_asx#_rld_bypass_setting", CVMX_CSR_DB_TYPE_RSL, 64, 8, 2, 13},
|
|
{"cvmx_asx#_rld_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 3, 15},
|
|
{"cvmx_asx#_rld_data_drv" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 3, 18},
|
|
{"cvmx_asx#_rld_nctl_strong" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 2, 21},
|
|
{"cvmx_asx#_rld_nctl_weak" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 2, 23},
|
|
{"cvmx_asx#_rld_pctl_strong" , CVMX_CSR_DB_TYPE_RSL, 64, 18, 2, 25},
|
|
{"cvmx_asx#_rld_pctl_weak" , CVMX_CSR_DB_TYPE_RSL, 64, 20, 2, 27},
|
|
{"cvmx_asx#_rld_setting" , CVMX_CSR_DB_TYPE_RSL, 64, 22, 6, 29},
|
|
{"cvmx_asx#_rx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 24, 2, 35},
|
|
{"cvmx_asx#_rx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 32, 2, 37},
|
|
{"cvmx_asx#_tx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 34, 2, 39},
|
|
{"cvmx_asx#_tx_comp_byp" , CVMX_CSR_DB_TYPE_RSL, 64, 42, 4, 41},
|
|
{"cvmx_asx#_tx_hi_water#" , CVMX_CSR_DB_TYPE_RSL, 64, 44, 2, 45},
|
|
{"cvmx_asx#_tx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 2, 47},
|
|
{"cvmx_asx0_dbg_data_drv" , CVMX_CSR_DB_TYPE_RSL, 64, 54, 3, 49},
|
|
{"cvmx_asx0_dbg_data_enable" , CVMX_CSR_DB_TYPE_RSL, 64, 55, 2, 52},
|
|
{"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 56, 2, 54},
|
|
{"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 57, 2, 56},
|
|
{"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 58, 2, 58},
|
|
{"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 59, 2, 60},
|
|
{"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 60, 15, 62},
|
|
{"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 93, 2, 77},
|
|
{"cvmx_ciu_int#_en4_0" , CVMX_CSR_DB_TYPE_NCB, 64, 126, 15, 79},
|
|
{"cvmx_ciu_int#_en4_1" , CVMX_CSR_DB_TYPE_NCB, 64, 142, 2, 94},
|
|
{"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 158, 15, 96},
|
|
{"cvmx_ciu_int#_sum4" , CVMX_CSR_DB_TYPE_NCB, 64, 191, 15, 111},
|
|
{"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 207, 2, 126},
|
|
{"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 208, 2, 128},
|
|
{"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 224, 2, 130},
|
|
{"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 240, 2, 132},
|
|
{"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 241, 2, 134},
|
|
{"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 242, 2, 136},
|
|
{"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 243, 1, 138},
|
|
{"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 259, 3, 139},
|
|
{"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 260, 2, 142},
|
|
{"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 261, 4, 144},
|
|
{"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 262, 2, 148},
|
|
{"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 263, 3, 150},
|
|
{"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 267, 7, 153},
|
|
{"cvmx_dbg_data" , CVMX_CSR_DB_TYPE_NCB, 64, 283, 5, 160},
|
|
{"cvmx_dfa_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 284, 4, 165},
|
|
{"cvmx_dfa_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 285, 10, 169},
|
|
{"cvmx_dfa_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 286, 5, 179},
|
|
{"cvmx_dfa_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 287, 2, 184},
|
|
{"cvmx_dfa_difctl" , CVMX_CSR_DB_TYPE_NCB, 64, 288, 4, 186},
|
|
{"cvmx_dfa_difrdptr" , CVMX_CSR_DB_TYPE_NCB, 64, 289, 3, 190},
|
|
{"cvmx_dfa_err" , CVMX_CSR_DB_TYPE_RSL, 64, 290, 21, 193},
|
|
{"cvmx_dfa_memcfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 291, 20, 214},
|
|
{"cvmx_dfa_memcfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 292, 11, 234},
|
|
{"cvmx_dfa_memcfg2" , CVMX_CSR_DB_TYPE_RSL, 64, 293, 8, 245},
|
|
{"cvmx_dfa_memfadr" , CVMX_CSR_DB_TYPE_RSL, 64, 294, 6, 253},
|
|
{"cvmx_dfa_memfcr" , CVMX_CSR_DB_TYPE_RSL, 64, 295, 6, 259},
|
|
{"cvmx_dfa_memrld" , CVMX_CSR_DB_TYPE_RSL, 64, 296, 2, 265},
|
|
{"cvmx_dfa_ncbctl" , CVMX_CSR_DB_TYPE_RSL, 64, 297, 8, 267},
|
|
{"cvmx_dfa_rodt_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 298, 6, 275},
|
|
{"cvmx_dfa_sbd_dbg0" , CVMX_CSR_DB_TYPE_RSL, 64, 299, 1, 281},
|
|
{"cvmx_dfa_sbd_dbg1" , CVMX_CSR_DB_TYPE_RSL, 64, 300, 1, 282},
|
|
{"cvmx_dfa_sbd_dbg2" , CVMX_CSR_DB_TYPE_RSL, 64, 301, 1, 283},
|
|
{"cvmx_dfa_sbd_dbg3" , CVMX_CSR_DB_TYPE_RSL, 64, 302, 1, 284},
|
|
{"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 303, 6, 285},
|
|
{"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 304, 7, 291},
|
|
{"cvmx_fpa_fpf#_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 305, 3, 298},
|
|
{"cvmx_fpa_fpf#_size" , CVMX_CSR_DB_TYPE_RSL, 64, 312, 2, 301},
|
|
{"cvmx_fpa_fpf0_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 319, 3, 303},
|
|
{"cvmx_fpa_fpf0_size" , CVMX_CSR_DB_TYPE_RSL, 64, 320, 2, 306},
|
|
{"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 321, 29, 308},
|
|
{"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 322, 29, 337},
|
|
{"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 323, 2, 366},
|
|
{"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 331, 2, 368},
|
|
{"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 339, 3, 370},
|
|
{"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 340, 3, 373},
|
|
{"cvmx_fpa_wart_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 341, 2, 376},
|
|
{"cvmx_fpa_wart_status" , CVMX_CSR_DB_TYPE_RSL, 64, 342, 2, 378},
|
|
{"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 343, 8, 380},
|
|
{"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 345, 2, 388},
|
|
{"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 347, 3, 390},
|
|
{"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 349, 2, 393},
|
|
{"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 351, 5, 395},
|
|
{"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 359, 1, 400},
|
|
{"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 367, 1, 401},
|
|
{"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 375, 1, 402},
|
|
{"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 383, 1, 403},
|
|
{"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 391, 1, 404},
|
|
{"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 399, 1, 405},
|
|
{"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 407, 2, 406},
|
|
{"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 415, 4, 408},
|
|
{"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 423, 2, 412},
|
|
{"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 431, 11, 414},
|
|
{"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 439, 10, 425},
|
|
{"cvmx_gmx#_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 447, 2, 435},
|
|
{"cvmx_gmx#_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 455, 2, 437},
|
|
{"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 463, 2, 439},
|
|
{"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 471, 21, 441},
|
|
{"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 479, 21, 462},
|
|
{"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 487, 2, 483},
|
|
{"cvmx_gmx#_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 495, 2, 485},
|
|
{"cvmx_gmx#_rx#_rx_inbnd" , CVMX_CSR_DB_TYPE_RSL, 64, 503, 4, 487},
|
|
{"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 511, 2, 491},
|
|
{"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 519, 2, 493},
|
|
{"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 527, 2, 495},
|
|
{"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 535, 2, 497},
|
|
{"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 543, 2, 499},
|
|
{"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 551, 2, 501},
|
|
{"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 559, 2, 503},
|
|
{"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 567, 2, 505},
|
|
{"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 575, 2, 507},
|
|
{"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 583, 2, 509},
|
|
{"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 591, 4, 511},
|
|
{"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 599, 2, 515},
|
|
{"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 607, 2, 517},
|
|
{"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 615, 2, 519},
|
|
{"cvmx_gmx#_rx_pass_en" , CVMX_CSR_DB_TYPE_RSL, 64, 623, 2, 521},
|
|
{"cvmx_gmx#_rx_pass_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 625, 2, 523},
|
|
{"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 657, 3, 525},
|
|
{"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 659, 2, 528},
|
|
{"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 661, 2, 530},
|
|
{"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 669, 3, 532},
|
|
{"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 671, 5, 535},
|
|
{"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 679, 2, 540},
|
|
{"cvmx_gmx#_tx#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 687, 2, 542},
|
|
{"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 695, 3, 544},
|
|
{"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 703, 2, 547},
|
|
{"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 711, 2, 549},
|
|
{"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 719, 2, 551},
|
|
{"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 727, 2, 553},
|
|
{"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 735, 2, 555},
|
|
{"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 743, 2, 557},
|
|
{"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 751, 2, 559},
|
|
{"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 759, 2, 561},
|
|
{"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 767, 2, 563},
|
|
{"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 775, 2, 565},
|
|
{"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 783, 2, 567},
|
|
{"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 791, 2, 569},
|
|
{"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 799, 2, 571},
|
|
{"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 807, 2, 573},
|
|
{"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 815, 2, 575},
|
|
{"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 823, 2, 577},
|
|
{"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 831, 2, 579},
|
|
{"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 839, 2, 581},
|
|
{"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 847, 2, 583},
|
|
{"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 855, 2, 585},
|
|
{"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 857, 2, 587},
|
|
{"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 859, 2, 589},
|
|
{"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 861, 3, 591},
|
|
{"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 863, 8, 594},
|
|
{"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 865, 8, 602},
|
|
{"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 867, 2, 610},
|
|
{"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 869, 2, 612},
|
|
{"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 871, 4, 614},
|
|
{"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 873, 2, 618},
|
|
{"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 875, 2, 620},
|
|
{"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 877, 2, 622},
|
|
{"cvmx_gmx#_tx_spi_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 879, 3, 624},
|
|
{"cvmx_gmx#_tx_spi_drain" , CVMX_CSR_DB_TYPE_RSL, 64, 881, 2, 627},
|
|
{"cvmx_gmx#_tx_spi_max" , CVMX_CSR_DB_TYPE_RSL, 64, 883, 4, 629},
|
|
{"cvmx_gmx#_tx_spi_round#" , CVMX_CSR_DB_TYPE_RSL, 64, 885, 2, 633},
|
|
{"cvmx_gmx#_tx_spi_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 949, 2, 635},
|
|
{"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 951, 7, 637},
|
|
{"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 967, 2, 644},
|
|
{"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 968, 2, 646},
|
|
{"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 969, 2, 648},
|
|
{"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 970, 2, 650},
|
|
{"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 971, 19, 652},
|
|
{"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 972, 6, 671},
|
|
{"cvmx_iob_dwb_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 973, 3, 677},
|
|
{"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 974, 3, 680},
|
|
{"cvmx_iob_i2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 975, 3, 683},
|
|
{"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 976, 5, 686},
|
|
{"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 977, 5, 691},
|
|
{"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 978, 1, 696},
|
|
{"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 979, 1, 697},
|
|
{"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 980, 7, 698},
|
|
{"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 981, 7, 705},
|
|
{"cvmx_iob_n2c_l2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 982, 3, 712},
|
|
{"cvmx_iob_n2c_rsp_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 983, 3, 715},
|
|
{"cvmx_iob_outb_com_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 984, 3, 718},
|
|
{"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 985, 5, 721},
|
|
{"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 986, 5, 726},
|
|
{"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 987, 1, 731},
|
|
{"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 988, 1, 732},
|
|
{"cvmx_iob_outb_fpa_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 989, 3, 733},
|
|
{"cvmx_iob_outb_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 990, 3, 736},
|
|
{"cvmx_iob_p2c_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 991, 3, 739},
|
|
{"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 992, 2, 742},
|
|
{"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 993, 2, 744},
|
|
{"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 994, 2, 746},
|
|
{"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 995, 2, 748},
|
|
{"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 996, 17, 750},
|
|
{"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 997, 2, 767},
|
|
{"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 998, 1, 769},
|
|
{"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 999, 12, 770},
|
|
{"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 1000, 11, 782},
|
|
{"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 1001, 11, 793},
|
|
{"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 1002, 2, 804},
|
|
{"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 1003, 2, 806},
|
|
{"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 1004, 2, 808},
|
|
{"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1005, 3, 810},
|
|
{"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 1041, 2, 813},
|
|
{"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 1077, 6, 815},
|
|
{"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 1078, 5, 821},
|
|
{"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 1079, 6, 826},
|
|
{"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1080, 7, 832},
|
|
{"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 1081, 2, 839},
|
|
{"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1089, 2, 841},
|
|
{"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 1090, 3, 843},
|
|
{"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 1091, 5, 846},
|
|
{"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 1099, 3, 851},
|
|
{"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 1100, 2, 854},
|
|
{"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 1101, 2, 856},
|
|
{"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 1102, 2, 858},
|
|
{"cvmx_key_bist_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1103, 4, 860},
|
|
{"cvmx_key_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1104, 3, 864},
|
|
{"cvmx_key_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1105, 5, 867},
|
|
{"cvmx_key_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1106, 5, 872},
|
|
{"cvmx_l2c_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 1107, 7, 877},
|
|
{"cvmx_l2c_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 1108, 5, 884},
|
|
{"cvmx_l2c_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 1109, 8, 889},
|
|
{"cvmx_l2c_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1110, 10, 897},
|
|
{"cvmx_l2c_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1111, 8, 907},
|
|
{"cvmx_l2c_dut" , CVMX_CSR_DB_TYPE_RSL, 64, 1112, 5, 915},
|
|
{"cvmx_l2c_lckbase" , CVMX_CSR_DB_TYPE_RSL, 64, 1113, 4, 920},
|
|
{"cvmx_l2c_lckoff" , CVMX_CSR_DB_TYPE_RSL, 64, 1114, 2, 924},
|
|
{"cvmx_l2c_lfb0" , CVMX_CSR_DB_TYPE_RSL, 64, 1115, 14, 926},
|
|
{"cvmx_l2c_lfb1" , CVMX_CSR_DB_TYPE_RSL, 64, 1116, 19, 940},
|
|
{"cvmx_l2c_lfb2" , CVMX_CSR_DB_TYPE_RSL, 64, 1117, 3, 959},
|
|
{"cvmx_l2c_lfb3" , CVMX_CSR_DB_TYPE_RSL, 64, 1118, 3, 962},
|
|
{"cvmx_l2c_pfc#" , CVMX_CSR_DB_TYPE_RSL, 64, 1119, 2, 965},
|
|
{"cvmx_l2c_pfctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1123, 17, 967},
|
|
{"cvmx_l2c_spar0" , CVMX_CSR_DB_TYPE_RSL, 64, 1124, 5, 984},
|
|
{"cvmx_l2c_spar1" , CVMX_CSR_DB_TYPE_RSL, 64, 1125, 5, 989},
|
|
{"cvmx_l2c_spar2" , CVMX_CSR_DB_TYPE_RSL, 64, 1126, 5, 994},
|
|
{"cvmx_l2c_spar3" , CVMX_CSR_DB_TYPE_RSL, 64, 1127, 5, 999},
|
|
{"cvmx_l2c_spar4" , CVMX_CSR_DB_TYPE_RSL, 64, 1128, 2, 1004},
|
|
{"cvmx_l2d_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 1129, 3, 1006},
|
|
{"cvmx_l2d_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 1130, 2, 1009},
|
|
{"cvmx_l2d_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 1131, 2, 1011},
|
|
{"cvmx_l2d_bst3" , CVMX_CSR_DB_TYPE_RSL, 64, 1132, 2, 1013},
|
|
{"cvmx_l2d_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1133, 7, 1015},
|
|
{"cvmx_l2d_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1134, 5, 1022},
|
|
{"cvmx_l2d_fsyn0" , CVMX_CSR_DB_TYPE_RSL, 64, 1135, 3, 1027},
|
|
{"cvmx_l2d_fsyn1" , CVMX_CSR_DB_TYPE_RSL, 64, 1136, 3, 1030},
|
|
{"cvmx_l2d_fus0" , CVMX_CSR_DB_TYPE_RSL, 64, 1137, 2, 1033},
|
|
{"cvmx_l2d_fus1" , CVMX_CSR_DB_TYPE_RSL, 64, 1138, 2, 1035},
|
|
{"cvmx_l2d_fus2" , CVMX_CSR_DB_TYPE_RSL, 64, 1139, 2, 1037},
|
|
{"cvmx_l2d_fus3" , CVMX_CSR_DB_TYPE_RSL, 64, 1140, 6, 1039},
|
|
{"cvmx_l2t_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1141, 14, 1045},
|
|
{"cvmx_led_blink" , CVMX_CSR_DB_TYPE_RSL, 64, 1142, 2, 1059},
|
|
{"cvmx_led_clk_phase" , CVMX_CSR_DB_TYPE_RSL, 64, 1143, 2, 1061},
|
|
{"cvmx_led_cylon" , CVMX_CSR_DB_TYPE_RSL, 64, 1144, 2, 1063},
|
|
{"cvmx_led_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1145, 2, 1065},
|
|
{"cvmx_led_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1146, 2, 1067},
|
|
{"cvmx_led_polarity" , CVMX_CSR_DB_TYPE_RSL, 64, 1147, 2, 1069},
|
|
{"cvmx_led_prt" , CVMX_CSR_DB_TYPE_RSL, 64, 1148, 2, 1071},
|
|
{"cvmx_led_prt_fmt" , CVMX_CSR_DB_TYPE_RSL, 64, 1149, 2, 1073},
|
|
{"cvmx_led_prt_status#" , CVMX_CSR_DB_TYPE_RSL, 64, 1150, 2, 1075},
|
|
{"cvmx_led_udd_cnt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1158, 2, 1077},
|
|
{"cvmx_led_udd_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 1160, 2, 1079},
|
|
{"cvmx_led_udd_dat_clr#" , CVMX_CSR_DB_TYPE_RSL, 64, 1162, 2, 1081},
|
|
{"cvmx_led_udd_dat_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 1164, 2, 1083},
|
|
{"cvmx_lmc#_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1166, 7, 1085},
|
|
{"cvmx_lmc#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1167, 19, 1092},
|
|
{"cvmx_lmc#_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 1168, 4, 1111},
|
|
{"cvmx_lmc#_dclk_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1169, 2, 1115},
|
|
{"cvmx_lmc#_dclk_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1170, 2, 1117},
|
|
{"cvmx_lmc#_ddr2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1171, 18, 1119},
|
|
{"cvmx_lmc#_delay_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1172, 6, 1137},
|
|
{"cvmx_lmc#_dual_memcfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1173, 5, 1143},
|
|
{"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 1174, 5, 1148},
|
|
{"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1175, 6, 1153},
|
|
{"cvmx_lmc#_ifb_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1176, 2, 1159},
|
|
{"cvmx_lmc#_ifb_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1177, 2, 1161},
|
|
{"cvmx_lmc#_mem_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 1178, 14, 1163},
|
|
{"cvmx_lmc#_mem_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 1179, 9, 1177},
|
|
{"cvmx_lmc#_ops_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1180, 2, 1186},
|
|
{"cvmx_lmc#_ops_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1181, 2, 1188},
|
|
{"cvmx_lmc#_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1182, 12, 1190},
|
|
{"cvmx_lmc#_pll_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1183, 3, 1202},
|
|
{"cvmx_lmc#_rodt_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1184, 6, 1205},
|
|
{"cvmx_lmc#_rodt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1185, 9, 1211},
|
|
{"cvmx_lmc#_wodt_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 1186, 9, 1220},
|
|
{"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 1187, 4, 1229},
|
|
{"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1188, 3, 1233},
|
|
{"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1189, 3, 1236},
|
|
{"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1190, 3, 1239},
|
|
{"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1191, 5, 1242},
|
|
{"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1193, 1, 1247},
|
|
{"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1194, 10, 1248},
|
|
{"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 1202, 13, 1258},
|
|
{"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1210, 4, 1271},
|
|
{"cvmx_mio_fus_bnk_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 1211, 1, 1275},
|
|
{"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 1215, 2, 1276},
|
|
{"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 1216, 2, 1278},
|
|
{"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 1217, 9, 1280},
|
|
{"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 1218, 8, 1289},
|
|
{"cvmx_mio_fus_ema" , CVMX_CSR_DB_TYPE_RSL, 64, 1219, 2, 1297},
|
|
{"cvmx_mio_fus_pll" , CVMX_CSR_DB_TYPE_RSL, 64, 1220, 3, 1299},
|
|
{"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 1221, 2, 1302},
|
|
{"cvmx_mio_fus_prog_times" , CVMX_CSR_DB_TYPE_RSL, 64, 1222, 6, 1304},
|
|
{"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1223, 8, 1310},
|
|
{"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 1224, 4, 1318},
|
|
{"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1225, 2, 1322},
|
|
{"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1226, 2, 1324},
|
|
{"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1227, 13, 1326},
|
|
{"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 1228, 12, 1339},
|
|
{"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 1229, 3, 1351},
|
|
{"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 1230, 3, 1354},
|
|
{"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 1231, 2, 1357},
|
|
{"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 1233, 2, 1359},
|
|
{"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 1235, 2, 1361},
|
|
{"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1237, 7, 1363},
|
|
{"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 1239, 2, 1370},
|
|
{"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 1241, 7, 1372},
|
|
{"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 1243, 4, 1379},
|
|
{"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1245, 8, 1383},
|
|
{"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 1247, 9, 1391},
|
|
{"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1249, 7, 1400},
|
|
{"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 1251, 9, 1407},
|
|
{"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 1253, 2, 1416},
|
|
{"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1255, 2, 1418},
|
|
{"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 1257, 4, 1420},
|
|
{"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1259, 2, 1424},
|
|
{"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 1261, 2, 1426},
|
|
{"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 1263, 2, 1428},
|
|
{"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 1265, 4, 1430},
|
|
{"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 1267, 2, 1434},
|
|
{"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 1269, 2, 1436},
|
|
{"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 1271, 2, 1438},
|
|
{"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1273, 2, 1440},
|
|
{"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 1275, 2, 1442},
|
|
{"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1277, 2, 1444},
|
|
{"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 1279, 6, 1446},
|
|
{"cvmx_npi_base_addr_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 1281, 2, 1452},
|
|
{"cvmx_npi_base_addr_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1285, 2, 1454},
|
|
{"cvmx_npi_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1289, 21, 1456},
|
|
{"cvmx_npi_buff_size_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1290, 3, 1477},
|
|
{"cvmx_npi_comp_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1294, 3, 1480},
|
|
{"cvmx_npi_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1295, 21, 1483},
|
|
{"cvmx_npi_dbg_select" , CVMX_CSR_DB_TYPE_NCB, 64, 1296, 2, 1504},
|
|
{"cvmx_npi_dma_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1297, 13, 1506},
|
|
{"cvmx_npi_dma_highp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 1298, 3, 1519},
|
|
{"cvmx_npi_dma_highp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1299, 3, 1522},
|
|
{"cvmx_npi_dma_lowp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 1300, 3, 1525},
|
|
{"cvmx_npi_dma_lowp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1301, 3, 1528},
|
|
{"cvmx_npi_highp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 1302, 2, 1531},
|
|
{"cvmx_npi_highp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1303, 2, 1533},
|
|
{"cvmx_npi_input_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1304, 10, 1535},
|
|
{"cvmx_npi_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 1305, 63, 1545},
|
|
{"cvmx_npi_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 1306, 63, 1608},
|
|
{"cvmx_npi_lowp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 1307, 2, 1671},
|
|
{"cvmx_npi_lowp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1308, 2, 1673},
|
|
{"cvmx_npi_mem_access_subid#" , CVMX_CSR_DB_TYPE_NCB, 64, 1309, 10, 1675},
|
|
{"cvmx_npi_msi_rcv" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1313, 1, 1685},
|
|
{"cvmx_npi_num_desc_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1314, 2, 1686},
|
|
{"cvmx_npi_output_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1318, 39, 1688},
|
|
{"cvmx_npi_p#_dbpair_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 1319, 3, 1727},
|
|
{"cvmx_npi_p#_instr_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 1323, 2, 1730},
|
|
{"cvmx_npi_p#_instr_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 1327, 3, 1732},
|
|
{"cvmx_npi_p#_pair_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 1331, 3, 1735},
|
|
{"cvmx_npi_pci_burst_size" , CVMX_CSR_DB_TYPE_NCB, 64, 1335, 3, 1738},
|
|
{"cvmx_npi_pci_int_arb_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 1336, 7, 1741},
|
|
{"cvmx_npi_pci_read_cmd" , CVMX_CSR_DB_TYPE_NCB, 64, 1337, 2, 1748},
|
|
{"cvmx_npi_port32_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1338, 13, 1750},
|
|
{"cvmx_npi_port33_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1339, 13, 1763},
|
|
{"cvmx_npi_port34_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1340, 13, 1776},
|
|
{"cvmx_npi_port35_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1341, 13, 1789},
|
|
{"cvmx_npi_port_bp_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1342, 3, 1802},
|
|
{"cvmx_npi_rsl_int_blocks" , CVMX_CSR_DB_TYPE_NCB, 64, 1343, 33, 1805},
|
|
{"cvmx_npi_size_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 1344, 2, 1838},
|
|
{"cvmx_npi_win_read_to" , CVMX_CSR_DB_TYPE_NCB, 64, 1348, 2, 1840},
|
|
{"cvmx_pci_bar1_index#" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1349, 5, 1842},
|
|
{"cvmx_pci_cfg00" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1381, 2, 1847},
|
|
{"cvmx_pci_cfg01" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1382, 24, 1849},
|
|
{"cvmx_pci_cfg02" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1383, 2, 1873},
|
|
{"cvmx_pci_cfg03" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1384, 7, 1875},
|
|
{"cvmx_pci_cfg04" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1385, 5, 1882},
|
|
{"cvmx_pci_cfg05" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1386, 1, 1887},
|
|
{"cvmx_pci_cfg06" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1387, 5, 1888},
|
|
{"cvmx_pci_cfg07" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1388, 1, 1893},
|
|
{"cvmx_pci_cfg08" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1389, 4, 1894},
|
|
{"cvmx_pci_cfg09" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1390, 2, 1898},
|
|
{"cvmx_pci_cfg10" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1391, 1, 1900},
|
|
{"cvmx_pci_cfg11" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1392, 2, 1901},
|
|
{"cvmx_pci_cfg12" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1393, 4, 1903},
|
|
{"cvmx_pci_cfg13" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1394, 2, 1907},
|
|
{"cvmx_pci_cfg15" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1395, 4, 1909},
|
|
{"cvmx_pci_cfg16" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1396, 16, 1913},
|
|
{"cvmx_pci_cfg17" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1397, 1, 1929},
|
|
{"cvmx_pci_cfg18" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1398, 1, 1930},
|
|
{"cvmx_pci_cfg19" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1399, 18, 1931},
|
|
{"cvmx_pci_cfg20" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1400, 1, 1949},
|
|
{"cvmx_pci_cfg21" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1401, 1, 1950},
|
|
{"cvmx_pci_cfg22" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1402, 7, 1951},
|
|
{"cvmx_pci_cfg56" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1403, 7, 1958},
|
|
{"cvmx_pci_cfg57" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1404, 13, 1965},
|
|
{"cvmx_pci_cfg58" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1405, 10, 1978},
|
|
{"cvmx_pci_cfg59" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1406, 10, 1988},
|
|
{"cvmx_pci_cfg60" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1407, 7, 1998},
|
|
{"cvmx_pci_cfg61" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1408, 2, 2005},
|
|
{"cvmx_pci_cfg62" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1409, 1, 2007},
|
|
{"cvmx_pci_cfg63" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1410, 2, 2008},
|
|
{"cvmx_pci_cnt_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1411, 6, 2010},
|
|
{"cvmx_pci_ctl_status_2" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1412, 22, 2016},
|
|
{"cvmx_pci_dbell#" , CVMX_CSR_DB_TYPE_PCI, 32, 1413, 2, 2038},
|
|
{"cvmx_pci_dma_cnt#" , CVMX_CSR_DB_TYPE_PCI, 32, 1417, 1, 2040},
|
|
{"cvmx_pci_dma_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 1419, 1, 2041},
|
|
{"cvmx_pci_dma_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 1421, 1, 2042},
|
|
{"cvmx_pci_instr_count#" , CVMX_CSR_DB_TYPE_PCI, 32, 1423, 1, 2043},
|
|
{"cvmx_pci_int_enb" , CVMX_CSR_DB_TYPE_PCI, 64, 1427, 35, 2044},
|
|
{"cvmx_pci_int_enb2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1428, 35, 2079},
|
|
{"cvmx_pci_int_sum" , CVMX_CSR_DB_TYPE_PCI, 64, 1429, 35, 2114},
|
|
{"cvmx_pci_int_sum2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1430, 35, 2149},
|
|
{"cvmx_pci_msi_rcv" , CVMX_CSR_DB_TYPE_PCI, 32, 1431, 2, 2184},
|
|
{"cvmx_pci_pkt_credits#" , CVMX_CSR_DB_TYPE_PCI, 32, 1432, 2, 2186},
|
|
{"cvmx_pci_pkts_sent#" , CVMX_CSR_DB_TYPE_PCI, 32, 1436, 1, 2188},
|
|
{"cvmx_pci_pkts_sent_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 1440, 1, 2189},
|
|
{"cvmx_pci_pkts_sent_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 1444, 1, 2190},
|
|
{"cvmx_pci_read_cmd_6" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1448, 3, 2191},
|
|
{"cvmx_pci_read_cmd_c" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1449, 3, 2194},
|
|
{"cvmx_pci_read_cmd_e" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1450, 3, 2197},
|
|
{"cvmx_pci_read_timeout" , CVMX_CSR_DB_TYPE_NCB, 64, 1451, 3, 2200},
|
|
{"cvmx_pci_scm_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1452, 2, 2203},
|
|
{"cvmx_pci_tsr_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1453, 2, 2205},
|
|
{"cvmx_pci_win_rd_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 1454, 4, 2207},
|
|
{"cvmx_pci_win_rd_data" , CVMX_CSR_DB_TYPE_PCI, 64, 1455, 1, 2211},
|
|
{"cvmx_pci_win_wr_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 1456, 4, 2212},
|
|
{"cvmx_pci_win_wr_data" , CVMX_CSR_DB_TYPE_PCI, 64, 1457, 1, 2216},
|
|
{"cvmx_pci_win_wr_mask" , CVMX_CSR_DB_TYPE_PCI, 64, 1458, 2, 2217},
|
|
{"cvmx_pip_bck_prs" , CVMX_CSR_DB_TYPE_RSL, 64, 1459, 5, 2219},
|
|
{"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1460, 2, 2224},
|
|
{"cvmx_pip_crc_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 1461, 3, 2226},
|
|
{"cvmx_pip_crc_iv#" , CVMX_CSR_DB_TYPE_RSL, 64, 1463, 2, 2229},
|
|
{"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 1465, 4, 2231},
|
|
{"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1469, 8, 2235},
|
|
{"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1470, 16, 2243},
|
|
{"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1471, 10, 2259},
|
|
{"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1472, 10, 2269},
|
|
{"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 1473, 2, 2279},
|
|
{"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1474, 19, 2281},
|
|
{"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 1510, 25, 2300},
|
|
{"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 1546, 2, 2325},
|
|
{"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 1610, 2, 2327},
|
|
{"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 1618, 9, 2329},
|
|
{"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 1622, 2, 2338},
|
|
{"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 1623, 2, 2340},
|
|
{"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1624, 2, 2342},
|
|
{"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1660, 2, 2344},
|
|
{"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1696, 2, 2346},
|
|
{"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1732, 2, 2348},
|
|
{"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1768, 2, 2350},
|
|
{"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1804, 2, 2352},
|
|
{"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1840, 2, 2354},
|
|
{"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1876, 2, 2356},
|
|
{"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1912, 2, 2358},
|
|
{"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1948, 2, 2360},
|
|
{"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1984, 2, 2362},
|
|
{"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 1985, 2, 2364},
|
|
{"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 2021, 2, 2366},
|
|
{"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 2057, 2, 2368},
|
|
{"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 2093, 2, 2370},
|
|
{"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2157, 2, 2372},
|
|
{"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 2158, 3, 2374},
|
|
{"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 2159, 3, 2377},
|
|
{"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 2160, 2, 2380},
|
|
{"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 2161, 2, 2382},
|
|
{"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2162, 4, 2384},
|
|
{"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2163, 5, 2388},
|
|
{"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 2164, 4, 2393},
|
|
{"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 2165, 8, 2397},
|
|
{"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 2166, 4, 2405},
|
|
{"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 2167, 5, 2409},
|
|
{"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2168, 5, 2414},
|
|
{"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2169, 1, 2419},
|
|
{"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 2170, 18, 2420},
|
|
{"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 2171, 4, 2438},
|
|
{"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 2172, 2, 2442},
|
|
{"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 2173, 6, 2444},
|
|
{"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 2174, 7, 2450},
|
|
{"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 2175, 4, 2457},
|
|
{"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 2176, 9, 2461},
|
|
{"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 2177, 5, 2470},
|
|
{"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2178, 15, 2475},
|
|
{"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2179, 4, 2490},
|
|
{"cvmx_pko_reg_crc_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 2180, 3, 2494},
|
|
{"cvmx_pko_reg_crc_enable" , CVMX_CSR_DB_TYPE_RSL, 64, 2182, 2, 2497},
|
|
{"cvmx_pko_reg_crc_iv#" , CVMX_CSR_DB_TYPE_RSL, 64, 2183, 2, 2499},
|
|
{"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2185, 1, 2501},
|
|
{"cvmx_pko_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2186, 1, 2502},
|
|
{"cvmx_pko_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2187, 1, 2503},
|
|
{"cvmx_pko_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2188, 1, 2504},
|
|
{"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2189, 4, 2505},
|
|
{"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2190, 5, 2509},
|
|
{"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2191, 3, 2514},
|
|
{"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2192, 4, 2517},
|
|
{"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2193, 2, 2521},
|
|
{"cvmx_pko_reg_queue_ptrs1" , CVMX_CSR_DB_TYPE_RSL, 64, 2194, 3, 2523},
|
|
{"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2195, 3, 2526},
|
|
{"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 2196, 13, 2529},
|
|
{"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2197, 2, 2542},
|
|
{"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 2198, 13, 2544},
|
|
{"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 2199, 3, 2557},
|
|
{"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2200, 2, 2560},
|
|
{"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2208, 2, 2562},
|
|
{"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2209, 2, 2564},
|
|
{"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 2210, 2, 2566},
|
|
{"cvmx_pow_pf_rst_msk" , CVMX_CSR_DB_TYPE_NCB, 64, 2211, 2, 2568},
|
|
{"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 2212, 10, 2570},
|
|
{"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 2228, 5, 2580},
|
|
{"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2236, 8, 2585},
|
|
{"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2244, 2, 2593},
|
|
{"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2245, 2, 2595},
|
|
{"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2246, 2, 2597},
|
|
{"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 2254, 3, 2599},
|
|
{"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2255, 4, 2602},
|
|
{"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2271, 5, 2606},
|
|
{"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2272, 7, 2611},
|
|
{"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2288, 2, 2618},
|
|
{"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2304, 3, 2620},
|
|
{"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2305, 7, 2623},
|
|
{"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 2306, 8, 2630},
|
|
{"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2307, 6, 2638},
|
|
{"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2308, 2, 2644},
|
|
{"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2309, 4, 2646},
|
|
{"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2310, 4, 2650},
|
|
{"cvmx_spx#_bckprs_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2311, 2, 2654},
|
|
{"cvmx_spx#_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2313, 4, 2656},
|
|
{"cvmx_spx#_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2315, 11, 2660},
|
|
{"cvmx_spx#_clk_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2317, 9, 2671},
|
|
{"cvmx_spx#_dbg_deskew_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2319, 16, 2680},
|
|
{"cvmx_spx#_dbg_deskew_state" , CVMX_CSR_DB_TYPE_RSL, 64, 2321, 5, 2696},
|
|
{"cvmx_spx#_drv_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2323, 5, 2701},
|
|
{"cvmx_spx#_err_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2325, 6, 2706},
|
|
{"cvmx_spx#_int_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2327, 6, 2712},
|
|
{"cvmx_spx#_int_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2329, 12, 2718},
|
|
{"cvmx_spx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2331, 14, 2730},
|
|
{"cvmx_spx#_int_sync" , CVMX_CSR_DB_TYPE_RSL, 64, 2333, 12, 2744},
|
|
{"cvmx_spx#_tpa_acc" , CVMX_CSR_DB_TYPE_RSL, 64, 2335, 2, 2756},
|
|
{"cvmx_spx#_tpa_max" , CVMX_CSR_DB_TYPE_RSL, 64, 2337, 2, 2758},
|
|
{"cvmx_spx#_tpa_sel" , CVMX_CSR_DB_TYPE_RSL, 64, 2339, 2, 2760},
|
|
{"cvmx_spx#_trn4_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2341, 8, 2762},
|
|
{"cvmx_srx#_com_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2343, 5, 2770},
|
|
{"cvmx_srx#_ign_rx_full" , CVMX_CSR_DB_TYPE_RSL, 64, 2345, 2, 2775},
|
|
{"cvmx_srx#_spi4_cal#" , CVMX_CSR_DB_TYPE_RSL, 64, 2347, 6, 2777},
|
|
{"cvmx_srx#_spi4_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2411, 4, 2783},
|
|
{"cvmx_srx#_sw_tick_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2413, 6, 2787},
|
|
{"cvmx_srx#_sw_tick_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2415, 1, 2793},
|
|
{"cvmx_stx#_arb_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2417, 5, 2794},
|
|
{"cvmx_stx#_bckprs_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2419, 2, 2799},
|
|
{"cvmx_stx#_com_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2421, 4, 2801},
|
|
{"cvmx_stx#_dip_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2423, 3, 2805},
|
|
{"cvmx_stx#_ign_cal" , CVMX_CSR_DB_TYPE_RSL, 64, 2425, 2, 2808},
|
|
{"cvmx_stx#_int_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2427, 9, 2810},
|
|
{"cvmx_stx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2429, 10, 2819},
|
|
{"cvmx_stx#_int_sync" , CVMX_CSR_DB_TYPE_RSL, 64, 2431, 9, 2829},
|
|
{"cvmx_stx#_min_bst" , CVMX_CSR_DB_TYPE_RSL, 64, 2433, 2, 2838},
|
|
{"cvmx_stx#_spi4_cal#" , CVMX_CSR_DB_TYPE_RSL, 64, 2435, 6, 2840},
|
|
{"cvmx_stx#_spi4_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2499, 3, 2846},
|
|
{"cvmx_stx#_spi4_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2501, 4, 2849},
|
|
{"cvmx_stx#_stat_bytes_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 2503, 2, 2853},
|
|
{"cvmx_stx#_stat_bytes_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 2505, 2, 2855},
|
|
{"cvmx_stx#_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2507, 3, 2857},
|
|
{"cvmx_stx#_stat_pkt_xmt" , CVMX_CSR_DB_TYPE_RSL, 64, 2509, 2, 2860},
|
|
{"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2511, 6, 2862},
|
|
{"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2512, 3, 2868},
|
|
{"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2513, 5, 2871},
|
|
{"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 2514, 4, 2876},
|
|
{"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 2515, 6, 2880},
|
|
{"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2516, 4, 2886},
|
|
{"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2517, 2, 2890},
|
|
{"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2518, 4, 2892},
|
|
{"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2519, 2, 2896},
|
|
{"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2520, 3, 2898},
|
|
{"cvmx_tra_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2521, 4, 2901},
|
|
{"cvmx_tra_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2522, 12, 2905},
|
|
{"cvmx_tra_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 2523, 3, 2917},
|
|
{"cvmx_tra_cycles_since1" , CVMX_CSR_DB_TYPE_RSL, 64, 2524, 5, 2920},
|
|
{"cvmx_tra_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2525, 2, 2925},
|
|
{"cvmx_tra_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2526, 2, 2927},
|
|
{"cvmx_tra_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2527, 18, 2929},
|
|
{"cvmx_tra_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2528, 12, 2947},
|
|
{"cvmx_tra_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2529, 6, 2959},
|
|
{"cvmx_tra_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2530, 5, 2965},
|
|
{"cvmx_tra_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2531, 1, 2970},
|
|
{"cvmx_tra_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2532, 2, 2971},
|
|
{"cvmx_tra_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2533, 2, 2973},
|
|
{"cvmx_tra_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2534, 18, 2975},
|
|
{"cvmx_tra_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2535, 12, 2993},
|
|
{"cvmx_tra_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2536, 6, 3005},
|
|
{"cvmx_tra_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2537, 2, 3011},
|
|
{"cvmx_tra_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2538, 2, 3013},
|
|
{"cvmx_tra_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2539, 18, 3015},
|
|
{"cvmx_tra_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2540, 12, 3033},
|
|
{"cvmx_tra_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2541, 6, 3045},
|
|
{"cvmx_zip_cmd_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2542, 3, 3051},
|
|
{"cvmx_zip_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2543, 5, 3054},
|
|
{"cvmx_zip_cmd_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2544, 3, 3059},
|
|
{"cvmx_zip_constants" , CVMX_CSR_DB_TYPE_RSL, 64, 2545, 6, 3062},
|
|
{"cvmx_zip_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2546, 2, 3068},
|
|
{"cvmx_zip_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2547, 2, 3070},
|
|
{"cvmx_zip_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2548, 2, 3072},
|
|
{NULL,0,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
|
|
/* name , --------------address, ---------------type, bits, csr offset */
|
|
{"ASX0_INT_EN" , 0x11800B0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
|
|
{"ASX1_INT_EN" , 0x11800B8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
|
|
{"ASX0_INT_REG" , 0x11800B0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
|
|
{"ASX1_INT_REG" , 0x11800B8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
|
|
{"ASX0_PRT_LOOP" , 0x11800B0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
|
|
{"ASX1_PRT_LOOP" , 0x11800B8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
|
|
{"ASX0_RLD_BYPASS" , 0x11800B0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
|
|
{"ASX1_RLD_BYPASS" , 0x11800B8000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
|
|
{"ASX0_RLD_BYPASS_SETTING" , 0x11800B0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
|
|
{"ASX1_RLD_BYPASS_SETTING" , 0x11800B8000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
|
|
{"ASX0_RLD_COMP" , 0x11800B0000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
|
|
{"ASX1_RLD_COMP" , 0x11800B8000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
|
|
{"ASX0_RLD_DATA_DRV" , 0x11800B0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
|
|
{"ASX1_RLD_DATA_DRV" , 0x11800B8000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
|
|
{"ASX0_RLD_NCTL_STRONG" , 0x11800B0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
|
|
{"ASX1_RLD_NCTL_STRONG" , 0x11800B8000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
|
|
{"ASX0_RLD_NCTL_WEAK" , 0x11800B0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
|
|
{"ASX1_RLD_NCTL_WEAK" , 0x11800B8000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
|
|
{"ASX0_RLD_PCTL_STRONG" , 0x11800B0000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
|
|
{"ASX1_RLD_PCTL_STRONG" , 0x11800B8000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
|
|
{"ASX0_RLD_PCTL_WEAK" , 0x11800B0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
|
|
{"ASX1_RLD_PCTL_WEAK" , 0x11800B8000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
|
|
{"ASX0_RLD_SETTING" , 0x11800B0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
|
|
{"ASX1_RLD_SETTING" , 0x11800B8000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
|
|
{"ASX0_RX_CLK_SET000" , 0x11800B0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"ASX0_RX_CLK_SET001" , 0x11800B0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"ASX0_RX_CLK_SET002" , 0x11800B0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"ASX0_RX_CLK_SET003" , 0x11800B0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"ASX1_RX_CLK_SET000" , 0x11800B8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"ASX1_RX_CLK_SET001" , 0x11800B8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"ASX1_RX_CLK_SET002" , 0x11800B8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"ASX1_RX_CLK_SET003" , 0x11800B8000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"ASX0_RX_PRT_EN" , 0x11800B0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"ASX1_RX_PRT_EN" , 0x11800B8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"ASX0_TX_CLK_SET000" , 0x11800B0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"ASX0_TX_CLK_SET001" , 0x11800B0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"ASX0_TX_CLK_SET002" , 0x11800B0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"ASX0_TX_CLK_SET003" , 0x11800B0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"ASX1_TX_CLK_SET000" , 0x11800B8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"ASX1_TX_CLK_SET001" , 0x11800B8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"ASX1_TX_CLK_SET002" , 0x11800B8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"ASX1_TX_CLK_SET003" , 0x11800B8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"ASX0_TX_COMP_BYP" , 0x11800B0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
|
|
{"ASX1_TX_COMP_BYP" , 0x11800B8000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
|
|
{"ASX0_TX_HI_WATER000" , 0x11800B0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"ASX0_TX_HI_WATER001" , 0x11800B0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"ASX0_TX_HI_WATER002" , 0x11800B0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"ASX0_TX_HI_WATER003" , 0x11800B0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"ASX1_TX_HI_WATER000" , 0x11800B8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"ASX1_TX_HI_WATER001" , 0x11800B8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"ASX1_TX_HI_WATER002" , 0x11800B8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"ASX1_TX_HI_WATER003" , 0x11800B8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"ASX0_TX_PRT_EN" , 0x11800B0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
|
|
{"ASX1_TX_PRT_EN" , 0x11800B8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
|
|
{"ASX0_DBG_DATA_DRV" , 0x11800B0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
|
|
{"ASX0_DBG_DATA_ENABLE" , 0x11800B0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
|
|
{"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
|
|
{"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 21},
|
|
{"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 22},
|
|
{"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 23},
|
|
{"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT4_EN0" , 0x1070000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT5_EN0" , 0x1070000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT6_EN0" , 0x1070000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT7_EN0" , 0x1070000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT8_EN0" , 0x1070000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT9_EN0" , 0x1070000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT10_EN0" , 0x10700000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT11_EN0" , 0x10700000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT12_EN0" , 0x10700000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT13_EN0" , 0x10700000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT14_EN0" , 0x10700000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT15_EN0" , 0x10700000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT16_EN0" , 0x1070000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT17_EN0" , 0x1070000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT18_EN0" , 0x1070000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT19_EN0" , 0x1070000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT20_EN0" , 0x1070000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT21_EN0" , 0x1070000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT22_EN0" , 0x1070000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT23_EN0" , 0x1070000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT24_EN0" , 0x1070000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT25_EN0" , 0x1070000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT26_EN0" , 0x10700000003A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT27_EN0" , 0x10700000003B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT28_EN0" , 0x10700000003C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT29_EN0" , 0x10700000003D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT30_EN0" , 0x10700000003E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT31_EN0" , 0x10700000003F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT4_EN1" , 0x1070000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT5_EN1" , 0x1070000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT6_EN1" , 0x1070000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT7_EN1" , 0x1070000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT8_EN1" , 0x1070000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT9_EN1" , 0x1070000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT10_EN1" , 0x10700000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT11_EN1" , 0x10700000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT12_EN1" , 0x10700000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT13_EN1" , 0x10700000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT14_EN1" , 0x10700000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT15_EN1" , 0x10700000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT16_EN1" , 0x1070000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT17_EN1" , 0x1070000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT18_EN1" , 0x1070000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT19_EN1" , 0x1070000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT20_EN1" , 0x1070000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT21_EN1" , 0x1070000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT22_EN1" , 0x1070000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT23_EN1" , 0x1070000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT24_EN1" , 0x1070000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT25_EN1" , 0x1070000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT26_EN1" , 0x10700000003A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT27_EN1" , 0x10700000003B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT28_EN1" , 0x10700000003C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT29_EN1" , 0x10700000003D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT30_EN1" , 0x10700000003E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT31_EN1" , 0x10700000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT0_EN4_0" , 0x1070000000C80ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT1_EN4_0" , 0x1070000000C90ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT2_EN4_0" , 0x1070000000CA0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT3_EN4_0" , 0x1070000000CB0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT4_EN4_0" , 0x1070000000CC0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT5_EN4_0" , 0x1070000000CD0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT6_EN4_0" , 0x1070000000CE0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT7_EN4_0" , 0x1070000000CF0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT8_EN4_0" , 0x1070000000D00ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT9_EN4_0" , 0x1070000000D10ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT10_EN4_0" , 0x1070000000D20ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT11_EN4_0" , 0x1070000000D30ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT12_EN4_0" , 0x1070000000D40ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT13_EN4_0" , 0x1070000000D50ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT14_EN4_0" , 0x1070000000D60ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT15_EN4_0" , 0x1070000000D70ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT0_EN4_1" , 0x1070000000C88ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT1_EN4_1" , 0x1070000000C98ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT2_EN4_1" , 0x1070000000CA8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT3_EN4_1" , 0x1070000000CB8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT4_EN4_1" , 0x1070000000CC8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT5_EN4_1" , 0x1070000000CD8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT6_EN4_1" , 0x1070000000CE8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT7_EN4_1" , 0x1070000000CF8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT8_EN4_1" , 0x1070000000D08ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT9_EN4_1" , 0x1070000000D18ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT10_EN4_1" , 0x1070000000D28ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT11_EN4_1" , 0x1070000000D38ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT12_EN4_1" , 0x1070000000D48ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT13_EN4_1" , 0x1070000000D58ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT14_EN4_1" , 0x1070000000D68ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT15_EN4_1" , 0x1070000000D78ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT4_SUM0" , 0x1070000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT5_SUM0" , 0x1070000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT6_SUM0" , 0x1070000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT7_SUM0" , 0x1070000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT8_SUM0" , 0x1070000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT9_SUM0" , 0x1070000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT10_SUM0" , 0x1070000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT11_SUM0" , 0x1070000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT12_SUM0" , 0x1070000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT13_SUM0" , 0x1070000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT14_SUM0" , 0x1070000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT15_SUM0" , 0x1070000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT16_SUM0" , 0x1070000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT17_SUM0" , 0x1070000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT18_SUM0" , 0x1070000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT19_SUM0" , 0x1070000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT20_SUM0" , 0x10700000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT21_SUM0" , 0x10700000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT22_SUM0" , 0x10700000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT23_SUM0" , 0x10700000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT24_SUM0" , 0x10700000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT25_SUM0" , 0x10700000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT26_SUM0" , 0x10700000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT27_SUM0" , 0x10700000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT28_SUM0" , 0x10700000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT29_SUM0" , 0x10700000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT30_SUM0" , 0x10700000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT31_SUM0" , 0x10700000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT0_SUM4" , 0x1070000000C00ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT1_SUM4" , 0x1070000000C08ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT2_SUM4" , 0x1070000000C10ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT3_SUM4" , 0x1070000000C18ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT4_SUM4" , 0x1070000000C20ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT5_SUM4" , 0x1070000000C28ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT6_SUM4" , 0x1070000000C30ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT7_SUM4" , 0x1070000000C38ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT8_SUM4" , 0x1070000000C40ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT9_SUM4" , 0x1070000000C48ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT10_SUM4" , 0x1070000000C50ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT11_SUM4" , 0x1070000000C58ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT12_SUM4" , 0x1070000000C60ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT13_SUM4" , 0x1070000000C68ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT14_SUM4" , 0x1070000000C70ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT15_SUM4" , 0x1070000000C78ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_MBOX_CLR2" , 0x1070000000690ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_MBOX_CLR3" , 0x1070000000698ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_MBOX_CLR4" , 0x10700000006A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_MBOX_CLR5" , 0x10700000006A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_MBOX_CLR6" , 0x10700000006B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_MBOX_CLR7" , 0x10700000006B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_MBOX_CLR8" , 0x10700000006C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_MBOX_CLR9" , 0x10700000006C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_MBOX_CLR10" , 0x10700000006D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_MBOX_CLR11" , 0x10700000006D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_MBOX_CLR12" , 0x10700000006E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_MBOX_CLR13" , 0x10700000006E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_MBOX_CLR14" , 0x10700000006F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_MBOX_CLR15" , 0x10700000006F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_MBOX_SET2" , 0x1070000000610ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_MBOX_SET3" , 0x1070000000618ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_MBOX_SET4" , 0x1070000000620ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_MBOX_SET5" , 0x1070000000628ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_MBOX_SET6" , 0x1070000000630ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_MBOX_SET7" , 0x1070000000638ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_MBOX_SET8" , 0x1070000000640ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_MBOX_SET9" , 0x1070000000648ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_MBOX_SET10" , 0x1070000000650ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_MBOX_SET11" , 0x1070000000658ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_MBOX_SET12" , 0x1070000000660ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_MBOX_SET13" , 0x1070000000668ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_MBOX_SET14" , 0x1070000000670ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_MBOX_SET15" , 0x1070000000678ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
|
|
{"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_PP_POKE2" , 0x1070000000590ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_PP_POKE3" , 0x1070000000598ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_PP_POKE4" , 0x10700000005A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_PP_POKE5" , 0x10700000005A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_PP_POKE6" , 0x10700000005B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_PP_POKE7" , 0x10700000005B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_PP_POKE8" , 0x10700000005C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_PP_POKE9" , 0x10700000005C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_PP_POKE10" , 0x10700000005D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_PP_POKE11" , 0x10700000005D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_PP_POKE12" , 0x10700000005E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_PP_POKE13" , 0x10700000005E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_PP_POKE14" , 0x10700000005F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_PP_POKE15" , 0x10700000005F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
|
|
{"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
|
|
{"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
|
|
{"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 41},
|
|
{"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 41},
|
|
{"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 41},
|
|
{"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 41},
|
|
{"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
|
|
{"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
|
|
{"CIU_WDOG2" , 0x1070000000510ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
|
|
{"CIU_WDOG3" , 0x1070000000518ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
|
|
{"CIU_WDOG4" , 0x1070000000520ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
|
|
{"CIU_WDOG5" , 0x1070000000528ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
|
|
{"CIU_WDOG6" , 0x1070000000530ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
|
|
{"CIU_WDOG7" , 0x1070000000538ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
|
|
{"CIU_WDOG8" , 0x1070000000540ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
|
|
{"CIU_WDOG9" , 0x1070000000548ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
|
|
{"CIU_WDOG10" , 0x1070000000550ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
|
|
{"CIU_WDOG11" , 0x1070000000558ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
|
|
{"CIU_WDOG12" , 0x1070000000560ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
|
|
{"CIU_WDOG13" , 0x1070000000568ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
|
|
{"CIU_WDOG14" , 0x1070000000570ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
|
|
{"CIU_WDOG15" , 0x1070000000578ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
|
|
{"DBG_DATA" , 0x11F00000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
|
|
{"DFA_BST0" , 0x11800300007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
|
|
{"DFA_BST1" , 0x11800300007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
|
|
{"DFA_CFG" , 0x1180030000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
|
|
{"DFA_DBELL" , 0x1370000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 47},
|
|
{"DFA_DIFCTL" , 0x1370600000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 48},
|
|
{"DFA_DIFRDPTR" , 0x1370200000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 49},
|
|
{"DFA_ERR" , 0x1180030000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
|
|
{"DFA_MEMCFG0" , 0x1180030000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
|
|
{"DFA_MEMCFG1" , 0x1180030000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
|
|
{"DFA_MEMCFG2" , 0x1180030000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
|
|
{"DFA_MEMFADR" , 0x1180030000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
|
|
{"DFA_MEMFCR" , 0x1180030000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
|
|
{"DFA_MEMRLD" , 0x1180030000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
|
|
{"DFA_NCBCTL" , 0x1180030000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
|
|
{"DFA_RODT_COMP_CTL" , 0x1180030000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
|
|
{"DFA_SBD_DBG0" , 0x1180030000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
|
|
{"DFA_SBD_DBG1" , 0x1180030000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
|
|
{"DFA_SBD_DBG2" , 0x1180030000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
|
|
{"DFA_SBD_DBG3" , 0x1180030000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
|
|
{"FPA_BIST_STATUS" , 0x11800280000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
|
|
{"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
|
|
{"FPA_FPF1_MARKS" , 0x1180028000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
|
|
{"FPA_FPF2_MARKS" , 0x1180028000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
|
|
{"FPA_FPF3_MARKS" , 0x1180028000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
|
|
{"FPA_FPF4_MARKS" , 0x1180028000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
|
|
{"FPA_FPF5_MARKS" , 0x1180028000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
|
|
{"FPA_FPF6_MARKS" , 0x1180028000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
|
|
{"FPA_FPF7_MARKS" , 0x1180028000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
|
|
{"FPA_FPF1_SIZE" , 0x1180028000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"FPA_FPF2_SIZE" , 0x1180028000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"FPA_FPF3_SIZE" , 0x1180028000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"FPA_FPF4_SIZE" , 0x1180028000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"FPA_FPF5_SIZE" , 0x1180028000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"FPA_FPF6_SIZE" , 0x1180028000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"FPA_FPF7_SIZE" , 0x1180028000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"FPA_FPF0_MARKS" , 0x1180028000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"FPA_FPF0_SIZE" , 0x1180028000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
|
|
{"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
|
|
{"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
|
|
{"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
|
|
{"FPA_QUE1_AVAILABLE" , 0x11800280000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
|
|
{"FPA_QUE2_AVAILABLE" , 0x11800280000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
|
|
{"FPA_QUE3_AVAILABLE" , 0x11800280000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
|
|
{"FPA_QUE4_AVAILABLE" , 0x11800280000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
|
|
{"FPA_QUE5_AVAILABLE" , 0x11800280000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
|
|
{"FPA_QUE6_AVAILABLE" , 0x11800280000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
|
|
{"FPA_QUE7_AVAILABLE" , 0x11800280000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
|
|
{"FPA_QUE0_PAGE_INDEX" , 0x11800280000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_QUE1_PAGE_INDEX" , 0x11800280000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
|
|
{"FPA_WART_CTL" , 0x11800280000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
|
|
{"FPA_WART_STATUS" , 0x11800280000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
|
|
{"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
|
|
{"GMX1_BAD_REG" , 0x1180010000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
|
|
{"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
|
|
{"GMX1_BIST" , 0x1180010000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
|
|
{"GMX0_INF_MODE" , 0x11800080007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
|
|
{"GMX1_INF_MODE" , 0x11800100007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
|
|
{"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
|
|
{"GMX1_NXA_ADR" , 0x1180010000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
|
|
{"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
|
|
{"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
|
|
{"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
|
|
{"GMX0_PRT003_CFG" , 0x1180008001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
|
|
{"GMX1_PRT000_CFG" , 0x1180010000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
|
|
{"GMX1_PRT001_CFG" , 0x1180010000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
|
|
{"GMX1_PRT002_CFG" , 0x1180010001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
|
|
{"GMX1_PRT003_CFG" , 0x1180010001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
|
|
{"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX0_RX003_ADR_CAM0" , 0x1180008001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX1_RX000_ADR_CAM0" , 0x1180010000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX1_RX001_ADR_CAM0" , 0x1180010000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX1_RX002_ADR_CAM0" , 0x1180010001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX1_RX003_ADR_CAM0" , 0x1180010001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX0_RX003_ADR_CAM1" , 0x1180008001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX1_RX000_ADR_CAM1" , 0x1180010000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX1_RX001_ADR_CAM1" , 0x1180010000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX1_RX002_ADR_CAM1" , 0x1180010001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX1_RX003_ADR_CAM1" , 0x1180010001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX0_RX003_ADR_CAM2" , 0x1180008001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX1_RX000_ADR_CAM2" , 0x1180010000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX1_RX001_ADR_CAM2" , 0x1180010000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX1_RX002_ADR_CAM2" , 0x1180010001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX1_RX003_ADR_CAM2" , 0x1180010001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX0_RX003_ADR_CAM3" , 0x1180008001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX1_RX000_ADR_CAM3" , 0x1180010000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX1_RX001_ADR_CAM3" , 0x1180010000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX1_RX002_ADR_CAM3" , 0x1180010001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX1_RX003_ADR_CAM3" , 0x1180010001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX0_RX000_ADR_CAM4" , 0x11800080001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX0_RX001_ADR_CAM4" , 0x11800080009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX0_RX002_ADR_CAM4" , 0x11800080011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX0_RX003_ADR_CAM4" , 0x11800080019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX1_RX000_ADR_CAM4" , 0x11800100001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX1_RX001_ADR_CAM4" , 0x11800100009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX1_RX002_ADR_CAM4" , 0x11800100011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX1_RX003_ADR_CAM4" , 0x11800100019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX0_RX000_ADR_CAM5" , 0x11800080001A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX0_RX001_ADR_CAM5" , 0x11800080009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX0_RX002_ADR_CAM5" , 0x11800080011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX0_RX003_ADR_CAM5" , 0x11800080019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX1_RX000_ADR_CAM5" , 0x11800100001A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX1_RX001_ADR_CAM5" , 0x11800100009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX1_RX002_ADR_CAM5" , 0x11800100011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX1_RX003_ADR_CAM5" , 0x11800100019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX0_RX003_ADR_CAM_EN" , 0x1180008001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX1_RX000_ADR_CAM_EN" , 0x1180010000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX1_RX001_ADR_CAM_EN" , 0x1180010000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX1_RX002_ADR_CAM_EN" , 0x1180010001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX1_RX003_ADR_CAM_EN" , 0x1180010001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_RX003_ADR_CTL" , 0x1180008001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX1_RX000_ADR_CTL" , 0x1180010000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX1_RX001_ADR_CTL" , 0x1180010000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX1_RX002_ADR_CTL" , 0x1180010001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX1_RX003_ADR_CTL" , 0x1180010001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_RX003_DECISION" , 0x1180008001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX1_RX000_DECISION" , 0x1180010000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX1_RX001_DECISION" , 0x1180010000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX1_RX002_DECISION" , 0x1180010001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX1_RX003_DECISION" , 0x1180010001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_RX003_FRM_CHK" , 0x1180008001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX1_RX000_FRM_CHK" , 0x1180010000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX1_RX001_FRM_CHK" , 0x1180010000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX1_RX002_FRM_CHK" , 0x1180010001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX1_RX003_FRM_CHK" , 0x1180010001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_RX003_FRM_CTL" , 0x1180008001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX1_RX000_FRM_CTL" , 0x1180010000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX1_RX001_FRM_CTL" , 0x1180010000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX1_RX002_FRM_CTL" , 0x1180010001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX1_RX003_FRM_CTL" , 0x1180010001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_RX000_FRM_MAX" , 0x1180008000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_RX001_FRM_MAX" , 0x1180008000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_RX002_FRM_MAX" , 0x1180008001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_RX003_FRM_MAX" , 0x1180008001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX1_RX000_FRM_MAX" , 0x1180010000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX1_RX001_FRM_MAX" , 0x1180010000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX1_RX002_FRM_MAX" , 0x1180010001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX1_RX003_FRM_MAX" , 0x1180010001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_RX000_FRM_MIN" , 0x1180008000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_RX001_FRM_MIN" , 0x1180008000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_RX002_FRM_MIN" , 0x1180008001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_RX003_FRM_MIN" , 0x1180008001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX1_RX000_FRM_MIN" , 0x1180010000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX1_RX001_FRM_MIN" , 0x1180010000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX1_RX002_FRM_MIN" , 0x1180010001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX1_RX003_FRM_MIN" , 0x1180010001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_RX003_IFG" , 0x1180008001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX1_RX000_IFG" , 0x1180010000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX1_RX001_IFG" , 0x1180010000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX1_RX002_IFG" , 0x1180010001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX1_RX003_IFG" , 0x1180010001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_RX003_INT_EN" , 0x1180008001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX1_RX000_INT_EN" , 0x1180010000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX1_RX001_INT_EN" , 0x1180010000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX1_RX002_INT_EN" , 0x1180010001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX1_RX003_INT_EN" , 0x1180010001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_RX003_INT_REG" , 0x1180008001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX1_RX000_INT_REG" , 0x1180010000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX1_RX001_INT_REG" , 0x1180010000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX1_RX002_INT_REG" , 0x1180010001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX1_RX003_INT_REG" , 0x1180010001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_RX003_JABBER" , 0x1180008001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX1_RX000_JABBER" , 0x1180010000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX1_RX001_JABBER" , 0x1180010000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX1_RX002_JABBER" , 0x1180010001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX1_RX003_JABBER" , 0x1180010001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_RX000_PAUSE_DROP_TIME" , 0x1180008000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_RX001_PAUSE_DROP_TIME" , 0x1180008000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_RX002_PAUSE_DROP_TIME" , 0x1180008001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_RX003_PAUSE_DROP_TIME" , 0x1180008001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX1_RX000_PAUSE_DROP_TIME" , 0x1180010000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX1_RX001_PAUSE_DROP_TIME" , 0x1180010000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX1_RX002_PAUSE_DROP_TIME" , 0x1180010001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX1_RX003_PAUSE_DROP_TIME" , 0x1180010001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_RX000_RX_INBND" , 0x1180008000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_RX001_RX_INBND" , 0x1180008000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_RX002_RX_INBND" , 0x1180008001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_RX003_RX_INBND" , 0x1180008001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX1_RX000_RX_INBND" , 0x1180010000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX1_RX001_RX_INBND" , 0x1180010000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX1_RX002_RX_INBND" , 0x1180010001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX1_RX003_RX_INBND" , 0x1180010001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX0_RX003_STATS_CTL" , 0x1180008001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX1_RX000_STATS_CTL" , 0x1180010000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX1_RX001_STATS_CTL" , 0x1180010000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX1_RX002_STATS_CTL" , 0x1180010001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX1_RX003_STATS_CTL" , 0x1180010001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX0_RX003_STATS_OCTS" , 0x1180008001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX1_RX000_STATS_OCTS" , 0x1180010000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX1_RX001_STATS_OCTS" , 0x1180010000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX1_RX002_STATS_OCTS" , 0x1180010001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX1_RX003_STATS_OCTS" , 0x1180010001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX0_RX003_STATS_OCTS_CTL" , 0x1180008001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX1_RX000_STATS_OCTS_CTL" , 0x1180010000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX1_RX001_STATS_OCTS_CTL" , 0x1180010000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX1_RX002_STATS_OCTS_CTL" , 0x1180010001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX1_RX003_STATS_OCTS_CTL" , 0x1180010001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_RX003_STATS_OCTS_DMAC" , 0x11800080018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX1_RX000_STATS_OCTS_DMAC" , 0x11800100000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX1_RX001_STATS_OCTS_DMAC" , 0x11800100008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX1_RX002_STATS_OCTS_DMAC" , 0x11800100010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX1_RX003_STATS_OCTS_DMAC" , 0x11800100018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX0_RX003_STATS_OCTS_DRP" , 0x11800080018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX1_RX000_STATS_OCTS_DRP" , 0x11800100000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX1_RX001_STATS_OCTS_DRP" , 0x11800100008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX1_RX002_STATS_OCTS_DRP" , 0x11800100010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX1_RX003_STATS_OCTS_DRP" , 0x11800100018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_RX003_STATS_PKTS" , 0x1180008001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX1_RX000_STATS_PKTS" , 0x1180010000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX1_RX001_STATS_PKTS" , 0x1180010000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX1_RX002_STATS_PKTS" , 0x1180010001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX1_RX003_STATS_PKTS" , 0x1180010001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_RX003_STATS_PKTS_BAD" , 0x11800080018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX1_RX000_STATS_PKTS_BAD" , 0x11800100000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX1_RX001_STATS_PKTS_BAD" , 0x11800100008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX1_RX002_STATS_PKTS_BAD" , 0x11800100010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX1_RX003_STATS_PKTS_BAD" , 0x11800100018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX0_RX003_STATS_PKTS_CTL" , 0x1180008001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX1_RX000_STATS_PKTS_CTL" , 0x1180010000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX1_RX001_STATS_PKTS_CTL" , 0x1180010000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX1_RX002_STATS_PKTS_CTL" , 0x1180010001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX1_RX003_STATS_PKTS_CTL" , 0x1180010001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_RX003_STATS_PKTS_DMAC" , 0x11800080018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX1_RX000_STATS_PKTS_DMAC" , 0x11800100000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX1_RX001_STATS_PKTS_DMAC" , 0x11800100008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX1_RX002_STATS_PKTS_DMAC" , 0x11800100010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX1_RX003_STATS_PKTS_DMAC" , 0x11800100018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX0_RX003_STATS_PKTS_DRP" , 0x11800080018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX1_RX000_STATS_PKTS_DRP" , 0x11800100000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX1_RX001_STATS_PKTS_DRP" , 0x11800100008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX1_RX002_STATS_PKTS_DRP" , 0x11800100010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX1_RX003_STATS_PKTS_DRP" , 0x11800100018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX0_RX003_UDD_SKP" , 0x1180008001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX1_RX000_UDD_SKP" , 0x1180010000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX1_RX001_UDD_SKP" , 0x1180010000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX1_RX002_UDD_SKP" , 0x1180010001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX1_RX003_UDD_SKP" , 0x1180010001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX0_RX_BP_DROP003" , 0x1180008000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX1_RX_BP_DROP000" , 0x1180010000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX1_RX_BP_DROP001" , 0x1180010000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX1_RX_BP_DROP002" , 0x1180010000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX1_RX_BP_DROP003" , 0x1180010000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX0_RX_BP_OFF003" , 0x1180008000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX1_RX_BP_OFF000" , 0x1180010000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX1_RX_BP_OFF001" , 0x1180010000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX1_RX_BP_OFF002" , 0x1180010000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX1_RX_BP_OFF003" , 0x1180010000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_RX_BP_ON003" , 0x1180008000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX1_RX_BP_ON000" , 0x1180010000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX1_RX_BP_ON001" , 0x1180010000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX1_RX_BP_ON002" , 0x1180010000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX1_RX_BP_ON003" , 0x1180010000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_RX_PASS_EN" , 0x11800080005F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX1_RX_PASS_EN" , 0x11800100005F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX0_RX_PASS_MAP000" , 0x1180008000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP001" , 0x1180008000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP002" , 0x1180008000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP003" , 0x1180008000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP004" , 0x1180008000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP005" , 0x1180008000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP006" , 0x1180008000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP007" , 0x1180008000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP008" , 0x1180008000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP009" , 0x1180008000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP010" , 0x1180008000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP011" , 0x1180008000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP012" , 0x1180008000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP013" , 0x1180008000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP014" , 0x1180008000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PASS_MAP015" , 0x1180008000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP000" , 0x1180010000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP001" , 0x1180010000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP002" , 0x1180010000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP003" , 0x1180010000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP004" , 0x1180010000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP005" , 0x1180010000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP006" , 0x1180010000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP007" , 0x1180010000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP008" , 0x1180010000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP009" , 0x1180010000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP010" , 0x1180010000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP011" , 0x1180010000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP012" , 0x1180010000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP013" , 0x1180010000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP014" , 0x1180010000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX_PASS_MAP015" , 0x1180010000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX_PRT_INFO" , 0x11800080004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX1_RX_PRT_INFO" , 0x11800100004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX1_RX_PRTS" , 0x1180010000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_SMAC001" , 0x1180008000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_SMAC003" , 0x1180008001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX1_SMAC000" , 0x1180010000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX1_SMAC001" , 0x1180010000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX1_SMAC002" , 0x1180010001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX1_SMAC003" , 0x1180010001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX1_STAT_BP" , 0x1180010000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_TX001_APPEND" , 0x1180008000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_TX003_APPEND" , 0x1180008001A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX1_TX000_APPEND" , 0x1180010000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX1_TX001_APPEND" , 0x1180010000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX1_TX002_APPEND" , 0x1180010001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX1_TX003_APPEND" , 0x1180010001A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_TX001_BURST" , 0x1180008000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_TX003_BURST" , 0x1180008001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX1_TX000_BURST" , 0x1180010000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX1_TX001_BURST" , 0x1180010000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX1_TX002_BURST" , 0x1180010001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX1_TX003_BURST" , 0x1180010001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_TX000_CLK" , 0x1180008000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_TX001_CLK" , 0x1180008000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_TX002_CLK" , 0x1180008001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_TX003_CLK" , 0x1180008001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX1_TX000_CLK" , 0x1180010000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX1_TX001_CLK" , 0x1180010000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX1_TX002_CLK" , 0x1180010001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX1_TX003_CLK" , 0x1180010001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_TX001_CTL" , 0x1180008000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_TX003_CTL" , 0x1180008001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_TX000_CTL" , 0x1180010000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_TX001_CTL" , 0x1180010000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_TX002_CTL" , 0x1180010001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_TX003_CTL" , 0x1180010001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_TX001_MIN_PKT" , 0x1180008000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_TX003_MIN_PKT" , 0x1180008001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX1_TX000_MIN_PKT" , 0x1180010000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX1_TX001_MIN_PKT" , 0x1180010000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX1_TX002_MIN_PKT" , 0x1180010001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX1_TX003_MIN_PKT" , 0x1180010001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_TX003_PAUSE_PKT_INTERVAL", 0x1180008001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX1_TX000_PAUSE_PKT_INTERVAL", 0x1180010000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX1_TX001_PAUSE_PKT_INTERVAL", 0x1180010000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX1_TX002_PAUSE_PKT_INTERVAL", 0x1180010001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX1_TX003_PAUSE_PKT_INTERVAL", 0x1180010001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_TX003_PAUSE_PKT_TIME" , 0x1180008001A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX1_TX000_PAUSE_PKT_TIME" , 0x1180010000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX1_TX001_PAUSE_PKT_TIME" , 0x1180010000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX1_TX002_PAUSE_PKT_TIME" , 0x1180010001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX1_TX003_PAUSE_PKT_TIME" , 0x1180010001A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_TX001_PAUSE_TOGO" , 0x1180008000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_TX003_PAUSE_TOGO" , 0x1180008001A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX1_TX000_PAUSE_TOGO" , 0x1180010000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX1_TX001_PAUSE_TOGO" , 0x1180010000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX1_TX002_PAUSE_TOGO" , 0x1180010001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX1_TX003_PAUSE_TOGO" , 0x1180010001A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_TX001_PAUSE_ZERO" , 0x1180008000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_TX003_PAUSE_ZERO" , 0x1180008001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX1_TX000_PAUSE_ZERO" , 0x1180010000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX1_TX001_PAUSE_ZERO" , 0x1180010000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX1_TX002_PAUSE_ZERO" , 0x1180010001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX1_TX003_PAUSE_ZERO" , 0x1180010001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_TX001_SLOT" , 0x1180008000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_TX003_SLOT" , 0x1180008001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX1_TX000_SLOT" , 0x1180010000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX1_TX001_SLOT" , 0x1180010000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX1_TX002_SLOT" , 0x1180010001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX1_TX003_SLOT" , 0x1180010001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_TX001_SOFT_PAUSE" , 0x1180008000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_TX003_SOFT_PAUSE" , 0x1180008001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX1_TX000_SOFT_PAUSE" , 0x1180010000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX1_TX001_SOFT_PAUSE" , 0x1180010000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX1_TX002_SOFT_PAUSE" , 0x1180010001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX1_TX003_SOFT_PAUSE" , 0x1180010001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_TX001_STAT0" , 0x1180008000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_TX003_STAT0" , 0x1180008001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX1_TX000_STAT0" , 0x1180010000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX1_TX001_STAT0" , 0x1180010000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX1_TX002_STAT0" , 0x1180010001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX1_TX003_STAT0" , 0x1180010001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_TX001_STAT1" , 0x1180008000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_TX003_STAT1" , 0x1180008001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX1_TX000_STAT1" , 0x1180010000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX1_TX001_STAT1" , 0x1180010000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX1_TX002_STAT1" , 0x1180010001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX1_TX003_STAT1" , 0x1180010001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_TX001_STAT2" , 0x1180008000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_TX003_STAT2" , 0x1180008001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX1_TX000_STAT2" , 0x1180010000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX1_TX001_STAT2" , 0x1180010000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX1_TX002_STAT2" , 0x1180010001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX1_TX003_STAT2" , 0x1180010001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_TX001_STAT3" , 0x1180008000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_TX003_STAT3" , 0x1180008001A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX1_TX000_STAT3" , 0x1180010000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX1_TX001_STAT3" , 0x1180010000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX1_TX002_STAT3" , 0x1180010001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX1_TX003_STAT3" , 0x1180010001A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_TX000_STAT4" , 0x11800080002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_TX001_STAT4" , 0x1180008000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_TX002_STAT4" , 0x11800080012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_TX003_STAT4" , 0x1180008001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX1_TX000_STAT4" , 0x11800100002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX1_TX001_STAT4" , 0x1180010000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX1_TX002_STAT4" , 0x11800100012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX1_TX003_STAT4" , 0x1180010001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_TX000_STAT5" , 0x11800080002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_TX001_STAT5" , 0x1180008000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_TX002_STAT5" , 0x11800080012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_TX003_STAT5" , 0x1180008001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX1_TX000_STAT5" , 0x11800100002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX1_TX001_STAT5" , 0x1180010000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX1_TX002_STAT5" , 0x11800100012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX1_TX003_STAT5" , 0x1180010001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_TX000_STAT6" , 0x11800080002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_TX001_STAT6" , 0x1180008000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_TX002_STAT6" , 0x11800080012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_TX003_STAT6" , 0x1180008001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX1_TX000_STAT6" , 0x11800100002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX1_TX001_STAT6" , 0x1180010000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX1_TX002_STAT6" , 0x11800100012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX1_TX003_STAT6" , 0x1180010001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_TX000_STAT7" , 0x11800080002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_TX001_STAT7" , 0x1180008000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_TX002_STAT7" , 0x11800080012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_TX003_STAT7" , 0x1180008001AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX1_TX000_STAT7" , 0x11800100002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX1_TX001_STAT7" , 0x1180010000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX1_TX002_STAT7" , 0x11800100012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX1_TX003_STAT7" , 0x1180010001AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_TX000_STAT8" , 0x11800080002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_TX001_STAT8" , 0x1180008000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_TX002_STAT8" , 0x11800080012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_TX003_STAT8" , 0x1180008001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX1_TX000_STAT8" , 0x11800100002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX1_TX001_STAT8" , 0x1180010000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX1_TX002_STAT8" , 0x11800100012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX1_TX003_STAT8" , 0x1180010001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_TX000_STAT9" , 0x11800080002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_TX001_STAT9" , 0x1180008000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_TX002_STAT9" , 0x11800080012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_TX003_STAT9" , 0x1180008001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX1_TX000_STAT9" , 0x11800100002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX1_TX001_STAT9" , 0x1180010000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX1_TX002_STAT9" , 0x11800100012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX1_TX003_STAT9" , 0x1180010001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_TX001_STATS_CTL" , 0x1180008000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_TX003_STATS_CTL" , 0x1180008001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX1_TX000_STATS_CTL" , 0x1180010000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX1_TX001_STATS_CTL" , 0x1180010000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX1_TX002_STATS_CTL" , 0x1180010001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX1_TX003_STATS_CTL" , 0x1180010001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_TX001_THRESH" , 0x1180008000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_TX003_THRESH" , 0x1180008001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX1_TX000_THRESH" , 0x1180010000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX1_TX001_THRESH" , 0x1180010000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX1_TX002_THRESH" , 0x1180010001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX1_TX003_THRESH" , 0x1180010001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_TX_BP" , 0x11800080004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX1_TX_BP" , 0x11800100004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX1_TX_COL_ATTEMPT" , 0x1180010000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX0_TX_CORRUPT" , 0x11800080004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX1_TX_CORRUPT" , 0x11800100004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX1_TX_IFG" , 0x1180010000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX1_TX_INT_EN" , 0x1180010000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX1_TX_INT_REG" , 0x1180010000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX1_TX_JAM" , 0x1180010000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX0_TX_LFSR" , 0x11800080004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX1_TX_LFSR" , 0x11800100004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX0_TX_OVR_BP" , 0x11800080004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX1_TX_OVR_BP" , 0x11800100004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX1_TX_PAUSE_PKT_DMAC" , 0x11800100004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX1_TX_PAUSE_PKT_TYPE" , 0x11800100004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX1_TX_PRTS" , 0x1180010000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX0_TX_SPI_CTL" , 0x11800080004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX1_TX_SPI_CTL" , 0x11800100004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX0_TX_SPI_DRAIN" , 0x11800080004E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX1_TX_SPI_DRAIN" , 0x11800100004E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX0_TX_SPI_MAX" , 0x11800080004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
|
|
{"GMX1_TX_SPI_MAX" , 0x11800100004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
|
|
{"GMX0_TX_SPI_ROUND000" , 0x1180008000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND001" , 0x1180008000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND002" , 0x1180008000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND003" , 0x1180008000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND004" , 0x11800080006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND005" , 0x11800080006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND006" , 0x11800080006B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND007" , 0x11800080006B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND008" , 0x11800080006C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND009" , 0x11800080006C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND010" , 0x11800080006D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND011" , 0x11800080006D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND012" , 0x11800080006E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND013" , 0x11800080006E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND014" , 0x11800080006F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND015" , 0x11800080006F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND016" , 0x1180008000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND017" , 0x1180008000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND018" , 0x1180008000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND019" , 0x1180008000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND020" , 0x1180008000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND021" , 0x1180008000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND022" , 0x1180008000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND023" , 0x1180008000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND024" , 0x1180008000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND025" , 0x1180008000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND026" , 0x1180008000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND027" , 0x1180008000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND028" , 0x1180008000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND029" , 0x1180008000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND030" , 0x1180008000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_ROUND031" , 0x1180008000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND000" , 0x1180010000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND001" , 0x1180010000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND002" , 0x1180010000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND003" , 0x1180010000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND004" , 0x11800100006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND005" , 0x11800100006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND006" , 0x11800100006B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND007" , 0x11800100006B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND008" , 0x11800100006C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND009" , 0x11800100006C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND010" , 0x11800100006D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND011" , 0x11800100006D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND012" , 0x11800100006E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND013" , 0x11800100006E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND014" , 0x11800100006F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND015" , 0x11800100006F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND016" , 0x1180010000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND017" , 0x1180010000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND018" , 0x1180010000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND019" , 0x1180010000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND020" , 0x1180010000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND021" , 0x1180010000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND022" , 0x1180010000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND023" , 0x1180010000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND024" , 0x1180010000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND025" , 0x1180010000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND026" , 0x1180010000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND027" , 0x1180010000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND028" , 0x1180010000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND029" , 0x1180010000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND030" , 0x1180010000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_SPI_ROUND031" , 0x1180010000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_SPI_THRESH" , 0x11800080004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
|
|
{"GMX1_TX_SPI_THRESH" , 0x11800100004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
|
|
{"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
|
|
{"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
|
|
{"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
|
|
{"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
|
|
{"IOB_BIST_STATUS" , 0x11800F00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"IOB_CTL_STATUS" , 0x11800F0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"IOB_DWB_PRI_CNT" , 0x11800F0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
|
|
{"IOB_FAU_TIMEOUT" , 0x11800F0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"IOB_I2C_PRI_CNT" , 0x11800F0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"IOB_INB_CONTROL_MATCH" , 0x11800F0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"IOB_INB_CONTROL_MATCH_ENB" , 0x11800F0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"IOB_INB_DATA_MATCH" , 0x11800F0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"IOB_INB_DATA_MATCH_ENB" , 0x11800F0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"IOB_INT_ENB" , 0x11800F0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"IOB_INT_SUM" , 0x11800F0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"IOB_N2C_L2C_PRI_CNT" , 0x11800F0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
|
|
{"IOB_N2C_RSP_PRI_CNT" , 0x11800F0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
|
|
{"IOB_OUTB_COM_PRI_CNT" , 0x11800F0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
|
|
{"IOB_OUTB_CONTROL_MATCH" , 0x11800F0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
|
|
{"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800F00000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
|
|
{"IOB_OUTB_DATA_MATCH" , 0x11800F0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
|
|
{"IOB_OUTB_DATA_MATCH_ENB" , 0x11800F00000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
|
|
{"IOB_OUTB_FPA_PRI_CNT" , 0x11800F0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
|
|
{"IOB_OUTB_REQ_PRI_CNT" , 0x11800F0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
|
|
{"IOB_P2C_REQ_PRI_CNT" , 0x11800F0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
|
|
{"IOB_PKT_ERR" , 0x11800F0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
|
|
{"IPD_1ST_MBUFF_SKIP" , 0x14F0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 188},
|
|
{"IPD_1ST_NEXT_PTR_BACK" , 0x14F0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 189},
|
|
{"IPD_2ND_NEXT_PTR_BACK" , 0x14F0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 190},
|
|
{"IPD_BIST_STATUS" , 0x14F00000007F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"IPD_BP_PRT_RED_END" , 0x14F0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
|
|
{"IPD_CLK_COUNT" , 0x14F0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 193},
|
|
{"IPD_CTL_STATUS" , 0x14F0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 194},
|
|
{"IPD_INT_ENB" , 0x14F0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 195},
|
|
{"IPD_INT_SUM" , 0x14F0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_NOT_1ST_MBUFF_SKIP" , 0x14F0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_PACKET_MBUFF_SIZE" , 0x14F0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 198},
|
|
{"IPD_PKT_PTR_VALID" , 0x14F0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_PORT0_BP_PAGE_CNT" , 0x14F0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT1_BP_PAGE_CNT" , 0x14F0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT2_BP_PAGE_CNT" , 0x14F0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT3_BP_PAGE_CNT" , 0x14F0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT4_BP_PAGE_CNT" , 0x14F0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT5_BP_PAGE_CNT" , 0x14F0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT6_BP_PAGE_CNT" , 0x14F0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT7_BP_PAGE_CNT" , 0x14F0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT8_BP_PAGE_CNT" , 0x14F0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT9_BP_PAGE_CNT" , 0x14F0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT10_BP_PAGE_CNT" , 0x14F0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT11_BP_PAGE_CNT" , 0x14F0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT12_BP_PAGE_CNT" , 0x14F0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT13_BP_PAGE_CNT" , 0x14F0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT14_BP_PAGE_CNT" , 0x14F0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT15_BP_PAGE_CNT" , 0x14F00000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT16_BP_PAGE_CNT" , 0x14F00000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT17_BP_PAGE_CNT" , 0x14F00000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT18_BP_PAGE_CNT" , 0x14F00000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT19_BP_PAGE_CNT" , 0x14F00000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT20_BP_PAGE_CNT" , 0x14F00000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT21_BP_PAGE_CNT" , 0x14F00000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT22_BP_PAGE_CNT" , 0x14F00000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT23_BP_PAGE_CNT" , 0x14F00000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT24_BP_PAGE_CNT" , 0x14F00000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT25_BP_PAGE_CNT" , 0x14F00000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT26_BP_PAGE_CNT" , 0x14F00000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT27_BP_PAGE_CNT" , 0x14F0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT28_BP_PAGE_CNT" , 0x14F0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT29_BP_PAGE_CNT" , 0x14F0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT30_BP_PAGE_CNT" , 0x14F0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT31_BP_PAGE_CNT" , 0x14F0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT32_BP_PAGE_CNT" , 0x14F0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT33_BP_PAGE_CNT" , 0x14F0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT34_BP_PAGE_CNT" , 0x14F0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT35_BP_PAGE_CNT" , 0x14F0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14F00000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14F00000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14F00000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR3" , 0x14F00000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR4" , 0x14F00000001D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR5" , 0x14F00000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR6" , 0x14F00000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR7" , 0x14F00000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR8" , 0x14F00000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR9" , 0x14F0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR10" , 0x14F0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR11" , 0x14F0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR12" , 0x14F0000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR13" , 0x14F0000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR14" , 0x14F0000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR15" , 0x14F0000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR16" , 0x14F0000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR17" , 0x14F0000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR18" , 0x14F0000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR19" , 0x14F0000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR20" , 0x14F0000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR21" , 0x14F0000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR22" , 0x14F0000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR23" , 0x14F0000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR24" , 0x14F0000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR25" , 0x14F0000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR26" , 0x14F0000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR27" , 0x14F0000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR28" , 0x14F0000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR29" , 0x14F00000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR30" , 0x14F00000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR31" , 0x14F00000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14F00000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR33" , 0x14F00000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR34" , 0x14F00000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR35" , 0x14F00000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14F0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14F0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
|
|
{"IPD_PTR_COUNT" , 0x14F0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
|
|
{"IPD_PWP_PTR_FIFO_CTL" , 0x14F0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
|
|
{"IPD_QOS0_RED_MARKS" , 0x14F0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"IPD_QOS1_RED_MARKS" , 0x14F0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"IPD_QOS2_RED_MARKS" , 0x14F0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"IPD_QOS3_RED_MARKS" , 0x14F0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"IPD_QOS4_RED_MARKS" , 0x14F0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"IPD_QOS5_RED_MARKS" , 0x14F00000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"IPD_QOS6_RED_MARKS" , 0x14F00000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"IPD_QOS7_RED_MARKS" , 0x14F00000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"IPD_QUE0_FREE_PAGE_CNT" , 0x14F0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
|
|
{"IPD_RED_PORT_ENABLE" , 0x14F00000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_RED_QUE0_PARAM" , 0x14F00000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_RED_QUE1_PARAM" , 0x14F00000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_RED_QUE2_PARAM" , 0x14F00000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_RED_QUE3_PARAM" , 0x14F00000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_RED_QUE4_PARAM" , 0x14F0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_RED_QUE5_PARAM" , 0x14F0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_RED_QUE6_PARAM" , 0x14F0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_RED_QUE7_PARAM" , 0x14F0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14F0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
|
|
{"IPD_SUB_PORT_FCS" , 0x14F0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
|
|
{"IPD_WQE_FPA_QUEUE" , 0x14F0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
|
|
{"IPD_WQE_PTR_VALID" , 0x14F0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
|
|
{"KEY_BIST_REG" , 0x1180020000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
|
|
{"KEY_CTL_STATUS" , 0x1180020000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
|
|
{"KEY_INT_ENB" , 0x1180020000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
|
|
{"KEY_INT_SUM" , 0x1180020000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
|
|
{"L2C_BST0" , 0x11800800007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
|
|
{"L2C_BST1" , 0x11800800007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
|
|
{"L2C_BST2" , 0x11800800007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
|
|
{"L2C_CFG" , 0x1180080000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
|
|
{"L2C_DBG" , 0x1180080000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
|
|
{"L2C_DUT" , 0x1180080000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
|
|
{"L2C_LCKBASE" , 0x1180080000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
|
|
{"L2C_LCKOFF" , 0x1180080000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
|
|
{"L2C_LFB0" , 0x1180080000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
|
|
{"L2C_LFB1" , 0x1180080000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
|
|
{"L2C_LFB2" , 0x1180080000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
|
|
{"L2C_LFB3" , 0x11800800000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
|
|
{"L2C_PFC0" , 0x1180080000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
|
|
{"L2C_PFC1" , 0x11800800000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
|
|
{"L2C_PFC2" , 0x11800800000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
|
|
{"L2C_PFC3" , 0x11800800000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
|
|
{"L2C_PFCTL" , 0x1180080000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
|
|
{"L2C_SPAR0" , 0x1180080000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
|
|
{"L2C_SPAR1" , 0x1180080000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
|
|
{"L2C_SPAR2" , 0x1180080000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
|
|
{"L2C_SPAR3" , 0x1180080000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
|
|
{"L2C_SPAR4" , 0x1180080000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
|
|
{"L2D_BST0" , 0x1180080000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
|
|
{"L2D_BST1" , 0x1180080000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
|
|
{"L2D_BST2" , 0x1180080000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
|
|
{"L2D_BST3" , 0x1180080000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
|
|
{"L2D_ERR" , 0x1180080000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
|
|
{"L2D_FADR" , 0x1180080000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
|
|
{"L2D_FSYN0" , 0x1180080000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
|
|
{"L2D_FSYN1" , 0x1180080000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
|
|
{"L2D_FUS0" , 0x11800800007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
|
|
{"L2D_FUS1" , 0x11800800007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
|
|
{"L2D_FUS2" , 0x11800800007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
|
|
{"L2D_FUS3" , 0x11800800007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
|
|
{"L2T_ERR" , 0x1180080000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
|
|
{"LED_BLINK" , 0x1180000001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
|
|
{"LED_CLK_PHASE" , 0x1180000001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
|
|
{"LED_CYLON" , 0x1180000001AF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
|
|
{"LED_DBG" , 0x1180000001A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
|
|
{"LED_EN" , 0x1180000001A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
|
|
{"LED_POLARITY" , 0x1180000001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
|
|
{"LED_PRT" , 0x1180000001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
|
|
{"LED_PRT_FMT" , 0x1180000001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
|
|
{"LED_PRT_STATUS0" , 0x1180000001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
|
|
{"LED_PRT_STATUS1" , 0x1180000001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
|
|
{"LED_PRT_STATUS2" , 0x1180000001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
|
|
{"LED_PRT_STATUS3" , 0x1180000001A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
|
|
{"LED_PRT_STATUS4" , 0x1180000001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
|
|
{"LED_PRT_STATUS5" , 0x1180000001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
|
|
{"LED_PRT_STATUS6" , 0x1180000001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
|
|
{"LED_PRT_STATUS7" , 0x1180000001AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
|
|
{"LED_UDD_CNT0" , 0x1180000001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
|
|
{"LED_UDD_CNT1" , 0x1180000001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
|
|
{"LED_UDD_DAT0" , 0x1180000001A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
|
|
{"LED_UDD_DAT1" , 0x1180000001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
|
|
{"LED_UDD_DAT_CLR0" , 0x1180000001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
|
|
{"LED_UDD_DAT_CLR1" , 0x1180000001AD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
|
|
{"LED_UDD_DAT_SET0" , 0x1180000001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
|
|
{"LED_UDD_DAT_SET1" , 0x1180000001AD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
|
|
{"LMC0_COMP_CTL" , 0x1180088000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
|
|
{"LMC0_CTL" , 0x1180088000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
|
|
{"LMC0_CTL1" , 0x1180088000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
|
|
{"LMC0_DCLK_CNT_HI" , 0x1180088000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
|
|
{"LMC0_DCLK_CNT_LO" , 0x1180088000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
|
|
{"LMC0_DDR2_CTL" , 0x1180088000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
|
|
{"LMC0_DELAY_CFG" , 0x1180088000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
|
|
{"LMC0_DUAL_MEMCFG" , 0x1180088000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
|
|
{"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
|
|
{"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
|
|
{"LMC0_IFB_CNT_HI" , 0x1180088000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
|
|
{"LMC0_IFB_CNT_LO" , 0x1180088000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
|
|
{"LMC0_MEM_CFG0" , 0x1180088000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
|
|
{"LMC0_MEM_CFG1" , 0x1180088000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
|
|
{"LMC0_OPS_CNT_HI" , 0x1180088000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
|
|
{"LMC0_OPS_CNT_LO" , 0x1180088000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
|
|
{"LMC0_PLL_CTL" , 0x11800880000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
|
|
{"LMC0_PLL_STATUS" , 0x11800880000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
|
|
{"LMC0_RODT_COMP_CTL" , 0x11800880000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
|
|
{"LMC0_RODT_CTL" , 0x1180088000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
|
|
{"LMC0_WODT_CTL0" , 0x1180088000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
|
|
{"MIO_BOOT_BIST_STAT" , 0x11800000000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
|
|
{"MIO_BOOT_ERR" , 0x11800000000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
|
|
{"MIO_BOOT_INT" , 0x11800000000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
|
|
{"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
|
|
{"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
|
|
{"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
|
|
{"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 289},
|
|
{"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
|
|
{"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
|
|
{"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
|
|
{"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
|
|
{"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
|
|
{"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
|
|
{"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
|
|
{"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
|
|
{"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
|
|
{"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
|
|
{"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
|
|
{"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
|
|
{"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
|
|
{"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
|
|
{"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
|
|
{"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
|
|
{"MIO_BOOT_THR" , 0x11800000000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
|
|
{"MIO_FUS_BNK_DAT0" , 0x1180000001520ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
|
|
{"MIO_FUS_BNK_DAT1" , 0x1180000001528ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
|
|
{"MIO_FUS_BNK_DAT2" , 0x1180000001530ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
|
|
{"MIO_FUS_BNK_DAT3" , 0x1180000001538ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
|
|
{"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
|
|
{"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
|
|
{"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
|
|
{"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
|
|
{"MIO_FUS_EMA" , 0x1180000001550ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
|
|
{"MIO_FUS_PLL" , 0x1180000001580ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
|
|
{"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
|
|
{"MIO_FUS_PROG_TIMES" , 0x1180000001518ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
|
|
{"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
|
|
{"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
|
|
{"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
|
|
{"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
|
|
{"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
|
|
{"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
|
|
{"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
|
|
{"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
|
|
{"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
|
|
{"MIO_UART1_DLH" , 0x1180000000C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
|
|
{"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
|
|
{"MIO_UART1_DLL" , 0x1180000000C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
|
|
{"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
|
|
{"MIO_UART1_FAR" , 0x1180000000D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
|
|
{"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
|
|
{"MIO_UART1_FCR" , 0x1180000000C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
|
|
{"MIO_UART0_HTX" , 0x1180000000B08ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
|
|
{"MIO_UART1_HTX" , 0x1180000000F08ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
|
|
{"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
|
|
{"MIO_UART1_IER" , 0x1180000000C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
|
|
{"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
|
|
{"MIO_UART1_IIR" , 0x1180000000C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
|
|
{"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
|
|
{"MIO_UART1_LCR" , 0x1180000000C18ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
|
|
{"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
|
|
{"MIO_UART1_LSR" , 0x1180000000C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
|
|
{"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
|
|
{"MIO_UART1_MCR" , 0x1180000000C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
|
|
{"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
|
|
{"MIO_UART1_MSR" , 0x1180000000C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
|
|
{"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
|
|
{"MIO_UART1_RBR" , 0x1180000000C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
|
|
{"MIO_UART0_RFL" , 0x1180000000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
|
|
{"MIO_UART1_RFL" , 0x1180000000E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
|
|
{"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
|
|
{"MIO_UART1_RFW" , 0x1180000000D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
|
|
{"MIO_UART0_SBCR" , 0x1180000000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
|
|
{"MIO_UART1_SBCR" , 0x1180000000E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
|
|
{"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
|
|
{"MIO_UART1_SCR" , 0x1180000000C38ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
|
|
{"MIO_UART0_SFE" , 0x1180000000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
|
|
{"MIO_UART1_SFE" , 0x1180000000E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
|
|
{"MIO_UART0_SRR" , 0x1180000000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
|
|
{"MIO_UART1_SRR" , 0x1180000000E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
|
|
{"MIO_UART0_SRT" , 0x1180000000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 328},
|
|
{"MIO_UART1_SRT" , 0x1180000000E38ull, CVMX_CSR_DB_TYPE_RSL, 64, 328},
|
|
{"MIO_UART0_SRTS" , 0x1180000000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
|
|
{"MIO_UART1_SRTS" , 0x1180000000E18ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
|
|
{"MIO_UART0_STT" , 0x1180000000B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
|
|
{"MIO_UART1_STT" , 0x1180000000F00ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
|
|
{"MIO_UART0_TFL" , 0x1180000000A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 331},
|
|
{"MIO_UART1_TFL" , 0x1180000000E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 331},
|
|
{"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
|
|
{"MIO_UART1_TFR" , 0x1180000000D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
|
|
{"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
|
|
{"MIO_UART1_THR" , 0x1180000000C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
|
|
{"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 334},
|
|
{"MIO_UART1_USR" , 0x1180000000D38ull, CVMX_CSR_DB_TYPE_RSL, 64, 334},
|
|
{"NPI_BASE_ADDR_INPUT0" , 0x11F0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 335},
|
|
{"NPI_BASE_ADDR_INPUT1" , 0x11F0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 335},
|
|
{"NPI_BASE_ADDR_INPUT2" , 0x11F0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 335},
|
|
{"NPI_BASE_ADDR_INPUT3" , 0x11F00000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 335},
|
|
{"NPI_BASE_ADDR_OUTPUT0" , 0x11F00000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
|
|
{"NPI_BASE_ADDR_OUTPUT1" , 0x11F00000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
|
|
{"NPI_BASE_ADDR_OUTPUT2" , 0x11F00000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
|
|
{"NPI_BASE_ADDR_OUTPUT3" , 0x11F00000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 336},
|
|
{"NPI_BIST_STATUS" , 0x11F00000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 337},
|
|
{"NPI_BUFF_SIZE_OUTPUT0" , 0x11F00000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
|
|
{"NPI_BUFF_SIZE_OUTPUT1" , 0x11F00000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
|
|
{"NPI_BUFF_SIZE_OUTPUT2" , 0x11F00000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
|
|
{"NPI_BUFF_SIZE_OUTPUT3" , 0x11F00000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 338},
|
|
{"NPI_COMP_CTL" , 0x11F0000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 339},
|
|
{"NPI_CTL_STATUS" , 0x11F0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 340},
|
|
{"NPI_DBG_SELECT" , 0x11F0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 341},
|
|
{"NPI_DMA_CONTROL" , 0x11F0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 342},
|
|
{"NPI_DMA_HIGHP_COUNTS" , 0x11F0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 343},
|
|
{"NPI_DMA_HIGHP_NADDR" , 0x11F0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 344},
|
|
{"NPI_DMA_LOWP_COUNTS" , 0x11F0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
|
|
{"NPI_DMA_LOWP_NADDR" , 0x11F0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 346},
|
|
{"NPI_HIGHP_DBELL" , 0x11F0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 347},
|
|
{"NPI_HIGHP_IBUFF_SADDR" , 0x11F0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 348},
|
|
{"NPI_INPUT_CONTROL" , 0x11F0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
|
|
{"NPI_INT_ENB" , 0x11F0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
|
|
{"NPI_INT_SUM" , 0x11F0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
|
|
{"NPI_LOWP_DBELL" , 0x11F0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 352},
|
|
{"NPI_LOWP_IBUFF_SADDR" , 0x11F0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 353},
|
|
{"NPI_MEM_ACCESS_SUBID3" , 0x11F0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
|
|
{"NPI_MEM_ACCESS_SUBID4" , 0x11F0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
|
|
{"NPI_MEM_ACCESS_SUBID5" , 0x11F0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
|
|
{"NPI_MEM_ACCESS_SUBID6" , 0x11F0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
|
|
{"NPI_MSI_RCV" , 0x11F0000001190ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 355},
|
|
{"NPI_NUM_DESC_OUTPUT0" , 0x11F0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 356},
|
|
{"NPI_NUM_DESC_OUTPUT1" , 0x11F0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 356},
|
|
{"NPI_NUM_DESC_OUTPUT2" , 0x11F0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 356},
|
|
{"NPI_NUM_DESC_OUTPUT3" , 0x11F0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 356},
|
|
{"NPI_OUTPUT_CONTROL" , 0x11F0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 357},
|
|
{"NPI_P0_DBPAIR_ADDR" , 0x11F0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 358},
|
|
{"NPI_P1_DBPAIR_ADDR" , 0x11F0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 358},
|
|
{"NPI_P2_DBPAIR_ADDR" , 0x11F0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 358},
|
|
{"NPI_P3_DBPAIR_ADDR" , 0x11F0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 358},
|
|
{"NPI_P0_INSTR_ADDR" , 0x11F00000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 359},
|
|
{"NPI_P1_INSTR_ADDR" , 0x11F00000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 359},
|
|
{"NPI_P2_INSTR_ADDR" , 0x11F00000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 359},
|
|
{"NPI_P3_INSTR_ADDR" , 0x11F00000001D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 359},
|
|
{"NPI_P0_INSTR_CNTS" , 0x11F00000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 360},
|
|
{"NPI_P1_INSTR_CNTS" , 0x11F00000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 360},
|
|
{"NPI_P2_INSTR_CNTS" , 0x11F00000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 360},
|
|
{"NPI_P3_INSTR_CNTS" , 0x11F00000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 360},
|
|
{"NPI_P0_PAIR_CNTS" , 0x11F0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 361},
|
|
{"NPI_P1_PAIR_CNTS" , 0x11F0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 361},
|
|
{"NPI_P2_PAIR_CNTS" , 0x11F0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 361},
|
|
{"NPI_P3_PAIR_CNTS" , 0x11F0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 361},
|
|
{"NPI_PCI_BURST_SIZE" , 0x11F00000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 362},
|
|
{"NPI_PCI_INT_ARB_CFG" , 0x11F0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 363},
|
|
{"NPI_PCI_READ_CMD" , 0x11F0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 364},
|
|
{"NPI_PORT32_INSTR_HDR" , 0x11F00000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 365},
|
|
{"NPI_PORT33_INSTR_HDR" , 0x11F0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 366},
|
|
{"NPI_PORT34_INSTR_HDR" , 0x11F0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 367},
|
|
{"NPI_PORT35_INSTR_HDR" , 0x11F0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 368},
|
|
{"NPI_PORT_BP_CONTROL" , 0x11F00000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 369},
|
|
{"NPI_RSL_INT_BLOCKS" , 0x11F0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 370},
|
|
{"NPI_SIZE_INPUT0" , 0x11F0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
|
|
{"NPI_SIZE_INPUT1" , 0x11F0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
|
|
{"NPI_SIZE_INPUT2" , 0x11F0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
|
|
{"NPI_SIZE_INPUT3" , 0x11F00000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
|
|
{"NPI_WIN_READ_TO" , 0x11F00000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 372},
|
|
{"PCI_BAR1_INDEX0" , 0x11F0000001100ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX1" , 0x11F0000001104ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX2" , 0x11F0000001108ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX3" , 0x11F000000110Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX4" , 0x11F0000001110ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX5" , 0x11F0000001114ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX6" , 0x11F0000001118ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX7" , 0x11F000000111Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX8" , 0x11F0000001120ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX9" , 0x11F0000001124ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX10" , 0x11F0000001128ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX11" , 0x11F000000112Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX12" , 0x11F0000001130ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX13" , 0x11F0000001134ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX14" , 0x11F0000001138ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX15" , 0x11F000000113Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX16" , 0x11F0000001140ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX17" , 0x11F0000001144ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX18" , 0x11F0000001148ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX19" , 0x11F000000114Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX20" , 0x11F0000001150ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX21" , 0x11F0000001154ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX22" , 0x11F0000001158ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX23" , 0x11F000000115Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX24" , 0x11F0000001160ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX25" , 0x11F0000001164ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX26" , 0x11F0000001168ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX27" , 0x11F000000116Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX28" , 0x11F0000001170ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX29" , 0x11F0000001174ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX30" , 0x11F0000001178ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_BAR1_INDEX31" , 0x11F000000117Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 373},
|
|
{"PCI_CFG00" , 0x11F0000001800ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 374},
|
|
{"PCI_CFG01" , 0x11F0000001804ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 375},
|
|
{"PCI_CFG02" , 0x11F0000001808ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 376},
|
|
{"PCI_CFG03" , 0x11F000000180Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 377},
|
|
{"PCI_CFG04" , 0x11F0000001810ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 378},
|
|
{"PCI_CFG05" , 0x11F0000001814ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 379},
|
|
{"PCI_CFG06" , 0x11F0000001818ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 380},
|
|
{"PCI_CFG07" , 0x11F000000181Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 381},
|
|
{"PCI_CFG08" , 0x11F0000001820ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 382},
|
|
{"PCI_CFG09" , 0x11F0000001824ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 383},
|
|
{"PCI_CFG10" , 0x11F0000001828ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 384},
|
|
{"PCI_CFG11" , 0x11F000000182Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 385},
|
|
{"PCI_CFG12" , 0x11F0000001830ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 386},
|
|
{"PCI_CFG13" , 0x11F0000001834ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 387},
|
|
{"PCI_CFG15" , 0x11F000000183Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 388},
|
|
{"PCI_CFG16" , 0x11F0000001840ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 389},
|
|
{"PCI_CFG17" , 0x11F0000001844ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 390},
|
|
{"PCI_CFG18" , 0x11F0000001848ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 391},
|
|
{"PCI_CFG19" , 0x11F000000184Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 392},
|
|
{"PCI_CFG20" , 0x11F0000001850ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 393},
|
|
{"PCI_CFG21" , 0x11F0000001854ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 394},
|
|
{"PCI_CFG22" , 0x11F0000001858ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 395},
|
|
{"PCI_CFG56" , 0x11F00000018E0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 396},
|
|
{"PCI_CFG57" , 0x11F00000018E4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 397},
|
|
{"PCI_CFG58" , 0x11F00000018E8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 398},
|
|
{"PCI_CFG59" , 0x11F00000018ECull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 399},
|
|
{"PCI_CFG60" , 0x11F00000018F0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 400},
|
|
{"PCI_CFG61" , 0x11F00000018F4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 401},
|
|
{"PCI_CFG62" , 0x11F00000018F8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 402},
|
|
{"PCI_CFG63" , 0x11F00000018FCull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 403},
|
|
{"PCI_CNT_REG" , 0x11F00000011B8ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 404},
|
|
{"PCI_CTL_STATUS_2" , 0x11F000000118Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 405},
|
|
{"PCI_DBELL0" , 0x80ull, CVMX_CSR_DB_TYPE_PCI, 32, 406},
|
|
{"PCI_DBELL1" , 0x88ull, CVMX_CSR_DB_TYPE_PCI, 32, 406},
|
|
{"PCI_DBELL2" , 0x90ull, CVMX_CSR_DB_TYPE_PCI, 32, 406},
|
|
{"PCI_DBELL3" , 0x98ull, CVMX_CSR_DB_TYPE_PCI, 32, 406},
|
|
{"PCI_DMA_CNT0" , 0xA0ull, CVMX_CSR_DB_TYPE_PCI, 32, 407},
|
|
{"PCI_DMA_CNT1" , 0xA8ull, CVMX_CSR_DB_TYPE_PCI, 32, 407},
|
|
{"PCI_DMA_INT_LEV0" , 0xA4ull, CVMX_CSR_DB_TYPE_PCI, 32, 408},
|
|
{"PCI_DMA_INT_LEV1" , 0xACull, CVMX_CSR_DB_TYPE_PCI, 32, 408},
|
|
{"PCI_DMA_TIME0" , 0xB0ull, CVMX_CSR_DB_TYPE_PCI, 32, 409},
|
|
{"PCI_DMA_TIME1" , 0xB4ull, CVMX_CSR_DB_TYPE_PCI, 32, 409},
|
|
{"PCI_INSTR_COUNT0" , 0x84ull, CVMX_CSR_DB_TYPE_PCI, 32, 410},
|
|
{"PCI_INSTR_COUNT1" , 0x8Cull, CVMX_CSR_DB_TYPE_PCI, 32, 410},
|
|
{"PCI_INSTR_COUNT2" , 0x94ull, CVMX_CSR_DB_TYPE_PCI, 32, 410},
|
|
{"PCI_INSTR_COUNT3" , 0x9Cull, CVMX_CSR_DB_TYPE_PCI, 32, 410},
|
|
{"PCI_INT_ENB" , 0x38ull, CVMX_CSR_DB_TYPE_PCI, 64, 411},
|
|
{"PCI_INT_ENB2" , 0x11F00000011A0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 412},
|
|
{"PCI_INT_SUM" , 0x30ull, CVMX_CSR_DB_TYPE_PCI, 64, 413},
|
|
{"PCI_INT_SUM2" , 0x11F0000001198ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 414},
|
|
{"PCI_MSI_RCV" , 0xF0ull, CVMX_CSR_DB_TYPE_PCI, 32, 415},
|
|
{"PCI_PKT_CREDITS0" , 0x44ull, CVMX_CSR_DB_TYPE_PCI, 32, 416},
|
|
{"PCI_PKT_CREDITS1" , 0x54ull, CVMX_CSR_DB_TYPE_PCI, 32, 416},
|
|
{"PCI_PKT_CREDITS2" , 0x64ull, CVMX_CSR_DB_TYPE_PCI, 32, 416},
|
|
{"PCI_PKT_CREDITS3" , 0x74ull, CVMX_CSR_DB_TYPE_PCI, 32, 416},
|
|
{"PCI_PKTS_SENT0" , 0x40ull, CVMX_CSR_DB_TYPE_PCI, 32, 417},
|
|
{"PCI_PKTS_SENT1" , 0x50ull, CVMX_CSR_DB_TYPE_PCI, 32, 417},
|
|
{"PCI_PKTS_SENT2" , 0x60ull, CVMX_CSR_DB_TYPE_PCI, 32, 417},
|
|
{"PCI_PKTS_SENT3" , 0x70ull, CVMX_CSR_DB_TYPE_PCI, 32, 417},
|
|
{"PCI_PKTS_SENT_INT_LEV0" , 0x48ull, CVMX_CSR_DB_TYPE_PCI, 32, 418},
|
|
{"PCI_PKTS_SENT_INT_LEV1" , 0x58ull, CVMX_CSR_DB_TYPE_PCI, 32, 418},
|
|
{"PCI_PKTS_SENT_INT_LEV2" , 0x68ull, CVMX_CSR_DB_TYPE_PCI, 32, 418},
|
|
{"PCI_PKTS_SENT_INT_LEV3" , 0x78ull, CVMX_CSR_DB_TYPE_PCI, 32, 418},
|
|
{"PCI_PKTS_SENT_TIME0" , 0x4Cull, CVMX_CSR_DB_TYPE_PCI, 32, 419},
|
|
{"PCI_PKTS_SENT_TIME1" , 0x5Cull, CVMX_CSR_DB_TYPE_PCI, 32, 419},
|
|
{"PCI_PKTS_SENT_TIME2" , 0x6Cull, CVMX_CSR_DB_TYPE_PCI, 32, 419},
|
|
{"PCI_PKTS_SENT_TIME3" , 0x7Cull, CVMX_CSR_DB_TYPE_PCI, 32, 419},
|
|
{"PCI_READ_CMD_6" , 0x11F0000001180ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 420},
|
|
{"PCI_READ_CMD_C" , 0x11F0000001184ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 421},
|
|
{"PCI_READ_CMD_E" , 0x11F0000001188ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 422},
|
|
{"PCI_READ_TIMEOUT" , 0x11F00000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 423},
|
|
{"PCI_SCM_REG" , 0x11F00000011A8ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 424},
|
|
{"PCI_TSR_REG" , 0x11F00000011B0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 425},
|
|
{"PCI_WIN_RD_ADDR" , 0x8ull, CVMX_CSR_DB_TYPE_PCI, 64, 426},
|
|
{"PCI_WIN_RD_DATA" , 0x20ull, CVMX_CSR_DB_TYPE_PCI, 64, 427},
|
|
{"PCI_WIN_WR_ADDR" , 0x0ull, CVMX_CSR_DB_TYPE_PCI, 64, 428},
|
|
{"PCI_WIN_WR_DATA" , 0x10ull, CVMX_CSR_DB_TYPE_PCI, 64, 429},
|
|
{"PCI_WIN_WR_MASK" , 0x18ull, CVMX_CSR_DB_TYPE_PCI, 64, 430},
|
|
{"PIP_BCK_PRS" , 0x11800A0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_BIST_STATUS" , 0x11800A0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_CRC_CTL0" , 0x11800A0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_CRC_CTL1" , 0x11800A0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_CRC_IV0" , 0x11800A0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_CRC_IV1" , 0x11800A0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_DEC_IPSEC0" , 0x11800A0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_DEC_IPSEC1" , 0x11800A0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_DEC_IPSEC2" , 0x11800A0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_DEC_IPSEC3" , 0x11800A0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_GBL_CFG" , 0x11800A0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
|
|
{"PIP_GBL_CTL" , 0x11800A0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PIP_INT_EN" , 0x11800A0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PIP_INT_REG" , 0x11800A0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PIP_IP_OFFSET" , 0x11800A0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PIP_PRT_CFG0" , 0x11800A0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG1" , 0x11800A0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG2" , 0x11800A0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG3" , 0x11800A0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG4" , 0x11800A0000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG5" , 0x11800A0000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG6" , 0x11800A0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG7" , 0x11800A0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG8" , 0x11800A0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG9" , 0x11800A0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG10" , 0x11800A0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG11" , 0x11800A0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG12" , 0x11800A0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG13" , 0x11800A0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG14" , 0x11800A0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG15" , 0x11800A0000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG16" , 0x11800A0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG17" , 0x11800A0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG18" , 0x11800A0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG19" , 0x11800A0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG20" , 0x11800A00002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG21" , 0x11800A00002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG22" , 0x11800A00002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG23" , 0x11800A00002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG24" , 0x11800A00002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG25" , 0x11800A00002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG26" , 0x11800A00002D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG27" , 0x11800A00002D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG28" , 0x11800A00002E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG29" , 0x11800A00002E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG30" , 0x11800A00002F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG31" , 0x11800A00002F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG32" , 0x11800A0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG33" , 0x11800A0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG34" , 0x11800A0000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_CFG35" , 0x11800A0000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_PRT_TAG0" , 0x11800A0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG1" , 0x11800A0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG2" , 0x11800A0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG3" , 0x11800A0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG4" , 0x11800A0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG5" , 0x11800A0000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG6" , 0x11800A0000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG7" , 0x11800A0000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG8" , 0x11800A0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG9" , 0x11800A0000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG10" , 0x11800A0000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG11" , 0x11800A0000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG12" , 0x11800A0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG13" , 0x11800A0000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG14" , 0x11800A0000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG15" , 0x11800A0000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG16" , 0x11800A0000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG17" , 0x11800A0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG18" , 0x11800A0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG19" , 0x11800A0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG20" , 0x11800A00004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG21" , 0x11800A00004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG22" , 0x11800A00004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG23" , 0x11800A00004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG24" , 0x11800A00004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG25" , 0x11800A00004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG26" , 0x11800A00004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG27" , 0x11800A00004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG28" , 0x11800A00004E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG29" , 0x11800A00004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG30" , 0x11800A00004F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG31" , 0x11800A00004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG32" , 0x11800A0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG33" , 0x11800A0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG34" , 0x11800A0000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_PRT_TAG35" , 0x11800A0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_QOS_DIFF0" , 0x11800A0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF1" , 0x11800A0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF2" , 0x11800A0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF3" , 0x11800A0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF4" , 0x11800A0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF5" , 0x11800A0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF6" , 0x11800A0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF7" , 0x11800A0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF8" , 0x11800A0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF9" , 0x11800A0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF10" , 0x11800A0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF11" , 0x11800A0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF12" , 0x11800A0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF13" , 0x11800A0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF14" , 0x11800A0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF15" , 0x11800A0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF16" , 0x11800A0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF17" , 0x11800A0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF18" , 0x11800A0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF19" , 0x11800A0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF20" , 0x11800A00006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF21" , 0x11800A00006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF22" , 0x11800A00006B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF23" , 0x11800A00006B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF24" , 0x11800A00006C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF25" , 0x11800A00006C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF26" , 0x11800A00006D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF27" , 0x11800A00006D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF28" , 0x11800A00006E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF29" , 0x11800A00006E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF30" , 0x11800A00006F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF31" , 0x11800A00006F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF32" , 0x11800A0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF33" , 0x11800A0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF34" , 0x11800A0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF35" , 0x11800A0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF36" , 0x11800A0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF37" , 0x11800A0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF38" , 0x11800A0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF39" , 0x11800A0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF40" , 0x11800A0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF41" , 0x11800A0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF42" , 0x11800A0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF43" , 0x11800A0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF44" , 0x11800A0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF45" , 0x11800A0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF46" , 0x11800A0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF47" , 0x11800A0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF48" , 0x11800A0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF49" , 0x11800A0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF50" , 0x11800A0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF51" , 0x11800A0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF52" , 0x11800A00007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF53" , 0x11800A00007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF54" , 0x11800A00007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF55" , 0x11800A00007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF56" , 0x11800A00007C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF57" , 0x11800A00007C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF58" , 0x11800A00007D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF59" , 0x11800A00007D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF60" , 0x11800A00007E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF61" , 0x11800A00007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF62" , 0x11800A00007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_DIFF63" , 0x11800A00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_QOS_VLAN0" , 0x11800A00000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_QOS_VLAN1" , 0x11800A00000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_QOS_VLAN2" , 0x11800A00000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_QOS_VLAN3" , 0x11800A00000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_QOS_VLAN4" , 0x11800A00000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_QOS_VLAN5" , 0x11800A00000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_QOS_VLAN6" , 0x11800A00000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_QOS_VLAN7" , 0x11800A00000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_QOS_WATCH0" , 0x11800A0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_QOS_WATCH1" , 0x11800A0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_QOS_WATCH2" , 0x11800A0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_QOS_WATCH3" , 0x11800A0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_RAW_WORD" , 0x11800A00000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_SFT_RST" , 0x11800A0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
|
|
{"PIP_STAT0_PRT0" , 0x11800A0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT1" , 0x11800A0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT2" , 0x11800A00008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT3" , 0x11800A00008F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT4" , 0x11800A0000940ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT5" , 0x11800A0000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT6" , 0x11800A00009E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT7" , 0x11800A0000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT8" , 0x11800A0000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT9" , 0x11800A0000AD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT10" , 0x11800A0000B20ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT11" , 0x11800A0000B70ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT12" , 0x11800A0000BC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT13" , 0x11800A0000C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT14" , 0x11800A0000C60ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT15" , 0x11800A0000CB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT16" , 0x11800A0000D00ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT17" , 0x11800A0000D50ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT18" , 0x11800A0000DA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT19" , 0x11800A0000DF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT20" , 0x11800A0000E40ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT21" , 0x11800A0000E90ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT22" , 0x11800A0000EE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT23" , 0x11800A0000F30ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT24" , 0x11800A0000F80ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT25" , 0x11800A0000FD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT26" , 0x11800A0001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT27" , 0x11800A0001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT28" , 0x11800A00010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT29" , 0x11800A0001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT30" , 0x11800A0001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT31" , 0x11800A00011B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT32" , 0x11800A0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT33" , 0x11800A0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT34" , 0x11800A00012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT0_PRT35" , 0x11800A00012F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_STAT1_PRT0" , 0x11800A0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT1" , 0x11800A0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT2" , 0x11800A00008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT3" , 0x11800A00008F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT4" , 0x11800A0000948ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT5" , 0x11800A0000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT6" , 0x11800A00009E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT7" , 0x11800A0000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT8" , 0x11800A0000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT9" , 0x11800A0000AD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT10" , 0x11800A0000B28ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT11" , 0x11800A0000B78ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT12" , 0x11800A0000BC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT13" , 0x11800A0000C18ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT14" , 0x11800A0000C68ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT15" , 0x11800A0000CB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT16" , 0x11800A0000D08ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT17" , 0x11800A0000D58ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT18" , 0x11800A0000DA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT19" , 0x11800A0000DF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT20" , 0x11800A0000E48ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT21" , 0x11800A0000E98ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT22" , 0x11800A0000EE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT23" , 0x11800A0000F38ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT24" , 0x11800A0000F88ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT25" , 0x11800A0000FD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT26" , 0x11800A0001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT27" , 0x11800A0001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT28" , 0x11800A00010C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT29" , 0x11800A0001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT30" , 0x11800A0001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT31" , 0x11800A00011B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT32" , 0x11800A0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT33" , 0x11800A0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT34" , 0x11800A00012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT1_PRT35" , 0x11800A00012F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_STAT2_PRT0" , 0x11800A0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT1" , 0x11800A0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT2" , 0x11800A00008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT3" , 0x11800A0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT4" , 0x11800A0000950ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT5" , 0x11800A00009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT6" , 0x11800A00009F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT7" , 0x11800A0000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT8" , 0x11800A0000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT9" , 0x11800A0000AE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT10" , 0x11800A0000B30ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT11" , 0x11800A0000B80ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT12" , 0x11800A0000BD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT13" , 0x11800A0000C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT14" , 0x11800A0000C70ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT15" , 0x11800A0000CC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT16" , 0x11800A0000D10ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT17" , 0x11800A0000D60ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT18" , 0x11800A0000DB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT19" , 0x11800A0000E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT20" , 0x11800A0000E50ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT21" , 0x11800A0000EA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT22" , 0x11800A0000EF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT23" , 0x11800A0000F40ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT24" , 0x11800A0000F90ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT25" , 0x11800A0000FE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT26" , 0x11800A0001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT27" , 0x11800A0001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT28" , 0x11800A00010D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT29" , 0x11800A0001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT30" , 0x11800A0001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT31" , 0x11800A00011C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT32" , 0x11800A0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT33" , 0x11800A0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT34" , 0x11800A00012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT2_PRT35" , 0x11800A0001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_STAT3_PRT0" , 0x11800A0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT1" , 0x11800A0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT2" , 0x11800A00008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT3" , 0x11800A0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT4" , 0x11800A0000958ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT5" , 0x11800A00009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT6" , 0x11800A00009F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT7" , 0x11800A0000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT8" , 0x11800A0000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT9" , 0x11800A0000AE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT10" , 0x11800A0000B38ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT11" , 0x11800A0000B88ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT12" , 0x11800A0000BD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT13" , 0x11800A0000C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT14" , 0x11800A0000C78ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT15" , 0x11800A0000CC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT16" , 0x11800A0000D18ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT17" , 0x11800A0000D68ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT18" , 0x11800A0000DB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT19" , 0x11800A0000E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT20" , 0x11800A0000E58ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT21" , 0x11800A0000EA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT22" , 0x11800A0000EF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT23" , 0x11800A0000F48ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT24" , 0x11800A0000F98ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT25" , 0x11800A0000FE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT26" , 0x11800A0001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT27" , 0x11800A0001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT28" , 0x11800A00010D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT29" , 0x11800A0001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT30" , 0x11800A0001178ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT31" , 0x11800A00011C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT32" , 0x11800A0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT33" , 0x11800A0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT34" , 0x11800A00012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT3_PRT35" , 0x11800A0001308ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_STAT4_PRT0" , 0x11800A0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT1" , 0x11800A0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT2" , 0x11800A00008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT3" , 0x11800A0000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT4" , 0x11800A0000960ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT5" , 0x11800A00009B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT6" , 0x11800A0000A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT7" , 0x11800A0000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT8" , 0x11800A0000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT9" , 0x11800A0000AF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT10" , 0x11800A0000B40ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT11" , 0x11800A0000B90ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT12" , 0x11800A0000BE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT13" , 0x11800A0000C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT14" , 0x11800A0000C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT15" , 0x11800A0000CD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT16" , 0x11800A0000D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT17" , 0x11800A0000D70ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT18" , 0x11800A0000DC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT19" , 0x11800A0000E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT20" , 0x11800A0000E60ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT21" , 0x11800A0000EB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT22" , 0x11800A0000F00ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT23" , 0x11800A0000F50ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT24" , 0x11800A0000FA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT25" , 0x11800A0000FF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT26" , 0x11800A0001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT27" , 0x11800A0001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT28" , 0x11800A00010E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT29" , 0x11800A0001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT30" , 0x11800A0001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT31" , 0x11800A00011D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT32" , 0x11800A0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT33" , 0x11800A0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT34" , 0x11800A00012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT4_PRT35" , 0x11800A0001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_STAT5_PRT0" , 0x11800A0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT1" , 0x11800A0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT2" , 0x11800A00008C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT3" , 0x11800A0000918ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT4" , 0x11800A0000968ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT5" , 0x11800A00009B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT6" , 0x11800A0000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT7" , 0x11800A0000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT8" , 0x11800A0000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT9" , 0x11800A0000AF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT10" , 0x11800A0000B48ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT11" , 0x11800A0000B98ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT12" , 0x11800A0000BE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT13" , 0x11800A0000C38ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT14" , 0x11800A0000C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT15" , 0x11800A0000CD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT16" , 0x11800A0000D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT17" , 0x11800A0000D78ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT18" , 0x11800A0000DC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT19" , 0x11800A0000E18ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT20" , 0x11800A0000E68ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT21" , 0x11800A0000EB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT22" , 0x11800A0000F08ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT23" , 0x11800A0000F58ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT24" , 0x11800A0000FA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT25" , 0x11800A0000FF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT26" , 0x11800A0001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT27" , 0x11800A0001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT28" , 0x11800A00010E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT29" , 0x11800A0001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT30" , 0x11800A0001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT31" , 0x11800A00011D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT32" , 0x11800A0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT33" , 0x11800A0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT34" , 0x11800A00012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT5_PRT35" , 0x11800A0001318ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_STAT6_PRT0" , 0x11800A0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT1" , 0x11800A0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT2" , 0x11800A00008D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT3" , 0x11800A0000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT4" , 0x11800A0000970ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT5" , 0x11800A00009C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT6" , 0x11800A0000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT7" , 0x11800A0000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT8" , 0x11800A0000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT9" , 0x11800A0000B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT10" , 0x11800A0000B50ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT11" , 0x11800A0000BA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT12" , 0x11800A0000BF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT13" , 0x11800A0000C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT14" , 0x11800A0000C90ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT15" , 0x11800A0000CE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT16" , 0x11800A0000D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT17" , 0x11800A0000D80ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT18" , 0x11800A0000DD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT19" , 0x11800A0000E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT20" , 0x11800A0000E70ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT21" , 0x11800A0000EC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT22" , 0x11800A0000F10ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT23" , 0x11800A0000F60ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT24" , 0x11800A0000FB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT25" , 0x11800A0001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT26" , 0x11800A0001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT27" , 0x11800A00010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT28" , 0x11800A00010F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT29" , 0x11800A0001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT30" , 0x11800A0001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT31" , 0x11800A00011E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT32" , 0x11800A0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT33" , 0x11800A0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT34" , 0x11800A00012D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT6_PRT35" , 0x11800A0001320ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_STAT7_PRT0" , 0x11800A0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT1" , 0x11800A0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT2" , 0x11800A00008D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT3" , 0x11800A0000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT4" , 0x11800A0000978ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT5" , 0x11800A00009C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT6" , 0x11800A0000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT7" , 0x11800A0000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT8" , 0x11800A0000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT9" , 0x11800A0000B08ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT10" , 0x11800A0000B58ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT11" , 0x11800A0000BA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT12" , 0x11800A0000BF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT13" , 0x11800A0000C48ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT14" , 0x11800A0000C98ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT15" , 0x11800A0000CE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT16" , 0x11800A0000D38ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT17" , 0x11800A0000D88ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT18" , 0x11800A0000DD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT19" , 0x11800A0000E28ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT20" , 0x11800A0000E78ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT21" , 0x11800A0000EC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT22" , 0x11800A0000F18ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT23" , 0x11800A0000F68ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT24" , 0x11800A0000FB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT25" , 0x11800A0001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT26" , 0x11800A0001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT27" , 0x11800A00010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT28" , 0x11800A00010F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT29" , 0x11800A0001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT30" , 0x11800A0001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT31" , 0x11800A00011E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT32" , 0x11800A0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT33" , 0x11800A0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT34" , 0x11800A00012D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT7_PRT35" , 0x11800A0001328ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_STAT8_PRT0" , 0x11800A0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT1" , 0x11800A0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT2" , 0x11800A00008E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT3" , 0x11800A0000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT4" , 0x11800A0000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT5" , 0x11800A00009D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT6" , 0x11800A0000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT7" , 0x11800A0000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT8" , 0x11800A0000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT9" , 0x11800A0000B10ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT10" , 0x11800A0000B60ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT11" , 0x11800A0000BB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT12" , 0x11800A0000C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT13" , 0x11800A0000C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT14" , 0x11800A0000CA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT15" , 0x11800A0000CF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT16" , 0x11800A0000D40ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT17" , 0x11800A0000D90ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT18" , 0x11800A0000DE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT19" , 0x11800A0000E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT20" , 0x11800A0000E80ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT21" , 0x11800A0000ED0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT22" , 0x11800A0000F20ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT23" , 0x11800A0000F70ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT24" , 0x11800A0000FC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT25" , 0x11800A0001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT26" , 0x11800A0001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT27" , 0x11800A00010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT28" , 0x11800A0001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT29" , 0x11800A0001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT30" , 0x11800A00011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT31" , 0x11800A00011F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT32" , 0x11800A0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT33" , 0x11800A0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT34" , 0x11800A00012E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT8_PRT35" , 0x11800A0001330ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_STAT9_PRT0" , 0x11800A0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT1" , 0x11800A0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT2" , 0x11800A00008E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT3" , 0x11800A0000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT4" , 0x11800A0000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT5" , 0x11800A00009D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT6" , 0x11800A0000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT7" , 0x11800A0000A78ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT8" , 0x11800A0000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT9" , 0x11800A0000B18ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT10" , 0x11800A0000B68ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT11" , 0x11800A0000BB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT12" , 0x11800A0000C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT13" , 0x11800A0000C58ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT14" , 0x11800A0000CA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT15" , 0x11800A0000CF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT16" , 0x11800A0000D48ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT17" , 0x11800A0000D98ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT18" , 0x11800A0000DE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT19" , 0x11800A0000E38ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT20" , 0x11800A0000E88ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT21" , 0x11800A0000ED8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT22" , 0x11800A0000F28ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT23" , 0x11800A0000F78ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT24" , 0x11800A0000FC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT25" , 0x11800A0001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT26" , 0x11800A0001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT27" , 0x11800A00010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT28" , 0x11800A0001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT29" , 0x11800A0001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT30" , 0x11800A00011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT31" , 0x11800A00011F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT32" , 0x11800A0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT33" , 0x11800A0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT34" , 0x11800A00012E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT9_PRT35" , 0x11800A0001338ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT_CTL" , 0x11800A0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT_INB_ERRS0" , 0x11800A0001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS1" , 0x11800A0001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS2" , 0x11800A0001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS3" , 0x11800A0001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS4" , 0x11800A0001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS5" , 0x11800A0001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS6" , 0x11800A0001AD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS7" , 0x11800A0001AF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS8" , 0x11800A0001B10ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS9" , 0x11800A0001B30ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS10" , 0x11800A0001B50ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS11" , 0x11800A0001B70ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS12" , 0x11800A0001B90ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS13" , 0x11800A0001BB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS14" , 0x11800A0001BD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS15" , 0x11800A0001BF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS16" , 0x11800A0001C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS17" , 0x11800A0001C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS18" , 0x11800A0001C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS19" , 0x11800A0001C70ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS20" , 0x11800A0001C90ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS21" , 0x11800A0001CB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS22" , 0x11800A0001CD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS23" , 0x11800A0001CF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS24" , 0x11800A0001D10ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS25" , 0x11800A0001D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS26" , 0x11800A0001D50ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS27" , 0x11800A0001D70ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS28" , 0x11800A0001D90ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS29" , 0x11800A0001DB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS30" , 0x11800A0001DD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS31" , 0x11800A0001DF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS32" , 0x11800A0001E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS33" , 0x11800A0001E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS34" , 0x11800A0001E50ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_ERRS35" , 0x11800A0001E70ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT_INB_OCTS0" , 0x11800A0001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS1" , 0x11800A0001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS2" , 0x11800A0001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS3" , 0x11800A0001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS4" , 0x11800A0001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS5" , 0x11800A0001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS6" , 0x11800A0001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS7" , 0x11800A0001AE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS8" , 0x11800A0001B08ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS9" , 0x11800A0001B28ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS10" , 0x11800A0001B48ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS11" , 0x11800A0001B68ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS12" , 0x11800A0001B88ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS13" , 0x11800A0001BA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS14" , 0x11800A0001BC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS15" , 0x11800A0001BE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS16" , 0x11800A0001C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS17" , 0x11800A0001C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS18" , 0x11800A0001C48ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS19" , 0x11800A0001C68ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS20" , 0x11800A0001C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS21" , 0x11800A0001CA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS22" , 0x11800A0001CC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS23" , 0x11800A0001CE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS24" , 0x11800A0001D08ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS25" , 0x11800A0001D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS26" , 0x11800A0001D48ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS27" , 0x11800A0001D68ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS28" , 0x11800A0001D88ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS29" , 0x11800A0001DA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS30" , 0x11800A0001DC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS31" , 0x11800A0001DE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS32" , 0x11800A0001E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS33" , 0x11800A0001E28ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS34" , 0x11800A0001E48ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_OCTS35" , 0x11800A0001E68ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT_INB_PKTS0" , 0x11800A0001A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS1" , 0x11800A0001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS2" , 0x11800A0001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS3" , 0x11800A0001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS4" , 0x11800A0001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS5" , 0x11800A0001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS6" , 0x11800A0001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS7" , 0x11800A0001AE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS8" , 0x11800A0001B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS9" , 0x11800A0001B20ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS10" , 0x11800A0001B40ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS11" , 0x11800A0001B60ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS12" , 0x11800A0001B80ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS13" , 0x11800A0001BA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS14" , 0x11800A0001BC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS15" , 0x11800A0001BE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS16" , 0x11800A0001C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS17" , 0x11800A0001C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS18" , 0x11800A0001C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS19" , 0x11800A0001C60ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS20" , 0x11800A0001C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS21" , 0x11800A0001CA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS22" , 0x11800A0001CC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS23" , 0x11800A0001CE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS24" , 0x11800A0001D00ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS25" , 0x11800A0001D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS26" , 0x11800A0001D40ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS27" , 0x11800A0001D60ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS28" , 0x11800A0001D80ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS29" , 0x11800A0001DA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS30" , 0x11800A0001DC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS31" , 0x11800A0001DE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS32" , 0x11800A0001E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS33" , 0x11800A0001E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS34" , 0x11800A0001E40ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT_INB_PKTS35" , 0x11800A0001E60ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_TAG_INC0" , 0x11800A0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC1" , 0x11800A0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC2" , 0x11800A0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC3" , 0x11800A0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC4" , 0x11800A0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC5" , 0x11800A0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC6" , 0x11800A0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC7" , 0x11800A0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC8" , 0x11800A0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC9" , 0x11800A0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC10" , 0x11800A0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC11" , 0x11800A0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC12" , 0x11800A0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC13" , 0x11800A0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC14" , 0x11800A0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC15" , 0x11800A0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC16" , 0x11800A0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC17" , 0x11800A0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC18" , 0x11800A0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC19" , 0x11800A0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC20" , 0x11800A00018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC21" , 0x11800A00018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC22" , 0x11800A00018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC23" , 0x11800A00018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC24" , 0x11800A00018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC25" , 0x11800A00018C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC26" , 0x11800A00018D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC27" , 0x11800A00018D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC28" , 0x11800A00018E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC29" , 0x11800A00018E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC30" , 0x11800A00018F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC31" , 0x11800A00018F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC32" , 0x11800A0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC33" , 0x11800A0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC34" , 0x11800A0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC35" , 0x11800A0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC36" , 0x11800A0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC37" , 0x11800A0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC38" , 0x11800A0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC39" , 0x11800A0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC40" , 0x11800A0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC41" , 0x11800A0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC42" , 0x11800A0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC43" , 0x11800A0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC44" , 0x11800A0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC45" , 0x11800A0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC46" , 0x11800A0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC47" , 0x11800A0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC48" , 0x11800A0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC49" , 0x11800A0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC50" , 0x11800A0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC51" , 0x11800A0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC52" , 0x11800A00019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC53" , 0x11800A00019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC54" , 0x11800A00019B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC55" , 0x11800A00019B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC56" , 0x11800A00019C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC57" , 0x11800A00019C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC58" , 0x11800A00019D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC59" , 0x11800A00019D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC60" , 0x11800A00019E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC61" , 0x11800A00019E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC62" , 0x11800A00019F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_INC63" , 0x11800A00019F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_TAG_MASK" , 0x11800A0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_TAG_SECRET" , 0x11800A0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_TODO_ENTRY" , 0x11800A0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 468},
|
|
{"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 473},
|
|
{"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 474},
|
|
{"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 475},
|
|
{"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 476},
|
|
{"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 477},
|
|
{"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 478},
|
|
{"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
|
|
{"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 480},
|
|
{"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
|
|
{"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 482},
|
|
{"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 483},
|
|
{"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 484},
|
|
{"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 485},
|
|
{"PKO_REG_CRC_CTL0" , 0x1180050000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 486},
|
|
{"PKO_REG_CRC_CTL1" , 0x1180050000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 486},
|
|
{"PKO_REG_CRC_ENABLE" , 0x1180050000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 487},
|
|
{"PKO_REG_CRC_IV0" , 0x1180050000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 488},
|
|
{"PKO_REG_CRC_IV1" , 0x1180050000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 488},
|
|
{"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 489},
|
|
{"PKO_REG_DEBUG1" , 0x11800500000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 490},
|
|
{"PKO_REG_DEBUG2" , 0x11800500000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 491},
|
|
{"PKO_REG_DEBUG3" , 0x11800500000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 492},
|
|
{"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 493},
|
|
{"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 494},
|
|
{"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 495},
|
|
{"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
|
|
{"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
|
|
{"PKO_REG_QUEUE_PTRS1" , 0x1180050000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
|
|
{"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
|
|
{"POW_BIST_STAT" , 0x16700000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 500},
|
|
{"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 501},
|
|
{"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 502},
|
|
{"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 503},
|
|
{"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
|
|
{"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
|
|
{"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
|
|
{"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
|
|
{"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
|
|
{"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
|
|
{"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
|
|
{"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 504},
|
|
{"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 505},
|
|
{"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 506},
|
|
{"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 507},
|
|
{"POW_PF_RST_MSK" , 0x1670000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 508},
|
|
{"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
|
|
{"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
|
|
{"POW_PP_GRP_MSK2" , 0x1670000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
|
|
{"POW_PP_GRP_MSK3" , 0x1670000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
|
|
{"POW_PP_GRP_MSK4" , 0x1670000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
|
|
{"POW_PP_GRP_MSK5" , 0x1670000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
|
|
{"POW_PP_GRP_MSK6" , 0x1670000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
|
|
{"POW_PP_GRP_MSK7" , 0x1670000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
|
|
{"POW_PP_GRP_MSK8" , 0x1670000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
|
|
{"POW_PP_GRP_MSK9" , 0x1670000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
|
|
{"POW_PP_GRP_MSK10" , 0x1670000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
|
|
{"POW_PP_GRP_MSK11" , 0x1670000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
|
|
{"POW_PP_GRP_MSK12" , 0x1670000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
|
|
{"POW_PP_GRP_MSK13" , 0x1670000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
|
|
{"POW_PP_GRP_MSK14" , 0x1670000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
|
|
{"POW_PP_GRP_MSK15" , 0x1670000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 509},
|
|
{"POW_QOS_RND0" , 0x16700000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 510},
|
|
{"POW_QOS_RND1" , 0x16700000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 510},
|
|
{"POW_QOS_RND2" , 0x16700000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 510},
|
|
{"POW_QOS_RND3" , 0x16700000001D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 510},
|
|
{"POW_QOS_RND4" , 0x16700000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 510},
|
|
{"POW_QOS_RND5" , 0x16700000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 510},
|
|
{"POW_QOS_RND6" , 0x16700000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 510},
|
|
{"POW_QOS_RND7" , 0x16700000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 510},
|
|
{"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 511},
|
|
{"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 511},
|
|
{"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 511},
|
|
{"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 511},
|
|
{"POW_QOS_THR4" , 0x16700000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 511},
|
|
{"POW_QOS_THR5" , 0x16700000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 511},
|
|
{"POW_QOS_THR6" , 0x16700000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 511},
|
|
{"POW_QOS_THR7" , 0x16700000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 511},
|
|
{"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 512},
|
|
{"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 513},
|
|
{"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
|
|
{"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
|
|
{"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
|
|
{"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
|
|
{"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
|
|
{"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
|
|
{"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
|
|
{"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
|
|
{"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 515},
|
|
{"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
|
|
{"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
|
|
{"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
|
|
{"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
|
|
{"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
|
|
{"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
|
|
{"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
|
|
{"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
|
|
{"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
|
|
{"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
|
|
{"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
|
|
{"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
|
|
{"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
|
|
{"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
|
|
{"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
|
|
{"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
|
|
{"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 517},
|
|
{"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
|
|
{"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
|
|
{"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
|
|
{"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
|
|
{"POW_WQ_INT_THR4" , 0x16700000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
|
|
{"POW_WQ_INT_THR5" , 0x16700000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
|
|
{"POW_WQ_INT_THR6" , 0x16700000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
|
|
{"POW_WQ_INT_THR7" , 0x16700000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
|
|
{"POW_WQ_INT_THR8" , 0x16700000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
|
|
{"POW_WQ_INT_THR9" , 0x16700000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
|
|
{"POW_WQ_INT_THR10" , 0x16700000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
|
|
{"POW_WQ_INT_THR11" , 0x16700000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
|
|
{"POW_WQ_INT_THR12" , 0x16700000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
|
|
{"POW_WQ_INT_THR13" , 0x16700000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
|
|
{"POW_WQ_INT_THR14" , 0x16700000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
|
|
{"POW_WQ_INT_THR15" , 0x16700000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
|
|
{"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_WS_PC4" , 0x16700000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_WS_PC5" , 0x16700000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_WS_PC6" , 0x16700000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_WS_PC7" , 0x16700000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_WS_PC8" , 0x16700000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_WS_PC9" , 0x16700000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_WS_PC10" , 0x16700000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_WS_PC11" , 0x16700000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_WS_PC12" , 0x16700000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_WS_PC13" , 0x16700000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_WS_PC14" , 0x16700000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_WS_PC15" , 0x16700000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 520},
|
|
{"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 521},
|
|
{"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 522},
|
|
{"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 523},
|
|
{"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 524},
|
|
{"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 525},
|
|
{"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 526},
|
|
{"SPX0_BCKPRS_CNT" , 0x1180090000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 527},
|
|
{"SPX1_BCKPRS_CNT" , 0x1180098000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 527},
|
|
{"SPX0_BIST_STAT" , 0x11800900007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 528},
|
|
{"SPX1_BIST_STAT" , 0x11800980007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 528},
|
|
{"SPX0_CLK_CTL" , 0x1180090000348ull, CVMX_CSR_DB_TYPE_RSL, 64, 529},
|
|
{"SPX1_CLK_CTL" , 0x1180098000348ull, CVMX_CSR_DB_TYPE_RSL, 64, 529},
|
|
{"SPX0_CLK_STAT" , 0x1180090000350ull, CVMX_CSR_DB_TYPE_RSL, 64, 530},
|
|
{"SPX1_CLK_STAT" , 0x1180098000350ull, CVMX_CSR_DB_TYPE_RSL, 64, 530},
|
|
{"SPX0_DBG_DESKEW_CTL" , 0x1180090000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 531},
|
|
{"SPX1_DBG_DESKEW_CTL" , 0x1180098000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 531},
|
|
{"SPX0_DBG_DESKEW_STATE" , 0x1180090000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SPX1_DBG_DESKEW_STATE" , 0x1180098000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SPX0_DRV_CTL" , 0x1180090000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 533},
|
|
{"SPX1_DRV_CTL" , 0x1180098000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 533},
|
|
{"SPX0_ERR_CTL" , 0x1180090000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 534},
|
|
{"SPX1_ERR_CTL" , 0x1180098000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 534},
|
|
{"SPX0_INT_DAT" , 0x1180090000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 535},
|
|
{"SPX1_INT_DAT" , 0x1180098000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 535},
|
|
{"SPX0_INT_MSK" , 0x1180090000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 536},
|
|
{"SPX1_INT_MSK" , 0x1180098000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 536},
|
|
{"SPX0_INT_REG" , 0x1180090000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 537},
|
|
{"SPX1_INT_REG" , 0x1180098000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 537},
|
|
{"SPX0_INT_SYNC" , 0x1180090000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 538},
|
|
{"SPX1_INT_SYNC" , 0x1180098000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 538},
|
|
{"SPX0_TPA_ACC" , 0x1180090000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 539},
|
|
{"SPX1_TPA_ACC" , 0x1180098000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 539},
|
|
{"SPX0_TPA_MAX" , 0x1180090000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
|
|
{"SPX1_TPA_MAX" , 0x1180098000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
|
|
{"SPX0_TPA_SEL" , 0x1180090000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 541},
|
|
{"SPX1_TPA_SEL" , 0x1180098000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 541},
|
|
{"SPX0_TRN4_CTL" , 0x1180090000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 542},
|
|
{"SPX1_TRN4_CTL" , 0x1180098000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 542},
|
|
{"SRX0_COM_CTL" , 0x1180090000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 543},
|
|
{"SRX1_COM_CTL" , 0x1180098000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 543},
|
|
{"SRX0_IGN_RX_FULL" , 0x1180090000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 544},
|
|
{"SRX1_IGN_RX_FULL" , 0x1180098000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 544},
|
|
{"SRX0_SPI4_CAL000" , 0x1180090000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL001" , 0x1180090000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL002" , 0x1180090000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL003" , 0x1180090000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL004" , 0x1180090000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL005" , 0x1180090000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL006" , 0x1180090000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL007" , 0x1180090000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL008" , 0x1180090000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL009" , 0x1180090000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL010" , 0x1180090000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL011" , 0x1180090000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL012" , 0x1180090000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL013" , 0x1180090000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL014" , 0x1180090000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL015" , 0x1180090000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL016" , 0x1180090000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL017" , 0x1180090000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL018" , 0x1180090000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL019" , 0x1180090000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL020" , 0x11800900000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL021" , 0x11800900000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL022" , 0x11800900000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL023" , 0x11800900000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL024" , 0x11800900000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL025" , 0x11800900000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL026" , 0x11800900000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL027" , 0x11800900000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL028" , 0x11800900000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL029" , 0x11800900000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL030" , 0x11800900000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_CAL031" , 0x11800900000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL000" , 0x1180098000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL001" , 0x1180098000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL002" , 0x1180098000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL003" , 0x1180098000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL004" , 0x1180098000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL005" , 0x1180098000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL006" , 0x1180098000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL007" , 0x1180098000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL008" , 0x1180098000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL009" , 0x1180098000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL010" , 0x1180098000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL011" , 0x1180098000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL012" , 0x1180098000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL013" , 0x1180098000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL014" , 0x1180098000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL015" , 0x1180098000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL016" , 0x1180098000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL017" , 0x1180098000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL018" , 0x1180098000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL019" , 0x1180098000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL020" , 0x11800980000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL021" , 0x11800980000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL022" , 0x11800980000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL023" , 0x11800980000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL024" , 0x11800980000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL025" , 0x11800980000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL026" , 0x11800980000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL027" , 0x11800980000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL028" , 0x11800980000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL029" , 0x11800980000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL030" , 0x11800980000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX1_SPI4_CAL031" , 0x11800980000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SRX0_SPI4_STAT" , 0x1180090000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 546},
|
|
{"SRX1_SPI4_STAT" , 0x1180098000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 546},
|
|
{"SRX0_SW_TICK_CTL" , 0x1180090000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 547},
|
|
{"SRX1_SW_TICK_CTL" , 0x1180098000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 547},
|
|
{"SRX0_SW_TICK_DAT" , 0x1180090000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 548},
|
|
{"SRX1_SW_TICK_DAT" , 0x1180098000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 548},
|
|
{"STX0_ARB_CTL" , 0x1180090000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 549},
|
|
{"STX1_ARB_CTL" , 0x1180098000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 549},
|
|
{"STX0_BCKPRS_CNT" , 0x1180090000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 550},
|
|
{"STX1_BCKPRS_CNT" , 0x1180098000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 550},
|
|
{"STX0_COM_CTL" , 0x1180090000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 551},
|
|
{"STX1_COM_CTL" , 0x1180098000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 551},
|
|
{"STX0_DIP_CNT" , 0x1180090000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 552},
|
|
{"STX1_DIP_CNT" , 0x1180098000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 552},
|
|
{"STX0_IGN_CAL" , 0x1180090000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 553},
|
|
{"STX1_IGN_CAL" , 0x1180098000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 553},
|
|
{"STX0_INT_MSK" , 0x11800900006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 554},
|
|
{"STX1_INT_MSK" , 0x11800980006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 554},
|
|
{"STX0_INT_REG" , 0x1180090000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"STX1_INT_REG" , 0x1180098000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"STX0_INT_SYNC" , 0x11800900006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 556},
|
|
{"STX1_INT_SYNC" , 0x11800980006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 556},
|
|
{"STX0_MIN_BST" , 0x1180090000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 557},
|
|
{"STX1_MIN_BST" , 0x1180098000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 557},
|
|
{"STX0_SPI4_CAL000" , 0x1180090000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL001" , 0x1180090000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL002" , 0x1180090000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL003" , 0x1180090000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL004" , 0x1180090000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL005" , 0x1180090000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL006" , 0x1180090000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL007" , 0x1180090000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL008" , 0x1180090000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL009" , 0x1180090000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL010" , 0x1180090000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL011" , 0x1180090000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL012" , 0x1180090000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL013" , 0x1180090000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL014" , 0x1180090000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL015" , 0x1180090000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL016" , 0x1180090000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL017" , 0x1180090000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL018" , 0x1180090000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL019" , 0x1180090000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL020" , 0x11800900004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL021" , 0x11800900004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL022" , 0x11800900004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL023" , 0x11800900004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL024" , 0x11800900004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL025" , 0x11800900004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL026" , 0x11800900004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL027" , 0x11800900004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL028" , 0x11800900004E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL029" , 0x11800900004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL030" , 0x11800900004F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_CAL031" , 0x11800900004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL000" , 0x1180098000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL001" , 0x1180098000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL002" , 0x1180098000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL003" , 0x1180098000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL004" , 0x1180098000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL005" , 0x1180098000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL006" , 0x1180098000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL007" , 0x1180098000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL008" , 0x1180098000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL009" , 0x1180098000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL010" , 0x1180098000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL011" , 0x1180098000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL012" , 0x1180098000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL013" , 0x1180098000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL014" , 0x1180098000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL015" , 0x1180098000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL016" , 0x1180098000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL017" , 0x1180098000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL018" , 0x1180098000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL019" , 0x1180098000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL020" , 0x11800980004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL021" , 0x11800980004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL022" , 0x11800980004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL023" , 0x11800980004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL024" , 0x11800980004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL025" , 0x11800980004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL026" , 0x11800980004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL027" , 0x11800980004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL028" , 0x11800980004E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL029" , 0x11800980004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL030" , 0x11800980004F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX1_SPI4_CAL031" , 0x11800980004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_SPI4_DAT" , 0x1180090000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 559},
|
|
{"STX1_SPI4_DAT" , 0x1180098000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 559},
|
|
{"STX0_SPI4_STAT" , 0x1180090000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 560},
|
|
{"STX1_SPI4_STAT" , 0x1180098000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 560},
|
|
{"STX0_STAT_BYTES_HI" , 0x1180090000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 561},
|
|
{"STX1_STAT_BYTES_HI" , 0x1180098000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 561},
|
|
{"STX0_STAT_BYTES_LO" , 0x1180090000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 562},
|
|
{"STX1_STAT_BYTES_LO" , 0x1180098000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 562},
|
|
{"STX0_STAT_CTL" , 0x1180090000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 563},
|
|
{"STX1_STAT_CTL" , 0x1180098000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 563},
|
|
{"STX0_STAT_PKT_XMT" , 0x1180090000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 564},
|
|
{"STX1_STAT_PKT_XMT" , 0x1180098000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 564},
|
|
{"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 565},
|
|
{"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 566},
|
|
{"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 567},
|
|
{"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 569},
|
|
{"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 570},
|
|
{"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 571},
|
|
{"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 572},
|
|
{"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 573},
|
|
{"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 574},
|
|
{"TRA_BIST_STATUS" , 0x11800A8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 575},
|
|
{"TRA_CTL" , 0x11800A8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 576},
|
|
{"TRA_CYCLES_SINCE" , 0x11800A8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 577},
|
|
{"TRA_CYCLES_SINCE1" , 0x11800A8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 578},
|
|
{"TRA_FILT_ADR_ADR" , 0x11800A8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 579},
|
|
{"TRA_FILT_ADR_MSK" , 0x11800A8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 580},
|
|
{"TRA_FILT_CMD" , 0x11800A8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 581},
|
|
{"TRA_FILT_DID" , 0x11800A8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 582},
|
|
{"TRA_FILT_SID" , 0x11800A8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 583},
|
|
{"TRA_INT_STATUS" , 0x11800A8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 584},
|
|
{"TRA_READ_DAT" , 0x11800A8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 585},
|
|
{"TRA_TRIG0_ADR_ADR" , 0x11800A8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 586},
|
|
{"TRA_TRIG0_ADR_MSK" , 0x11800A80000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 587},
|
|
{"TRA_TRIG0_CMD" , 0x11800A8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 588},
|
|
{"TRA_TRIG0_DID" , 0x11800A8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 589},
|
|
{"TRA_TRIG0_SID" , 0x11800A8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 590},
|
|
{"TRA_TRIG1_ADR_ADR" , 0x11800A80000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 591},
|
|
{"TRA_TRIG1_ADR_MSK" , 0x11800A80000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 592},
|
|
{"TRA_TRIG1_CMD" , 0x11800A80000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 593},
|
|
{"TRA_TRIG1_DID" , 0x11800A80000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 594},
|
|
{"TRA_TRIG1_SID" , 0x11800A80000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 595},
|
|
{"ZIP_CMD_BIST_RESULT" , 0x1180038000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 596},
|
|
{"ZIP_CMD_BUF" , 0x1180038000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 597},
|
|
{"ZIP_CMD_CTL" , 0x1180038000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 598},
|
|
{"ZIP_CONSTANTS" , 0x11800380000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 599},
|
|
{"ZIP_DEBUG0" , 0x1180038000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 600},
|
|
{"ZIP_ERROR" , 0x1180038000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 601},
|
|
{"ZIP_INT_MASK" , 0x1180038000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 602},
|
|
{NULL,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xxp1[] = {
|
|
/* name , bit, width, csr, type, rst un, typ un, reset, typical */
|
|
{"OVRFLW" , 0, 4, 0, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXPOP" , 4, 4, 0, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXPSH" , 8, 4, 0, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_12_63" , 12, 52, 0, "RAZ", 1, 1, 0, 0},
|
|
{"OVRFLW" , 0, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXPOP" , 4, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXPSH" , 8, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 1, "RAZ", 1, 1, 0, 0},
|
|
{"INT_LOOP" , 0, 4, 2, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EXT_LOOP" , 4, 4, 2, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 2, "RAZ", 1, 1, 0, 0},
|
|
{"BYPASS" , 0, 1, 3, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 3, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 4, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 4, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 4, 5, "RO", 0, 1, 0ull, 0},
|
|
{"PCTL" , 4, 5, 5, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_9_63" , 9, 55, 5, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 4, 6, "R/W", 0, 1, 0ull, 0},
|
|
{"PCTL" , 4, 4, 6, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 6, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 5, 7, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 7, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 5, 8, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 8, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL" , 0, 5, 9, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 9, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL" , 0, 5, 10, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 10, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 11, "RO", 1, 1, 0, 0},
|
|
{"DFALOCK" , 5, 1, 11, "RO", 1, 1, 0, 0},
|
|
{"DFALEAD" , 6, 1, 11, "RO", 1, 1, 0, 0},
|
|
{"DFALAG" , 7, 1, 11, "RO", 1, 1, 0, 0},
|
|
{"DFASET" , 8, 5, 11, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_13_63" , 13, 51, 11, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 12, "R/W", 0, 0, 24ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 12, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_EN" , 0, 4, 13, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 13, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 14, "R/W", 0, 0, 24ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 14, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 5, 15, "R/W", 0, 0, 6ull, 6ull},
|
|
{"RESERVED_5_7" , 5, 3, 15, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL" , 8, 5, 15, "R/W", 0, 0, 9ull, 9ull},
|
|
{"RESERVED_13_63" , 13, 51, 15, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 4, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 16, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_EN" , 0, 4, 17, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 17, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 4, 18, "R/W", 0, 1, 15ull, 0},
|
|
{"PCTL" , 4, 5, 18, "R/W", 0, 1, 31ull, 0},
|
|
{"RESERVED_9_63" , 9, 55, 18, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 19, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 19, "RAZ", 1, 1, 0, 0},
|
|
{"BIST" , 0, 4, 20, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 20, "RAZ", 1, 1, 0, 0},
|
|
{"DINT" , 0, 16, 21, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 21, "RAZ", 1, 1, 0, 0},
|
|
{"FUSE" , 0, 16, 22, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_16_63" , 16, 48, 22, "RAZ", 1, 1, 0, 0},
|
|
{"GSTOP" , 0, 1, 23, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 23, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 24, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 24, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 16, 25, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 25, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 26, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 26, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 26, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 26, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 26, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 26, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 26, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 26, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 26, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 26, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 26, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 26, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 26, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 26, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 26, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 16, 27, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 27, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 28, "RO", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 28, "RO", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 28, "RO", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 28, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 28, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 28, "RO", 0, 0, 0ull, 0ull},
|
|
{"WDOG_SUM" , 44, 1, 28, "RO", 0, 0, 0ull, 0ull},
|
|
{"TWSI" , 45, 1, 28, "RO", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 28, "RO", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 28, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 28, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 28, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 28, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 28, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 28, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 29, "RO", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 29, "RO", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 29, "RO", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 29, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 29, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 29, "RO", 0, 0, 0ull, 0ull},
|
|
{"WDOG_SUM" , 44, 1, 29, "RO", 0, 0, 0ull, 0ull},
|
|
{"TWSI" , 45, 1, 29, "RO", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 29, "RO", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 29, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 29, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 29, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 29, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 29, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 29, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 16, 30, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 30, "RAZ", 1, 1, 0, 0},
|
|
{"BITS" , 0, 32, 31, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 31, "RAZ", 1, 1, 0, 0},
|
|
{"BITS" , 0, 32, 32, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 32, "RAZ", 1, 1, 0, 0},
|
|
{"NMI" , 0, 16, 33, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 33, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 0, 2, 34, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 34, "RAZ", 1, 1, 0, 0},
|
|
{"PPDBG" , 0, 16, 35, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 35, "RAZ", 1, 1, 0, 0},
|
|
{"POKE" , 0, 64, 36, "RAZ", 1, 1, 0, 0},
|
|
{"RST0" , 0, 1, 37, "R/W", 1, 1, 0, 0},
|
|
{"RST" , 1, 15, 37, "R/W", 0, 0, 32767ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 37, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_BIST" , 0, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 38, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_PRST" , 0, 1, 39, "R/W", 0, 0, 1ull, 0ull},
|
|
{"NPI" , 1, 1, 39, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HOST64" , 2, 1, 39, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_3_63" , 3, 61, 39, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_RST" , 0, 1, 40, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 40, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 36, 41, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ONE_SHOT" , 36, 1, 41, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 41, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 0, 2, 42, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STATE" , 2, 2, 42, "RO", 0, 0, 0ull, 0ull},
|
|
{"LEN" , 4, 16, 42, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 20, 24, 42, "RO", 0, 0, 0ull, 0ull},
|
|
{"DSTOP" , 44, 1, 42, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GSTOPEN" , 45, 1, 42, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_46_63" , 46, 18, 42, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 17, 43, "RO", 0, 1, 0ull, 0},
|
|
{"DSEL_EXT" , 17, 1, 43, "R/W", 0, 0, 1ull, 0ull},
|
|
{"C_MUL" , 18, 5, 43, "RO", 1, 1, 0, 0},
|
|
{"REM" , 23, 6, 43, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 43, "RAZ", 1, 1, 0, 0},
|
|
{"PDF" , 0, 4, 44, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_15" , 4, 12, 44, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RDF" , 16, 4, 44, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 44, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"P1_BRF" , 0, 8, 45, "RO", 0, 0, 0ull, 0ull},
|
|
{"P0_BRF" , 8, 8, 45, "RO", 0, 0, 0ull, 0ull},
|
|
{"P1_BWB" , 16, 1, 45, "RO", 0, 0, 0ull, 0ull},
|
|
{"P0_BWB" , 17, 1, 45, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRF" , 18, 1, 45, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_19" , 19, 1, 45, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"GFU" , 20, 1, 45, "RO", 0, 0, 0ull, 0ull},
|
|
{"IFU" , 21, 1, 45, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRQ" , 22, 1, 45, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 45, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SARB" , 0, 1, 46, "R/W", 0, 0, 1ull, 1ull},
|
|
{"GXOR_ENA" , 1, 1, 46, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NXOR_ENA" , 2, 1, 46, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NRPL_ENA" , 3, 1, 46, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 46, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 20, 47, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_63" , 20, 44, 47, "RAZ", 1, 1, 0, 0},
|
|
{"SIZE" , 0, 9, 48, "R/W", 0, 1, 3ull, 0},
|
|
{"POOL" , 9, 3, 48, "R/W", 0, 1, 0ull, 0},
|
|
{"DWBCNT" , 12, 8, 48, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_20_63" , 20, 44, 48, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_4" , 0, 5, 49, "RAZ", 1, 1, 0, 0},
|
|
{"RDPTR" , 5, 31, 49, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 49, "RAZ", 1, 1, 0, 0},
|
|
{"CP2ECCENA" , 0, 1, 50, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2SBE" , 1, 1, 50, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CP2DBE" , 2, 1, 50, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CP2SBINA" , 3, 1, 50, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2DBINA" , 4, 1, 50, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2SYN" , 5, 8, 50, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTEECCENA" , 13, 1, 50, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DTESBE" , 14, 1, 50, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTEDBE" , 15, 1, 50, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTESBINA" , 16, 1, 50, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DTEDBINA" , 17, 1, 50, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DTESYN" , 18, 7, 50, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTEPARENA" , 25, 1, 50, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DTEPERR" , 26, 1, 50, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTEPINA" , 27, 1, 50, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2PARENA" , 28, 1, 50, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2PERR" , 29, 1, 50, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CP2PINA" , 30, 1, 50, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DBLOVF" , 31, 1, 50, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DBLINA" , 32, 1, 50, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_33_63" , 33, 31, 50, "RAZ", 1, 1, 0, 0},
|
|
{"ENA_P1" , 0, 1, 51, "R/W", 0, 0, 1ull, 1ull},
|
|
{"ENA_P0" , 1, 1, 51, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_2" , 2, 1, 51, "RAZ", 1, 1, 0, 0},
|
|
{"MTYPE" , 3, 1, 51, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SIL_LAT" , 4, 2, 51, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RW_DLY" , 6, 4, 51, "R/W", 0, 0, 1ull, 1ull},
|
|
{"WR_DLY" , 10, 4, 51, "R/W", 0, 0, 2ull, 2ull},
|
|
{"FPRCH" , 14, 2, 51, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BPRCH" , 16, 2, 51, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BLEN" , 18, 1, 51, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PBUNK" , 19, 3, 51, "R/W", 0, 0, 2ull, 2ull},
|
|
{"R2R_PBUNK" , 22, 1, 51, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INIT_P1" , 23, 1, 51, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INIT_P0" , 24, 1, 51, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BUNK_INIT" , 25, 2, 51, "R/W", 0, 0, 3ull, 3ull},
|
|
{"LPP_ENA" , 27, 1, 51, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLKDIV" , 28, 2, 51, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RLDCK_RST" , 30, 1, 51, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RLDQCK90_RST" , 31, 1, 51, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 51, "RAZ", 1, 1, 0, 0},
|
|
{"REF_INT" , 0, 4, 52, "R/W", 0, 0, 3ull, 3ull},
|
|
{"TSKW" , 4, 2, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 52, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TRL" , 8, 4, 52, "R/W", 0, 0, 6ull, 6ull},
|
|
{"TWL" , 12, 4, 52, "R/W", 0, 0, 7ull, 7ull},
|
|
{"TRC" , 16, 4, 52, "R/W", 0, 0, 6ull, 6ull},
|
|
{"TMRSC" , 20, 3, 52, "R/W", 0, 0, 6ull, 6ull},
|
|
{"MRS_ENA" , 23, 1, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AREF_ENA" , 24, 1, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"REF_INTLO" , 25, 9, 52, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 52, "RAZ", 1, 1, 0, 0},
|
|
{"FCRAM2P" , 0, 1, 53, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAXBNK" , 1, 1, 53, "R/W", 0, 0, 1ull, 1ull},
|
|
{"UA_START" , 2, 2, 53, "R/W", 0, 0, 1ull, 1ull},
|
|
{"REFSHORT" , 4, 1, 53, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRFC" , 5, 5, 53, "R/W", 0, 0, 9ull, 9ull},
|
|
{"SILRST" , 10, 1, 53, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DTECLKDIS" , 11, 1, 53, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 53, "RAZ", 1, 1, 0, 0},
|
|
{"MADDR" , 0, 24, 54, "RO", 0, 0, 0ull, 0ull},
|
|
{"BNUM" , 24, 3, 54, "RO", 0, 0, 0ull, 0ull},
|
|
{"PNUM" , 27, 1, 54, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSRC" , 28, 2, 54, "RO", 0, 0, 0ull, 0ull},
|
|
{"FDST" , 30, 9, 54, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_39_63" , 39, 25, 54, "RAZ", 1, 1, 0, 0},
|
|
{"MRS" , 0, 15, 55, "R/W", 0, 0, 66ull, 66ull},
|
|
{"RESERVED_15_15" , 15, 1, 55, "RAZ", 1, 1, 0, 0},
|
|
{"EMRS" , 16, 15, 55, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_31_31" , 31, 1, 55, "RAZ", 1, 1, 0, 0},
|
|
{"EMRS2" , 32, 15, 55, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_47_63" , 47, 17, 55, "RAZ", 1, 1, 0, 0},
|
|
{"MRSDAT" , 0, 23, 56, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_23_63" , 23, 41, 56, "RAZ", 1, 1, 0, 0},
|
|
{"IMODE" , 0, 1, 57, "R/W", 0, 0, 1ull, 1ull},
|
|
{"QMODE" , 1, 1, 57, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PMODE" , 2, 1, 57, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DTMODE" , 3, 1, 57, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DCMODE" , 4, 1, 57, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SBDLCK" , 5, 1, 57, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SBDNUM" , 6, 5, 57, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 57, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL" , 0, 5, 58, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 58, "RAZ", 0, 1, 0ull, 0},
|
|
{"NCTL" , 8, 4, 58, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_12_15" , 12, 4, 58, "RAZ", 0, 1, 0ull, 0},
|
|
{"ENABLE" , 16, 1, 58, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_17_63" , 17, 47, 58, "RAZ", 0, 1, 0ull, 0},
|
|
{"SBD0" , 0, 64, 59, "RO", 1, 1, 0, 0},
|
|
{"SBD1" , 0, 64, 60, "RO", 1, 1, 0, 0},
|
|
{"SBD2" , 0, 64, 61, "RO", 1, 1, 0, 0},
|
|
{"SBD3" , 0, 64, 62, "RO", 1, 1, 0, 0},
|
|
{"FDR" , 0, 1, 63, "RO", 0, 0, 0ull, 0ull},
|
|
{"FFR" , 1, 1, 63, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPF1" , 2, 1, 63, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPF0" , 3, 1, 63, "RO", 0, 0, 0ull, 0ull},
|
|
{"FRD" , 4, 1, 63, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 63, "RAZ", 1, 1, 0, 0},
|
|
{"MEM0_ERR" , 0, 7, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM1_ERR" , 7, 7, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 14, 1, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USE_STT" , 15, 1, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USE_LDT" , 16, 1, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 17, 1, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 64, "RAZ", 1, 1, 0, 0},
|
|
{"FPF_RD" , 0, 11, 65, "R/W", 0, 0, 64ull, 0ull},
|
|
{"FPF_WR" , 11, 11, 65, "R/W", 0, 0, 196ull, 0ull},
|
|
{"RESERVED_22_63" , 22, 42, 65, "RAZ", 1, 1, 0, 0},
|
|
{"FPF_SIZ" , 0, 11, 66, "R/W", 0, 0, 256ull, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 66, "RAZ", 1, 1, 0, 0},
|
|
{"FPF_RD" , 0, 12, 67, "R/W", 0, 0, 64ull, 0ull},
|
|
{"FPF_WR" , 12, 12, 67, "R/W", 0, 0, 196ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 67, "RAZ", 1, 1, 0, 0},
|
|
{"FPF_SIZ" , 0, 12, 68, "R/W", 0, 0, 256ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 68, "RAZ", 1, 1, 0, 0},
|
|
{"FED0_SBE" , 0, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED0_DBE" , 1, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED1_SBE" , 2, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED1_DBE" , 3, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_UND" , 4, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_COFF" , 5, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_PERR" , 6, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_UND" , 7, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_COFF" , 8, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_PERR" , 9, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_UND" , 10, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_COFF" , 11, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_PERR" , 12, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_UND" , 13, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_COFF" , 14, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_PERR" , 15, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_UND" , 16, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_COFF" , 17, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_PERR" , 18, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_UND" , 19, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_COFF" , 20, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_PERR" , 21, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_UND" , 22, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_COFF" , 23, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_PERR" , 24, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_UND" , 25, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_COFF" , 26, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_PERR" , 27, 1, 69, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 69, "RAZ", 1, 1, 0, 0},
|
|
{"FED0_SBE" , 0, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED0_DBE" , 1, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED1_SBE" , 2, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED1_DBE" , 3, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_UND" , 4, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_COFF" , 5, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_PERR" , 6, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_UND" , 7, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_COFF" , 8, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_PERR" , 9, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_UND" , 10, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_COFF" , 11, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_PERR" , 12, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_UND" , 13, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_COFF" , 14, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_PERR" , 15, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_UND" , 16, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_COFF" , 17, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_PERR" , 18, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_UND" , 19, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_COFF" , 20, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_PERR" , 21, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_UND" , 22, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_COFF" , 23, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_PERR" , 24, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_UND" , 25, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_COFF" , 26, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_PERR" , 27, 1, 70, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 70, "RAZ", 1, 1, 0, 0},
|
|
{"QUE_SIZ" , 0, 29, 71, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 71, "RAZ", 1, 1, 0, 0},
|
|
{"PG_NUM" , 0, 25, 72, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 72, "RAZ", 1, 1, 0, 0},
|
|
{"ACT_INDX" , 0, 26, 73, "RO", 0, 1, 0ull, 0},
|
|
{"ACT_QUE" , 26, 3, 73, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 73, "RAZ", 0, 0, 0ull, 7ull},
|
|
{"EXP_INDX" , 0, 26, 74, "RO", 0, 1, 0ull, 0},
|
|
{"EXP_QUE" , 26, 3, 74, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 74, "RAZ", 0, 0, 0ull, 7ull},
|
|
{"CTL" , 0, 16, 75, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 75, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 32, 76, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 76, "RAZ", 1, 1, 0, 0},
|
|
{"OUT_COL" , 0, 1, 77, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NCB_OVR" , 1, 1, 77, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OUT_OVR" , 2, 16, 77, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_21" , 18, 4, 77, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LOSTSTAT" , 22, 4, 77, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"STATOVR" , 26, 1, 77, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INB_NXA" , 27, 4, 77, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 77, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 17, 78, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 78, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 1, 79, "RO", 1, 1, 0, 0},
|
|
{"EN" , 1, 1, 79, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_2_63" , 2, 62, 79, "RAZ", 1, 1, 0, 0},
|
|
{"PRT" , 0, 6, 80, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 80, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 81, "R/W", 0, 1, 0ull, 0},
|
|
{"SPEED" , 1, 1, 81, "R/W", 0, 1, 1ull, 0},
|
|
{"DUPLEX" , 2, 1, 81, "R/W", 0, 1, 1ull, 0},
|
|
{"SLOTTIME" , 3, 1, 81, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 81, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 64, 82, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 83, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 84, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 85, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 86, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 87, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 0, 8, 88, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 88, "RAZ", 1, 1, 0, 0},
|
|
{"BCST" , 0, 1, 89, "R/W", 0, 1, 1ull, 0},
|
|
{"MCST" , 1, 2, 89, "R/W", 0, 1, 0ull, 0},
|
|
{"CAM_MODE" , 3, 1, 89, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 89, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 5, 90, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_5_63" , 5, 59, 90, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 91, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CAREXT" , 1, 1, 91, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MAXERR" , 2, 1, 91, "R/W", 0, 0, 1ull, 1ull},
|
|
{"JABBER" , 3, 1, 91, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCSERR" , 4, 1, 91, "R/W", 0, 0, 1ull, 1ull},
|
|
{"ALNERR" , 5, 1, 91, "R/W", 0, 0, 1ull, 1ull},
|
|
{"LENERR" , 6, 1, 91, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RCVERR" , 7, 1, 91, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SKPERR" , 8, 1, 91, "R/W", 0, 0, 1ull, 1ull},
|
|
{"NIBERR" , 9, 1, 91, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_10_63" , 10, 54, 91, "RAZ", 1, 1, 0, 0},
|
|
{"PRE_CHK" , 0, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PRE_STRP" , 1, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_DRP" , 2, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_BCK" , 3, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_MCST" , 4, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_SMAC" , 5, 1, 92, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PRE_FREE" , 6, 1, 92, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VLAN_LEN" , 7, 1, 92, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PAD_LEN" , 8, 1, 92, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 92, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 16, 93, "R/W", 0, 0, 1536ull, 1536ull},
|
|
{"RESERVED_16_63" , 16, 48, 93, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 16, 94, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_16_63" , 16, 48, 94, "RAZ", 1, 1, 0, 0},
|
|
{"IFG" , 0, 4, 95, "R/W", 0, 0, 12ull, 12ull},
|
|
{"RESERVED_4_63" , 4, 60, 95, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 96, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAREXT" , 1, 1, 96, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 2, 1, 96, "R/W", 0, 0, 0ull, 0ull},
|
|
{"JABBER" , 3, 1, 96, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 96, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ALNERR" , 5, 1, 96, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 6, 1, 96, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RCVERR" , 7, 1, 96, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 96, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NIBERR" , 9, 1, 96, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OVRERR" , 10, 1, 96, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 96, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 96, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 96, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 96, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 96, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHY_LINK" , 16, 1, 96, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHY_SPD" , 17, 1, 96, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHY_DUPX" , 18, 1, 96, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PAUSE_DRP" , 19, 1, 96, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 96, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CAREXT" , 1, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 2, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"JABBER" , 3, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ALNERR" , 5, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 6, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RCVERR" , 7, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NIBERR" , 9, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OVRERR" , 10, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PHY_LINK" , 16, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PHY_SPD" , 17, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PHY_DUPX" , 18, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PAUSE_DRP" , 19, 1, 97, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 97, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 98, "R/W", 0, 0, 10240ull, 10240ull},
|
|
{"RESERVED_16_63" , 16, 48, 98, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 16, 99, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 99, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 1, 100, "RO", 0, 1, 0ull, 0},
|
|
{"SPEED" , 1, 2, 100, "RO", 0, 1, 0ull, 0},
|
|
{"DUPLEX" , 3, 1, 100, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 100, "RAZ", 1, 1, 0, 0},
|
|
{"RD_CLR" , 0, 1, 101, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 101, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 102, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 102, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 103, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 103, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 104, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 104, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 105, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 105, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 106, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 106, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 107, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 107, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 108, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 108, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 109, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 109, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 110, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 110, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 7, 111, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 111, "RAZ", 1, 1, 0, 0},
|
|
{"FCSSEL" , 8, 1, 111, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 111, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 112, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_6_63" , 6, 58, 112, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 113, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_6_63" , 6, 58, 113, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 9, 114, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_9_63" , 9, 55, 114, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 16, 115, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 115, "RAZ", 1, 1, 0, 0},
|
|
{"DPRT" , 0, 4, 116, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 116, "RAZ", 1, 1, 0, 0},
|
|
{"COMMIT" , 0, 16, 117, "RO", 0, 0, 0ull, 0ull},
|
|
{"DROP" , 16, 16, 117, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 117, "RAZ", 1, 1, 0, 0},
|
|
{"PRTS" , 0, 3, 118, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_3_63" , 3, 61, 118, "RAZ", 1, 1, 0, 0},
|
|
{"SMAC" , 0, 48, 119, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 119, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 120, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP" , 16, 1, 120, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 120, "RAZ", 1, 1, 0, 0},
|
|
{"PREAMBLE" , 0, 1, 121, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PAD" , 1, 1, 121, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCS" , 2, 1, 121, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FORCE_FCS" , 3, 1, 121, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 121, "RAZ", 1, 1, 0, 0},
|
|
{"BURST" , 0, 16, 122, "R/W", 0, 0, 8192ull, 8192ull},
|
|
{"RESERVED_16_63" , 16, 48, 122, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_CNT" , 0, 6, 123, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_63" , 6, 58, 123, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL_EN" , 0, 1, 124, "R/W", 0, 0, 1ull, 1ull},
|
|
{"XSDEF_EN" , 1, 1, 124, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 124, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_SIZE" , 0, 8, 125, "R/W", 0, 0, 59ull, 59ull},
|
|
{"RESERVED_8_63" , 8, 56, 125, "RAZ", 1, 1, 0, 0},
|
|
{"INTERVAL" , 0, 16, 126, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 126, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 127, "R/W", 0, 1, 96ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 127, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 128, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_16_63" , 16, 48, 128, "RAZ", 1, 1, 0, 0},
|
|
{"SEND" , 0, 1, 129, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 129, "RAZ", 1, 1, 0, 0},
|
|
{"SLOT" , 0, 10, 130, "R/W", 0, 0, 512ull, 512ull},
|
|
{"RESERVED_10_63" , 10, 54, 130, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 131, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 131, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL" , 0, 32, 132, "RC/W", 0, 1, 0ull, 0},
|
|
{"XSDEF" , 32, 32, 132, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCOL" , 0, 32, 133, "RC/W", 0, 1, 0ull, 0},
|
|
{"SCOL" , 32, 32, 133, "RC/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 134, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 134, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 135, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 135, "RAZ", 1, 1, 0, 0},
|
|
{"HIST0" , 0, 32, 136, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST1" , 32, 32, 136, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST2" , 0, 32, 137, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST3" , 32, 32, 137, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST4" , 0, 32, 138, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST5" , 32, 32, 138, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST6" , 0, 32, 139, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST7" , 32, 32, 139, "RC/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 0, 32, 140, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 32, 32, 140, "RC/W", 0, 1, 0ull, 0},
|
|
{"CTL" , 0, 32, 141, "RC/W", 0, 1, 0ull, 0},
|
|
{"UNDFLW" , 32, 32, 141, "RC/W", 0, 1, 0ull, 0},
|
|
{"RD_CLR" , 0, 1, 142, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 142, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 9, 143, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_9_63" , 9, 55, 143, "RAZ", 1, 1, 0, 0},
|
|
{"BP" , 0, 4, 144, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 144, "RAZ", 1, 1, 0, 0},
|
|
{"LIMIT" , 0, 5, 145, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_5_63" , 5, 59, 145, "RAZ", 1, 1, 0, 0},
|
|
{"CORRUPT" , 0, 4, 146, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_4_63" , 4, 60, 146, "RAZ", 1, 1, 0, 0},
|
|
{"IFG1" , 0, 4, 147, "R/W", 0, 1, 8ull, 0},
|
|
{"IFG2" , 4, 4, 147, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 147, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 148, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NCB_NXA" , 1, 1, 148, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 4, 148, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 148, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 4, 148, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 4, 148, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LATE_COL" , 16, 4, 148, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 148, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NCB_NXA" , 1, 1, 149, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 4, 149, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 149, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 4, 149, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 4, 149, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LATE_COL" , 16, 4, 149, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 149, "RAZ", 1, 1, 0, 0},
|
|
{"JAM" , 0, 8, 150, "R/W", 0, 1, 238ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 150, "RAZ", 1, 1, 0, 0},
|
|
{"LFSR" , 0, 16, 151, "R/W", 0, 1, 65535ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 151, "RAZ", 1, 1, 0, 0},
|
|
{"IGN_FULL" , 0, 4, 152, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP" , 4, 4, 152, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EN" , 8, 4, 152, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 152, "RAZ", 1, 1, 0, 0},
|
|
{"DMAC" , 0, 48, 153, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
|
|
{"RESERVED_48_63" , 48, 16, 153, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 154, "R/W", 0, 0, 34824ull, 34824ull},
|
|
{"RESERVED_16_63" , 16, 48, 154, "RAZ", 1, 1, 0, 0},
|
|
{"PRTS" , 0, 5, 155, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 155, "RAZ", 1, 1, 0, 0},
|
|
{"CONT_PKT" , 0, 1, 156, "R/W", 0, 1, 0ull, 0},
|
|
{"TPA_CLR" , 1, 1, 156, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 156, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DRAIN" , 0, 16, 157, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 157, "RAZ", 1, 1, 0, 0},
|
|
{"MAX1" , 0, 8, 158, "R/W", 0, 1, 8ull, 0},
|
|
{"MAX2" , 8, 8, 158, "R/W", 0, 1, 4ull, 0},
|
|
{"SLICE" , 16, 7, 158, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_23_63" , 23, 41, 158, "RAZ", 1, 1, 0, 0},
|
|
{"ROUND" , 0, 16, 159, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 159, "RAZ", 1, 1, 0, 0},
|
|
{"THRESH" , 0, 6, 160, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 160, "RAZ", 1, 1, 0, 0},
|
|
{"TX_OE" , 0, 1, 161, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RX_XOR" , 1, 1, 161, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_EN" , 2, 1, 161, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_TYPE" , 3, 1, 161, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_CNT" , 4, 4, 161, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_SEL" , 8, 4, 161, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 161, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 162, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 162, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 163, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 163, "RAZ", 1, 1, 0, 0},
|
|
{"CLR" , 0, 16, 164, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 164, "RAZ", 1, 1, 0, 0},
|
|
{"SET" , 0, 16, 165, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 165, "RAZ", 1, 1, 0, 0},
|
|
{"ICD" , 0, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBD" , 1, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRP1" , 2, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRP0" , 3, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRN1" , 4, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRN0" , 5, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBRQ1" , 6, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBRQ0" , 7, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNRT" , 8, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBR1" , 9, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBR0" , 10, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBDR1" , 11, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBDR0" , 12, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNR0" , 13, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNR1" , 14, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICR1" , 15, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICR0" , 16, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNRCB" , 17, 1, 166, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 166, "RAZ", 1, 1, 0, 0},
|
|
{"FAU_END" , 0, 1, 167, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB_ENB" , 1, 1, 167, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PKO_ENB" , 2, 1, 167, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INB_MAT" , 3, 1, 167, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OUTB_MAT" , 4, 1, 167, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 167, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 168, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 168, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 168, "RAZ", 1, 1, 0, 0},
|
|
{"TOUT_VAL" , 0, 12, 169, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TOUT_ENB" , 12, 1, 169, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 169, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 170, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 170, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 170, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 8, 171, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 8, 9, 171, "R/W", 0, 1, 0ull, 0},
|
|
{"OPC" , 17, 4, 171, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 21, 8, 171, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 171, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 8, 172, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 8, 9, 172, "R/W", 0, 1, 0ull, 0},
|
|
{"OPC" , 17, 4, 172, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 21, 8, 172, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 172, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 173, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 174, "R/W", 0, 1, 0ull, 0},
|
|
{"NP_SOP" , 0, 1, 175, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NP_EOP" , 1, 1, 175, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_SOP" , 2, 1, 175, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_EOP" , 3, 1, 175, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NP_DAT" , 4, 1, 175, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_DAT" , 5, 1, 175, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 175, "RAZ", 1, 1, 0, 0},
|
|
{"NP_SOP" , 0, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NP_EOP" , 1, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_SOP" , 2, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_EOP" , 3, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NP_DAT" , 4, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_DAT" , 5, 1, 176, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 176, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 177, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 177, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 177, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 178, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 178, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 178, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 179, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 179, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 179, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 9, 180, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 9, 8, 180, "R/W", 0, 1, 0ull, 0},
|
|
{"EOT" , 17, 1, 180, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 18, 8, 180, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_26_63" , 26, 38, 180, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 9, 181, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 9, 8, 181, "R/W", 0, 1, 0ull, 0},
|
|
{"EOT" , 17, 1, 181, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 18, 8, 181, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_26_63" , 26, 38, 181, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 182, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 183, "R/W", 0, 1, 0ull, 0},
|
|
{"CNT_VAL" , 0, 15, 184, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 184, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 184, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 185, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 185, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 185, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 186, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 186, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 186, "RAZ", 1, 1, 0, 0},
|
|
{"PORT" , 0, 6, 187, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 187, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP_SZ" , 0, 6, 188, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 188, "RAZ", 1, 1, 0, 0},
|
|
{"BACK" , 0, 4, 189, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 189, "RAZ", 1, 1, 0, 0},
|
|
{"BACK" , 0, 4, 190, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 190, "RAZ", 1, 1, 0, 0},
|
|
{"PWP" , 0, 1, 191, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_NEW" , 1, 1, 191, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_OLD" , 2, 1, 191, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRC_OFF" , 3, 1, 191, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ0" , 4, 1, 191, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ1" , 5, 1, 191, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM_WORD" , 6, 1, 191, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM0" , 7, 1, 191, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM1" , 8, 1, 191, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM2" , 9, 1, 191, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM3" , 10, 1, 191, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPQ_PBE0" , 11, 1, 191, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPQ_PBE1" , 12, 1, 191, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_POW" , 13, 1, 191, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_WP1" , 14, 1, 191, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_WQED" , 15, 1, 191, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 191, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_ENB" , 0, 36, 192, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 192, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_CNT" , 0, 64, 193, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_EN" , 0, 1, 194, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OPC_MODE" , 1, 2, 194, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PBP_EN" , 3, 1, 194, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WQE_LEND" , 4, 1, 194, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKT_LEND" , 5, 1, 194, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NADDBUF" , 6, 1, 194, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDPKT" , 7, 1, 194, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 8, 1, 194, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LEN_M8" , 9, 1, 194, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PKT_OFF" , 10, 1, 194, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPD_FULL" , 11, 1, 194, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 194, "RAZ", 1, 1, 0, 0},
|
|
{"PRC_PAR0" , 0, 1, 195, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR1" , 1, 1, 195, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR2" , 2, 1, 195, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR3" , 3, 1, 195, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_SUB" , 4, 1, 195, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DC_OVR" , 5, 1, 195, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CC_OVR" , 6, 1, 195, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C_COLL" , 7, 1, 195, "R/W", 0, 0, 0ull, 0ull},
|
|
{"D_COLL" , 8, 1, 195, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BC_OVR" , 9, 1, 195, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 195, "RAZ", 1, 1, 0, 0},
|
|
{"PRC_PAR0" , 0, 1, 196, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR1" , 1, 1, 196, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR2" , 2, 1, 196, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR3" , 3, 1, 196, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP_SUB" , 4, 1, 196, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DC_OVR" , 5, 1, 196, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CC_OVR" , 6, 1, 196, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C_COLL" , 7, 1, 196, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"D_COLL" , 8, 1, 196, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BC_OVR" , 9, 1, 196, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 196, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP_SZ" , 0, 6, 197, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 197, "RAZ", 1, 1, 0, 0},
|
|
{"MB_SIZE" , 0, 12, 198, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_12_63" , 12, 52, 198, "RAZ", 1, 1, 0, 0},
|
|
{"PTR" , 0, 29, 199, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 199, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 17, 200, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_ENB" , 17, 1, 200, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 200, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 25, 201, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 201, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 3, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 3, 1, 202, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 4, 29, 202, "RO", 1, 1, 0, 0},
|
|
{"PRADDR" , 33, 3, 202, "RO", 1, 1, 0, 0},
|
|
{"MAX_PKT" , 36, 3, 202, "RO", 0, 0, 5ull, 5ull},
|
|
{"RESERVED_39_63" , 39, 25, 202, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 7, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 7, 1, 203, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 8, 29, 203, "RO", 1, 1, 0, 0},
|
|
{"MAX_PKT" , 37, 7, 203, "RO", 0, 0, 36ull, 36ull},
|
|
{"RESERVED_44_63" , 44, 20, 203, "RAZ", 1, 1, 0, 0},
|
|
{"WQE_PCNT" , 0, 7, 204, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_PCNT" , 7, 7, 204, "RO", 0, 0, 0ull, 0ull},
|
|
{"PFIF_CNT" , 14, 3, 204, "RO", 0, 0, 0ull, 0ull},
|
|
{"WQEV_CNT" , 17, 1, 204, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTV_CNT" , 18, 1, 204, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 204, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 8, 205, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 8, 1, 205, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 9, 29, 205, "RO", 1, 1, 0, 0},
|
|
{"PRADDR" , 38, 8, 205, "RO", 1, 1, 0, 0},
|
|
{"WRADDR" , 46, 8, 205, "RO", 1, 1, 0, 0},
|
|
{"MAX_CNTS" , 54, 7, 205, "RO", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_61_63" , 61, 3, 205, "RAZ", 1, 1, 0, 0},
|
|
{"PASS" , 0, 32, 206, "R/W", 0, 1, 0ull, 0},
|
|
{"DROP" , 32, 32, 206, "R/W", 0, 1, 0ull, 0},
|
|
{"Q0_PCNT" , 0, 32, 207, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 207, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_ENB" , 0, 36, 208, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AVG_DLY" , 36, 14, 208, "R/W", 0, 1, 0ull, 0},
|
|
{"PRB_DLY" , 50, 14, 208, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRB_CON" , 0, 32, 209, "R/W", 0, 1, 0ull, 0},
|
|
{"AVG_CON" , 32, 8, 209, "R/W", 0, 1, 0ull, 0},
|
|
{"NEW_CON" , 40, 8, 209, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_PCNT" , 48, 1, 209, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 209, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 25, 210, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT" , 25, 6, 210, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 210, "RAZ", 1, 1, 0, 0},
|
|
{"PORT_BIT" , 0, 32, 211, "R/W", 0, 0, 4294967295ull, 4294967295ull},
|
|
{"RESERVED_32_63" , 32, 32, 211, "RAZ", 1, 1, 0, 0},
|
|
{"WQE_POOL" , 0, 3, 212, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_3_63" , 3, 61, 212, "RAZ", 1, 1, 0, 0},
|
|
{"PTR" , 0, 29, 213, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 213, "RAZ", 1, 1, 0, 0},
|
|
{"MEM0" , 0, 1, 214, "RO", 0, 0, 0ull, 0ull},
|
|
{"MEM1" , 1, 1, 214, "RO", 0, 0, 0ull, 0ull},
|
|
{"RRC" , 2, 1, 214, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 214, "RAZ", 1, 1, 0, 0},
|
|
{"MEM0_ERR" , 0, 7, 215, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM1_ERR" , 7, 7, 215, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 215, "RAZ", 1, 1, 0, 0},
|
|
{"KED0_SBE" , 0, 1, 216, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KED0_DBE" , 1, 1, 216, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KED1_SBE" , 2, 1, 216, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KED1_DBE" , 3, 1, 216, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 216, "RAZ", 1, 1, 0, 0},
|
|
{"KED0_SBE" , 0, 1, 217, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KED0_DBE" , 1, 1, 217, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KED1_SBE" , 2, 1, 217, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KED1_DBE" , 3, 1, 217, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 217, "RAZ", 1, 1, 0, 0},
|
|
{"WLB_DAT" , 0, 4, 218, "RO", 0, 0, 0ull, 0ull},
|
|
{"STIN_MSK" , 4, 1, 218, "RO", 0, 0, 0ull, 0ull},
|
|
{"DT" , 5, 1, 218, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTCNT" , 6, 13, 218, "RO", 0, 0, 0ull, 0ull},
|
|
{"WLB_MSK" , 19, 4, 218, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTBNK" , 23, 1, 218, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 218, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"L2T" , 0, 9, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"VAB_VWCF" , 9, 1, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"LRF" , 10, 2, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"VWDF" , 12, 4, 219, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 219, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XRDDAT" , 0, 1, 220, "RO", 0, 0, 0ull, 0ull},
|
|
{"XRDMSK" , 1, 1, 220, "RO", 0, 0, 0ull, 0ull},
|
|
{"PICBST" , 2, 1, 220, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPCBST" , 3, 1, 220, "RO", 0, 0, 0ull, 0ull},
|
|
{"RHDB" , 4, 4, 220, "RO", 0, 0, 0ull, 0ull},
|
|
{"RMDB" , 8, 4, 220, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRB" , 12, 4, 220, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 220, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LRF_ARB_MODE" , 0, 1, 221, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RFB_ARB_MODE" , 1, 1, 221, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RSP_ARB_MODE" , 2, 1, 221, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MWF_CRD" , 3, 4, 221, "R/W", 0, 0, 2ull, 2ull},
|
|
{"IDXALIAS" , 7, 1, 221, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPEN" , 8, 1, 221, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FPEMPTY" , 9, 1, 221, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FPEXP" , 10, 4, 221, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DFILL_DIS" , 14, 1, 221, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 221, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"L2T" , 0, 1, 222, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2D" , 1, 1, 222, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FINV" , 2, 1, 222, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SET" , 3, 3, 222, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PPNUM" , 6, 4, 222, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LFB_DMP" , 10, 1, 222, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LFB_ENUM" , 11, 4, 222, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 222, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DT_TAG" , 0, 29, 223, "RO", 0, 0, 0ull, 0ull},
|
|
{"DT_VLD" , 29, 1, 223, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_30" , 30, 1, 223, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DTENA" , 31, 1, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 223, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_ENA" , 0, 1, 224, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_3" , 1, 3, 224, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_BASE" , 4, 27, 224, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 224, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_OFFSET" , 0, 10, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 225, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VLD" , 0, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"CMD" , 1, 4, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"SID" , 5, 9, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"VABNUM" , 14, 4, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"SET" , 18, 3, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"IHD" , 21, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"ITL" , 22, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"INXT" , 23, 4, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"VAM" , 27, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"STCFL" , 28, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"STINV" , 29, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"STPND" , 30, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"STCPND" , 31, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 226, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VLD" , 0, 1, 227, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTPRB" , 1, 1, 227, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRBRTY" , 2, 1, 227, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTMFL" , 3, 1, 227, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTVTM" , 4, 1, 227, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTRSC" , 5, 1, 227, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTRSP" , 6, 1, 227, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTDT" , 7, 1, 227, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTRDA" , 8, 1, 227, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTM" , 9, 1, 227, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWRM" , 10, 1, 227, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWHF" , 11, 1, 227, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWHP" , 12, 1, 227, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTDQ" , 13, 1, 227, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTDW" , 14, 1, 227, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTRSP" , 15, 1, 227, "RO", 0, 0, 0ull, 0ull},
|
|
{"BID" , 16, 2, 227, "RO", 0, 0, 0ull, 0ull},
|
|
{"DSGOING" , 18, 1, 227, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 227, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_IDX" , 0, 11, 228, "RO", 0, 0, 0ull, 0ull},
|
|
{"LFB_TAG" , 11, 16, 228, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_63" , 27, 37, 228, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_HWM" , 0, 4, 229, "R/W", 0, 0, 15ull, 15ull},
|
|
{"STPARTDIS" , 4, 1, 229, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 229, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PFCNT0" , 0, 36, 230, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 230, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT0SEL" , 0, 6, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0CLR" , 6, 1, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0ENA" , 7, 1, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1SEL" , 8, 6, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1CLR" , 14, 1, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1ENA" , 15, 1, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2SEL" , 16, 6, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2CLR" , 22, 1, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2ENA" , 23, 1, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3SEL" , 24, 6, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3CLR" , 30, 1, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3ENA" , 31, 1, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0RDCLR" , 32, 1, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1RDCLR" , 33, 1, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2RDCLR" , 34, 1, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3RDCLR" , 35, 1, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 231, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK0" , 0, 8, 232, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK1" , 8, 8, 232, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK2" , 16, 8, 232, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK3" , 24, 8, 232, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 232, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK4" , 0, 8, 233, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK5" , 8, 8, 233, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK6" , 16, 8, 233, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK7" , 24, 8, 233, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 233, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK8" , 0, 8, 234, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK9" , 8, 8, 234, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK10" , 16, 8, 234, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK11" , 24, 8, 234, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 234, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK12" , 0, 8, 235, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK13" , 8, 8, 235, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK14" , 16, 8, 235, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK15" , 24, 8, 235, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 235, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSKIOB" , 0, 8, 236, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 236, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q0STAT" , 0, 34, 237, "RO", 0, 0, 0ull, 0ull},
|
|
{"FTL" , 34, 1, 237, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_35_63" , 35, 29, 237, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q1STAT" , 0, 34, 238, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 238, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q2STAT" , 0, 34, 239, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 239, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q3STAT" , 0, 34, 240, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 240, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 0, 1, 241, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_INTENA" , 1, 1, 241, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DED_INTENA" , 2, 1, 241, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 3, 1, 241, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 4, 1, 241, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BMHCLSEL" , 5, 1, 241, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 241, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 0, 11, 242, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSET" , 11, 3, 242, "RO", 0, 0, 0ull, 0ull},
|
|
{"FOWMSK" , 14, 4, 242, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADRU" , 18, 1, 242, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 242, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW0" , 0, 10, 243, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW1" , 10, 10, 243, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 243, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW2" , 0, 10, 244, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW3" , 10, 10, 244, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 244, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q0FUS" , 0, 34, 245, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 245, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q1FUS" , 0, 34, 246, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 246, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q2FUS" , 0, 34, 247, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 247, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q3FUS" , 0, 34, 248, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRIP_1024K" , 34, 1, 248, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRIP_512K" , 35, 1, 248, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_36" , 36, 1, 248, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EMA_CTL" , 37, 2, 248, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_39_63" , 39, 25, 248, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 0, 1, 249, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_INTENA" , 1, 1, 249, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DED_INTENA" , 2, 1, 249, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 3, 1, 249, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 4, 1, 249, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FSYN" , 5, 6, 249, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 11, 10, 249, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSET" , 21, 3, 249, "RO", 0, 0, 0ull, 0ull},
|
|
{"LCKERR" , 24, 1, 249, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK_INTENA" , 25, 1, 249, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LCKERR2" , 26, 1, 249, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK_INTENA2" , 27, 1, 249, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FADRU" , 28, 1, 249, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 249, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RATE" , 0, 8, 250, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_8_63" , 8, 56, 250, "RAZ", 1, 1, 0, 0},
|
|
{"PHASE" , 0, 7, 251, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_7_63" , 7, 57, 251, "RAZ", 1, 1, 0, 0},
|
|
{"RATE" , 0, 16, 252, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 252, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_EN" , 0, 1, 253, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 253, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 254, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 254, "RAZ", 1, 1, 0, 0},
|
|
{"POLARITY" , 0, 1, 255, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 255, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_EN" , 0, 8, 256, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 256, "RAZ", 1, 1, 0, 0},
|
|
{"FORMAT" , 0, 4, 257, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 257, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 6, 258, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 258, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 6, 259, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 259, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 32, 260, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 260, "RAZ", 1, 1, 0, 0},
|
|
{"CLR" , 0, 32, 261, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 261, "RAZ", 1, 1, 0, 0},
|
|
{"SET" , 0, 32, 262, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 262, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL_DAT" , 0, 4, 263, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_11" , 4, 8, 263, "RAZ", 0, 1, 0ull, 0},
|
|
{"PCTL_CSR" , 12, 4, 263, "R/W", 0, 1, 15ull, 0},
|
|
{"NCTL_DAT" , 16, 4, 263, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_27" , 20, 8, 263, "RAZ", 0, 1, 0ull, 0},
|
|
{"NCTL_CSR" , 28, 4, 263, "R/W", 0, 1, 15ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 263, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DIC" , 0, 2, 264, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QS_DIC" , 2, 2, 264, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TSKW" , 4, 2, 264, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SIL_LAT" , 6, 2, 264, "R/W", 0, 0, 1ull, 1ull},
|
|
{"BPRCH" , 8, 1, 264, "R/W", 0, 1, 0ull, 0},
|
|
{"FPRCH2" , 9, 1, 264, "R/W", 0, 0, 0ull, 1ull},
|
|
{"MODE128B" , 10, 1, 264, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DRESET" , 11, 1, 264, "R/W", 0, 0, 1ull, 0ull},
|
|
{"INORDER_MRF" , 12, 1, 264, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INORDER_MWF" , 13, 1, 264, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"R2R_SLOT" , 14, 1, 264, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RDIMM_ENA" , 15, 1, 264, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_17" , 16, 2, 264, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX_WRITE_BATCH" , 18, 4, 264, "R/W", 0, 0, 8ull, 8ull},
|
|
{"XOR_BANK" , 22, 1, 264, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SLOW_SCF" , 23, 1, 264, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DDR__PCTL" , 24, 4, 264, "RO", 1, 1, 0, 0},
|
|
{"DDR__NCTL" , 28, 4, 264, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 264, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 265, "RAZ", 0, 1, 0ull, 0},
|
|
{"DCC_ENABLE" , 8, 1, 265, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SIL_MODE" , 9, 1, 265, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_10_63" , 10, 54, 265, "RAZ", 1, 1, 0, 0},
|
|
{"DCLKCNT_HI" , 0, 32, 266, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 266, "RAZ", 1, 1, 0, 0},
|
|
{"DCLKCNT_LO" , 0, 32, 267, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 267, "RAZ", 1, 1, 0, 0},
|
|
{"DDR2" , 0, 1, 268, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RDQS" , 1, 1, 268, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLL90_BYP" , 2, 1, 268, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLL90_VLU" , 3, 5, 268, "R/W", 0, 1, 0ull, 0},
|
|
{"QDLL_ENA" , 8, 1, 268, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ODT_ENA" , 9, 1, 268, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DDR2T" , 10, 1, 268, "R/W", 0, 1, 0ull, 0},
|
|
{"CRIP_MODE" , 11, 1, 268, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TFAW" , 12, 5, 268, "R/W", 0, 0, 0ull, 9ull},
|
|
{"DDR_EOF" , 17, 4, 268, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SILO_HC" , 21, 1, 268, "R/W", 0, 1, 1ull, 0},
|
|
{"TWR" , 22, 3, 268, "R/W", 0, 0, 3ull, 1ull},
|
|
{"BWCNT" , 25, 1, 268, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POCAS" , 26, 1, 268, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDLAT" , 27, 3, 268, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BURST8" , 30, 1, 268, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BANK8" , 31, 1, 268, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 268, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CLK" , 0, 4, 269, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_4" , 4, 1, 269, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CMD" , 5, 4, 269, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 269, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DQ" , 10, 4, 269, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 269, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CS_MASK" , 0, 8, 270, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_15" , 8, 8, 270, "RAZ", 0, 1, 0ull, 0},
|
|
{"ROW_LSB" , 16, 3, 270, "R/W", 0, 1, 3ull, 0},
|
|
{"BANK8" , 19, 1, 270, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_63" , 20, 44, 270, "RAZ", 0, 1, 0ull, 0},
|
|
{"MRDSYN0" , 0, 8, 271, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN1" , 8, 8, 271, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN2" , 16, 8, 271, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN3" , 24, 8, 271, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 271, "RAZ", 1, 1, 0, 0},
|
|
{"FCOL" , 0, 12, 272, "RO", 0, 0, 0ull, 0ull},
|
|
{"FROW" , 12, 14, 272, "RO", 0, 0, 0ull, 0ull},
|
|
{"FBANK" , 26, 3, 272, "RO", 0, 0, 0ull, 0ull},
|
|
{"FBUNK" , 29, 1, 272, "RO", 0, 0, 0ull, 0ull},
|
|
{"FDIMM" , 30, 2, 272, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 272, "RAZ", 1, 1, 0, 0},
|
|
{"IFBCNT_HI" , 0, 32, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 273, "RAZ", 1, 1, 0, 0},
|
|
{"IFBCNT_LO" , 0, 32, 274, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 274, "RAZ", 1, 1, 0, 0},
|
|
{"INIT_START" , 0, 1, 275, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 1, 1, 275, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ROW_LSB" , 2, 3, 275, "R/W", 0, 1, 3ull, 0},
|
|
{"PBANK_LSB" , 5, 4, 275, "R/W", 0, 1, 5ull, 0},
|
|
{"REF_INT" , 9, 6, 275, "R/W", 0, 0, 1ull, 2ull},
|
|
{"TCL" , 15, 4, 275, "R/W", 0, 1, 3ull, 0},
|
|
{"INTR_SEC_ENA" , 19, 1, 275, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INTR_DED_ENA" , 20, 1, 275, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 21, 4, 275, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 25, 4, 275, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BUNK_ENA" , 29, 1, 275, "R/W", 0, 1, 0ull, 0},
|
|
{"SILO_QC" , 30, 1, 275, "R/W", 0, 1, 0ull, 0},
|
|
{"RESET" , 31, 1, 275, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 275, "RAZ", 1, 1, 0, 0},
|
|
{"TRAS" , 0, 5, 276, "R/W", 0, 0, 12ull, 12ull},
|
|
{"TRCD" , 5, 4, 276, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TWTR" , 9, 4, 276, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TRP" , 13, 4, 276, "R/W", 0, 0, 5ull, 4ull},
|
|
{"TRFC" , 17, 5, 276, "R/W", 0, 0, 6ull, 7ull},
|
|
{"TMRD" , 22, 3, 276, "R/W", 0, 0, 2ull, 2ull},
|
|
{"CASLAT" , 25, 3, 276, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TRRD" , 28, 3, 276, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_31_63" , 31, 33, 276, "RAZ", 1, 1, 0, 0},
|
|
{"OPSCNT_HI" , 0, 32, 277, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 277, "RAZ", 1, 1, 0, 0},
|
|
{"OPSCNT_LO" , 0, 32, 278, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 278, "RAZ", 1, 1, 0, 0},
|
|
{"EN2" , 0, 1, 279, "R/W", 0, 1, 0ull, 0},
|
|
{"EN4" , 1, 1, 279, "R/W", 0, 1, 0ull, 0},
|
|
{"EN6" , 2, 1, 279, "R/W", 0, 1, 0ull, 0},
|
|
{"EN8" , 3, 1, 279, "R/W", 0, 1, 1ull, 0},
|
|
{"EN12" , 4, 1, 279, "R/W", 0, 1, 0ull, 0},
|
|
{"EN16" , 5, 1, 279, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_7" , 6, 2, 279, "RAZ", 0, 1, 0ull, 0},
|
|
{"CLKR" , 8, 6, 279, "R/W", 0, 1, 0ull, 0},
|
|
{"CLKF" , 14, 12, 279, "R/W", 0, 1, 31ull, 0},
|
|
{"RESET_N" , 26, 1, 279, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DIV_RESET" , 27, 1, 279, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 279, "RAZ", 0, 1, 0ull, 0},
|
|
{"FBSLIP" , 0, 1, 280, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RFSLIP" , 1, 1, 280, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 280, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL" , 0, 5, 281, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 281, "RAZ", 0, 1, 0ull, 0},
|
|
{"NCTL" , 8, 4, 281, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_12_15" , 12, 4, 281, "RAZ", 0, 1, 0ull, 0},
|
|
{"ENABLE" , 16, 1, 281, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_17_63" , 17, 47, 281, "RAZ", 0, 1, 0ull, 0},
|
|
{"RODT_LO0" , 0, 4, 282, "R/W", 0, 0, 15ull, 0ull},
|
|
{"RODT_LO1" , 4, 4, 282, "R/W", 0, 0, 15ull, 0ull},
|
|
{"RODT_LO2" , 8, 4, 282, "R/W", 0, 0, 15ull, 0ull},
|
|
{"RODT_LO3" , 12, 4, 282, "R/W", 0, 0, 15ull, 0ull},
|
|
{"RODT_HI0" , 16, 4, 282, "R/W", 0, 0, 15ull, 0ull},
|
|
{"RODT_HI1" , 20, 4, 282, "R/W", 0, 0, 15ull, 0ull},
|
|
{"RODT_HI2" , 24, 4, 282, "R/W", 0, 0, 15ull, 0ull},
|
|
{"RODT_HI3" , 28, 4, 282, "R/W", 0, 0, 15ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 282, "RAZ", 1, 1, 0, 0},
|
|
{"WODT_LO0" , 0, 4, 283, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_LO1" , 4, 4, 283, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_LO2" , 8, 4, 283, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_LO3" , 12, 4, 283, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_HI0" , 16, 4, 283, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_HI1" , 20, 4, 283, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_HI2" , 24, 4, 283, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_HI3" , 28, 4, 283, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_32_63" , 32, 32, 283, "RAZ", 1, 1, 0, 0},
|
|
{"NCBI" , 0, 1, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"LOC" , 1, 1, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"NCBO_0" , 2, 1, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 284, "RAZ", 1, 1, 0, 0},
|
|
{"ADR_ERR" , 0, 1, 285, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WAIT_ERR" , 1, 1, 285, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 285, "RAZ", 1, 1, 0, 0},
|
|
{"ADR_INT" , 0, 1, 286, "R/W", 0, 1, 0ull, 0},
|
|
{"WAIT_INT" , 1, 1, 286, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 286, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 287, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 3, 5, 287, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 287, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 288, "RAZ", 1, 1, 0, 0},
|
|
{"BASE" , 3, 25, 288, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_30" , 28, 3, 288, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 31, 1, 288, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 288, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 289, "R/W", 1, 1, 0, 0},
|
|
{"BASE" , 0, 16, 290, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 16, 12, 290, "R/W", 0, 1, 0ull, 0},
|
|
{"WIDTH" , 28, 1, 290, "R/W", 0, 1, 0ull, 0},
|
|
{"ALE" , 29, 1, 290, "R/W", 0, 1, 0ull, 0},
|
|
{"ORBIT" , 30, 1, 290, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 31, 1, 290, "R/W", 0, 1, 0ull, 0},
|
|
{"OE_EXT" , 32, 2, 290, "R/W", 0, 1, 0ull, 0},
|
|
{"WE_EXT" , 34, 2, 290, "R/W", 0, 1, 0ull, 0},
|
|
{"SAM" , 36, 1, 290, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_37_63" , 37, 27, 290, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 6, 291, "R/W", 0, 1, 63ull, 0},
|
|
{"CE" , 6, 6, 291, "R/W", 0, 1, 63ull, 0},
|
|
{"OE" , 12, 6, 291, "R/W", 0, 1, 63ull, 0},
|
|
{"WE" , 18, 6, 291, "R/W", 0, 1, 63ull, 0},
|
|
{"RD_HLD" , 24, 6, 291, "R/W", 0, 1, 63ull, 0},
|
|
{"WR_HLD" , 30, 6, 291, "R/W", 0, 1, 63ull, 0},
|
|
{"PAUSE" , 36, 6, 291, "R/W", 0, 1, 63ull, 0},
|
|
{"WAIT" , 42, 6, 291, "R/W", 0, 1, 63ull, 0},
|
|
{"PAGE" , 48, 6, 291, "R/W", 0, 1, 63ull, 0},
|
|
{"ALE" , 54, 6, 291, "R/W", 0, 1, 63ull, 0},
|
|
{"PAGES" , 60, 2, 291, "R/W", 0, 1, 0ull, 0},
|
|
{"WAITM" , 62, 1, 291, "R/W", 0, 1, 0ull, 0},
|
|
{"PAGEM" , 63, 1, 291, "R/W", 0, 1, 0ull, 0},
|
|
{"FIF_THR" , 0, 6, 292, "R/W", 0, 0, 26ull, 26ull},
|
|
{"RESERVED_6_7" , 6, 2, 292, "RAZ", 1, 1, 0, 0},
|
|
{"FIF_CNT" , 8, 6, 292, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_63" , 14, 50, 292, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 64, 293, "R/W", 1, 1, 0, 0},
|
|
{"MAN_INFO" , 0, 32, 294, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 294, "RAZ", 1, 1, 0, 0},
|
|
{"MAN_INFO" , 0, 32, 295, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 295, "RAZ", 1, 1, 0, 0},
|
|
{"PP_DIS" , 0, 16, 296, "RO", 1, 1, 0, 0},
|
|
{"CHIP_ID" , 16, 8, 296, "RO", 1, 1, 0, 0},
|
|
{"BIST_DIS" , 24, 1, 296, "RO", 1, 1, 0, 0},
|
|
{"RST_SHT" , 25, 1, 296, "RO", 1, 1, 0, 0},
|
|
{"NOCRYPTO" , 26, 1, 296, "RO", 1, 1, 0, 0},
|
|
{"NOMUL" , 27, 1, 296, "RO", 1, 1, 0, 0},
|
|
{"NODFA_CP2" , 28, 1, 296, "RO", 1, 1, 0, 0},
|
|
{"NOKASU" , 29, 1, 296, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_30_63" , 30, 34, 296, "RAZ", 1, 1, 0, 0},
|
|
{"ICACHE" , 0, 24, 297, "RO", 1, 1, 0, 0},
|
|
{"NODFA_DTE" , 24, 1, 297, "RO", 1, 1, 0, 0},
|
|
{"NOZIP" , 25, 1, 297, "RO", 1, 1, 0, 0},
|
|
{"EFUS_IGN" , 26, 1, 297, "RO", 1, 1, 0, 0},
|
|
{"EFUS_LCK" , 27, 1, 297, "RO", 1, 1, 0, 0},
|
|
{"BAR2_EN" , 28, 1, 297, "RO", 1, 1, 0, 0},
|
|
{"ZIP_CRIP" , 29, 2, 297, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_31_63" , 31, 33, 297, "RAZ", 1, 1, 0, 0},
|
|
{"EMA" , 0, 2, 298, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 298, "RAZ", 1, 1, 0, 0},
|
|
{"FBSLIP" , 0, 1, 299, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RFSLIP" , 1, 1, 299, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 299, "RAZ", 1, 1, 0, 0},
|
|
{"PROG" , 0, 1, 300, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_1_63" , 1, 63, 300, "RAZ", 1, 1, 0, 0},
|
|
{"SETUP" , 0, 8, 301, "R/W", 0, 1, 3ull, 0},
|
|
{"SCLK_HI" , 8, 12, 301, "R/W", 0, 1, 100ull, 0},
|
|
{"SCLK_LO" , 20, 4, 301, "R/W", 0, 1, 2ull, 0},
|
|
{"OUT" , 24, 8, 301, "R/W", 0, 1, 3ull, 0},
|
|
{"PROG_PIN" , 32, 1, 301, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_33_63" , 33, 31, 301, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 7, 302, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 302, "RAZ", 1, 1, 0, 0},
|
|
{"EFUSE" , 8, 1, 302, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 302, "RAZ", 1, 1, 0, 0},
|
|
{"PEND" , 12, 1, 302, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 302, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 16, 8, 302, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_24_63" , 24, 40, 302, "RAZ", 1, 1, 0, 0},
|
|
{"REPAIR0" , 0, 14, 303, "RO", 0, 0, 0ull, 0ull},
|
|
{"REPAIR1" , 14, 14, 303, "RO", 0, 0, 0ull, 0ull},
|
|
{"REPAIR2" , 28, 14, 303, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_42_63" , 42, 22, 303, "RAZ", 1, 1, 0, 0},
|
|
{"TOO_MANY" , 0, 1, 304, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 304, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 2, 305, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_2_63" , 2, 62, 305, "RAZ", 1, 1, 0, 0},
|
|
{"ST_INT" , 0, 1, 306, "R/W1C", 0, 1, 0ull, 0},
|
|
{"TS_INT" , 1, 1, 306, "R/W1C", 0, 1, 0ull, 0},
|
|
{"CORE_INT" , 2, 1, 306, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_3" , 3, 1, 306, "RAZ", 1, 1, 0, 0},
|
|
{"ST_EN" , 4, 1, 306, "R/W", 0, 1, 0ull, 0},
|
|
{"TS_EN" , 5, 1, 306, "R/W", 0, 1, 0ull, 0},
|
|
{"CORE_EN" , 6, 1, 306, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_7" , 7, 1, 306, "RAZ", 1, 1, 0, 0},
|
|
{"SDA_OVR" , 8, 1, 306, "R/W", 0, 1, 0ull, 0},
|
|
{"SCL_OVR" , 9, 1, 306, "R/W", 0, 1, 0ull, 0},
|
|
{"SDA" , 10, 1, 306, "RO", 1, 1, 0, 0},
|
|
{"SCL" , 11, 1, 306, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_12_63" , 12, 52, 306, "RAZ", 1, 1, 0, 0},
|
|
{"D" , 0, 32, 307, "R/W", 0, 1, 0ull, 0},
|
|
{"EOP_IA" , 32, 3, 307, "R/W", 0, 1, 0ull, 0},
|
|
{"IA" , 35, 5, 307, "R/W", 0, 1, 0ull, 0},
|
|
{"A" , 40, 10, 307, "R/W", 0, 1, 0ull, 0},
|
|
{"SCR" , 50, 2, 307, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 52, 3, 307, "R/W", 0, 1, 0ull, 0},
|
|
{"SOVR" , 55, 1, 307, "R/W", 0, 1, 0ull, 0},
|
|
{"R" , 56, 1, 307, "R/W", 0, 1, 0ull, 0},
|
|
{"OP" , 57, 4, 307, "R/W", 0, 1, 0ull, 0},
|
|
{"EIA" , 61, 1, 307, "R/W", 0, 1, 0ull, 0},
|
|
{"SLONLY" , 62, 1, 307, "R/W", 0, 1, 0ull, 0},
|
|
{"V" , 63, 1, 307, "RC/W", 0, 1, 0ull, 0},
|
|
{"D" , 0, 32, 308, "R/W", 0, 1, 0ull, 0},
|
|
{"IA" , 32, 8, 308, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_40_63" , 40, 24, 308, "RAZ", 1, 1, 0, 0},
|
|
{"D" , 0, 32, 309, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_32_61" , 32, 30, 309, "RAZ", 1, 1, 0, 0},
|
|
{"V" , 62, 2, 309, "RC/W", 0, 1, 0ull, 0},
|
|
{"DLH" , 0, 8, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 310, "RAZ", 1, 1, 0, 0},
|
|
{"DLL" , 0, 8, 311, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 311, "RAZ", 1, 1, 0, 0},
|
|
{"FAR" , 0, 1, 312, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 312, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 313, "WO", 0, 1, 0ull, 0},
|
|
{"RXFR" , 1, 1, 313, "WO", 0, 1, 0ull, 0},
|
|
{"TXFR" , 2, 1, 313, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_3" , 3, 1, 313, "RAZ", 0, 1, 0ull, 0},
|
|
{"TXTRIG" , 4, 2, 313, "WO", 0, 1, 0ull, 0},
|
|
{"RXTRIG" , 6, 2, 313, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 313, "RAZ", 1, 1, 0, 0},
|
|
{"HTX" , 0, 1, 314, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 314, "RAZ", 1, 1, 0, 0},
|
|
{"ERBFI" , 0, 1, 315, "R/W", 0, 1, 0ull, 0},
|
|
{"ETBEI" , 1, 1, 315, "R/W", 0, 1, 0ull, 0},
|
|
{"ELSI" , 2, 1, 315, "R/W", 0, 1, 0ull, 0},
|
|
{"EDSSI" , 3, 1, 315, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_6" , 4, 3, 315, "RAZ", 0, 1, 0ull, 0},
|
|
{"PTIME" , 7, 1, 315, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 315, "RAZ", 1, 1, 0, 0},
|
|
{"IID" , 0, 4, 316, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_4_5" , 4, 2, 316, "RAZ", 0, 1, 0ull, 0},
|
|
{"FEN" , 6, 2, 316, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 316, "RAZ", 1, 1, 0, 0},
|
|
{"CLS" , 0, 2, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"STOP" , 2, 1, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"PEN" , 3, 1, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"EPS" , 4, 1, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_5" , 5, 1, 317, "RAZ", 0, 1, 0ull, 0},
|
|
{"BRK" , 6, 1, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"DLAB" , 7, 1, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 317, "RAZ", 1, 1, 0, 0},
|
|
{"DR" , 0, 1, 318, "RO", 0, 1, 0ull, 0},
|
|
{"OE" , 1, 1, 318, "RC", 0, 1, 0ull, 0},
|
|
{"PE" , 2, 1, 318, "RC", 0, 1, 0ull, 0},
|
|
{"FE" , 3, 1, 318, "RC", 0, 1, 0ull, 0},
|
|
{"BI" , 4, 1, 318, "RC", 0, 1, 0ull, 0},
|
|
{"THRE" , 5, 1, 318, "RO", 0, 1, 1ull, 0},
|
|
{"TEMT" , 6, 1, 318, "RO", 0, 1, 1ull, 0},
|
|
{"FERR" , 7, 1, 318, "RC", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 318, "RAZ", 1, 1, 0, 0},
|
|
{"DTR" , 0, 1, 319, "R/W", 0, 1, 0ull, 0},
|
|
{"RTS" , 1, 1, 319, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT1" , 2, 1, 319, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT2" , 3, 1, 319, "R/W", 0, 1, 0ull, 0},
|
|
{"LOOP" , 4, 1, 319, "R/W", 0, 1, 0ull, 0},
|
|
{"AFCE" , 5, 1, 319, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 319, "RAZ", 0, 1, 0ull, 0},
|
|
{"DCTS" , 0, 1, 320, "RC", 0, 1, 0ull, 0},
|
|
{"DDSR" , 1, 1, 320, "RC", 0, 1, 0ull, 0},
|
|
{"TERI" , 2, 1, 320, "RC", 0, 1, 0ull, 0},
|
|
{"DDCD" , 3, 1, 320, "RC", 0, 1, 0ull, 0},
|
|
{"CTS" , 4, 1, 320, "RO", 1, 1, 0, 0},
|
|
{"DSR" , 5, 1, 320, "RO", 0, 1, 0ull, 0},
|
|
{"RI" , 6, 1, 320, "RO", 0, 1, 0ull, 0},
|
|
{"DCD" , 7, 1, 320, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 320, "RAZ", 1, 1, 0, 0},
|
|
{"RBR" , 0, 8, 321, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 321, "RAZ", 1, 1, 0, 0},
|
|
{"RFL" , 0, 7, 322, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 322, "RAZ", 1, 1, 0, 0},
|
|
{"RFWD" , 0, 8, 323, "WO", 0, 1, 0ull, 0},
|
|
{"RFPE" , 8, 1, 323, "WO", 0, 1, 0ull, 0},
|
|
{"RFFE" , 9, 1, 323, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_10_63" , 10, 54, 323, "RAZ", 1, 1, 0, 0},
|
|
{"SBCR" , 0, 1, 324, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 324, "RAZ", 1, 1, 0, 0},
|
|
{"SCR" , 0, 8, 325, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 325, "RAZ", 1, 1, 0, 0},
|
|
{"SFE" , 0, 1, 326, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 326, "RAZ", 1, 1, 0, 0},
|
|
{"USR" , 0, 1, 327, "WO", 0, 1, 0ull, 0},
|
|
{"SRFR" , 1, 1, 327, "WO", 0, 1, 0ull, 0},
|
|
{"STFR" , 2, 1, 327, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_63" , 3, 61, 327, "RAZ", 1, 1, 0, 0},
|
|
{"SRT" , 0, 2, 328, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 328, "RAZ", 1, 1, 0, 0},
|
|
{"SRTS" , 0, 1, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 329, "RAZ", 1, 1, 0, 0},
|
|
{"STT" , 0, 2, 330, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 330, "RAZ", 1, 1, 0, 0},
|
|
{"TFL" , 0, 7, 331, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 331, "RAZ", 1, 1, 0, 0},
|
|
{"TFR" , 0, 8, 332, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 332, "RAZ", 1, 1, 0, 0},
|
|
{"THR" , 0, 8, 333, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 333, "RAZ", 1, 1, 0, 0},
|
|
{"BUSY" , 0, 1, 334, "RO", 0, 1, 0ull, 0},
|
|
{"TFNF" , 1, 1, 334, "RO", 0, 1, 1ull, 0},
|
|
{"TFE" , 2, 1, 334, "RO", 0, 1, 1ull, 0},
|
|
{"RFNE" , 3, 1, 334, "RO", 0, 1, 0ull, 0},
|
|
{"RFF" , 4, 1, 334, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 334, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 335, "RAZ", 1, 1, 0, 0},
|
|
{"BADDR" , 3, 61, 335, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_0_2" , 0, 3, 336, "RAZ", 1, 1, 0, 0},
|
|
{"BADDR" , 3, 61, 336, "R/W", 0, 1, 0ull, 0},
|
|
{"DPI_BS" , 0, 1, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"PDF_BS" , 1, 1, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"DOB_BS" , 2, 1, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"NUS_BS" , 3, 1, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"POS_BS" , 4, 1, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"POF3_BS" , 5, 1, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"POF2_BS" , 6, 1, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"POF1_BS" , 7, 1, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"POF0_BS" , 8, 1, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"PIG_BS" , 9, 1, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"PGF_BS" , 10, 1, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"RDNL_BS" , 11, 1, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCAD_BS" , 12, 1, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCAC_BS" , 13, 1, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"RDN_BS" , 14, 1, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCN_BS" , 15, 1, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCNC_BS" , 16, 1, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"RDP_BS" , 17, 1, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF_BS" , 18, 1, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSR_BS" , 19, 1, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 337, "RAZ", 1, 1, 0, 0},
|
|
{"BSIZE" , 0, 16, 338, "R/W", 0, 1, 1024ull, 0},
|
|
{"ISIZE" , 16, 7, 338, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_23_63" , 23, 41, 338, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 5, 339, "R/W", 0, 1, 16ull, 0},
|
|
{"PCTL" , 5, 5, 339, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_10_63" , 10, 54, 339, "RAZ", 1, 1, 0, 0},
|
|
{"TIMER" , 0, 10, 340, "R/W", 0, 0, 0ull, 50ull},
|
|
{"RESERVED_10_31" , 10, 22, 340, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX_WORD" , 32, 5, 340, "R/W", 0, 0, 2ull, 0ull},
|
|
{"RESERVED_37_39" , 37, 3, 340, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WAIT_COM" , 40, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCI_WDIS" , 41, 1, 340, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INS0_64B" , 42, 1, 340, "R/W", 0, 1, 0ull, 0},
|
|
{"INS1_64B" , 43, 1, 340, "R/W", 0, 1, 0ull, 0},
|
|
{"INS2_64B" , 44, 1, 340, "R/W", 0, 1, 0ull, 0},
|
|
{"INS3_64B" , 45, 1, 340, "R/W", 0, 1, 0ull, 0},
|
|
{"INS0_ENB" , 46, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INS1_ENB" , 47, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INS2_ENB" , 48, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INS3_ENB" , 49, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OUT0_ENB" , 50, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OUT1_ENB" , 51, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OUT2_ENB" , 52, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OUT3_ENB" , 53, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DIS_PNIW" , 54, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CHIP_REV" , 55, 8, 340, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_63_63" , 63, 1, 340, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_SEL" , 0, 16, 341, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 341, "RAZ", 1, 1, 0, 0},
|
|
{"CSIZE" , 0, 14, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"LP_ENB" , 14, 1, 342, "R/W", 0, 0, 0ull, 1ull},
|
|
{"HP_ENB" , 15, 1, 342, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O_MODE" , 16, 1, 342, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O_ES" , 17, 2, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"O_NS" , 19, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"O_RO" , 20, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"O_ADD1" , 21, 1, 342, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA_QUE" , 22, 3, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB_ICHK" , 25, 9, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB_DENB" , 34, 1, 342, "R/W", 0, 0, 0ull, 1ull},
|
|
{"B0_LEND" , 35, 1, 342, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 342, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 32, 343, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 7, 343, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_39_63" , 39, 25, 343, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 344, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 36, 4, 344, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 344, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 32, 345, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 7, 345, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_39_63" , 39, 25, 345, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 346, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 36, 4, 346, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 346, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 16, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 347, "RAZ", 1, 1, 0, 0},
|
|
{"SADDR" , 0, 36, 348, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 348, "RAZ", 1, 1, 0, 0},
|
|
{"ROR" , 0, 1, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR" , 1, 2, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR" , 3, 1, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_CSR" , 4, 1, 349, "R/W", 0, 0, 0ull, 1ull},
|
|
{"D_ROR" , 5, 1, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"D_ESR" , 6, 2, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"D_NSR" , 8, 1, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP_DHI" , 9, 13, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_RR" , 22, 1, 349, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 349, "RAZ", 1, 1, 0, 0},
|
|
{"RML_RTO" , 0, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RML_WTO" , 1, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCI_RSL" , 2, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PO0_2SML" , 3, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PO1_2SML" , 4, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PO2_2SML" , 5, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PO3_2SML" , 6, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I0_RTOUT" , 7, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I1_RTOUT" , 8, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I2_RTOUT" , 9, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I3_RTOUT" , 10, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I0_OVERF" , 11, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I1_OVERF" , 12, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I2_OVERF" , 13, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I3_OVERF" , 14, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P0_RTOUT" , 15, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_RTOUT" , 16, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P2_RTOUT" , 17, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P3_RTOUT" , 18, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P0_PERR" , 19, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_PERR" , 20, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P2_PERR" , 21, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P3_PERR" , 22, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"G0_RTOUT" , 23, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"G1_RTOUT" , 24, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"G2_RTOUT" , 25, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"G3_RTOUT" , 26, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P0_PPERR" , 27, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_PPERR" , 28, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P2_PPERR" , 29, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P3_PPERR" , 30, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P0_PTOUT" , 31, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_PTOUT" , 32, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P2_PTOUT" , 33, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P3_PTOUT" , 34, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I0_PPERR" , 35, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I1_PPERR" , 36, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I2_PPERR" , 37, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I3_PPERR" , 38, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"WIN_RTO" , 39, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P_DPERR" , 40, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 41, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FCR_S_E" , 42, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FCR_A_F" , 43, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCR_S_E" , 44, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCR_A_F" , 45, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q2_S_E" , 46, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q2_A_F" , 47, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q3_S_E" , 48, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q3_A_F" , 49, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"COM_S_E" , 50, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"COM_A_F" , 51, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PNC_S_E" , 52, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PNC_A_F" , 53, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RWX_S_E" , 54, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RDX_S_E" , 55, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCF_P_E" , 56, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCF_P_F" , 57, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PDF_P_E" , 58, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PDF_P_F" , 59, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q1_S_E" , 60, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q1_A_F" , 61, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_62_63" , 62, 2, 350, "RAZ", 1, 1, 0, 0},
|
|
{"RML_RTO" , 0, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RML_WTO" , 1, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCI_RSL" , 2, 1, 351, "RO", 0, 0, 0ull, 0ull},
|
|
{"PO0_2SML" , 3, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PO1_2SML" , 4, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PO2_2SML" , 5, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PO3_2SML" , 6, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I0_RTOUT" , 7, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I1_RTOUT" , 8, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I2_RTOUT" , 9, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I3_RTOUT" , 10, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I0_OVERF" , 11, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I1_OVERF" , 12, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I2_OVERF" , 13, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I3_OVERF" , 14, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P0_RTOUT" , 15, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_RTOUT" , 16, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P2_RTOUT" , 17, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P3_RTOUT" , 18, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P0_PERR" , 19, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_PERR" , 20, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P2_PERR" , 21, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P3_PERR" , 22, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"G0_RTOUT" , 23, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"G1_RTOUT" , 24, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"G2_RTOUT" , 25, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"G3_RTOUT" , 26, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P0_PPERR" , 27, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_PPERR" , 28, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P2_PPERR" , 29, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P3_PPERR" , 30, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P0_PTOUT" , 31, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_PTOUT" , 32, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P2_PTOUT" , 33, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P3_PTOUT" , 34, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I0_PPERR" , 35, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I1_PPERR" , 36, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I2_PPERR" , 37, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I3_PPERR" , 38, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WIN_RTO" , 39, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_DPERR" , 40, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IOBDMA" , 41, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCR_S_E" , 42, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCR_A_F" , 43, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCR_S_E" , 44, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCR_A_F" , 45, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_S_E" , 46, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_A_F" , 47, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_S_E" , 48, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_A_F" , 49, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COM_S_E" , 50, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COM_A_F" , 51, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PNC_S_E" , 52, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PNC_A_F" , 53, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RWX_S_E" , 54, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RDX_S_E" , 55, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCF_P_E" , 56, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCF_P_F" , 57, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PDF_P_E" , 58, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PDF_P_F" , 59, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_S_E" , 60, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_A_F" , 61, 1, 351, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_62_63" , 62, 2, 351, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 16, 352, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 352, "RAZ", 1, 1, 0, 0},
|
|
{"SADDR" , 0, 36, 353, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 353, "RAZ", 1, 1, 0, 0},
|
|
{"BA" , 0, 28, 354, "R/W", 0, 1, 0ull, 0},
|
|
{"ROW" , 28, 1, 354, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR" , 29, 1, 354, "R/W", 0, 1, 0ull, 0},
|
|
{"NSW" , 30, 1, 354, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR" , 31, 1, 354, "R/W", 0, 1, 0ull, 0},
|
|
{"ESW" , 32, 2, 354, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR" , 34, 2, 354, "R/W", 0, 1, 0ull, 0},
|
|
{"NMERGE" , 36, 1, 354, "R/W", 0, 1, 0ull, 0},
|
|
{"SHORTL" , 37, 1, 354, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_38_63" , 38, 26, 354, "RAZ", 1, 1, 0, 0},
|
|
{"INT_VEC" , 0, 64, 355, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 0, 32, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 356, "RAZ", 1, 1, 0, 0},
|
|
{"ROR_SL0" , 0, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR_SL0" , 1, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR_SL0" , 2, 2, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR_SL1" , 4, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR_SL1" , 5, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR_SL1" , 6, 2, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR_SL2" , 8, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR_SL2" , 9, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR_SL2" , 10, 2, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR_SL3" , 12, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR_SL3" , 13, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR_SL3" , 14, 2, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"IPTR_O0" , 16, 1, 357, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IPTR_O1" , 17, 1, 357, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IPTR_O2" , 18, 1, 357, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IPTR_O3" , 19, 1, 357, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_20_23" , 20, 4, 357, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"O0_CSRM" , 24, 1, 357, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O1_CSRM" , 25, 1, 357, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O2_CSRM" , 26, 1, 357, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O3_CSRM" , 27, 1, 357, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O0_RO" , 28, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"O0_NS" , 29, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"O0_ES" , 30, 2, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"O1_RO" , 32, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"O1_NS" , 33, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"O1_ES" , 34, 2, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"O2_RO" , 36, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"O2_NS" , 37, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"O2_ES" , 38, 2, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"O3_RO" , 40, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"O3_NS" , 41, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"O3_ES" , 42, 2, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"P0_BMODE" , 44, 1, 357, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P1_BMODE" , 45, 1, 357, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P2_BMODE" , 46, 1, 357, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P3_BMODE" , 47, 1, 357, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKT_RR" , 48, 1, 357, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 357, "RAZ", 1, 1, 0, 0},
|
|
{"NADDR" , 0, 61, 358, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 61, 2, 358, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_63_63" , 63, 1, 358, "RAZ", 1, 1, 0, 0},
|
|
{"NADDR" , 0, 61, 359, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 61, 3, 359, "RO", 0, 0, 0ull, 0ull},
|
|
{"AVAIL" , 0, 32, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 6, 360, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 360, "RAZ", 1, 1, 0, 0},
|
|
{"AVAIL" , 0, 32, 361, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 5, 361, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 361, "RAZ", 1, 1, 0, 0},
|
|
{"RD_BRST" , 0, 7, 362, "R/W", 0, 0, 17ull, 64ull},
|
|
{"WR_BRST" , 7, 7, 362, "R/W", 0, 0, 16ull, 64ull},
|
|
{"RESERVED_14_63" , 14, 50, 362, "RAZ", 1, 1, 0, 0},
|
|
{"PARK_DEV" , 0, 3, 363, "R/W", 0, 1, 0ull, 0},
|
|
{"PARK_MOD" , 3, 1, 363, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 4, 1, 363, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 363, "RAZ", 1, 1, 0, 0},
|
|
{"PCI_OVR" , 8, 4, 363, "R/W", 0, 1, 0ull, 0},
|
|
{"HOSTMODE" , 12, 1, 363, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_13_63" , 13, 51, 363, "RAZ", 1, 1, 0, 0},
|
|
{"CMD_SIZE" , 0, 11, 364, "R/W", 0, 0, 9ull, 9ull},
|
|
{"RESERVED_11_63" , 11, 53, 364, "RAZ", 1, 1, 0, 0},
|
|
{"RSV_A" , 0, 6, 365, "R/W", 0, 1, 0ull, 0},
|
|
{"SKP_LEN" , 6, 7, 365, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_B" , 13, 1, 365, "R/W", 0, 1, 0ull, 0},
|
|
{"PAR_MODE" , 14, 2, 365, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_C" , 16, 5, 365, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_IHDR" , 21, 1, 365, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_D" , 22, 6, 365, "R/W", 0, 1, 0ull, 0},
|
|
{"RSKP_LEN" , 28, 7, 365, "R/W", 0, 1, 8ull, 0},
|
|
{"RSV_E" , 35, 1, 365, "R/W", 0, 1, 0ull, 0},
|
|
{"RPARMODE" , 36, 2, 365, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_F" , 38, 5, 365, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP" , 43, 1, 365, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 365, "RAZ", 1, 1, 0, 0},
|
|
{"RSV_A" , 0, 6, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"SKP_LEN" , 6, 7, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_B" , 13, 1, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"PAR_MODE" , 14, 2, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_C" , 16, 5, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_IHDR" , 21, 1, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_D" , 22, 6, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"RSKP_LEN" , 28, 7, 366, "R/W", 0, 1, 8ull, 0},
|
|
{"RSV_E" , 35, 1, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"RPARMODE" , 36, 2, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_F" , 38, 5, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP" , 43, 1, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 366, "RAZ", 1, 1, 0, 0},
|
|
{"RSV_A" , 0, 6, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"SKP_LEN" , 6, 7, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_B" , 13, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"PAR_MODE" , 14, 2, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_C" , 16, 5, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_IHDR" , 21, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_D" , 22, 6, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"RSKP_LEN" , 28, 7, 367, "R/W", 0, 1, 8ull, 0},
|
|
{"RSV_E" , 35, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"RPARMODE" , 36, 2, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_F" , 38, 5, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP" , 43, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 367, "RAZ", 1, 1, 0, 0},
|
|
{"RSV_A" , 0, 6, 368, "R/W", 0, 1, 0ull, 0},
|
|
{"SKP_LEN" , 6, 7, 368, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_B" , 13, 1, 368, "R/W", 0, 1, 0ull, 0},
|
|
{"PAR_MODE" , 14, 2, 368, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_C" , 16, 5, 368, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_IHDR" , 21, 1, 368, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_D" , 22, 6, 368, "R/W", 0, 1, 0ull, 0},
|
|
{"RSKP_LEN" , 28, 7, 368, "R/W", 0, 1, 8ull, 0},
|
|
{"RSV_E" , 35, 1, 368, "R/W", 0, 1, 0ull, 0},
|
|
{"RPARMODE" , 36, 2, 368, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_F" , 38, 5, 368, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP" , 43, 1, 368, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 368, "RAZ", 1, 1, 0, 0},
|
|
{"ENB" , 0, 4, 369, "R/W", 0, 0, 15ull, 15ull},
|
|
{"BP_ON" , 4, 4, 369, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 369, "RAZ", 1, 1, 0, 0},
|
|
{"MIO" , 0, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX0" , 1, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX1" , 2, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPI" , 3, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"KEY" , 4, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPA" , 5, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"DFA" , 6, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"ZIP" , 7, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_8" , 8, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD" , 9, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 10, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"TIM" , 11, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"POW" , 12, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_13" , 13, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_14" , 14, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_15" , 15, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"L2C" , 16, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"LMC" , 17, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"SPX0" , 18, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"SPX1" , 19, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"PIP" , 20, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_21" , 21, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASX0" , 22, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASX1" , 23, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_24" , 24, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_25" , 25, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_26" , 26, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_27" , 27, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_28" , 28, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_29" , 29, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"IOB" , 30, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_31" , 31, 1, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 370, "RAZ", 1, 1, 0, 0},
|
|
{"SIZE" , 0, 32, 371, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 371, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 32, 372, "R/W", 0, 0, 0ull, 131072ull},
|
|
{"RESERVED_32_63" , 32, 32, 372, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR_V" , 0, 1, 373, "R/W", 0, 1, 0ull, 0},
|
|
{"END_SWP" , 1, 2, 373, "R/W", 0, 1, 0ull, 0},
|
|
{"CA" , 3, 1, 373, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDR_IDX" , 4, 14, 373, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_31" , 18, 14, 373, "RAZ", 1, 1, 0, 0},
|
|
{"VENDID" , 0, 16, 374, "RO", 0, 0, 6013ull, 6013ull},
|
|
{"DEVID" , 16, 16, 374, "RO", 0, 0, 64ull, 64ull},
|
|
{"ISAE" , 0, 1, 375, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSAE" , 1, 1, 375, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ME" , 2, 1, 375, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SCSE" , 3, 1, 375, "RO", 0, 0, 0ull, 0ull},
|
|
{"MWICE" , 4, 1, 375, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VPS" , 5, 1, 375, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEE" , 6, 1, 375, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ADS" , 7, 1, 375, "RO", 0, 0, 0ull, 0ull},
|
|
{"SEE" , 8, 1, 375, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FBBE" , 9, 1, 375, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I_DIS" , 10, 1, 375, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_18" , 11, 8, 375, "RAZ", 1, 1, 0, 0},
|
|
{"I_STAT" , 19, 1, 375, "RO", 0, 0, 0ull, 0ull},
|
|
{"CLE" , 20, 1, 375, "RO", 0, 0, 1ull, 1ull},
|
|
{"M66" , 21, 1, 375, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_22_22" , 22, 1, 375, "RAZ", 1, 1, 0, 0},
|
|
{"FBB" , 23, 1, 375, "RO", 0, 1, 1ull, 0},
|
|
{"MDPE" , 24, 1, 375, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DEVT" , 25, 2, 375, "RO", 0, 0, 1ull, 1ull},
|
|
{"STA" , 27, 1, 375, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTA" , 28, 1, 375, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RMA" , 29, 1, 375, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SSE" , 30, 1, 375, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPE" , 31, 1, 375, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RID" , 0, 8, 376, "RO", 0, 0, 0ull, 0ull},
|
|
{"CC" , 8, 24, 376, "RO", 0, 0, 733184ull, 733184ull},
|
|
{"CLS" , 0, 8, 377, "R/W", 0, 1, 0ull, 0},
|
|
{"LT" , 8, 8, 377, "R/W", 0, 0, 0ull, 64ull},
|
|
{"HT" , 16, 8, 377, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCOD" , 24, 4, 377, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_29" , 28, 2, 377, "RAZ", 1, 1, 0, 0},
|
|
{"BRB" , 30, 1, 377, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BCAP" , 31, 1, 377, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSPC" , 0, 1, 378, "RO", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 378, "RO", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 378, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBASEZ" , 4, 8, 378, "RO", 0, 0, 0ull, 0ull},
|
|
{"LBASE" , 12, 20, 378, "R/W", 0, 1, 0ull, 0},
|
|
{"HBASE" , 0, 32, 379, "R/W", 0, 1, 0ull, 0},
|
|
{"MSPC" , 0, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 380, "RO", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 380, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBASEZ" , 4, 23, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"LBASE" , 27, 5, 380, "R/W", 0, 1, 0ull, 0},
|
|
{"HBASE" , 0, 32, 381, "R/W", 0, 1, 0ull, 0},
|
|
{"MSPC" , 0, 1, 382, "RO", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 382, "RO", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 382, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBASEZ" , 4, 28, 382, "RO", 0, 0, 0ull, 0ull},
|
|
{"HBASEZ" , 0, 7, 383, "RO", 0, 0, 0ull, 0ull},
|
|
{"HBASE" , 7, 25, 383, "R/W", 0, 1, 0ull, 0},
|
|
{"CISP" , 0, 32, 384, "RO", 0, 0, 0ull, 0ull},
|
|
{"SSVID" , 0, 16, 385, "RO", 0, 0, 6013ull, 6013ull},
|
|
{"SSID" , 16, 16, 385, "RO", 0, 0, 1ull, 1ull},
|
|
{"ERBAR_EN" , 0, 1, 386, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_10" , 1, 10, 386, "RAZ", 1, 1, 0, 0},
|
|
{"ERBARZ" , 11, 5, 386, "RO", 0, 0, 0ull, 0ull},
|
|
{"ERBAR" , 16, 16, 386, "R/W", 0, 1, 0ull, 0},
|
|
{"CP" , 0, 8, 387, "RO", 0, 0, 224ull, 224ull},
|
|
{"RESERVED_8_31" , 8, 24, 387, "RAZ", 1, 1, 0, 0},
|
|
{"IL" , 0, 8, 388, "R/W", 0, 1, 0ull, 0},
|
|
{"INTA" , 8, 8, 388, "RO", 0, 0, 1ull, 1ull},
|
|
{"MG" , 16, 8, 388, "RO", 0, 0, 64ull, 64ull},
|
|
{"ML" , 24, 8, 388, "RO", 0, 0, 64ull, 64ull},
|
|
{"MLTD" , 0, 1, 389, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TSWC" , 1, 1, 389, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 389, "RAZ", 1, 1, 0, 0},
|
|
{"DPPMR" , 3, 1, 389, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PBE" , 4, 12, 389, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TILT" , 16, 4, 389, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TSLTE" , 20, 3, 389, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TMAE" , 23, 1, 389, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWTAE" , 24, 1, 389, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWSEN" , 25, 1, 389, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWSEI" , 26, 1, 389, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRTAE" , 27, 1, 389, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRDRS" , 28, 1, 389, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RDSATI" , 29, 1, 389, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRDARD" , 30, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TRDNPR" , 31, 1, 389, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TSCME" , 0, 32, 390, "R/W1C", 0, 1, 0ull, 0},
|
|
{"TDSRPS" , 0, 32, 391, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TDOMC" , 0, 5, 392, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TIDOMC" , 5, 1, 392, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_6" , 6, 1, 392, "RAZ", 1, 1, 0, 0},
|
|
{"TIBDE" , 7, 1, 392, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIBCD" , 8, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_10" , 9, 2, 392, "RAZ", 1, 1, 0, 0},
|
|
{"TMAPES" , 11, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TMDPES" , 12, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TMSE" , 13, 1, 392, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TMEI" , 14, 1, 392, "RO", 0, 0, 0ull, 0ull},
|
|
{"TECI" , 15, 1, 392, "RO", 0, 0, 0ull, 0ull},
|
|
{"TMES" , 16, 8, 392, "RO", 0, 0, 0ull, 0ull},
|
|
{"MDRRMC" , 24, 3, 392, "R/W", 0, 0, 2ull, 2ull},
|
|
{"MDRIMC" , 27, 1, 392, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MDRE" , 28, 1, 392, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MDWE" , 29, 1, 392, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRBCI" , 30, 1, 392, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRBCM" , 31, 1, 392, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MDSP" , 0, 32, 393, "R/W1C", 0, 1, 0ull, 0},
|
|
{"SCMRE" , 0, 32, 394, "R/W1C", 0, 1, 0ull, 0},
|
|
{"MTTV" , 0, 8, 395, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRV" , 8, 8, 395, "R/W", 0, 0, 0ull, 255ull},
|
|
{"MTTA" , 16, 1, 395, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRA" , 17, 1, 395, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FLUSH" , 18, 1, 395, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_19_24" , 19, 6, 395, "RAZ", 1, 1, 0, 0},
|
|
{"MAC" , 25, 7, 395, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PXCID" , 0, 8, 396, "RO", 0, 0, 7ull, 7ull},
|
|
{"NCP" , 8, 8, 396, "RO", 0, 0, 232ull, 232ull},
|
|
{"DPERE" , 16, 1, 396, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROE" , 17, 1, 396, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MMBC" , 18, 2, 396, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MOST" , 20, 3, 396, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_23_31" , 23, 9, 396, "RAZ", 1, 1, 0, 0},
|
|
{"FN" , 0, 3, 397, "RO", 0, 0, 0ull, 0ull},
|
|
{"DN" , 3, 5, 397, "RO", 0, 0, 31ull, 31ull},
|
|
{"BN" , 8, 8, 397, "RO", 0, 1, 17ull, 0},
|
|
{"W64" , 16, 1, 397, "RO", 0, 0, 1ull, 1ull},
|
|
{"M133" , 17, 1, 397, "RO", 0, 0, 1ull, 1ull},
|
|
{"SCD" , 18, 1, 397, "R/W1C", 0, 1, 0ull, 0},
|
|
{"USC" , 19, 1, 397, "R/W1C", 0, 1, 0ull, 0},
|
|
{"DC" , 20, 1, 397, "RO", 0, 0, 0ull, 0ull},
|
|
{"MMRBCD" , 21, 2, 397, "RO", 0, 0, 2ull, 2ull},
|
|
{"MOSTD" , 23, 3, 397, "RO", 0, 0, 3ull, 3ull},
|
|
{"MCRSD" , 26, 3, 397, "RO", 0, 0, 7ull, 7ull},
|
|
{"SCEMR" , 29, 1, 397, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_30_31" , 30, 2, 397, "RAZ", 1, 1, 0, 0},
|
|
{"PMCID" , 0, 8, 398, "RO", 0, 0, 1ull, 1ull},
|
|
{"NCP" , 8, 8, 398, "RO", 0, 0, 240ull, 240ull},
|
|
{"PCIMIV" , 16, 3, 398, "RO", 0, 0, 2ull, 2ull},
|
|
{"PMEC" , 19, 1, 398, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 398, "RAZ", 1, 1, 0, 0},
|
|
{"DSI" , 21, 1, 398, "RO", 0, 0, 0ull, 0ull},
|
|
{"AUXC" , 22, 3, 398, "RO", 0, 0, 0ull, 0ull},
|
|
{"D1S" , 25, 1, 398, "RO", 0, 0, 0ull, 0ull},
|
|
{"D2S" , 26, 1, 398, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMES" , 27, 5, 398, "RO", 0, 0, 0ull, 0ull},
|
|
{"PS" , 0, 2, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_7" , 2, 6, 399, "RAZ", 1, 1, 0, 0},
|
|
{"PMEENS" , 8, 1, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMDS" , 9, 4, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMEDSIA" , 13, 2, 399, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMESS" , 15, 1, 399, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_21" , 16, 6, 399, "RAZ", 1, 1, 0, 0},
|
|
{"BD3H" , 22, 1, 399, "RO", 0, 0, 0ull, 0ull},
|
|
{"BPCCEN" , 23, 1, 399, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMDIA" , 24, 8, 399, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSICID" , 0, 8, 400, "RO", 0, 0, 5ull, 5ull},
|
|
{"NCP" , 8, 8, 400, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSIEN" , 16, 1, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MMC" , 17, 3, 400, "RO", 0, 0, 0ull, 0ull},
|
|
{"MME" , 20, 3, 400, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M64" , 23, 1, 400, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_24_31" , 24, 8, 400, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 401, "RAZ", 1, 1, 0, 0},
|
|
{"MSI31T2" , 2, 30, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"MSI" , 0, 32, 402, "R/W", 0, 1, 0ull, 0},
|
|
{"MSIMD" , 0, 16, 403, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_31" , 16, 16, 403, "RAZ", 1, 1, 0, 0},
|
|
{"PCICNT" , 0, 32, 404, "R/W", 0, 1, 0ull, 0},
|
|
{"AP_SPEED" , 32, 2, 404, "RO", 1, 1, 0, 0},
|
|
{"AP_PCIX" , 34, 1, 404, "RO", 1, 1, 0, 0},
|
|
{"HM_SPEED" , 35, 2, 404, "RO", 0, 1, 0ull, 0},
|
|
{"HM_PCIX" , 37, 1, 404, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_38_63" , 38, 26, 404, "RAZ", 1, 1, 0, 0},
|
|
{"BAR2_CAX" , 0, 1, 405, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAR2_ESX" , 1, 2, 405, "R/W", 0, 1, 0ull, 0},
|
|
{"BAR2_ENB" , 3, 1, 405, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TSR_HWM" , 4, 3, 405, "R/W", 0, 1, 1ull, 0},
|
|
{"PMO_FPC" , 7, 3, 405, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMO_AMOD" , 10, 1, 405, "R/W", 0, 0, 0ull, 0ull},
|
|
{"B12_BIST" , 11, 1, 405, "RO", 0, 0, 0ull, 0ull},
|
|
{"AP_64AD" , 12, 1, 405, "RO", 0, 1, 0ull, 0},
|
|
{"AP_PCIX" , 13, 1, 405, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_14" , 14, 1, 405, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EN_WFILT" , 15, 1, 405, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SCM" , 16, 1, 405, "RO", 0, 1, 0ull, 0},
|
|
{"SCMTYP" , 17, 1, 405, "RO", 0, 1, 0ull, 0},
|
|
{"BAR2PRES" , 18, 1, 405, "R/W", 1, 1, 0, 0},
|
|
{"ERST_N" , 19, 1, 405, "RO", 0, 0, 1ull, 1ull},
|
|
{"BB0" , 20, 1, 405, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB1" , 21, 1, 405, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB_ES" , 22, 2, 405, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB_CA" , 24, 1, 405, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB1_SIZ" , 25, 1, 405, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB1_HOLE" , 26, 3, 405, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_31" , 29, 3, 405, "RAZ", 1, 1, 0, 0},
|
|
{"INC_VAL" , 0, 16, 406, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_31" , 16, 16, 406, "RAZ", 1, 1, 0, 0},
|
|
{"DMA_CNT" , 0, 32, 407, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKT_CNT" , 0, 32, 408, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA_TIME" , 0, 32, 409, "R/W", 0, 1, 0ull, 0},
|
|
{"ICNT" , 0, 32, 410, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ITR_WABT" , 0, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_WABT" , 1, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_WTTO" , 2, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"ITR_ABT" , 3, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_ABT" , 4, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_TTO" , 5, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSI_PER" , 6, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSI_TABT" , 7, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSI_MABT" , 8, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSC_MSG" , 9, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"ITSR_ABT" , 10, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"ISERR" , 11, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"IAPERR" , 12, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"IDPERR" , 13, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RWR" , 14, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RRD" , 15, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"IRSL_INT" , 16, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"IPCNT0" , 17, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"IPCNT1" , 18, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"IPCNT2" , 19, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"IPCNT3" , 20, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"IPTIME0" , 21, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"IPTIME1" , 22, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"IPTIME2" , 23, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"IPTIME3" , 24, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"IDCNT0" , 25, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"IDCNT1" , 26, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"IDTIME0" , 27, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"IDTIME1" , 28, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA0_FI" , 29, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA1_FI" , 30, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"WIN_WR" , 31, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_WR" , 32, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RD" , 33, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_34_63" , 34, 30, 411, "RAZ", 1, 1, 0, 0},
|
|
{"RTR_WABT" , 0, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_WABT" , 1, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_WTTO" , 2, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RTR_ABT" , 3, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_ABT" , 4, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_TTO" , 5, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSI_PER" , 6, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSI_TABT" , 7, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSI_MABT" , 8, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSC_MSG" , 9, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RTSR_ABT" , 10, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RSERR" , 11, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RAPERR" , 12, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RDPERR" , 13, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RWR" , 14, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RRD" , 15, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RRSL_INT" , 16, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RPCNT0" , 17, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RPCNT1" , 18, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RPCNT2" , 19, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RPCNT3" , 20, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RPTIME0" , 21, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RPTIME1" , 22, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RPTIME2" , 23, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RPTIME3" , 24, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RDCNT0" , 25, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RDCNT1" , 26, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RDTIME0" , 27, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RDTIME1" , 28, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA0_FI" , 29, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA1_FI" , 30, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"WIN_WR" , 31, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_WR" , 32, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RD" , 33, 1, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_34_63" , 34, 30, 412, "RAZ", 1, 1, 0, 0},
|
|
{"TR_WABT" , 0, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WABT" , 1, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WTTO" , 2, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TR_ABT" , 3, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_ABT" , 4, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_TTO" , 5, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_PER" , 6, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_TABT" , 7, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_MABT" , 8, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSC_MSG" , 9, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TSR_ABT" , 10, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SERR" , 11, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"APERR" , 12, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPERR" , 13, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RWR" , 14, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RRD" , 15, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSL_INT" , 16, 1, 413, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCNT0" , 17, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT1" , 18, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT2" , 19, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT3" , 20, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME0" , 21, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME1" , 22, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME2" , 23, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME3" , 24, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT0" , 25, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT1" , 26, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME0" , 27, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME1" , 28, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA0_FI" , 29, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1_FI" , 30, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WIN_WR" , 31, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_WR" , 32, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RD" , 33, 1, 413, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 413, "RAZ", 1, 1, 0, 0},
|
|
{"TR_WABT" , 0, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WABT" , 1, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WTTO" , 2, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TR_ABT" , 3, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_ABT" , 4, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_TTO" , 5, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_PER" , 6, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_TABT" , 7, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_MABT" , 8, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSC_MSG" , 9, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TSR_ABT" , 10, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SERR" , 11, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"APERR" , 12, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPERR" , 13, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RWR" , 14, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RRD" , 15, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSL_INT" , 16, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCNT0" , 17, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT1" , 18, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT2" , 19, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT3" , 20, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME0" , 21, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME1" , 22, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME2" , 23, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME3" , 24, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT0" , 25, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT1" , 26, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME0" , 27, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME1" , 28, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA0_FI" , 29, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1_FI" , 30, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WIN_WR" , 31, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_WR" , 32, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RD" , 33, 1, 414, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 414, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 0, 6, 415, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_31" , 6, 26, 415, "R/W", 1, 1, 0, 0},
|
|
{"PTR_CNT" , 0, 16, 416, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_CNT" , 16, 16, 416, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_CNT" , 0, 32, 417, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_CNT" , 0, 32, 418, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_TIME" , 0, 32, 419, "R/W", 0, 1, 0ull, 0},
|
|
{"PREFETCH" , 0, 3, 420, "R/W", 0, 0, 0ull, 2ull},
|
|
{"MIN_DATA" , 3, 6, 420, "R/W", 0, 0, 0ull, 4ull},
|
|
{"RESERVED_9_31" , 9, 23, 420, "RAZ", 1, 1, 0, 0},
|
|
{"PREFETCH" , 0, 3, 421, "R/W", 0, 0, 0ull, 3ull},
|
|
{"MIN_DATA" , 3, 6, 421, "R/W", 0, 0, 0ull, 6ull},
|
|
{"RESERVED_9_31" , 9, 23, 421, "RAZ", 1, 1, 0, 0},
|
|
{"PREFETCH" , 0, 3, 422, "R/W", 0, 0, 0ull, 3ull},
|
|
{"MIN_DATA" , 3, 6, 422, "R/W", 0, 0, 0ull, 6ull},
|
|
{"RESERVED_9_31" , 9, 23, 422, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 31, 423, "R/W", 0, 0, 10000ull, 10000ull},
|
|
{"ENB" , 31, 1, 423, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_32_63" , 32, 32, 423, "RAZ", 1, 1, 0, 0},
|
|
{"SCM" , 0, 32, 424, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 424, "RAZ", 1, 1, 0, 0},
|
|
{"TSR" , 0, 36, 425, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 425, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 426, "RAZ", 1, 1, 0, 0},
|
|
{"RD_ADDR" , 3, 45, 426, "R/W", 0, 1, 0ull, 0},
|
|
{"IOBIT" , 48, 1, 426, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 426, "RAZ", 1, 1, 0, 0},
|
|
{"RD_DATA" , 0, 64, 427, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_0_2" , 0, 3, 428, "RAZ", 1, 1, 0, 0},
|
|
{"WR_ADDR" , 3, 45, 428, "R/W", 0, 1, 0ull, 0},
|
|
{"IOBIT" , 48, 1, 428, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 428, "RAZ", 1, 1, 0, 0},
|
|
{"WR_DATA" , 0, 64, 429, "R/W", 0, 1, 0ull, 0},
|
|
{"WR_MASK" , 0, 8, 430, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 430, "RAZ", 1, 1, 0, 0},
|
|
{"LOWATER" , 0, 5, 431, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_5_7" , 5, 3, 431, "RAZ", 0, 1, 0ull, 0},
|
|
{"HIWATER" , 8, 5, 431, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_13_62" , 13, 50, 431, "RAZ", 0, 1, 0ull, 0},
|
|
{"BCKPRS" , 63, 1, 431, "RO", 0, 0, 0ull, 0ull},
|
|
{"BIST" , 0, 18, 432, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 432, "RAZ", 1, 1, 0, 0},
|
|
{"REFLECT" , 0, 1, 433, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INVRES" , 1, 1, 433, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 433, "RAZ", 1, 1, 0, 0},
|
|
{"IV" , 0, 32, 434, "R/W", 0, 0, 1185899593ull, 1185899593ull},
|
|
{"RESERVED_32_63" , 32, 32, 434, "RAZ", 1, 1, 0, 0},
|
|
{"DPRT" , 0, 16, 435, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UDP" , 16, 1, 435, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP" , 17, 1, 435, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 435, "RAZ", 1, 1, 0, 0},
|
|
{"NIP_SHF" , 0, 3, 436, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_7" , 3, 5, 436, "RAZ", 1, 1, 0, 0},
|
|
{"RAW_SHF" , 8, 3, 436, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_15" , 11, 5, 436, "RAZ", 1, 1, 0, 0},
|
|
{"MAX_L2" , 16, 1, 436, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_UDP" , 17, 1, 436, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TAG_SYN" , 18, 1, 436, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 436, "RAZ", 1, 1, 0, 0},
|
|
{"IP_CHK" , 0, 1, 437, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP_MAL" , 1, 1, 437, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP_HOP" , 2, 1, 437, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP4_OPTS" , 3, 1, 437, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP6_EEXT" , 4, 2, 437, "R/W", 0, 0, 1ull, 3ull},
|
|
{"RESERVED_6_7" , 6, 2, 437, "RAZ", 0, 1, 0ull, 0},
|
|
{"L4_MAL" , 8, 1, 437, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_PRT" , 9, 1, 437, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_CHK" , 10, 1, 437, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_LEN" , 11, 1, 437, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TCP_FLAG" , 12, 1, 437, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L2_MAL" , 13, 1, 437, "R/W", 0, 0, 1ull, 1ull},
|
|
{"VS_QOS" , 14, 1, 437, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VS_WQE" , 15, 1, 437, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IGNRS" , 16, 1, 437, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 437, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PKTDRP" , 0, 1, 438, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CRCERR" , 1, 1, 438, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BCKPRS" , 2, 1, 438, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 3, 1, 438, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BADTAG" , 4, 1, 438, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPRUNT" , 5, 1, 438, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TODOOVR" , 6, 1, 438, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FEPERR" , 7, 1, 438, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BEPERR" , 8, 1, 438, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 438, "RAZ", 1, 1, 0, 0},
|
|
{"PKTDRP" , 0, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CRCERR" , 1, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BCKPRS" , 2, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 3, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BADTAG" , 4, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPRUNT" , 5, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TODOOVR" , 6, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FEPERR" , 7, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BEPERR" , 8, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 439, "RAZ", 1, 1, 0, 0},
|
|
{"OFFSET" , 0, 3, 440, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 440, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP" , 0, 7, 441, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 441, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 8, 2, 441, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_11" , 10, 2, 441, "RAZ", 1, 1, 0, 0},
|
|
{"CRC_EN" , 12, 1, 441, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_13_15" , 13, 3, 441, "RAZ", 1, 1, 0, 0},
|
|
{"QOS_VLAN" , 16, 1, 441, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS_DIFF" , 17, 1, 441, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS_VOD" , 18, 1, 441, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_19" , 19, 1, 441, "RAZ", 1, 1, 0, 0},
|
|
{"QOS_WAT" , 20, 4, 441, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS" , 24, 3, 441, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 441, "RAZ", 1, 1, 0, 0},
|
|
{"GRP_WAT" , 28, 4, 441, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INST_HDR" , 32, 1, 441, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DYN_RS" , 33, 1, 441, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TAG_INC" , 34, 2, 441, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RAWDRP" , 36, 1, 441, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 441, "RAZ", 1, 1, 0, 0},
|
|
{"GRP" , 0, 4, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NON_TAG_TYPE" , 4, 2, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_TAG_TYPE" , 6, 2, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_TAG_TYPE" , 8, 2, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP4_TAG_TYPE" , 10, 2, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP6_TAG_TYPE" , 12, 2, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_SRC_FLAG" , 14, 1, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_SRC_FLAG" , 15, 1, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_DST_FLAG" , 16, 1, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_DST_FLAG" , 17, 1, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_PCTL_FLAG" , 18, 1, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_NXTH_FLAG" , 19, 1, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_SPRT_FLAG" , 20, 1, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_SPRT_FLAG" , 21, 1, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_DPRT_FLAG" , 22, 1, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_DPRT_FLAG" , 23, 1, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_PRT_FLAG" , 24, 1, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_VLAN" , 25, 1, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_VS" , 26, 2, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TAG_MODE" , 28, 2, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_30" , 30, 1, 442, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"GRPTAG" , 31, 1, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAGMASK" , 32, 4, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAGBASE" , 36, 4, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 442, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 0, 3, 443, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 443, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 0, 3, 444, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 444, "RAZ", 1, 1, 0, 0},
|
|
{"MATCH_VALUE" , 0, 16, 445, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MATCH_TYPE" , 16, 2, 445, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_19" , 18, 2, 445, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 20, 3, 445, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 445, "RAZ", 1, 1, 0, 0},
|
|
{"GRP" , 24, 4, 445, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_31" , 28, 4, 445, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 32, 16, 445, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 445, "RAZ", 1, 1, 0, 0},
|
|
{"WORD" , 0, 56, 446, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 446, "RAZ", 1, 1, 0, 0},
|
|
{"RST" , 0, 1, 447, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 447, "RAZ", 1, 1, 0, 0},
|
|
{"DRP_OCTS" , 0, 32, 448, "R/W", 0, 1, 0ull, 0},
|
|
{"DRP_PKTS" , 32, 32, 448, "R/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 449, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 449, "RAZ", 1, 1, 0, 0},
|
|
{"RAW" , 0, 32, 450, "R/W", 0, 1, 0ull, 0},
|
|
{"PKTS" , 32, 32, 450, "R/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 0, 32, 451, "R/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 32, 32, 451, "R/W", 0, 1, 0ull, 0},
|
|
{"H64" , 0, 32, 452, "R/W", 0, 1, 0ull, 0},
|
|
{"H65TO127" , 32, 32, 452, "R/W", 0, 1, 0ull, 0},
|
|
{"H128TO255" , 0, 32, 453, "R/W", 0, 1, 0ull, 0},
|
|
{"H256TO511" , 32, 32, 453, "R/W", 0, 1, 0ull, 0},
|
|
{"H512TO1023" , 0, 32, 454, "R/W", 0, 1, 0ull, 0},
|
|
{"H1024TO1518" , 32, 32, 454, "R/W", 0, 1, 0ull, 0},
|
|
{"H1519" , 0, 32, 455, "R/W", 0, 1, 0ull, 0},
|
|
{"FCS" , 32, 32, 455, "R/W", 0, 1, 0ull, 0},
|
|
{"UNDERSZ" , 0, 32, 456, "R/W", 0, 1, 0ull, 0},
|
|
{"FRAG" , 32, 32, 456, "R/W", 0, 1, 0ull, 0},
|
|
{"OVERSZ" , 0, 32, 457, "R/W", 0, 1, 0ull, 0},
|
|
{"JABBER" , 32, 32, 457, "R/W", 0, 1, 0ull, 0},
|
|
{"RDCLR" , 0, 1, 458, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 458, "RAZ", 1, 1, 0, 0},
|
|
{"ERRS" , 0, 16, 459, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 459, "RAZ", 1, 1, 0, 0},
|
|
{"OCTS" , 0, 48, 460, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 460, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 461, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 461, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 8, 462, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 462, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 0, 16, 463, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 463, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 16, 464, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DST" , 16, 16, 464, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 464, "RAZ", 1, 1, 0, 0},
|
|
{"ENTRY" , 0, 62, 465, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_62_62" , 62, 1, 465, "RAZ", 1, 1, 0, 0},
|
|
{"VAL" , 63, 1, 465, "RO", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 32, 466, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 466, "RAZ", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 48, 467, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 467, "RAZ", 1, 1, 0, 0},
|
|
{"SIZE" , 0, 16, 468, "RO", 1, 0, 0, 0ull},
|
|
{"SEGS" , 16, 6, 468, "RO", 1, 0, 0, 0ull},
|
|
{"CMD" , 22, 14, 468, "RO", 1, 0, 0, 0ull},
|
|
{"FAU" , 36, 28, 468, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 469, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 469, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 469, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 469, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 469, "RO", 1, 0, 0, 0ull},
|
|
{"PTRS2" , 0, 17, 470, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 470, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTRS1" , 32, 17, 470, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 470, "RAZ", 1, 0, 0, 0ull},
|
|
{"MOD" , 0, 3, 471, "RO", 1, 0, 0, 0ull},
|
|
{"CNT" , 3, 13, 471, "RO", 1, 0, 0, 0ull},
|
|
{"CHK" , 16, 1, 471, "RO", 1, 0, 0, 0ull},
|
|
{"LEN" , 17, 1, 471, "RO", 1, 0, 0, 0ull},
|
|
{"SOP" , 18, 1, 471, "RO", 1, 0, 0, 0ull},
|
|
{"UID" , 19, 3, 471, "RO", 1, 0, 0, 0ull},
|
|
{"MAJ" , 22, 1, 471, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 471, "RAZ", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 16, 472, "RO", 1, 0, 0, 0ull},
|
|
{"SEGS" , 16, 6, 472, "RO", 1, 0, 0, 0ull},
|
|
{"CMD" , 22, 14, 472, "RO", 1, 0, 0, 0ull},
|
|
{"FAU" , 36, 28, 472, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 473, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 473, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 473, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 473, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 473, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 474, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 474, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 474, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 474, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 474, "RO", 1, 0, 0, 0ull},
|
|
{"DATA" , 0, 64, 475, "RO", 1, 0, 0, 0ull},
|
|
{"MAJOR" , 0, 3, 476, "RO", 1, 0, 0, 0ull},
|
|
{"MINOR" , 3, 2, 476, "RO", 1, 0, 0, 0ull},
|
|
{"WAIT" , 5, 1, 476, "RO", 1, 0, 0, 0ull},
|
|
{"QID_BASE" , 6, 8, 476, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFF" , 14, 4, 476, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFF_MAX" , 18, 4, 476, "RO", 1, 0, 0, 0ull},
|
|
{"QCB_RIDX" , 22, 5, 476, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 27, 3, 476, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 30, 1, 476, "RO", 1, 0, 0, 0ull},
|
|
{"ACTIVE" , 31, 1, 476, "RO", 1, 0, 0, 0ull},
|
|
{"CHK_MODE" , 32, 1, 476, "RO", 1, 0, 0, 0ull},
|
|
{"CHK_ONCE" , 33, 1, 476, "RO", 1, 0, 0, 0ull},
|
|
{"INIT_DWRITE" , 34, 1, 476, "RO", 1, 0, 0, 0ull},
|
|
{"DREAD_SOP" , 35, 1, 476, "RO", 1, 0, 0, 0ull},
|
|
{"UID" , 36, 3, 476, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_OFF" , 39, 6, 476, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_SIZ" , 45, 16, 476, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_SEGS" , 61, 3, 476, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_SEGS" , 0, 3, 477, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_OFF" , 3, 16, 477, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_SIZ" , 19, 16, 477, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_PTR" , 35, 29, 477, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_PTR" , 0, 11, 478, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 478, "RAZ", 1, 0, 0, 0ull},
|
|
{"QCB_RIDX" , 0, 6, 479, "RO", 1, 0, 0, 0ull},
|
|
{"QCB_WIDX" , 6, 6, 479, "RO", 1, 0, 0, 0ull},
|
|
{"BUF_PTR" , 12, 33, 479, "RO", 1, 0, 0, 0ull},
|
|
{"BUF_SIZ" , 45, 13, 479, "RO", 1, 0, 0, 0ull},
|
|
{"TAIL" , 58, 1, 479, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 59, 5, 479, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 0, 3, 480, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_Q" , 3, 1, 480, "RO", 1, 0, 0, 0ull},
|
|
{"S_TAIL" , 4, 1, 480, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 5, 1, 480, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 480, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 8, 20, 480, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 480, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTRS3" , 0, 17, 481, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 481, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTRS0" , 32, 17, 481, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 481, "RAZ", 1, 0, 0, 0ull},
|
|
{"QUEUE" , 0, 7, 482, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT" , 7, 6, 482, "WR0", 1, 0, 0, 0ull},
|
|
{"INDEX" , 13, 3, 482, "WR0", 1, 0, 0, 0ull},
|
|
{"TAIL" , 16, 1, 482, "R/W", 1, 0, 0, 0ull},
|
|
{"BUF_PTR" , 17, 36, 482, "R/W", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 482, "R/W", 1, 0, 0, 0ull},
|
|
{"STATIC_Q" , 61, 1, 482, "R/W", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 62, 1, 482, "R/W", 1, 0, 0, 0ull},
|
|
{"S_TAIL" , 63, 1, 482, "R/W", 1, 0, 0, 0ull},
|
|
{"QID" , 0, 7, 483, "R/W", 1, 0, 0, 0ull},
|
|
{"PID" , 7, 6, 483, "WR0", 1, 0, 0, 0ull},
|
|
{"RESERVED_13_52" , 13, 40, 483, "RAZ", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 483, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_61_63" , 61, 3, 483, "RAZ", 1, 0, 0, 0ull},
|
|
{"DAT_PTR" , 0, 4, 484, "RO", 1, 0, 0, 0ull},
|
|
{"DAT_DAT" , 4, 4, 484, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_QSB" , 8, 3, 484, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_QCB" , 11, 2, 484, "RO", 1, 0, 0, 0ull},
|
|
{"NCB_INB" , 13, 2, 484, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_PSB" , 15, 6, 484, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_NXT" , 21, 1, 484, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_CHK" , 22, 3, 484, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_WIF" , 25, 1, 484, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_STA" , 26, 1, 484, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_CTL" , 27, 3, 484, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_CRC" , 30, 1, 484, "RO", 1, 0, 0, 0ull},
|
|
{"IOB" , 31, 1, 484, "RO", 1, 0, 0, 0ull},
|
|
{"CSR" , 32, 1, 484, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_33_63" , 33, 31, 484, "RAZ", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 13, 485, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_19" , 13, 7, 485, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 20, 3, 485, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 485, "RAZ", 1, 0, 0, 0ull},
|
|
{"REFIN" , 0, 1, 486, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INVRES" , 1, 1, 486, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 486, "RAZ", 1, 1, 0, 0},
|
|
{"ENABLE" , 0, 32, 487, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 487, "RAZ", 1, 0, 0, 0ull},
|
|
{"IV" , 0, 32, 488, "R/W", 0, 0, 1185899593ull, 1185899593ull},
|
|
{"RESERVED_32_63" , 32, 32, 488, "RAZ", 1, 1, 0, 0},
|
|
{"ASSERTS" , 0, 64, 489, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 64, 490, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 64, 491, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 64, 492, "RO", 0, 0, 0ull, 0ull},
|
|
{"PARITY" , 0, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 1, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CURRZERO" , 2, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 493, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENA_PKO" , 0, 1, 494, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENA_DWB" , 1, 1, 494, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STORE_BE" , 2, 1, 494, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 3, 1, 494, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 494, "RAZ", 1, 0, 0, 0ull},
|
|
{"MODE0" , 0, 3, 495, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MODE1" , 3, 3, 495, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 495, "RAZ", 1, 0, 0, 0ull},
|
|
{"PARITY" , 0, 1, 496, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 1, 1, 496, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CURRZERO" , 2, 1, 496, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 496, "RAZ", 1, 0, 0, 0ull},
|
|
{"MODE" , 0, 2, 497, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 497, "RAZ", 1, 0, 0, 0ull},
|
|
{"QID7" , 0, 1, 498, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDX3" , 1, 1, 498, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 498, "RAZ", 1, 0, 0, 0ull},
|
|
{"INDEX" , 0, 8, 499, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 8, 8, 499, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 499, "RAZ", 1, 0, 0, 0ull},
|
|
{"ADR0" , 0, 1, 500, "RO", 0, 0, 0ull, 0ull},
|
|
{"ADR1" , 1, 1, 500, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEND0" , 2, 1, 500, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEND1" , 3, 1, 500, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBR0" , 4, 1, 500, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBR1" , 5, 1, 500, "RO", 0, 0, 0ull, 0ull},
|
|
{"FIDX" , 6, 1, 500, "RO", 0, 0, 0ull, 0ull},
|
|
{"INDEX" , 7, 1, 500, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBT" , 8, 1, 500, "RO", 0, 0, 0ull, 0ull},
|
|
{"CAM" , 9, 1, 500, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_15" , 10, 6, 500, "RAZ", 1, 1, 0, 0},
|
|
{"PP" , 16, 16, 500, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 500, "RAZ", 1, 1, 0, 0},
|
|
{"DS_PC" , 0, 32, 501, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 501, "RAZ", 1, 1, 0, 0},
|
|
{"SBE" , 0, 1, 502, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DBE" , 1, 1, 502, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SBE_IE" , 2, 1, 502, "R/W", 0, 1, 0ull, 0},
|
|
{"DBE_IE" , 3, 1, 502, "R/W", 0, 1, 0ull, 0},
|
|
{"SYN" , 4, 5, 502, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_9_11" , 9, 3, 502, "RAZ", 1, 1, 0, 0},
|
|
{"RPE" , 12, 1, 502, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPE_IE" , 13, 1, 502, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_15" , 14, 2, 502, "RAZ", 1, 1, 0, 0},
|
|
{"IOP" , 16, 13, 502, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_31" , 29, 3, 502, "RAZ", 1, 1, 0, 0},
|
|
{"IOP_IE" , 32, 13, 502, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_45_63" , 45, 19, 502, "RAZ", 1, 1, 0, 0},
|
|
{"NBR_THR" , 0, 5, 503, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PFR_DIS" , 5, 1, 503, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 503, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 32, 504, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 504, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 32, 505, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 505, "RAZ", 1, 1, 0, 0},
|
|
{"NOS_CNT" , 0, 12, 506, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_12_63" , 12, 52, 506, "RAZ", 1, 1, 0, 0},
|
|
{"NW_TIM" , 0, 10, 507, "R/W", 0, 0, 0ull, 1023ull},
|
|
{"RESERVED_10_63" , 10, 54, 507, "RAZ", 1, 1, 0, 0},
|
|
{"RST_MSK" , 0, 8, 508, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 508, "RAZ", 1, 1, 0, 0},
|
|
{"GRP_MSK" , 0, 16, 509, "R/W", 0, 0, 65535ull, 65535ull},
|
|
{"QOS0_PRI" , 16, 4, 509, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS1_PRI" , 20, 4, 509, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS2_PRI" , 24, 4, 509, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS3_PRI" , 28, 4, 509, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS4_PRI" , 32, 4, 509, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS5_PRI" , 36, 4, 509, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS6_PRI" , 40, 4, 509, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS7_PRI" , 44, 4, 509, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 509, "RAZ", 1, 1, 0, 0},
|
|
{"RND" , 0, 8, 510, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P1" , 8, 8, 510, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P2" , 16, 8, 510, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P3" , 24, 8, 510, "R/W", 0, 1, 255ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 510, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_THR" , 0, 11, 511, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_11_11" , 11, 1, 511, "RAZ", 1, 1, 0, 0},
|
|
{"MAX_THR" , 12, 11, 511, "R/W", 0, 1, 2047ull, 0},
|
|
{"RESERVED_23_23" , 23, 1, 511, "RAZ", 1, 1, 0, 0},
|
|
{"FREE_CNT" , 24, 12, 511, "RO", 0, 1, 2027ull, 0},
|
|
{"BUF_CNT" , 36, 12, 511, "RO", 0, 1, 0ull, 0},
|
|
{"DES_CNT" , 48, 12, 511, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 511, "RAZ", 1, 1, 0, 0},
|
|
{"TS_PC" , 0, 32, 512, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 512, "RAZ", 1, 1, 0, 0},
|
|
{"WA_PC" , 0, 32, 513, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 513, "RAZ", 1, 1, 0, 0},
|
|
{"WA_PC" , 0, 32, 514, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 514, "RAZ", 1, 1, 0, 0},
|
|
{"WQ_INT" , 0, 16, 515, "R/W1C", 0, 1, 0ull, 0},
|
|
{"IQ_DIS" , 16, 16, 515, "R/W1", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 515, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 12, 516, "RO", 0, 1, 0ull, 0},
|
|
{"DS_CNT" , 12, 12, 516, "RO", 0, 1, 0ull, 0},
|
|
{"TC_CNT" , 24, 4, 516, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_63" , 28, 36, 516, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 517, "RAZ", 1, 1, 0, 0},
|
|
{"PC_THR" , 8, 20, 517, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_31" , 28, 4, 517, "RAZ", 1, 1, 0, 0},
|
|
{"PC" , 32, 28, 517, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 517, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_THR" , 0, 11, 518, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_11_11" , 11, 1, 518, "RAZ", 1, 1, 0, 0},
|
|
{"DS_THR" , 12, 11, 518, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_23_23" , 23, 1, 518, "RAZ", 1, 1, 0, 0},
|
|
{"TC_THR" , 24, 4, 518, "R/W", 0, 1, 0ull, 0},
|
|
{"TC_EN" , 28, 1, 518, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 518, "RAZ", 1, 1, 0, 0},
|
|
{"WS_PC" , 0, 32, 519, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 519, "RAZ", 1, 1, 0, 0},
|
|
{"MEM" , 0, 1, 520, "RO", 0, 0, 0ull, 0ull},
|
|
{"RRC" , 1, 1, 520, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 520, "RAZ", 1, 1, 0, 0},
|
|
{"ENT_EN" , 0, 1, 521, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNG_EN" , 1, 1, 521, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNM_RST" , 2, 1, 521, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNG_RST" , 3, 1, 521, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EXP_ENT" , 4, 1, 521, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENT_SEL" , 5, 4, 521, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 521, "RAZ", 1, 1, 0, 0},
|
|
{"PHASE" , 0, 8, 522, "R/W", 0, 0, 100ull, 100ull},
|
|
{"SAMPLE" , 8, 4, 522, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PREAMBLE" , 12, 1, 522, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CLK_IDLE" , 13, 1, 522, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_14" , 14, 1, 522, "RAZ", 1, 1, 0, 0},
|
|
{"SAMPLE_MODE" , 15, 1, 522, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SAMPLE_HI" , 16, 5, 522, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_63" , 21, 43, 522, "RAZ", 1, 1, 0, 0},
|
|
{"REG_ADR" , 0, 5, 523, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 523, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_ADR" , 8, 5, 523, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_13_15" , 13, 3, 523, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_OP" , 16, 1, 523, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_17_63" , 17, 47, 523, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 524, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 524, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 525, "RO", 0, 1, 0ull, 0},
|
|
{"VAL" , 16, 1, 525, "RO", 0, 1, 0ull, 0},
|
|
{"PENDING" , 17, 1, 525, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 525, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 526, "R/W", 0, 1, 0ull, 0},
|
|
{"VAL" , 16, 1, 526, "RO", 0, 1, 0ull, 0},
|
|
{"PENDING" , 17, 1, 526, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 526, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 527, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 527, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STAT0" , 0, 1, 528, "RO", 0, 0, 0ull, 0ull},
|
|
{"STAT1" , 1, 1, 528, "RO", 0, 0, 0ull, 0ull},
|
|
{"STAT2" , 2, 1, 528, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 528, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SRXDLCK" , 0, 1, 529, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RCVTRN" , 1, 1, 529, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DRPTRN" , 2, 1, 529, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SNDTRN" , 3, 1, 529, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STATRCV" , 4, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STATDRV" , 5, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RUNBIST" , 6, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLKDLY" , 7, 5, 529, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_12_15" , 12, 4, 529, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SEETRN" , 16, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 529, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_3" , 0, 4, 530, "RAZ", 0, 1, 0ull, 0},
|
|
{"D4CLK0" , 4, 1, 530, "R/W1C", 0, 1, 0ull, 0},
|
|
{"D4CLK1" , 5, 1, 530, "R/W1C", 0, 1, 0ull, 0},
|
|
{"S4CLK0" , 6, 1, 530, "R/W1C", 0, 1, 0ull, 0},
|
|
{"S4CLK1" , 7, 1, 530, "R/W1C", 0, 1, 0ull, 0},
|
|
{"SRXTRN" , 8, 1, 530, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_9_9" , 9, 1, 530, "RAZ", 0, 1, 0ull, 0},
|
|
{"STXCAL" , 10, 1, 530, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_11_63" , 11, 53, 530, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DLLDIS" , 0, 1, 531, "R/W", 1, 0, 0, 0ull},
|
|
{"DLLFRC" , 1, 1, 531, "WR0", 1, 0, 0, 0ull},
|
|
{"OFFDLY" , 2, 6, 531, "R/W", 1, 0, 0, 0ull},
|
|
{"BITSEL" , 8, 5, 531, "R/W", 1, 1, 0, 0},
|
|
{"OFFSET" , 13, 5, 531, "R/W", 1, 1, 0, 0},
|
|
{"MUX" , 18, 1, 531, "WR0", 1, 1, 0, 0},
|
|
{"INC" , 19, 1, 531, "WR0", 1, 1, 0, 0},
|
|
{"DEC" , 20, 1, 531, "WR0", 1, 1, 0, 0},
|
|
{"CLRDLY" , 21, 1, 531, "WR0", 1, 1, 0, 0},
|
|
{"RESERVED_22_23" , 22, 2, 531, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SSTEP" , 24, 1, 531, "R/W", 1, 0, 0, 0ull},
|
|
{"SSTEP_GO" , 25, 1, 531, "WR0", 1, 1, 0, 0},
|
|
{"RESERVED_26_27" , 26, 2, 531, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FALL8" , 28, 1, 531, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FALLNOP" , 29, 1, 531, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_63" , 30, 34, 531, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OFFSET" , 0, 5, 532, "RO", 0, 1, 0ull, 0},
|
|
{"MUXSEL" , 5, 2, 532, "RO", 0, 1, 0ull, 0},
|
|
{"UNXTERM" , 7, 1, 532, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TESTRES" , 8, 1, 532, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 532, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SRX4CMP" , 0, 10, 533, "R/W", 0, 0, 239ull, 239ull},
|
|
{"RESERVED_10_15" , 10, 6, 533, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STX4PCMP" , 16, 4, 533, "R/W", 0, 0, 3ull, 3ull},
|
|
{"STX4NCMP" , 20, 4, 533, "R/W", 0, 0, 12ull, 12ull},
|
|
{"RESERVED_24_63" , 24, 40, 533, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ERRCNT" , 0, 4, 534, "R/W", 0, 0, 0ull, 3ull},
|
|
{"RESERVED_4_5" , 4, 2, 534, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DIPPAY" , 6, 1, 534, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DIPCLS" , 7, 1, 534, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 8, 1, 534, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 534, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRT" , 0, 8, 535, "RO", 0, 0, 0ull, 0ull},
|
|
{"RSVOP" , 8, 4, 535, "RO", 0, 0, 0ull, 0ull},
|
|
{"CALBNK" , 12, 2, 535, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_30" , 14, 17, 535, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MUL" , 31, 1, 535, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 535, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 0, 1, 536, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ABNORM" , 1, 1, 536, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_3" , 2, 2, 536, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SPIOVR" , 4, 1, 536, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLSERR" , 5, 1, 536, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRWNNG" , 6, 1, 536, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 7, 1, 536, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TPAOVR" , 8, 1, 536, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DIPERR" , 9, 1, 536, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SYNCERR" , 10, 1, 536, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CALERR" , 11, 1, 536, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 536, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 0, 1, 537, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ABNORM" , 1, 1, 537, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_3" , 2, 2, 537, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SPIOVR" , 4, 1, 537, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CLSERR" , 5, 1, 537, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DRWNNG" , 6, 1, 537, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 7, 1, 537, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TPAOVR" , 8, 1, 537, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DIPERR" , 9, 1, 537, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SYNCERR" , 10, 1, 537, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CALERR" , 11, 1, 537, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_30" , 12, 19, 537, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SPF" , 31, 1, 537, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 537, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 0, 1, 538, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ABNORM" , 1, 1, 538, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_3" , 2, 2, 538, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SPIOVR" , 4, 1, 538, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLSERR" , 5, 1, 538, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRWNNG" , 6, 1, 538, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 7, 1, 538, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TPAOVR" , 8, 1, 538, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DIPERR" , 9, 1, 538, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SYNCERR" , 10, 1, 538, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CALERR" , 11, 1, 538, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 538, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 0, 32, 539, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 539, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX" , 0, 32, 540, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 540, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRTSEL" , 0, 4, 541, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 541, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MUX_EN" , 0, 1, 542, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MACRO_EN" , 1, 1, 542, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAXDIST" , 2, 5, 542, "R/W", 0, 0, 0ull, 8ull},
|
|
{"SET_BOOT" , 7, 1, 542, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLR_BOOT" , 8, 1, 542, "R/W", 0, 0, 0ull, 0ull},
|
|
{"JITTER" , 9, 3, 542, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TRNTEST" , 12, 1, 542, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 542, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"INF_EN" , 0, 1, 543, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_2" , 1, 2, 543, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ST_EN" , 3, 1, 543, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PRTS" , 4, 4, 543, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 543, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IGNORE" , 0, 16, 544, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 544, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRT0" , 0, 4, 545, "R/W", 1, 1, 0, 0},
|
|
{"PRT1" , 4, 4, 545, "R/W", 1, 1, 0, 0},
|
|
{"PRT2" , 8, 4, 545, "R/W", 1, 1, 0, 0},
|
|
{"PRT3" , 12, 4, 545, "R/W", 1, 1, 0, 0},
|
|
{"ODDPAR" , 16, 1, 545, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_17_63" , 17, 47, 545, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LEN" , 0, 7, 546, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_7" , 7, 1, 546, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"M" , 8, 8, 546, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 546, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 4, 547, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OPC" , 4, 4, 547, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MOD" , 8, 4, 547, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SOP" , 12, 1, 547, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EOP" , 13, 1, 547, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 547, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DAT" , 0, 64, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_2" , 0, 3, 549, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IGNTPA" , 3, 1, 549, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_4" , 4, 1, 549, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MINTRN" , 5, 1, 549, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 549, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 0, 32, 550, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 550, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"INF_EN" , 0, 1, 551, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_2" , 1, 2, 551, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ST_EN" , 3, 1, 551, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 551, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DIPMAX" , 0, 4, 552, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMMAX" , 4, 4, 552, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 552, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IGNTPA" , 0, 16, 553, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 553, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CALPAR0" , 0, 1, 554, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CALPAR1" , 1, 1, 554, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OVRBST" , 2, 1, 554, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DATOVR" , 3, 1, 554, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DIPERR" , 4, 1, 554, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NOSYNC" , 5, 1, 554, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UNXFRM" , 6, 1, 554, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMERR" , 7, 1, 554, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 554, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CALPAR0" , 0, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CALPAR1" , 1, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OVRBST" , 2, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DATOVR" , 3, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DIPERR" , 4, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NOSYNC" , 5, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UNXFRM" , 6, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FRMERR" , 7, 1, 555, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SYNCERR" , 8, 1, 555, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 555, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CALPAR0" , 0, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CALPAR1" , 1, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OVRBST" , 2, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DATOVR" , 3, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DIPERR" , 4, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NOSYNC" , 5, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UNXFRM" , 6, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMERR" , 7, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 556, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MINB" , 0, 9, 557, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 557, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRT0" , 0, 4, 558, "R/W", 1, 1, 0, 0},
|
|
{"PRT1" , 4, 4, 558, "R/W", 1, 1, 0, 0},
|
|
{"PRT2" , 8, 4, 558, "R/W", 1, 1, 0, 0},
|
|
{"PRT3" , 12, 4, 558, "R/W", 1, 1, 0, 0},
|
|
{"ODDPAR" , 16, 1, 558, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_17_63" , 17, 47, 558, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX_T" , 0, 16, 559, "R/W", 0, 1, 0ull, 0},
|
|
{"ALPHA" , 16, 16, 559, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 559, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LEN" , 0, 7, 560, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_7" , 7, 1, 560, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"M" , 8, 8, 560, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 560, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 0, 32, 561, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 561, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 0, 32, 562, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 562, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"BCKPRS" , 0, 4, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLR" , 4, 1, 563, "WR0", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 563, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 0, 32, 564, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 564, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"INTERVAL" , 0, 22, 565, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 565, "RAZ", 1, 0, 0, 0ull},
|
|
{"COUNT" , 24, 22, 565, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_46_46" , 46, 1, 565, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENA" , 47, 1, 565, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 565, "RAZ", 1, 0, 0, 0ull},
|
|
{"BSIZE" , 0, 20, 566, "RO", 1, 0, 0, 0ull},
|
|
{"BASE" , 20, 31, 566, "RO", 1, 0, 0, 0ull},
|
|
{"BUCKET" , 51, 13, 566, "RO", 1, 0, 0, 0ull},
|
|
{"BUCKET" , 0, 7, 567, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 567, "RAZ", 1, 0, 0, 0ull},
|
|
{"CSIZE" , 8, 13, 567, "RO", 1, 0, 0, 0ull},
|
|
{"CPOOL" , 21, 3, 567, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 567, "RAZ", 1, 0, 0, 0ull},
|
|
{"RING" , 0, 4, 568, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NUM_BUCKETS" , 4, 20, 568, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIRST_BUCKET" , 24, 31, 568, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_55_63" , 55, 9, 568, "RAZ", 1, 0, 0, 0ull},
|
|
{"RING" , 0, 4, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTERVAL" , 4, 22, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WORDS_PER_CHUNK" , 26, 13, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 39, 3, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENABLE" , 42, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_43_63" , 43, 21, 569, "RAZ", 1, 0, 0, 0ull},
|
|
{"CTL" , 0, 1, 570, "RO", 1, 0, 0, 0ull},
|
|
{"NCB" , 1, 1, 570, "RO", 1, 0, 0, 0ull},
|
|
{"STA" , 2, 2, 570, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 570, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 16, 571, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 571, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENABLE_TIMERS" , 0, 1, 572, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENABLE_DWB" , 1, 1, 572, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 2, 1, 572, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 572, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 16, 573, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 573, "RAZ", 1, 0, 0, 0ull},
|
|
{"INDEX" , 0, 8, 574, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 8, 8, 574, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 574, "RAZ", 1, 0, 0, 0ull},
|
|
{"TDF0" , 0, 1, 575, "RO", 0, 0, 0ull, 0ull},
|
|
{"TDF1" , 1, 1, 575, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCF" , 2, 1, 575, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 575, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ENA" , 0, 1, 576, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WRAP" , 1, 1, 576, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRIG_CTL" , 2, 2, 576, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIME_GRN" , 4, 3, 576, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FULL_THR" , 7, 2, 576, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CIU_TRG" , 9, 1, 576, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CIU_THR" , 10, 1, 576, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_TRG" , 11, 1, 576, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_THR" , 12, 1, 576, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_ENA" , 13, 1, 576, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IGNORE_O" , 14, 1, 576, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 576, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WPTR" , 0, 8, 577, "RO", 0, 0, 0ull, 0ull},
|
|
{"RPTR" , 8, 8, 577, "RO", 0, 0, 0ull, 0ull},
|
|
{"CYCLES" , 16, 48, 577, "RO", 0, 0, 0ull, 0ull},
|
|
{"WPTR" , 0, 10, 578, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_11" , 10, 2, 578, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RPTR" , 12, 10, 578, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 578, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CYCLES" , 24, 40, 578, "RO", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 579, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 579, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 580, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 581, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 581, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 581, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 581, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 581, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 581, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 581, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 581, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 581, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 581, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 581, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 581, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 581, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 581, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 581, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 581, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SAA" , 16, 1, 581, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_17_63" , 17, 47, 581, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 582, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 582, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 582, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 582, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 582, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 582, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 582, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 582, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 582, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 582, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 582, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 582, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 583, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 583, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 583, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 583, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 583, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 583, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CIU_TRG" , 0, 1, 584, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CIU_THR" , 1, 1, 584, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MCD0_TRG" , 2, 1, 584, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MCD0_THR" , 3, 1, 584, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 584, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DATA" , 0, 64, 585, "RO", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 586, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 586, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 587, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 587, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 588, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 588, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 588, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 588, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 588, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 588, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 588, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 588, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 588, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 588, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 588, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 588, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 588, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 588, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 588, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 588, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SAA" , 16, 1, 588, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_17_63" , 17, 47, 588, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 589, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 589, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 589, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 589, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 589, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 589, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 589, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 589, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 589, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 589, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 589, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 589, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 590, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 590, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 590, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 590, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 590, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 590, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 591, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 591, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 592, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 592, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 593, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 593, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 593, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 593, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 593, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 593, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 593, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 593, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 593, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 593, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 593, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 593, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 593, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 593, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 593, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 593, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SAA" , 16, 1, 593, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_17_63" , 17, 47, 593, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 594, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 594, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 594, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 594, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 594, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 594, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 594, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 594, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 594, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 594, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 594, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 594, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 595, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 595, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 595, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 595, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 595, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 595, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ZIP_CTL" , 0, 4, 596, "RO", 1, 0, 0, 0ull},
|
|
{"ZIP_CORE" , 4, 27, 596, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 596, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 33, 597, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 33, 13, 597, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 46, 3, 597, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 49, 9, 597, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_58_63" , 58, 6, 597, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 0, 1, 598, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FORCECLK" , 1, 1, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 598, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DISABLED" , 0, 1, 599, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_7" , 1, 7, 599, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CTXSIZE" , 8, 12, 599, "RO", 0, 0, 1536ull, 1536ull},
|
|
{"ONFSIZE" , 20, 12, 599, "RO", 0, 0, 512ull, 512ull},
|
|
{"DEPTH" , 32, 16, 599, "RO", 0, 0, 31744ull, 31744ull},
|
|
{"RESERVED_48_63" , 48, 16, 599, "RAZ", 1, 0, 0, 0ull},
|
|
{"ASSERTS" , 0, 14, 600, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 600, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 0, 1, 601, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 601, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 0, 1, 602, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 602, "RAZ", 1, 0, 0, 0ull},
|
|
{NULL,0,0,0,0,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn58xx[] = {
|
|
/* name , ---------------type, bits, off, #field, fld of */
|
|
{"cvmx_asx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 4, 0},
|
|
{"cvmx_asx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 4, 4},
|
|
{"cvmx_asx#_prt_loop" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 3, 8},
|
|
{"cvmx_asx#_rld_bypass" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 2, 11},
|
|
{"cvmx_asx#_rld_bypass_setting", CVMX_CSR_DB_TYPE_RSL, 64, 8, 2, 13},
|
|
{"cvmx_asx#_rld_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 3, 15},
|
|
{"cvmx_asx#_rld_data_drv" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 3, 18},
|
|
{"cvmx_asx#_rld_nctl_strong" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 2, 21},
|
|
{"cvmx_asx#_rld_nctl_weak" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 2, 23},
|
|
{"cvmx_asx#_rld_pctl_strong" , CVMX_CSR_DB_TYPE_RSL, 64, 18, 2, 25},
|
|
{"cvmx_asx#_rld_pctl_weak" , CVMX_CSR_DB_TYPE_RSL, 64, 20, 2, 27},
|
|
{"cvmx_asx#_rld_setting" , CVMX_CSR_DB_TYPE_RSL, 64, 22, 6, 29},
|
|
{"cvmx_asx#_rx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 24, 2, 35},
|
|
{"cvmx_asx#_rx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 32, 2, 37},
|
|
{"cvmx_asx#_tx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 34, 2, 39},
|
|
{"cvmx_asx#_tx_comp_byp" , CVMX_CSR_DB_TYPE_RSL, 64, 42, 4, 41},
|
|
{"cvmx_asx#_tx_hi_water#" , CVMX_CSR_DB_TYPE_RSL, 64, 44, 2, 45},
|
|
{"cvmx_asx#_tx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 2, 47},
|
|
{"cvmx_asx0_dbg_data_drv" , CVMX_CSR_DB_TYPE_RSL, 64, 54, 3, 49},
|
|
{"cvmx_asx0_dbg_data_enable" , CVMX_CSR_DB_TYPE_RSL, 64, 55, 2, 52},
|
|
{"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 56, 2, 54},
|
|
{"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 57, 2, 56},
|
|
{"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 58, 2, 58},
|
|
{"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 59, 2, 60},
|
|
{"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 60, 15, 62},
|
|
{"cvmx_ciu_int#_en0_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 93, 15, 77},
|
|
{"cvmx_ciu_int#_en0_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 126, 15, 92},
|
|
{"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 159, 2, 107},
|
|
{"cvmx_ciu_int#_en1_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 192, 2, 109},
|
|
{"cvmx_ciu_int#_en1_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 225, 2, 111},
|
|
{"cvmx_ciu_int#_en4_0" , CVMX_CSR_DB_TYPE_NCB, 64, 258, 15, 113},
|
|
{"cvmx_ciu_int#_en4_0_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 274, 15, 128},
|
|
{"cvmx_ciu_int#_en4_0_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 290, 15, 143},
|
|
{"cvmx_ciu_int#_en4_1" , CVMX_CSR_DB_TYPE_NCB, 64, 306, 2, 158},
|
|
{"cvmx_ciu_int#_en4_1_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 322, 2, 160},
|
|
{"cvmx_ciu_int#_en4_1_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 338, 2, 162},
|
|
{"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 354, 15, 164},
|
|
{"cvmx_ciu_int#_sum4" , CVMX_CSR_DB_TYPE_NCB, 64, 387, 15, 179},
|
|
{"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 403, 2, 194},
|
|
{"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 404, 2, 196},
|
|
{"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 420, 2, 198},
|
|
{"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 436, 2, 200},
|
|
{"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 437, 2, 202},
|
|
{"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 438, 2, 204},
|
|
{"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 439, 1, 206},
|
|
{"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 455, 3, 207},
|
|
{"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 456, 2, 210},
|
|
{"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 457, 4, 212},
|
|
{"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 458, 2, 216},
|
|
{"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 459, 3, 218},
|
|
{"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 463, 7, 221},
|
|
{"cvmx_dbg_data" , CVMX_CSR_DB_TYPE_NCB, 64, 479, 5, 228},
|
|
{"cvmx_dfa_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 480, 4, 233},
|
|
{"cvmx_dfa_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 481, 10, 237},
|
|
{"cvmx_dfa_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 482, 5, 247},
|
|
{"cvmx_dfa_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 483, 2, 252},
|
|
{"cvmx_dfa_difctl" , CVMX_CSR_DB_TYPE_NCB, 64, 484, 4, 254},
|
|
{"cvmx_dfa_difrdptr" , CVMX_CSR_DB_TYPE_NCB, 64, 485, 3, 258},
|
|
{"cvmx_dfa_err" , CVMX_CSR_DB_TYPE_RSL, 64, 486, 21, 261},
|
|
{"cvmx_dfa_memcfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 487, 20, 282},
|
|
{"cvmx_dfa_memcfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 488, 11, 302},
|
|
{"cvmx_dfa_memcfg2" , CVMX_CSR_DB_TYPE_RSL, 64, 489, 8, 313},
|
|
{"cvmx_dfa_memfadr" , CVMX_CSR_DB_TYPE_RSL, 64, 490, 6, 321},
|
|
{"cvmx_dfa_memfcr" , CVMX_CSR_DB_TYPE_RSL, 64, 491, 6, 327},
|
|
{"cvmx_dfa_memrld" , CVMX_CSR_DB_TYPE_RSL, 64, 492, 2, 333},
|
|
{"cvmx_dfa_ncbctl" , CVMX_CSR_DB_TYPE_RSL, 64, 493, 8, 335},
|
|
{"cvmx_dfa_rodt_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 494, 6, 343},
|
|
{"cvmx_dfa_sbd_dbg0" , CVMX_CSR_DB_TYPE_RSL, 64, 495, 1, 349},
|
|
{"cvmx_dfa_sbd_dbg1" , CVMX_CSR_DB_TYPE_RSL, 64, 496, 1, 350},
|
|
{"cvmx_dfa_sbd_dbg2" , CVMX_CSR_DB_TYPE_RSL, 64, 497, 1, 351},
|
|
{"cvmx_dfa_sbd_dbg3" , CVMX_CSR_DB_TYPE_RSL, 64, 498, 1, 352},
|
|
{"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 499, 6, 353},
|
|
{"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 500, 7, 359},
|
|
{"cvmx_fpa_fpf#_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 501, 3, 366},
|
|
{"cvmx_fpa_fpf#_size" , CVMX_CSR_DB_TYPE_RSL, 64, 508, 2, 369},
|
|
{"cvmx_fpa_fpf0_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 515, 3, 371},
|
|
{"cvmx_fpa_fpf0_size" , CVMX_CSR_DB_TYPE_RSL, 64, 516, 2, 374},
|
|
{"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 517, 29, 376},
|
|
{"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 518, 29, 405},
|
|
{"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 519, 2, 434},
|
|
{"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 527, 2, 436},
|
|
{"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 535, 3, 438},
|
|
{"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 536, 3, 441},
|
|
{"cvmx_fpa_wart_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 537, 2, 444},
|
|
{"cvmx_fpa_wart_status" , CVMX_CSR_DB_TYPE_RSL, 64, 538, 2, 446},
|
|
{"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 539, 8, 448},
|
|
{"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 541, 2, 456},
|
|
{"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 543, 3, 458},
|
|
{"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 545, 2, 461},
|
|
{"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 547, 5, 463},
|
|
{"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 555, 1, 468},
|
|
{"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 563, 1, 469},
|
|
{"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 571, 1, 470},
|
|
{"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 579, 1, 471},
|
|
{"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 587, 1, 472},
|
|
{"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 595, 1, 473},
|
|
{"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 603, 2, 474},
|
|
{"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 611, 4, 476},
|
|
{"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 619, 2, 480},
|
|
{"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 627, 11, 482},
|
|
{"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 635, 12, 493},
|
|
{"cvmx_gmx#_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 643, 2, 505},
|
|
{"cvmx_gmx#_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 651, 2, 507},
|
|
{"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 659, 2, 509},
|
|
{"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 667, 21, 511},
|
|
{"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 675, 21, 532},
|
|
{"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 683, 2, 553},
|
|
{"cvmx_gmx#_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 691, 2, 555},
|
|
{"cvmx_gmx#_rx#_rx_inbnd" , CVMX_CSR_DB_TYPE_RSL, 64, 699, 4, 557},
|
|
{"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 707, 2, 561},
|
|
{"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 715, 2, 563},
|
|
{"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 723, 2, 565},
|
|
{"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 731, 2, 567},
|
|
{"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 739, 2, 569},
|
|
{"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 747, 2, 571},
|
|
{"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 755, 2, 573},
|
|
{"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 763, 2, 575},
|
|
{"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 771, 2, 577},
|
|
{"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 779, 2, 579},
|
|
{"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 787, 4, 581},
|
|
{"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 795, 2, 585},
|
|
{"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 803, 2, 587},
|
|
{"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 811, 2, 589},
|
|
{"cvmx_gmx#_rx_pass_en" , CVMX_CSR_DB_TYPE_RSL, 64, 819, 2, 591},
|
|
{"cvmx_gmx#_rx_pass_map#" , CVMX_CSR_DB_TYPE_RSL, 64, 821, 2, 593},
|
|
{"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 853, 3, 595},
|
|
{"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 855, 2, 598},
|
|
{"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 857, 2, 600},
|
|
{"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 865, 3, 602},
|
|
{"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 867, 5, 605},
|
|
{"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 875, 2, 610},
|
|
{"cvmx_gmx#_tx#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 883, 2, 612},
|
|
{"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 891, 3, 614},
|
|
{"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 899, 2, 617},
|
|
{"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 907, 2, 619},
|
|
{"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 915, 2, 621},
|
|
{"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 923, 2, 623},
|
|
{"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 931, 2, 625},
|
|
{"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 939, 2, 627},
|
|
{"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 947, 2, 629},
|
|
{"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 955, 2, 631},
|
|
{"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 963, 2, 633},
|
|
{"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 971, 2, 635},
|
|
{"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 979, 2, 637},
|
|
{"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 987, 2, 639},
|
|
{"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 995, 2, 641},
|
|
{"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 1003, 2, 643},
|
|
{"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 1011, 2, 645},
|
|
{"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 1019, 2, 647},
|
|
{"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 1027, 2, 649},
|
|
{"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1035, 2, 651},
|
|
{"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 1043, 2, 653},
|
|
{"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 1051, 2, 655},
|
|
{"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 1053, 2, 657},
|
|
{"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 1055, 2, 659},
|
|
{"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 1057, 3, 661},
|
|
{"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1059, 8, 664},
|
|
{"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1061, 8, 672},
|
|
{"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 1063, 2, 680},
|
|
{"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 1065, 2, 682},
|
|
{"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 1067, 4, 684},
|
|
{"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 1069, 2, 688},
|
|
{"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 1071, 2, 690},
|
|
{"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 1073, 2, 692},
|
|
{"cvmx_gmx#_tx_spi_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1075, 3, 694},
|
|
{"cvmx_gmx#_tx_spi_drain" , CVMX_CSR_DB_TYPE_RSL, 64, 1077, 2, 697},
|
|
{"cvmx_gmx#_tx_spi_max" , CVMX_CSR_DB_TYPE_RSL, 64, 1079, 4, 699},
|
|
{"cvmx_gmx#_tx_spi_round#" , CVMX_CSR_DB_TYPE_RSL, 64, 1081, 2, 703},
|
|
{"cvmx_gmx#_tx_spi_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 1145, 2, 705},
|
|
{"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 1147, 7, 707},
|
|
{"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 1163, 2, 714},
|
|
{"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 1164, 2, 716},
|
|
{"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 1165, 2, 718},
|
|
{"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 1166, 2, 720},
|
|
{"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1167, 19, 722},
|
|
{"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1168, 6, 741},
|
|
{"cvmx_iob_dwb_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1169, 3, 747},
|
|
{"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 1170, 3, 750},
|
|
{"cvmx_iob_i2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1171, 3, 753},
|
|
{"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 1172, 5, 756},
|
|
{"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 1173, 5, 761},
|
|
{"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 1174, 1, 766},
|
|
{"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1175, 1, 767},
|
|
{"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1176, 7, 768},
|
|
{"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1177, 7, 775},
|
|
{"cvmx_iob_n2c_l2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1178, 3, 782},
|
|
{"cvmx_iob_n2c_rsp_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1179, 3, 785},
|
|
{"cvmx_iob_outb_com_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1180, 3, 788},
|
|
{"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 1181, 5, 791},
|
|
{"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 1182, 5, 796},
|
|
{"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 1183, 1, 801},
|
|
{"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 1184, 1, 802},
|
|
{"cvmx_iob_outb_fpa_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1185, 3, 803},
|
|
{"cvmx_iob_outb_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1186, 3, 806},
|
|
{"cvmx_iob_p2c_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 1187, 3, 809},
|
|
{"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1188, 2, 812},
|
|
{"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 1189, 2, 814},
|
|
{"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 1190, 2, 816},
|
|
{"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 1191, 2, 818},
|
|
{"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1192, 17, 820},
|
|
{"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 1193, 2, 837},
|
|
{"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 1194, 1, 839},
|
|
{"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1195, 12, 840},
|
|
{"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 1196, 11, 852},
|
|
{"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 1197, 11, 863},
|
|
{"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 1198, 2, 874},
|
|
{"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 1199, 2, 876},
|
|
{"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 1200, 2, 878},
|
|
{"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1201, 3, 880},
|
|
{"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 1237, 2, 883},
|
|
{"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 1273, 6, 885},
|
|
{"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 1274, 5, 891},
|
|
{"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 1275, 6, 896},
|
|
{"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1276, 7, 902},
|
|
{"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 1277, 2, 909},
|
|
{"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1285, 2, 911},
|
|
{"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 1286, 3, 913},
|
|
{"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 1287, 5, 916},
|
|
{"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 1295, 3, 921},
|
|
{"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 1296, 2, 924},
|
|
{"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 1297, 2, 926},
|
|
{"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 1298, 2, 928},
|
|
{"cvmx_key_bist_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1299, 4, 930},
|
|
{"cvmx_key_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1300, 3, 934},
|
|
{"cvmx_key_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1301, 5, 937},
|
|
{"cvmx_key_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1302, 5, 942},
|
|
{"cvmx_l2c_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 1303, 7, 947},
|
|
{"cvmx_l2c_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 1304, 5, 954},
|
|
{"cvmx_l2c_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 1305, 8, 959},
|
|
{"cvmx_l2c_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1306, 13, 967},
|
|
{"cvmx_l2c_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1307, 8, 980},
|
|
{"cvmx_l2c_dut" , CVMX_CSR_DB_TYPE_RSL, 64, 1308, 5, 988},
|
|
{"cvmx_l2c_lckbase" , CVMX_CSR_DB_TYPE_RSL, 64, 1309, 4, 993},
|
|
{"cvmx_l2c_lckoff" , CVMX_CSR_DB_TYPE_RSL, 64, 1310, 2, 997},
|
|
{"cvmx_l2c_lfb0" , CVMX_CSR_DB_TYPE_RSL, 64, 1311, 14, 999},
|
|
{"cvmx_l2c_lfb1" , CVMX_CSR_DB_TYPE_RSL, 64, 1312, 19, 1013},
|
|
{"cvmx_l2c_lfb2" , CVMX_CSR_DB_TYPE_RSL, 64, 1313, 3, 1032},
|
|
{"cvmx_l2c_lfb3" , CVMX_CSR_DB_TYPE_RSL, 64, 1314, 3, 1035},
|
|
{"cvmx_l2c_pfc#" , CVMX_CSR_DB_TYPE_RSL, 64, 1315, 2, 1038},
|
|
{"cvmx_l2c_pfctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1319, 17, 1040},
|
|
{"cvmx_l2c_spar0" , CVMX_CSR_DB_TYPE_RSL, 64, 1320, 5, 1057},
|
|
{"cvmx_l2c_spar1" , CVMX_CSR_DB_TYPE_RSL, 64, 1321, 5, 1062},
|
|
{"cvmx_l2c_spar2" , CVMX_CSR_DB_TYPE_RSL, 64, 1322, 5, 1067},
|
|
{"cvmx_l2c_spar3" , CVMX_CSR_DB_TYPE_RSL, 64, 1323, 5, 1072},
|
|
{"cvmx_l2c_spar4" , CVMX_CSR_DB_TYPE_RSL, 64, 1324, 2, 1077},
|
|
{"cvmx_l2d_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 1325, 3, 1079},
|
|
{"cvmx_l2d_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 1326, 2, 1082},
|
|
{"cvmx_l2d_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 1327, 2, 1084},
|
|
{"cvmx_l2d_bst3" , CVMX_CSR_DB_TYPE_RSL, 64, 1328, 2, 1086},
|
|
{"cvmx_l2d_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1329, 7, 1088},
|
|
{"cvmx_l2d_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1330, 5, 1095},
|
|
{"cvmx_l2d_fsyn0" , CVMX_CSR_DB_TYPE_RSL, 64, 1331, 3, 1100},
|
|
{"cvmx_l2d_fsyn1" , CVMX_CSR_DB_TYPE_RSL, 64, 1332, 3, 1103},
|
|
{"cvmx_l2d_fus0" , CVMX_CSR_DB_TYPE_RSL, 64, 1333, 2, 1106},
|
|
{"cvmx_l2d_fus1" , CVMX_CSR_DB_TYPE_RSL, 64, 1334, 2, 1108},
|
|
{"cvmx_l2d_fus2" , CVMX_CSR_DB_TYPE_RSL, 64, 1335, 2, 1110},
|
|
{"cvmx_l2d_fus3" , CVMX_CSR_DB_TYPE_RSL, 64, 1336, 6, 1112},
|
|
{"cvmx_l2t_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1337, 14, 1118},
|
|
{"cvmx_led_blink" , CVMX_CSR_DB_TYPE_RSL, 64, 1338, 2, 1132},
|
|
{"cvmx_led_clk_phase" , CVMX_CSR_DB_TYPE_RSL, 64, 1339, 2, 1134},
|
|
{"cvmx_led_cylon" , CVMX_CSR_DB_TYPE_RSL, 64, 1340, 2, 1136},
|
|
{"cvmx_led_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1341, 2, 1138},
|
|
{"cvmx_led_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1342, 2, 1140},
|
|
{"cvmx_led_polarity" , CVMX_CSR_DB_TYPE_RSL, 64, 1343, 2, 1142},
|
|
{"cvmx_led_prt" , CVMX_CSR_DB_TYPE_RSL, 64, 1344, 2, 1144},
|
|
{"cvmx_led_prt_fmt" , CVMX_CSR_DB_TYPE_RSL, 64, 1345, 2, 1146},
|
|
{"cvmx_led_prt_status#" , CVMX_CSR_DB_TYPE_RSL, 64, 1346, 2, 1148},
|
|
{"cvmx_led_udd_cnt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1354, 2, 1150},
|
|
{"cvmx_led_udd_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 1356, 2, 1152},
|
|
{"cvmx_led_udd_dat_clr#" , CVMX_CSR_DB_TYPE_RSL, 64, 1358, 2, 1154},
|
|
{"cvmx_led_udd_dat_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 1360, 2, 1156},
|
|
{"cvmx_lmc#_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1362, 7, 1158},
|
|
{"cvmx_lmc#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1363, 19, 1165},
|
|
{"cvmx_lmc#_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 1364, 4, 1184},
|
|
{"cvmx_lmc#_dclk_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1365, 2, 1188},
|
|
{"cvmx_lmc#_dclk_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1366, 2, 1190},
|
|
{"cvmx_lmc#_ddr2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1367, 18, 1192},
|
|
{"cvmx_lmc#_delay_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1368, 6, 1210},
|
|
{"cvmx_lmc#_dual_memcfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1369, 5, 1216},
|
|
{"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 1370, 5, 1221},
|
|
{"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1371, 6, 1226},
|
|
{"cvmx_lmc#_ifb_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1372, 2, 1232},
|
|
{"cvmx_lmc#_ifb_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1373, 2, 1234},
|
|
{"cvmx_lmc#_mem_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 1374, 14, 1236},
|
|
{"cvmx_lmc#_mem_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 1375, 9, 1250},
|
|
{"cvmx_lmc#_nxm" , CVMX_CSR_DB_TYPE_RSL, 64, 1376, 2, 1259},
|
|
{"cvmx_lmc#_ops_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1377, 2, 1261},
|
|
{"cvmx_lmc#_ops_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1378, 2, 1263},
|
|
{"cvmx_lmc#_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1379, 12, 1265},
|
|
{"cvmx_lmc#_pll_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1380, 6, 1277},
|
|
{"cvmx_lmc#_rodt_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1381, 6, 1283},
|
|
{"cvmx_lmc#_rodt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1382, 9, 1289},
|
|
{"cvmx_lmc#_wodt_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 1383, 9, 1298},
|
|
{"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 1384, 4, 1307},
|
|
{"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1385, 3, 1311},
|
|
{"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1386, 3, 1314},
|
|
{"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1387, 3, 1317},
|
|
{"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1388, 5, 1320},
|
|
{"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1390, 1, 1325},
|
|
{"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1391, 10, 1326},
|
|
{"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 1399, 13, 1336},
|
|
{"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1407, 4, 1349},
|
|
{"cvmx_mio_fus_bnk_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 1408, 1, 1353},
|
|
{"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 1412, 2, 1354},
|
|
{"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 1413, 2, 1356},
|
|
{"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 1414, 9, 1358},
|
|
{"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 1415, 8, 1367},
|
|
{"cvmx_mio_fus_ema" , CVMX_CSR_DB_TYPE_RSL, 64, 1416, 2, 1375},
|
|
{"cvmx_mio_fus_pdf" , CVMX_CSR_DB_TYPE_RSL, 64, 1417, 1, 1377},
|
|
{"cvmx_mio_fus_pll" , CVMX_CSR_DB_TYPE_RSL, 64, 1418, 3, 1378},
|
|
{"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 1419, 2, 1381},
|
|
{"cvmx_mio_fus_prog_times" , CVMX_CSR_DB_TYPE_RSL, 64, 1420, 6, 1383},
|
|
{"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1421, 8, 1389},
|
|
{"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 1422, 4, 1397},
|
|
{"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1423, 2, 1401},
|
|
{"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1424, 2, 1403},
|
|
{"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1425, 13, 1405},
|
|
{"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 1426, 12, 1418},
|
|
{"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 1427, 3, 1430},
|
|
{"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 1428, 3, 1433},
|
|
{"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 1429, 2, 1436},
|
|
{"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 1431, 2, 1438},
|
|
{"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 1433, 2, 1440},
|
|
{"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1435, 7, 1442},
|
|
{"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 1437, 2, 1449},
|
|
{"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 1439, 7, 1451},
|
|
{"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 1441, 4, 1458},
|
|
{"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1443, 8, 1462},
|
|
{"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 1445, 9, 1470},
|
|
{"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1447, 7, 1479},
|
|
{"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 1449, 9, 1486},
|
|
{"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 1451, 2, 1495},
|
|
{"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1453, 2, 1497},
|
|
{"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 1455, 4, 1499},
|
|
{"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1457, 2, 1503},
|
|
{"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 1459, 2, 1505},
|
|
{"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 1461, 2, 1507},
|
|
{"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 1463, 4, 1509},
|
|
{"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 1465, 2, 1513},
|
|
{"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 1467, 2, 1515},
|
|
{"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 1469, 2, 1517},
|
|
{"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1471, 2, 1519},
|
|
{"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 1473, 2, 1521},
|
|
{"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1475, 2, 1523},
|
|
{"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 1477, 6, 1525},
|
|
{"cvmx_npi_base_addr_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 1479, 2, 1531},
|
|
{"cvmx_npi_base_addr_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1483, 2, 1533},
|
|
{"cvmx_npi_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1487, 21, 1535},
|
|
{"cvmx_npi_buff_size_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1488, 3, 1556},
|
|
{"cvmx_npi_comp_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1492, 3, 1559},
|
|
{"cvmx_npi_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1493, 21, 1562},
|
|
{"cvmx_npi_dbg_select" , CVMX_CSR_DB_TYPE_NCB, 64, 1494, 2, 1583},
|
|
{"cvmx_npi_dma_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1495, 13, 1585},
|
|
{"cvmx_npi_dma_highp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 1496, 3, 1598},
|
|
{"cvmx_npi_dma_highp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1497, 3, 1601},
|
|
{"cvmx_npi_dma_lowp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 1498, 3, 1604},
|
|
{"cvmx_npi_dma_lowp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1499, 3, 1607},
|
|
{"cvmx_npi_highp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 1500, 2, 1610},
|
|
{"cvmx_npi_highp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1501, 2, 1612},
|
|
{"cvmx_npi_input_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1502, 10, 1614},
|
|
{"cvmx_npi_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 1503, 63, 1624},
|
|
{"cvmx_npi_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 1504, 63, 1687},
|
|
{"cvmx_npi_lowp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 1505, 2, 1750},
|
|
{"cvmx_npi_lowp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 1506, 2, 1752},
|
|
{"cvmx_npi_mem_access_subid#" , CVMX_CSR_DB_TYPE_NCB, 64, 1507, 10, 1754},
|
|
{"cvmx_npi_msi_rcv" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1511, 1, 1764},
|
|
{"cvmx_npi_num_desc_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 1512, 2, 1765},
|
|
{"cvmx_npi_output_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1516, 39, 1767},
|
|
{"cvmx_npi_p#_dbpair_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 1517, 3, 1806},
|
|
{"cvmx_npi_p#_instr_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 1521, 2, 1809},
|
|
{"cvmx_npi_p#_instr_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 1525, 3, 1811},
|
|
{"cvmx_npi_p#_pair_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 1529, 3, 1814},
|
|
{"cvmx_npi_pci_burst_size" , CVMX_CSR_DB_TYPE_NCB, 64, 1533, 3, 1817},
|
|
{"cvmx_npi_pci_int_arb_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 1534, 7, 1820},
|
|
{"cvmx_npi_pci_read_cmd" , CVMX_CSR_DB_TYPE_NCB, 64, 1535, 2, 1827},
|
|
{"cvmx_npi_port32_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1536, 13, 1829},
|
|
{"cvmx_npi_port33_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1537, 13, 1842},
|
|
{"cvmx_npi_port34_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1538, 13, 1855},
|
|
{"cvmx_npi_port35_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 1539, 13, 1868},
|
|
{"cvmx_npi_port_bp_control" , CVMX_CSR_DB_TYPE_NCB, 64, 1540, 3, 1881},
|
|
{"cvmx_npi_rsl_int_blocks" , CVMX_CSR_DB_TYPE_NCB, 64, 1541, 33, 1884},
|
|
{"cvmx_npi_size_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 1542, 2, 1917},
|
|
{"cvmx_npi_win_read_to" , CVMX_CSR_DB_TYPE_NCB, 64, 1546, 2, 1919},
|
|
{"cvmx_pci_bar1_index#" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1547, 5, 1921},
|
|
{"cvmx_pci_cfg00" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1579, 2, 1926},
|
|
{"cvmx_pci_cfg01" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1580, 24, 1928},
|
|
{"cvmx_pci_cfg02" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1581, 2, 1952},
|
|
{"cvmx_pci_cfg03" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1582, 7, 1954},
|
|
{"cvmx_pci_cfg04" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1583, 5, 1961},
|
|
{"cvmx_pci_cfg05" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1584, 1, 1966},
|
|
{"cvmx_pci_cfg06" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1585, 5, 1967},
|
|
{"cvmx_pci_cfg07" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1586, 1, 1972},
|
|
{"cvmx_pci_cfg08" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1587, 4, 1973},
|
|
{"cvmx_pci_cfg09" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1588, 2, 1977},
|
|
{"cvmx_pci_cfg10" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1589, 1, 1979},
|
|
{"cvmx_pci_cfg11" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1590, 2, 1980},
|
|
{"cvmx_pci_cfg12" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1591, 4, 1982},
|
|
{"cvmx_pci_cfg13" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1592, 2, 1986},
|
|
{"cvmx_pci_cfg15" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1593, 4, 1988},
|
|
{"cvmx_pci_cfg16" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1594, 16, 1992},
|
|
{"cvmx_pci_cfg17" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1595, 1, 2008},
|
|
{"cvmx_pci_cfg18" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1596, 1, 2009},
|
|
{"cvmx_pci_cfg19" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1597, 18, 2010},
|
|
{"cvmx_pci_cfg20" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1598, 1, 2028},
|
|
{"cvmx_pci_cfg21" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1599, 1, 2029},
|
|
{"cvmx_pci_cfg22" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1600, 7, 2030},
|
|
{"cvmx_pci_cfg56" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1601, 7, 2037},
|
|
{"cvmx_pci_cfg57" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1602, 13, 2044},
|
|
{"cvmx_pci_cfg58" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1603, 10, 2057},
|
|
{"cvmx_pci_cfg59" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1604, 10, 2067},
|
|
{"cvmx_pci_cfg60" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1605, 7, 2077},
|
|
{"cvmx_pci_cfg61" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1606, 2, 2084},
|
|
{"cvmx_pci_cfg62" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1607, 1, 2086},
|
|
{"cvmx_pci_cfg63" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 1608, 2, 2087},
|
|
{"cvmx_pci_cnt_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1609, 6, 2089},
|
|
{"cvmx_pci_ctl_status_2" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1610, 22, 2095},
|
|
{"cvmx_pci_dbell#" , CVMX_CSR_DB_TYPE_PCI, 32, 1611, 2, 2117},
|
|
{"cvmx_pci_dma_cnt#" , CVMX_CSR_DB_TYPE_PCI, 32, 1615, 1, 2119},
|
|
{"cvmx_pci_dma_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 1617, 1, 2120},
|
|
{"cvmx_pci_dma_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 1619, 1, 2121},
|
|
{"cvmx_pci_instr_count#" , CVMX_CSR_DB_TYPE_PCI, 32, 1621, 1, 2122},
|
|
{"cvmx_pci_int_enb" , CVMX_CSR_DB_TYPE_PCI, 64, 1625, 35, 2123},
|
|
{"cvmx_pci_int_enb2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1626, 35, 2158},
|
|
{"cvmx_pci_int_sum" , CVMX_CSR_DB_TYPE_PCI, 64, 1627, 35, 2193},
|
|
{"cvmx_pci_int_sum2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1628, 35, 2228},
|
|
{"cvmx_pci_msi_rcv" , CVMX_CSR_DB_TYPE_PCI, 32, 1629, 2, 2263},
|
|
{"cvmx_pci_pkt_credits#" , CVMX_CSR_DB_TYPE_PCI, 32, 1630, 2, 2265},
|
|
{"cvmx_pci_pkts_sent#" , CVMX_CSR_DB_TYPE_PCI, 32, 1634, 1, 2267},
|
|
{"cvmx_pci_pkts_sent_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 1638, 1, 2268},
|
|
{"cvmx_pci_pkts_sent_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 1642, 1, 2269},
|
|
{"cvmx_pci_read_cmd_6" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1646, 3, 2270},
|
|
{"cvmx_pci_read_cmd_c" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1647, 3, 2273},
|
|
{"cvmx_pci_read_cmd_e" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 1648, 3, 2276},
|
|
{"cvmx_pci_read_timeout" , CVMX_CSR_DB_TYPE_NCB, 64, 1649, 3, 2279},
|
|
{"cvmx_pci_scm_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1650, 2, 2282},
|
|
{"cvmx_pci_tsr_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 1651, 2, 2284},
|
|
{"cvmx_pci_win_rd_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 1652, 4, 2286},
|
|
{"cvmx_pci_win_rd_data" , CVMX_CSR_DB_TYPE_PCI, 64, 1653, 1, 2290},
|
|
{"cvmx_pci_win_wr_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 1654, 4, 2291},
|
|
{"cvmx_pci_win_wr_data" , CVMX_CSR_DB_TYPE_PCI, 64, 1655, 1, 2295},
|
|
{"cvmx_pci_win_wr_mask" , CVMX_CSR_DB_TYPE_PCI, 64, 1656, 2, 2296},
|
|
{"cvmx_pip_bck_prs" , CVMX_CSR_DB_TYPE_RSL, 64, 1657, 5, 2298},
|
|
{"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1658, 2, 2303},
|
|
{"cvmx_pip_crc_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 1659, 3, 2305},
|
|
{"cvmx_pip_crc_iv#" , CVMX_CSR_DB_TYPE_RSL, 64, 1661, 2, 2308},
|
|
{"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 1663, 4, 2310},
|
|
{"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1667, 8, 2314},
|
|
{"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1668, 16, 2322},
|
|
{"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1669, 12, 2338},
|
|
{"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1670, 12, 2350},
|
|
{"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 1671, 2, 2362},
|
|
{"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1672, 19, 2364},
|
|
{"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 1708, 25, 2383},
|
|
{"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 1744, 2, 2408},
|
|
{"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 1808, 2, 2410},
|
|
{"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 1816, 9, 2412},
|
|
{"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 1820, 2, 2421},
|
|
{"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 1821, 2, 2423},
|
|
{"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1822, 2, 2425},
|
|
{"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1858, 2, 2427},
|
|
{"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1894, 2, 2429},
|
|
{"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1930, 2, 2431},
|
|
{"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1966, 2, 2433},
|
|
{"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2002, 2, 2435},
|
|
{"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2038, 2, 2437},
|
|
{"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2074, 2, 2439},
|
|
{"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2110, 2, 2441},
|
|
{"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2146, 2, 2443},
|
|
{"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2182, 2, 2445},
|
|
{"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 2183, 2, 2447},
|
|
{"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 2219, 2, 2449},
|
|
{"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 2255, 2, 2451},
|
|
{"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 2291, 2, 2453},
|
|
{"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2355, 2, 2455},
|
|
{"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 2356, 3, 2457},
|
|
{"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 2357, 3, 2460},
|
|
{"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 2358, 2, 2463},
|
|
{"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 2359, 2, 2465},
|
|
{"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2360, 4, 2467},
|
|
{"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2361, 5, 2471},
|
|
{"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 2362, 4, 2476},
|
|
{"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 2363, 8, 2480},
|
|
{"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 2364, 4, 2488},
|
|
{"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 2365, 5, 2492},
|
|
{"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2366, 5, 2497},
|
|
{"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2367, 1, 2502},
|
|
{"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 2368, 18, 2503},
|
|
{"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 2369, 4, 2521},
|
|
{"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 2370, 2, 2525},
|
|
{"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 2371, 6, 2527},
|
|
{"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 2372, 7, 2533},
|
|
{"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 2373, 4, 2540},
|
|
{"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 2374, 9, 2544},
|
|
{"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 2375, 5, 2553},
|
|
{"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2376, 15, 2558},
|
|
{"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2377, 4, 2573},
|
|
{"cvmx_pko_reg_crc_ctl#" , CVMX_CSR_DB_TYPE_RSL, 64, 2378, 3, 2577},
|
|
{"cvmx_pko_reg_crc_enable" , CVMX_CSR_DB_TYPE_RSL, 64, 2380, 2, 2580},
|
|
{"cvmx_pko_reg_crc_iv#" , CVMX_CSR_DB_TYPE_RSL, 64, 2381, 2, 2582},
|
|
{"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2383, 1, 2584},
|
|
{"cvmx_pko_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2384, 1, 2585},
|
|
{"cvmx_pko_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2385, 1, 2586},
|
|
{"cvmx_pko_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2386, 1, 2587},
|
|
{"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2387, 4, 2588},
|
|
{"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2388, 5, 2592},
|
|
{"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2389, 3, 2597},
|
|
{"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2390, 4, 2600},
|
|
{"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2391, 2, 2604},
|
|
{"cvmx_pko_reg_queue_ptrs1" , CVMX_CSR_DB_TYPE_RSL, 64, 2392, 3, 2606},
|
|
{"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2393, 3, 2609},
|
|
{"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 2394, 13, 2612},
|
|
{"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2395, 2, 2625},
|
|
{"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 2396, 13, 2627},
|
|
{"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 2397, 3, 2640},
|
|
{"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2398, 2, 2643},
|
|
{"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2406, 2, 2645},
|
|
{"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2407, 2, 2647},
|
|
{"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 2408, 2, 2649},
|
|
{"cvmx_pow_pf_rst_msk" , CVMX_CSR_DB_TYPE_NCB, 64, 2409, 2, 2651},
|
|
{"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 2410, 10, 2653},
|
|
{"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 2426, 5, 2663},
|
|
{"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2434, 8, 2668},
|
|
{"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2442, 2, 2676},
|
|
{"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2443, 2, 2678},
|
|
{"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2444, 2, 2680},
|
|
{"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 2452, 3, 2682},
|
|
{"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2453, 4, 2685},
|
|
{"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2469, 5, 2689},
|
|
{"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2470, 7, 2694},
|
|
{"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2486, 2, 2701},
|
|
{"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2502, 3, 2703},
|
|
{"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2503, 7, 2706},
|
|
{"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 2504, 8, 2713},
|
|
{"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2505, 6, 2721},
|
|
{"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2506, 2, 2727},
|
|
{"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2507, 4, 2729},
|
|
{"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2508, 4, 2733},
|
|
{"cvmx_spx#_bckprs_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2509, 2, 2737},
|
|
{"cvmx_spx#_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2511, 4, 2739},
|
|
{"cvmx_spx#_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2513, 11, 2743},
|
|
{"cvmx_spx#_clk_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2515, 9, 2754},
|
|
{"cvmx_spx#_dbg_deskew_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2517, 16, 2763},
|
|
{"cvmx_spx#_dbg_deskew_state" , CVMX_CSR_DB_TYPE_RSL, 64, 2519, 5, 2779},
|
|
{"cvmx_spx#_drv_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2521, 5, 2784},
|
|
{"cvmx_spx#_err_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2523, 6, 2789},
|
|
{"cvmx_spx#_int_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2525, 6, 2795},
|
|
{"cvmx_spx#_int_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2527, 12, 2801},
|
|
{"cvmx_spx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2529, 14, 2813},
|
|
{"cvmx_spx#_int_sync" , CVMX_CSR_DB_TYPE_RSL, 64, 2531, 12, 2827},
|
|
{"cvmx_spx#_tpa_acc" , CVMX_CSR_DB_TYPE_RSL, 64, 2533, 2, 2839},
|
|
{"cvmx_spx#_tpa_max" , CVMX_CSR_DB_TYPE_RSL, 64, 2535, 2, 2841},
|
|
{"cvmx_spx#_tpa_sel" , CVMX_CSR_DB_TYPE_RSL, 64, 2537, 2, 2843},
|
|
{"cvmx_spx#_trn4_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2539, 8, 2845},
|
|
{"cvmx_srx#_com_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2541, 5, 2853},
|
|
{"cvmx_srx#_ign_rx_full" , CVMX_CSR_DB_TYPE_RSL, 64, 2543, 2, 2858},
|
|
{"cvmx_srx#_spi4_cal#" , CVMX_CSR_DB_TYPE_RSL, 64, 2545, 6, 2860},
|
|
{"cvmx_srx#_spi4_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2609, 4, 2866},
|
|
{"cvmx_srx#_sw_tick_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2611, 6, 2870},
|
|
{"cvmx_srx#_sw_tick_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2613, 1, 2876},
|
|
{"cvmx_stx#_arb_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2615, 5, 2877},
|
|
{"cvmx_stx#_bckprs_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2617, 2, 2882},
|
|
{"cvmx_stx#_com_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2619, 4, 2884},
|
|
{"cvmx_stx#_dip_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 2621, 3, 2888},
|
|
{"cvmx_stx#_ign_cal" , CVMX_CSR_DB_TYPE_RSL, 64, 2623, 2, 2891},
|
|
{"cvmx_stx#_int_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2625, 9, 2893},
|
|
{"cvmx_stx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2627, 10, 2902},
|
|
{"cvmx_stx#_int_sync" , CVMX_CSR_DB_TYPE_RSL, 64, 2629, 9, 2912},
|
|
{"cvmx_stx#_min_bst" , CVMX_CSR_DB_TYPE_RSL, 64, 2631, 2, 2921},
|
|
{"cvmx_stx#_spi4_cal#" , CVMX_CSR_DB_TYPE_RSL, 64, 2633, 6, 2923},
|
|
{"cvmx_stx#_spi4_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2697, 3, 2929},
|
|
{"cvmx_stx#_spi4_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 2699, 4, 2932},
|
|
{"cvmx_stx#_stat_bytes_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 2701, 2, 2936},
|
|
{"cvmx_stx#_stat_bytes_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 2703, 2, 2938},
|
|
{"cvmx_stx#_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2705, 3, 2940},
|
|
{"cvmx_stx#_stat_pkt_xmt" , CVMX_CSR_DB_TYPE_RSL, 64, 2707, 2, 2943},
|
|
{"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2709, 6, 2945},
|
|
{"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2710, 3, 2951},
|
|
{"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2711, 5, 2954},
|
|
{"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 2712, 4, 2959},
|
|
{"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 2713, 6, 2963},
|
|
{"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2714, 4, 2969},
|
|
{"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2715, 2, 2973},
|
|
{"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2716, 4, 2975},
|
|
{"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2717, 2, 2979},
|
|
{"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2718, 3, 2981},
|
|
{"cvmx_tra_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2719, 4, 2984},
|
|
{"cvmx_tra_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2720, 12, 2988},
|
|
{"cvmx_tra_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 2721, 3, 3000},
|
|
{"cvmx_tra_cycles_since1" , CVMX_CSR_DB_TYPE_RSL, 64, 2722, 5, 3003},
|
|
{"cvmx_tra_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2723, 2, 3008},
|
|
{"cvmx_tra_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2724, 2, 3010},
|
|
{"cvmx_tra_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2725, 18, 3012},
|
|
{"cvmx_tra_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2726, 12, 3030},
|
|
{"cvmx_tra_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2727, 6, 3042},
|
|
{"cvmx_tra_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2728, 5, 3048},
|
|
{"cvmx_tra_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2729, 1, 3053},
|
|
{"cvmx_tra_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2730, 2, 3054},
|
|
{"cvmx_tra_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2731, 2, 3056},
|
|
{"cvmx_tra_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2732, 18, 3058},
|
|
{"cvmx_tra_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2733, 12, 3076},
|
|
{"cvmx_tra_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2734, 6, 3088},
|
|
{"cvmx_tra_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2735, 2, 3094},
|
|
{"cvmx_tra_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2736, 2, 3096},
|
|
{"cvmx_tra_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2737, 18, 3098},
|
|
{"cvmx_tra_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2738, 12, 3116},
|
|
{"cvmx_tra_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2739, 6, 3128},
|
|
{"cvmx_zip_cmd_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2740, 3, 3134},
|
|
{"cvmx_zip_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2741, 5, 3137},
|
|
{"cvmx_zip_cmd_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2742, 3, 3142},
|
|
{"cvmx_zip_constants" , CVMX_CSR_DB_TYPE_RSL, 64, 2743, 6, 3145},
|
|
{"cvmx_zip_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2744, 2, 3151},
|
|
{"cvmx_zip_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2745, 2, 3153},
|
|
{"cvmx_zip_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2746, 2, 3155},
|
|
{NULL,0,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
|
|
/* name , --------------address, ---------------type, bits, csr offset */
|
|
{"ASX0_INT_EN" , 0x11800B0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
|
|
{"ASX1_INT_EN" , 0x11800B8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
|
|
{"ASX0_INT_REG" , 0x11800B0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
|
|
{"ASX1_INT_REG" , 0x11800B8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
|
|
{"ASX0_PRT_LOOP" , 0x11800B0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
|
|
{"ASX1_PRT_LOOP" , 0x11800B8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
|
|
{"ASX0_RLD_BYPASS" , 0x11800B0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
|
|
{"ASX1_RLD_BYPASS" , 0x11800B8000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
|
|
{"ASX0_RLD_BYPASS_SETTING" , 0x11800B0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
|
|
{"ASX1_RLD_BYPASS_SETTING" , 0x11800B8000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
|
|
{"ASX0_RLD_COMP" , 0x11800B0000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
|
|
{"ASX1_RLD_COMP" , 0x11800B8000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
|
|
{"ASX0_RLD_DATA_DRV" , 0x11800B0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
|
|
{"ASX1_RLD_DATA_DRV" , 0x11800B8000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
|
|
{"ASX0_RLD_NCTL_STRONG" , 0x11800B0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
|
|
{"ASX1_RLD_NCTL_STRONG" , 0x11800B8000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
|
|
{"ASX0_RLD_NCTL_WEAK" , 0x11800B0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
|
|
{"ASX1_RLD_NCTL_WEAK" , 0x11800B8000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
|
|
{"ASX0_RLD_PCTL_STRONG" , 0x11800B0000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
|
|
{"ASX1_RLD_PCTL_STRONG" , 0x11800B8000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
|
|
{"ASX0_RLD_PCTL_WEAK" , 0x11800B0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
|
|
{"ASX1_RLD_PCTL_WEAK" , 0x11800B8000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
|
|
{"ASX0_RLD_SETTING" , 0x11800B0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
|
|
{"ASX1_RLD_SETTING" , 0x11800B8000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
|
|
{"ASX0_RX_CLK_SET000" , 0x11800B0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"ASX0_RX_CLK_SET001" , 0x11800B0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"ASX0_RX_CLK_SET002" , 0x11800B0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"ASX0_RX_CLK_SET003" , 0x11800B0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"ASX1_RX_CLK_SET000" , 0x11800B8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"ASX1_RX_CLK_SET001" , 0x11800B8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"ASX1_RX_CLK_SET002" , 0x11800B8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"ASX1_RX_CLK_SET003" , 0x11800B8000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"ASX0_RX_PRT_EN" , 0x11800B0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"ASX1_RX_PRT_EN" , 0x11800B8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"ASX0_TX_CLK_SET000" , 0x11800B0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"ASX0_TX_CLK_SET001" , 0x11800B0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"ASX0_TX_CLK_SET002" , 0x11800B0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"ASX0_TX_CLK_SET003" , 0x11800B0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"ASX1_TX_CLK_SET000" , 0x11800B8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"ASX1_TX_CLK_SET001" , 0x11800B8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"ASX1_TX_CLK_SET002" , 0x11800B8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"ASX1_TX_CLK_SET003" , 0x11800B8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"ASX0_TX_COMP_BYP" , 0x11800B0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
|
|
{"ASX1_TX_COMP_BYP" , 0x11800B8000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
|
|
{"ASX0_TX_HI_WATER000" , 0x11800B0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"ASX0_TX_HI_WATER001" , 0x11800B0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"ASX0_TX_HI_WATER002" , 0x11800B0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"ASX0_TX_HI_WATER003" , 0x11800B0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"ASX1_TX_HI_WATER000" , 0x11800B8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"ASX1_TX_HI_WATER001" , 0x11800B8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"ASX1_TX_HI_WATER002" , 0x11800B8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"ASX1_TX_HI_WATER003" , 0x11800B8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"ASX0_TX_PRT_EN" , 0x11800B0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
|
|
{"ASX1_TX_PRT_EN" , 0x11800B8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
|
|
{"ASX0_DBG_DATA_DRV" , 0x11800B0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
|
|
{"ASX0_DBG_DATA_ENABLE" , 0x11800B0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
|
|
{"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
|
|
{"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 21},
|
|
{"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 22},
|
|
{"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 23},
|
|
{"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT4_EN0" , 0x1070000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT5_EN0" , 0x1070000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT6_EN0" , 0x1070000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT7_EN0" , 0x1070000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT8_EN0" , 0x1070000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT9_EN0" , 0x1070000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT10_EN0" , 0x10700000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT11_EN0" , 0x10700000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT12_EN0" , 0x10700000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT13_EN0" , 0x10700000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT14_EN0" , 0x10700000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT15_EN0" , 0x10700000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT16_EN0" , 0x1070000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT17_EN0" , 0x1070000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT18_EN0" , 0x1070000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT19_EN0" , 0x1070000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT20_EN0" , 0x1070000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT21_EN0" , 0x1070000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT22_EN0" , 0x1070000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT23_EN0" , 0x1070000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT24_EN0" , 0x1070000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT25_EN0" , 0x1070000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT26_EN0" , 0x10700000003A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT27_EN0" , 0x10700000003B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT28_EN0" , 0x10700000003C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT29_EN0" , 0x10700000003D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT30_EN0" , 0x10700000003E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT31_EN0" , 0x10700000003F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_INT0_EN0_W1C" , 0x1070000002200ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT1_EN0_W1C" , 0x1070000002210ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT2_EN0_W1C" , 0x1070000002220ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT3_EN0_W1C" , 0x1070000002230ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT4_EN0_W1C" , 0x1070000002240ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT5_EN0_W1C" , 0x1070000002250ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT6_EN0_W1C" , 0x1070000002260ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT7_EN0_W1C" , 0x1070000002270ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT8_EN0_W1C" , 0x1070000002280ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT9_EN0_W1C" , 0x1070000002290ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT10_EN0_W1C" , 0x10700000022A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT11_EN0_W1C" , 0x10700000022B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT12_EN0_W1C" , 0x10700000022C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT13_EN0_W1C" , 0x10700000022D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT14_EN0_W1C" , 0x10700000022E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT15_EN0_W1C" , 0x10700000022F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT16_EN0_W1C" , 0x1070000002300ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT17_EN0_W1C" , 0x1070000002310ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT18_EN0_W1C" , 0x1070000002320ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT19_EN0_W1C" , 0x1070000002330ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT20_EN0_W1C" , 0x1070000002340ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT21_EN0_W1C" , 0x1070000002350ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT22_EN0_W1C" , 0x1070000002360ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT23_EN0_W1C" , 0x1070000002370ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT24_EN0_W1C" , 0x1070000002380ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT25_EN0_W1C" , 0x1070000002390ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT26_EN0_W1C" , 0x10700000023A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT27_EN0_W1C" , 0x10700000023B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT28_EN0_W1C" , 0x10700000023C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT29_EN0_W1C" , 0x10700000023D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT30_EN0_W1C" , 0x10700000023E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT31_EN0_W1C" , 0x10700000023F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT32_EN0_W1C" , 0x1070000002400ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_INT0_EN0_W1S" , 0x1070000006200ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT1_EN0_W1S" , 0x1070000006210ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT2_EN0_W1S" , 0x1070000006220ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT3_EN0_W1S" , 0x1070000006230ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT4_EN0_W1S" , 0x1070000006240ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT5_EN0_W1S" , 0x1070000006250ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT6_EN0_W1S" , 0x1070000006260ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT7_EN0_W1S" , 0x1070000006270ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT8_EN0_W1S" , 0x1070000006280ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT9_EN0_W1S" , 0x1070000006290ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT10_EN0_W1S" , 0x10700000062A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT11_EN0_W1S" , 0x10700000062B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT12_EN0_W1S" , 0x10700000062C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT13_EN0_W1S" , 0x10700000062D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT14_EN0_W1S" , 0x10700000062E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT15_EN0_W1S" , 0x10700000062F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT16_EN0_W1S" , 0x1070000006300ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT17_EN0_W1S" , 0x1070000006310ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT18_EN0_W1S" , 0x1070000006320ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT19_EN0_W1S" , 0x1070000006330ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT20_EN0_W1S" , 0x1070000006340ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT21_EN0_W1S" , 0x1070000006350ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT22_EN0_W1S" , 0x1070000006360ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT23_EN0_W1S" , 0x1070000006370ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT24_EN0_W1S" , 0x1070000006380ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT25_EN0_W1S" , 0x1070000006390ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT26_EN0_W1S" , 0x10700000063A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT27_EN0_W1S" , 0x10700000063B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT28_EN0_W1S" , 0x10700000063C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT29_EN0_W1S" , 0x10700000063D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT30_EN0_W1S" , 0x10700000063E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT31_EN0_W1S" , 0x10700000063F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT32_EN0_W1S" , 0x1070000006400ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT4_EN1" , 0x1070000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT5_EN1" , 0x1070000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT6_EN1" , 0x1070000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT7_EN1" , 0x1070000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT8_EN1" , 0x1070000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT9_EN1" , 0x1070000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT10_EN1" , 0x10700000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT11_EN1" , 0x10700000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT12_EN1" , 0x10700000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT13_EN1" , 0x10700000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT14_EN1" , 0x10700000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT15_EN1" , 0x10700000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT16_EN1" , 0x1070000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT17_EN1" , 0x1070000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT18_EN1" , 0x1070000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT19_EN1" , 0x1070000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT20_EN1" , 0x1070000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT21_EN1" , 0x1070000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT22_EN1" , 0x1070000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT23_EN1" , 0x1070000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT24_EN1" , 0x1070000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT25_EN1" , 0x1070000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT26_EN1" , 0x10700000003A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT27_EN1" , 0x10700000003B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT28_EN1" , 0x10700000003C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT29_EN1" , 0x10700000003D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT30_EN1" , 0x10700000003E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT31_EN1" , 0x10700000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_INT0_EN1_W1C" , 0x1070000002208ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT1_EN1_W1C" , 0x1070000002218ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT2_EN1_W1C" , 0x1070000002228ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT3_EN1_W1C" , 0x1070000002238ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT4_EN1_W1C" , 0x1070000002248ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT5_EN1_W1C" , 0x1070000002258ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT6_EN1_W1C" , 0x1070000002268ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT7_EN1_W1C" , 0x1070000002278ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT8_EN1_W1C" , 0x1070000002288ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT9_EN1_W1C" , 0x1070000002298ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT10_EN1_W1C" , 0x10700000022A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT11_EN1_W1C" , 0x10700000022B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT12_EN1_W1C" , 0x10700000022C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT13_EN1_W1C" , 0x10700000022D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT14_EN1_W1C" , 0x10700000022E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT15_EN1_W1C" , 0x10700000022F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT16_EN1_W1C" , 0x1070000002308ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT17_EN1_W1C" , 0x1070000002318ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT18_EN1_W1C" , 0x1070000002328ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT19_EN1_W1C" , 0x1070000002338ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT20_EN1_W1C" , 0x1070000002348ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT21_EN1_W1C" , 0x1070000002358ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT22_EN1_W1C" , 0x1070000002368ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT23_EN1_W1C" , 0x1070000002378ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT24_EN1_W1C" , 0x1070000002388ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT25_EN1_W1C" , 0x1070000002398ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT26_EN1_W1C" , 0x10700000023A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT27_EN1_W1C" , 0x10700000023B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT28_EN1_W1C" , 0x10700000023C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT29_EN1_W1C" , 0x10700000023D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT30_EN1_W1C" , 0x10700000023E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT31_EN1_W1C" , 0x10700000023F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT32_EN1_W1C" , 0x1070000002408ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_INT0_EN1_W1S" , 0x1070000006208ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT1_EN1_W1S" , 0x1070000006218ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT2_EN1_W1S" , 0x1070000006228ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT3_EN1_W1S" , 0x1070000006238ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT4_EN1_W1S" , 0x1070000006248ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT5_EN1_W1S" , 0x1070000006258ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT6_EN1_W1S" , 0x1070000006268ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT7_EN1_W1S" , 0x1070000006278ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT8_EN1_W1S" , 0x1070000006288ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT9_EN1_W1S" , 0x1070000006298ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT10_EN1_W1S" , 0x10700000062A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT11_EN1_W1S" , 0x10700000062B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT12_EN1_W1S" , 0x10700000062C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT13_EN1_W1S" , 0x10700000062D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT14_EN1_W1S" , 0x10700000062E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT15_EN1_W1S" , 0x10700000062F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT16_EN1_W1S" , 0x1070000006308ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT17_EN1_W1S" , 0x1070000006318ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT18_EN1_W1S" , 0x1070000006328ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT19_EN1_W1S" , 0x1070000006338ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT20_EN1_W1S" , 0x1070000006348ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT21_EN1_W1S" , 0x1070000006358ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT22_EN1_W1S" , 0x1070000006368ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT23_EN1_W1S" , 0x1070000006378ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT24_EN1_W1S" , 0x1070000006388ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT25_EN1_W1S" , 0x1070000006398ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT26_EN1_W1S" , 0x10700000063A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT27_EN1_W1S" , 0x10700000063B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT28_EN1_W1S" , 0x10700000063C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT29_EN1_W1S" , 0x10700000063D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT30_EN1_W1S" , 0x10700000063E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT31_EN1_W1S" , 0x10700000063F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT32_EN1_W1S" , 0x1070000006408ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_INT0_EN4_0" , 0x1070000000C80ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT1_EN4_0" , 0x1070000000C90ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT2_EN4_0" , 0x1070000000CA0ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT3_EN4_0" , 0x1070000000CB0ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT4_EN4_0" , 0x1070000000CC0ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT5_EN4_0" , 0x1070000000CD0ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT6_EN4_0" , 0x1070000000CE0ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT7_EN4_0" , 0x1070000000CF0ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT8_EN4_0" , 0x1070000000D00ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT9_EN4_0" , 0x1070000000D10ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT10_EN4_0" , 0x1070000000D20ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT11_EN4_0" , 0x1070000000D30ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT12_EN4_0" , 0x1070000000D40ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT13_EN4_0" , 0x1070000000D50ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT14_EN4_0" , 0x1070000000D60ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT15_EN4_0" , 0x1070000000D70ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_INT0_EN4_0_W1C" , 0x1070000002C80ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT1_EN4_0_W1C" , 0x1070000002C90ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT2_EN4_0_W1C" , 0x1070000002CA0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT3_EN4_0_W1C" , 0x1070000002CB0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT4_EN4_0_W1C" , 0x1070000002CC0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT5_EN4_0_W1C" , 0x1070000002CD0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT6_EN4_0_W1C" , 0x1070000002CE0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT7_EN4_0_W1C" , 0x1070000002CF0ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT8_EN4_0_W1C" , 0x1070000002D00ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT9_EN4_0_W1C" , 0x1070000002D10ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT10_EN4_0_W1C" , 0x1070000002D20ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT11_EN4_0_W1C" , 0x1070000002D30ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT12_EN4_0_W1C" , 0x1070000002D40ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT13_EN4_0_W1C" , 0x1070000002D50ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT14_EN4_0_W1C" , 0x1070000002D60ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT15_EN4_0_W1C" , 0x1070000002D70ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_INT0_EN4_0_W1S" , 0x1070000006C80ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_INT1_EN4_0_W1S" , 0x1070000006C90ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_INT2_EN4_0_W1S" , 0x1070000006CA0ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_INT3_EN4_0_W1S" , 0x1070000006CB0ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_INT4_EN4_0_W1S" , 0x1070000006CC0ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_INT5_EN4_0_W1S" , 0x1070000006CD0ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_INT6_EN4_0_W1S" , 0x1070000006CE0ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_INT7_EN4_0_W1S" , 0x1070000006CF0ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_INT8_EN4_0_W1S" , 0x1070000006D00ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_INT9_EN4_0_W1S" , 0x1070000006D10ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_INT10_EN4_0_W1S" , 0x1070000006D20ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_INT11_EN4_0_W1S" , 0x1070000006D30ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_INT12_EN4_0_W1S" , 0x1070000006D40ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_INT13_EN4_0_W1S" , 0x1070000006D50ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_INT14_EN4_0_W1S" , 0x1070000006D60ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_INT15_EN4_0_W1S" , 0x1070000006D70ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_INT0_EN4_1" , 0x1070000000C88ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_INT1_EN4_1" , 0x1070000000C98ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_INT2_EN4_1" , 0x1070000000CA8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_INT3_EN4_1" , 0x1070000000CB8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_INT4_EN4_1" , 0x1070000000CC8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_INT5_EN4_1" , 0x1070000000CD8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_INT6_EN4_1" , 0x1070000000CE8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_INT7_EN4_1" , 0x1070000000CF8ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_INT8_EN4_1" , 0x1070000000D08ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_INT9_EN4_1" , 0x1070000000D18ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_INT10_EN4_1" , 0x1070000000D28ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_INT11_EN4_1" , 0x1070000000D38ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_INT12_EN4_1" , 0x1070000000D48ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_INT13_EN4_1" , 0x1070000000D58ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_INT14_EN4_1" , 0x1070000000D68ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_INT15_EN4_1" , 0x1070000000D78ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_INT0_EN4_1_W1C" , 0x1070000002C88ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_INT1_EN4_1_W1C" , 0x1070000002C98ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_INT2_EN4_1_W1C" , 0x1070000002CA8ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_INT3_EN4_1_W1C" , 0x1070000002CB8ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_INT4_EN4_1_W1C" , 0x1070000002CC8ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_INT5_EN4_1_W1C" , 0x1070000002CD8ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_INT6_EN4_1_W1C" , 0x1070000002CE8ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_INT7_EN4_1_W1C" , 0x1070000002CF8ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_INT8_EN4_1_W1C" , 0x1070000002D08ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_INT9_EN4_1_W1C" , 0x1070000002D18ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_INT10_EN4_1_W1C" , 0x1070000002D28ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_INT11_EN4_1_W1C" , 0x1070000002D38ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_INT12_EN4_1_W1C" , 0x1070000002D48ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_INT13_EN4_1_W1C" , 0x1070000002D58ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_INT14_EN4_1_W1C" , 0x1070000002D68ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_INT15_EN4_1_W1C" , 0x1070000002D78ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_INT0_EN4_1_W1S" , 0x1070000006C88ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
|
|
{"CIU_INT1_EN4_1_W1S" , 0x1070000006C98ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
|
|
{"CIU_INT2_EN4_1_W1S" , 0x1070000006CA8ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
|
|
{"CIU_INT3_EN4_1_W1S" , 0x1070000006CB8ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
|
|
{"CIU_INT4_EN4_1_W1S" , 0x1070000006CC8ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
|
|
{"CIU_INT5_EN4_1_W1S" , 0x1070000006CD8ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
|
|
{"CIU_INT6_EN4_1_W1S" , 0x1070000006CE8ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
|
|
{"CIU_INT7_EN4_1_W1S" , 0x1070000006CF8ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
|
|
{"CIU_INT8_EN4_1_W1S" , 0x1070000006D08ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
|
|
{"CIU_INT9_EN4_1_W1S" , 0x1070000006D18ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
|
|
{"CIU_INT10_EN4_1_W1S" , 0x1070000006D28ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
|
|
{"CIU_INT11_EN4_1_W1S" , 0x1070000006D38ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
|
|
{"CIU_INT12_EN4_1_W1S" , 0x1070000006D48ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
|
|
{"CIU_INT13_EN4_1_W1S" , 0x1070000006D58ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
|
|
{"CIU_INT14_EN4_1_W1S" , 0x1070000006D68ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
|
|
{"CIU_INT15_EN4_1_W1S" , 0x1070000006D78ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
|
|
{"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT4_SUM0" , 0x1070000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT5_SUM0" , 0x1070000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT6_SUM0" , 0x1070000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT7_SUM0" , 0x1070000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT8_SUM0" , 0x1070000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT9_SUM0" , 0x1070000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT10_SUM0" , 0x1070000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT11_SUM0" , 0x1070000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT12_SUM0" , 0x1070000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT13_SUM0" , 0x1070000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT14_SUM0" , 0x1070000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT15_SUM0" , 0x1070000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT16_SUM0" , 0x1070000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT17_SUM0" , 0x1070000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT18_SUM0" , 0x1070000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT19_SUM0" , 0x1070000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT20_SUM0" , 0x10700000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT21_SUM0" , 0x10700000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT22_SUM0" , 0x10700000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT23_SUM0" , 0x10700000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT24_SUM0" , 0x10700000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT25_SUM0" , 0x10700000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT26_SUM0" , 0x10700000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT27_SUM0" , 0x10700000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT28_SUM0" , 0x10700000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT29_SUM0" , 0x10700000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT30_SUM0" , 0x10700000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT31_SUM0" , 0x10700000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 36},
|
|
{"CIU_INT0_SUM4" , 0x1070000000C00ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
|
|
{"CIU_INT1_SUM4" , 0x1070000000C08ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
|
|
{"CIU_INT2_SUM4" , 0x1070000000C10ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
|
|
{"CIU_INT3_SUM4" , 0x1070000000C18ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
|
|
{"CIU_INT4_SUM4" , 0x1070000000C20ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
|
|
{"CIU_INT5_SUM4" , 0x1070000000C28ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
|
|
{"CIU_INT6_SUM4" , 0x1070000000C30ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
|
|
{"CIU_INT7_SUM4" , 0x1070000000C38ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
|
|
{"CIU_INT8_SUM4" , 0x1070000000C40ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
|
|
{"CIU_INT9_SUM4" , 0x1070000000C48ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
|
|
{"CIU_INT10_SUM4" , 0x1070000000C50ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
|
|
{"CIU_INT11_SUM4" , 0x1070000000C58ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
|
|
{"CIU_INT12_SUM4" , 0x1070000000C60ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
|
|
{"CIU_INT13_SUM4" , 0x1070000000C68ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
|
|
{"CIU_INT14_SUM4" , 0x1070000000C70ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
|
|
{"CIU_INT15_SUM4" , 0x1070000000C78ull, CVMX_CSR_DB_TYPE_NCB, 64, 37},
|
|
{"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 38},
|
|
{"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
|
|
{"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
|
|
{"CIU_MBOX_CLR2" , 0x1070000000690ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
|
|
{"CIU_MBOX_CLR3" , 0x1070000000698ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
|
|
{"CIU_MBOX_CLR4" , 0x10700000006A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
|
|
{"CIU_MBOX_CLR5" , 0x10700000006A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
|
|
{"CIU_MBOX_CLR6" , 0x10700000006B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
|
|
{"CIU_MBOX_CLR7" , 0x10700000006B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
|
|
{"CIU_MBOX_CLR8" , 0x10700000006C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
|
|
{"CIU_MBOX_CLR9" , 0x10700000006C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
|
|
{"CIU_MBOX_CLR10" , 0x10700000006D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
|
|
{"CIU_MBOX_CLR11" , 0x10700000006D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
|
|
{"CIU_MBOX_CLR12" , 0x10700000006E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
|
|
{"CIU_MBOX_CLR13" , 0x10700000006E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
|
|
{"CIU_MBOX_CLR14" , 0x10700000006F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
|
|
{"CIU_MBOX_CLR15" , 0x10700000006F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 39},
|
|
{"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
|
|
{"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
|
|
{"CIU_MBOX_SET2" , 0x1070000000610ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
|
|
{"CIU_MBOX_SET3" , 0x1070000000618ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
|
|
{"CIU_MBOX_SET4" , 0x1070000000620ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
|
|
{"CIU_MBOX_SET5" , 0x1070000000628ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
|
|
{"CIU_MBOX_SET6" , 0x1070000000630ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
|
|
{"CIU_MBOX_SET7" , 0x1070000000638ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
|
|
{"CIU_MBOX_SET8" , 0x1070000000640ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
|
|
{"CIU_MBOX_SET9" , 0x1070000000648ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
|
|
{"CIU_MBOX_SET10" , 0x1070000000650ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
|
|
{"CIU_MBOX_SET11" , 0x1070000000658ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
|
|
{"CIU_MBOX_SET12" , 0x1070000000660ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
|
|
{"CIU_MBOX_SET13" , 0x1070000000668ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
|
|
{"CIU_MBOX_SET14" , 0x1070000000670ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
|
|
{"CIU_MBOX_SET15" , 0x1070000000678ull, CVMX_CSR_DB_TYPE_NCB, 64, 40},
|
|
{"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 41},
|
|
{"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 42},
|
|
{"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 43},
|
|
{"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_PP_POKE2" , 0x1070000000590ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_PP_POKE3" , 0x1070000000598ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_PP_POKE4" , 0x10700000005A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_PP_POKE5" , 0x10700000005A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_PP_POKE6" , 0x10700000005B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_PP_POKE7" , 0x10700000005B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_PP_POKE8" , 0x10700000005C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_PP_POKE9" , 0x10700000005C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_PP_POKE10" , 0x10700000005D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_PP_POKE11" , 0x10700000005D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_PP_POKE12" , 0x10700000005E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_PP_POKE13" , 0x10700000005E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_PP_POKE14" , 0x10700000005F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_PP_POKE15" , 0x10700000005F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 44},
|
|
{"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 45},
|
|
{"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 46},
|
|
{"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 47},
|
|
{"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 48},
|
|
{"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 49},
|
|
{"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 49},
|
|
{"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 49},
|
|
{"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 49},
|
|
{"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
|
|
{"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
|
|
{"CIU_WDOG2" , 0x1070000000510ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
|
|
{"CIU_WDOG3" , 0x1070000000518ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
|
|
{"CIU_WDOG4" , 0x1070000000520ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
|
|
{"CIU_WDOG5" , 0x1070000000528ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
|
|
{"CIU_WDOG6" , 0x1070000000530ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
|
|
{"CIU_WDOG7" , 0x1070000000538ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
|
|
{"CIU_WDOG8" , 0x1070000000540ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
|
|
{"CIU_WDOG9" , 0x1070000000548ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
|
|
{"CIU_WDOG10" , 0x1070000000550ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
|
|
{"CIU_WDOG11" , 0x1070000000558ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
|
|
{"CIU_WDOG12" , 0x1070000000560ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
|
|
{"CIU_WDOG13" , 0x1070000000568ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
|
|
{"CIU_WDOG14" , 0x1070000000570ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
|
|
{"CIU_WDOG15" , 0x1070000000578ull, CVMX_CSR_DB_TYPE_NCB, 64, 50},
|
|
{"DBG_DATA" , 0x11F00000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 51},
|
|
{"DFA_BST0" , 0x11800300007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
|
|
{"DFA_BST1" , 0x11800300007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
|
|
{"DFA_CFG" , 0x1180030000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
|
|
{"DFA_DBELL" , 0x1370000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 55},
|
|
{"DFA_DIFCTL" , 0x1370600000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 56},
|
|
{"DFA_DIFRDPTR" , 0x1370200000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 57},
|
|
{"DFA_ERR" , 0x1180030000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
|
|
{"DFA_MEMCFG0" , 0x1180030000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
|
|
{"DFA_MEMCFG1" , 0x1180030000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
|
|
{"DFA_MEMCFG2" , 0x1180030000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
|
|
{"DFA_MEMFADR" , 0x1180030000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
|
|
{"DFA_MEMFCR" , 0x1180030000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
|
|
{"DFA_MEMRLD" , 0x1180030000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
|
|
{"DFA_NCBCTL" , 0x1180030000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
|
|
{"DFA_RODT_COMP_CTL" , 0x1180030000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"DFA_SBD_DBG0" , 0x1180030000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"DFA_SBD_DBG1" , 0x1180030000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
|
|
{"DFA_SBD_DBG2" , 0x1180030000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
|
|
{"DFA_SBD_DBG3" , 0x1180030000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
|
|
{"FPA_BIST_STATUS" , 0x11800280000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
|
|
{"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"FPA_FPF1_MARKS" , 0x1180028000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"FPA_FPF2_MARKS" , 0x1180028000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"FPA_FPF3_MARKS" , 0x1180028000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"FPA_FPF4_MARKS" , 0x1180028000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"FPA_FPF5_MARKS" , 0x1180028000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"FPA_FPF6_MARKS" , 0x1180028000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"FPA_FPF7_MARKS" , 0x1180028000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"FPA_FPF1_SIZE" , 0x1180028000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
|
|
{"FPA_FPF2_SIZE" , 0x1180028000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
|
|
{"FPA_FPF3_SIZE" , 0x1180028000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
|
|
{"FPA_FPF4_SIZE" , 0x1180028000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
|
|
{"FPA_FPF5_SIZE" , 0x1180028000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
|
|
{"FPA_FPF6_SIZE" , 0x1180028000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
|
|
{"FPA_FPF7_SIZE" , 0x1180028000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
|
|
{"FPA_FPF0_MARKS" , 0x1180028000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
|
|
{"FPA_FPF0_SIZE" , 0x1180028000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
|
|
{"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
|
|
{"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
|
|
{"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
|
|
{"FPA_QUE1_AVAILABLE" , 0x11800280000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
|
|
{"FPA_QUE2_AVAILABLE" , 0x11800280000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
|
|
{"FPA_QUE3_AVAILABLE" , 0x11800280000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
|
|
{"FPA_QUE4_AVAILABLE" , 0x11800280000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
|
|
{"FPA_QUE5_AVAILABLE" , 0x11800280000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
|
|
{"FPA_QUE6_AVAILABLE" , 0x11800280000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
|
|
{"FPA_QUE7_AVAILABLE" , 0x11800280000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
|
|
{"FPA_QUE0_PAGE_INDEX" , 0x11800280000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
|
|
{"FPA_QUE1_PAGE_INDEX" , 0x11800280000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
|
|
{"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
|
|
{"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
|
|
{"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
|
|
{"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
|
|
{"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
|
|
{"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
|
|
{"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
|
|
{"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"FPA_WART_CTL" , 0x11800280000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"FPA_WART_STATUS" , 0x11800280000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX1_BAD_REG" , 0x1180010000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX1_BIST" , 0x1180010000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX0_INF_MODE" , 0x11800080007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX1_INF_MODE" , 0x11800100007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX1_NXA_ADR" , 0x1180010000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_PRT003_CFG" , 0x1180008001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX1_PRT000_CFG" , 0x1180010000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX1_PRT001_CFG" , 0x1180010000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX1_PRT002_CFG" , 0x1180010001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX1_PRT003_CFG" , 0x1180010001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_RX003_ADR_CAM0" , 0x1180008001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX1_RX000_ADR_CAM0" , 0x1180010000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX1_RX001_ADR_CAM0" , 0x1180010000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX1_RX002_ADR_CAM0" , 0x1180010001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX1_RX003_ADR_CAM0" , 0x1180010001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_RX003_ADR_CAM1" , 0x1180008001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX1_RX000_ADR_CAM1" , 0x1180010000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX1_RX001_ADR_CAM1" , 0x1180010000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX1_RX002_ADR_CAM1" , 0x1180010001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX1_RX003_ADR_CAM1" , 0x1180010001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_RX003_ADR_CAM2" , 0x1180008001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX1_RX000_ADR_CAM2" , 0x1180010000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX1_RX001_ADR_CAM2" , 0x1180010000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX1_RX002_ADR_CAM2" , 0x1180010001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX1_RX003_ADR_CAM2" , 0x1180010001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_RX003_ADR_CAM3" , 0x1180008001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX1_RX000_ADR_CAM3" , 0x1180010000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX1_RX001_ADR_CAM3" , 0x1180010000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX1_RX002_ADR_CAM3" , 0x1180010001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX1_RX003_ADR_CAM3" , 0x1180010001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_RX000_ADR_CAM4" , 0x11800080001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_RX001_ADR_CAM4" , 0x11800080009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_RX002_ADR_CAM4" , 0x11800080011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_RX003_ADR_CAM4" , 0x11800080019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX1_RX000_ADR_CAM4" , 0x11800100001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX1_RX001_ADR_CAM4" , 0x11800100009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX1_RX002_ADR_CAM4" , 0x11800100011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX1_RX003_ADR_CAM4" , 0x11800100019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_RX000_ADR_CAM5" , 0x11800080001A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_RX001_ADR_CAM5" , 0x11800080009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_RX002_ADR_CAM5" , 0x11800080011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_RX003_ADR_CAM5" , 0x11800080019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX1_RX000_ADR_CAM5" , 0x11800100001A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX1_RX001_ADR_CAM5" , 0x11800100009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX1_RX002_ADR_CAM5" , 0x11800100011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX1_RX003_ADR_CAM5" , 0x11800100019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_RX003_ADR_CAM_EN" , 0x1180008001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX1_RX000_ADR_CAM_EN" , 0x1180010000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX1_RX001_ADR_CAM_EN" , 0x1180010000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX1_RX002_ADR_CAM_EN" , 0x1180010001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX1_RX003_ADR_CAM_EN" , 0x1180010001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_RX003_ADR_CTL" , 0x1180008001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX1_RX000_ADR_CTL" , 0x1180010000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX1_RX001_ADR_CTL" , 0x1180010000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX1_RX002_ADR_CTL" , 0x1180010001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX1_RX003_ADR_CTL" , 0x1180010001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_RX003_DECISION" , 0x1180008001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX1_RX000_DECISION" , 0x1180010000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX1_RX001_DECISION" , 0x1180010000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX1_RX002_DECISION" , 0x1180010001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX1_RX003_DECISION" , 0x1180010001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_RX003_FRM_CHK" , 0x1180008001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX1_RX000_FRM_CHK" , 0x1180010000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX1_RX001_FRM_CHK" , 0x1180010000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX1_RX002_FRM_CHK" , 0x1180010001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX1_RX003_FRM_CHK" , 0x1180010001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_RX003_FRM_CTL" , 0x1180008001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX1_RX000_FRM_CTL" , 0x1180010000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX1_RX001_FRM_CTL" , 0x1180010000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX1_RX002_FRM_CTL" , 0x1180010001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX1_RX003_FRM_CTL" , 0x1180010001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_RX000_FRM_MAX" , 0x1180008000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX0_RX001_FRM_MAX" , 0x1180008000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX0_RX002_FRM_MAX" , 0x1180008001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX0_RX003_FRM_MAX" , 0x1180008001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX1_RX000_FRM_MAX" , 0x1180010000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX1_RX001_FRM_MAX" , 0x1180010000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX1_RX002_FRM_MAX" , 0x1180010001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX1_RX003_FRM_MAX" , 0x1180010001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX0_RX000_FRM_MIN" , 0x1180008000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX0_RX001_FRM_MIN" , 0x1180008000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX0_RX002_FRM_MIN" , 0x1180008001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX0_RX003_FRM_MIN" , 0x1180008001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX1_RX000_FRM_MIN" , 0x1180010000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX1_RX001_FRM_MIN" , 0x1180010000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX1_RX002_FRM_MIN" , 0x1180010001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX1_RX003_FRM_MIN" , 0x1180010001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX0_RX003_IFG" , 0x1180008001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX1_RX000_IFG" , 0x1180010000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX1_RX001_IFG" , 0x1180010000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX1_RX002_IFG" , 0x1180010001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX1_RX003_IFG" , 0x1180010001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_RX003_INT_EN" , 0x1180008001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX1_RX000_INT_EN" , 0x1180010000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX1_RX001_INT_EN" , 0x1180010000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX1_RX002_INT_EN" , 0x1180010001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX1_RX003_INT_EN" , 0x1180010001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX0_RX003_INT_REG" , 0x1180008001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX1_RX000_INT_REG" , 0x1180010000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX1_RX001_INT_REG" , 0x1180010000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX1_RX002_INT_REG" , 0x1180010001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX1_RX003_INT_REG" , 0x1180010001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_RX003_JABBER" , 0x1180008001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX1_RX000_JABBER" , 0x1180010000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX1_RX001_JABBER" , 0x1180010000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX1_RX002_JABBER" , 0x1180010001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX1_RX003_JABBER" , 0x1180010001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_RX000_PAUSE_DROP_TIME" , 0x1180008000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_RX001_PAUSE_DROP_TIME" , 0x1180008000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_RX002_PAUSE_DROP_TIME" , 0x1180008001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_RX003_PAUSE_DROP_TIME" , 0x1180008001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX1_RX000_PAUSE_DROP_TIME" , 0x1180010000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX1_RX001_PAUSE_DROP_TIME" , 0x1180010000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX1_RX002_PAUSE_DROP_TIME" , 0x1180010001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX1_RX003_PAUSE_DROP_TIME" , 0x1180010001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_RX000_RX_INBND" , 0x1180008000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX0_RX001_RX_INBND" , 0x1180008000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX0_RX002_RX_INBND" , 0x1180008001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX0_RX003_RX_INBND" , 0x1180008001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX1_RX000_RX_INBND" , 0x1180010000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX1_RX001_RX_INBND" , 0x1180010000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX1_RX002_RX_INBND" , 0x1180010001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX1_RX003_RX_INBND" , 0x1180010001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_RX003_STATS_CTL" , 0x1180008001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX1_RX000_STATS_CTL" , 0x1180010000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX1_RX001_STATS_CTL" , 0x1180010000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX1_RX002_STATS_CTL" , 0x1180010001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX1_RX003_STATS_CTL" , 0x1180010001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX0_RX003_STATS_OCTS" , 0x1180008001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX1_RX000_STATS_OCTS" , 0x1180010000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX1_RX001_STATS_OCTS" , 0x1180010000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX1_RX002_STATS_OCTS" , 0x1180010001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX1_RX003_STATS_OCTS" , 0x1180010001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX0_RX003_STATS_OCTS_CTL" , 0x1180008001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX1_RX000_STATS_OCTS_CTL" , 0x1180010000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX1_RX001_STATS_OCTS_CTL" , 0x1180010000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX1_RX002_STATS_OCTS_CTL" , 0x1180010001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX1_RX003_STATS_OCTS_CTL" , 0x1180010001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX0_RX003_STATS_OCTS_DMAC" , 0x11800080018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX1_RX000_STATS_OCTS_DMAC" , 0x11800100000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX1_RX001_STATS_OCTS_DMAC" , 0x11800100008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX1_RX002_STATS_OCTS_DMAC" , 0x11800100010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX1_RX003_STATS_OCTS_DMAC" , 0x11800100018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX0_RX003_STATS_OCTS_DRP" , 0x11800080018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX1_RX000_STATS_OCTS_DRP" , 0x11800100000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX1_RX001_STATS_OCTS_DRP" , 0x11800100008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX1_RX002_STATS_OCTS_DRP" , 0x11800100010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX1_RX003_STATS_OCTS_DRP" , 0x11800100018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_RX003_STATS_PKTS" , 0x1180008001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX1_RX000_STATS_PKTS" , 0x1180010000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX1_RX001_STATS_PKTS" , 0x1180010000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX1_RX002_STATS_PKTS" , 0x1180010001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX1_RX003_STATS_PKTS" , 0x1180010001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX0_RX003_STATS_PKTS_BAD" , 0x11800080018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX1_RX000_STATS_PKTS_BAD" , 0x11800100000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX1_RX001_STATS_PKTS_BAD" , 0x11800100008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX1_RX002_STATS_PKTS_BAD" , 0x11800100010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX1_RX003_STATS_PKTS_BAD" , 0x11800100018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX003_STATS_PKTS_CTL" , 0x1180008001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX000_STATS_PKTS_CTL" , 0x1180010000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX001_STATS_PKTS_CTL" , 0x1180010000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX002_STATS_PKTS_CTL" , 0x1180010001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_RX003_STATS_PKTS_CTL" , 0x1180010001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX0_RX003_STATS_PKTS_DMAC" , 0x11800080018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX1_RX000_STATS_PKTS_DMAC" , 0x11800100000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX1_RX001_STATS_PKTS_DMAC" , 0x11800100008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX1_RX002_STATS_PKTS_DMAC" , 0x11800100010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX1_RX003_STATS_PKTS_DMAC" , 0x11800100018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX0_RX003_STATS_PKTS_DRP" , 0x11800080018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX1_RX000_STATS_PKTS_DRP" , 0x11800100000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX1_RX001_STATS_PKTS_DRP" , 0x11800100008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX1_RX002_STATS_PKTS_DRP" , 0x11800100010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX1_RX003_STATS_PKTS_DRP" , 0x11800100018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_RX003_UDD_SKP" , 0x1180008001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX1_RX000_UDD_SKP" , 0x1180010000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX1_RX001_UDD_SKP" , 0x1180010000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX1_RX002_UDD_SKP" , 0x1180010001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX1_RX003_UDD_SKP" , 0x1180010001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX0_RX_BP_DROP003" , 0x1180008000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX1_RX_BP_DROP000" , 0x1180010000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX1_RX_BP_DROP001" , 0x1180010000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX1_RX_BP_DROP002" , 0x1180010000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX1_RX_BP_DROP003" , 0x1180010000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_RX_BP_OFF003" , 0x1180008000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX1_RX_BP_OFF000" , 0x1180010000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX1_RX_BP_OFF001" , 0x1180010000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX1_RX_BP_OFF002" , 0x1180010000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX1_RX_BP_OFF003" , 0x1180010000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_RX_BP_ON003" , 0x1180008000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX1_RX_BP_ON000" , 0x1180010000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX1_RX_BP_ON001" , 0x1180010000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX1_RX_BP_ON002" , 0x1180010000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX1_RX_BP_ON003" , 0x1180010000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_RX_PASS_EN" , 0x11800080005F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX1_RX_PASS_EN" , 0x11800100005F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_RX_PASS_MAP000" , 0x1180008000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX_PASS_MAP001" , 0x1180008000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX_PASS_MAP002" , 0x1180008000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX_PASS_MAP003" , 0x1180008000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX_PASS_MAP004" , 0x1180008000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX_PASS_MAP005" , 0x1180008000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX_PASS_MAP006" , 0x1180008000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX_PASS_MAP007" , 0x1180008000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX_PASS_MAP008" , 0x1180008000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX_PASS_MAP009" , 0x1180008000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX_PASS_MAP010" , 0x1180008000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX_PASS_MAP011" , 0x1180008000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX_PASS_MAP012" , 0x1180008000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX_PASS_MAP013" , 0x1180008000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX_PASS_MAP014" , 0x1180008000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX_PASS_MAP015" , 0x1180008000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_RX_PASS_MAP000" , 0x1180010000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_RX_PASS_MAP001" , 0x1180010000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_RX_PASS_MAP002" , 0x1180010000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_RX_PASS_MAP003" , 0x1180010000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_RX_PASS_MAP004" , 0x1180010000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_RX_PASS_MAP005" , 0x1180010000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_RX_PASS_MAP006" , 0x1180010000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_RX_PASS_MAP007" , 0x1180010000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_RX_PASS_MAP008" , 0x1180010000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_RX_PASS_MAP009" , 0x1180010000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_RX_PASS_MAP010" , 0x1180010000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_RX_PASS_MAP011" , 0x1180010000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_RX_PASS_MAP012" , 0x1180010000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_RX_PASS_MAP013" , 0x1180010000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_RX_PASS_MAP014" , 0x1180010000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_RX_PASS_MAP015" , 0x1180010000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX_PRT_INFO" , 0x11800080004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX1_RX_PRT_INFO" , 0x11800100004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX1_RX_PRTS" , 0x1180010000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_SMAC001" , 0x1180008000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_SMAC003" , 0x1180008001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX1_SMAC000" , 0x1180010000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX1_SMAC001" , 0x1180010000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX1_SMAC002" , 0x1180010001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX1_SMAC003" , 0x1180010001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX1_STAT_BP" , 0x1180010000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_TX001_APPEND" , 0x1180008000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_TX003_APPEND" , 0x1180008001A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX1_TX000_APPEND" , 0x1180010000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX1_TX001_APPEND" , 0x1180010000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX1_TX002_APPEND" , 0x1180010001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX1_TX003_APPEND" , 0x1180010001A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_TX001_BURST" , 0x1180008000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_TX003_BURST" , 0x1180008001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX1_TX000_BURST" , 0x1180010000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX1_TX001_BURST" , 0x1180010000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX1_TX002_BURST" , 0x1180010001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX1_TX003_BURST" , 0x1180010001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_TX000_CLK" , 0x1180008000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_TX001_CLK" , 0x1180008000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_TX002_CLK" , 0x1180008001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_TX003_CLK" , 0x1180008001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX1_TX000_CLK" , 0x1180010000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX1_TX001_CLK" , 0x1180010000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX1_TX002_CLK" , 0x1180010001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX1_TX003_CLK" , 0x1180010001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_TX001_CTL" , 0x1180008000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_TX003_CTL" , 0x1180008001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX1_TX000_CTL" , 0x1180010000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX1_TX001_CTL" , 0x1180010000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX1_TX002_CTL" , 0x1180010001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX1_TX003_CTL" , 0x1180010001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_TX001_MIN_PKT" , 0x1180008000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_TX003_MIN_PKT" , 0x1180008001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX1_TX000_MIN_PKT" , 0x1180010000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX1_TX001_MIN_PKT" , 0x1180010000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX1_TX002_MIN_PKT" , 0x1180010001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX1_TX003_MIN_PKT" , 0x1180010001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_TX003_PAUSE_PKT_INTERVAL", 0x1180008001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX1_TX000_PAUSE_PKT_INTERVAL", 0x1180010000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX1_TX001_PAUSE_PKT_INTERVAL", 0x1180010000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX1_TX002_PAUSE_PKT_INTERVAL", 0x1180010001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX1_TX003_PAUSE_PKT_INTERVAL", 0x1180010001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_TX003_PAUSE_PKT_TIME" , 0x1180008001A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX1_TX000_PAUSE_PKT_TIME" , 0x1180010000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX1_TX001_PAUSE_PKT_TIME" , 0x1180010000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX1_TX002_PAUSE_PKT_TIME" , 0x1180010001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX1_TX003_PAUSE_PKT_TIME" , 0x1180010001A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_TX001_PAUSE_TOGO" , 0x1180008000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_TX003_PAUSE_TOGO" , 0x1180008001A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX1_TX000_PAUSE_TOGO" , 0x1180010000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX1_TX001_PAUSE_TOGO" , 0x1180010000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX1_TX002_PAUSE_TOGO" , 0x1180010001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX1_TX003_PAUSE_TOGO" , 0x1180010001A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_TX001_PAUSE_ZERO" , 0x1180008000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_TX003_PAUSE_ZERO" , 0x1180008001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX1_TX000_PAUSE_ZERO" , 0x1180010000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX1_TX001_PAUSE_ZERO" , 0x1180010000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX1_TX002_PAUSE_ZERO" , 0x1180010001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX1_TX003_PAUSE_ZERO" , 0x1180010001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_TX001_SLOT" , 0x1180008000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_TX003_SLOT" , 0x1180008001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX1_TX000_SLOT" , 0x1180010000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX1_TX001_SLOT" , 0x1180010000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX1_TX002_SLOT" , 0x1180010001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX1_TX003_SLOT" , 0x1180010001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_TX001_SOFT_PAUSE" , 0x1180008000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_TX003_SOFT_PAUSE" , 0x1180008001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX1_TX000_SOFT_PAUSE" , 0x1180010000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX1_TX001_SOFT_PAUSE" , 0x1180010000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX1_TX002_SOFT_PAUSE" , 0x1180010001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX1_TX003_SOFT_PAUSE" , 0x1180010001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_TX001_STAT0" , 0x1180008000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_TX003_STAT0" , 0x1180008001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX1_TX000_STAT0" , 0x1180010000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX1_TX001_STAT0" , 0x1180010000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX1_TX002_STAT0" , 0x1180010001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX1_TX003_STAT0" , 0x1180010001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_TX001_STAT1" , 0x1180008000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_TX003_STAT1" , 0x1180008001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX1_TX000_STAT1" , 0x1180010000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX1_TX001_STAT1" , 0x1180010000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX1_TX002_STAT1" , 0x1180010001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX1_TX003_STAT1" , 0x1180010001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_TX001_STAT2" , 0x1180008000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_TX003_STAT2" , 0x1180008001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX1_TX000_STAT2" , 0x1180010000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX1_TX001_STAT2" , 0x1180010000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX1_TX002_STAT2" , 0x1180010001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX1_TX003_STAT2" , 0x1180010001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_TX001_STAT3" , 0x1180008000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_TX003_STAT3" , 0x1180008001A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX1_TX000_STAT3" , 0x1180010000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX1_TX001_STAT3" , 0x1180010000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX1_TX002_STAT3" , 0x1180010001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX1_TX003_STAT3" , 0x1180010001A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_TX000_STAT4" , 0x11800080002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX0_TX001_STAT4" , 0x1180008000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX0_TX002_STAT4" , 0x11800080012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX0_TX003_STAT4" , 0x1180008001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX1_TX000_STAT4" , 0x11800100002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX1_TX001_STAT4" , 0x1180010000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX1_TX002_STAT4" , 0x11800100012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX1_TX003_STAT4" , 0x1180010001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX0_TX000_STAT5" , 0x11800080002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX0_TX001_STAT5" , 0x1180008000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX0_TX002_STAT5" , 0x11800080012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX0_TX003_STAT5" , 0x1180008001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX1_TX000_STAT5" , 0x11800100002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX1_TX001_STAT5" , 0x1180010000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX1_TX002_STAT5" , 0x11800100012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX1_TX003_STAT5" , 0x1180010001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX0_TX000_STAT6" , 0x11800080002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX0_TX001_STAT6" , 0x1180008000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX0_TX002_STAT6" , 0x11800080012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX0_TX003_STAT6" , 0x1180008001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX1_TX000_STAT6" , 0x11800100002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX1_TX001_STAT6" , 0x1180010000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX1_TX002_STAT6" , 0x11800100012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX1_TX003_STAT6" , 0x1180010001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX0_TX000_STAT7" , 0x11800080002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX0_TX001_STAT7" , 0x1180008000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX0_TX002_STAT7" , 0x11800080012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX0_TX003_STAT7" , 0x1180008001AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX1_TX000_STAT7" , 0x11800100002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX1_TX001_STAT7" , 0x1180010000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX1_TX002_STAT7" , 0x11800100012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX1_TX003_STAT7" , 0x1180010001AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX0_TX000_STAT8" , 0x11800080002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX0_TX001_STAT8" , 0x1180008000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX0_TX002_STAT8" , 0x11800080012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX0_TX003_STAT8" , 0x1180008001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX1_TX000_STAT8" , 0x11800100002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX1_TX001_STAT8" , 0x1180010000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX1_TX002_STAT8" , 0x11800100012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX1_TX003_STAT8" , 0x1180010001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX0_TX000_STAT9" , 0x11800080002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX0_TX001_STAT9" , 0x1180008000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX0_TX002_STAT9" , 0x11800080012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX0_TX003_STAT9" , 0x1180008001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX1_TX000_STAT9" , 0x11800100002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX1_TX001_STAT9" , 0x1180010000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX1_TX002_STAT9" , 0x11800100012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX1_TX003_STAT9" , 0x1180010001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX0_TX001_STATS_CTL" , 0x1180008000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX0_TX003_STATS_CTL" , 0x1180008001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX1_TX000_STATS_CTL" , 0x1180010000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX1_TX001_STATS_CTL" , 0x1180010000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX1_TX002_STATS_CTL" , 0x1180010001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX1_TX003_STATS_CTL" , 0x1180010001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX0_TX001_THRESH" , 0x1180008000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX0_TX003_THRESH" , 0x1180008001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX1_TX000_THRESH" , 0x1180010000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX1_TX001_THRESH" , 0x1180010000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX1_TX002_THRESH" , 0x1180010001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX1_TX003_THRESH" , 0x1180010001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX0_TX_BP" , 0x11800080004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX1_TX_BP" , 0x11800100004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX1_TX_COL_ATTEMPT" , 0x1180010000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX0_TX_CORRUPT" , 0x11800080004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX1_TX_CORRUPT" , 0x11800100004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX1_TX_IFG" , 0x1180010000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX1_TX_INT_EN" , 0x1180010000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX1_TX_INT_REG" , 0x1180010000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
|
|
{"GMX1_TX_JAM" , 0x1180010000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
|
|
{"GMX0_TX_LFSR" , 0x11800080004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX_LFSR" , 0x11800100004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX_OVR_BP" , 0x11800080004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
|
|
{"GMX1_TX_OVR_BP" , 0x11800100004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
|
|
{"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
|
|
{"GMX1_TX_PAUSE_PKT_DMAC" , 0x11800100004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
|
|
{"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
|
|
{"GMX1_TX_PAUSE_PKT_TYPE" , 0x11800100004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
|
|
{"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
|
|
{"GMX1_TX_PRTS" , 0x1180010000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
|
|
{"GMX0_TX_SPI_CTL" , 0x11800080004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
|
|
{"GMX1_TX_SPI_CTL" , 0x11800100004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
|
|
{"GMX0_TX_SPI_DRAIN" , 0x11800080004E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX1_TX_SPI_DRAIN" , 0x11800100004E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX0_TX_SPI_MAX" , 0x11800080004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX1_TX_SPI_MAX" , 0x11800100004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX0_TX_SPI_ROUND000" , 0x1180008000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND001" , 0x1180008000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND002" , 0x1180008000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND003" , 0x1180008000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND004" , 0x11800080006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND005" , 0x11800080006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND006" , 0x11800080006B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND007" , 0x11800080006B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND008" , 0x11800080006C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND009" , 0x11800080006C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND010" , 0x11800080006D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND011" , 0x11800080006D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND012" , 0x11800080006E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND013" , 0x11800080006E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND014" , 0x11800080006F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND015" , 0x11800080006F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND016" , 0x1180008000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND017" , 0x1180008000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND018" , 0x1180008000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND019" , 0x1180008000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND020" , 0x1180008000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND021" , 0x1180008000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND022" , 0x1180008000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND023" , 0x1180008000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND024" , 0x1180008000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND025" , 0x1180008000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND026" , 0x1180008000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND027" , 0x1180008000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND028" , 0x1180008000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND029" , 0x1180008000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND030" , 0x1180008000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_ROUND031" , 0x1180008000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND000" , 0x1180010000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND001" , 0x1180010000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND002" , 0x1180010000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND003" , 0x1180010000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND004" , 0x11800100006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND005" , 0x11800100006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND006" , 0x11800100006B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND007" , 0x11800100006B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND008" , 0x11800100006C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND009" , 0x11800100006C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND010" , 0x11800100006D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND011" , 0x11800100006D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND012" , 0x11800100006E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND013" , 0x11800100006E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND014" , 0x11800100006F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND015" , 0x11800100006F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND016" , 0x1180010000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND017" , 0x1180010000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND018" , 0x1180010000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND019" , 0x1180010000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND020" , 0x1180010000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND021" , 0x1180010000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND022" , 0x1180010000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND023" , 0x1180010000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND024" , 0x1180010000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND025" , 0x1180010000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND026" , 0x1180010000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND027" , 0x1180010000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND028" , 0x1180010000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND029" , 0x1180010000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND030" , 0x1180010000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX_SPI_ROUND031" , 0x1180010000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX_SPI_THRESH" , 0x11800080004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
|
|
{"GMX1_TX_SPI_THRESH" , 0x11800100004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
|
|
{"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
|
|
{"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
|
|
{"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
|
|
{"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
|
|
{"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
|
|
{"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
|
|
{"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
|
|
{"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
|
|
{"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
|
|
{"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
|
|
{"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
|
|
{"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
|
|
{"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
|
|
{"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
|
|
{"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
|
|
{"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
|
|
{"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
|
|
{"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 171},
|
|
{"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 172},
|
|
{"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 173},
|
|
{"IOB_BIST_STATUS" , 0x11800F00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"IOB_CTL_STATUS" , 0x11800F0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"IOB_DWB_PRI_CNT" , 0x11800F0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"IOB_FAU_TIMEOUT" , 0x11800F0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
|
|
{"IOB_I2C_PRI_CNT" , 0x11800F0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
|
|
{"IOB_INB_CONTROL_MATCH" , 0x11800F0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
|
|
{"IOB_INB_CONTROL_MATCH_ENB" , 0x11800F0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
|
|
{"IOB_INB_DATA_MATCH" , 0x11800F0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
|
|
{"IOB_INB_DATA_MATCH_ENB" , 0x11800F0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
|
|
{"IOB_INT_ENB" , 0x11800F0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
|
|
{"IOB_INT_SUM" , 0x11800F0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
|
|
{"IOB_N2C_L2C_PRI_CNT" , 0x11800F0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
|
|
{"IOB_N2C_RSP_PRI_CNT" , 0x11800F0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
|
|
{"IOB_OUTB_COM_PRI_CNT" , 0x11800F0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
|
|
{"IOB_OUTB_CONTROL_MATCH" , 0x11800F0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
|
|
{"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800F00000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
|
|
{"IOB_OUTB_DATA_MATCH" , 0x11800F0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
|
|
{"IOB_OUTB_DATA_MATCH_ENB" , 0x11800F00000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 191},
|
|
{"IOB_OUTB_FPA_PRI_CNT" , 0x11800F0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 192},
|
|
{"IOB_OUTB_REQ_PRI_CNT" , 0x11800F0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 193},
|
|
{"IOB_P2C_REQ_PRI_CNT" , 0x11800F0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 194},
|
|
{"IOB_PKT_ERR" , 0x11800F0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 195},
|
|
{"IPD_1ST_MBUFF_SKIP" , 0x14F0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IPD_1ST_NEXT_PTR_BACK" , 0x14F0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 197},
|
|
{"IPD_2ND_NEXT_PTR_BACK" , 0x14F0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 198},
|
|
{"IPD_BIST_STATUS" , 0x14F00000007F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 199},
|
|
{"IPD_BP_PRT_RED_END" , 0x14F0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 200},
|
|
{"IPD_CLK_COUNT" , 0x14F0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 201},
|
|
{"IPD_CTL_STATUS" , 0x14F0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"IPD_INT_ENB" , 0x14F0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
|
|
{"IPD_INT_SUM" , 0x14F0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
|
|
{"IPD_NOT_1ST_MBUFF_SKIP" , 0x14F0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
|
|
{"IPD_PACKET_MBUFF_SIZE" , 0x14F0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"IPD_PKT_PTR_VALID" , 0x14F0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
|
|
{"IPD_PORT0_BP_PAGE_CNT" , 0x14F0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT1_BP_PAGE_CNT" , 0x14F0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT2_BP_PAGE_CNT" , 0x14F0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT3_BP_PAGE_CNT" , 0x14F0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT4_BP_PAGE_CNT" , 0x14F0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT5_BP_PAGE_CNT" , 0x14F0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT6_BP_PAGE_CNT" , 0x14F0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT7_BP_PAGE_CNT" , 0x14F0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT8_BP_PAGE_CNT" , 0x14F0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT9_BP_PAGE_CNT" , 0x14F0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT10_BP_PAGE_CNT" , 0x14F0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT11_BP_PAGE_CNT" , 0x14F0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT12_BP_PAGE_CNT" , 0x14F0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT13_BP_PAGE_CNT" , 0x14F0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT14_BP_PAGE_CNT" , 0x14F0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT15_BP_PAGE_CNT" , 0x14F00000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT16_BP_PAGE_CNT" , 0x14F00000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT17_BP_PAGE_CNT" , 0x14F00000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT18_BP_PAGE_CNT" , 0x14F00000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT19_BP_PAGE_CNT" , 0x14F00000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT20_BP_PAGE_CNT" , 0x14F00000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT21_BP_PAGE_CNT" , 0x14F00000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT22_BP_PAGE_CNT" , 0x14F00000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT23_BP_PAGE_CNT" , 0x14F00000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT24_BP_PAGE_CNT" , 0x14F00000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT25_BP_PAGE_CNT" , 0x14F00000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT26_BP_PAGE_CNT" , 0x14F00000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT27_BP_PAGE_CNT" , 0x14F0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT28_BP_PAGE_CNT" , 0x14F0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT29_BP_PAGE_CNT" , 0x14F0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT30_BP_PAGE_CNT" , 0x14F0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT31_BP_PAGE_CNT" , 0x14F0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT32_BP_PAGE_CNT" , 0x14F0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT33_BP_PAGE_CNT" , 0x14F0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT34_BP_PAGE_CNT" , 0x14F0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT35_BP_PAGE_CNT" , 0x14F0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14F00000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14F00000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14F00000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR3" , 0x14F00000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR4" , 0x14F00000001D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR5" , 0x14F00000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR6" , 0x14F00000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR7" , 0x14F00000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR8" , 0x14F00000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR9" , 0x14F0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR10" , 0x14F0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR11" , 0x14F0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR12" , 0x14F0000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR13" , 0x14F0000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR14" , 0x14F0000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR15" , 0x14F0000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR16" , 0x14F0000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR17" , 0x14F0000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR18" , 0x14F0000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR19" , 0x14F0000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR20" , 0x14F0000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR21" , 0x14F0000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR22" , 0x14F0000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR23" , 0x14F0000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR24" , 0x14F0000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR25" , 0x14F0000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR26" , 0x14F0000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR27" , 0x14F0000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR28" , 0x14F0000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR29" , 0x14F00000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR30" , 0x14F00000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR31" , 0x14F00000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14F00000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR33" , 0x14F00000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR34" , 0x14F00000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR35" , 0x14F00000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14F0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
|
|
{"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14F0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
|
|
{"IPD_PTR_COUNT" , 0x14F0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 212},
|
|
{"IPD_PWP_PTR_FIFO_CTL" , 0x14F0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 213},
|
|
{"IPD_QOS0_RED_MARKS" , 0x14F0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
|
|
{"IPD_QOS1_RED_MARKS" , 0x14F0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
|
|
{"IPD_QOS2_RED_MARKS" , 0x14F0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
|
|
{"IPD_QOS3_RED_MARKS" , 0x14F0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
|
|
{"IPD_QOS4_RED_MARKS" , 0x14F0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
|
|
{"IPD_QOS5_RED_MARKS" , 0x14F00000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
|
|
{"IPD_QOS6_RED_MARKS" , 0x14F00000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
|
|
{"IPD_QOS7_RED_MARKS" , 0x14F00000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 214},
|
|
{"IPD_QUE0_FREE_PAGE_CNT" , 0x14F0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 215},
|
|
{"IPD_RED_PORT_ENABLE" , 0x14F00000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 216},
|
|
{"IPD_RED_QUE0_PARAM" , 0x14F00000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
|
|
{"IPD_RED_QUE1_PARAM" , 0x14F00000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
|
|
{"IPD_RED_QUE2_PARAM" , 0x14F00000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
|
|
{"IPD_RED_QUE3_PARAM" , 0x14F00000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
|
|
{"IPD_RED_QUE4_PARAM" , 0x14F0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
|
|
{"IPD_RED_QUE5_PARAM" , 0x14F0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
|
|
{"IPD_RED_QUE6_PARAM" , 0x14F0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
|
|
{"IPD_RED_QUE7_PARAM" , 0x14F0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 217},
|
|
{"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14F0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 218},
|
|
{"IPD_SUB_PORT_FCS" , 0x14F0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
|
|
{"IPD_WQE_FPA_QUEUE" , 0x14F0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
|
|
{"IPD_WQE_PTR_VALID" , 0x14F0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
|
|
{"KEY_BIST_REG" , 0x1180020000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
|
|
{"KEY_CTL_STATUS" , 0x1180020000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
|
|
{"KEY_INT_ENB" , 0x1180020000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
|
|
{"KEY_INT_SUM" , 0x1180020000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
|
|
{"L2C_BST0" , 0x11800800007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
|
|
{"L2C_BST1" , 0x11800800007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
|
|
{"L2C_BST2" , 0x11800800007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
|
|
{"L2C_CFG" , 0x1180080000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
|
|
{"L2C_DBG" , 0x1180080000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
|
|
{"L2C_DUT" , 0x1180080000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
|
|
{"L2C_LCKBASE" , 0x1180080000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
|
|
{"L2C_LCKOFF" , 0x1180080000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
|
|
{"L2C_LFB0" , 0x1180080000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
|
|
{"L2C_LFB1" , 0x1180080000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
|
|
{"L2C_LFB2" , 0x1180080000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
|
|
{"L2C_LFB3" , 0x11800800000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
|
|
{"L2C_PFC0" , 0x1180080000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
|
|
{"L2C_PFC1" , 0x11800800000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
|
|
{"L2C_PFC2" , 0x11800800000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
|
|
{"L2C_PFC3" , 0x11800800000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
|
|
{"L2C_PFCTL" , 0x1180080000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
|
|
{"L2C_SPAR0" , 0x1180080000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
|
|
{"L2C_SPAR1" , 0x1180080000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
|
|
{"L2C_SPAR2" , 0x1180080000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
|
|
{"L2C_SPAR3" , 0x1180080000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
|
|
{"L2C_SPAR4" , 0x1180080000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
|
|
{"L2D_BST0" , 0x1180080000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
|
|
{"L2D_BST1" , 0x1180080000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
|
|
{"L2D_BST2" , 0x1180080000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
|
|
{"L2D_BST3" , 0x1180080000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
|
|
{"L2D_ERR" , 0x1180080000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
|
|
{"L2D_FADR" , 0x1180080000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
|
|
{"L2D_FSYN0" , 0x1180080000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
|
|
{"L2D_FSYN1" , 0x1180080000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
|
|
{"L2D_FUS0" , 0x11800800007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
|
|
{"L2D_FUS1" , 0x11800800007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
|
|
{"L2D_FUS2" , 0x11800800007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
|
|
{"L2D_FUS3" , 0x11800800007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
|
|
{"L2T_ERR" , 0x1180080000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
|
|
{"LED_BLINK" , 0x1180000001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
|
|
{"LED_CLK_PHASE" , 0x1180000001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
|
|
{"LED_CYLON" , 0x1180000001AF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
|
|
{"LED_DBG" , 0x1180000001A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
|
|
{"LED_EN" , 0x1180000001A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
|
|
{"LED_POLARITY" , 0x1180000001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
|
|
{"LED_PRT" , 0x1180000001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
|
|
{"LED_PRT_FMT" , 0x1180000001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
|
|
{"LED_PRT_STATUS0" , 0x1180000001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
|
|
{"LED_PRT_STATUS1" , 0x1180000001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
|
|
{"LED_PRT_STATUS2" , 0x1180000001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
|
|
{"LED_PRT_STATUS3" , 0x1180000001A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
|
|
{"LED_PRT_STATUS4" , 0x1180000001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
|
|
{"LED_PRT_STATUS5" , 0x1180000001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
|
|
{"LED_PRT_STATUS6" , 0x1180000001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
|
|
{"LED_PRT_STATUS7" , 0x1180000001AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
|
|
{"LED_UDD_CNT0" , 0x1180000001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
|
|
{"LED_UDD_CNT1" , 0x1180000001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
|
|
{"LED_UDD_DAT0" , 0x1180000001A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
|
|
{"LED_UDD_DAT1" , 0x1180000001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
|
|
{"LED_UDD_DAT_CLR0" , 0x1180000001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
|
|
{"LED_UDD_DAT_CLR1" , 0x1180000001AD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
|
|
{"LED_UDD_DAT_SET0" , 0x1180000001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
|
|
{"LED_UDD_DAT_SET1" , 0x1180000001AD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
|
|
{"LMC0_COMP_CTL" , 0x1180088000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
|
|
{"LMC0_CTL" , 0x1180088000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
|
|
{"LMC0_CTL1" , 0x1180088000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
|
|
{"LMC0_DCLK_CNT_HI" , 0x1180088000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
|
|
{"LMC0_DCLK_CNT_LO" , 0x1180088000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
|
|
{"LMC0_DDR2_CTL" , 0x1180088000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
|
|
{"LMC0_DELAY_CFG" , 0x1180088000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
|
|
{"LMC0_DUAL_MEMCFG" , 0x1180088000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
|
|
{"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
|
|
{"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
|
|
{"LMC0_IFB_CNT_HI" , 0x1180088000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
|
|
{"LMC0_IFB_CNT_LO" , 0x1180088000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
|
|
{"LMC0_MEM_CFG0" , 0x1180088000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
|
|
{"LMC0_MEM_CFG1" , 0x1180088000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
|
|
{"LMC0_NXM" , 0x11800880000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
|
|
{"LMC0_OPS_CNT_HI" , 0x1180088000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
|
|
{"LMC0_OPS_CNT_LO" , 0x1180088000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
|
|
{"LMC0_PLL_CTL" , 0x11800880000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
|
|
{"LMC0_PLL_STATUS" , 0x11800880000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 289},
|
|
{"LMC0_RODT_COMP_CTL" , 0x11800880000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
|
|
{"LMC0_RODT_CTL" , 0x1180088000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
|
|
{"LMC0_WODT_CTL0" , 0x1180088000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
|
|
{"MIO_BOOT_BIST_STAT" , 0x11800000000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
|
|
{"MIO_BOOT_ERR" , 0x11800000000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
|
|
{"MIO_BOOT_INT" , 0x11800000000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
|
|
{"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
|
|
{"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
|
|
{"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
|
|
{"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
|
|
{"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
|
|
{"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
|
|
{"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
|
|
{"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
|
|
{"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
|
|
{"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
|
|
{"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
|
|
{"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
|
|
{"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
|
|
{"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
|
|
{"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
|
|
{"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
|
|
{"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
|
|
{"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
|
|
{"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
|
|
{"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
|
|
{"MIO_BOOT_THR" , 0x11800000000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
|
|
{"MIO_FUS_BNK_DAT0" , 0x1180000001520ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
|
|
{"MIO_FUS_BNK_DAT1" , 0x1180000001528ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
|
|
{"MIO_FUS_BNK_DAT2" , 0x1180000001530ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
|
|
{"MIO_FUS_BNK_DAT3" , 0x1180000001538ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
|
|
{"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
|
|
{"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
|
|
{"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
|
|
{"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
|
|
{"MIO_FUS_EMA" , 0x1180000001550ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
|
|
{"MIO_FUS_PDF" , 0x1180000001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
|
|
{"MIO_FUS_PLL" , 0x1180000001580ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
|
|
{"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
|
|
{"MIO_FUS_PROG_TIMES" , 0x1180000001518ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
|
|
{"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
|
|
{"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
|
|
{"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
|
|
{"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
|
|
{"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
|
|
{"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
|
|
{"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
|
|
{"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
|
|
{"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
|
|
{"MIO_UART1_DLH" , 0x1180000000C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
|
|
{"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
|
|
{"MIO_UART1_DLL" , 0x1180000000C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
|
|
{"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
|
|
{"MIO_UART1_FAR" , 0x1180000000D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
|
|
{"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
|
|
{"MIO_UART1_FCR" , 0x1180000000C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
|
|
{"MIO_UART0_HTX" , 0x1180000000B08ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
|
|
{"MIO_UART1_HTX" , 0x1180000000F08ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
|
|
{"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
|
|
{"MIO_UART1_IER" , 0x1180000000C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
|
|
{"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
|
|
{"MIO_UART1_IIR" , 0x1180000000C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
|
|
{"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
|
|
{"MIO_UART1_LCR" , 0x1180000000C18ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
|
|
{"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 328},
|
|
{"MIO_UART1_LSR" , 0x1180000000C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 328},
|
|
{"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
|
|
{"MIO_UART1_MCR" , 0x1180000000C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
|
|
{"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
|
|
{"MIO_UART1_MSR" , 0x1180000000C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
|
|
{"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 331},
|
|
{"MIO_UART1_RBR" , 0x1180000000C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 331},
|
|
{"MIO_UART0_RFL" , 0x1180000000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
|
|
{"MIO_UART1_RFL" , 0x1180000000E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
|
|
{"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
|
|
{"MIO_UART1_RFW" , 0x1180000000D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
|
|
{"MIO_UART0_SBCR" , 0x1180000000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 334},
|
|
{"MIO_UART1_SBCR" , 0x1180000000E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 334},
|
|
{"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 335},
|
|
{"MIO_UART1_SCR" , 0x1180000000C38ull, CVMX_CSR_DB_TYPE_RSL, 64, 335},
|
|
{"MIO_UART0_SFE" , 0x1180000000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 336},
|
|
{"MIO_UART1_SFE" , 0x1180000000E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 336},
|
|
{"MIO_UART0_SRR" , 0x1180000000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 337},
|
|
{"MIO_UART1_SRR" , 0x1180000000E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 337},
|
|
{"MIO_UART0_SRT" , 0x1180000000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 338},
|
|
{"MIO_UART1_SRT" , 0x1180000000E38ull, CVMX_CSR_DB_TYPE_RSL, 64, 338},
|
|
{"MIO_UART0_SRTS" , 0x1180000000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 339},
|
|
{"MIO_UART1_SRTS" , 0x1180000000E18ull, CVMX_CSR_DB_TYPE_RSL, 64, 339},
|
|
{"MIO_UART0_STT" , 0x1180000000B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 340},
|
|
{"MIO_UART1_STT" , 0x1180000000F00ull, CVMX_CSR_DB_TYPE_RSL, 64, 340},
|
|
{"MIO_UART0_TFL" , 0x1180000000A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 341},
|
|
{"MIO_UART1_TFL" , 0x1180000000E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 341},
|
|
{"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 342},
|
|
{"MIO_UART1_TFR" , 0x1180000000D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 342},
|
|
{"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
|
|
{"MIO_UART1_THR" , 0x1180000000C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
|
|
{"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
|
|
{"MIO_UART1_USR" , 0x1180000000D38ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
|
|
{"NPI_BASE_ADDR_INPUT0" , 0x11F0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
|
|
{"NPI_BASE_ADDR_INPUT1" , 0x11F0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
|
|
{"NPI_BASE_ADDR_INPUT2" , 0x11F0000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
|
|
{"NPI_BASE_ADDR_INPUT3" , 0x11F00000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 345},
|
|
{"NPI_BASE_ADDR_OUTPUT0" , 0x11F00000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 346},
|
|
{"NPI_BASE_ADDR_OUTPUT1" , 0x11F00000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 346},
|
|
{"NPI_BASE_ADDR_OUTPUT2" , 0x11F00000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 346},
|
|
{"NPI_BASE_ADDR_OUTPUT3" , 0x11F00000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 346},
|
|
{"NPI_BIST_STATUS" , 0x11F00000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 347},
|
|
{"NPI_BUFF_SIZE_OUTPUT0" , 0x11F00000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 348},
|
|
{"NPI_BUFF_SIZE_OUTPUT1" , 0x11F00000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 348},
|
|
{"NPI_BUFF_SIZE_OUTPUT2" , 0x11F00000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 348},
|
|
{"NPI_BUFF_SIZE_OUTPUT3" , 0x11F00000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 348},
|
|
{"NPI_COMP_CTL" , 0x11F0000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 349},
|
|
{"NPI_CTL_STATUS" , 0x11F0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 350},
|
|
{"NPI_DBG_SELECT" , 0x11F0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 351},
|
|
{"NPI_DMA_CONTROL" , 0x11F0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 352},
|
|
{"NPI_DMA_HIGHP_COUNTS" , 0x11F0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 353},
|
|
{"NPI_DMA_HIGHP_NADDR" , 0x11F0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 354},
|
|
{"NPI_DMA_LOWP_COUNTS" , 0x11F0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 355},
|
|
{"NPI_DMA_LOWP_NADDR" , 0x11F0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 356},
|
|
{"NPI_HIGHP_DBELL" , 0x11F0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 357},
|
|
{"NPI_HIGHP_IBUFF_SADDR" , 0x11F0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 358},
|
|
{"NPI_INPUT_CONTROL" , 0x11F0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 359},
|
|
{"NPI_INT_ENB" , 0x11F0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 360},
|
|
{"NPI_INT_SUM" , 0x11F0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 361},
|
|
{"NPI_LOWP_DBELL" , 0x11F0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 362},
|
|
{"NPI_LOWP_IBUFF_SADDR" , 0x11F0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 363},
|
|
{"NPI_MEM_ACCESS_SUBID3" , 0x11F0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 364},
|
|
{"NPI_MEM_ACCESS_SUBID4" , 0x11F0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 364},
|
|
{"NPI_MEM_ACCESS_SUBID5" , 0x11F0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 364},
|
|
{"NPI_MEM_ACCESS_SUBID6" , 0x11F0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 364},
|
|
{"NPI_MSI_RCV" , 0x11F0000001190ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 365},
|
|
{"NPI_NUM_DESC_OUTPUT0" , 0x11F0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 366},
|
|
{"NPI_NUM_DESC_OUTPUT1" , 0x11F0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 366},
|
|
{"NPI_NUM_DESC_OUTPUT2" , 0x11F0000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 366},
|
|
{"NPI_NUM_DESC_OUTPUT3" , 0x11F0000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 366},
|
|
{"NPI_OUTPUT_CONTROL" , 0x11F0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 367},
|
|
{"NPI_P0_DBPAIR_ADDR" , 0x11F0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 368},
|
|
{"NPI_P1_DBPAIR_ADDR" , 0x11F0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 368},
|
|
{"NPI_P2_DBPAIR_ADDR" , 0x11F0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 368},
|
|
{"NPI_P3_DBPAIR_ADDR" , 0x11F0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 368},
|
|
{"NPI_P0_INSTR_ADDR" , 0x11F00000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 369},
|
|
{"NPI_P1_INSTR_ADDR" , 0x11F00000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 369},
|
|
{"NPI_P2_INSTR_ADDR" , 0x11F00000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 369},
|
|
{"NPI_P3_INSTR_ADDR" , 0x11F00000001D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 369},
|
|
{"NPI_P0_INSTR_CNTS" , 0x11F00000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 370},
|
|
{"NPI_P1_INSTR_CNTS" , 0x11F00000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 370},
|
|
{"NPI_P2_INSTR_CNTS" , 0x11F00000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 370},
|
|
{"NPI_P3_INSTR_CNTS" , 0x11F00000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 370},
|
|
{"NPI_P0_PAIR_CNTS" , 0x11F0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
|
|
{"NPI_P1_PAIR_CNTS" , 0x11F0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
|
|
{"NPI_P2_PAIR_CNTS" , 0x11F0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
|
|
{"NPI_P3_PAIR_CNTS" , 0x11F0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 371},
|
|
{"NPI_PCI_BURST_SIZE" , 0x11F00000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 372},
|
|
{"NPI_PCI_INT_ARB_CFG" , 0x11F0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 373},
|
|
{"NPI_PCI_READ_CMD" , 0x11F0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 374},
|
|
{"NPI_PORT32_INSTR_HDR" , 0x11F00000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 375},
|
|
{"NPI_PORT33_INSTR_HDR" , 0x11F0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 376},
|
|
{"NPI_PORT34_INSTR_HDR" , 0x11F0000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
|
|
{"NPI_PORT35_INSTR_HDR" , 0x11F0000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
|
|
{"NPI_PORT_BP_CONTROL" , 0x11F00000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 379},
|
|
{"NPI_RSL_INT_BLOCKS" , 0x11F0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 380},
|
|
{"NPI_SIZE_INPUT0" , 0x11F0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
|
|
{"NPI_SIZE_INPUT1" , 0x11F0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
|
|
{"NPI_SIZE_INPUT2" , 0x11F0000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
|
|
{"NPI_SIZE_INPUT3" , 0x11F00000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
|
|
{"NPI_WIN_READ_TO" , 0x11F00000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
|
|
{"PCI_BAR1_INDEX0" , 0x11F0000001100ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX1" , 0x11F0000001104ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX2" , 0x11F0000001108ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX3" , 0x11F000000110Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX4" , 0x11F0000001110ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX5" , 0x11F0000001114ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX6" , 0x11F0000001118ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX7" , 0x11F000000111Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX8" , 0x11F0000001120ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX9" , 0x11F0000001124ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX10" , 0x11F0000001128ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX11" , 0x11F000000112Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX12" , 0x11F0000001130ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX13" , 0x11F0000001134ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX14" , 0x11F0000001138ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX15" , 0x11F000000113Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX16" , 0x11F0000001140ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX17" , 0x11F0000001144ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX18" , 0x11F0000001148ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX19" , 0x11F000000114Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX20" , 0x11F0000001150ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX21" , 0x11F0000001154ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX22" , 0x11F0000001158ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX23" , 0x11F000000115Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX24" , 0x11F0000001160ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX25" , 0x11F0000001164ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX26" , 0x11F0000001168ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX27" , 0x11F000000116Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX28" , 0x11F0000001170ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX29" , 0x11F0000001174ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX30" , 0x11F0000001178ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_BAR1_INDEX31" , 0x11F000000117Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 383},
|
|
{"PCI_CFG00" , 0x11F0000001800ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 384},
|
|
{"PCI_CFG01" , 0x11F0000001804ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 385},
|
|
{"PCI_CFG02" , 0x11F0000001808ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 386},
|
|
{"PCI_CFG03" , 0x11F000000180Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 387},
|
|
{"PCI_CFG04" , 0x11F0000001810ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 388},
|
|
{"PCI_CFG05" , 0x11F0000001814ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 389},
|
|
{"PCI_CFG06" , 0x11F0000001818ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 390},
|
|
{"PCI_CFG07" , 0x11F000000181Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 391},
|
|
{"PCI_CFG08" , 0x11F0000001820ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 392},
|
|
{"PCI_CFG09" , 0x11F0000001824ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 393},
|
|
{"PCI_CFG10" , 0x11F0000001828ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 394},
|
|
{"PCI_CFG11" , 0x11F000000182Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 395},
|
|
{"PCI_CFG12" , 0x11F0000001830ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 396},
|
|
{"PCI_CFG13" , 0x11F0000001834ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 397},
|
|
{"PCI_CFG15" , 0x11F000000183Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 398},
|
|
{"PCI_CFG16" , 0x11F0000001840ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 399},
|
|
{"PCI_CFG17" , 0x11F0000001844ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 400},
|
|
{"PCI_CFG18" , 0x11F0000001848ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 401},
|
|
{"PCI_CFG19" , 0x11F000000184Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 402},
|
|
{"PCI_CFG20" , 0x11F0000001850ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 403},
|
|
{"PCI_CFG21" , 0x11F0000001854ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 404},
|
|
{"PCI_CFG22" , 0x11F0000001858ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 405},
|
|
{"PCI_CFG56" , 0x11F00000018E0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 406},
|
|
{"PCI_CFG57" , 0x11F00000018E4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 407},
|
|
{"PCI_CFG58" , 0x11F00000018E8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 408},
|
|
{"PCI_CFG59" , 0x11F00000018ECull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 409},
|
|
{"PCI_CFG60" , 0x11F00000018F0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 410},
|
|
{"PCI_CFG61" , 0x11F00000018F4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 411},
|
|
{"PCI_CFG62" , 0x11F00000018F8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 412},
|
|
{"PCI_CFG63" , 0x11F00000018FCull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 413},
|
|
{"PCI_CNT_REG" , 0x11F00000011B8ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 414},
|
|
{"PCI_CTL_STATUS_2" , 0x11F000000118Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 415},
|
|
{"PCI_DBELL0" , 0x80ull, CVMX_CSR_DB_TYPE_PCI, 32, 416},
|
|
{"PCI_DBELL1" , 0x88ull, CVMX_CSR_DB_TYPE_PCI, 32, 416},
|
|
{"PCI_DBELL2" , 0x90ull, CVMX_CSR_DB_TYPE_PCI, 32, 416},
|
|
{"PCI_DBELL3" , 0x98ull, CVMX_CSR_DB_TYPE_PCI, 32, 416},
|
|
{"PCI_DMA_CNT0" , 0xA0ull, CVMX_CSR_DB_TYPE_PCI, 32, 417},
|
|
{"PCI_DMA_CNT1" , 0xA8ull, CVMX_CSR_DB_TYPE_PCI, 32, 417},
|
|
{"PCI_DMA_INT_LEV0" , 0xA4ull, CVMX_CSR_DB_TYPE_PCI, 32, 418},
|
|
{"PCI_DMA_INT_LEV1" , 0xACull, CVMX_CSR_DB_TYPE_PCI, 32, 418},
|
|
{"PCI_DMA_TIME0" , 0xB0ull, CVMX_CSR_DB_TYPE_PCI, 32, 419},
|
|
{"PCI_DMA_TIME1" , 0xB4ull, CVMX_CSR_DB_TYPE_PCI, 32, 419},
|
|
{"PCI_INSTR_COUNT0" , 0x84ull, CVMX_CSR_DB_TYPE_PCI, 32, 420},
|
|
{"PCI_INSTR_COUNT1" , 0x8Cull, CVMX_CSR_DB_TYPE_PCI, 32, 420},
|
|
{"PCI_INSTR_COUNT2" , 0x94ull, CVMX_CSR_DB_TYPE_PCI, 32, 420},
|
|
{"PCI_INSTR_COUNT3" , 0x9Cull, CVMX_CSR_DB_TYPE_PCI, 32, 420},
|
|
{"PCI_INT_ENB" , 0x38ull, CVMX_CSR_DB_TYPE_PCI, 64, 421},
|
|
{"PCI_INT_ENB2" , 0x11F00000011A0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 422},
|
|
{"PCI_INT_SUM" , 0x30ull, CVMX_CSR_DB_TYPE_PCI, 64, 423},
|
|
{"PCI_INT_SUM2" , 0x11F0000001198ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 424},
|
|
{"PCI_MSI_RCV" , 0xF0ull, CVMX_CSR_DB_TYPE_PCI, 32, 425},
|
|
{"PCI_PKT_CREDITS0" , 0x44ull, CVMX_CSR_DB_TYPE_PCI, 32, 426},
|
|
{"PCI_PKT_CREDITS1" , 0x54ull, CVMX_CSR_DB_TYPE_PCI, 32, 426},
|
|
{"PCI_PKT_CREDITS2" , 0x64ull, CVMX_CSR_DB_TYPE_PCI, 32, 426},
|
|
{"PCI_PKT_CREDITS3" , 0x74ull, CVMX_CSR_DB_TYPE_PCI, 32, 426},
|
|
{"PCI_PKTS_SENT0" , 0x40ull, CVMX_CSR_DB_TYPE_PCI, 32, 427},
|
|
{"PCI_PKTS_SENT1" , 0x50ull, CVMX_CSR_DB_TYPE_PCI, 32, 427},
|
|
{"PCI_PKTS_SENT2" , 0x60ull, CVMX_CSR_DB_TYPE_PCI, 32, 427},
|
|
{"PCI_PKTS_SENT3" , 0x70ull, CVMX_CSR_DB_TYPE_PCI, 32, 427},
|
|
{"PCI_PKTS_SENT_INT_LEV0" , 0x48ull, CVMX_CSR_DB_TYPE_PCI, 32, 428},
|
|
{"PCI_PKTS_SENT_INT_LEV1" , 0x58ull, CVMX_CSR_DB_TYPE_PCI, 32, 428},
|
|
{"PCI_PKTS_SENT_INT_LEV2" , 0x68ull, CVMX_CSR_DB_TYPE_PCI, 32, 428},
|
|
{"PCI_PKTS_SENT_INT_LEV3" , 0x78ull, CVMX_CSR_DB_TYPE_PCI, 32, 428},
|
|
{"PCI_PKTS_SENT_TIME0" , 0x4Cull, CVMX_CSR_DB_TYPE_PCI, 32, 429},
|
|
{"PCI_PKTS_SENT_TIME1" , 0x5Cull, CVMX_CSR_DB_TYPE_PCI, 32, 429},
|
|
{"PCI_PKTS_SENT_TIME2" , 0x6Cull, CVMX_CSR_DB_TYPE_PCI, 32, 429},
|
|
{"PCI_PKTS_SENT_TIME3" , 0x7Cull, CVMX_CSR_DB_TYPE_PCI, 32, 429},
|
|
{"PCI_READ_CMD_6" , 0x11F0000001180ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 430},
|
|
{"PCI_READ_CMD_C" , 0x11F0000001184ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 431},
|
|
{"PCI_READ_CMD_E" , 0x11F0000001188ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 432},
|
|
{"PCI_READ_TIMEOUT" , 0x11F00000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 433},
|
|
{"PCI_SCM_REG" , 0x11F00000011A8ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 434},
|
|
{"PCI_TSR_REG" , 0x11F00000011B0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 435},
|
|
{"PCI_WIN_RD_ADDR" , 0x8ull, CVMX_CSR_DB_TYPE_PCI, 64, 436},
|
|
{"PCI_WIN_RD_DATA" , 0x20ull, CVMX_CSR_DB_TYPE_PCI, 64, 437},
|
|
{"PCI_WIN_WR_ADDR" , 0x0ull, CVMX_CSR_DB_TYPE_PCI, 64, 438},
|
|
{"PCI_WIN_WR_DATA" , 0x10ull, CVMX_CSR_DB_TYPE_PCI, 64, 439},
|
|
{"PCI_WIN_WR_MASK" , 0x18ull, CVMX_CSR_DB_TYPE_PCI, 64, 440},
|
|
{"PIP_BCK_PRS" , 0x11800A0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PIP_BIST_STATUS" , 0x11800A0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PIP_CRC_CTL0" , 0x11800A0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_CRC_CTL1" , 0x11800A0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PIP_CRC_IV0" , 0x11800A0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_CRC_IV1" , 0x11800A0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PIP_DEC_IPSEC0" , 0x11800A0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_DEC_IPSEC1" , 0x11800A0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_DEC_IPSEC2" , 0x11800A0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_DEC_IPSEC3" , 0x11800A0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PIP_GBL_CFG" , 0x11800A0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PIP_GBL_CTL" , 0x11800A0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
|
|
{"PIP_INT_EN" , 0x11800A0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PIP_INT_REG" , 0x11800A0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PIP_IP_OFFSET" , 0x11800A0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PIP_PRT_CFG0" , 0x11800A0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG1" , 0x11800A0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG2" , 0x11800A0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG3" , 0x11800A0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG4" , 0x11800A0000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG5" , 0x11800A0000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG6" , 0x11800A0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG7" , 0x11800A0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG8" , 0x11800A0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG9" , 0x11800A0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG10" , 0x11800A0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG11" , 0x11800A0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG12" , 0x11800A0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG13" , 0x11800A0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG14" , 0x11800A0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG15" , 0x11800A0000278ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG16" , 0x11800A0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG17" , 0x11800A0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG18" , 0x11800A0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG19" , 0x11800A0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG20" , 0x11800A00002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG21" , 0x11800A00002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG22" , 0x11800A00002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG23" , 0x11800A00002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG24" , 0x11800A00002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG25" , 0x11800A00002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG26" , 0x11800A00002D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG27" , 0x11800A00002D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG28" , 0x11800A00002E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG29" , 0x11800A00002E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG30" , 0x11800A00002F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG31" , 0x11800A00002F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG32" , 0x11800A0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG33" , 0x11800A0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG34" , 0x11800A0000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_CFG35" , 0x11800A0000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PIP_PRT_TAG0" , 0x11800A0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG1" , 0x11800A0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG2" , 0x11800A0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG3" , 0x11800A0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG4" , 0x11800A0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG5" , 0x11800A0000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG6" , 0x11800A0000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG7" , 0x11800A0000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG8" , 0x11800A0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG9" , 0x11800A0000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG10" , 0x11800A0000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG11" , 0x11800A0000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG12" , 0x11800A0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG13" , 0x11800A0000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG14" , 0x11800A0000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG15" , 0x11800A0000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG16" , 0x11800A0000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG17" , 0x11800A0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG18" , 0x11800A0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG19" , 0x11800A0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG20" , 0x11800A00004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG21" , 0x11800A00004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG22" , 0x11800A00004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG23" , 0x11800A00004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG24" , 0x11800A00004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG25" , 0x11800A00004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG26" , 0x11800A00004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG27" , 0x11800A00004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG28" , 0x11800A00004E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG29" , 0x11800A00004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG30" , 0x11800A00004F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG31" , 0x11800A00004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG32" , 0x11800A0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG33" , 0x11800A0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG34" , 0x11800A0000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_PRT_TAG35" , 0x11800A0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PIP_QOS_DIFF0" , 0x11800A0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF1" , 0x11800A0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF2" , 0x11800A0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF3" , 0x11800A0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF4" , 0x11800A0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF5" , 0x11800A0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF6" , 0x11800A0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF7" , 0x11800A0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF8" , 0x11800A0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF9" , 0x11800A0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF10" , 0x11800A0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF11" , 0x11800A0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF12" , 0x11800A0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF13" , 0x11800A0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF14" , 0x11800A0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF15" , 0x11800A0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF16" , 0x11800A0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF17" , 0x11800A0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF18" , 0x11800A0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF19" , 0x11800A0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF20" , 0x11800A00006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF21" , 0x11800A00006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF22" , 0x11800A00006B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF23" , 0x11800A00006B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF24" , 0x11800A00006C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF25" , 0x11800A00006C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF26" , 0x11800A00006D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF27" , 0x11800A00006D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF28" , 0x11800A00006E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF29" , 0x11800A00006E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF30" , 0x11800A00006F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF31" , 0x11800A00006F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF32" , 0x11800A0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF33" , 0x11800A0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF34" , 0x11800A0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF35" , 0x11800A0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF36" , 0x11800A0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF37" , 0x11800A0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF38" , 0x11800A0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF39" , 0x11800A0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF40" , 0x11800A0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF41" , 0x11800A0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF42" , 0x11800A0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF43" , 0x11800A0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF44" , 0x11800A0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF45" , 0x11800A0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF46" , 0x11800A0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF47" , 0x11800A0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF48" , 0x11800A0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF49" , 0x11800A0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF50" , 0x11800A0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF51" , 0x11800A0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF52" , 0x11800A00007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF53" , 0x11800A00007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF54" , 0x11800A00007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF55" , 0x11800A00007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF56" , 0x11800A00007C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF57" , 0x11800A00007C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF58" , 0x11800A00007D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF59" , 0x11800A00007D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF60" , 0x11800A00007E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF61" , 0x11800A00007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF62" , 0x11800A00007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_DIFF63" , 0x11800A00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PIP_QOS_VLAN0" , 0x11800A00000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_QOS_VLAN1" , 0x11800A00000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_QOS_VLAN2" , 0x11800A00000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_QOS_VLAN3" , 0x11800A00000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_QOS_VLAN4" , 0x11800A00000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_QOS_VLAN5" , 0x11800A00000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_QOS_VLAN6" , 0x11800A00000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_QOS_VLAN7" , 0x11800A00000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PIP_QOS_WATCH0" , 0x11800A0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_QOS_WATCH1" , 0x11800A0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_QOS_WATCH2" , 0x11800A0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_QOS_WATCH3" , 0x11800A0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PIP_RAW_WORD" , 0x11800A00000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PIP_SFT_RST" , 0x11800A0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PIP_STAT0_PRT0" , 0x11800A0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT1" , 0x11800A0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT2" , 0x11800A00008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT3" , 0x11800A00008F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT4" , 0x11800A0000940ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT5" , 0x11800A0000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT6" , 0x11800A00009E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT7" , 0x11800A0000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT8" , 0x11800A0000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT9" , 0x11800A0000AD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT10" , 0x11800A0000B20ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT11" , 0x11800A0000B70ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT12" , 0x11800A0000BC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT13" , 0x11800A0000C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT14" , 0x11800A0000C60ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT15" , 0x11800A0000CB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT16" , 0x11800A0000D00ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT17" , 0x11800A0000D50ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT18" , 0x11800A0000DA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT19" , 0x11800A0000DF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT20" , 0x11800A0000E40ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT21" , 0x11800A0000E90ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT22" , 0x11800A0000EE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT23" , 0x11800A0000F30ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT24" , 0x11800A0000F80ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT25" , 0x11800A0000FD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT26" , 0x11800A0001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT27" , 0x11800A0001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT28" , 0x11800A00010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT29" , 0x11800A0001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT30" , 0x11800A0001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT31" , 0x11800A00011B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT32" , 0x11800A0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT33" , 0x11800A0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT34" , 0x11800A00012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT0_PRT35" , 0x11800A00012F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PIP_STAT1_PRT0" , 0x11800A0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT1" , 0x11800A0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT2" , 0x11800A00008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT3" , 0x11800A00008F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT4" , 0x11800A0000948ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT5" , 0x11800A0000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT6" , 0x11800A00009E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT7" , 0x11800A0000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT8" , 0x11800A0000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT9" , 0x11800A0000AD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT10" , 0x11800A0000B28ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT11" , 0x11800A0000B78ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT12" , 0x11800A0000BC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT13" , 0x11800A0000C18ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT14" , 0x11800A0000C68ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT15" , 0x11800A0000CB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT16" , 0x11800A0000D08ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT17" , 0x11800A0000D58ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT18" , 0x11800A0000DA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT19" , 0x11800A0000DF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT20" , 0x11800A0000E48ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT21" , 0x11800A0000E98ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT22" , 0x11800A0000EE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT23" , 0x11800A0000F38ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT24" , 0x11800A0000F88ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT25" , 0x11800A0000FD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT26" , 0x11800A0001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT27" , 0x11800A0001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT28" , 0x11800A00010C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT29" , 0x11800A0001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT30" , 0x11800A0001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT31" , 0x11800A00011B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT32" , 0x11800A0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT33" , 0x11800A0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT34" , 0x11800A00012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT1_PRT35" , 0x11800A00012F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PIP_STAT2_PRT0" , 0x11800A0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT1" , 0x11800A0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT2" , 0x11800A00008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT3" , 0x11800A0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT4" , 0x11800A0000950ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT5" , 0x11800A00009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT6" , 0x11800A00009F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT7" , 0x11800A0000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT8" , 0x11800A0000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT9" , 0x11800A0000AE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT10" , 0x11800A0000B30ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT11" , 0x11800A0000B80ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT12" , 0x11800A0000BD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT13" , 0x11800A0000C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT14" , 0x11800A0000C70ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT15" , 0x11800A0000CC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT16" , 0x11800A0000D10ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT17" , 0x11800A0000D60ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT18" , 0x11800A0000DB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT19" , 0x11800A0000E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT20" , 0x11800A0000E50ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT21" , 0x11800A0000EA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT22" , 0x11800A0000EF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT23" , 0x11800A0000F40ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT24" , 0x11800A0000F90ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT25" , 0x11800A0000FE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT26" , 0x11800A0001030ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT27" , 0x11800A0001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT28" , 0x11800A00010D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT29" , 0x11800A0001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT30" , 0x11800A0001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT31" , 0x11800A00011C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT32" , 0x11800A0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT33" , 0x11800A0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT34" , 0x11800A00012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT2_PRT35" , 0x11800A0001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PIP_STAT3_PRT0" , 0x11800A0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT1" , 0x11800A0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT2" , 0x11800A00008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT3" , 0x11800A0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT4" , 0x11800A0000958ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT5" , 0x11800A00009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT6" , 0x11800A00009F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT7" , 0x11800A0000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT8" , 0x11800A0000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT9" , 0x11800A0000AE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT10" , 0x11800A0000B38ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT11" , 0x11800A0000B88ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT12" , 0x11800A0000BD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT13" , 0x11800A0000C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT14" , 0x11800A0000C78ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT15" , 0x11800A0000CC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT16" , 0x11800A0000D18ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT17" , 0x11800A0000D68ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT18" , 0x11800A0000DB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT19" , 0x11800A0000E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT20" , 0x11800A0000E58ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT21" , 0x11800A0000EA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT22" , 0x11800A0000EF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT23" , 0x11800A0000F48ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT24" , 0x11800A0000F98ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT25" , 0x11800A0000FE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT26" , 0x11800A0001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT27" , 0x11800A0001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT28" , 0x11800A00010D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT29" , 0x11800A0001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT30" , 0x11800A0001178ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT31" , 0x11800A00011C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT32" , 0x11800A0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT33" , 0x11800A0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT34" , 0x11800A00012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT3_PRT35" , 0x11800A0001308ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PIP_STAT4_PRT0" , 0x11800A0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT1" , 0x11800A0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT2" , 0x11800A00008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT3" , 0x11800A0000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT4" , 0x11800A0000960ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT5" , 0x11800A00009B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT6" , 0x11800A0000A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT7" , 0x11800A0000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT8" , 0x11800A0000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT9" , 0x11800A0000AF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT10" , 0x11800A0000B40ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT11" , 0x11800A0000B90ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT12" , 0x11800A0000BE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT13" , 0x11800A0000C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT14" , 0x11800A0000C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT15" , 0x11800A0000CD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT16" , 0x11800A0000D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT17" , 0x11800A0000D70ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT18" , 0x11800A0000DC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT19" , 0x11800A0000E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT20" , 0x11800A0000E60ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT21" , 0x11800A0000EB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT22" , 0x11800A0000F00ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT23" , 0x11800A0000F50ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT24" , 0x11800A0000FA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT25" , 0x11800A0000FF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT26" , 0x11800A0001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT27" , 0x11800A0001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT28" , 0x11800A00010E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT29" , 0x11800A0001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT30" , 0x11800A0001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT31" , 0x11800A00011D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT32" , 0x11800A0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT33" , 0x11800A0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT34" , 0x11800A00012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT4_PRT35" , 0x11800A0001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PIP_STAT5_PRT0" , 0x11800A0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT1" , 0x11800A0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT2" , 0x11800A00008C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT3" , 0x11800A0000918ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT4" , 0x11800A0000968ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT5" , 0x11800A00009B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT6" , 0x11800A0000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT7" , 0x11800A0000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT8" , 0x11800A0000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT9" , 0x11800A0000AF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT10" , 0x11800A0000B48ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT11" , 0x11800A0000B98ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT12" , 0x11800A0000BE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT13" , 0x11800A0000C38ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT14" , 0x11800A0000C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT15" , 0x11800A0000CD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT16" , 0x11800A0000D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT17" , 0x11800A0000D78ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT18" , 0x11800A0000DC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT19" , 0x11800A0000E18ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT20" , 0x11800A0000E68ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT21" , 0x11800A0000EB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT22" , 0x11800A0000F08ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT23" , 0x11800A0000F58ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT24" , 0x11800A0000FA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT25" , 0x11800A0000FF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT26" , 0x11800A0001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT27" , 0x11800A0001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT28" , 0x11800A00010E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT29" , 0x11800A0001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT30" , 0x11800A0001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT31" , 0x11800A00011D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT32" , 0x11800A0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT33" , 0x11800A0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT34" , 0x11800A00012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT5_PRT35" , 0x11800A0001318ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PIP_STAT6_PRT0" , 0x11800A0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT1" , 0x11800A0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT2" , 0x11800A00008D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT3" , 0x11800A0000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT4" , 0x11800A0000970ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT5" , 0x11800A00009C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT6" , 0x11800A0000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT7" , 0x11800A0000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT8" , 0x11800A0000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT9" , 0x11800A0000B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT10" , 0x11800A0000B50ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT11" , 0x11800A0000BA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT12" , 0x11800A0000BF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT13" , 0x11800A0000C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT14" , 0x11800A0000C90ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT15" , 0x11800A0000CE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT16" , 0x11800A0000D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT17" , 0x11800A0000D80ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT18" , 0x11800A0000DD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT19" , 0x11800A0000E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT20" , 0x11800A0000E70ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT21" , 0x11800A0000EC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT22" , 0x11800A0000F10ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT23" , 0x11800A0000F60ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT24" , 0x11800A0000FB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT25" , 0x11800A0001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT26" , 0x11800A0001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT27" , 0x11800A00010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT28" , 0x11800A00010F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT29" , 0x11800A0001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT30" , 0x11800A0001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT31" , 0x11800A00011E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT32" , 0x11800A0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT33" , 0x11800A0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT34" , 0x11800A00012D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT6_PRT35" , 0x11800A0001320ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PIP_STAT7_PRT0" , 0x11800A0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT1" , 0x11800A0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT2" , 0x11800A00008D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT3" , 0x11800A0000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT4" , 0x11800A0000978ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT5" , 0x11800A00009C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT6" , 0x11800A0000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT7" , 0x11800A0000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT8" , 0x11800A0000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT9" , 0x11800A0000B08ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT10" , 0x11800A0000B58ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT11" , 0x11800A0000BA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT12" , 0x11800A0000BF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT13" , 0x11800A0000C48ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT14" , 0x11800A0000C98ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT15" , 0x11800A0000CE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT16" , 0x11800A0000D38ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT17" , 0x11800A0000D88ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT18" , 0x11800A0000DD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT19" , 0x11800A0000E28ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT20" , 0x11800A0000E78ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT21" , 0x11800A0000EC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT22" , 0x11800A0000F18ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT23" , 0x11800A0000F68ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT24" , 0x11800A0000FB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT25" , 0x11800A0001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT26" , 0x11800A0001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT27" , 0x11800A00010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT28" , 0x11800A00010F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT29" , 0x11800A0001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT30" , 0x11800A0001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT31" , 0x11800A00011E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT32" , 0x11800A0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT33" , 0x11800A0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT34" , 0x11800A00012D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT7_PRT35" , 0x11800A0001328ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PIP_STAT8_PRT0" , 0x11800A0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT1" , 0x11800A0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT2" , 0x11800A00008E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT3" , 0x11800A0000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT4" , 0x11800A0000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT5" , 0x11800A00009D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT6" , 0x11800A0000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT7" , 0x11800A0000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT8" , 0x11800A0000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT9" , 0x11800A0000B10ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT10" , 0x11800A0000B60ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT11" , 0x11800A0000BB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT12" , 0x11800A0000C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT13" , 0x11800A0000C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT14" , 0x11800A0000CA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT15" , 0x11800A0000CF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT16" , 0x11800A0000D40ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT17" , 0x11800A0000D90ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT18" , 0x11800A0000DE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT19" , 0x11800A0000E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT20" , 0x11800A0000E80ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT21" , 0x11800A0000ED0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT22" , 0x11800A0000F20ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT23" , 0x11800A0000F70ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT24" , 0x11800A0000FC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT25" , 0x11800A0001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT26" , 0x11800A0001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT27" , 0x11800A00010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT28" , 0x11800A0001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT29" , 0x11800A0001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT30" , 0x11800A00011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT31" , 0x11800A00011F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT32" , 0x11800A0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT33" , 0x11800A0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT34" , 0x11800A00012E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT8_PRT35" , 0x11800A0001330ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PIP_STAT9_PRT0" , 0x11800A0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT1" , 0x11800A0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT2" , 0x11800A00008E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT3" , 0x11800A0000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT4" , 0x11800A0000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT5" , 0x11800A00009D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT6" , 0x11800A0000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT7" , 0x11800A0000A78ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT8" , 0x11800A0000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT9" , 0x11800A0000B18ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT10" , 0x11800A0000B68ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT11" , 0x11800A0000BB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT12" , 0x11800A0000C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT13" , 0x11800A0000C58ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT14" , 0x11800A0000CA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT15" , 0x11800A0000CF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT16" , 0x11800A0000D48ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT17" , 0x11800A0000D98ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT18" , 0x11800A0000DE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT19" , 0x11800A0000E38ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT20" , 0x11800A0000E88ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT21" , 0x11800A0000ED8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT22" , 0x11800A0000F28ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT23" , 0x11800A0000F78ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT24" , 0x11800A0000FC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT25" , 0x11800A0001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT26" , 0x11800A0001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT27" , 0x11800A00010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT28" , 0x11800A0001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT29" , 0x11800A0001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT30" , 0x11800A00011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT31" , 0x11800A00011F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT32" , 0x11800A0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT33" , 0x11800A0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT34" , 0x11800A00012E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT9_PRT35" , 0x11800A0001338ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PIP_STAT_CTL" , 0x11800A0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 468},
|
|
{"PIP_STAT_INB_ERRS0" , 0x11800A0001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS1" , 0x11800A0001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS2" , 0x11800A0001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS3" , 0x11800A0001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS4" , 0x11800A0001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS5" , 0x11800A0001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS6" , 0x11800A0001AD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS7" , 0x11800A0001AF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS8" , 0x11800A0001B10ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS9" , 0x11800A0001B30ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS10" , 0x11800A0001B50ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS11" , 0x11800A0001B70ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS12" , 0x11800A0001B90ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS13" , 0x11800A0001BB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS14" , 0x11800A0001BD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS15" , 0x11800A0001BF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS16" , 0x11800A0001C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS17" , 0x11800A0001C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS18" , 0x11800A0001C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS19" , 0x11800A0001C70ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS20" , 0x11800A0001C90ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS21" , 0x11800A0001CB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS22" , 0x11800A0001CD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS23" , 0x11800A0001CF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS24" , 0x11800A0001D10ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS25" , 0x11800A0001D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS26" , 0x11800A0001D50ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS27" , 0x11800A0001D70ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS28" , 0x11800A0001D90ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS29" , 0x11800A0001DB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS30" , 0x11800A0001DD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS31" , 0x11800A0001DF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS32" , 0x11800A0001E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS33" , 0x11800A0001E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS34" , 0x11800A0001E50ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_ERRS35" , 0x11800A0001E70ull, CVMX_CSR_DB_TYPE_RSL, 64, 469},
|
|
{"PIP_STAT_INB_OCTS0" , 0x11800A0001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS1" , 0x11800A0001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS2" , 0x11800A0001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS3" , 0x11800A0001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS4" , 0x11800A0001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS5" , 0x11800A0001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS6" , 0x11800A0001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS7" , 0x11800A0001AE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS8" , 0x11800A0001B08ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS9" , 0x11800A0001B28ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS10" , 0x11800A0001B48ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS11" , 0x11800A0001B68ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS12" , 0x11800A0001B88ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS13" , 0x11800A0001BA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS14" , 0x11800A0001BC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS15" , 0x11800A0001BE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS16" , 0x11800A0001C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS17" , 0x11800A0001C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS18" , 0x11800A0001C48ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS19" , 0x11800A0001C68ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS20" , 0x11800A0001C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS21" , 0x11800A0001CA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS22" , 0x11800A0001CC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS23" , 0x11800A0001CE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS24" , 0x11800A0001D08ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS25" , 0x11800A0001D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS26" , 0x11800A0001D48ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS27" , 0x11800A0001D68ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS28" , 0x11800A0001D88ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS29" , 0x11800A0001DA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS30" , 0x11800A0001DC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS31" , 0x11800A0001DE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS32" , 0x11800A0001E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS33" , 0x11800A0001E28ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS34" , 0x11800A0001E48ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_OCTS35" , 0x11800A0001E68ull, CVMX_CSR_DB_TYPE_RSL, 64, 470},
|
|
{"PIP_STAT_INB_PKTS0" , 0x11800A0001A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS1" , 0x11800A0001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS2" , 0x11800A0001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS3" , 0x11800A0001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS4" , 0x11800A0001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS5" , 0x11800A0001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS6" , 0x11800A0001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS7" , 0x11800A0001AE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS8" , 0x11800A0001B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS9" , 0x11800A0001B20ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS10" , 0x11800A0001B40ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS11" , 0x11800A0001B60ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS12" , 0x11800A0001B80ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS13" , 0x11800A0001BA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS14" , 0x11800A0001BC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS15" , 0x11800A0001BE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS16" , 0x11800A0001C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS17" , 0x11800A0001C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS18" , 0x11800A0001C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS19" , 0x11800A0001C60ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS20" , 0x11800A0001C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS21" , 0x11800A0001CA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS22" , 0x11800A0001CC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS23" , 0x11800A0001CE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS24" , 0x11800A0001D00ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS25" , 0x11800A0001D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS26" , 0x11800A0001D40ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS27" , 0x11800A0001D60ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS28" , 0x11800A0001D80ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS29" , 0x11800A0001DA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS30" , 0x11800A0001DC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS31" , 0x11800A0001DE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS32" , 0x11800A0001E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS33" , 0x11800A0001E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS34" , 0x11800A0001E40ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_STAT_INB_PKTS35" , 0x11800A0001E60ull, CVMX_CSR_DB_TYPE_RSL, 64, 471},
|
|
{"PIP_TAG_INC0" , 0x11800A0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC1" , 0x11800A0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC2" , 0x11800A0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC3" , 0x11800A0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC4" , 0x11800A0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC5" , 0x11800A0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC6" , 0x11800A0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC7" , 0x11800A0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC8" , 0x11800A0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC9" , 0x11800A0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC10" , 0x11800A0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC11" , 0x11800A0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC12" , 0x11800A0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC13" , 0x11800A0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC14" , 0x11800A0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC15" , 0x11800A0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC16" , 0x11800A0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC17" , 0x11800A0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC18" , 0x11800A0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC19" , 0x11800A0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC20" , 0x11800A00018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC21" , 0x11800A00018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC22" , 0x11800A00018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC23" , 0x11800A00018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC24" , 0x11800A00018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC25" , 0x11800A00018C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC26" , 0x11800A00018D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC27" , 0x11800A00018D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC28" , 0x11800A00018E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC29" , 0x11800A00018E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC30" , 0x11800A00018F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC31" , 0x11800A00018F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC32" , 0x11800A0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC33" , 0x11800A0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC34" , 0x11800A0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC35" , 0x11800A0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC36" , 0x11800A0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC37" , 0x11800A0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC38" , 0x11800A0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC39" , 0x11800A0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC40" , 0x11800A0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC41" , 0x11800A0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC42" , 0x11800A0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC43" , 0x11800A0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC44" , 0x11800A0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC45" , 0x11800A0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC46" , 0x11800A0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC47" , 0x11800A0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC48" , 0x11800A0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC49" , 0x11800A0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC50" , 0x11800A0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC51" , 0x11800A0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC52" , 0x11800A00019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC53" , 0x11800A00019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC54" , 0x11800A00019B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC55" , 0x11800A00019B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC56" , 0x11800A00019C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC57" , 0x11800A00019C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC58" , 0x11800A00019D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC59" , 0x11800A00019D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC60" , 0x11800A00019E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC61" , 0x11800A00019E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC62" , 0x11800A00019F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_INC63" , 0x11800A00019F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 472},
|
|
{"PIP_TAG_MASK" , 0x11800A0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 473},
|
|
{"PIP_TAG_SECRET" , 0x11800A0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 474},
|
|
{"PIP_TODO_ENTRY" , 0x11800A0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 475},
|
|
{"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 476},
|
|
{"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 477},
|
|
{"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 478},
|
|
{"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 479},
|
|
{"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 480},
|
|
{"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 481},
|
|
{"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 482},
|
|
{"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 483},
|
|
{"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 484},
|
|
{"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 485},
|
|
{"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 486},
|
|
{"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 487},
|
|
{"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 488},
|
|
{"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 489},
|
|
{"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 490},
|
|
{"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 491},
|
|
{"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 492},
|
|
{"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 493},
|
|
{"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 494},
|
|
{"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 495},
|
|
{"PKO_REG_CRC_CTL0" , 0x1180050000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
|
|
{"PKO_REG_CRC_CTL1" , 0x1180050000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
|
|
{"PKO_REG_CRC_ENABLE" , 0x1180050000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
|
|
{"PKO_REG_CRC_IV0" , 0x1180050000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
|
|
{"PKO_REG_CRC_IV1" , 0x1180050000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
|
|
{"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
|
|
{"PKO_REG_DEBUG1" , 0x11800500000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
|
|
{"PKO_REG_DEBUG2" , 0x11800500000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
|
|
{"PKO_REG_DEBUG3" , 0x11800500000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
|
|
{"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
|
|
{"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
|
|
{"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
|
|
{"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 506},
|
|
{"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 507},
|
|
{"PKO_REG_QUEUE_PTRS1" , 0x1180050000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 508},
|
|
{"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 509},
|
|
{"POW_BIST_STAT" , 0x16700000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 510},
|
|
{"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 511},
|
|
{"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 512},
|
|
{"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 513},
|
|
{"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
|
|
{"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
|
|
{"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
|
|
{"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
|
|
{"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
|
|
{"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
|
|
{"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
|
|
{"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 514},
|
|
{"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 515},
|
|
{"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 516},
|
|
{"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 517},
|
|
{"POW_PF_RST_MSK" , 0x1670000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 518},
|
|
{"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_PP_GRP_MSK2" , 0x1670000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_PP_GRP_MSK3" , 0x1670000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_PP_GRP_MSK4" , 0x1670000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_PP_GRP_MSK5" , 0x1670000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_PP_GRP_MSK6" , 0x1670000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_PP_GRP_MSK7" , 0x1670000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_PP_GRP_MSK8" , 0x1670000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_PP_GRP_MSK9" , 0x1670000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_PP_GRP_MSK10" , 0x1670000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_PP_GRP_MSK11" , 0x1670000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_PP_GRP_MSK12" , 0x1670000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_PP_GRP_MSK13" , 0x1670000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_PP_GRP_MSK14" , 0x1670000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_PP_GRP_MSK15" , 0x1670000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 519},
|
|
{"POW_QOS_RND0" , 0x16700000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 520},
|
|
{"POW_QOS_RND1" , 0x16700000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 520},
|
|
{"POW_QOS_RND2" , 0x16700000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 520},
|
|
{"POW_QOS_RND3" , 0x16700000001D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 520},
|
|
{"POW_QOS_RND4" , 0x16700000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 520},
|
|
{"POW_QOS_RND5" , 0x16700000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 520},
|
|
{"POW_QOS_RND6" , 0x16700000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 520},
|
|
{"POW_QOS_RND7" , 0x16700000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 520},
|
|
{"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 521},
|
|
{"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 521},
|
|
{"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 521},
|
|
{"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 521},
|
|
{"POW_QOS_THR4" , 0x16700000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 521},
|
|
{"POW_QOS_THR5" , 0x16700000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 521},
|
|
{"POW_QOS_THR6" , 0x16700000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 521},
|
|
{"POW_QOS_THR7" , 0x16700000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 521},
|
|
{"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 522},
|
|
{"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 523},
|
|
{"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 524},
|
|
{"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 524},
|
|
{"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 524},
|
|
{"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 524},
|
|
{"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 524},
|
|
{"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 524},
|
|
{"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 524},
|
|
{"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 524},
|
|
{"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 525},
|
|
{"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
|
|
{"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
|
|
{"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
|
|
{"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
|
|
{"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
|
|
{"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
|
|
{"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
|
|
{"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
|
|
{"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
|
|
{"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
|
|
{"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
|
|
{"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
|
|
{"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
|
|
{"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
|
|
{"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
|
|
{"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 526},
|
|
{"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 527},
|
|
{"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
|
|
{"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
|
|
{"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
|
|
{"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
|
|
{"POW_WQ_INT_THR4" , 0x16700000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
|
|
{"POW_WQ_INT_THR5" , 0x16700000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
|
|
{"POW_WQ_INT_THR6" , 0x16700000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
|
|
{"POW_WQ_INT_THR7" , 0x16700000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
|
|
{"POW_WQ_INT_THR8" , 0x16700000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
|
|
{"POW_WQ_INT_THR9" , 0x16700000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
|
|
{"POW_WQ_INT_THR10" , 0x16700000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
|
|
{"POW_WQ_INT_THR11" , 0x16700000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
|
|
{"POW_WQ_INT_THR12" , 0x16700000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
|
|
{"POW_WQ_INT_THR13" , 0x16700000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
|
|
{"POW_WQ_INT_THR14" , 0x16700000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
|
|
{"POW_WQ_INT_THR15" , 0x16700000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 528},
|
|
{"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
|
|
{"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
|
|
{"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
|
|
{"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
|
|
{"POW_WS_PC4" , 0x16700000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
|
|
{"POW_WS_PC5" , 0x16700000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
|
|
{"POW_WS_PC6" , 0x16700000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
|
|
{"POW_WS_PC7" , 0x16700000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
|
|
{"POW_WS_PC8" , 0x16700000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
|
|
{"POW_WS_PC9" , 0x16700000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
|
|
{"POW_WS_PC10" , 0x16700000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
|
|
{"POW_WS_PC11" , 0x16700000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
|
|
{"POW_WS_PC12" , 0x16700000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
|
|
{"POW_WS_PC13" , 0x16700000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
|
|
{"POW_WS_PC14" , 0x16700000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
|
|
{"POW_WS_PC15" , 0x16700000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 529},
|
|
{"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 530},
|
|
{"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 531},
|
|
{"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 532},
|
|
{"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 533},
|
|
{"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 534},
|
|
{"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 535},
|
|
{"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 536},
|
|
{"SPX0_BCKPRS_CNT" , 0x1180090000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 537},
|
|
{"SPX1_BCKPRS_CNT" , 0x1180098000340ull, CVMX_CSR_DB_TYPE_RSL, 64, 537},
|
|
{"SPX0_BIST_STAT" , 0x11800900007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 538},
|
|
{"SPX1_BIST_STAT" , 0x11800980007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 538},
|
|
{"SPX0_CLK_CTL" , 0x1180090000348ull, CVMX_CSR_DB_TYPE_RSL, 64, 539},
|
|
{"SPX1_CLK_CTL" , 0x1180098000348ull, CVMX_CSR_DB_TYPE_RSL, 64, 539},
|
|
{"SPX0_CLK_STAT" , 0x1180090000350ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
|
|
{"SPX1_CLK_STAT" , 0x1180098000350ull, CVMX_CSR_DB_TYPE_RSL, 64, 540},
|
|
{"SPX0_DBG_DESKEW_CTL" , 0x1180090000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 541},
|
|
{"SPX1_DBG_DESKEW_CTL" , 0x1180098000368ull, CVMX_CSR_DB_TYPE_RSL, 64, 541},
|
|
{"SPX0_DBG_DESKEW_STATE" , 0x1180090000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 542},
|
|
{"SPX1_DBG_DESKEW_STATE" , 0x1180098000370ull, CVMX_CSR_DB_TYPE_RSL, 64, 542},
|
|
{"SPX0_DRV_CTL" , 0x1180090000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 543},
|
|
{"SPX1_DRV_CTL" , 0x1180098000358ull, CVMX_CSR_DB_TYPE_RSL, 64, 543},
|
|
{"SPX0_ERR_CTL" , 0x1180090000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 544},
|
|
{"SPX1_ERR_CTL" , 0x1180098000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 544},
|
|
{"SPX0_INT_DAT" , 0x1180090000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SPX1_INT_DAT" , 0x1180098000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 545},
|
|
{"SPX0_INT_MSK" , 0x1180090000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 546},
|
|
{"SPX1_INT_MSK" , 0x1180098000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 546},
|
|
{"SPX0_INT_REG" , 0x1180090000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 547},
|
|
{"SPX1_INT_REG" , 0x1180098000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 547},
|
|
{"SPX0_INT_SYNC" , 0x1180090000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 548},
|
|
{"SPX1_INT_SYNC" , 0x1180098000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 548},
|
|
{"SPX0_TPA_ACC" , 0x1180090000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 549},
|
|
{"SPX1_TPA_ACC" , 0x1180098000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 549},
|
|
{"SPX0_TPA_MAX" , 0x1180090000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 550},
|
|
{"SPX1_TPA_MAX" , 0x1180098000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 550},
|
|
{"SPX0_TPA_SEL" , 0x1180090000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 551},
|
|
{"SPX1_TPA_SEL" , 0x1180098000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 551},
|
|
{"SPX0_TRN4_CTL" , 0x1180090000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 552},
|
|
{"SPX1_TRN4_CTL" , 0x1180098000360ull, CVMX_CSR_DB_TYPE_RSL, 64, 552},
|
|
{"SRX0_COM_CTL" , 0x1180090000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 553},
|
|
{"SRX1_COM_CTL" , 0x1180098000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 553},
|
|
{"SRX0_IGN_RX_FULL" , 0x1180090000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 554},
|
|
{"SRX1_IGN_RX_FULL" , 0x1180098000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 554},
|
|
{"SRX0_SPI4_CAL000" , 0x1180090000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL001" , 0x1180090000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL002" , 0x1180090000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL003" , 0x1180090000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL004" , 0x1180090000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL005" , 0x1180090000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL006" , 0x1180090000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL007" , 0x1180090000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL008" , 0x1180090000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL009" , 0x1180090000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL010" , 0x1180090000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL011" , 0x1180090000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL012" , 0x1180090000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL013" , 0x1180090000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL014" , 0x1180090000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL015" , 0x1180090000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL016" , 0x1180090000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL017" , 0x1180090000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL018" , 0x1180090000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL019" , 0x1180090000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL020" , 0x11800900000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL021" , 0x11800900000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL022" , 0x11800900000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL023" , 0x11800900000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL024" , 0x11800900000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL025" , 0x11800900000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL026" , 0x11800900000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL027" , 0x11800900000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL028" , 0x11800900000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL029" , 0x11800900000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL030" , 0x11800900000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_CAL031" , 0x11800900000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL000" , 0x1180098000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL001" , 0x1180098000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL002" , 0x1180098000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL003" , 0x1180098000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL004" , 0x1180098000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL005" , 0x1180098000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL006" , 0x1180098000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL007" , 0x1180098000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL008" , 0x1180098000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL009" , 0x1180098000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL010" , 0x1180098000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL011" , 0x1180098000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL012" , 0x1180098000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL013" , 0x1180098000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL014" , 0x1180098000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL015" , 0x1180098000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL016" , 0x1180098000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL017" , 0x1180098000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL018" , 0x1180098000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL019" , 0x1180098000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL020" , 0x11800980000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL021" , 0x11800980000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL022" , 0x11800980000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL023" , 0x11800980000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL024" , 0x11800980000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL025" , 0x11800980000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL026" , 0x11800980000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL027" , 0x11800980000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL028" , 0x11800980000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL029" , 0x11800980000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL030" , 0x11800980000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX1_SPI4_CAL031" , 0x11800980000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 555},
|
|
{"SRX0_SPI4_STAT" , 0x1180090000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 556},
|
|
{"SRX1_SPI4_STAT" , 0x1180098000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 556},
|
|
{"SRX0_SW_TICK_CTL" , 0x1180090000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 557},
|
|
{"SRX1_SW_TICK_CTL" , 0x1180098000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 557},
|
|
{"SRX0_SW_TICK_DAT" , 0x1180090000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"SRX1_SW_TICK_DAT" , 0x1180098000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"STX0_ARB_CTL" , 0x1180090000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 559},
|
|
{"STX1_ARB_CTL" , 0x1180098000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 559},
|
|
{"STX0_BCKPRS_CNT" , 0x1180090000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 560},
|
|
{"STX1_BCKPRS_CNT" , 0x1180098000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 560},
|
|
{"STX0_COM_CTL" , 0x1180090000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 561},
|
|
{"STX1_COM_CTL" , 0x1180098000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 561},
|
|
{"STX0_DIP_CNT" , 0x1180090000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 562},
|
|
{"STX1_DIP_CNT" , 0x1180098000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 562},
|
|
{"STX0_IGN_CAL" , 0x1180090000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 563},
|
|
{"STX1_IGN_CAL" , 0x1180098000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 563},
|
|
{"STX0_INT_MSK" , 0x11800900006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 564},
|
|
{"STX1_INT_MSK" , 0x11800980006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 564},
|
|
{"STX0_INT_REG" , 0x1180090000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 565},
|
|
{"STX1_INT_REG" , 0x1180098000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 565},
|
|
{"STX0_INT_SYNC" , 0x11800900006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 566},
|
|
{"STX1_INT_SYNC" , 0x11800980006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 566},
|
|
{"STX0_MIN_BST" , 0x1180090000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 567},
|
|
{"STX1_MIN_BST" , 0x1180098000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 567},
|
|
{"STX0_SPI4_CAL000" , 0x1180090000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL001" , 0x1180090000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL002" , 0x1180090000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL003" , 0x1180090000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL004" , 0x1180090000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL005" , 0x1180090000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL006" , 0x1180090000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL007" , 0x1180090000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL008" , 0x1180090000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL009" , 0x1180090000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL010" , 0x1180090000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL011" , 0x1180090000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL012" , 0x1180090000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL013" , 0x1180090000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL014" , 0x1180090000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL015" , 0x1180090000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL016" , 0x1180090000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL017" , 0x1180090000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL018" , 0x1180090000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL019" , 0x1180090000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL020" , 0x11800900004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL021" , 0x11800900004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL022" , 0x11800900004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL023" , 0x11800900004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL024" , 0x11800900004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL025" , 0x11800900004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL026" , 0x11800900004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL027" , 0x11800900004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL028" , 0x11800900004E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL029" , 0x11800900004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL030" , 0x11800900004F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_CAL031" , 0x11800900004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL000" , 0x1180098000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL001" , 0x1180098000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL002" , 0x1180098000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL003" , 0x1180098000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL004" , 0x1180098000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL005" , 0x1180098000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL006" , 0x1180098000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL007" , 0x1180098000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL008" , 0x1180098000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL009" , 0x1180098000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL010" , 0x1180098000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL011" , 0x1180098000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL012" , 0x1180098000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL013" , 0x1180098000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL014" , 0x1180098000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL015" , 0x1180098000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL016" , 0x1180098000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL017" , 0x1180098000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL018" , 0x1180098000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL019" , 0x1180098000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL020" , 0x11800980004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL021" , 0x11800980004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL022" , 0x11800980004B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL023" , 0x11800980004B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL024" , 0x11800980004C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL025" , 0x11800980004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL026" , 0x11800980004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL027" , 0x11800980004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL028" , 0x11800980004E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL029" , 0x11800980004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL030" , 0x11800980004F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX1_SPI4_CAL031" , 0x11800980004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 568},
|
|
{"STX0_SPI4_DAT" , 0x1180090000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 569},
|
|
{"STX1_SPI4_DAT" , 0x1180098000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 569},
|
|
{"STX0_SPI4_STAT" , 0x1180090000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 570},
|
|
{"STX1_SPI4_STAT" , 0x1180098000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 570},
|
|
{"STX0_STAT_BYTES_HI" , 0x1180090000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 571},
|
|
{"STX1_STAT_BYTES_HI" , 0x1180098000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 571},
|
|
{"STX0_STAT_BYTES_LO" , 0x1180090000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 572},
|
|
{"STX1_STAT_BYTES_LO" , 0x1180098000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 572},
|
|
{"STX0_STAT_CTL" , 0x1180090000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 573},
|
|
{"STX1_STAT_CTL" , 0x1180098000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 573},
|
|
{"STX0_STAT_PKT_XMT" , 0x1180090000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 574},
|
|
{"STX1_STAT_PKT_XMT" , 0x1180098000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 574},
|
|
{"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 575},
|
|
{"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 576},
|
|
{"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 577},
|
|
{"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 578},
|
|
{"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 579},
|
|
{"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 580},
|
|
{"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 581},
|
|
{"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 582},
|
|
{"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 583},
|
|
{"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 584},
|
|
{"TRA_BIST_STATUS" , 0x11800A8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 585},
|
|
{"TRA_CTL" , 0x11800A8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 586},
|
|
{"TRA_CYCLES_SINCE" , 0x11800A8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 587},
|
|
{"TRA_CYCLES_SINCE1" , 0x11800A8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 588},
|
|
{"TRA_FILT_ADR_ADR" , 0x11800A8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 589},
|
|
{"TRA_FILT_ADR_MSK" , 0x11800A8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 590},
|
|
{"TRA_FILT_CMD" , 0x11800A8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 591},
|
|
{"TRA_FILT_DID" , 0x11800A8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 592},
|
|
{"TRA_FILT_SID" , 0x11800A8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 593},
|
|
{"TRA_INT_STATUS" , 0x11800A8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 594},
|
|
{"TRA_READ_DAT" , 0x11800A8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 595},
|
|
{"TRA_TRIG0_ADR_ADR" , 0x11800A8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 596},
|
|
{"TRA_TRIG0_ADR_MSK" , 0x11800A80000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 597},
|
|
{"TRA_TRIG0_CMD" , 0x11800A8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 598},
|
|
{"TRA_TRIG0_DID" , 0x11800A8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 599},
|
|
{"TRA_TRIG0_SID" , 0x11800A8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 600},
|
|
{"TRA_TRIG1_ADR_ADR" , 0x11800A80000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 601},
|
|
{"TRA_TRIG1_ADR_MSK" , 0x11800A80000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 602},
|
|
{"TRA_TRIG1_CMD" , 0x11800A80000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 603},
|
|
{"TRA_TRIG1_DID" , 0x11800A80000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 604},
|
|
{"TRA_TRIG1_SID" , 0x11800A80000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 605},
|
|
{"ZIP_CMD_BIST_RESULT" , 0x1180038000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 606},
|
|
{"ZIP_CMD_BUF" , 0x1180038000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 607},
|
|
{"ZIP_CMD_CTL" , 0x1180038000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 608},
|
|
{"ZIP_CONSTANTS" , 0x11800380000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 609},
|
|
{"ZIP_DEBUG0" , 0x1180038000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 610},
|
|
{"ZIP_ERROR" , 0x1180038000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 611},
|
|
{"ZIP_INT_MASK" , 0x1180038000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 612},
|
|
{NULL,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xx[] = {
|
|
/* name , bit, width, csr, type, rst un, typ un, reset, typical */
|
|
{"OVRFLW" , 0, 4, 0, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXPOP" , 4, 4, 0, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXPSH" , 8, 4, 0, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_12_63" , 12, 52, 0, "RAZ", 1, 1, 0, 0},
|
|
{"OVRFLW" , 0, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXPOP" , 4, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXPSH" , 8, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 1, "RAZ", 1, 1, 0, 0},
|
|
{"INT_LOOP" , 0, 4, 2, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EXT_LOOP" , 4, 4, 2, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 2, "RAZ", 1, 1, 0, 0},
|
|
{"BYPASS" , 0, 1, 3, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 3, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 4, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 4, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 4, 5, "RO", 0, 1, 0ull, 0},
|
|
{"PCTL" , 4, 5, 5, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_9_63" , 9, 55, 5, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 4, 6, "R/W", 0, 1, 0ull, 0},
|
|
{"PCTL" , 4, 4, 6, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 6, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 5, 7, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 7, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 5, 8, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 8, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL" , 0, 5, 9, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 9, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL" , 0, 5, 10, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 10, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 11, "RO", 1, 1, 0, 0},
|
|
{"DFALOCK" , 5, 1, 11, "RO", 1, 1, 0, 0},
|
|
{"DFALEAD" , 6, 1, 11, "RO", 1, 1, 0, 0},
|
|
{"DFALAG" , 7, 1, 11, "RO", 1, 1, 0, 0},
|
|
{"DFASET" , 8, 5, 11, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_13_63" , 13, 51, 11, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 12, "R/W", 0, 0, 24ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 12, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_EN" , 0, 4, 13, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 13, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 14, "R/W", 0, 0, 24ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 14, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 5, 15, "R/W", 0, 0, 6ull, 6ull},
|
|
{"RESERVED_5_7" , 5, 3, 15, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL" , 8, 5, 15, "R/W", 0, 0, 9ull, 9ull},
|
|
{"RESERVED_13_63" , 13, 51, 15, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 4, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 16, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_EN" , 0, 4, 17, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 17, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 4, 18, "R/W", 0, 1, 15ull, 0},
|
|
{"PCTL" , 4, 5, 18, "R/W", 0, 1, 31ull, 0},
|
|
{"RESERVED_9_63" , 9, 55, 18, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 19, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 19, "RAZ", 1, 1, 0, 0},
|
|
{"BIST" , 0, 4, 20, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 20, "RAZ", 1, 1, 0, 0},
|
|
{"DINT" , 0, 16, 21, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 21, "RAZ", 1, 1, 0, 0},
|
|
{"FUSE" , 0, 16, 22, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_16_63" , 16, 48, 22, "RAZ", 1, 1, 0, 0},
|
|
{"GSTOP" , 0, 1, 23, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 23, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 24, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 24, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 24, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 25, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 25, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 25, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 25, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 25, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 25, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 25, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 25, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 25, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 25, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 25, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 25, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 25, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 25, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 25, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 26, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 26, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 26, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 26, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 26, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 26, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 26, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 26, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 26, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 26, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 26, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 26, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 26, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 26, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 26, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 16, 27, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 27, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 16, 28, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 28, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 16, 29, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 29, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 30, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 30, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 30, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 30, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 30, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 30, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 30, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 30, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 30, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 30, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 30, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 30, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 30, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 30, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 30, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 31, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 31, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 31, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 31, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 31, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 31, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 31, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 31, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 31, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 31, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 31, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 31, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 31, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 31, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 31, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 32, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 32, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 32, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 32, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 32, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 32, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 32, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 32, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 32, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 32, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 32, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 32, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 32, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 32, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 32, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 16, 33, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 33, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 16, 34, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 34, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 16, 35, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 35, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 36, "RO", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 36, "RO", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 36, "RO", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 36, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 36, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 36, "RO", 0, 0, 0ull, 0ull},
|
|
{"WDOG_SUM" , 44, 1, 36, "RO", 0, 0, 0ull, 0ull},
|
|
{"TWSI" , 45, 1, 36, "RO", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 36, "RO", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 36, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 36, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 36, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 37, "RO", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 37, "RO", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 37, "RO", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 37, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 37, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 37, "RO", 0, 0, 0ull, 0ull},
|
|
{"WDOG_SUM" , 44, 1, 37, "RO", 0, 0, 0ull, 0ull},
|
|
{"TWSI" , 45, 1, 37, "RO", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 37, "RO", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 37, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 37, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 37, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 37, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 37, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 37, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 16, 38, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 38, "RAZ", 1, 1, 0, 0},
|
|
{"BITS" , 0, 32, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 39, "RAZ", 1, 1, 0, 0},
|
|
{"BITS" , 0, 32, 40, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 40, "RAZ", 1, 1, 0, 0},
|
|
{"NMI" , 0, 16, 41, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 41, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 0, 2, 42, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 42, "RAZ", 1, 1, 0, 0},
|
|
{"PPDBG" , 0, 16, 43, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 43, "RAZ", 1, 1, 0, 0},
|
|
{"POKE" , 0, 64, 44, "RAZ", 1, 1, 0, 0},
|
|
{"RST0" , 0, 1, 45, "R/W", 1, 1, 0, 0},
|
|
{"RST" , 1, 15, 45, "R/W", 0, 0, 32767ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 45, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_BIST" , 0, 1, 46, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 46, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_PRST" , 0, 1, 47, "R/W", 0, 0, 1ull, 0ull},
|
|
{"NPI" , 1, 1, 47, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HOST64" , 2, 1, 47, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_3_63" , 3, 61, 47, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_RST" , 0, 1, 48, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 48, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 36, 49, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ONE_SHOT" , 36, 1, 49, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 49, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 0, 2, 50, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STATE" , 2, 2, 50, "RO", 0, 0, 0ull, 0ull},
|
|
{"LEN" , 4, 16, 50, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 20, 24, 50, "RO", 0, 0, 0ull, 0ull},
|
|
{"DSTOP" , 44, 1, 50, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GSTOPEN" , 45, 1, 50, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_46_63" , 46, 18, 50, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 17, 51, "RO", 0, 1, 0ull, 0},
|
|
{"DSEL_EXT" , 17, 1, 51, "R/W", 0, 0, 1ull, 0ull},
|
|
{"C_MUL" , 18, 5, 51, "RO", 1, 1, 0, 0},
|
|
{"REM" , 23, 6, 51, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 51, "RAZ", 1, 1, 0, 0},
|
|
{"PDF" , 0, 4, 52, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_15" , 4, 12, 52, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RDF" , 16, 4, 52, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 52, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"P1_BRF" , 0, 8, 53, "RO", 0, 0, 0ull, 0ull},
|
|
{"P0_BRF" , 8, 8, 53, "RO", 0, 0, 0ull, 0ull},
|
|
{"P1_BWB" , 16, 1, 53, "RO", 0, 0, 0ull, 0ull},
|
|
{"P0_BWB" , 17, 1, 53, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRF" , 18, 1, 53, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_19" , 19, 1, 53, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"GFU" , 20, 1, 53, "RO", 0, 0, 0ull, 0ull},
|
|
{"IFU" , 21, 1, 53, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRQ" , 22, 1, 53, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 53, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SARB" , 0, 1, 54, "R/W", 0, 0, 1ull, 1ull},
|
|
{"GXOR_ENA" , 1, 1, 54, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NXOR_ENA" , 2, 1, 54, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NRPL_ENA" , 3, 1, 54, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 54, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 20, 55, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_63" , 20, 44, 55, "RAZ", 1, 1, 0, 0},
|
|
{"SIZE" , 0, 9, 56, "R/W", 0, 1, 3ull, 0},
|
|
{"POOL" , 9, 3, 56, "R/W", 0, 1, 0ull, 0},
|
|
{"DWBCNT" , 12, 8, 56, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_20_63" , 20, 44, 56, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_4" , 0, 5, 57, "RAZ", 1, 1, 0, 0},
|
|
{"RDPTR" , 5, 31, 57, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 57, "RAZ", 1, 1, 0, 0},
|
|
{"CP2ECCENA" , 0, 1, 58, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2SBE" , 1, 1, 58, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CP2DBE" , 2, 1, 58, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CP2SBINA" , 3, 1, 58, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2DBINA" , 4, 1, 58, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2SYN" , 5, 8, 58, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTEECCENA" , 13, 1, 58, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DTESBE" , 14, 1, 58, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTEDBE" , 15, 1, 58, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTESBINA" , 16, 1, 58, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DTEDBINA" , 17, 1, 58, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DTESYN" , 18, 7, 58, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTEPARENA" , 25, 1, 58, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DTEPERR" , 26, 1, 58, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTEPINA" , 27, 1, 58, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2PARENA" , 28, 1, 58, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP2PERR" , 29, 1, 58, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CP2PINA" , 30, 1, 58, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DBLOVF" , 31, 1, 58, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DBLINA" , 32, 1, 58, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_33_63" , 33, 31, 58, "RAZ", 1, 1, 0, 0},
|
|
{"ENA_P1" , 0, 1, 59, "R/W", 0, 0, 1ull, 1ull},
|
|
{"ENA_P0" , 1, 1, 59, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_2" , 2, 1, 59, "RAZ", 1, 1, 0, 0},
|
|
{"MTYPE" , 3, 1, 59, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SIL_LAT" , 4, 2, 59, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RW_DLY" , 6, 4, 59, "R/W", 0, 0, 1ull, 1ull},
|
|
{"WR_DLY" , 10, 4, 59, "R/W", 0, 0, 2ull, 2ull},
|
|
{"FPRCH" , 14, 2, 59, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BPRCH" , 16, 2, 59, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BLEN" , 18, 1, 59, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PBUNK" , 19, 3, 59, "R/W", 0, 0, 2ull, 2ull},
|
|
{"R2R_PBUNK" , 22, 1, 59, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INIT_P1" , 23, 1, 59, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INIT_P0" , 24, 1, 59, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BUNK_INIT" , 25, 2, 59, "R/W", 0, 0, 3ull, 3ull},
|
|
{"LPP_ENA" , 27, 1, 59, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLKDIV" , 28, 2, 59, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RLDCK_RST" , 30, 1, 59, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RLDQCK90_RST" , 31, 1, 59, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 59, "RAZ", 1, 1, 0, 0},
|
|
{"REF_INT" , 0, 4, 60, "R/W", 0, 0, 3ull, 3ull},
|
|
{"TSKW" , 4, 2, 60, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 60, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TRL" , 8, 4, 60, "R/W", 0, 0, 6ull, 6ull},
|
|
{"TWL" , 12, 4, 60, "R/W", 0, 0, 7ull, 7ull},
|
|
{"TRC" , 16, 4, 60, "R/W", 0, 0, 6ull, 6ull},
|
|
{"TMRSC" , 20, 3, 60, "R/W", 0, 0, 6ull, 6ull},
|
|
{"MRS_ENA" , 23, 1, 60, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AREF_ENA" , 24, 1, 60, "R/W", 0, 0, 0ull, 0ull},
|
|
{"REF_INTLO" , 25, 9, 60, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 60, "RAZ", 1, 1, 0, 0},
|
|
{"FCRAM2P" , 0, 1, 61, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAXBNK" , 1, 1, 61, "R/W", 0, 0, 1ull, 1ull},
|
|
{"UA_START" , 2, 2, 61, "R/W", 0, 0, 1ull, 1ull},
|
|
{"REFSHORT" , 4, 1, 61, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRFC" , 5, 5, 61, "R/W", 0, 0, 9ull, 9ull},
|
|
{"SILRST" , 10, 1, 61, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DTECLKDIS" , 11, 1, 61, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 61, "RAZ", 1, 1, 0, 0},
|
|
{"MADDR" , 0, 24, 62, "RO", 0, 0, 0ull, 0ull},
|
|
{"BNUM" , 24, 3, 62, "RO", 0, 0, 0ull, 0ull},
|
|
{"PNUM" , 27, 1, 62, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSRC" , 28, 2, 62, "RO", 0, 0, 0ull, 0ull},
|
|
{"FDST" , 30, 9, 62, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_39_63" , 39, 25, 62, "RAZ", 1, 1, 0, 0},
|
|
{"MRS" , 0, 15, 63, "R/W", 0, 0, 66ull, 66ull},
|
|
{"RESERVED_15_15" , 15, 1, 63, "RAZ", 1, 1, 0, 0},
|
|
{"EMRS" , 16, 15, 63, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_31_31" , 31, 1, 63, "RAZ", 1, 1, 0, 0},
|
|
{"EMRS2" , 32, 15, 63, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_47_63" , 47, 17, 63, "RAZ", 1, 1, 0, 0},
|
|
{"MRSDAT" , 0, 23, 64, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_23_63" , 23, 41, 64, "RAZ", 1, 1, 0, 0},
|
|
{"IMODE" , 0, 1, 65, "R/W", 0, 0, 1ull, 1ull},
|
|
{"QMODE" , 1, 1, 65, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PMODE" , 2, 1, 65, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DTMODE" , 3, 1, 65, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DCMODE" , 4, 1, 65, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SBDLCK" , 5, 1, 65, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SBDNUM" , 6, 5, 65, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 65, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL" , 0, 5, 66, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 66, "RAZ", 0, 1, 0ull, 0},
|
|
{"NCTL" , 8, 4, 66, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_12_15" , 12, 4, 66, "RAZ", 0, 1, 0ull, 0},
|
|
{"ENABLE" , 16, 1, 66, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_17_63" , 17, 47, 66, "RAZ", 0, 1, 0ull, 0},
|
|
{"SBD0" , 0, 64, 67, "RO", 1, 1, 0, 0},
|
|
{"SBD1" , 0, 64, 68, "RO", 1, 1, 0, 0},
|
|
{"SBD2" , 0, 64, 69, "RO", 1, 1, 0, 0},
|
|
{"SBD3" , 0, 64, 70, "RO", 1, 1, 0, 0},
|
|
{"FDR" , 0, 1, 71, "RO", 0, 0, 0ull, 0ull},
|
|
{"FFR" , 1, 1, 71, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPF1" , 2, 1, 71, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPF0" , 3, 1, 71, "RO", 0, 0, 0ull, 0ull},
|
|
{"FRD" , 4, 1, 71, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 71, "RAZ", 1, 1, 0, 0},
|
|
{"MEM0_ERR" , 0, 7, 72, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM1_ERR" , 7, 7, 72, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 14, 1, 72, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USE_STT" , 15, 1, 72, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USE_LDT" , 16, 1, 72, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 17, 1, 72, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 72, "RAZ", 1, 1, 0, 0},
|
|
{"FPF_RD" , 0, 11, 73, "R/W", 0, 0, 64ull, 0ull},
|
|
{"FPF_WR" , 11, 11, 73, "R/W", 0, 0, 196ull, 0ull},
|
|
{"RESERVED_22_63" , 22, 42, 73, "RAZ", 1, 1, 0, 0},
|
|
{"FPF_SIZ" , 0, 11, 74, "R/W", 0, 0, 256ull, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 74, "RAZ", 1, 1, 0, 0},
|
|
{"FPF_RD" , 0, 12, 75, "R/W", 0, 0, 64ull, 0ull},
|
|
{"FPF_WR" , 12, 12, 75, "R/W", 0, 0, 196ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 75, "RAZ", 1, 1, 0, 0},
|
|
{"FPF_SIZ" , 0, 12, 76, "R/W", 0, 0, 256ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 76, "RAZ", 1, 1, 0, 0},
|
|
{"FED0_SBE" , 0, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED0_DBE" , 1, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED1_SBE" , 2, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED1_DBE" , 3, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_UND" , 4, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_COFF" , 5, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_PERR" , 6, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_UND" , 7, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_COFF" , 8, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_PERR" , 9, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_UND" , 10, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_COFF" , 11, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_PERR" , 12, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_UND" , 13, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_COFF" , 14, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_PERR" , 15, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_UND" , 16, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_COFF" , 17, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_PERR" , 18, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_UND" , 19, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_COFF" , 20, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_PERR" , 21, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_UND" , 22, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_COFF" , 23, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_PERR" , 24, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_UND" , 25, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_COFF" , 26, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_PERR" , 27, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 77, "RAZ", 1, 1, 0, 0},
|
|
{"FED0_SBE" , 0, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED0_DBE" , 1, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED1_SBE" , 2, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED1_DBE" , 3, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_UND" , 4, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_COFF" , 5, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_PERR" , 6, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_UND" , 7, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_COFF" , 8, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_PERR" , 9, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_UND" , 10, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_COFF" , 11, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_PERR" , 12, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_UND" , 13, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_COFF" , 14, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_PERR" , 15, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_UND" , 16, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_COFF" , 17, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_PERR" , 18, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_UND" , 19, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_COFF" , 20, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_PERR" , 21, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_UND" , 22, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_COFF" , 23, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_PERR" , 24, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_UND" , 25, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_COFF" , 26, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_PERR" , 27, 1, 78, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 78, "RAZ", 1, 1, 0, 0},
|
|
{"QUE_SIZ" , 0, 29, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 79, "RAZ", 1, 1, 0, 0},
|
|
{"PG_NUM" , 0, 25, 80, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 80, "RAZ", 1, 1, 0, 0},
|
|
{"ACT_INDX" , 0, 26, 81, "RO", 0, 1, 0ull, 0},
|
|
{"ACT_QUE" , 26, 3, 81, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 81, "RAZ", 0, 0, 0ull, 7ull},
|
|
{"EXP_INDX" , 0, 26, 82, "RO", 0, 1, 0ull, 0},
|
|
{"EXP_QUE" , 26, 3, 82, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 82, "RAZ", 0, 0, 0ull, 7ull},
|
|
{"CTL" , 0, 16, 83, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 83, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 32, 84, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 84, "RAZ", 1, 1, 0, 0},
|
|
{"OUT_COL" , 0, 1, 85, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NCB_OVR" , 1, 1, 85, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OUT_OVR" , 2, 16, 85, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_21" , 18, 4, 85, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LOSTSTAT" , 22, 4, 85, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"STATOVR" , 26, 1, 85, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INB_NXA" , 27, 4, 85, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 85, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 17, 86, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 86, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 1, 87, "RO", 1, 1, 0, 0},
|
|
{"EN" , 1, 1, 87, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_2_63" , 2, 62, 87, "RAZ", 1, 1, 0, 0},
|
|
{"PRT" , 0, 6, 88, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 88, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 89, "R/W", 0, 1, 0ull, 0},
|
|
{"SPEED" , 1, 1, 89, "R/W", 0, 1, 1ull, 0},
|
|
{"DUPLEX" , 2, 1, 89, "R/W", 0, 1, 1ull, 0},
|
|
{"SLOTTIME" , 3, 1, 89, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 89, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 64, 90, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 91, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 92, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 93, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 94, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 95, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 0, 8, 96, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 96, "RAZ", 1, 1, 0, 0},
|
|
{"BCST" , 0, 1, 97, "R/W", 0, 1, 1ull, 0},
|
|
{"MCST" , 1, 2, 97, "R/W", 0, 1, 0ull, 0},
|
|
{"CAM_MODE" , 3, 1, 97, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 97, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 5, 98, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_5_63" , 5, 59, 98, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 99, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CAREXT" , 1, 1, 99, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MAXERR" , 2, 1, 99, "R/W", 0, 0, 1ull, 1ull},
|
|
{"JABBER" , 3, 1, 99, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCSERR" , 4, 1, 99, "R/W", 0, 0, 1ull, 1ull},
|
|
{"ALNERR" , 5, 1, 99, "R/W", 0, 0, 1ull, 1ull},
|
|
{"LENERR" , 6, 1, 99, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RCVERR" , 7, 1, 99, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SKPERR" , 8, 1, 99, "R/W", 0, 0, 1ull, 1ull},
|
|
{"NIBERR" , 9, 1, 99, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_10_63" , 10, 54, 99, "RAZ", 1, 1, 0, 0},
|
|
{"PRE_CHK" , 0, 1, 100, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PRE_STRP" , 1, 1, 100, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_DRP" , 2, 1, 100, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_BCK" , 3, 1, 100, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_MCST" , 4, 1, 100, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_SMAC" , 5, 1, 100, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PRE_FREE" , 6, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VLAN_LEN" , 7, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PAD_LEN" , 8, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRE_ALIGN" , 9, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NULL_DIS" , 10, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 100, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 16, 101, "R/W", 0, 0, 1536ull, 1536ull},
|
|
{"RESERVED_16_63" , 16, 48, 101, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 16, 102, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_16_63" , 16, 48, 102, "RAZ", 1, 1, 0, 0},
|
|
{"IFG" , 0, 4, 103, "R/W", 0, 0, 12ull, 12ull},
|
|
{"RESERVED_4_63" , 4, 60, 103, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAREXT" , 1, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 2, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"JABBER" , 3, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ALNERR" , 5, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 6, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RCVERR" , 7, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NIBERR" , 9, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OVRERR" , 10, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHY_LINK" , 16, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHY_SPD" , 17, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHY_DUPX" , 18, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PAUSE_DRP" , 19, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 104, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CAREXT" , 1, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 2, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"JABBER" , 3, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ALNERR" , 5, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 6, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RCVERR" , 7, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NIBERR" , 9, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OVRERR" , 10, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PHY_LINK" , 16, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PHY_SPD" , 17, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PHY_DUPX" , 18, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PAUSE_DRP" , 19, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 105, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 106, "R/W", 0, 0, 10240ull, 10240ull},
|
|
{"RESERVED_16_63" , 16, 48, 106, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 16, 107, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 107, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 1, 108, "RO", 0, 1, 0ull, 0},
|
|
{"SPEED" , 1, 2, 108, "RO", 0, 1, 0ull, 0},
|
|
{"DUPLEX" , 3, 1, 108, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 108, "RAZ", 1, 1, 0, 0},
|
|
{"RD_CLR" , 0, 1, 109, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 109, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 110, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 110, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 111, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 111, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 112, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 112, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 113, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 113, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 114, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 114, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 115, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 115, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 116, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 116, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 117, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 117, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 118, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 118, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 7, 119, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 119, "RAZ", 1, 1, 0, 0},
|
|
{"FCSSEL" , 8, 1, 119, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 119, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 120, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_6_63" , 6, 58, 120, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 121, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_6_63" , 6, 58, 121, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 9, 122, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_9_63" , 9, 55, 122, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 16, 123, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 123, "RAZ", 1, 1, 0, 0},
|
|
{"DPRT" , 0, 4, 124, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 124, "RAZ", 1, 1, 0, 0},
|
|
{"COMMIT" , 0, 16, 125, "RO", 0, 0, 0ull, 0ull},
|
|
{"DROP" , 16, 16, 125, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 125, "RAZ", 1, 1, 0, 0},
|
|
{"PRTS" , 0, 3, 126, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_3_63" , 3, 61, 126, "RAZ", 1, 1, 0, 0},
|
|
{"SMAC" , 0, 48, 127, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 127, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 128, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP" , 16, 1, 128, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 128, "RAZ", 1, 1, 0, 0},
|
|
{"PREAMBLE" , 0, 1, 129, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PAD" , 1, 1, 129, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCS" , 2, 1, 129, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FORCE_FCS" , 3, 1, 129, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 129, "RAZ", 1, 1, 0, 0},
|
|
{"BURST" , 0, 16, 130, "R/W", 0, 0, 8192ull, 8192ull},
|
|
{"RESERVED_16_63" , 16, 48, 130, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_CNT" , 0, 6, 131, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_63" , 6, 58, 131, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL_EN" , 0, 1, 132, "R/W", 0, 0, 1ull, 1ull},
|
|
{"XSDEF_EN" , 1, 1, 132, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 132, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_SIZE" , 0, 8, 133, "R/W", 0, 0, 59ull, 59ull},
|
|
{"RESERVED_8_63" , 8, 56, 133, "RAZ", 1, 1, 0, 0},
|
|
{"INTERVAL" , 0, 16, 134, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 134, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 135, "R/W", 0, 1, 96ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 135, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 136, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_16_63" , 16, 48, 136, "RAZ", 1, 1, 0, 0},
|
|
{"SEND" , 0, 1, 137, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 137, "RAZ", 1, 1, 0, 0},
|
|
{"SLOT" , 0, 10, 138, "R/W", 0, 0, 512ull, 512ull},
|
|
{"RESERVED_10_63" , 10, 54, 138, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 139, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 139, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL" , 0, 32, 140, "RC/W", 0, 1, 0ull, 0},
|
|
{"XSDEF" , 32, 32, 140, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCOL" , 0, 32, 141, "RC/W", 0, 1, 0ull, 0},
|
|
{"SCOL" , 32, 32, 141, "RC/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 142, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 142, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 143, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 143, "RAZ", 1, 1, 0, 0},
|
|
{"HIST0" , 0, 32, 144, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST1" , 32, 32, 144, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST2" , 0, 32, 145, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST3" , 32, 32, 145, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST4" , 0, 32, 146, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST5" , 32, 32, 146, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST6" , 0, 32, 147, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST7" , 32, 32, 147, "RC/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 0, 32, 148, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 32, 32, 148, "RC/W", 0, 1, 0ull, 0},
|
|
{"CTL" , 0, 32, 149, "RC/W", 0, 1, 0ull, 0},
|
|
{"UNDFLW" , 32, 32, 149, "RC/W", 0, 1, 0ull, 0},
|
|
{"RD_CLR" , 0, 1, 150, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 150, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 9, 151, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_9_63" , 9, 55, 151, "RAZ", 1, 1, 0, 0},
|
|
{"BP" , 0, 4, 152, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 152, "RAZ", 1, 1, 0, 0},
|
|
{"LIMIT" , 0, 5, 153, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_5_63" , 5, 59, 153, "RAZ", 1, 1, 0, 0},
|
|
{"CORRUPT" , 0, 4, 154, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_4_63" , 4, 60, 154, "RAZ", 1, 1, 0, 0},
|
|
{"IFG1" , 0, 4, 155, "R/W", 0, 1, 8ull, 0},
|
|
{"IFG2" , 4, 4, 155, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 155, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 156, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NCB_NXA" , 1, 1, 156, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 4, 156, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 156, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 4, 156, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 4, 156, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LATE_COL" , 16, 4, 156, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 156, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 157, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NCB_NXA" , 1, 1, 157, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 4, 157, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 157, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 4, 157, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 4, 157, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LATE_COL" , 16, 4, 157, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 157, "RAZ", 1, 1, 0, 0},
|
|
{"JAM" , 0, 8, 158, "R/W", 0, 1, 238ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 158, "RAZ", 1, 1, 0, 0},
|
|
{"LFSR" , 0, 16, 159, "R/W", 0, 1, 65535ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 159, "RAZ", 1, 1, 0, 0},
|
|
{"IGN_FULL" , 0, 4, 160, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP" , 4, 4, 160, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EN" , 8, 4, 160, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 160, "RAZ", 1, 1, 0, 0},
|
|
{"DMAC" , 0, 48, 161, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
|
|
{"RESERVED_48_63" , 48, 16, 161, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 162, "R/W", 0, 0, 34824ull, 34824ull},
|
|
{"RESERVED_16_63" , 16, 48, 162, "RAZ", 1, 1, 0, 0},
|
|
{"PRTS" , 0, 5, 163, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 163, "RAZ", 1, 1, 0, 0},
|
|
{"CONT_PKT" , 0, 1, 164, "R/W", 0, 1, 0ull, 0},
|
|
{"TPA_CLR" , 1, 1, 164, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 164, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DRAIN" , 0, 16, 165, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 165, "RAZ", 1, 1, 0, 0},
|
|
{"MAX1" , 0, 8, 166, "R/W", 0, 1, 8ull, 0},
|
|
{"MAX2" , 8, 8, 166, "R/W", 0, 1, 4ull, 0},
|
|
{"SLICE" , 16, 7, 166, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_23_63" , 23, 41, 166, "RAZ", 1, 1, 0, 0},
|
|
{"ROUND" , 0, 16, 167, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 167, "RAZ", 1, 1, 0, 0},
|
|
{"THRESH" , 0, 6, 168, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 168, "RAZ", 1, 1, 0, 0},
|
|
{"TX_OE" , 0, 1, 169, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RX_XOR" , 1, 1, 169, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_EN" , 2, 1, 169, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_TYPE" , 3, 1, 169, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_CNT" , 4, 4, 169, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_SEL" , 8, 4, 169, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 169, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 170, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 170, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 171, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 171, "RAZ", 1, 1, 0, 0},
|
|
{"CLR" , 0, 16, 172, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 172, "RAZ", 1, 1, 0, 0},
|
|
{"SET" , 0, 16, 173, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 173, "RAZ", 1, 1, 0, 0},
|
|
{"ICD" , 0, 1, 174, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBD" , 1, 1, 174, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRP1" , 2, 1, 174, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRP0" , 3, 1, 174, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRN1" , 4, 1, 174, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRN0" , 5, 1, 174, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBRQ1" , 6, 1, 174, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBRQ0" , 7, 1, 174, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNRT" , 8, 1, 174, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBR1" , 9, 1, 174, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBR0" , 10, 1, 174, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBDR1" , 11, 1, 174, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBDR0" , 12, 1, 174, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNR0" , 13, 1, 174, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNR1" , 14, 1, 174, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICR1" , 15, 1, 174, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICR0" , 16, 1, 174, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNRCB" , 17, 1, 174, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 174, "RAZ", 1, 1, 0, 0},
|
|
{"FAU_END" , 0, 1, 175, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB_ENB" , 1, 1, 175, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PKO_ENB" , 2, 1, 175, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INB_MAT" , 3, 1, 175, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OUTB_MAT" , 4, 1, 175, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 175, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 176, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 176, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 176, "RAZ", 1, 1, 0, 0},
|
|
{"TOUT_VAL" , 0, 12, 177, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TOUT_ENB" , 12, 1, 177, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 177, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 178, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 178, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 178, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 8, 179, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 8, 9, 179, "R/W", 0, 1, 0ull, 0},
|
|
{"OPC" , 17, 4, 179, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 21, 8, 179, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 179, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 8, 180, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 8, 9, 180, "R/W", 0, 1, 0ull, 0},
|
|
{"OPC" , 17, 4, 180, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 21, 8, 180, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 180, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 181, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 182, "R/W", 0, 1, 0ull, 0},
|
|
{"NP_SOP" , 0, 1, 183, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NP_EOP" , 1, 1, 183, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_SOP" , 2, 1, 183, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_EOP" , 3, 1, 183, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NP_DAT" , 4, 1, 183, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_DAT" , 5, 1, 183, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 183, "RAZ", 1, 1, 0, 0},
|
|
{"NP_SOP" , 0, 1, 184, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NP_EOP" , 1, 1, 184, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_SOP" , 2, 1, 184, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_EOP" , 3, 1, 184, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NP_DAT" , 4, 1, 184, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_DAT" , 5, 1, 184, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 184, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 185, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 185, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 185, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 186, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 186, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 186, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 187, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 187, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 187, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 9, 188, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 9, 8, 188, "R/W", 0, 1, 0ull, 0},
|
|
{"EOT" , 17, 1, 188, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 18, 8, 188, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_26_63" , 26, 38, 188, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 9, 189, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 9, 8, 189, "R/W", 0, 1, 0ull, 0},
|
|
{"EOT" , 17, 1, 189, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 18, 8, 189, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_26_63" , 26, 38, 189, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 190, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 191, "R/W", 0, 1, 0ull, 0},
|
|
{"CNT_VAL" , 0, 15, 192, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 192, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 192, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 193, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 193, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 193, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 194, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 194, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 194, "RAZ", 1, 1, 0, 0},
|
|
{"PORT" , 0, 6, 195, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 195, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP_SZ" , 0, 6, 196, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 196, "RAZ", 1, 1, 0, 0},
|
|
{"BACK" , 0, 4, 197, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 197, "RAZ", 1, 1, 0, 0},
|
|
{"BACK" , 0, 4, 198, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 198, "RAZ", 1, 1, 0, 0},
|
|
{"PWP" , 0, 1, 199, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_NEW" , 1, 1, 199, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_OLD" , 2, 1, 199, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRC_OFF" , 3, 1, 199, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ0" , 4, 1, 199, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ1" , 5, 1, 199, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM_WORD" , 6, 1, 199, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM0" , 7, 1, 199, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM1" , 8, 1, 199, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM2" , 9, 1, 199, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM3" , 10, 1, 199, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPQ_PBE0" , 11, 1, 199, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPQ_PBE1" , 12, 1, 199, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_POW" , 13, 1, 199, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_WP1" , 14, 1, 199, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_WQED" , 15, 1, 199, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 199, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_ENB" , 0, 36, 200, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 200, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_CNT" , 0, 64, 201, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_EN" , 0, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OPC_MODE" , 1, 2, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PBP_EN" , 3, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WQE_LEND" , 4, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKT_LEND" , 5, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NADDBUF" , 6, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDPKT" , 7, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 8, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LEN_M8" , 9, 1, 202, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PKT_OFF" , 10, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPD_FULL" , 11, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 202, "RAZ", 1, 1, 0, 0},
|
|
{"PRC_PAR0" , 0, 1, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR1" , 1, 1, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR2" , 2, 1, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR3" , 3, 1, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_SUB" , 4, 1, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DC_OVR" , 5, 1, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CC_OVR" , 6, 1, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C_COLL" , 7, 1, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"D_COLL" , 8, 1, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BC_OVR" , 9, 1, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 203, "RAZ", 1, 1, 0, 0},
|
|
{"PRC_PAR0" , 0, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR1" , 1, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR2" , 2, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR3" , 3, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP_SUB" , 4, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DC_OVR" , 5, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CC_OVR" , 6, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C_COLL" , 7, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"D_COLL" , 8, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BC_OVR" , 9, 1, 204, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 204, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP_SZ" , 0, 6, 205, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 205, "RAZ", 1, 1, 0, 0},
|
|
{"MB_SIZE" , 0, 12, 206, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_12_63" , 12, 52, 206, "RAZ", 1, 1, 0, 0},
|
|
{"PTR" , 0, 29, 207, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 207, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 17, 208, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_ENB" , 17, 1, 208, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 208, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 25, 209, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 209, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 3, 210, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 3, 1, 210, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 4, 29, 210, "RO", 1, 1, 0, 0},
|
|
{"PRADDR" , 33, 3, 210, "RO", 1, 1, 0, 0},
|
|
{"MAX_PKT" , 36, 3, 210, "RO", 0, 0, 5ull, 5ull},
|
|
{"RESERVED_39_63" , 39, 25, 210, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 7, 211, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 7, 1, 211, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 8, 29, 211, "RO", 1, 1, 0, 0},
|
|
{"MAX_PKT" , 37, 7, 211, "RO", 0, 0, 36ull, 36ull},
|
|
{"RESERVED_44_63" , 44, 20, 211, "RAZ", 1, 1, 0, 0},
|
|
{"WQE_PCNT" , 0, 7, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_PCNT" , 7, 7, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"PFIF_CNT" , 14, 3, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"WQEV_CNT" , 17, 1, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTV_CNT" , 18, 1, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 212, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 8, 213, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 8, 1, 213, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 9, 29, 213, "RO", 1, 1, 0, 0},
|
|
{"PRADDR" , 38, 8, 213, "RO", 1, 1, 0, 0},
|
|
{"WRADDR" , 46, 8, 213, "RO", 1, 1, 0, 0},
|
|
{"MAX_CNTS" , 54, 7, 213, "RO", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_61_63" , 61, 3, 213, "RAZ", 1, 1, 0, 0},
|
|
{"PASS" , 0, 32, 214, "R/W", 0, 1, 0ull, 0},
|
|
{"DROP" , 32, 32, 214, "R/W", 0, 1, 0ull, 0},
|
|
{"Q0_PCNT" , 0, 32, 215, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 215, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_ENB" , 0, 36, 216, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AVG_DLY" , 36, 14, 216, "R/W", 0, 1, 0ull, 0},
|
|
{"PRB_DLY" , 50, 14, 216, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRB_CON" , 0, 32, 217, "R/W", 0, 1, 0ull, 0},
|
|
{"AVG_CON" , 32, 8, 217, "R/W", 0, 1, 0ull, 0},
|
|
{"NEW_CON" , 40, 8, 217, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_PCNT" , 48, 1, 217, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 217, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 25, 218, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT" , 25, 6, 218, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 218, "RAZ", 1, 1, 0, 0},
|
|
{"PORT_BIT" , 0, 32, 219, "R/W", 0, 0, 4294967295ull, 4294967295ull},
|
|
{"RESERVED_32_63" , 32, 32, 219, "RAZ", 1, 1, 0, 0},
|
|
{"WQE_POOL" , 0, 3, 220, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_3_63" , 3, 61, 220, "RAZ", 1, 1, 0, 0},
|
|
{"PTR" , 0, 29, 221, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 221, "RAZ", 1, 1, 0, 0},
|
|
{"MEM0" , 0, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"MEM1" , 1, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"RRC" , 2, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 222, "RAZ", 1, 1, 0, 0},
|
|
{"MEM0_ERR" , 0, 7, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM1_ERR" , 7, 7, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 223, "RAZ", 1, 1, 0, 0},
|
|
{"KED0_SBE" , 0, 1, 224, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KED0_DBE" , 1, 1, 224, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KED1_SBE" , 2, 1, 224, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KED1_DBE" , 3, 1, 224, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 224, "RAZ", 1, 1, 0, 0},
|
|
{"KED0_SBE" , 0, 1, 225, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KED0_DBE" , 1, 1, 225, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KED1_SBE" , 2, 1, 225, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KED1_DBE" , 3, 1, 225, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 225, "RAZ", 1, 1, 0, 0},
|
|
{"WLB_DAT" , 0, 4, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"STIN_MSK" , 4, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"DT" , 5, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTCNT" , 6, 13, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"WLB_MSK" , 19, 4, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTBNK" , 23, 1, 226, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 226, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"L2T" , 0, 9, 227, "RO", 0, 0, 0ull, 0ull},
|
|
{"VAB_VWCF" , 9, 1, 227, "RO", 0, 0, 0ull, 0ull},
|
|
{"LRF" , 10, 2, 227, "RO", 0, 0, 0ull, 0ull},
|
|
{"VWDF" , 12, 4, 227, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 227, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XRDDAT" , 0, 1, 228, "RO", 0, 0, 0ull, 0ull},
|
|
{"XRDMSK" , 1, 1, 228, "RO", 0, 0, 0ull, 0ull},
|
|
{"PICBST" , 2, 1, 228, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPCBST" , 3, 1, 228, "RO", 0, 0, 0ull, 0ull},
|
|
{"RHDB" , 4, 4, 228, "RO", 0, 0, 0ull, 0ull},
|
|
{"RMDB" , 8, 4, 228, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRB" , 12, 4, 228, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 228, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LRF_ARB_MODE" , 0, 1, 229, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RFB_ARB_MODE" , 1, 1, 229, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RSP_ARB_MODE" , 2, 1, 229, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MWF_CRD" , 3, 4, 229, "R/W", 0, 0, 2ull, 2ull},
|
|
{"IDXALIAS" , 7, 1, 229, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPEN" , 8, 1, 229, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FPEMPTY" , 9, 1, 229, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FPEXP" , 10, 4, 229, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DFILL_DIS" , 14, 1, 229, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_17" , 15, 3, 229, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LBIST" , 18, 1, 229, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BSTRUN" , 19, 1, 229, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 229, "RAZ", 1, 1, 0, 0},
|
|
{"L2T" , 0, 1, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2D" , 1, 1, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FINV" , 2, 1, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SET" , 3, 3, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PPNUM" , 6, 4, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LFB_DMP" , 10, 1, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LFB_ENUM" , 11, 4, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 230, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DT_TAG" , 0, 29, 231, "RO", 0, 0, 0ull, 0ull},
|
|
{"DT_VLD" , 29, 1, 231, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_30" , 30, 1, 231, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DTENA" , 31, 1, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 231, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_ENA" , 0, 1, 232, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_3" , 1, 3, 232, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_BASE" , 4, 27, 232, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 232, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_OFFSET" , 0, 10, 233, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 233, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VLD" , 0, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"CMD" , 1, 4, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"SID" , 5, 9, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"VABNUM" , 14, 4, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"SET" , 18, 3, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"IHD" , 21, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"ITL" , 22, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"INXT" , 23, 4, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"VAM" , 27, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"STCFL" , 28, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"STINV" , 29, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"STPND" , 30, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"STCPND" , 31, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 234, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VLD" , 0, 1, 235, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTPRB" , 1, 1, 235, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRBRTY" , 2, 1, 235, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTMFL" , 3, 1, 235, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTVTM" , 4, 1, 235, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTRSC" , 5, 1, 235, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTRSP" , 6, 1, 235, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTDT" , 7, 1, 235, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTRDA" , 8, 1, 235, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTM" , 9, 1, 235, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWRM" , 10, 1, 235, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWHF" , 11, 1, 235, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWHP" , 12, 1, 235, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTDQ" , 13, 1, 235, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTDW" , 14, 1, 235, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTRSP" , 15, 1, 235, "RO", 0, 0, 0ull, 0ull},
|
|
{"BID" , 16, 2, 235, "RO", 0, 0, 0ull, 0ull},
|
|
{"DSGOING" , 18, 1, 235, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 235, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_IDX" , 0, 11, 236, "RO", 0, 0, 0ull, 0ull},
|
|
{"LFB_TAG" , 11, 16, 236, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_63" , 27, 37, 236, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_HWM" , 0, 4, 237, "R/W", 0, 0, 15ull, 15ull},
|
|
{"STPARTDIS" , 4, 1, 237, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 237, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PFCNT0" , 0, 36, 238, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 238, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT0SEL" , 0, 6, 239, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0CLR" , 6, 1, 239, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0ENA" , 7, 1, 239, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1SEL" , 8, 6, 239, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1CLR" , 14, 1, 239, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1ENA" , 15, 1, 239, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2SEL" , 16, 6, 239, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2CLR" , 22, 1, 239, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2ENA" , 23, 1, 239, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3SEL" , 24, 6, 239, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3CLR" , 30, 1, 239, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3ENA" , 31, 1, 239, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0RDCLR" , 32, 1, 239, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1RDCLR" , 33, 1, 239, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2RDCLR" , 34, 1, 239, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3RDCLR" , 35, 1, 239, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 239, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK0" , 0, 8, 240, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK1" , 8, 8, 240, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK2" , 16, 8, 240, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK3" , 24, 8, 240, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 240, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK4" , 0, 8, 241, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK5" , 8, 8, 241, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK6" , 16, 8, 241, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK7" , 24, 8, 241, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 241, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK8" , 0, 8, 242, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK9" , 8, 8, 242, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK10" , 16, 8, 242, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK11" , 24, 8, 242, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 242, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK12" , 0, 8, 243, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK13" , 8, 8, 243, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK14" , 16, 8, 243, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK15" , 24, 8, 243, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 243, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSKIOB" , 0, 8, 244, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 244, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q0STAT" , 0, 34, 245, "RO", 0, 0, 0ull, 0ull},
|
|
{"FTL" , 34, 1, 245, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_35_63" , 35, 29, 245, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q1STAT" , 0, 34, 246, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 246, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q2STAT" , 0, 34, 247, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 247, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q3STAT" , 0, 34, 248, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 248, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 0, 1, 249, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_INTENA" , 1, 1, 249, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DED_INTENA" , 2, 1, 249, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 3, 1, 249, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 4, 1, 249, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BMHCLSEL" , 5, 1, 249, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 249, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 0, 11, 250, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSET" , 11, 3, 250, "RO", 0, 0, 0ull, 0ull},
|
|
{"FOWMSK" , 14, 4, 250, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADRU" , 18, 1, 250, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 250, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW0" , 0, 10, 251, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW1" , 10, 10, 251, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 251, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW2" , 0, 10, 252, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW3" , 10, 10, 252, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 252, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q0FUS" , 0, 34, 253, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 253, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q1FUS" , 0, 34, 254, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 254, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q2FUS" , 0, 34, 255, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 255, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q3FUS" , 0, 34, 256, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRIP_1024K" , 34, 1, 256, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRIP_512K" , 35, 1, 256, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_36" , 36, 1, 256, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EMA_CTL" , 37, 2, 256, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_39_63" , 39, 25, 256, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 0, 1, 257, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_INTENA" , 1, 1, 257, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DED_INTENA" , 2, 1, 257, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 3, 1, 257, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 4, 1, 257, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FSYN" , 5, 6, 257, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 11, 10, 257, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSET" , 21, 3, 257, "RO", 0, 0, 0ull, 0ull},
|
|
{"LCKERR" , 24, 1, 257, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK_INTENA" , 25, 1, 257, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LCKERR2" , 26, 1, 257, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK_INTENA2" , 27, 1, 257, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FADRU" , 28, 1, 257, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 257, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RATE" , 0, 8, 258, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_8_63" , 8, 56, 258, "RAZ", 1, 1, 0, 0},
|
|
{"PHASE" , 0, 7, 259, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_7_63" , 7, 57, 259, "RAZ", 1, 1, 0, 0},
|
|
{"RATE" , 0, 16, 260, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 260, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_EN" , 0, 1, 261, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 261, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 262, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 262, "RAZ", 1, 1, 0, 0},
|
|
{"POLARITY" , 0, 1, 263, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 263, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_EN" , 0, 8, 264, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 264, "RAZ", 1, 1, 0, 0},
|
|
{"FORMAT" , 0, 4, 265, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 265, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 6, 266, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 266, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 6, 267, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 267, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 32, 268, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 268, "RAZ", 1, 1, 0, 0},
|
|
{"CLR" , 0, 32, 269, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 269, "RAZ", 1, 1, 0, 0},
|
|
{"SET" , 0, 32, 270, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 270, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL_DAT" , 0, 5, 271, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_11" , 5, 7, 271, "RAZ", 0, 1, 0ull, 0},
|
|
{"PCTL_CSR" , 12, 4, 271, "R/W", 0, 1, 15ull, 0},
|
|
{"NCTL_DAT" , 16, 4, 271, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_27" , 20, 8, 271, "RAZ", 0, 1, 0ull, 0},
|
|
{"NCTL_CSR" , 28, 4, 271, "R/W", 0, 1, 15ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 271, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DIC" , 0, 2, 272, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QS_DIC" , 2, 2, 272, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TSKW" , 4, 2, 272, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SIL_LAT" , 6, 2, 272, "R/W", 0, 0, 1ull, 1ull},
|
|
{"BPRCH" , 8, 1, 272, "R/W", 0, 1, 0ull, 0},
|
|
{"FPRCH2" , 9, 1, 272, "R/W", 0, 0, 0ull, 1ull},
|
|
{"MODE128B" , 10, 1, 272, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DRESET" , 11, 1, 272, "R/W", 0, 0, 1ull, 0ull},
|
|
{"INORDER_MRF" , 12, 1, 272, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INORDER_MWF" , 13, 1, 272, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"R2R_SLOT" , 14, 1, 272, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RDIMM_ENA" , 15, 1, 272, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_17" , 16, 2, 272, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX_WRITE_BATCH" , 18, 4, 272, "R/W", 0, 0, 8ull, 8ull},
|
|
{"XOR_BANK" , 22, 1, 272, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SLOW_SCF" , 23, 1, 272, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DDR__PCTL" , 24, 4, 272, "RO", 1, 1, 0, 0},
|
|
{"DDR__NCTL" , 28, 4, 272, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 272, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 273, "RAZ", 0, 1, 0ull, 0},
|
|
{"DCC_ENABLE" , 8, 1, 273, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SIL_MODE" , 9, 1, 273, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_10_63" , 10, 54, 273, "RAZ", 1, 1, 0, 0},
|
|
{"DCLKCNT_HI" , 0, 32, 274, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 274, "RAZ", 1, 1, 0, 0},
|
|
{"DCLKCNT_LO" , 0, 32, 275, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 275, "RAZ", 1, 1, 0, 0},
|
|
{"DDR2" , 0, 1, 276, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RDQS" , 1, 1, 276, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLL90_BYP" , 2, 1, 276, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLL90_VLU" , 3, 5, 276, "R/W", 0, 1, 0ull, 0},
|
|
{"QDLL_ENA" , 8, 1, 276, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ODT_ENA" , 9, 1, 276, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DDR2T" , 10, 1, 276, "R/W", 0, 1, 0ull, 0},
|
|
{"CRIP_MODE" , 11, 1, 276, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TFAW" , 12, 5, 276, "R/W", 0, 0, 0ull, 9ull},
|
|
{"DDR_EOF" , 17, 4, 276, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SILO_HC" , 21, 1, 276, "R/W", 0, 1, 1ull, 0},
|
|
{"TWR" , 22, 3, 276, "R/W", 0, 0, 3ull, 1ull},
|
|
{"BWCNT" , 25, 1, 276, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POCAS" , 26, 1, 276, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDLAT" , 27, 3, 276, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BURST8" , 30, 1, 276, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BANK8" , 31, 1, 276, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 276, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CLK" , 0, 4, 277, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_4" , 4, 1, 277, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CMD" , 5, 4, 277, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 277, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DQ" , 10, 4, 277, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 277, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CS_MASK" , 0, 8, 278, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_15" , 8, 8, 278, "RAZ", 0, 1, 0ull, 0},
|
|
{"ROW_LSB" , 16, 3, 278, "R/W", 0, 1, 3ull, 0},
|
|
{"BANK8" , 19, 1, 278, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_63" , 20, 44, 278, "RAZ", 0, 1, 0ull, 0},
|
|
{"MRDSYN0" , 0, 8, 279, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN1" , 8, 8, 279, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN2" , 16, 8, 279, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN3" , 24, 8, 279, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 279, "RAZ", 1, 1, 0, 0},
|
|
{"FCOL" , 0, 12, 280, "RO", 0, 0, 0ull, 0ull},
|
|
{"FROW" , 12, 14, 280, "RO", 0, 0, 0ull, 0ull},
|
|
{"FBANK" , 26, 3, 280, "RO", 0, 0, 0ull, 0ull},
|
|
{"FBUNK" , 29, 1, 280, "RO", 0, 0, 0ull, 0ull},
|
|
{"FDIMM" , 30, 2, 280, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 280, "RAZ", 1, 1, 0, 0},
|
|
{"IFBCNT_HI" , 0, 32, 281, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 281, "RAZ", 1, 1, 0, 0},
|
|
{"IFBCNT_LO" , 0, 32, 282, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 282, "RAZ", 1, 1, 0, 0},
|
|
{"INIT_START" , 0, 1, 283, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 1, 1, 283, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ROW_LSB" , 2, 3, 283, "R/W", 0, 1, 3ull, 0},
|
|
{"PBANK_LSB" , 5, 4, 283, "R/W", 0, 1, 5ull, 0},
|
|
{"REF_INT" , 9, 6, 283, "R/W", 0, 0, 1ull, 2ull},
|
|
{"TCL" , 15, 4, 283, "R/W", 0, 1, 3ull, 0},
|
|
{"INTR_SEC_ENA" , 19, 1, 283, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INTR_DED_ENA" , 20, 1, 283, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 21, 4, 283, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 25, 4, 283, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BUNK_ENA" , 29, 1, 283, "R/W", 0, 1, 0ull, 0},
|
|
{"SILO_QC" , 30, 1, 283, "R/W", 0, 1, 0ull, 0},
|
|
{"RESET" , 31, 1, 283, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 283, "RAZ", 1, 1, 0, 0},
|
|
{"TRAS" , 0, 5, 284, "R/W", 0, 0, 12ull, 12ull},
|
|
{"TRCD" , 5, 4, 284, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TWTR" , 9, 4, 284, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TRP" , 13, 4, 284, "R/W", 0, 0, 5ull, 4ull},
|
|
{"TRFC" , 17, 5, 284, "R/W", 0, 0, 6ull, 7ull},
|
|
{"TMRD" , 22, 3, 284, "R/W", 0, 0, 2ull, 2ull},
|
|
{"CASLAT" , 25, 3, 284, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TRRD" , 28, 3, 284, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_31_63" , 31, 33, 284, "RAZ", 1, 1, 0, 0},
|
|
{"CS_MASK" , 0, 8, 285, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 285, "RAZ", 1, 1, 0, 0},
|
|
{"OPSCNT_HI" , 0, 32, 286, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 286, "RAZ", 1, 1, 0, 0},
|
|
{"OPSCNT_LO" , 0, 32, 287, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 287, "RAZ", 1, 1, 0, 0},
|
|
{"EN2" , 0, 1, 288, "R/W", 0, 1, 0ull, 0},
|
|
{"EN4" , 1, 1, 288, "R/W", 0, 1, 0ull, 0},
|
|
{"EN6" , 2, 1, 288, "R/W", 0, 1, 0ull, 0},
|
|
{"EN8" , 3, 1, 288, "R/W", 0, 1, 1ull, 0},
|
|
{"EN12" , 4, 1, 288, "R/W", 0, 1, 0ull, 0},
|
|
{"EN16" , 5, 1, 288, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_7" , 6, 2, 288, "RAZ", 0, 1, 0ull, 0},
|
|
{"CLKR" , 8, 6, 288, "R/W", 0, 1, 0ull, 0},
|
|
{"CLKF" , 14, 12, 288, "R/W", 0, 1, 31ull, 0},
|
|
{"RESET_N" , 26, 1, 288, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DIV_RESET" , 27, 1, 288, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 288, "RAZ", 0, 1, 0ull, 0},
|
|
{"FBSLIP" , 0, 1, 289, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RFSLIP" , 1, 1, 289, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_21" , 2, 20, 289, "RAZ", 1, 1, 0, 0},
|
|
{"DDR__PCTL" , 22, 5, 289, "RO", 1, 1, 0, 0},
|
|
{"DDR__NCTL" , 27, 5, 289, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 289, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL" , 0, 5, 290, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 290, "RAZ", 0, 1, 0ull, 0},
|
|
{"NCTL" , 8, 4, 290, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_12_15" , 12, 4, 290, "RAZ", 0, 1, 0ull, 0},
|
|
{"ENABLE" , 16, 1, 290, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_17_63" , 17, 47, 290, "RAZ", 0, 1, 0ull, 0},
|
|
{"RODT_LO0" , 0, 4, 291, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_LO1" , 4, 4, 291, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_LO2" , 8, 4, 291, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_LO3" , 12, 4, 291, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI0" , 16, 4, 291, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI1" , 20, 4, 291, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI2" , 24, 4, 291, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI3" , 28, 4, 291, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_32_63" , 32, 32, 291, "RAZ", 1, 1, 0, 0},
|
|
{"WODT_LO0" , 0, 4, 292, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_LO1" , 4, 4, 292, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_LO2" , 8, 4, 292, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_LO3" , 12, 4, 292, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_HI0" , 16, 4, 292, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_HI1" , 20, 4, 292, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_HI2" , 24, 4, 292, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_HI3" , 28, 4, 292, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_32_63" , 32, 32, 292, "RAZ", 1, 1, 0, 0},
|
|
{"NCBI" , 0, 1, 293, "RO", 0, 0, 0ull, 0ull},
|
|
{"LOC" , 1, 1, 293, "RO", 0, 0, 0ull, 0ull},
|
|
{"NCBO_0" , 2, 1, 293, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 293, "RAZ", 1, 1, 0, 0},
|
|
{"ADR_ERR" , 0, 1, 294, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WAIT_ERR" , 1, 1, 294, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 294, "RAZ", 1, 1, 0, 0},
|
|
{"ADR_INT" , 0, 1, 295, "R/W", 0, 1, 0ull, 0},
|
|
{"WAIT_INT" , 1, 1, 295, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 295, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 296, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 3, 5, 296, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 296, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 297, "RAZ", 1, 1, 0, 0},
|
|
{"BASE" , 3, 25, 297, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_30" , 28, 3, 297, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 31, 1, 297, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 297, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 298, "R/W", 1, 1, 0, 0},
|
|
{"BASE" , 0, 16, 299, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 16, 12, 299, "R/W", 0, 1, 0ull, 0},
|
|
{"WIDTH" , 28, 1, 299, "R/W", 0, 1, 0ull, 0},
|
|
{"ALE" , 29, 1, 299, "R/W", 0, 1, 0ull, 0},
|
|
{"ORBIT" , 30, 1, 299, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 31, 1, 299, "R/W", 0, 1, 0ull, 0},
|
|
{"OE_EXT" , 32, 2, 299, "R/W", 0, 1, 0ull, 0},
|
|
{"WE_EXT" , 34, 2, 299, "R/W", 0, 1, 0ull, 0},
|
|
{"SAM" , 36, 1, 299, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_37_63" , 37, 27, 299, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 6, 300, "R/W", 0, 1, 63ull, 0},
|
|
{"CE" , 6, 6, 300, "R/W", 0, 1, 63ull, 0},
|
|
{"OE" , 12, 6, 300, "R/W", 0, 1, 63ull, 0},
|
|
{"WE" , 18, 6, 300, "R/W", 0, 1, 63ull, 0},
|
|
{"RD_HLD" , 24, 6, 300, "R/W", 0, 1, 63ull, 0},
|
|
{"WR_HLD" , 30, 6, 300, "R/W", 0, 1, 63ull, 0},
|
|
{"PAUSE" , 36, 6, 300, "R/W", 0, 1, 63ull, 0},
|
|
{"WAIT" , 42, 6, 300, "R/W", 0, 1, 63ull, 0},
|
|
{"PAGE" , 48, 6, 300, "R/W", 0, 1, 63ull, 0},
|
|
{"ALE" , 54, 6, 300, "R/W", 0, 1, 63ull, 0},
|
|
{"PAGES" , 60, 2, 300, "R/W", 0, 1, 0ull, 0},
|
|
{"WAITM" , 62, 1, 300, "R/W", 0, 1, 0ull, 0},
|
|
{"PAGEM" , 63, 1, 300, "R/W", 0, 1, 0ull, 0},
|
|
{"FIF_THR" , 0, 6, 301, "R/W", 0, 0, 26ull, 26ull},
|
|
{"RESERVED_6_7" , 6, 2, 301, "RAZ", 1, 1, 0, 0},
|
|
{"FIF_CNT" , 8, 6, 301, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_63" , 14, 50, 301, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 64, 302, "R/W", 1, 1, 0, 0},
|
|
{"MAN_INFO" , 0, 32, 303, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 303, "RAZ", 1, 1, 0, 0},
|
|
{"MAN_INFO" , 0, 32, 304, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 304, "RAZ", 1, 1, 0, 0},
|
|
{"PP_DIS" , 0, 16, 305, "RO", 1, 1, 0, 0},
|
|
{"CHIP_ID" , 16, 8, 305, "RO", 1, 1, 0, 0},
|
|
{"BIST_DIS" , 24, 1, 305, "RO", 1, 1, 0, 0},
|
|
{"RST_SHT" , 25, 1, 305, "RO", 1, 1, 0, 0},
|
|
{"NOCRYPTO" , 26, 1, 305, "RO", 1, 1, 0, 0},
|
|
{"NOMUL" , 27, 1, 305, "RO", 1, 1, 0, 0},
|
|
{"NODFA_CP2" , 28, 1, 305, "RO", 1, 1, 0, 0},
|
|
{"NOKASU" , 29, 1, 305, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_30_63" , 30, 34, 305, "RAZ", 1, 1, 0, 0},
|
|
{"ICACHE" , 0, 24, 306, "RO", 1, 1, 0, 0},
|
|
{"NODFA_DTE" , 24, 1, 306, "RO", 1, 1, 0, 0},
|
|
{"NOZIP" , 25, 1, 306, "RO", 1, 1, 0, 0},
|
|
{"EFUS_IGN" , 26, 1, 306, "RO", 1, 1, 0, 0},
|
|
{"EFUS_LCK" , 27, 1, 306, "RO", 1, 1, 0, 0},
|
|
{"BAR2_EN" , 28, 1, 306, "RO", 1, 1, 0, 0},
|
|
{"ZIP_CRIP" , 29, 2, 306, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_31_63" , 31, 33, 306, "RAZ", 1, 1, 0, 0},
|
|
{"EMA" , 0, 2, 307, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 307, "RAZ", 1, 1, 0, 0},
|
|
{"PDF" , 0, 64, 308, "RO", 1, 1, 0, 0},
|
|
{"FBSLIP" , 0, 1, 309, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RFSLIP" , 1, 1, 309, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 309, "RAZ", 1, 1, 0, 0},
|
|
{"PROG" , 0, 1, 310, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_1_63" , 1, 63, 310, "RAZ", 1, 1, 0, 0},
|
|
{"SETUP" , 0, 8, 311, "R/W", 0, 1, 3ull, 0},
|
|
{"SCLK_HI" , 8, 12, 311, "R/W", 0, 1, 100ull, 0},
|
|
{"SCLK_LO" , 20, 4, 311, "R/W", 0, 1, 2ull, 0},
|
|
{"OUT" , 24, 8, 311, "R/W", 0, 1, 3ull, 0},
|
|
{"PROG_PIN" , 32, 1, 311, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_33_63" , 33, 31, 311, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 7, 312, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 312, "RAZ", 1, 1, 0, 0},
|
|
{"EFUSE" , 8, 1, 312, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 312, "RAZ", 1, 1, 0, 0},
|
|
{"PEND" , 12, 1, 312, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 312, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 16, 8, 312, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_24_63" , 24, 40, 312, "RAZ", 1, 1, 0, 0},
|
|
{"REPAIR0" , 0, 14, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"REPAIR1" , 14, 14, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"REPAIR2" , 28, 14, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_42_63" , 42, 22, 313, "RAZ", 1, 1, 0, 0},
|
|
{"TOO_MANY" , 0, 1, 314, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 314, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 2, 315, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_2_63" , 2, 62, 315, "RAZ", 1, 1, 0, 0},
|
|
{"ST_INT" , 0, 1, 316, "R/W1C", 0, 1, 0ull, 0},
|
|
{"TS_INT" , 1, 1, 316, "R/W1C", 0, 1, 0ull, 0},
|
|
{"CORE_INT" , 2, 1, 316, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_3" , 3, 1, 316, "RAZ", 1, 1, 0, 0},
|
|
{"ST_EN" , 4, 1, 316, "R/W", 0, 1, 0ull, 0},
|
|
{"TS_EN" , 5, 1, 316, "R/W", 0, 1, 0ull, 0},
|
|
{"CORE_EN" , 6, 1, 316, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_7" , 7, 1, 316, "RAZ", 1, 1, 0, 0},
|
|
{"SDA_OVR" , 8, 1, 316, "R/W", 0, 1, 0ull, 0},
|
|
{"SCL_OVR" , 9, 1, 316, "R/W", 0, 1, 0ull, 0},
|
|
{"SDA" , 10, 1, 316, "RO", 1, 1, 0, 0},
|
|
{"SCL" , 11, 1, 316, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_12_63" , 12, 52, 316, "RAZ", 1, 1, 0, 0},
|
|
{"D" , 0, 32, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"EOP_IA" , 32, 3, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"IA" , 35, 5, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"A" , 40, 10, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"SCR" , 50, 2, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 52, 3, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"SOVR" , 55, 1, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"R" , 56, 1, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"OP" , 57, 4, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"EIA" , 61, 1, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"SLONLY" , 62, 1, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"V" , 63, 1, 317, "RC/W", 0, 1, 0ull, 0},
|
|
{"D" , 0, 32, 318, "R/W", 0, 1, 0ull, 0},
|
|
{"IA" , 32, 8, 318, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_40_63" , 40, 24, 318, "RAZ", 1, 1, 0, 0},
|
|
{"D" , 0, 32, 319, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_32_61" , 32, 30, 319, "RAZ", 1, 1, 0, 0},
|
|
{"V" , 62, 2, 319, "RC/W", 0, 1, 0ull, 0},
|
|
{"DLH" , 0, 8, 320, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 320, "RAZ", 1, 1, 0, 0},
|
|
{"DLL" , 0, 8, 321, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 321, "RAZ", 1, 1, 0, 0},
|
|
{"FAR" , 0, 1, 322, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 322, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 323, "WO", 0, 1, 0ull, 0},
|
|
{"RXFR" , 1, 1, 323, "WO", 0, 1, 0ull, 0},
|
|
{"TXFR" , 2, 1, 323, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_3" , 3, 1, 323, "RAZ", 0, 1, 0ull, 0},
|
|
{"TXTRIG" , 4, 2, 323, "WO", 0, 1, 0ull, 0},
|
|
{"RXTRIG" , 6, 2, 323, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 323, "RAZ", 1, 1, 0, 0},
|
|
{"HTX" , 0, 1, 324, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 324, "RAZ", 1, 1, 0, 0},
|
|
{"ERBFI" , 0, 1, 325, "R/W", 0, 1, 0ull, 0},
|
|
{"ETBEI" , 1, 1, 325, "R/W", 0, 1, 0ull, 0},
|
|
{"ELSI" , 2, 1, 325, "R/W", 0, 1, 0ull, 0},
|
|
{"EDSSI" , 3, 1, 325, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_6" , 4, 3, 325, "RAZ", 0, 1, 0ull, 0},
|
|
{"PTIME" , 7, 1, 325, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 325, "RAZ", 1, 1, 0, 0},
|
|
{"IID" , 0, 4, 326, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_4_5" , 4, 2, 326, "RAZ", 0, 1, 0ull, 0},
|
|
{"FEN" , 6, 2, 326, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 326, "RAZ", 1, 1, 0, 0},
|
|
{"CLS" , 0, 2, 327, "R/W", 0, 1, 0ull, 0},
|
|
{"STOP" , 2, 1, 327, "R/W", 0, 1, 0ull, 0},
|
|
{"PEN" , 3, 1, 327, "R/W", 0, 1, 0ull, 0},
|
|
{"EPS" , 4, 1, 327, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_5" , 5, 1, 327, "RAZ", 0, 1, 0ull, 0},
|
|
{"BRK" , 6, 1, 327, "R/W", 0, 1, 0ull, 0},
|
|
{"DLAB" , 7, 1, 327, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 327, "RAZ", 1, 1, 0, 0},
|
|
{"DR" , 0, 1, 328, "RO", 0, 1, 0ull, 0},
|
|
{"OE" , 1, 1, 328, "RC", 0, 1, 0ull, 0},
|
|
{"PE" , 2, 1, 328, "RC", 0, 1, 0ull, 0},
|
|
{"FE" , 3, 1, 328, "RC", 0, 1, 0ull, 0},
|
|
{"BI" , 4, 1, 328, "RC", 0, 1, 0ull, 0},
|
|
{"THRE" , 5, 1, 328, "RO", 0, 1, 1ull, 0},
|
|
{"TEMT" , 6, 1, 328, "RO", 0, 1, 1ull, 0},
|
|
{"FERR" , 7, 1, 328, "RC", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 328, "RAZ", 1, 1, 0, 0},
|
|
{"DTR" , 0, 1, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"RTS" , 1, 1, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT1" , 2, 1, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT2" , 3, 1, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"LOOP" , 4, 1, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"AFCE" , 5, 1, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 329, "RAZ", 0, 1, 0ull, 0},
|
|
{"DCTS" , 0, 1, 330, "RC", 0, 1, 0ull, 0},
|
|
{"DDSR" , 1, 1, 330, "RC", 0, 1, 0ull, 0},
|
|
{"TERI" , 2, 1, 330, "RC", 0, 1, 0ull, 0},
|
|
{"DDCD" , 3, 1, 330, "RC", 0, 1, 0ull, 0},
|
|
{"CTS" , 4, 1, 330, "RO", 1, 1, 0, 0},
|
|
{"DSR" , 5, 1, 330, "RO", 0, 1, 0ull, 0},
|
|
{"RI" , 6, 1, 330, "RO", 0, 1, 0ull, 0},
|
|
{"DCD" , 7, 1, 330, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 330, "RAZ", 1, 1, 0, 0},
|
|
{"RBR" , 0, 8, 331, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 331, "RAZ", 1, 1, 0, 0},
|
|
{"RFL" , 0, 7, 332, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 332, "RAZ", 1, 1, 0, 0},
|
|
{"RFWD" , 0, 8, 333, "WO", 0, 1, 0ull, 0},
|
|
{"RFPE" , 8, 1, 333, "WO", 0, 1, 0ull, 0},
|
|
{"RFFE" , 9, 1, 333, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_10_63" , 10, 54, 333, "RAZ", 1, 1, 0, 0},
|
|
{"SBCR" , 0, 1, 334, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 334, "RAZ", 1, 1, 0, 0},
|
|
{"SCR" , 0, 8, 335, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 335, "RAZ", 1, 1, 0, 0},
|
|
{"SFE" , 0, 1, 336, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 336, "RAZ", 1, 1, 0, 0},
|
|
{"USR" , 0, 1, 337, "WO", 0, 1, 0ull, 0},
|
|
{"SRFR" , 1, 1, 337, "WO", 0, 1, 0ull, 0},
|
|
{"STFR" , 2, 1, 337, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_63" , 3, 61, 337, "RAZ", 1, 1, 0, 0},
|
|
{"SRT" , 0, 2, 338, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 338, "RAZ", 1, 1, 0, 0},
|
|
{"SRTS" , 0, 1, 339, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 339, "RAZ", 1, 1, 0, 0},
|
|
{"STT" , 0, 2, 340, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 340, "RAZ", 1, 1, 0, 0},
|
|
{"TFL" , 0, 7, 341, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 341, "RAZ", 1, 1, 0, 0},
|
|
{"TFR" , 0, 8, 342, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 342, "RAZ", 1, 1, 0, 0},
|
|
{"THR" , 0, 8, 343, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 343, "RAZ", 1, 1, 0, 0},
|
|
{"BUSY" , 0, 1, 344, "RO", 0, 1, 0ull, 0},
|
|
{"TFNF" , 1, 1, 344, "RO", 0, 1, 1ull, 0},
|
|
{"TFE" , 2, 1, 344, "RO", 0, 1, 1ull, 0},
|
|
{"RFNE" , 3, 1, 344, "RO", 0, 1, 0ull, 0},
|
|
{"RFF" , 4, 1, 344, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 344, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 345, "RAZ", 1, 1, 0, 0},
|
|
{"BADDR" , 3, 61, 345, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_0_2" , 0, 3, 346, "RAZ", 1, 1, 0, 0},
|
|
{"BADDR" , 3, 61, 346, "R/W", 0, 1, 0ull, 0},
|
|
{"DPI_BS" , 0, 1, 347, "RO", 0, 0, 0ull, 0ull},
|
|
{"PDF_BS" , 1, 1, 347, "RO", 0, 0, 0ull, 0ull},
|
|
{"DOB_BS" , 2, 1, 347, "RO", 0, 0, 0ull, 0ull},
|
|
{"NUS_BS" , 3, 1, 347, "RO", 0, 0, 0ull, 0ull},
|
|
{"POS_BS" , 4, 1, 347, "RO", 0, 0, 0ull, 0ull},
|
|
{"POF3_BS" , 5, 1, 347, "RO", 0, 0, 0ull, 0ull},
|
|
{"POF2_BS" , 6, 1, 347, "RO", 0, 0, 0ull, 0ull},
|
|
{"POF1_BS" , 7, 1, 347, "RO", 0, 0, 0ull, 0ull},
|
|
{"POF0_BS" , 8, 1, 347, "RO", 0, 0, 0ull, 0ull},
|
|
{"PIG_BS" , 9, 1, 347, "RO", 0, 0, 0ull, 0ull},
|
|
{"PGF_BS" , 10, 1, 347, "RO", 0, 0, 0ull, 0ull},
|
|
{"RDNL_BS" , 11, 1, 347, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCAD_BS" , 12, 1, 347, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCAC_BS" , 13, 1, 347, "RO", 0, 0, 0ull, 0ull},
|
|
{"RDN_BS" , 14, 1, 347, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCN_BS" , 15, 1, 347, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCNC_BS" , 16, 1, 347, "RO", 0, 0, 0ull, 0ull},
|
|
{"RDP_BS" , 17, 1, 347, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF_BS" , 18, 1, 347, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSR_BS" , 19, 1, 347, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 347, "RAZ", 1, 1, 0, 0},
|
|
{"BSIZE" , 0, 16, 348, "R/W", 0, 1, 1024ull, 0},
|
|
{"ISIZE" , 16, 7, 348, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_23_63" , 23, 41, 348, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 5, 349, "R/W", 0, 1, 16ull, 0},
|
|
{"PCTL" , 5, 5, 349, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_10_63" , 10, 54, 349, "RAZ", 1, 1, 0, 0},
|
|
{"TIMER" , 0, 10, 350, "R/W", 0, 0, 0ull, 50ull},
|
|
{"RESERVED_10_31" , 10, 22, 350, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX_WORD" , 32, 5, 350, "R/W", 0, 0, 2ull, 0ull},
|
|
{"RESERVED_37_39" , 37, 3, 350, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WAIT_COM" , 40, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCI_WDIS" , 41, 1, 350, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INS0_64B" , 42, 1, 350, "R/W", 0, 1, 0ull, 0},
|
|
{"INS1_64B" , 43, 1, 350, "R/W", 0, 1, 0ull, 0},
|
|
{"INS2_64B" , 44, 1, 350, "R/W", 0, 1, 0ull, 0},
|
|
{"INS3_64B" , 45, 1, 350, "R/W", 0, 1, 0ull, 0},
|
|
{"INS0_ENB" , 46, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INS1_ENB" , 47, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INS2_ENB" , 48, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INS3_ENB" , 49, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OUT0_ENB" , 50, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OUT1_ENB" , 51, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OUT2_ENB" , 52, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OUT3_ENB" , 53, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DIS_PNIW" , 54, 1, 350, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CHIP_REV" , 55, 8, 350, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_63_63" , 63, 1, 350, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_SEL" , 0, 16, 351, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 351, "RAZ", 1, 1, 0, 0},
|
|
{"CSIZE" , 0, 14, 352, "R/W", 0, 1, 0ull, 0},
|
|
{"LP_ENB" , 14, 1, 352, "R/W", 0, 0, 0ull, 1ull},
|
|
{"HP_ENB" , 15, 1, 352, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O_MODE" , 16, 1, 352, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O_ES" , 17, 2, 352, "R/W", 0, 1, 0ull, 0},
|
|
{"O_NS" , 19, 1, 352, "R/W", 0, 1, 0ull, 0},
|
|
{"O_RO" , 20, 1, 352, "R/W", 0, 1, 0ull, 0},
|
|
{"O_ADD1" , 21, 1, 352, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA_QUE" , 22, 3, 352, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB_ICHK" , 25, 9, 352, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB_DENB" , 34, 1, 352, "R/W", 0, 0, 0ull, 1ull},
|
|
{"B0_LEND" , 35, 1, 352, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 352, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 32, 353, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 7, 353, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_39_63" , 39, 25, 353, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 354, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 36, 4, 354, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 354, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 32, 355, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 7, 355, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_39_63" , 39, 25, 355, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 356, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 36, 4, 356, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 356, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 16, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 357, "RAZ", 1, 1, 0, 0},
|
|
{"SADDR" , 0, 36, 358, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 358, "RAZ", 1, 1, 0, 0},
|
|
{"ROR" , 0, 1, 359, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR" , 1, 2, 359, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR" , 3, 1, 359, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_CSR" , 4, 1, 359, "R/W", 0, 0, 0ull, 1ull},
|
|
{"D_ROR" , 5, 1, 359, "R/W", 0, 1, 0ull, 0},
|
|
{"D_ESR" , 6, 2, 359, "R/W", 0, 1, 0ull, 0},
|
|
{"D_NSR" , 8, 1, 359, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP_DHI" , 9, 13, 359, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_RR" , 22, 1, 359, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 359, "RAZ", 1, 1, 0, 0},
|
|
{"RML_RTO" , 0, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RML_WTO" , 1, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCI_RSL" , 2, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PO0_2SML" , 3, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PO1_2SML" , 4, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PO2_2SML" , 5, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PO3_2SML" , 6, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I0_RTOUT" , 7, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I1_RTOUT" , 8, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I2_RTOUT" , 9, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I3_RTOUT" , 10, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I0_OVERF" , 11, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I1_OVERF" , 12, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I2_OVERF" , 13, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I3_OVERF" , 14, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P0_RTOUT" , 15, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_RTOUT" , 16, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P2_RTOUT" , 17, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P3_RTOUT" , 18, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P0_PERR" , 19, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_PERR" , 20, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P2_PERR" , 21, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P3_PERR" , 22, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"G0_RTOUT" , 23, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"G1_RTOUT" , 24, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"G2_RTOUT" , 25, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"G3_RTOUT" , 26, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P0_PPERR" , 27, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_PPERR" , 28, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P2_PPERR" , 29, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P3_PPERR" , 30, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P0_PTOUT" , 31, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_PTOUT" , 32, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P2_PTOUT" , 33, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P3_PTOUT" , 34, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I0_PPERR" , 35, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I1_PPERR" , 36, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I2_PPERR" , 37, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I3_PPERR" , 38, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"WIN_RTO" , 39, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P_DPERR" , 40, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 41, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FCR_S_E" , 42, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FCR_A_F" , 43, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCR_S_E" , 44, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCR_A_F" , 45, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q2_S_E" , 46, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q2_A_F" , 47, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q3_S_E" , 48, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q3_A_F" , 49, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"COM_S_E" , 50, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"COM_A_F" , 51, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PNC_S_E" , 52, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PNC_A_F" , 53, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RWX_S_E" , 54, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RDX_S_E" , 55, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCF_P_E" , 56, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCF_P_F" , 57, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PDF_P_E" , 58, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PDF_P_F" , 59, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q1_S_E" , 60, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q1_A_F" , 61, 1, 360, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_62_63" , 62, 2, 360, "RAZ", 1, 1, 0, 0},
|
|
{"RML_RTO" , 0, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RML_WTO" , 1, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCI_RSL" , 2, 1, 361, "RO", 0, 0, 0ull, 0ull},
|
|
{"PO0_2SML" , 3, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PO1_2SML" , 4, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PO2_2SML" , 5, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PO3_2SML" , 6, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I0_RTOUT" , 7, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I1_RTOUT" , 8, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I2_RTOUT" , 9, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I3_RTOUT" , 10, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I0_OVERF" , 11, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I1_OVERF" , 12, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I2_OVERF" , 13, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I3_OVERF" , 14, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P0_RTOUT" , 15, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_RTOUT" , 16, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P2_RTOUT" , 17, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P3_RTOUT" , 18, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P0_PERR" , 19, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_PERR" , 20, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P2_PERR" , 21, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P3_PERR" , 22, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"G0_RTOUT" , 23, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"G1_RTOUT" , 24, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"G2_RTOUT" , 25, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"G3_RTOUT" , 26, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P0_PPERR" , 27, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_PPERR" , 28, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P2_PPERR" , 29, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P3_PPERR" , 30, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P0_PTOUT" , 31, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_PTOUT" , 32, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P2_PTOUT" , 33, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P3_PTOUT" , 34, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I0_PPERR" , 35, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I1_PPERR" , 36, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I2_PPERR" , 37, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I3_PPERR" , 38, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WIN_RTO" , 39, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_DPERR" , 40, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IOBDMA" , 41, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCR_S_E" , 42, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCR_A_F" , 43, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCR_S_E" , 44, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCR_A_F" , 45, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_S_E" , 46, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_A_F" , 47, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_S_E" , 48, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_A_F" , 49, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COM_S_E" , 50, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COM_A_F" , 51, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PNC_S_E" , 52, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PNC_A_F" , 53, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RWX_S_E" , 54, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RDX_S_E" , 55, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCF_P_E" , 56, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCF_P_F" , 57, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PDF_P_E" , 58, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PDF_P_F" , 59, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_S_E" , 60, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_A_F" , 61, 1, 361, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_62_63" , 62, 2, 361, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 16, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 362, "RAZ", 1, 1, 0, 0},
|
|
{"SADDR" , 0, 36, 363, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 363, "RAZ", 1, 1, 0, 0},
|
|
{"BA" , 0, 28, 364, "R/W", 0, 1, 0ull, 0},
|
|
{"ROW" , 28, 1, 364, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR" , 29, 1, 364, "R/W", 0, 1, 0ull, 0},
|
|
{"NSW" , 30, 1, 364, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR" , 31, 1, 364, "R/W", 0, 1, 0ull, 0},
|
|
{"ESW" , 32, 2, 364, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR" , 34, 2, 364, "R/W", 0, 1, 0ull, 0},
|
|
{"NMERGE" , 36, 1, 364, "R/W", 0, 1, 0ull, 0},
|
|
{"SHORTL" , 37, 1, 364, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_38_63" , 38, 26, 364, "RAZ", 1, 1, 0, 0},
|
|
{"INT_VEC" , 0, 64, 365, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 0, 32, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 366, "RAZ", 1, 1, 0, 0},
|
|
{"ROR_SL0" , 0, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR_SL0" , 1, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR_SL0" , 2, 2, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR_SL1" , 4, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR_SL1" , 5, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR_SL1" , 6, 2, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR_SL2" , 8, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR_SL2" , 9, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR_SL2" , 10, 2, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR_SL3" , 12, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR_SL3" , 13, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR_SL3" , 14, 2, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"IPTR_O0" , 16, 1, 367, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IPTR_O1" , 17, 1, 367, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IPTR_O2" , 18, 1, 367, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IPTR_O3" , 19, 1, 367, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_20_23" , 20, 4, 367, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"O0_CSRM" , 24, 1, 367, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O1_CSRM" , 25, 1, 367, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O2_CSRM" , 26, 1, 367, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O3_CSRM" , 27, 1, 367, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O0_RO" , 28, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"O0_NS" , 29, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"O0_ES" , 30, 2, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"O1_RO" , 32, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"O1_NS" , 33, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"O1_ES" , 34, 2, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"O2_RO" , 36, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"O2_NS" , 37, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"O2_ES" , 38, 2, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"O3_RO" , 40, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"O3_NS" , 41, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"O3_ES" , 42, 2, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"P0_BMODE" , 44, 1, 367, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P1_BMODE" , 45, 1, 367, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P2_BMODE" , 46, 1, 367, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P3_BMODE" , 47, 1, 367, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKT_RR" , 48, 1, 367, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 367, "RAZ", 1, 1, 0, 0},
|
|
{"NADDR" , 0, 61, 368, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 61, 2, 368, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_63_63" , 63, 1, 368, "RAZ", 1, 1, 0, 0},
|
|
{"NADDR" , 0, 61, 369, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 61, 3, 369, "RO", 0, 0, 0ull, 0ull},
|
|
{"AVAIL" , 0, 32, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 6, 370, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 370, "RAZ", 1, 1, 0, 0},
|
|
{"AVAIL" , 0, 32, 371, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 5, 371, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 371, "RAZ", 1, 1, 0, 0},
|
|
{"RD_BRST" , 0, 7, 372, "R/W", 0, 0, 17ull, 64ull},
|
|
{"WR_BRST" , 7, 7, 372, "R/W", 0, 0, 16ull, 64ull},
|
|
{"RESERVED_14_63" , 14, 50, 372, "RAZ", 1, 1, 0, 0},
|
|
{"PARK_DEV" , 0, 3, 373, "R/W", 0, 1, 0ull, 0},
|
|
{"PARK_MOD" , 3, 1, 373, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 4, 1, 373, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 373, "RAZ", 1, 1, 0, 0},
|
|
{"PCI_OVR" , 8, 4, 373, "R/W", 0, 1, 0ull, 0},
|
|
{"HOSTMODE" , 12, 1, 373, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_13_63" , 13, 51, 373, "RAZ", 1, 1, 0, 0},
|
|
{"CMD_SIZE" , 0, 11, 374, "R/W", 0, 0, 9ull, 9ull},
|
|
{"RESERVED_11_63" , 11, 53, 374, "RAZ", 1, 1, 0, 0},
|
|
{"RSV_A" , 0, 6, 375, "R/W", 0, 1, 0ull, 0},
|
|
{"SKP_LEN" , 6, 7, 375, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_B" , 13, 1, 375, "R/W", 0, 1, 0ull, 0},
|
|
{"PAR_MODE" , 14, 2, 375, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_C" , 16, 5, 375, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_IHDR" , 21, 1, 375, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_D" , 22, 6, 375, "R/W", 0, 1, 0ull, 0},
|
|
{"RSKP_LEN" , 28, 7, 375, "R/W", 0, 1, 8ull, 0},
|
|
{"RSV_E" , 35, 1, 375, "R/W", 0, 1, 0ull, 0},
|
|
{"RPARMODE" , 36, 2, 375, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_F" , 38, 5, 375, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP" , 43, 1, 375, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 375, "RAZ", 1, 1, 0, 0},
|
|
{"RSV_A" , 0, 6, 376, "R/W", 0, 1, 0ull, 0},
|
|
{"SKP_LEN" , 6, 7, 376, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_B" , 13, 1, 376, "R/W", 0, 1, 0ull, 0},
|
|
{"PAR_MODE" , 14, 2, 376, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_C" , 16, 5, 376, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_IHDR" , 21, 1, 376, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_D" , 22, 6, 376, "R/W", 0, 1, 0ull, 0},
|
|
{"RSKP_LEN" , 28, 7, 376, "R/W", 0, 1, 8ull, 0},
|
|
{"RSV_E" , 35, 1, 376, "R/W", 0, 1, 0ull, 0},
|
|
{"RPARMODE" , 36, 2, 376, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_F" , 38, 5, 376, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP" , 43, 1, 376, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 376, "RAZ", 1, 1, 0, 0},
|
|
{"RSV_A" , 0, 6, 377, "R/W", 0, 1, 0ull, 0},
|
|
{"SKP_LEN" , 6, 7, 377, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_B" , 13, 1, 377, "R/W", 0, 1, 0ull, 0},
|
|
{"PAR_MODE" , 14, 2, 377, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_C" , 16, 5, 377, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_IHDR" , 21, 1, 377, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_D" , 22, 6, 377, "R/W", 0, 1, 0ull, 0},
|
|
{"RSKP_LEN" , 28, 7, 377, "R/W", 0, 1, 8ull, 0},
|
|
{"RSV_E" , 35, 1, 377, "R/W", 0, 1, 0ull, 0},
|
|
{"RPARMODE" , 36, 2, 377, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_F" , 38, 5, 377, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP" , 43, 1, 377, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 377, "RAZ", 1, 1, 0, 0},
|
|
{"RSV_A" , 0, 6, 378, "R/W", 0, 1, 0ull, 0},
|
|
{"SKP_LEN" , 6, 7, 378, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_B" , 13, 1, 378, "R/W", 0, 1, 0ull, 0},
|
|
{"PAR_MODE" , 14, 2, 378, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_C" , 16, 5, 378, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_IHDR" , 21, 1, 378, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_D" , 22, 6, 378, "R/W", 0, 1, 0ull, 0},
|
|
{"RSKP_LEN" , 28, 7, 378, "R/W", 0, 1, 8ull, 0},
|
|
{"RSV_E" , 35, 1, 378, "R/W", 0, 1, 0ull, 0},
|
|
{"RPARMODE" , 36, 2, 378, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_F" , 38, 5, 378, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP" , 43, 1, 378, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 378, "RAZ", 1, 1, 0, 0},
|
|
{"ENB" , 0, 4, 379, "R/W", 0, 0, 15ull, 15ull},
|
|
{"BP_ON" , 4, 4, 379, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 379, "RAZ", 1, 1, 0, 0},
|
|
{"MIO" , 0, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX0" , 1, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX1" , 2, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPI" , 3, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"KEY" , 4, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPA" , 5, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"DFA" , 6, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"ZIP" , 7, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_8" , 8, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD" , 9, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 10, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"TIM" , 11, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"POW" , 12, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_13" , 13, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_14" , 14, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_15" , 15, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"L2C" , 16, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"LMC" , 17, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"SPX0" , 18, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"SPX1" , 19, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"PIP" , 20, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_21" , 21, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASX0" , 22, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASX1" , 23, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_24" , 24, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_25" , 25, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_26" , 26, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_27" , 27, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_28" , 28, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_29" , 29, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"IOB" , 30, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"RINT_31" , 31, 1, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 380, "RAZ", 1, 1, 0, 0},
|
|
{"SIZE" , 0, 32, 381, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 381, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 32, 382, "R/W", 0, 0, 0ull, 131072ull},
|
|
{"RESERVED_32_63" , 32, 32, 382, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR_V" , 0, 1, 383, "R/W", 0, 1, 0ull, 0},
|
|
{"END_SWP" , 1, 2, 383, "R/W", 0, 1, 0ull, 0},
|
|
{"CA" , 3, 1, 383, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDR_IDX" , 4, 14, 383, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_31" , 18, 14, 383, "RAZ", 1, 1, 0, 0},
|
|
{"VENDID" , 0, 16, 384, "RO", 0, 0, 6013ull, 6013ull},
|
|
{"DEVID" , 16, 16, 384, "RO", 0, 0, 64ull, 64ull},
|
|
{"ISAE" , 0, 1, 385, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSAE" , 1, 1, 385, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ME" , 2, 1, 385, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SCSE" , 3, 1, 385, "RO", 0, 0, 0ull, 0ull},
|
|
{"MWICE" , 4, 1, 385, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VPS" , 5, 1, 385, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEE" , 6, 1, 385, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ADS" , 7, 1, 385, "RO", 0, 0, 0ull, 0ull},
|
|
{"SEE" , 8, 1, 385, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FBBE" , 9, 1, 385, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I_DIS" , 10, 1, 385, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_18" , 11, 8, 385, "RAZ", 1, 1, 0, 0},
|
|
{"I_STAT" , 19, 1, 385, "RO", 0, 0, 0ull, 0ull},
|
|
{"CLE" , 20, 1, 385, "RO", 0, 0, 1ull, 1ull},
|
|
{"M66" , 21, 1, 385, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_22_22" , 22, 1, 385, "RAZ", 1, 1, 0, 0},
|
|
{"FBB" , 23, 1, 385, "RO", 0, 1, 1ull, 0},
|
|
{"MDPE" , 24, 1, 385, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DEVT" , 25, 2, 385, "RO", 0, 0, 1ull, 1ull},
|
|
{"STA" , 27, 1, 385, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTA" , 28, 1, 385, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RMA" , 29, 1, 385, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SSE" , 30, 1, 385, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPE" , 31, 1, 385, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RID" , 0, 8, 386, "RO", 0, 0, 0ull, 0ull},
|
|
{"CC" , 8, 24, 386, "RO", 0, 0, 733184ull, 733184ull},
|
|
{"CLS" , 0, 8, 387, "R/W", 0, 1, 0ull, 0},
|
|
{"LT" , 8, 8, 387, "R/W", 0, 0, 0ull, 64ull},
|
|
{"HT" , 16, 8, 387, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCOD" , 24, 4, 387, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_29" , 28, 2, 387, "RAZ", 1, 1, 0, 0},
|
|
{"BRB" , 30, 1, 387, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BCAP" , 31, 1, 387, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSPC" , 0, 1, 388, "RO", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 388, "RO", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 388, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBASEZ" , 4, 8, 388, "RO", 0, 0, 0ull, 0ull},
|
|
{"LBASE" , 12, 20, 388, "R/W", 0, 1, 0ull, 0},
|
|
{"HBASE" , 0, 32, 389, "R/W", 0, 1, 0ull, 0},
|
|
{"MSPC" , 0, 1, 390, "RO", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 390, "RO", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 390, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBASEZ" , 4, 23, 390, "RO", 0, 0, 0ull, 0ull},
|
|
{"LBASE" , 27, 5, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"HBASE" , 0, 32, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"MSPC" , 0, 1, 392, "RO", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 392, "RO", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 392, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBASEZ" , 4, 28, 392, "RO", 0, 0, 0ull, 0ull},
|
|
{"HBASEZ" , 0, 7, 393, "RO", 0, 0, 0ull, 0ull},
|
|
{"HBASE" , 7, 25, 393, "R/W", 0, 1, 0ull, 0},
|
|
{"CISP" , 0, 32, 394, "RO", 0, 0, 0ull, 0ull},
|
|
{"SSVID" , 0, 16, 395, "RO", 0, 0, 6013ull, 6013ull},
|
|
{"SSID" , 16, 16, 395, "RO", 0, 0, 1ull, 1ull},
|
|
{"ERBAR_EN" , 0, 1, 396, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_10" , 1, 10, 396, "RAZ", 1, 1, 0, 0},
|
|
{"ERBARZ" , 11, 5, 396, "RO", 0, 0, 0ull, 0ull},
|
|
{"ERBAR" , 16, 16, 396, "R/W", 0, 1, 0ull, 0},
|
|
{"CP" , 0, 8, 397, "RO", 0, 0, 224ull, 224ull},
|
|
{"RESERVED_8_31" , 8, 24, 397, "RAZ", 1, 1, 0, 0},
|
|
{"IL" , 0, 8, 398, "R/W", 0, 1, 0ull, 0},
|
|
{"INTA" , 8, 8, 398, "RO", 0, 0, 1ull, 1ull},
|
|
{"MG" , 16, 8, 398, "RO", 0, 0, 64ull, 64ull},
|
|
{"ML" , 24, 8, 398, "RO", 0, 0, 64ull, 64ull},
|
|
{"MLTD" , 0, 1, 399, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TSWC" , 1, 1, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 399, "RAZ", 1, 1, 0, 0},
|
|
{"DPPMR" , 3, 1, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PBE" , 4, 12, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TILT" , 16, 4, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TSLTE" , 20, 3, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TMAE" , 23, 1, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWTAE" , 24, 1, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWSEN" , 25, 1, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWSEI" , 26, 1, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRTAE" , 27, 1, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRDRS" , 28, 1, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RDSATI" , 29, 1, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRDARD" , 30, 1, 399, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TRDNPR" , 31, 1, 399, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TSCME" , 0, 32, 400, "R/W1C", 0, 1, 0ull, 0},
|
|
{"TDSRPS" , 0, 32, 401, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TDOMC" , 0, 5, 402, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TIDOMC" , 5, 1, 402, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_6" , 6, 1, 402, "RAZ", 1, 1, 0, 0},
|
|
{"TIBDE" , 7, 1, 402, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIBCD" , 8, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_10" , 9, 2, 402, "RAZ", 1, 1, 0, 0},
|
|
{"TMAPES" , 11, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TMDPES" , 12, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TMSE" , 13, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TMEI" , 14, 1, 402, "RO", 0, 0, 0ull, 0ull},
|
|
{"TECI" , 15, 1, 402, "RO", 0, 0, 0ull, 0ull},
|
|
{"TMES" , 16, 8, 402, "RO", 0, 0, 0ull, 0ull},
|
|
{"MDRRMC" , 24, 3, 402, "R/W", 0, 0, 2ull, 2ull},
|
|
{"MDRIMC" , 27, 1, 402, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MDRE" , 28, 1, 402, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MDWE" , 29, 1, 402, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRBCI" , 30, 1, 402, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRBCM" , 31, 1, 402, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MDSP" , 0, 32, 403, "R/W1C", 0, 1, 0ull, 0},
|
|
{"SCMRE" , 0, 32, 404, "R/W1C", 0, 1, 0ull, 0},
|
|
{"MTTV" , 0, 8, 405, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRV" , 8, 8, 405, "R/W", 0, 0, 0ull, 255ull},
|
|
{"MTTA" , 16, 1, 405, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRA" , 17, 1, 405, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FLUSH" , 18, 1, 405, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_19_24" , 19, 6, 405, "RAZ", 1, 1, 0, 0},
|
|
{"MAC" , 25, 7, 405, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PXCID" , 0, 8, 406, "RO", 0, 0, 7ull, 7ull},
|
|
{"NCP" , 8, 8, 406, "RO", 0, 0, 232ull, 232ull},
|
|
{"DPERE" , 16, 1, 406, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROE" , 17, 1, 406, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MMBC" , 18, 2, 406, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MOST" , 20, 3, 406, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_23_31" , 23, 9, 406, "RAZ", 1, 1, 0, 0},
|
|
{"FN" , 0, 3, 407, "RO", 0, 0, 0ull, 0ull},
|
|
{"DN" , 3, 5, 407, "RO", 0, 0, 31ull, 31ull},
|
|
{"BN" , 8, 8, 407, "RO", 0, 1, 17ull, 0},
|
|
{"W64" , 16, 1, 407, "RO", 0, 0, 1ull, 1ull},
|
|
{"M133" , 17, 1, 407, "RO", 0, 0, 1ull, 1ull},
|
|
{"SCD" , 18, 1, 407, "R/W1C", 0, 1, 0ull, 0},
|
|
{"USC" , 19, 1, 407, "R/W1C", 0, 1, 0ull, 0},
|
|
{"DC" , 20, 1, 407, "RO", 0, 0, 0ull, 0ull},
|
|
{"MMRBCD" , 21, 2, 407, "RO", 0, 0, 2ull, 2ull},
|
|
{"MOSTD" , 23, 3, 407, "RO", 0, 0, 3ull, 3ull},
|
|
{"MCRSD" , 26, 3, 407, "RO", 0, 0, 7ull, 7ull},
|
|
{"SCEMR" , 29, 1, 407, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_30_31" , 30, 2, 407, "RAZ", 1, 1, 0, 0},
|
|
{"PMCID" , 0, 8, 408, "RO", 0, 0, 1ull, 1ull},
|
|
{"NCP" , 8, 8, 408, "RO", 0, 0, 240ull, 240ull},
|
|
{"PCIMIV" , 16, 3, 408, "RO", 0, 0, 2ull, 2ull},
|
|
{"PMEC" , 19, 1, 408, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 408, "RAZ", 1, 1, 0, 0},
|
|
{"DSI" , 21, 1, 408, "RO", 0, 0, 0ull, 0ull},
|
|
{"AUXC" , 22, 3, 408, "RO", 0, 0, 0ull, 0ull},
|
|
{"D1S" , 25, 1, 408, "RO", 0, 0, 0ull, 0ull},
|
|
{"D2S" , 26, 1, 408, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMES" , 27, 5, 408, "RO", 0, 0, 0ull, 0ull},
|
|
{"PS" , 0, 2, 409, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_7" , 2, 6, 409, "RAZ", 1, 1, 0, 0},
|
|
{"PMEENS" , 8, 1, 409, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMDS" , 9, 4, 409, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMEDSIA" , 13, 2, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMESS" , 15, 1, 409, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_21" , 16, 6, 409, "RAZ", 1, 1, 0, 0},
|
|
{"BD3H" , 22, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"BPCCEN" , 23, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMDIA" , 24, 8, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSICID" , 0, 8, 410, "RO", 0, 0, 5ull, 5ull},
|
|
{"NCP" , 8, 8, 410, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSIEN" , 16, 1, 410, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MMC" , 17, 3, 410, "RO", 0, 0, 0ull, 0ull},
|
|
{"MME" , 20, 3, 410, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M64" , 23, 1, 410, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_24_31" , 24, 8, 410, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 411, "RAZ", 1, 1, 0, 0},
|
|
{"MSI31T2" , 2, 30, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"MSI" , 0, 32, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"MSIMD" , 0, 16, 413, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_31" , 16, 16, 413, "RAZ", 1, 1, 0, 0},
|
|
{"PCICNT" , 0, 32, 414, "R/W", 0, 1, 0ull, 0},
|
|
{"AP_SPEED" , 32, 2, 414, "RO", 1, 1, 0, 0},
|
|
{"AP_PCIX" , 34, 1, 414, "RO", 1, 1, 0, 0},
|
|
{"HM_SPEED" , 35, 2, 414, "RO", 0, 1, 0ull, 0},
|
|
{"HM_PCIX" , 37, 1, 414, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_38_63" , 38, 26, 414, "RAZ", 1, 1, 0, 0},
|
|
{"BAR2_CAX" , 0, 1, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAR2_ESX" , 1, 2, 415, "R/W", 0, 1, 0ull, 0},
|
|
{"BAR2_ENB" , 3, 1, 415, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TSR_HWM" , 4, 3, 415, "R/W", 0, 1, 1ull, 0},
|
|
{"PMO_FPC" , 7, 3, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMO_AMOD" , 10, 1, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"B12_BIST" , 11, 1, 415, "RO", 0, 0, 0ull, 0ull},
|
|
{"AP_64AD" , 12, 1, 415, "RO", 0, 1, 0ull, 0},
|
|
{"AP_PCIX" , 13, 1, 415, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_14" , 14, 1, 415, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EN_WFILT" , 15, 1, 415, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SCM" , 16, 1, 415, "RO", 0, 1, 0ull, 0},
|
|
{"SCMTYP" , 17, 1, 415, "RO", 0, 1, 0ull, 0},
|
|
{"BAR2PRES" , 18, 1, 415, "R/W", 1, 1, 0, 0},
|
|
{"ERST_N" , 19, 1, 415, "RO", 0, 0, 1ull, 1ull},
|
|
{"BB0" , 20, 1, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB1" , 21, 1, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB_ES" , 22, 2, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB_CA" , 24, 1, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB1_SIZ" , 25, 1, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB1_HOLE" , 26, 3, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_31" , 29, 3, 415, "RAZ", 1, 1, 0, 0},
|
|
{"INC_VAL" , 0, 16, 416, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_31" , 16, 16, 416, "RAZ", 1, 1, 0, 0},
|
|
{"DMA_CNT" , 0, 32, 417, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKT_CNT" , 0, 32, 418, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA_TIME" , 0, 32, 419, "R/W", 0, 1, 0ull, 0},
|
|
{"ICNT" , 0, 32, 420, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ITR_WABT" , 0, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_WABT" , 1, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_WTTO" , 2, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"ITR_ABT" , 3, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_ABT" , 4, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_TTO" , 5, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSI_PER" , 6, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSI_TABT" , 7, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSI_MABT" , 8, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSC_MSG" , 9, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"ITSR_ABT" , 10, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"ISERR" , 11, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"IAPERR" , 12, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"IDPERR" , 13, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RWR" , 14, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RRD" , 15, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"IRSL_INT" , 16, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"IPCNT0" , 17, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"IPCNT1" , 18, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"IPCNT2" , 19, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"IPCNT3" , 20, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"IPTIME0" , 21, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"IPTIME1" , 22, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"IPTIME2" , 23, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"IPTIME3" , 24, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"IDCNT0" , 25, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"IDCNT1" , 26, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"IDTIME0" , 27, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"IDTIME1" , 28, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA0_FI" , 29, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA1_FI" , 30, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"WIN_WR" , 31, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_WR" , 32, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RD" , 33, 1, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_34_63" , 34, 30, 421, "RAZ", 1, 1, 0, 0},
|
|
{"RTR_WABT" , 0, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_WABT" , 1, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_WTTO" , 2, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RTR_ABT" , 3, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_ABT" , 4, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_TTO" , 5, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSI_PER" , 6, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSI_TABT" , 7, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSI_MABT" , 8, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSC_MSG" , 9, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RTSR_ABT" , 10, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RSERR" , 11, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RAPERR" , 12, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RDPERR" , 13, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RWR" , 14, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RRD" , 15, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RRSL_INT" , 16, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RPCNT0" , 17, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RPCNT1" , 18, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RPCNT2" , 19, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RPCNT3" , 20, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RPTIME0" , 21, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RPTIME1" , 22, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RPTIME2" , 23, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RPTIME3" , 24, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RDCNT0" , 25, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RDCNT1" , 26, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RDTIME0" , 27, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RDTIME1" , 28, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA0_FI" , 29, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA1_FI" , 30, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"WIN_WR" , 31, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_WR" , 32, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RD" , 33, 1, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_34_63" , 34, 30, 422, "RAZ", 1, 1, 0, 0},
|
|
{"TR_WABT" , 0, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WABT" , 1, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WTTO" , 2, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TR_ABT" , 3, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_ABT" , 4, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_TTO" , 5, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_PER" , 6, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_TABT" , 7, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_MABT" , 8, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSC_MSG" , 9, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TSR_ABT" , 10, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SERR" , 11, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"APERR" , 12, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPERR" , 13, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RWR" , 14, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RRD" , 15, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSL_INT" , 16, 1, 423, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCNT0" , 17, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT1" , 18, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT2" , 19, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT3" , 20, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME0" , 21, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME1" , 22, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME2" , 23, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME3" , 24, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT0" , 25, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT1" , 26, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME0" , 27, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME1" , 28, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA0_FI" , 29, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1_FI" , 30, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WIN_WR" , 31, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_WR" , 32, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RD" , 33, 1, 423, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 423, "RAZ", 1, 1, 0, 0},
|
|
{"TR_WABT" , 0, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WABT" , 1, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WTTO" , 2, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TR_ABT" , 3, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_ABT" , 4, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_TTO" , 5, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_PER" , 6, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_TABT" , 7, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_MABT" , 8, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSC_MSG" , 9, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TSR_ABT" , 10, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SERR" , 11, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"APERR" , 12, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPERR" , 13, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RWR" , 14, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RRD" , 15, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSL_INT" , 16, 1, 424, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCNT0" , 17, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT1" , 18, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT2" , 19, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT3" , 20, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME0" , 21, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME1" , 22, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME2" , 23, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME3" , 24, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT0" , 25, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT1" , 26, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME0" , 27, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME1" , 28, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA0_FI" , 29, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1_FI" , 30, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WIN_WR" , 31, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_WR" , 32, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RD" , 33, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 424, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 0, 6, 425, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_31" , 6, 26, 425, "R/W", 1, 1, 0, 0},
|
|
{"PTR_CNT" , 0, 16, 426, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_CNT" , 16, 16, 426, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_CNT" , 0, 32, 427, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_CNT" , 0, 32, 428, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_TIME" , 0, 32, 429, "R/W", 0, 1, 0ull, 0},
|
|
{"PREFETCH" , 0, 3, 430, "R/W", 0, 0, 0ull, 2ull},
|
|
{"MIN_DATA" , 3, 6, 430, "R/W", 0, 0, 0ull, 4ull},
|
|
{"RESERVED_9_31" , 9, 23, 430, "RAZ", 1, 1, 0, 0},
|
|
{"PREFETCH" , 0, 3, 431, "R/W", 0, 0, 0ull, 3ull},
|
|
{"MIN_DATA" , 3, 6, 431, "R/W", 0, 0, 0ull, 6ull},
|
|
{"RESERVED_9_31" , 9, 23, 431, "RAZ", 1, 1, 0, 0},
|
|
{"PREFETCH" , 0, 3, 432, "R/W", 0, 0, 0ull, 3ull},
|
|
{"MIN_DATA" , 3, 6, 432, "R/W", 0, 0, 0ull, 6ull},
|
|
{"RESERVED_9_31" , 9, 23, 432, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 31, 433, "R/W", 0, 0, 10000ull, 10000ull},
|
|
{"ENB" , 31, 1, 433, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_32_63" , 32, 32, 433, "RAZ", 1, 1, 0, 0},
|
|
{"SCM" , 0, 32, 434, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 434, "RAZ", 1, 1, 0, 0},
|
|
{"TSR" , 0, 36, 435, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 435, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 436, "RAZ", 1, 1, 0, 0},
|
|
{"RD_ADDR" , 3, 45, 436, "R/W", 0, 1, 0ull, 0},
|
|
{"IOBIT" , 48, 1, 436, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 436, "RAZ", 1, 1, 0, 0},
|
|
{"RD_DATA" , 0, 64, 437, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_0_2" , 0, 3, 438, "RAZ", 1, 1, 0, 0},
|
|
{"WR_ADDR" , 3, 45, 438, "R/W", 0, 1, 0ull, 0},
|
|
{"IOBIT" , 48, 1, 438, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 438, "RAZ", 1, 1, 0, 0},
|
|
{"WR_DATA" , 0, 64, 439, "R/W", 0, 1, 0ull, 0},
|
|
{"WR_MASK" , 0, 8, 440, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 440, "RAZ", 1, 1, 0, 0},
|
|
{"LOWATER" , 0, 5, 441, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_5_7" , 5, 3, 441, "RAZ", 0, 1, 0ull, 0},
|
|
{"HIWATER" , 8, 5, 441, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_13_62" , 13, 50, 441, "RAZ", 0, 1, 0ull, 0},
|
|
{"BCKPRS" , 63, 1, 441, "RO", 0, 0, 0ull, 0ull},
|
|
{"BIST" , 0, 18, 442, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 442, "RAZ", 1, 1, 0, 0},
|
|
{"REFLECT" , 0, 1, 443, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INVRES" , 1, 1, 443, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 443, "RAZ", 1, 1, 0, 0},
|
|
{"IV" , 0, 32, 444, "R/W", 0, 0, 1185899593ull, 1185899593ull},
|
|
{"RESERVED_32_63" , 32, 32, 444, "RAZ", 1, 1, 0, 0},
|
|
{"DPRT" , 0, 16, 445, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UDP" , 16, 1, 445, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP" , 17, 1, 445, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 445, "RAZ", 1, 1, 0, 0},
|
|
{"NIP_SHF" , 0, 3, 446, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_7" , 3, 5, 446, "RAZ", 1, 1, 0, 0},
|
|
{"RAW_SHF" , 8, 3, 446, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_15" , 11, 5, 446, "RAZ", 1, 1, 0, 0},
|
|
{"MAX_L2" , 16, 1, 446, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_UDP" , 17, 1, 446, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TAG_SYN" , 18, 1, 446, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 446, "RAZ", 1, 1, 0, 0},
|
|
{"IP_CHK" , 0, 1, 447, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP_MAL" , 1, 1, 447, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP_HOP" , 2, 1, 447, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP4_OPTS" , 3, 1, 447, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP6_EEXT" , 4, 2, 447, "R/W", 0, 0, 1ull, 3ull},
|
|
{"RESERVED_6_7" , 6, 2, 447, "RAZ", 0, 1, 0ull, 0},
|
|
{"L4_MAL" , 8, 1, 447, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_PRT" , 9, 1, 447, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_CHK" , 10, 1, 447, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_LEN" , 11, 1, 447, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TCP_FLAG" , 12, 1, 447, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L2_MAL" , 13, 1, 447, "R/W", 0, 0, 1ull, 1ull},
|
|
{"VS_QOS" , 14, 1, 447, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VS_WQE" , 15, 1, 447, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IGNRS" , 16, 1, 447, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 447, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PKTDRP" , 0, 1, 448, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CRCERR" , 1, 1, 448, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BCKPRS" , 2, 1, 448, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 3, 1, 448, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BADTAG" , 4, 1, 448, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPRUNT" , 5, 1, 448, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TODOOVR" , 6, 1, 448, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FEPERR" , 7, 1, 448, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BEPERR" , 8, 1, 448, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 448, "RAZ", 1, 1, 0, 0},
|
|
{"PUNYERR" , 12, 1, 448, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 448, "RAZ", 1, 1, 0, 0},
|
|
{"PKTDRP" , 0, 1, 449, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CRCERR" , 1, 1, 449, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BCKPRS" , 2, 1, 449, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 3, 1, 449, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BADTAG" , 4, 1, 449, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPRUNT" , 5, 1, 449, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TODOOVR" , 6, 1, 449, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FEPERR" , 7, 1, 449, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BEPERR" , 8, 1, 449, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 449, "RAZ", 1, 1, 0, 0},
|
|
{"PUNYERR" , 12, 1, 449, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 449, "RAZ", 1, 1, 0, 0},
|
|
{"OFFSET" , 0, 3, 450, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 450, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP" , 0, 7, 451, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 451, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 8, 2, 451, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_11" , 10, 2, 451, "RAZ", 1, 1, 0, 0},
|
|
{"CRC_EN" , 12, 1, 451, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_13_15" , 13, 3, 451, "RAZ", 1, 1, 0, 0},
|
|
{"QOS_VLAN" , 16, 1, 451, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS_DIFF" , 17, 1, 451, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS_VOD" , 18, 1, 451, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_19" , 19, 1, 451, "RAZ", 1, 1, 0, 0},
|
|
{"QOS_WAT" , 20, 4, 451, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS" , 24, 3, 451, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 451, "RAZ", 1, 1, 0, 0},
|
|
{"GRP_WAT" , 28, 4, 451, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INST_HDR" , 32, 1, 451, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DYN_RS" , 33, 1, 451, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TAG_INC" , 34, 2, 451, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RAWDRP" , 36, 1, 451, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 451, "RAZ", 1, 1, 0, 0},
|
|
{"GRP" , 0, 4, 452, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NON_TAG_TYPE" , 4, 2, 452, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_TAG_TYPE" , 6, 2, 452, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_TAG_TYPE" , 8, 2, 452, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP4_TAG_TYPE" , 10, 2, 452, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP6_TAG_TYPE" , 12, 2, 452, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_SRC_FLAG" , 14, 1, 452, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_SRC_FLAG" , 15, 1, 452, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_DST_FLAG" , 16, 1, 452, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_DST_FLAG" , 17, 1, 452, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_PCTL_FLAG" , 18, 1, 452, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_NXTH_FLAG" , 19, 1, 452, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_SPRT_FLAG" , 20, 1, 452, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_SPRT_FLAG" , 21, 1, 452, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_DPRT_FLAG" , 22, 1, 452, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_DPRT_FLAG" , 23, 1, 452, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_PRT_FLAG" , 24, 1, 452, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_VLAN" , 25, 1, 452, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_VS" , 26, 2, 452, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TAG_MODE" , 28, 2, 452, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_30" , 30, 1, 452, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"GRPTAG" , 31, 1, 452, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAGMASK" , 32, 4, 452, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAGBASE" , 36, 4, 452, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 452, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 0, 3, 453, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 453, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 0, 3, 454, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 454, "RAZ", 1, 1, 0, 0},
|
|
{"MATCH_VALUE" , 0, 16, 455, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MATCH_TYPE" , 16, 2, 455, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_19" , 18, 2, 455, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 20, 3, 455, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 455, "RAZ", 1, 1, 0, 0},
|
|
{"GRP" , 24, 4, 455, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_31" , 28, 4, 455, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 32, 16, 455, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 455, "RAZ", 1, 1, 0, 0},
|
|
{"WORD" , 0, 56, 456, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 456, "RAZ", 1, 1, 0, 0},
|
|
{"RST" , 0, 1, 457, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 457, "RAZ", 1, 1, 0, 0},
|
|
{"DRP_OCTS" , 0, 32, 458, "R/W", 0, 1, 0ull, 0},
|
|
{"DRP_PKTS" , 32, 32, 458, "R/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 459, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 459, "RAZ", 1, 1, 0, 0},
|
|
{"RAW" , 0, 32, 460, "R/W", 0, 1, 0ull, 0},
|
|
{"PKTS" , 32, 32, 460, "R/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 0, 32, 461, "R/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 32, 32, 461, "R/W", 0, 1, 0ull, 0},
|
|
{"H64" , 0, 32, 462, "R/W", 0, 1, 0ull, 0},
|
|
{"H65TO127" , 32, 32, 462, "R/W", 0, 1, 0ull, 0},
|
|
{"H128TO255" , 0, 32, 463, "R/W", 0, 1, 0ull, 0},
|
|
{"H256TO511" , 32, 32, 463, "R/W", 0, 1, 0ull, 0},
|
|
{"H512TO1023" , 0, 32, 464, "R/W", 0, 1, 0ull, 0},
|
|
{"H1024TO1518" , 32, 32, 464, "R/W", 0, 1, 0ull, 0},
|
|
{"H1519" , 0, 32, 465, "R/W", 0, 1, 0ull, 0},
|
|
{"FCS" , 32, 32, 465, "R/W", 0, 1, 0ull, 0},
|
|
{"UNDERSZ" , 0, 32, 466, "R/W", 0, 1, 0ull, 0},
|
|
{"FRAG" , 32, 32, 466, "R/W", 0, 1, 0ull, 0},
|
|
{"OVERSZ" , 0, 32, 467, "R/W", 0, 1, 0ull, 0},
|
|
{"JABBER" , 32, 32, 467, "R/W", 0, 1, 0ull, 0},
|
|
{"RDCLR" , 0, 1, 468, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 468, "RAZ", 1, 1, 0, 0},
|
|
{"ERRS" , 0, 16, 469, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 469, "RAZ", 1, 1, 0, 0},
|
|
{"OCTS" , 0, 48, 470, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 470, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 471, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 471, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 8, 472, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 472, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 0, 16, 473, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 473, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 16, 474, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DST" , 16, 16, 474, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 474, "RAZ", 1, 1, 0, 0},
|
|
{"ENTRY" , 0, 62, 475, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_62_62" , 62, 1, 475, "RAZ", 1, 1, 0, 0},
|
|
{"VAL" , 63, 1, 475, "RO", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 32, 476, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 476, "RAZ", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 48, 477, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 477, "RAZ", 1, 1, 0, 0},
|
|
{"SIZE" , 0, 16, 478, "RO", 1, 0, 0, 0ull},
|
|
{"SEGS" , 16, 6, 478, "RO", 1, 0, 0, 0ull},
|
|
{"CMD" , 22, 14, 478, "RO", 1, 0, 0, 0ull},
|
|
{"FAU" , 36, 28, 478, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 479, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 479, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 479, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 479, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 479, "RO", 1, 0, 0, 0ull},
|
|
{"PTRS2" , 0, 17, 480, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 480, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTRS1" , 32, 17, 480, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 480, "RAZ", 1, 0, 0, 0ull},
|
|
{"MOD" , 0, 3, 481, "RO", 1, 0, 0, 0ull},
|
|
{"CNT" , 3, 13, 481, "RO", 1, 0, 0, 0ull},
|
|
{"CHK" , 16, 1, 481, "RO", 1, 0, 0, 0ull},
|
|
{"LEN" , 17, 1, 481, "RO", 1, 0, 0, 0ull},
|
|
{"SOP" , 18, 1, 481, "RO", 1, 0, 0, 0ull},
|
|
{"UID" , 19, 3, 481, "RO", 1, 0, 0, 0ull},
|
|
{"MAJ" , 22, 1, 481, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 481, "RAZ", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 16, 482, "RO", 1, 0, 0, 0ull},
|
|
{"SEGS" , 16, 6, 482, "RO", 1, 0, 0, 0ull},
|
|
{"CMD" , 22, 14, 482, "RO", 1, 0, 0, 0ull},
|
|
{"FAU" , 36, 28, 482, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 483, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 483, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 483, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 483, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 483, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 484, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 484, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 484, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 484, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 484, "RO", 1, 0, 0, 0ull},
|
|
{"DATA" , 0, 64, 485, "RO", 1, 0, 0, 0ull},
|
|
{"MAJOR" , 0, 3, 486, "RO", 1, 0, 0, 0ull},
|
|
{"MINOR" , 3, 2, 486, "RO", 1, 0, 0, 0ull},
|
|
{"WAIT" , 5, 1, 486, "RO", 1, 0, 0, 0ull},
|
|
{"QID_BASE" , 6, 8, 486, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFF" , 14, 4, 486, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFF_MAX" , 18, 4, 486, "RO", 1, 0, 0, 0ull},
|
|
{"QCB_RIDX" , 22, 5, 486, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 27, 3, 486, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 30, 1, 486, "RO", 1, 0, 0, 0ull},
|
|
{"ACTIVE" , 31, 1, 486, "RO", 1, 0, 0, 0ull},
|
|
{"CHK_MODE" , 32, 1, 486, "RO", 1, 0, 0, 0ull},
|
|
{"CHK_ONCE" , 33, 1, 486, "RO", 1, 0, 0, 0ull},
|
|
{"INIT_DWRITE" , 34, 1, 486, "RO", 1, 0, 0, 0ull},
|
|
{"DREAD_SOP" , 35, 1, 486, "RO", 1, 0, 0, 0ull},
|
|
{"UID" , 36, 3, 486, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_OFF" , 39, 6, 486, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_SIZ" , 45, 16, 486, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_SEGS" , 61, 3, 486, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_SEGS" , 0, 3, 487, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_OFF" , 3, 16, 487, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_SIZ" , 19, 16, 487, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_PTR" , 35, 29, 487, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_PTR" , 0, 11, 488, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 488, "RAZ", 1, 0, 0, 0ull},
|
|
{"QCB_RIDX" , 0, 6, 489, "RO", 1, 0, 0, 0ull},
|
|
{"QCB_WIDX" , 6, 6, 489, "RO", 1, 0, 0, 0ull},
|
|
{"BUF_PTR" , 12, 33, 489, "RO", 1, 0, 0, 0ull},
|
|
{"BUF_SIZ" , 45, 13, 489, "RO", 1, 0, 0, 0ull},
|
|
{"TAIL" , 58, 1, 489, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 59, 5, 489, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 0, 3, 490, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_Q" , 3, 1, 490, "RO", 1, 0, 0, 0ull},
|
|
{"S_TAIL" , 4, 1, 490, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 5, 1, 490, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 490, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 8, 20, 490, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 490, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTRS3" , 0, 17, 491, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 491, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTRS0" , 32, 17, 491, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 491, "RAZ", 1, 0, 0, 0ull},
|
|
{"QUEUE" , 0, 7, 492, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT" , 7, 6, 492, "WR0", 1, 0, 0, 0ull},
|
|
{"INDEX" , 13, 3, 492, "WR0", 1, 0, 0, 0ull},
|
|
{"TAIL" , 16, 1, 492, "R/W", 1, 0, 0, 0ull},
|
|
{"BUF_PTR" , 17, 36, 492, "R/W", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 492, "R/W", 1, 0, 0, 0ull},
|
|
{"STATIC_Q" , 61, 1, 492, "R/W", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 62, 1, 492, "R/W", 1, 0, 0, 0ull},
|
|
{"S_TAIL" , 63, 1, 492, "R/W", 1, 0, 0, 0ull},
|
|
{"QID" , 0, 7, 493, "R/W", 1, 0, 0, 0ull},
|
|
{"PID" , 7, 6, 493, "WR0", 1, 0, 0, 0ull},
|
|
{"RESERVED_13_52" , 13, 40, 493, "RAZ", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 493, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_61_63" , 61, 3, 493, "RAZ", 1, 0, 0, 0ull},
|
|
{"DAT_PTR" , 0, 4, 494, "RO", 1, 0, 0, 0ull},
|
|
{"DAT_DAT" , 4, 4, 494, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_QSB" , 8, 3, 494, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_QCB" , 11, 2, 494, "RO", 1, 0, 0, 0ull},
|
|
{"NCB_INB" , 13, 2, 494, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_PSB" , 15, 6, 494, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_NXT" , 21, 1, 494, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_CHK" , 22, 3, 494, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_WIF" , 25, 1, 494, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_STA" , 26, 1, 494, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_CTL" , 27, 3, 494, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_CRC" , 30, 1, 494, "RO", 1, 0, 0, 0ull},
|
|
{"IOB" , 31, 1, 494, "RO", 1, 0, 0, 0ull},
|
|
{"CSR" , 32, 1, 494, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_33_63" , 33, 31, 494, "RAZ", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 13, 495, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_19" , 13, 7, 495, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 20, 3, 495, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 495, "RAZ", 1, 0, 0, 0ull},
|
|
{"REFIN" , 0, 1, 496, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INVRES" , 1, 1, 496, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 496, "RAZ", 1, 1, 0, 0},
|
|
{"ENABLE" , 0, 32, 497, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 497, "RAZ", 1, 0, 0, 0ull},
|
|
{"IV" , 0, 32, 498, "R/W", 0, 0, 1185899593ull, 1185899593ull},
|
|
{"RESERVED_32_63" , 32, 32, 498, "RAZ", 1, 1, 0, 0},
|
|
{"ASSERTS" , 0, 64, 499, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 64, 500, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 64, 501, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 64, 502, "RO", 0, 0, 0ull, 0ull},
|
|
{"PARITY" , 0, 1, 503, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 1, 1, 503, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CURRZERO" , 2, 1, 503, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 503, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENA_PKO" , 0, 1, 504, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENA_DWB" , 1, 1, 504, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STORE_BE" , 2, 1, 504, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 3, 1, 504, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 504, "RAZ", 1, 0, 0, 0ull},
|
|
{"MODE0" , 0, 3, 505, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MODE1" , 3, 3, 505, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 505, "RAZ", 1, 0, 0, 0ull},
|
|
{"PARITY" , 0, 1, 506, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 1, 1, 506, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CURRZERO" , 2, 1, 506, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 506, "RAZ", 1, 0, 0, 0ull},
|
|
{"MODE" , 0, 2, 507, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 507, "RAZ", 1, 0, 0, 0ull},
|
|
{"QID7" , 0, 1, 508, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDX3" , 1, 1, 508, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 508, "RAZ", 1, 0, 0, 0ull},
|
|
{"INDEX" , 0, 8, 509, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 8, 8, 509, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 509, "RAZ", 1, 0, 0, 0ull},
|
|
{"ADR0" , 0, 1, 510, "RO", 0, 0, 0ull, 0ull},
|
|
{"ADR1" , 1, 1, 510, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEND0" , 2, 1, 510, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEND1" , 3, 1, 510, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBR0" , 4, 1, 510, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBR1" , 5, 1, 510, "RO", 0, 0, 0ull, 0ull},
|
|
{"FIDX" , 6, 1, 510, "RO", 0, 0, 0ull, 0ull},
|
|
{"INDEX" , 7, 1, 510, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBT" , 8, 1, 510, "RO", 0, 0, 0ull, 0ull},
|
|
{"CAM" , 9, 1, 510, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_15" , 10, 6, 510, "RAZ", 1, 1, 0, 0},
|
|
{"PP" , 16, 16, 510, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 510, "RAZ", 1, 1, 0, 0},
|
|
{"DS_PC" , 0, 32, 511, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 511, "RAZ", 1, 1, 0, 0},
|
|
{"SBE" , 0, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DBE" , 1, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SBE_IE" , 2, 1, 512, "R/W", 0, 1, 0ull, 0},
|
|
{"DBE_IE" , 3, 1, 512, "R/W", 0, 1, 0ull, 0},
|
|
{"SYN" , 4, 5, 512, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_9_11" , 9, 3, 512, "RAZ", 1, 1, 0, 0},
|
|
{"RPE" , 12, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPE_IE" , 13, 1, 512, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_15" , 14, 2, 512, "RAZ", 1, 1, 0, 0},
|
|
{"IOP" , 16, 13, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_31" , 29, 3, 512, "RAZ", 1, 1, 0, 0},
|
|
{"IOP_IE" , 32, 13, 512, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_45_63" , 45, 19, 512, "RAZ", 1, 1, 0, 0},
|
|
{"NBR_THR" , 0, 5, 513, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PFR_DIS" , 5, 1, 513, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 513, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 32, 514, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 514, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 32, 515, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 515, "RAZ", 1, 1, 0, 0},
|
|
{"NOS_CNT" , 0, 12, 516, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_12_63" , 12, 52, 516, "RAZ", 1, 1, 0, 0},
|
|
{"NW_TIM" , 0, 10, 517, "R/W", 0, 0, 0ull, 1023ull},
|
|
{"RESERVED_10_63" , 10, 54, 517, "RAZ", 1, 1, 0, 0},
|
|
{"RST_MSK" , 0, 8, 518, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 518, "RAZ", 1, 1, 0, 0},
|
|
{"GRP_MSK" , 0, 16, 519, "R/W", 0, 0, 65535ull, 65535ull},
|
|
{"QOS0_PRI" , 16, 4, 519, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS1_PRI" , 20, 4, 519, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS2_PRI" , 24, 4, 519, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS3_PRI" , 28, 4, 519, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS4_PRI" , 32, 4, 519, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS5_PRI" , 36, 4, 519, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS6_PRI" , 40, 4, 519, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS7_PRI" , 44, 4, 519, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 519, "RAZ", 1, 1, 0, 0},
|
|
{"RND" , 0, 8, 520, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P1" , 8, 8, 520, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P2" , 16, 8, 520, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P3" , 24, 8, 520, "R/W", 0, 1, 255ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 520, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_THR" , 0, 11, 521, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_11_11" , 11, 1, 521, "RAZ", 1, 1, 0, 0},
|
|
{"MAX_THR" , 12, 11, 521, "R/W", 0, 1, 2047ull, 0},
|
|
{"RESERVED_23_23" , 23, 1, 521, "RAZ", 1, 1, 0, 0},
|
|
{"FREE_CNT" , 24, 12, 521, "RO", 0, 1, 2027ull, 0},
|
|
{"BUF_CNT" , 36, 12, 521, "RO", 0, 1, 0ull, 0},
|
|
{"DES_CNT" , 48, 12, 521, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 521, "RAZ", 1, 1, 0, 0},
|
|
{"TS_PC" , 0, 32, 522, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 522, "RAZ", 1, 1, 0, 0},
|
|
{"WA_PC" , 0, 32, 523, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 523, "RAZ", 1, 1, 0, 0},
|
|
{"WA_PC" , 0, 32, 524, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 524, "RAZ", 1, 1, 0, 0},
|
|
{"WQ_INT" , 0, 16, 525, "R/W1C", 0, 1, 0ull, 0},
|
|
{"IQ_DIS" , 16, 16, 525, "R/W1", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 525, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 12, 526, "RO", 0, 1, 0ull, 0},
|
|
{"DS_CNT" , 12, 12, 526, "RO", 0, 1, 0ull, 0},
|
|
{"TC_CNT" , 24, 4, 526, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_63" , 28, 36, 526, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 527, "RAZ", 1, 1, 0, 0},
|
|
{"PC_THR" , 8, 20, 527, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_31" , 28, 4, 527, "RAZ", 1, 1, 0, 0},
|
|
{"PC" , 32, 28, 527, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 527, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_THR" , 0, 11, 528, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_11_11" , 11, 1, 528, "RAZ", 1, 1, 0, 0},
|
|
{"DS_THR" , 12, 11, 528, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_23_23" , 23, 1, 528, "RAZ", 1, 1, 0, 0},
|
|
{"TC_THR" , 24, 4, 528, "R/W", 0, 1, 0ull, 0},
|
|
{"TC_EN" , 28, 1, 528, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 528, "RAZ", 1, 1, 0, 0},
|
|
{"WS_PC" , 0, 32, 529, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 529, "RAZ", 1, 1, 0, 0},
|
|
{"MEM" , 0, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"RRC" , 1, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 530, "RAZ", 1, 1, 0, 0},
|
|
{"ENT_EN" , 0, 1, 531, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNG_EN" , 1, 1, 531, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNM_RST" , 2, 1, 531, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNG_RST" , 3, 1, 531, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EXP_ENT" , 4, 1, 531, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENT_SEL" , 5, 4, 531, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 531, "RAZ", 1, 1, 0, 0},
|
|
{"PHASE" , 0, 8, 532, "R/W", 0, 0, 100ull, 100ull},
|
|
{"SAMPLE" , 8, 4, 532, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PREAMBLE" , 12, 1, 532, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CLK_IDLE" , 13, 1, 532, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_14" , 14, 1, 532, "RAZ", 1, 1, 0, 0},
|
|
{"SAMPLE_MODE" , 15, 1, 532, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SAMPLE_HI" , 16, 5, 532, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_63" , 21, 43, 532, "RAZ", 1, 1, 0, 0},
|
|
{"REG_ADR" , 0, 5, 533, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 533, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_ADR" , 8, 5, 533, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_13_15" , 13, 3, 533, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_OP" , 16, 1, 533, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_17_63" , 17, 47, 533, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 534, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 534, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 535, "RO", 0, 1, 0ull, 0},
|
|
{"VAL" , 16, 1, 535, "RO", 0, 1, 0ull, 0},
|
|
{"PENDING" , 17, 1, 535, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 535, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 536, "R/W", 0, 1, 0ull, 0},
|
|
{"VAL" , 16, 1, 536, "RO", 0, 1, 0ull, 0},
|
|
{"PENDING" , 17, 1, 536, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 536, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 537, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 537, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STAT0" , 0, 1, 538, "RO", 0, 0, 0ull, 0ull},
|
|
{"STAT1" , 1, 1, 538, "RO", 0, 0, 0ull, 0ull},
|
|
{"STAT2" , 2, 1, 538, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 538, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SRXDLCK" , 0, 1, 539, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RCVTRN" , 1, 1, 539, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DRPTRN" , 2, 1, 539, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SNDTRN" , 3, 1, 539, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STATRCV" , 4, 1, 539, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STATDRV" , 5, 1, 539, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RUNBIST" , 6, 1, 539, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLKDLY" , 7, 5, 539, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_12_15" , 12, 4, 539, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SEETRN" , 16, 1, 539, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 539, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_3" , 0, 4, 540, "RAZ", 0, 1, 0ull, 0},
|
|
{"D4CLK0" , 4, 1, 540, "R/W1C", 0, 1, 0ull, 0},
|
|
{"D4CLK1" , 5, 1, 540, "R/W1C", 0, 1, 0ull, 0},
|
|
{"S4CLK0" , 6, 1, 540, "R/W1C", 0, 1, 0ull, 0},
|
|
{"S4CLK1" , 7, 1, 540, "R/W1C", 0, 1, 0ull, 0},
|
|
{"SRXTRN" , 8, 1, 540, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_9_9" , 9, 1, 540, "RAZ", 0, 1, 0ull, 0},
|
|
{"STXCAL" , 10, 1, 540, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_11_63" , 11, 53, 540, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DLLDIS" , 0, 1, 541, "R/W", 1, 0, 0, 0ull},
|
|
{"DLLFRC" , 1, 1, 541, "WR0", 1, 0, 0, 0ull},
|
|
{"OFFDLY" , 2, 6, 541, "R/W", 1, 0, 0, 0ull},
|
|
{"BITSEL" , 8, 5, 541, "R/W", 1, 1, 0, 0},
|
|
{"OFFSET" , 13, 5, 541, "R/W", 1, 1, 0, 0},
|
|
{"MUX" , 18, 1, 541, "WR0", 1, 1, 0, 0},
|
|
{"INC" , 19, 1, 541, "WR0", 1, 1, 0, 0},
|
|
{"DEC" , 20, 1, 541, "WR0", 1, 1, 0, 0},
|
|
{"CLRDLY" , 21, 1, 541, "WR0", 1, 1, 0, 0},
|
|
{"RESERVED_22_23" , 22, 2, 541, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SSTEP" , 24, 1, 541, "R/W", 1, 0, 0, 0ull},
|
|
{"SSTEP_GO" , 25, 1, 541, "WR0", 1, 1, 0, 0},
|
|
{"RESERVED_26_27" , 26, 2, 541, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FALL8" , 28, 1, 541, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FALLNOP" , 29, 1, 541, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_63" , 30, 34, 541, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OFFSET" , 0, 5, 542, "RO", 0, 1, 0ull, 0},
|
|
{"MUXSEL" , 5, 2, 542, "RO", 0, 1, 0ull, 0},
|
|
{"UNXTERM" , 7, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TESTRES" , 8, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 542, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SRX4CMP" , 0, 10, 543, "R/W", 0, 0, 239ull, 239ull},
|
|
{"RESERVED_10_15" , 10, 6, 543, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STX4PCMP" , 16, 4, 543, "R/W", 0, 0, 3ull, 3ull},
|
|
{"STX4NCMP" , 20, 4, 543, "R/W", 0, 0, 12ull, 12ull},
|
|
{"RESERVED_24_63" , 24, 40, 543, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ERRCNT" , 0, 4, 544, "R/W", 0, 0, 0ull, 3ull},
|
|
{"RESERVED_4_5" , 4, 2, 544, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DIPPAY" , 6, 1, 544, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DIPCLS" , 7, 1, 544, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 8, 1, 544, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 544, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRT" , 0, 8, 545, "RO", 0, 0, 0ull, 0ull},
|
|
{"RSVOP" , 8, 4, 545, "RO", 0, 0, 0ull, 0ull},
|
|
{"CALBNK" , 12, 2, 545, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_30" , 14, 17, 545, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MUL" , 31, 1, 545, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 545, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 0, 1, 546, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ABNORM" , 1, 1, 546, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_3" , 2, 2, 546, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SPIOVR" , 4, 1, 546, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLSERR" , 5, 1, 546, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRWNNG" , 6, 1, 546, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 7, 1, 546, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TPAOVR" , 8, 1, 546, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DIPERR" , 9, 1, 546, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SYNCERR" , 10, 1, 546, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CALERR" , 11, 1, 546, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 546, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 0, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ABNORM" , 1, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_3" , 2, 2, 547, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SPIOVR" , 4, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CLSERR" , 5, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DRWNNG" , 6, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 7, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TPAOVR" , 8, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DIPERR" , 9, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SYNCERR" , 10, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CALERR" , 11, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_30" , 12, 19, 547, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SPF" , 31, 1, 547, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 547, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 0, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ABNORM" , 1, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_3" , 2, 2, 548, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SPIOVR" , 4, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLSERR" , 5, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRWNNG" , 6, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 7, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TPAOVR" , 8, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DIPERR" , 9, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SYNCERR" , 10, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CALERR" , 11, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 548, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 0, 32, 549, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 549, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX" , 0, 32, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 550, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRTSEL" , 0, 4, 551, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 551, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MUX_EN" , 0, 1, 552, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MACRO_EN" , 1, 1, 552, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAXDIST" , 2, 5, 552, "R/W", 0, 0, 0ull, 8ull},
|
|
{"SET_BOOT" , 7, 1, 552, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLR_BOOT" , 8, 1, 552, "R/W", 0, 0, 0ull, 0ull},
|
|
{"JITTER" , 9, 3, 552, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TRNTEST" , 12, 1, 552, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 552, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"INF_EN" , 0, 1, 553, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_2" , 1, 2, 553, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ST_EN" , 3, 1, 553, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PRTS" , 4, 4, 553, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 553, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IGNORE" , 0, 16, 554, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 554, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRT0" , 0, 4, 555, "R/W", 1, 1, 0, 0},
|
|
{"PRT1" , 4, 4, 555, "R/W", 1, 1, 0, 0},
|
|
{"PRT2" , 8, 4, 555, "R/W", 1, 1, 0, 0},
|
|
{"PRT3" , 12, 4, 555, "R/W", 1, 1, 0, 0},
|
|
{"ODDPAR" , 16, 1, 555, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_17_63" , 17, 47, 555, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LEN" , 0, 7, 556, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_7" , 7, 1, 556, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"M" , 8, 8, 556, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 556, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 4, 557, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OPC" , 4, 4, 557, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MOD" , 8, 4, 557, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SOP" , 12, 1, 557, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EOP" , 13, 1, 557, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 557, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DAT" , 0, 64, 558, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_2" , 0, 3, 559, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IGNTPA" , 3, 1, 559, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_4" , 4, 1, 559, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MINTRN" , 5, 1, 559, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 559, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 0, 32, 560, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 560, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"INF_EN" , 0, 1, 561, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_2" , 1, 2, 561, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ST_EN" , 3, 1, 561, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 561, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DIPMAX" , 0, 4, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMMAX" , 4, 4, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 562, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IGNTPA" , 0, 16, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 563, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CALPAR0" , 0, 1, 564, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CALPAR1" , 1, 1, 564, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OVRBST" , 2, 1, 564, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DATOVR" , 3, 1, 564, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DIPERR" , 4, 1, 564, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NOSYNC" , 5, 1, 564, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UNXFRM" , 6, 1, 564, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMERR" , 7, 1, 564, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 564, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CALPAR0" , 0, 1, 565, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CALPAR1" , 1, 1, 565, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OVRBST" , 2, 1, 565, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DATOVR" , 3, 1, 565, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DIPERR" , 4, 1, 565, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NOSYNC" , 5, 1, 565, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UNXFRM" , 6, 1, 565, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FRMERR" , 7, 1, 565, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SYNCERR" , 8, 1, 565, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 565, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CALPAR0" , 0, 1, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CALPAR1" , 1, 1, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OVRBST" , 2, 1, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DATOVR" , 3, 1, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DIPERR" , 4, 1, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NOSYNC" , 5, 1, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UNXFRM" , 6, 1, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMERR" , 7, 1, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 566, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MINB" , 0, 9, 567, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 567, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PRT0" , 0, 4, 568, "R/W", 1, 1, 0, 0},
|
|
{"PRT1" , 4, 4, 568, "R/W", 1, 1, 0, 0},
|
|
{"PRT2" , 8, 4, 568, "R/W", 1, 1, 0, 0},
|
|
{"PRT3" , 12, 4, 568, "R/W", 1, 1, 0, 0},
|
|
{"ODDPAR" , 16, 1, 568, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_17_63" , 17, 47, 568, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX_T" , 0, 16, 569, "R/W", 0, 1, 0ull, 0},
|
|
{"ALPHA" , 16, 16, 569, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 569, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LEN" , 0, 7, 570, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_7" , 7, 1, 570, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"M" , 8, 8, 570, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 570, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 0, 32, 571, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 571, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 0, 32, 572, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 572, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"BCKPRS" , 0, 4, 573, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLR" , 4, 1, 573, "WR0", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 573, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 0, 32, 574, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 574, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"INTERVAL" , 0, 22, 575, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 575, "RAZ", 1, 0, 0, 0ull},
|
|
{"COUNT" , 24, 22, 575, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_46_46" , 46, 1, 575, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENA" , 47, 1, 575, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 575, "RAZ", 1, 0, 0, 0ull},
|
|
{"BSIZE" , 0, 20, 576, "RO", 1, 0, 0, 0ull},
|
|
{"BASE" , 20, 31, 576, "RO", 1, 0, 0, 0ull},
|
|
{"BUCKET" , 51, 13, 576, "RO", 1, 0, 0, 0ull},
|
|
{"BUCKET" , 0, 7, 577, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 577, "RAZ", 1, 0, 0, 0ull},
|
|
{"CSIZE" , 8, 13, 577, "RO", 1, 0, 0, 0ull},
|
|
{"CPOOL" , 21, 3, 577, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 577, "RAZ", 1, 0, 0, 0ull},
|
|
{"RING" , 0, 4, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NUM_BUCKETS" , 4, 20, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIRST_BUCKET" , 24, 31, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_55_63" , 55, 9, 578, "RAZ", 1, 0, 0, 0ull},
|
|
{"RING" , 0, 4, 579, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTERVAL" , 4, 22, 579, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WORDS_PER_CHUNK" , 26, 13, 579, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 39, 3, 579, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENABLE" , 42, 1, 579, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_43_63" , 43, 21, 579, "RAZ", 1, 0, 0, 0ull},
|
|
{"CTL" , 0, 1, 580, "RO", 1, 0, 0, 0ull},
|
|
{"NCB" , 1, 1, 580, "RO", 1, 0, 0, 0ull},
|
|
{"STA" , 2, 2, 580, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 580, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 16, 581, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 581, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENABLE_TIMERS" , 0, 1, 582, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENABLE_DWB" , 1, 1, 582, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 2, 1, 582, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 582, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 16, 583, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 583, "RAZ", 1, 0, 0, 0ull},
|
|
{"INDEX" , 0, 8, 584, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 8, 8, 584, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 584, "RAZ", 1, 0, 0, 0ull},
|
|
{"TDF0" , 0, 1, 585, "RO", 0, 0, 0ull, 0ull},
|
|
{"TDF1" , 1, 1, 585, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCF" , 2, 1, 585, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 585, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ENA" , 0, 1, 586, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WRAP" , 1, 1, 586, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRIG_CTL" , 2, 2, 586, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIME_GRN" , 4, 3, 586, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FULL_THR" , 7, 2, 586, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CIU_TRG" , 9, 1, 586, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CIU_THR" , 10, 1, 586, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_TRG" , 11, 1, 586, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_THR" , 12, 1, 586, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_ENA" , 13, 1, 586, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IGNORE_O" , 14, 1, 586, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 586, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WPTR" , 0, 8, 587, "RO", 0, 0, 0ull, 0ull},
|
|
{"RPTR" , 8, 8, 587, "RO", 0, 0, 0ull, 0ull},
|
|
{"CYCLES" , 16, 48, 587, "RO", 0, 0, 0ull, 0ull},
|
|
{"WPTR" , 0, 10, 588, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_11" , 10, 2, 588, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RPTR" , 12, 10, 588, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 588, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CYCLES" , 24, 40, 588, "RO", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 589, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 589, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 590, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 590, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 591, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 591, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 591, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 591, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 591, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 591, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 591, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 591, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 591, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 591, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 591, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 591, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 591, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 591, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 591, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 591, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SAA" , 16, 1, 591, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_17_63" , 17, 47, 591, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 592, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 592, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 592, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 592, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 592, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 592, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 592, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 592, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 592, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 592, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 592, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 592, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 593, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 593, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 593, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 593, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 593, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 593, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CIU_TRG" , 0, 1, 594, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CIU_THR" , 1, 1, 594, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MCD0_TRG" , 2, 1, 594, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MCD0_THR" , 3, 1, 594, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 594, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DATA" , 0, 64, 595, "RO", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 596, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 596, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 597, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 597, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 598, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 598, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 598, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 598, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 598, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 598, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 598, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 598, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 598, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 598, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 598, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 598, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 598, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 598, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 598, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 598, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SAA" , 16, 1, 598, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_17_63" , 17, 47, 598, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 599, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 599, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 599, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 599, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 599, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 599, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 599, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 599, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 599, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 599, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 599, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 599, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 600, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 600, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 600, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 600, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 600, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 600, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 601, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 601, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 602, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 602, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 603, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 603, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 603, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 603, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 603, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 603, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 603, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 603, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 603, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 603, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 603, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 603, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 603, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 603, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 603, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 603, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SAA" , 16, 1, 603, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_17_63" , 17, 47, 603, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 604, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 604, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 604, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 604, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 604, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 604, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 604, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 604, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 604, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 604, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 604, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 604, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 605, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 605, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 605, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 605, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 605, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 605, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ZIP_CTL" , 0, 4, 606, "RO", 1, 0, 0, 0ull},
|
|
{"ZIP_CORE" , 4, 27, 606, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 606, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 33, 607, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 33, 13, 607, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 46, 3, 607, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 49, 9, 607, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_58_63" , 58, 6, 607, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 0, 1, 608, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FORCECLK" , 1, 1, 608, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 608, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DISABLED" , 0, 1, 609, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_7" , 1, 7, 609, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CTXSIZE" , 8, 12, 609, "RO", 0, 0, 1536ull, 1536ull},
|
|
{"ONFSIZE" , 20, 12, 609, "RO", 0, 0, 512ull, 512ull},
|
|
{"DEPTH" , 32, 16, 609, "RO", 0, 0, 31744ull, 31744ull},
|
|
{"RESERVED_48_63" , 48, 16, 609, "RAZ", 1, 0, 0, 0ull},
|
|
{"ASSERTS" , 0, 14, 610, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 610, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 0, 1, 611, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 611, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 0, 1, 612, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 612, "RAZ", 1, 0, 0, 0ull},
|
|
{NULL,0,0,0,0,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn56xxp1[] = {
|
|
/* name , ---------------type, bits, off, #field, fld of */
|
|
{"cvmx_agl_gmx_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 11, 0},
|
|
{"cvmx_agl_gmx_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 1, 2, 11},
|
|
{"cvmx_agl_gmx_drv_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 6, 13},
|
|
{"cvmx_agl_gmx_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 3, 3, 19},
|
|
{"cvmx_agl_gmx_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 7, 22},
|
|
{"cvmx_agl_gmx_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 5, 1, 29},
|
|
{"cvmx_agl_gmx_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 1, 30},
|
|
{"cvmx_agl_gmx_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 7, 1, 31},
|
|
{"cvmx_agl_gmx_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 8, 1, 32},
|
|
{"cvmx_agl_gmx_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 9, 1, 33},
|
|
{"cvmx_agl_gmx_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 1, 34},
|
|
{"cvmx_agl_gmx_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 11, 2, 35},
|
|
{"cvmx_agl_gmx_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 4, 37},
|
|
{"cvmx_agl_gmx_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 13, 2, 41},
|
|
{"cvmx_agl_gmx_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 10, 43},
|
|
{"cvmx_agl_gmx_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 15, 11, 53},
|
|
{"cvmx_agl_gmx_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 2, 64},
|
|
{"cvmx_agl_gmx_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 17, 2, 66},
|
|
{"cvmx_agl_gmx_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 18, 2, 68},
|
|
{"cvmx_agl_gmx_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 19, 19, 70},
|
|
{"cvmx_agl_gmx_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 20, 19, 89},
|
|
{"cvmx_agl_gmx_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 21, 2, 108},
|
|
{"cvmx_agl_gmx_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 22, 2, 110},
|
|
{"cvmx_agl_gmx_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 23, 2, 112},
|
|
{"cvmx_agl_gmx_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 24, 2, 114},
|
|
{"cvmx_agl_gmx_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 25, 2, 116},
|
|
{"cvmx_agl_gmx_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 26, 2, 118},
|
|
{"cvmx_agl_gmx_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 27, 2, 120},
|
|
{"cvmx_agl_gmx_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 28, 2, 122},
|
|
{"cvmx_agl_gmx_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 29, 2, 124},
|
|
{"cvmx_agl_gmx_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 30, 2, 126},
|
|
{"cvmx_agl_gmx_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 31, 2, 128},
|
|
{"cvmx_agl_gmx_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 32, 2, 130},
|
|
{"cvmx_agl_gmx_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 33, 4, 132},
|
|
{"cvmx_agl_gmx_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 34, 2, 136},
|
|
{"cvmx_agl_gmx_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 35, 2, 138},
|
|
{"cvmx_agl_gmx_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 36, 2, 140},
|
|
{"cvmx_agl_gmx_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 37, 4, 142},
|
|
{"cvmx_agl_gmx_rx_tx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 38, 4, 146},
|
|
{"cvmx_agl_gmx_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 39, 2, 150},
|
|
{"cvmx_agl_gmx_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 40, 3, 152},
|
|
{"cvmx_agl_gmx_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 41, 5, 155},
|
|
{"cvmx_agl_gmx_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 42, 3, 160},
|
|
{"cvmx_agl_gmx_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 43, 2, 163},
|
|
{"cvmx_agl_gmx_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 44, 2, 165},
|
|
{"cvmx_agl_gmx_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 45, 2, 167},
|
|
{"cvmx_agl_gmx_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 46, 2, 169},
|
|
{"cvmx_agl_gmx_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 47, 2, 171},
|
|
{"cvmx_agl_gmx_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 48, 2, 173},
|
|
{"cvmx_agl_gmx_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 49, 2, 175},
|
|
{"cvmx_agl_gmx_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 50, 2, 177},
|
|
{"cvmx_agl_gmx_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 51, 2, 179},
|
|
{"cvmx_agl_gmx_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 2, 181},
|
|
{"cvmx_agl_gmx_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 53, 2, 183},
|
|
{"cvmx_agl_gmx_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 54, 2, 185},
|
|
{"cvmx_agl_gmx_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 55, 2, 187},
|
|
{"cvmx_agl_gmx_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 56, 2, 189},
|
|
{"cvmx_agl_gmx_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 57, 2, 191},
|
|
{"cvmx_agl_gmx_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 58, 2, 193},
|
|
{"cvmx_agl_gmx_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 59, 2, 195},
|
|
{"cvmx_agl_gmx_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 60, 2, 197},
|
|
{"cvmx_agl_gmx_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 61, 2, 199},
|
|
{"cvmx_agl_gmx_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 62, 2, 201},
|
|
{"cvmx_agl_gmx_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 63, 3, 203},
|
|
{"cvmx_agl_gmx_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 64, 10, 206},
|
|
{"cvmx_agl_gmx_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 65, 10, 216},
|
|
{"cvmx_agl_gmx_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 66, 2, 226},
|
|
{"cvmx_agl_gmx_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 67, 2, 228},
|
|
{"cvmx_agl_gmx_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 68, 6, 230},
|
|
{"cvmx_agl_gmx_tx_pause_pkt_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 69, 2, 236},
|
|
{"cvmx_agl_gmx_tx_pause_pkt_type", CVMX_CSR_DB_TYPE_RSL, 64, 70, 2, 238},
|
|
{"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 71, 2, 240},
|
|
{"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 72, 2, 242},
|
|
{"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 73, 2, 244},
|
|
{"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 74, 2, 246},
|
|
{"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 75, 21, 248},
|
|
{"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 100, 2, 269},
|
|
{"cvmx_ciu_int#_en4_0" , CVMX_CSR_DB_TYPE_NCB, 64, 125, 21, 271},
|
|
{"cvmx_ciu_int#_en4_1" , CVMX_CSR_DB_TYPE_NCB, 64, 137, 2, 292},
|
|
{"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 149, 21, 294},
|
|
{"cvmx_ciu_int#_sum4" , CVMX_CSR_DB_TYPE_NCB, 64, 174, 21, 315},
|
|
{"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 186, 2, 336},
|
|
{"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 187, 2, 338},
|
|
{"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 199, 2, 340},
|
|
{"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 211, 2, 342},
|
|
{"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 212, 2, 344},
|
|
{"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 213, 2, 346},
|
|
{"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 214, 1, 348},
|
|
{"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 226, 3, 349},
|
|
{"cvmx_ciu_qlm_dcok" , CVMX_CSR_DB_TYPE_NCB, 64, 227, 2, 352},
|
|
{"cvmx_ciu_qlm_jtgc" , CVMX_CSR_DB_TYPE_NCB, 64, 228, 5, 354},
|
|
{"cvmx_ciu_qlm_jtgd" , CVMX_CSR_DB_TYPE_NCB, 64, 229, 6, 359},
|
|
{"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 230, 2, 365},
|
|
{"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 231, 2, 367},
|
|
{"cvmx_ciu_soft_prst1" , CVMX_CSR_DB_TYPE_NCB, 64, 232, 2, 369},
|
|
{"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 233, 2, 371},
|
|
{"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 234, 3, 373},
|
|
{"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 238, 7, 376},
|
|
{"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 250, 6, 383},
|
|
{"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 251, 7, 389},
|
|
{"cvmx_fpa_fpf#_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 252, 3, 396},
|
|
{"cvmx_fpa_fpf#_size" , CVMX_CSR_DB_TYPE_RSL, 64, 259, 2, 399},
|
|
{"cvmx_fpa_fpf0_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 266, 3, 401},
|
|
{"cvmx_fpa_fpf0_size" , CVMX_CSR_DB_TYPE_RSL, 64, 267, 2, 404},
|
|
{"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 268, 29, 406},
|
|
{"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 269, 29, 435},
|
|
{"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 270, 2, 464},
|
|
{"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 278, 2, 466},
|
|
{"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 286, 3, 468},
|
|
{"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 287, 3, 471},
|
|
{"cvmx_fpa_wart_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 288, 2, 474},
|
|
{"cvmx_fpa_wart_status" , CVMX_CSR_DB_TYPE_RSL, 64, 289, 2, 476},
|
|
{"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 290, 7, 478},
|
|
{"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 292, 2, 485},
|
|
{"cvmx_gmx#_clk_en" , CVMX_CSR_DB_TYPE_RSL, 64, 294, 2, 487},
|
|
{"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 296, 7, 489},
|
|
{"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 298, 2, 496},
|
|
{"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 300, 10, 498},
|
|
{"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 308, 1, 508},
|
|
{"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 316, 1, 509},
|
|
{"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 324, 1, 510},
|
|
{"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 332, 1, 511},
|
|
{"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 340, 1, 512},
|
|
{"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 348, 1, 513},
|
|
{"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 356, 2, 514},
|
|
{"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 364, 4, 516},
|
|
{"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 372, 2, 520},
|
|
{"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 380, 9, 522},
|
|
{"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 388, 10, 531},
|
|
{"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 396, 2, 541},
|
|
{"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 404, 25, 543},
|
|
{"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 412, 25, 568},
|
|
{"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 420, 2, 593},
|
|
{"cvmx_gmx#_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 428, 2, 595},
|
|
{"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 436, 2, 597},
|
|
{"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 444, 2, 599},
|
|
{"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 452, 2, 601},
|
|
{"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 460, 2, 603},
|
|
{"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 468, 2, 605},
|
|
{"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 476, 2, 607},
|
|
{"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 484, 2, 609},
|
|
{"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 492, 2, 611},
|
|
{"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 500, 2, 613},
|
|
{"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 508, 2, 615},
|
|
{"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 516, 4, 617},
|
|
{"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 524, 2, 621},
|
|
{"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 532, 2, 623},
|
|
{"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 540, 2, 625},
|
|
{"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 548, 4, 627},
|
|
{"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 550, 2, 631},
|
|
{"cvmx_gmx#_rx_xaui_bad_col" , CVMX_CSR_DB_TYPE_RSL, 64, 552, 5, 633},
|
|
{"cvmx_gmx#_rx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 554, 2, 638},
|
|
{"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 556, 2, 640},
|
|
{"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 564, 3, 642},
|
|
{"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 566, 5, 645},
|
|
{"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 574, 2, 650},
|
|
{"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 582, 3, 652},
|
|
{"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 590, 2, 655},
|
|
{"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 598, 2, 657},
|
|
{"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 606, 2, 659},
|
|
{"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 614, 2, 661},
|
|
{"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 622, 2, 663},
|
|
{"cvmx_gmx#_tx#_sgmii_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 630, 2, 665},
|
|
{"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 638, 2, 667},
|
|
{"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 646, 2, 669},
|
|
{"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 654, 2, 671},
|
|
{"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 662, 2, 673},
|
|
{"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 670, 2, 675},
|
|
{"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 678, 2, 677},
|
|
{"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 686, 2, 679},
|
|
{"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 694, 2, 681},
|
|
{"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 702, 2, 683},
|
|
{"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 710, 2, 685},
|
|
{"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 718, 2, 687},
|
|
{"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 726, 2, 689},
|
|
{"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 734, 2, 691},
|
|
{"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 742, 2, 693},
|
|
{"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 750, 2, 695},
|
|
{"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 752, 2, 697},
|
|
{"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 754, 2, 699},
|
|
{"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 756, 3, 701},
|
|
{"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 758, 8, 704},
|
|
{"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 760, 8, 712},
|
|
{"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 762, 2, 720},
|
|
{"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 764, 2, 722},
|
|
{"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 766, 6, 724},
|
|
{"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 768, 2, 730},
|
|
{"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 770, 2, 732},
|
|
{"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 772, 2, 734},
|
|
{"cvmx_gmx#_tx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 774, 9, 736},
|
|
{"cvmx_gmx#_xaui_ext_loopback" , CVMX_CSR_DB_TYPE_RSL, 64, 776, 3, 745},
|
|
{"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 778, 9, 748},
|
|
{"cvmx_gpio_clk_gen#" , CVMX_CSR_DB_TYPE_NCB, 64, 794, 2, 757},
|
|
{"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 798, 2, 759},
|
|
{"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 799, 2, 761},
|
|
{"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 800, 2, 763},
|
|
{"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 801, 2, 765},
|
|
{"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 802, 19, 767},
|
|
{"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 803, 6, 786},
|
|
{"cvmx_iob_dwb_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 804, 3, 792},
|
|
{"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 805, 3, 795},
|
|
{"cvmx_iob_i2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 806, 3, 798},
|
|
{"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 807, 5, 801},
|
|
{"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 808, 5, 806},
|
|
{"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 809, 1, 811},
|
|
{"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 810, 1, 812},
|
|
{"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 811, 7, 813},
|
|
{"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 812, 7, 820},
|
|
{"cvmx_iob_n2c_l2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 813, 3, 827},
|
|
{"cvmx_iob_n2c_rsp_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 814, 3, 830},
|
|
{"cvmx_iob_outb_com_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 815, 3, 833},
|
|
{"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 816, 5, 836},
|
|
{"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 817, 5, 841},
|
|
{"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 818, 1, 846},
|
|
{"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 819, 1, 847},
|
|
{"cvmx_iob_outb_fpa_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 820, 3, 848},
|
|
{"cvmx_iob_outb_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 821, 3, 851},
|
|
{"cvmx_iob_p2c_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 822, 3, 854},
|
|
{"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 823, 2, 857},
|
|
{"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 824, 2, 859},
|
|
{"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 825, 2, 861},
|
|
{"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 826, 2, 863},
|
|
{"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 827, 19, 865},
|
|
{"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 828, 2, 884},
|
|
{"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 829, 1, 886},
|
|
{"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 830, 15, 887},
|
|
{"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 831, 13, 902},
|
|
{"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 832, 13, 915},
|
|
{"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 833, 2, 928},
|
|
{"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 834, 2, 930},
|
|
{"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 835, 2, 932},
|
|
{"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 836, 3, 934},
|
|
{"cvmx_ipd_port#_bp_page_cnt2" , CVMX_CSR_DB_TYPE_NCB, 64, 844, 3, 937},
|
|
{"cvmx_ipd_port_bp_counters2_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 848, 2, 940},
|
|
{"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 852, 2, 942},
|
|
{"cvmx_ipd_port_qos_#_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 860, 2, 944},
|
|
{"cvmx_ipd_port_qos_int#" , CVMX_CSR_DB_TYPE_NCB, 64, 956, 1, 946},
|
|
{"cvmx_ipd_port_qos_int_enb#" , CVMX_CSR_DB_TYPE_NCB, 64, 959, 1, 947},
|
|
{"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 962, 6, 948},
|
|
{"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 963, 5, 954},
|
|
{"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 964, 6, 959},
|
|
{"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 965, 7, 965},
|
|
{"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 966, 2, 972},
|
|
{"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 974, 2, 974},
|
|
{"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 975, 3, 976},
|
|
{"cvmx_ipd_red_port_enable2" , CVMX_CSR_DB_TYPE_NCB, 64, 976, 2, 979},
|
|
{"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 977, 5, 981},
|
|
{"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 985, 3, 986},
|
|
{"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 986, 4, 989},
|
|
{"cvmx_ipd_sub_port_qos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 987, 3, 993},
|
|
{"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 988, 2, 996},
|
|
{"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 989, 2, 998},
|
|
{"cvmx_key_bist_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 990, 4, 1000},
|
|
{"cvmx_key_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 991, 3, 1004},
|
|
{"cvmx_key_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 992, 5, 1007},
|
|
{"cvmx_key_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 993, 5, 1012},
|
|
{"cvmx_l2c_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 994, 7, 1017},
|
|
{"cvmx_l2c_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 995, 11, 1024},
|
|
{"cvmx_l2c_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 996, 8, 1035},
|
|
{"cvmx_l2c_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 997, 15, 1043},
|
|
{"cvmx_l2c_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 998, 8, 1058},
|
|
{"cvmx_l2c_dut" , CVMX_CSR_DB_TYPE_RSL, 64, 999, 5, 1066},
|
|
{"cvmx_l2c_grpwrr0" , CVMX_CSR_DB_TYPE_RSL, 64, 1000, 2, 1071},
|
|
{"cvmx_l2c_grpwrr1" , CVMX_CSR_DB_TYPE_RSL, 64, 1001, 2, 1073},
|
|
{"cvmx_l2c_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1002, 10, 1075},
|
|
{"cvmx_l2c_int_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 1003, 10, 1085},
|
|
{"cvmx_l2c_lckbase" , CVMX_CSR_DB_TYPE_RSL, 64, 1004, 4, 1095},
|
|
{"cvmx_l2c_lckoff" , CVMX_CSR_DB_TYPE_RSL, 64, 1005, 2, 1099},
|
|
{"cvmx_l2c_lfb0" , CVMX_CSR_DB_TYPE_RSL, 64, 1006, 14, 1101},
|
|
{"cvmx_l2c_lfb1" , CVMX_CSR_DB_TYPE_RSL, 64, 1007, 19, 1115},
|
|
{"cvmx_l2c_lfb2" , CVMX_CSR_DB_TYPE_RSL, 64, 1008, 3, 1134},
|
|
{"cvmx_l2c_lfb3" , CVMX_CSR_DB_TYPE_RSL, 64, 1009, 3, 1137},
|
|
{"cvmx_l2c_oob" , CVMX_CSR_DB_TYPE_RSL, 64, 1010, 3, 1140},
|
|
{"cvmx_l2c_oob1" , CVMX_CSR_DB_TYPE_RSL, 64, 1011, 6, 1143},
|
|
{"cvmx_l2c_oob2" , CVMX_CSR_DB_TYPE_RSL, 64, 1012, 6, 1149},
|
|
{"cvmx_l2c_oob3" , CVMX_CSR_DB_TYPE_RSL, 64, 1013, 6, 1155},
|
|
{"cvmx_l2c_pfc#" , CVMX_CSR_DB_TYPE_RSL, 64, 1014, 2, 1161},
|
|
{"cvmx_l2c_pfctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1018, 17, 1163},
|
|
{"cvmx_l2c_ppgrp" , CVMX_CSR_DB_TYPE_RSL, 64, 1019, 13, 1180},
|
|
{"cvmx_l2c_spar0" , CVMX_CSR_DB_TYPE_RSL, 64, 1020, 5, 1193},
|
|
{"cvmx_l2c_spar1" , CVMX_CSR_DB_TYPE_RSL, 64, 1021, 5, 1198},
|
|
{"cvmx_l2c_spar2" , CVMX_CSR_DB_TYPE_RSL, 64, 1022, 5, 1203},
|
|
{"cvmx_l2c_spar4" , CVMX_CSR_DB_TYPE_RSL, 64, 1023, 2, 1208},
|
|
{"cvmx_l2d_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 1024, 3, 1210},
|
|
{"cvmx_l2d_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 1025, 2, 1213},
|
|
{"cvmx_l2d_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 1026, 2, 1215},
|
|
{"cvmx_l2d_bst3" , CVMX_CSR_DB_TYPE_RSL, 64, 1027, 2, 1217},
|
|
{"cvmx_l2d_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1028, 7, 1219},
|
|
{"cvmx_l2d_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1029, 5, 1226},
|
|
{"cvmx_l2d_fsyn0" , CVMX_CSR_DB_TYPE_RSL, 64, 1030, 3, 1231},
|
|
{"cvmx_l2d_fsyn1" , CVMX_CSR_DB_TYPE_RSL, 64, 1031, 3, 1234},
|
|
{"cvmx_l2d_fus0" , CVMX_CSR_DB_TYPE_RSL, 64, 1032, 2, 1237},
|
|
{"cvmx_l2d_fus1" , CVMX_CSR_DB_TYPE_RSL, 64, 1033, 2, 1239},
|
|
{"cvmx_l2d_fus2" , CVMX_CSR_DB_TYPE_RSL, 64, 1034, 2, 1241},
|
|
{"cvmx_l2d_fus3" , CVMX_CSR_DB_TYPE_RSL, 64, 1035, 6, 1243},
|
|
{"cvmx_l2t_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1036, 14, 1249},
|
|
{"cvmx_led_blink" , CVMX_CSR_DB_TYPE_RSL, 64, 1037, 2, 1263},
|
|
{"cvmx_led_clk_phase" , CVMX_CSR_DB_TYPE_RSL, 64, 1038, 2, 1265},
|
|
{"cvmx_led_cylon" , CVMX_CSR_DB_TYPE_RSL, 64, 1039, 2, 1267},
|
|
{"cvmx_led_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1040, 2, 1269},
|
|
{"cvmx_led_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1041, 2, 1271},
|
|
{"cvmx_led_polarity" , CVMX_CSR_DB_TYPE_RSL, 64, 1042, 2, 1273},
|
|
{"cvmx_led_prt" , CVMX_CSR_DB_TYPE_RSL, 64, 1043, 2, 1275},
|
|
{"cvmx_led_prt_fmt" , CVMX_CSR_DB_TYPE_RSL, 64, 1044, 2, 1277},
|
|
{"cvmx_led_prt_status#" , CVMX_CSR_DB_TYPE_RSL, 64, 1045, 2, 1279},
|
|
{"cvmx_led_udd_cnt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1053, 2, 1281},
|
|
{"cvmx_led_udd_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 1055, 2, 1283},
|
|
{"cvmx_led_udd_dat_clr#" , CVMX_CSR_DB_TYPE_RSL, 64, 1057, 2, 1285},
|
|
{"cvmx_led_udd_dat_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 1059, 2, 1287},
|
|
{"cvmx_lmc#_bist_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1061, 2, 1289},
|
|
{"cvmx_lmc#_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1063, 8, 1291},
|
|
{"cvmx_lmc#_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1065, 7, 1299},
|
|
{"cvmx_lmc#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1067, 19, 1306},
|
|
{"cvmx_lmc#_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 1069, 8, 1325},
|
|
{"cvmx_lmc#_dclk_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1071, 2, 1333},
|
|
{"cvmx_lmc#_dclk_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1073, 2, 1335},
|
|
{"cvmx_lmc#_dclk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1075, 5, 1337},
|
|
{"cvmx_lmc#_ddr2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1077, 18, 1342},
|
|
{"cvmx_lmc#_delay_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1079, 6, 1360},
|
|
{"cvmx_lmc#_dll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1081, 5, 1366},
|
|
{"cvmx_lmc#_dual_memcfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1083, 5, 1371},
|
|
{"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 1085, 5, 1376},
|
|
{"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1087, 6, 1381},
|
|
{"cvmx_lmc#_ifb_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1089, 2, 1387},
|
|
{"cvmx_lmc#_ifb_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1091, 2, 1389},
|
|
{"cvmx_lmc#_mem_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 1093, 14, 1391},
|
|
{"cvmx_lmc#_mem_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 1095, 9, 1405},
|
|
{"cvmx_lmc#_ops_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1097, 2, 1414},
|
|
{"cvmx_lmc#_ops_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1099, 2, 1416},
|
|
{"cvmx_lmc#_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1101, 12, 1418},
|
|
{"cvmx_lmc#_pll_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1103, 6, 1430},
|
|
{"cvmx_lmc#_read_level_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1105, 7, 1436},
|
|
{"cvmx_lmc#_read_level_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1107, 4, 1443},
|
|
{"cvmx_lmc#_read_level_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 1109, 11, 1447},
|
|
{"cvmx_lmc#_rodt_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1117, 6, 1458},
|
|
{"cvmx_lmc#_rodt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1119, 9, 1464},
|
|
{"cvmx_lmc#_wodt_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 1121, 5, 1473},
|
|
{"cvmx_lmc#_wodt_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 1123, 5, 1478},
|
|
{"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 1125, 5, 1483},
|
|
{"cvmx_mio_boot_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 1126, 3, 1488},
|
|
{"cvmx_mio_boot_dma_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1127, 10, 1491},
|
|
{"cvmx_mio_boot_dma_int#" , CVMX_CSR_DB_TYPE_RSL, 64, 1130, 3, 1501},
|
|
{"cvmx_mio_boot_dma_int_en#" , CVMX_CSR_DB_TYPE_RSL, 64, 1133, 3, 1504},
|
|
{"cvmx_mio_boot_dma_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 1136, 15, 1507},
|
|
{"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1139, 3, 1522},
|
|
{"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1140, 3, 1525},
|
|
{"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1141, 3, 1528},
|
|
{"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1142, 5, 1531},
|
|
{"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1144, 1, 1536},
|
|
{"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1145, 13, 1537},
|
|
{"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 1153, 13, 1550},
|
|
{"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1161, 6, 1563},
|
|
{"cvmx_mio_fus_bnk_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 1162, 1, 1569},
|
|
{"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 1166, 2, 1570},
|
|
{"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 1167, 2, 1572},
|
|
{"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 1168, 13, 1574},
|
|
{"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 1169, 8, 1587},
|
|
{"cvmx_mio_fus_ema" , CVMX_CSR_DB_TYPE_RSL, 64, 1170, 4, 1595},
|
|
{"cvmx_mio_fus_pdf" , CVMX_CSR_DB_TYPE_RSL, 64, 1171, 1, 1599},
|
|
{"cvmx_mio_fus_pll" , CVMX_CSR_DB_TYPE_RSL, 64, 1172, 3, 1600},
|
|
{"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 1173, 2, 1603},
|
|
{"cvmx_mio_fus_prog_times" , CVMX_CSR_DB_TYPE_RSL, 64, 1174, 6, 1605},
|
|
{"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1175, 7, 1611},
|
|
{"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 1176, 4, 1618},
|
|
{"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1177, 2, 1622},
|
|
{"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1178, 2, 1624},
|
|
{"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1179, 13, 1626},
|
|
{"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 1181, 12, 1639},
|
|
{"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 1183, 3, 1651},
|
|
{"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 1185, 3, 1654},
|
|
{"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 1187, 2, 1657},
|
|
{"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 1189, 2, 1659},
|
|
{"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 1191, 2, 1661},
|
|
{"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1193, 7, 1663},
|
|
{"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 1195, 2, 1670},
|
|
{"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 1197, 7, 1672},
|
|
{"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 1199, 4, 1679},
|
|
{"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1201, 8, 1683},
|
|
{"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 1203, 9, 1691},
|
|
{"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1205, 7, 1700},
|
|
{"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 1207, 9, 1707},
|
|
{"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 1209, 2, 1716},
|
|
{"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1211, 2, 1718},
|
|
{"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 1213, 4, 1720},
|
|
{"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1215, 2, 1724},
|
|
{"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 1217, 2, 1726},
|
|
{"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 1219, 2, 1728},
|
|
{"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 1221, 4, 1730},
|
|
{"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 1223, 2, 1734},
|
|
{"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 1225, 2, 1736},
|
|
{"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 1227, 2, 1738},
|
|
{"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1229, 2, 1740},
|
|
{"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 1231, 2, 1742},
|
|
{"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1233, 2, 1744},
|
|
{"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 1235, 6, 1746},
|
|
{"cvmx_mix#_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 1237, 5, 1752},
|
|
{"cvmx_mix#_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1238, 8, 1757},
|
|
{"cvmx_mix#_intena" , CVMX_CSR_DB_TYPE_NCB, 64, 1239, 8, 1765},
|
|
{"cvmx_mix#_ircnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1240, 2, 1773},
|
|
{"cvmx_mix#_irhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 1241, 3, 1775},
|
|
{"cvmx_mix#_iring1" , CVMX_CSR_DB_TYPE_NCB, 64, 1242, 5, 1778},
|
|
{"cvmx_mix#_iring2" , CVMX_CSR_DB_TYPE_NCB, 64, 1243, 4, 1783},
|
|
{"cvmx_mix#_isr" , CVMX_CSR_DB_TYPE_NCB, 64, 1244, 8, 1787},
|
|
{"cvmx_mix#_orcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1245, 2, 1795},
|
|
{"cvmx_mix#_orhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 1246, 2, 1797},
|
|
{"cvmx_mix#_oring1" , CVMX_CSR_DB_TYPE_NCB, 64, 1247, 5, 1799},
|
|
{"cvmx_mix#_oring2" , CVMX_CSR_DB_TYPE_NCB, 64, 1248, 4, 1804},
|
|
{"cvmx_mix#_remcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1249, 4, 1808},
|
|
{"cvmx_npei_bar1_index#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 1250, 5, 1812},
|
|
{"cvmx_npei_bist_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1282, 59, 1817},
|
|
{"cvmx_npei_ctl_port0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1283, 17, 1876},
|
|
{"cvmx_npei_ctl_port1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1284, 17, 1893},
|
|
{"cvmx_npei_ctl_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1285, 6, 1910},
|
|
{"cvmx_npei_ctl_status2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1286, 11, 1916},
|
|
{"cvmx_npei_data_out_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1287, 5, 1927},
|
|
{"cvmx_npei_dbg_data" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1288, 8, 1932},
|
|
{"cvmx_npei_dbg_select" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1289, 2, 1940},
|
|
{"cvmx_npei_dma#_counts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1290, 3, 1942},
|
|
{"cvmx_npei_dma#_dbell" , CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 1295, 2, 1945},
|
|
{"cvmx_npei_dma#_ibuff_saddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1300, 3, 1947},
|
|
{"cvmx_npei_dma#_naddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1305, 2, 1950},
|
|
{"cvmx_npei_dma0_int_level" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1310, 2, 1952},
|
|
{"cvmx_npei_dma1_int_level" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1311, 2, 1954},
|
|
{"cvmx_npei_dma_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1312, 2, 1956},
|
|
{"cvmx_npei_dma_control" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1313, 16, 1958},
|
|
{"cvmx_npei_dma_state1_p1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1314, 11, 1974},
|
|
{"cvmx_npei_dma_state2_p1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1315, 6, 1985},
|
|
{"cvmx_npei_dma_state3_p1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1316, 5, 1991},
|
|
{"cvmx_npei_dma_state4_p1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1317, 5, 1996},
|
|
{"cvmx_npei_dma_state5_p1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1318, 3, 2001},
|
|
{"cvmx_npei_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1319, 63, 2004},
|
|
{"cvmx_npei_int_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1320, 62, 2067},
|
|
{"cvmx_npei_int_info" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1321, 3, 2129},
|
|
{"cvmx_npei_int_sum" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1322, 60, 2132},
|
|
{"cvmx_npei_last_win_rdata0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1323, 1, 2192},
|
|
{"cvmx_npei_last_win_rdata1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1324, 1, 2193},
|
|
{"cvmx_npei_mem_access_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1325, 3, 2194},
|
|
{"cvmx_npei_mem_access_subid#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1326, 11, 2197},
|
|
{"cvmx_npei_msi_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1342, 1, 2208},
|
|
{"cvmx_npei_msi_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1343, 1, 2209},
|
|
{"cvmx_npei_msi_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1344, 1, 2210},
|
|
{"cvmx_npei_msi_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1345, 1, 2211},
|
|
{"cvmx_npei_msi_rcv0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1346, 1, 2212},
|
|
{"cvmx_npei_msi_rcv1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1347, 1, 2213},
|
|
{"cvmx_npei_msi_rcv2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1348, 1, 2214},
|
|
{"cvmx_npei_msi_rcv3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1349, 1, 2215},
|
|
{"cvmx_npei_msi_rd_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1350, 3, 2216},
|
|
{"cvmx_npei_msi_wr_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1351, 3, 2219},
|
|
{"cvmx_npei_pcie_msi_rcv" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1352, 2, 2222},
|
|
{"cvmx_npei_pcie_msi_rcv_b1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1353, 3, 2224},
|
|
{"cvmx_npei_pcie_msi_rcv_b2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1354, 3, 2227},
|
|
{"cvmx_npei_pcie_msi_rcv_b3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1355, 3, 2230},
|
|
{"cvmx_npei_rsl_int_blocks" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1356, 29, 2233},
|
|
{"cvmx_npei_scratch_1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1357, 1, 2262},
|
|
{"cvmx_npei_state1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1358, 4, 2263},
|
|
{"cvmx_npei_state2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1359, 7, 2267},
|
|
{"cvmx_npei_state3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1360, 5, 2274},
|
|
{"cvmx_npei_win_rd_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 1361, 4, 2279},
|
|
{"cvmx_npei_win_rd_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 1362, 1, 2283},
|
|
{"cvmx_npei_win_wr_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 1363, 4, 2284},
|
|
{"cvmx_npei_win_wr_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 1364, 1, 2288},
|
|
{"cvmx_npei_win_wr_mask" , CVMX_CSR_DB_TYPE_PEXP, 64, 1365, 2, 2289},
|
|
{"cvmx_npei_window_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1366, 2, 2291},
|
|
{"cvmx_pcieep_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1367, 2, 2293},
|
|
{"cvmx_pcieep_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1368, 24, 2295},
|
|
{"cvmx_pcieep_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1369, 4, 2319},
|
|
{"cvmx_pcieep_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1370, 5, 2323},
|
|
{"cvmx_pcieep_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1371, 5, 2328},
|
|
{"cvmx_pcieep_cfg004_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1372, 2, 2333},
|
|
{"cvmx_pcieep_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1373, 1, 2335},
|
|
{"cvmx_pcieep_cfg005_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1374, 1, 2336},
|
|
{"cvmx_pcieep_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1375, 5, 2337},
|
|
{"cvmx_pcieep_cfg006_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1376, 2, 2342},
|
|
{"cvmx_pcieep_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1377, 1, 2344},
|
|
{"cvmx_pcieep_cfg007_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1378, 1, 2345},
|
|
{"cvmx_pcieep_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1379, 4, 2346},
|
|
{"cvmx_pcieep_cfg008_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1380, 2, 2350},
|
|
{"cvmx_pcieep_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1381, 2, 2352},
|
|
{"cvmx_pcieep_cfg009_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1382, 1, 2354},
|
|
{"cvmx_pcieep_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1383, 1, 2355},
|
|
{"cvmx_pcieep_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1384, 2, 2356},
|
|
{"cvmx_pcieep_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1385, 3, 2358},
|
|
{"cvmx_pcieep_cfg012_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1386, 2, 2361},
|
|
{"cvmx_pcieep_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1387, 2, 2363},
|
|
{"cvmx_pcieep_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1388, 4, 2365},
|
|
{"cvmx_pcieep_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1389, 10, 2369},
|
|
{"cvmx_pcieep_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1390, 12, 2379},
|
|
{"cvmx_pcieep_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1391, 7, 2391},
|
|
{"cvmx_pcieep_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1392, 2, 2398},
|
|
{"cvmx_pcieep_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1393, 1, 2400},
|
|
{"cvmx_pcieep_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1394, 2, 2401},
|
|
{"cvmx_pcieep_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1395, 7, 2403},
|
|
{"cvmx_pcieep_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1396, 11, 2410},
|
|
{"cvmx_pcieep_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1397, 19, 2421},
|
|
{"cvmx_pcieep_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1398, 11, 2440},
|
|
{"cvmx_pcieep_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1399, 17, 2451},
|
|
{"cvmx_pcieep_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1400, 12, 2468},
|
|
{"cvmx_pcieep_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1401, 22, 2480},
|
|
{"cvmx_pcieep_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1402, 3, 2502},
|
|
{"cvmx_pcieep_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1403, 3, 2505},
|
|
{"cvmx_pcieep_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1404, 1, 2508},
|
|
{"cvmx_pcieep_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1405, 1, 2509},
|
|
{"cvmx_pcieep_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1406, 1, 2510},
|
|
{"cvmx_pcieep_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1407, 1, 2511},
|
|
{"cvmx_pcieep_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1408, 3, 2512},
|
|
{"cvmx_pcieep_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1409, 14, 2515},
|
|
{"cvmx_pcieep_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1410, 14, 2529},
|
|
{"cvmx_pcieep_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1411, 14, 2543},
|
|
{"cvmx_pcieep_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1412, 9, 2557},
|
|
{"cvmx_pcieep_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1413, 9, 2566},
|
|
{"cvmx_pcieep_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1414, 6, 2575},
|
|
{"cvmx_pcieep_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1415, 1, 2581},
|
|
{"cvmx_pcieep_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1416, 1, 2582},
|
|
{"cvmx_pcieep_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1417, 1, 2583},
|
|
{"cvmx_pcieep_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1418, 1, 2584},
|
|
{"cvmx_pcieep_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1419, 2, 2585},
|
|
{"cvmx_pcieep_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1420, 1, 2587},
|
|
{"cvmx_pcieep_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1421, 6, 2588},
|
|
{"cvmx_pcieep_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1422, 6, 2594},
|
|
{"cvmx_pcieep_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1423, 13, 2600},
|
|
{"cvmx_pcieep_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1424, 5, 2613},
|
|
{"cvmx_pcieep_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1425, 8, 2618},
|
|
{"cvmx_pcieep_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1426, 19, 2626},
|
|
{"cvmx_pcieep_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1427, 3, 2645},
|
|
{"cvmx_pcieep_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1428, 1, 2648},
|
|
{"cvmx_pcieep_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1429, 1, 2649},
|
|
{"cvmx_pcieep_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1430, 3, 2650},
|
|
{"cvmx_pcieep_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1431, 3, 2653},
|
|
{"cvmx_pcieep_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1432, 3, 2656},
|
|
{"cvmx_pcieep_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1433, 4, 2659},
|
|
{"cvmx_pcieep_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1434, 4, 2663},
|
|
{"cvmx_pcieep_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1435, 4, 2667},
|
|
{"cvmx_pcieep_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1436, 7, 2671},
|
|
{"cvmx_pcieep_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1437, 5, 2678},
|
|
{"cvmx_pcieep_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1438, 5, 2683},
|
|
{"cvmx_pcieep_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1439, 4, 2688},
|
|
{"cvmx_pcieep_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1440, 4, 2692},
|
|
{"cvmx_pcieep_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1441, 4, 2696},
|
|
{"cvmx_pcieep_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1442, 1, 2700},
|
|
{"cvmx_pcieep_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1443, 1, 2701},
|
|
{"cvmx_pcierc#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1444, 2, 2702},
|
|
{"cvmx_pcierc#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1446, 24, 2704},
|
|
{"cvmx_pcierc#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1448, 4, 2728},
|
|
{"cvmx_pcierc#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1450, 5, 2732},
|
|
{"cvmx_pcierc#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1452, 1, 2737},
|
|
{"cvmx_pcierc#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1454, 1, 2738},
|
|
{"cvmx_pcierc#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1456, 4, 2739},
|
|
{"cvmx_pcierc#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1458, 17, 2743},
|
|
{"cvmx_pcierc#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1460, 4, 2760},
|
|
{"cvmx_pcierc#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1462, 6, 2764},
|
|
{"cvmx_pcierc#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1464, 1, 2770},
|
|
{"cvmx_pcierc#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1466, 1, 2771},
|
|
{"cvmx_pcierc#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1468, 2, 2772},
|
|
{"cvmx_pcierc#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1470, 2, 2774},
|
|
{"cvmx_pcierc#_cfg014" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1472, 1, 2776},
|
|
{"cvmx_pcierc#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1474, 15, 2777},
|
|
{"cvmx_pcierc#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1476, 10, 2792},
|
|
{"cvmx_pcierc#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1478, 12, 2802},
|
|
{"cvmx_pcierc#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1480, 7, 2814},
|
|
{"cvmx_pcierc#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1482, 2, 2821},
|
|
{"cvmx_pcierc#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1484, 1, 2823},
|
|
{"cvmx_pcierc#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1486, 2, 2824},
|
|
{"cvmx_pcierc#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1488, 7, 2826},
|
|
{"cvmx_pcierc#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1490, 11, 2833},
|
|
{"cvmx_pcierc#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1492, 19, 2844},
|
|
{"cvmx_pcierc#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1494, 11, 2863},
|
|
{"cvmx_pcierc#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1496, 20, 2874},
|
|
{"cvmx_pcierc#_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1498, 12, 2894},
|
|
{"cvmx_pcierc#_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1500, 22, 2906},
|
|
{"cvmx_pcierc#_cfg035" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1502, 8, 2928},
|
|
{"cvmx_pcierc#_cfg036" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1504, 4, 2936},
|
|
{"cvmx_pcierc#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1506, 3, 2940},
|
|
{"cvmx_pcierc#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1508, 3, 2943},
|
|
{"cvmx_pcierc#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1510, 1, 2946},
|
|
{"cvmx_pcierc#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1512, 1, 2947},
|
|
{"cvmx_pcierc#_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1514, 1, 2948},
|
|
{"cvmx_pcierc#_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1516, 1, 2949},
|
|
{"cvmx_pcierc#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1518, 3, 2950},
|
|
{"cvmx_pcierc#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1520, 14, 2953},
|
|
{"cvmx_pcierc#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1522, 14, 2967},
|
|
{"cvmx_pcierc#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1524, 14, 2981},
|
|
{"cvmx_pcierc#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1526, 9, 2995},
|
|
{"cvmx_pcierc#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1528, 9, 3004},
|
|
{"cvmx_pcierc#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1530, 6, 3013},
|
|
{"cvmx_pcierc#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1532, 1, 3019},
|
|
{"cvmx_pcierc#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1534, 1, 3020},
|
|
{"cvmx_pcierc#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1536, 1, 3021},
|
|
{"cvmx_pcierc#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1538, 1, 3022},
|
|
{"cvmx_pcierc#_cfg075" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1540, 4, 3023},
|
|
{"cvmx_pcierc#_cfg076" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1542, 9, 3027},
|
|
{"cvmx_pcierc#_cfg077" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1544, 2, 3036},
|
|
{"cvmx_pcierc#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1546, 2, 3038},
|
|
{"cvmx_pcierc#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1548, 1, 3040},
|
|
{"cvmx_pcierc#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1550, 6, 3041},
|
|
{"cvmx_pcierc#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1552, 6, 3047},
|
|
{"cvmx_pcierc#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1554, 13, 3053},
|
|
{"cvmx_pcierc#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1556, 5, 3066},
|
|
{"cvmx_pcierc#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1558, 8, 3071},
|
|
{"cvmx_pcierc#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1560, 19, 3079},
|
|
{"cvmx_pcierc#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1562, 3, 3098},
|
|
{"cvmx_pcierc#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1564, 1, 3101},
|
|
{"cvmx_pcierc#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1566, 1, 3102},
|
|
{"cvmx_pcierc#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1568, 3, 3103},
|
|
{"cvmx_pcierc#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1570, 3, 3106},
|
|
{"cvmx_pcierc#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1572, 3, 3109},
|
|
{"cvmx_pcierc#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1574, 4, 3112},
|
|
{"cvmx_pcierc#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1576, 4, 3116},
|
|
{"cvmx_pcierc#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1578, 4, 3120},
|
|
{"cvmx_pcierc#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1580, 7, 3124},
|
|
{"cvmx_pcierc#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1582, 5, 3131},
|
|
{"cvmx_pcierc#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1584, 5, 3136},
|
|
{"cvmx_pcierc#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1586, 4, 3141},
|
|
{"cvmx_pcierc#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1588, 4, 3145},
|
|
{"cvmx_pcierc#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1590, 4, 3149},
|
|
{"cvmx_pcierc#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1592, 1, 3153},
|
|
{"cvmx_pcierc#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1594, 1, 3154},
|
|
{"cvmx_pcs#_an#_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1596, 9, 3155},
|
|
{"cvmx_pcs#_an#_ext_st_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1604, 6, 3164},
|
|
{"cvmx_pcs#_an#_lp_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1612, 9, 3170},
|
|
{"cvmx_pcs#_an#_results_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1620, 6, 3179},
|
|
{"cvmx_pcs#_int#_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1628, 13, 3185},
|
|
{"cvmx_pcs#_int#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1636, 13, 3198},
|
|
{"cvmx_pcs#_link#_timer_count_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1644, 2, 3211},
|
|
{"cvmx_pcs#_log_anl#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1652, 4, 3213},
|
|
{"cvmx_pcs#_misc#_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1660, 8, 3217},
|
|
{"cvmx_pcs#_mr#_control_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1668, 13, 3225},
|
|
{"cvmx_pcs#_mr#_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1676, 17, 3238},
|
|
{"cvmx_pcs#_rx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1684, 7, 3255},
|
|
{"cvmx_pcs#_rx#_sync_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1692, 3, 3262},
|
|
{"cvmx_pcs#_sgm#_an_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1700, 8, 3265},
|
|
{"cvmx_pcs#_sgm#_lp_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1708, 7, 3273},
|
|
{"cvmx_pcs#_tx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1716, 4, 3280},
|
|
{"cvmx_pcs#_tx_rx#_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1724, 5, 3284},
|
|
{"cvmx_pcsx#_10gbx_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1732, 8, 3289},
|
|
{"cvmx_pcsx#_bist_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1734, 2, 3297},
|
|
{"cvmx_pcsx#_bit_lock_status_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1736, 5, 3299},
|
|
{"cvmx_pcsx#_control1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1738, 10, 3304},
|
|
{"cvmx_pcsx#_control2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1740, 2, 3314},
|
|
{"cvmx_pcsx#_int_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1742, 7, 3316},
|
|
{"cvmx_pcsx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1744, 7, 3323},
|
|
{"cvmx_pcsx#_log_anl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1746, 6, 3330},
|
|
{"cvmx_pcsx#_misc_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1748, 5, 3336},
|
|
{"cvmx_pcsx#_rx_sync_states_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1750, 5, 3341},
|
|
{"cvmx_pcsx#_spd_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1752, 3, 3346},
|
|
{"cvmx_pcsx#_status1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1754, 6, 3349},
|
|
{"cvmx_pcsx#_status2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1756, 9, 3355},
|
|
{"cvmx_pcsx#_tx_rx_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1758, 3, 3364},
|
|
{"cvmx_pcsx#_tx_rx_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1760, 9, 3367},
|
|
{"cvmx_pesc#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1762, 13, 3376},
|
|
{"cvmx_pesc#_bist_status2" , CVMX_CSR_DB_TYPE_RSL, 64, 1764, 15, 3389},
|
|
{"cvmx_pesc#_cfg_rd" , CVMX_CSR_DB_TYPE_RSL, 64, 1766, 2, 3404},
|
|
{"cvmx_pesc#_cfg_wr" , CVMX_CSR_DB_TYPE_RSL, 64, 1768, 2, 3406},
|
|
{"cvmx_pesc#_cpl_lut_valid" , CVMX_CSR_DB_TYPE_RSL, 64, 1770, 2, 3408},
|
|
{"cvmx_pesc#_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1772, 16, 3410},
|
|
{"cvmx_pesc#_ctl_status2" , CVMX_CSR_DB_TYPE_RSL, 64, 1774, 2, 3426},
|
|
{"cvmx_pesc#_dbg_info" , CVMX_CSR_DB_TYPE_RSL, 64, 1776, 32, 3428},
|
|
{"cvmx_pesc#_dbg_info_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1778, 32, 3460},
|
|
{"cvmx_pesc#_diag_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1780, 5, 3492},
|
|
{"cvmx_pesc#_p2n_bar0_start" , CVMX_CSR_DB_TYPE_RSL, 64, 1782, 2, 3497},
|
|
{"cvmx_pesc#_p2n_bar1_start" , CVMX_CSR_DB_TYPE_RSL, 64, 1784, 2, 3499},
|
|
{"cvmx_pesc#_p2n_bar2_start" , CVMX_CSR_DB_TYPE_RSL, 64, 1786, 2, 3501},
|
|
{"cvmx_pesc#_p2p_bar#_end" , CVMX_CSR_DB_TYPE_RSL, 64, 1788, 2, 3503},
|
|
{"cvmx_pesc#_p2p_bar#_start" , CVMX_CSR_DB_TYPE_RSL, 64, 1796, 2, 3505},
|
|
{"cvmx_pesc#_tlp_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 1804, 8, 3507},
|
|
{"cvmx_pip_bck_prs" , CVMX_CSR_DB_TYPE_RSL, 64, 1806, 5, 3515},
|
|
{"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1807, 2, 3520},
|
|
{"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 1808, 4, 3522},
|
|
{"cvmx_pip_frm_len_chk#" , CVMX_CSR_DB_TYPE_RSL, 64, 1812, 3, 3526},
|
|
{"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1814, 8, 3529},
|
|
{"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1815, 18, 3537},
|
|
{"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1816, 13, 3555},
|
|
{"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1817, 13, 3568},
|
|
{"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 1818, 2, 3581},
|
|
{"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1819, 27, 3583},
|
|
{"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 1831, 25, 3610},
|
|
{"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 1843, 2, 3635},
|
|
{"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 1907, 2, 3637},
|
|
{"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 1915, 9, 3639},
|
|
{"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 1923, 2, 3648},
|
|
{"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 1924, 2, 3650},
|
|
{"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1925, 2, 3652},
|
|
{"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1937, 2, 3654},
|
|
{"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1949, 2, 3656},
|
|
{"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1961, 2, 3658},
|
|
{"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1973, 2, 3660},
|
|
{"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1985, 2, 3662},
|
|
{"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1997, 2, 3664},
|
|
{"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2009, 2, 3666},
|
|
{"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2021, 2, 3668},
|
|
{"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2033, 2, 3670},
|
|
{"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2045, 2, 3672},
|
|
{"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 2046, 2, 3674},
|
|
{"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 2058, 2, 3676},
|
|
{"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 2070, 2, 3678},
|
|
{"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 2082, 2, 3680},
|
|
{"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2146, 2, 3682},
|
|
{"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 2147, 3, 3684},
|
|
{"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 2148, 3, 3687},
|
|
{"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 2149, 2, 3690},
|
|
{"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 2150, 2, 3692},
|
|
{"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2151, 4, 3694},
|
|
{"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2152, 5, 3698},
|
|
{"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 2153, 4, 3703},
|
|
{"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 2154, 8, 3707},
|
|
{"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 2155, 4, 3715},
|
|
{"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 2156, 5, 3719},
|
|
{"cvmx_pko_mem_debug14" , CVMX_CSR_DB_TYPE_RSL, 64, 2157, 1, 3724},
|
|
{"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2158, 5, 3725},
|
|
{"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2159, 1, 3730},
|
|
{"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 2160, 13, 3731},
|
|
{"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 2161, 4, 3744},
|
|
{"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 2162, 13, 3748},
|
|
{"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 2163, 6, 3761},
|
|
{"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 2164, 9, 3767},
|
|
{"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 2165, 4, 3776},
|
|
{"cvmx_pko_mem_port_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 2166, 7, 3780},
|
|
{"cvmx_pko_mem_port_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 2167, 5, 3787},
|
|
{"cvmx_pko_mem_port_rate0" , CVMX_CSR_DB_TYPE_RSL, 64, 2168, 5, 3792},
|
|
{"cvmx_pko_mem_port_rate1" , CVMX_CSR_DB_TYPE_RSL, 64, 2169, 4, 3797},
|
|
{"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 2170, 9, 3801},
|
|
{"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 2171, 5, 3810},
|
|
{"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2172, 16, 3815},
|
|
{"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2173, 4, 3831},
|
|
{"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2174, 1, 3835},
|
|
{"cvmx_pko_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2175, 1, 3836},
|
|
{"cvmx_pko_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2176, 1, 3837},
|
|
{"cvmx_pko_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2177, 1, 3838},
|
|
{"cvmx_pko_reg_engine_inflight", CVMX_CSR_DB_TYPE_RSL, 64, 2178, 11, 3839},
|
|
{"cvmx_pko_reg_engine_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 2179, 2, 3850},
|
|
{"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2180, 4, 3852},
|
|
{"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2181, 5, 3856},
|
|
{"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2182, 3, 3861},
|
|
{"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2183, 4, 3864},
|
|
{"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2184, 2, 3868},
|
|
{"cvmx_pko_reg_queue_ptrs1" , CVMX_CSR_DB_TYPE_RSL, 64, 2185, 3, 3870},
|
|
{"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2186, 3, 3873},
|
|
{"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 2187, 13, 3876},
|
|
{"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2188, 2, 3889},
|
|
{"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 2189, 13, 3891},
|
|
{"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 2190, 3, 3904},
|
|
{"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2191, 2, 3907},
|
|
{"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2199, 2, 3909},
|
|
{"cvmx_pow_iq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 2200, 2, 3911},
|
|
{"cvmx_pow_iq_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 2201, 2, 3913},
|
|
{"cvmx_pow_iq_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2202, 2, 3915},
|
|
{"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2210, 2, 3917},
|
|
{"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 2211, 2, 3919},
|
|
{"cvmx_pow_pf_rst_msk" , CVMX_CSR_DB_TYPE_NCB, 64, 2212, 2, 3921},
|
|
{"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 2213, 10, 3923},
|
|
{"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 2225, 5, 3933},
|
|
{"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2233, 8, 3938},
|
|
{"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2241, 2, 3946},
|
|
{"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2242, 2, 3948},
|
|
{"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2243, 2, 3950},
|
|
{"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 2251, 3, 3952},
|
|
{"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2252, 4, 3955},
|
|
{"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2268, 5, 3959},
|
|
{"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2269, 7, 3964},
|
|
{"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2285, 2, 3971},
|
|
{"cvmx_rad_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2301, 1, 3973},
|
|
{"cvmx_rad_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2302, 1, 3974},
|
|
{"cvmx_rad_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2303, 1, 3975},
|
|
{"cvmx_rad_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2304, 5, 3976},
|
|
{"cvmx_rad_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2305, 5, 3981},
|
|
{"cvmx_rad_reg_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2306, 4, 3986},
|
|
{"cvmx_rad_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2307, 10, 3990},
|
|
{"cvmx_rad_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2308, 1, 4000},
|
|
{"cvmx_rad_reg_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 2309, 3, 4001},
|
|
{"cvmx_rad_reg_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 2310, 7, 4004},
|
|
{"cvmx_rad_reg_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 2311, 2, 4011},
|
|
{"cvmx_rad_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2312, 1, 4013},
|
|
{"cvmx_rad_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2313, 1, 4014},
|
|
{"cvmx_rad_reg_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 2314, 1, 4015},
|
|
{"cvmx_rad_reg_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 2315, 18, 4016},
|
|
{"cvmx_rad_reg_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 2316, 3, 4034},
|
|
{"cvmx_rad_reg_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 2317, 2, 4037},
|
|
{"cvmx_rad_reg_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 2318, 3, 4039},
|
|
{"cvmx_rad_reg_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 2319, 7, 4042},
|
|
{"cvmx_rad_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2320, 2, 4049},
|
|
{"cvmx_rad_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2321, 2, 4051},
|
|
{"cvmx_rad_reg_polynomial" , CVMX_CSR_DB_TYPE_RSL, 64, 2322, 2, 4053},
|
|
{"cvmx_rad_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2323, 3, 4055},
|
|
{"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2324, 3, 4058},
|
|
{"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2325, 7, 4061},
|
|
{"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 2326, 10, 4068},
|
|
{"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2328, 6, 4078},
|
|
{"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2330, 2, 4084},
|
|
{"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2332, 4, 4086},
|
|
{"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2334, 4, 4090},
|
|
{"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2336, 6, 4094},
|
|
{"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2337, 3, 4100},
|
|
{"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2338, 5, 4103},
|
|
{"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 2339, 4, 4108},
|
|
{"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 2340, 6, 4112},
|
|
{"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2341, 4, 4118},
|
|
{"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2342, 2, 4122},
|
|
{"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2343, 4, 4124},
|
|
{"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2344, 2, 4128},
|
|
{"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2345, 3, 4130},
|
|
{"cvmx_tra_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2346, 4, 4133},
|
|
{"cvmx_tra_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2347, 12, 4137},
|
|
{"cvmx_tra_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 2348, 3, 4149},
|
|
{"cvmx_tra_cycles_since1" , CVMX_CSR_DB_TYPE_RSL, 64, 2349, 5, 4152},
|
|
{"cvmx_tra_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2350, 2, 4157},
|
|
{"cvmx_tra_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2351, 2, 4159},
|
|
{"cvmx_tra_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2352, 18, 4161},
|
|
{"cvmx_tra_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2353, 12, 4179},
|
|
{"cvmx_tra_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2354, 6, 4191},
|
|
{"cvmx_tra_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2355, 5, 4197},
|
|
{"cvmx_tra_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2356, 1, 4202},
|
|
{"cvmx_tra_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2357, 2, 4203},
|
|
{"cvmx_tra_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2358, 2, 4205},
|
|
{"cvmx_tra_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2359, 18, 4207},
|
|
{"cvmx_tra_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2360, 12, 4225},
|
|
{"cvmx_tra_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2361, 6, 4237},
|
|
{"cvmx_tra_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2362, 2, 4243},
|
|
{"cvmx_tra_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2363, 2, 4245},
|
|
{"cvmx_tra_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2364, 18, 4247},
|
|
{"cvmx_tra_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2365, 12, 4265},
|
|
{"cvmx_tra_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2366, 6, 4277},
|
|
{"cvmx_usbc#_daint" , CVMX_CSR_DB_TYPE_NCB, 32, 2367, 2, 4283},
|
|
{"cvmx_usbc#_daintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 2368, 2, 4285},
|
|
{"cvmx_usbc#_dcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 2369, 8, 4287},
|
|
{"cvmx_usbc#_dctl" , CVMX_CSR_DB_TYPE_NCB, 32, 2370, 11, 4295},
|
|
{"cvmx_usbc#_diepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 2371, 15, 4306},
|
|
{"cvmx_usbc#_diepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 2376, 8, 4321},
|
|
{"cvmx_usbc#_diepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 2381, 8, 4329},
|
|
{"cvmx_usbc#_dieptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 2382, 4, 4337},
|
|
{"cvmx_usbc#_doepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 2387, 15, 4341},
|
|
{"cvmx_usbc#_doepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 2392, 6, 4356},
|
|
{"cvmx_usbc#_doepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 2397, 6, 4362},
|
|
{"cvmx_usbc#_doeptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 2398, 4, 4368},
|
|
{"cvmx_usbc#_dptxfsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 2403, 2, 4372},
|
|
{"cvmx_usbc#_dsts" , CVMX_CSR_DB_TYPE_NCB, 32, 2407, 6, 4374},
|
|
{"cvmx_usbc#_dtknqr1" , CVMX_CSR_DB_TYPE_NCB, 32, 2408, 4, 4380},
|
|
{"cvmx_usbc#_dtknqr2" , CVMX_CSR_DB_TYPE_NCB, 32, 2409, 1, 4384},
|
|
{"cvmx_usbc#_dtknqr3" , CVMX_CSR_DB_TYPE_NCB, 32, 2410, 1, 4385},
|
|
{"cvmx_usbc#_dtknqr4" , CVMX_CSR_DB_TYPE_NCB, 32, 2411, 1, 4386},
|
|
{"cvmx_usbc#_gahbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 2412, 7, 4387},
|
|
{"cvmx_usbc#_ghwcfg1" , CVMX_CSR_DB_TYPE_NCB, 32, 2413, 1, 4394},
|
|
{"cvmx_usbc#_ghwcfg2" , CVMX_CSR_DB_TYPE_NCB, 32, 2414, 14, 4395},
|
|
{"cvmx_usbc#_ghwcfg3" , CVMX_CSR_DB_TYPE_NCB, 32, 2415, 10, 4409},
|
|
{"cvmx_usbc#_ghwcfg4" , CVMX_CSR_DB_TYPE_NCB, 32, 2416, 14, 4419},
|
|
{"cvmx_usbc#_gintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 2417, 32, 4433},
|
|
{"cvmx_usbc#_gintsts" , CVMX_CSR_DB_TYPE_NCB, 32, 2418, 32, 4465},
|
|
{"cvmx_usbc#_gnptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 2419, 2, 4497},
|
|
{"cvmx_usbc#_gnptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 2420, 4, 4499},
|
|
{"cvmx_usbc#_gotgctl" , CVMX_CSR_DB_TYPE_NCB, 32, 2421, 13, 4503},
|
|
{"cvmx_usbc#_gotgint" , CVMX_CSR_DB_TYPE_NCB, 32, 2422, 10, 4516},
|
|
{"cvmx_usbc#_grstctl" , CVMX_CSR_DB_TYPE_NCB, 32, 2423, 10, 4526},
|
|
{"cvmx_usbc#_grxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 2424, 2, 4536},
|
|
{"cvmx_usbc#_grxstspd" , CVMX_CSR_DB_TYPE_NCB, 32, 2425, 6, 4538},
|
|
{"cvmx_usbc#_grxstsph" , CVMX_CSR_DB_TYPE_NCB, 32, 2426, 5, 4544},
|
|
{"cvmx_usbc#_grxstsrd" , CVMX_CSR_DB_TYPE_NCB, 32, 2427, 6, 4549},
|
|
{"cvmx_usbc#_grxstsrh" , CVMX_CSR_DB_TYPE_NCB, 32, 2428, 5, 4555},
|
|
{"cvmx_usbc#_gsnpsid" , CVMX_CSR_DB_TYPE_NCB, 32, 2429, 1, 4560},
|
|
{"cvmx_usbc#_gusbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 2430, 13, 4561},
|
|
{"cvmx_usbc#_haint" , CVMX_CSR_DB_TYPE_NCB, 32, 2431, 2, 4574},
|
|
{"cvmx_usbc#_haintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 2432, 2, 4576},
|
|
{"cvmx_usbc#_hcchar#" , CVMX_CSR_DB_TYPE_NCB, 32, 2433, 11, 4578},
|
|
{"cvmx_usbc#_hcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 2441, 3, 4589},
|
|
{"cvmx_usbc#_hcint#" , CVMX_CSR_DB_TYPE_NCB, 32, 2442, 12, 4592},
|
|
{"cvmx_usbc#_hcintmsk#" , CVMX_CSR_DB_TYPE_NCB, 32, 2450, 12, 4604},
|
|
{"cvmx_usbc#_hcsplt#" , CVMX_CSR_DB_TYPE_NCB, 32, 2458, 6, 4616},
|
|
{"cvmx_usbc#_hctsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 2466, 4, 4622},
|
|
{"cvmx_usbc#_hfir" , CVMX_CSR_DB_TYPE_NCB, 32, 2474, 2, 4626},
|
|
{"cvmx_usbc#_hfnum" , CVMX_CSR_DB_TYPE_NCB, 32, 2475, 2, 4628},
|
|
{"cvmx_usbc#_hprt" , CVMX_CSR_DB_TYPE_NCB, 32, 2476, 15, 4630},
|
|
{"cvmx_usbc#_hptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 2477, 2, 4645},
|
|
{"cvmx_usbc#_hptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 2478, 3, 4647},
|
|
{"cvmx_usbc#_nptxdfifo#" , CVMX_CSR_DB_TYPE_NCB, 32, 2479, 1, 4650},
|
|
{"cvmx_usbc#_pcgcctl" , CVMX_CSR_DB_TYPE_NCB, 32, 2487, 6, 4651},
|
|
{"cvmx_usbn#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2488, 8, 4657},
|
|
{"cvmx_usbn#_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2489, 15, 4665},
|
|
{"cvmx_usbn#_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 2490, 6, 4680},
|
|
{"cvmx_usbn#_dma0_inb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 2491, 2, 4686},
|
|
{"cvmx_usbn#_dma0_inb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 2492, 2, 4688},
|
|
{"cvmx_usbn#_dma0_inb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 2493, 2, 4690},
|
|
{"cvmx_usbn#_dma0_inb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 2494, 2, 4692},
|
|
{"cvmx_usbn#_dma0_inb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 2495, 2, 4694},
|
|
{"cvmx_usbn#_dma0_inb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 2496, 2, 4696},
|
|
{"cvmx_usbn#_dma0_inb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 2497, 2, 4698},
|
|
{"cvmx_usbn#_dma0_inb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 2498, 2, 4700},
|
|
{"cvmx_usbn#_dma0_outb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 2499, 2, 4702},
|
|
{"cvmx_usbn#_dma0_outb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 2500, 2, 4704},
|
|
{"cvmx_usbn#_dma0_outb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 2501, 2, 4706},
|
|
{"cvmx_usbn#_dma0_outb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 2502, 2, 4708},
|
|
{"cvmx_usbn#_dma0_outb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 2503, 2, 4710},
|
|
{"cvmx_usbn#_dma0_outb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 2504, 2, 4712},
|
|
{"cvmx_usbn#_dma0_outb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 2505, 2, 4714},
|
|
{"cvmx_usbn#_dma0_outb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 2506, 2, 4716},
|
|
{"cvmx_usbn#_dma_test" , CVMX_CSR_DB_TYPE_NCB, 64, 2507, 7, 4718},
|
|
{"cvmx_usbn#_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 2508, 34, 4725},
|
|
{"cvmx_usbn#_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 2509, 34, 4759},
|
|
{"cvmx_usbn#_usbp_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2510, 35, 4793},
|
|
{"cvmx_zip_cmd_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2511, 3, 4828},
|
|
{"cvmx_zip_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2512, 5, 4831},
|
|
{"cvmx_zip_cmd_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2513, 3, 4836},
|
|
{"cvmx_zip_constants" , CVMX_CSR_DB_TYPE_RSL, 64, 2514, 6, 4839},
|
|
{"cvmx_zip_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2515, 2, 4845},
|
|
{"cvmx_zip_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2516, 2, 4847},
|
|
{"cvmx_zip_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2517, 2, 4849},
|
|
{NULL,0,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
|
|
/* name , --------------address, ---------------type, bits, csr offset */
|
|
{"AGL_GMX_BAD_REG" , 0x11800E0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
|
|
{"AGL_GMX_BIST" , 0x11800E0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
|
|
{"AGL_GMX_DRV_CTL" , 0x11800E00007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
|
|
{"AGL_GMX_INF_MODE" , 0x11800E00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
|
|
{"AGL_GMX_PRT0_CFG" , 0x11800E0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
|
|
{"AGL_GMX_RX0_ADR_CAM0" , 0x11800E0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
|
|
{"AGL_GMX_RX0_ADR_CAM1" , 0x11800E0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
|
|
{"AGL_GMX_RX0_ADR_CAM2" , 0x11800E0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
|
|
{"AGL_GMX_RX0_ADR_CAM3" , 0x11800E0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
|
|
{"AGL_GMX_RX0_ADR_CAM4" , 0x11800E00001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
|
|
{"AGL_GMX_RX0_ADR_CAM5" , 0x11800E00001A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
|
|
{"AGL_GMX_RX0_ADR_CAM_EN" , 0x11800E0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
|
|
{"AGL_GMX_RX0_ADR_CTL" , 0x11800E0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"AGL_GMX_RX0_DECISION" , 0x11800E0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"AGL_GMX_RX0_FRM_CHK" , 0x11800E0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"AGL_GMX_RX0_FRM_CTL" , 0x11800E0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
|
|
{"AGL_GMX_RX0_FRM_MAX" , 0x11800E0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"AGL_GMX_RX0_FRM_MIN" , 0x11800E0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
|
|
{"AGL_GMX_RX0_IFG" , 0x11800E0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
|
|
{"AGL_GMX_RX0_INT_EN" , 0x11800E0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
|
|
{"AGL_GMX_RX0_INT_REG" , 0x11800E0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
|
|
{"AGL_GMX_RX0_JABBER" , 0x11800E0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
|
|
{"AGL_GMX_RX0_PAUSE_DROP_TIME" , 0x11800E0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
|
|
{"AGL_GMX_RX0_STATS_CTL" , 0x11800E0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
|
|
{"AGL_GMX_RX0_STATS_OCTS" , 0x11800E0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
|
|
{"AGL_GMX_RX0_STATS_OCTS_CTL" , 0x11800E0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 25},
|
|
{"AGL_GMX_RX0_STATS_OCTS_DMAC" , 0x11800E00000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 26},
|
|
{"AGL_GMX_RX0_STATS_OCTS_DRP" , 0x11800E00000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 27},
|
|
{"AGL_GMX_RX0_STATS_PKTS" , 0x11800E0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 28},
|
|
{"AGL_GMX_RX0_STATS_PKTS_BAD" , 0x11800E00000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 29},
|
|
{"AGL_GMX_RX0_STATS_PKTS_CTL" , 0x11800E0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 30},
|
|
{"AGL_GMX_RX0_STATS_PKTS_DMAC" , 0x11800E00000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 31},
|
|
{"AGL_GMX_RX0_STATS_PKTS_DRP" , 0x11800E00000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
|
|
{"AGL_GMX_RX0_UDD_SKP" , 0x11800E0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
|
|
{"AGL_GMX_RX_BP_DROP0" , 0x11800E0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 34},
|
|
{"AGL_GMX_RX_BP_OFF0" , 0x11800E0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
|
|
{"AGL_GMX_RX_BP_ON0" , 0x11800E0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
|
|
{"AGL_GMX_RX_PRT_INFO" , 0x11800E00004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
|
|
{"AGL_GMX_RX_TX_STATUS" , 0x11800E00007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
|
|
{"AGL_GMX_SMAC0" , 0x11800E0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
|
|
{"AGL_GMX_STAT_BP" , 0x11800E0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
|
|
{"AGL_GMX_TX0_APPEND" , 0x11800E0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
|
|
{"AGL_GMX_TX0_CTL" , 0x11800E0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
|
|
{"AGL_GMX_TX0_MIN_PKT" , 0x11800E0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
|
|
{"AGL_GMX_TX0_PAUSE_PKT_INTERVAL", 0x11800E0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
|
|
{"AGL_GMX_TX0_PAUSE_PKT_TIME" , 0x11800E0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
|
|
{"AGL_GMX_TX0_PAUSE_TOGO" , 0x11800E0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
|
|
{"AGL_GMX_TX0_PAUSE_ZERO" , 0x11800E0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
|
|
{"AGL_GMX_TX0_SOFT_PAUSE" , 0x11800E0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
|
|
{"AGL_GMX_TX0_STAT0" , 0x11800E0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
|
|
{"AGL_GMX_TX0_STAT1" , 0x11800E0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
|
|
{"AGL_GMX_TX0_STAT2" , 0x11800E0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
|
|
{"AGL_GMX_TX0_STAT3" , 0x11800E0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
|
|
{"AGL_GMX_TX0_STAT4" , 0x11800E00002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
|
|
{"AGL_GMX_TX0_STAT5" , 0x11800E00002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
|
|
{"AGL_GMX_TX0_STAT6" , 0x11800E00002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
|
|
{"AGL_GMX_TX0_STAT7" , 0x11800E00002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
|
|
{"AGL_GMX_TX0_STAT8" , 0x11800E00002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
|
|
{"AGL_GMX_TX0_STAT9" , 0x11800E00002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
|
|
{"AGL_GMX_TX0_STATS_CTL" , 0x11800E0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
|
|
{"AGL_GMX_TX0_THRESH" , 0x11800E0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
|
|
{"AGL_GMX_TX_BP" , 0x11800E00004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
|
|
{"AGL_GMX_TX_COL_ATTEMPT" , 0x11800E0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
|
|
{"AGL_GMX_TX_IFG" , 0x11800E0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
|
|
{"AGL_GMX_TX_INT_EN" , 0x11800E0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
|
|
{"AGL_GMX_TX_INT_REG" , 0x11800E0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
|
|
{"AGL_GMX_TX_JAM" , 0x11800E0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"AGL_GMX_TX_LFSR" , 0x11800E00004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"AGL_GMX_TX_OVR_BP" , 0x11800E00004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
|
|
{"AGL_GMX_TX_PAUSE_PKT_DMAC" , 0x11800E00004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
|
|
{"AGL_GMX_TX_PAUSE_PKT_TYPE" , 0x11800E00004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
|
|
{"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 71},
|
|
{"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 72},
|
|
{"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
|
|
{"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
|
|
{"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT4_EN0" , 0x1070000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT5_EN0" , 0x1070000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT6_EN0" , 0x1070000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT7_EN0" , 0x1070000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT8_EN0" , 0x1070000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT9_EN0" , 0x1070000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT10_EN0" , 0x10700000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT11_EN0" , 0x10700000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT12_EN0" , 0x10700000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT13_EN0" , 0x10700000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT14_EN0" , 0x10700000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT15_EN0" , 0x10700000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT16_EN0" , 0x1070000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT17_EN0" , 0x1070000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT18_EN0" , 0x1070000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT19_EN0" , 0x1070000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT20_EN0" , 0x1070000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT21_EN0" , 0x1070000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT22_EN0" , 0x1070000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT23_EN0" , 0x1070000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT4_EN1" , 0x1070000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT5_EN1" , 0x1070000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT6_EN1" , 0x1070000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT7_EN1" , 0x1070000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT8_EN1" , 0x1070000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT9_EN1" , 0x1070000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT10_EN1" , 0x10700000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT11_EN1" , 0x10700000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT12_EN1" , 0x10700000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT13_EN1" , 0x10700000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT14_EN1" , 0x10700000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT15_EN1" , 0x10700000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT16_EN1" , 0x1070000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT17_EN1" , 0x1070000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT18_EN1" , 0x1070000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT19_EN1" , 0x1070000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT20_EN1" , 0x1070000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT21_EN1" , 0x1070000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT22_EN1" , 0x1070000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT23_EN1" , 0x1070000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT0_EN4_0" , 0x1070000000C80ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT1_EN4_0" , 0x1070000000C90ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT2_EN4_0" , 0x1070000000CA0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT3_EN4_0" , 0x1070000000CB0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT4_EN4_0" , 0x1070000000CC0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT5_EN4_0" , 0x1070000000CD0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT6_EN4_0" , 0x1070000000CE0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT7_EN4_0" , 0x1070000000CF0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT8_EN4_0" , 0x1070000000D00ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT9_EN4_0" , 0x1070000000D10ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT10_EN4_0" , 0x1070000000D20ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT11_EN4_0" , 0x1070000000D30ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT0_EN4_1" , 0x1070000000C88ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT1_EN4_1" , 0x1070000000C98ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT2_EN4_1" , 0x1070000000CA8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT3_EN4_1" , 0x1070000000CB8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT4_EN4_1" , 0x1070000000CC8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT5_EN4_1" , 0x1070000000CD8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT6_EN4_1" , 0x1070000000CE8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT7_EN4_1" , 0x1070000000CF8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT8_EN4_1" , 0x1070000000D08ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT9_EN4_1" , 0x1070000000D18ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT10_EN4_1" , 0x1070000000D28ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT11_EN4_1" , 0x1070000000D38ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT4_SUM0" , 0x1070000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT5_SUM0" , 0x1070000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT6_SUM0" , 0x1070000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT7_SUM0" , 0x1070000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT8_SUM0" , 0x1070000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT9_SUM0" , 0x1070000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT10_SUM0" , 0x1070000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT11_SUM0" , 0x1070000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT12_SUM0" , 0x1070000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT13_SUM0" , 0x1070000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT14_SUM0" , 0x1070000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT15_SUM0" , 0x1070000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT16_SUM0" , 0x1070000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT17_SUM0" , 0x1070000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT18_SUM0" , 0x1070000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT19_SUM0" , 0x1070000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT20_SUM0" , 0x10700000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT21_SUM0" , 0x10700000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT22_SUM0" , 0x10700000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT23_SUM0" , 0x10700000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT0_SUM4" , 0x1070000000C00ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT1_SUM4" , 0x1070000000C08ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT2_SUM4" , 0x1070000000C10ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT3_SUM4" , 0x1070000000C18ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT4_SUM4" , 0x1070000000C20ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT5_SUM4" , 0x1070000000C28ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT6_SUM4" , 0x1070000000C30ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT7_SUM4" , 0x1070000000C38ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT8_SUM4" , 0x1070000000C40ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT9_SUM4" , 0x1070000000C48ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT10_SUM4" , 0x1070000000C50ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT11_SUM4" , 0x1070000000C58ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
|
|
{"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_MBOX_CLR2" , 0x1070000000690ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_MBOX_CLR3" , 0x1070000000698ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_MBOX_CLR4" , 0x10700000006A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_MBOX_CLR5" , 0x10700000006A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_MBOX_CLR6" , 0x10700000006B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_MBOX_CLR7" , 0x10700000006B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_MBOX_CLR8" , 0x10700000006C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_MBOX_CLR9" , 0x10700000006C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_MBOX_CLR10" , 0x10700000006D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_MBOX_CLR11" , 0x10700000006D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_MBOX_SET2" , 0x1070000000610ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_MBOX_SET3" , 0x1070000000618ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_MBOX_SET4" , 0x1070000000620ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_MBOX_SET5" , 0x1070000000628ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_MBOX_SET6" , 0x1070000000630ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_MBOX_SET7" , 0x1070000000638ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_MBOX_SET8" , 0x1070000000640ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_MBOX_SET9" , 0x1070000000648ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_MBOX_SET10" , 0x1070000000650ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_MBOX_SET11" , 0x1070000000658ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
|
|
{"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
|
|
{"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
|
|
{"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_PP_POKE2" , 0x1070000000590ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_PP_POKE3" , 0x1070000000598ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_PP_POKE4" , 0x10700000005A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_PP_POKE5" , 0x10700000005A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_PP_POKE6" , 0x10700000005B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_PP_POKE7" , 0x10700000005B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_PP_POKE8" , 0x10700000005C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_PP_POKE9" , 0x10700000005C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_PP_POKE10" , 0x10700000005D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_PP_POKE11" , 0x10700000005D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
|
|
{"CIU_QLM_DCOK" , 0x1070000000760ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
|
|
{"CIU_QLM_JTGC" , 0x1070000000768ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
|
|
{"CIU_QLM_JTGD" , 0x1070000000770ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
|
|
{"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
|
|
{"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
|
|
{"CIU_SOFT_PRST1" , 0x1070000000758ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
|
|
{"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
|
|
{"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
|
|
{"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
|
|
{"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
|
|
{"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
|
|
{"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
|
|
{"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
|
|
{"CIU_WDOG2" , 0x1070000000510ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
|
|
{"CIU_WDOG3" , 0x1070000000518ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
|
|
{"CIU_WDOG4" , 0x1070000000520ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
|
|
{"CIU_WDOG5" , 0x1070000000528ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
|
|
{"CIU_WDOG6" , 0x1070000000530ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
|
|
{"CIU_WDOG7" , 0x1070000000538ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
|
|
{"CIU_WDOG8" , 0x1070000000540ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
|
|
{"CIU_WDOG9" , 0x1070000000548ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
|
|
{"CIU_WDOG10" , 0x1070000000550ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
|
|
{"CIU_WDOG11" , 0x1070000000558ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
|
|
{"FPA_BIST_STATUS" , 0x11800280000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"FPA_FPF1_MARKS" , 0x1180028000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"FPA_FPF2_MARKS" , 0x1180028000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"FPA_FPF3_MARKS" , 0x1180028000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"FPA_FPF4_MARKS" , 0x1180028000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"FPA_FPF5_MARKS" , 0x1180028000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"FPA_FPF6_MARKS" , 0x1180028000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"FPA_FPF7_MARKS" , 0x1180028000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"FPA_FPF1_SIZE" , 0x1180028000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"FPA_FPF2_SIZE" , 0x1180028000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"FPA_FPF3_SIZE" , 0x1180028000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"FPA_FPF4_SIZE" , 0x1180028000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"FPA_FPF5_SIZE" , 0x1180028000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"FPA_FPF6_SIZE" , 0x1180028000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"FPA_FPF7_SIZE" , 0x1180028000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"FPA_FPF0_MARKS" , 0x1180028000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"FPA_FPF0_SIZE" , 0x1180028000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"FPA_QUE1_AVAILABLE" , 0x11800280000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"FPA_QUE2_AVAILABLE" , 0x11800280000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"FPA_QUE3_AVAILABLE" , 0x11800280000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"FPA_QUE4_AVAILABLE" , 0x11800280000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"FPA_QUE5_AVAILABLE" , 0x11800280000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"FPA_QUE6_AVAILABLE" , 0x11800280000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"FPA_QUE7_AVAILABLE" , 0x11800280000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"FPA_QUE0_PAGE_INDEX" , 0x11800280000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"FPA_QUE1_PAGE_INDEX" , 0x11800280000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"FPA_WART_CTL" , 0x11800280000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"FPA_WART_STATUS" , 0x11800280000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX1_BAD_REG" , 0x1180010000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX1_BIST" , 0x1180010000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX0_CLK_EN" , 0x11800080007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX1_CLK_EN" , 0x11800100007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_INF_MODE" , 0x11800080007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX1_INF_MODE" , 0x11800100007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX1_NXA_ADR" , 0x1180010000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX0_PRT003_CFG" , 0x1180008001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX1_PRT000_CFG" , 0x1180010000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX1_PRT001_CFG" , 0x1180010000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX1_PRT002_CFG" , 0x1180010001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX1_PRT003_CFG" , 0x1180010001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX0_RX003_ADR_CAM0" , 0x1180008001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX1_RX000_ADR_CAM0" , 0x1180010000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX1_RX001_ADR_CAM0" , 0x1180010000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX1_RX002_ADR_CAM0" , 0x1180010001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX1_RX003_ADR_CAM0" , 0x1180010001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_RX003_ADR_CAM1" , 0x1180008001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX1_RX000_ADR_CAM1" , 0x1180010000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX1_RX001_ADR_CAM1" , 0x1180010000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX1_RX002_ADR_CAM1" , 0x1180010001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX1_RX003_ADR_CAM1" , 0x1180010001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX0_RX003_ADR_CAM2" , 0x1180008001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX1_RX000_ADR_CAM2" , 0x1180010000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX1_RX001_ADR_CAM2" , 0x1180010000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX1_RX002_ADR_CAM2" , 0x1180010001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX1_RX003_ADR_CAM2" , 0x1180010001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_RX003_ADR_CAM3" , 0x1180008001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX1_RX000_ADR_CAM3" , 0x1180010000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX1_RX001_ADR_CAM3" , 0x1180010000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX1_RX002_ADR_CAM3" , 0x1180010001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX1_RX003_ADR_CAM3" , 0x1180010001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_RX000_ADR_CAM4" , 0x11800080001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_RX001_ADR_CAM4" , 0x11800080009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_RX002_ADR_CAM4" , 0x11800080011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_RX003_ADR_CAM4" , 0x11800080019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX1_RX000_ADR_CAM4" , 0x11800100001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX1_RX001_ADR_CAM4" , 0x11800100009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX1_RX002_ADR_CAM4" , 0x11800100011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX1_RX003_ADR_CAM4" , 0x11800100019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_RX000_ADR_CAM5" , 0x11800080001A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_RX001_ADR_CAM5" , 0x11800080009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_RX002_ADR_CAM5" , 0x11800080011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_RX003_ADR_CAM5" , 0x11800080019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX1_RX000_ADR_CAM5" , 0x11800100001A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX1_RX001_ADR_CAM5" , 0x11800100009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX1_RX002_ADR_CAM5" , 0x11800100011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX1_RX003_ADR_CAM5" , 0x11800100019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX003_ADR_CAM_EN" , 0x1180008001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_RX000_ADR_CAM_EN" , 0x1180010000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_RX001_ADR_CAM_EN" , 0x1180010000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_RX002_ADR_CAM_EN" , 0x1180010001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_RX003_ADR_CAM_EN" , 0x1180010001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_RX003_ADR_CTL" , 0x1180008001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX1_RX000_ADR_CTL" , 0x1180010000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX1_RX001_ADR_CTL" , 0x1180010000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX1_RX002_ADR_CTL" , 0x1180010001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX1_RX003_ADR_CTL" , 0x1180010001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_RX003_DECISION" , 0x1180008001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX1_RX000_DECISION" , 0x1180010000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX1_RX001_DECISION" , 0x1180010000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX1_RX002_DECISION" , 0x1180010001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX1_RX003_DECISION" , 0x1180010001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_RX003_FRM_CHK" , 0x1180008001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX1_RX000_FRM_CHK" , 0x1180010000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX1_RX001_FRM_CHK" , 0x1180010000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX1_RX002_FRM_CHK" , 0x1180010001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX1_RX003_FRM_CHK" , 0x1180010001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_RX003_FRM_CTL" , 0x1180008001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX1_RX000_FRM_CTL" , 0x1180010000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX1_RX001_FRM_CTL" , 0x1180010000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX1_RX002_FRM_CTL" , 0x1180010001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX1_RX003_FRM_CTL" , 0x1180010001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_RX003_IFG" , 0x1180008001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX1_RX000_IFG" , 0x1180010000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX1_RX001_IFG" , 0x1180010000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX1_RX002_IFG" , 0x1180010001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX1_RX003_IFG" , 0x1180010001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_RX003_INT_EN" , 0x1180008001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX1_RX000_INT_EN" , 0x1180010000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX1_RX001_INT_EN" , 0x1180010000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX1_RX002_INT_EN" , 0x1180010001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX1_RX003_INT_EN" , 0x1180010001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_RX003_INT_REG" , 0x1180008001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX1_RX000_INT_REG" , 0x1180010000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX1_RX001_INT_REG" , 0x1180010000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX1_RX002_INT_REG" , 0x1180010001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX1_RX003_INT_REG" , 0x1180010001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_RX003_JABBER" , 0x1180008001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX1_RX000_JABBER" , 0x1180010000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX1_RX001_JABBER" , 0x1180010000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX1_RX002_JABBER" , 0x1180010001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX1_RX003_JABBER" , 0x1180010001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_RX000_PAUSE_DROP_TIME" , 0x1180008000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_RX001_PAUSE_DROP_TIME" , 0x1180008000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_RX002_PAUSE_DROP_TIME" , 0x1180008001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_RX003_PAUSE_DROP_TIME" , 0x1180008001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX1_RX000_PAUSE_DROP_TIME" , 0x1180010000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX1_RX001_PAUSE_DROP_TIME" , 0x1180010000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX1_RX002_PAUSE_DROP_TIME" , 0x1180010001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX1_RX003_PAUSE_DROP_TIME" , 0x1180010001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_RX003_STATS_CTL" , 0x1180008001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX1_RX000_STATS_CTL" , 0x1180010000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX1_RX001_STATS_CTL" , 0x1180010000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX1_RX002_STATS_CTL" , 0x1180010001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX1_RX003_STATS_CTL" , 0x1180010001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_RX003_STATS_OCTS" , 0x1180008001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX1_RX000_STATS_OCTS" , 0x1180010000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX1_RX001_STATS_OCTS" , 0x1180010000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX1_RX002_STATS_OCTS" , 0x1180010001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX1_RX003_STATS_OCTS" , 0x1180010001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_RX003_STATS_OCTS_CTL" , 0x1180008001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX1_RX000_STATS_OCTS_CTL" , 0x1180010000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX1_RX001_STATS_OCTS_CTL" , 0x1180010000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX1_RX002_STATS_OCTS_CTL" , 0x1180010001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX1_RX003_STATS_OCTS_CTL" , 0x1180010001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_RX003_STATS_OCTS_DMAC" , 0x11800080018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX1_RX000_STATS_OCTS_DMAC" , 0x11800100000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX1_RX001_STATS_OCTS_DMAC" , 0x11800100008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX1_RX002_STATS_OCTS_DMAC" , 0x11800100010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX1_RX003_STATS_OCTS_DMAC" , 0x11800100018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_RX003_STATS_OCTS_DRP" , 0x11800080018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX1_RX000_STATS_OCTS_DRP" , 0x11800100000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX1_RX001_STATS_OCTS_DRP" , 0x11800100008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX1_RX002_STATS_OCTS_DRP" , 0x11800100010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX1_RX003_STATS_OCTS_DRP" , 0x11800100018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_RX003_STATS_PKTS" , 0x1180008001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX1_RX000_STATS_PKTS" , 0x1180010000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX1_RX001_STATS_PKTS" , 0x1180010000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX1_RX002_STATS_PKTS" , 0x1180010001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX1_RX003_STATS_PKTS" , 0x1180010001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_RX003_STATS_PKTS_BAD" , 0x11800080018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX1_RX000_STATS_PKTS_BAD" , 0x11800100000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX1_RX001_STATS_PKTS_BAD" , 0x11800100008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX1_RX002_STATS_PKTS_BAD" , 0x11800100010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX1_RX003_STATS_PKTS_BAD" , 0x11800100018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_RX003_STATS_PKTS_CTL" , 0x1180008001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX1_RX000_STATS_PKTS_CTL" , 0x1180010000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX1_RX001_STATS_PKTS_CTL" , 0x1180010000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX1_RX002_STATS_PKTS_CTL" , 0x1180010001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX1_RX003_STATS_PKTS_CTL" , 0x1180010001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_RX003_STATS_PKTS_DMAC" , 0x11800080018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX1_RX000_STATS_PKTS_DMAC" , 0x11800100000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX1_RX001_STATS_PKTS_DMAC" , 0x11800100008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX1_RX002_STATS_PKTS_DMAC" , 0x11800100010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX1_RX003_STATS_PKTS_DMAC" , 0x11800100018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_RX003_STATS_PKTS_DRP" , 0x11800080018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX1_RX000_STATS_PKTS_DRP" , 0x11800100000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX1_RX001_STATS_PKTS_DRP" , 0x11800100008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX1_RX002_STATS_PKTS_DRP" , 0x11800100010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX1_RX003_STATS_PKTS_DRP" , 0x11800100018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX0_RX003_UDD_SKP" , 0x1180008001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX1_RX000_UDD_SKP" , 0x1180010000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX1_RX001_UDD_SKP" , 0x1180010000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX1_RX002_UDD_SKP" , 0x1180010001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX1_RX003_UDD_SKP" , 0x1180010001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX0_RX_BP_DROP003" , 0x1180008000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX1_RX_BP_DROP000" , 0x1180010000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX1_RX_BP_DROP001" , 0x1180010000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX1_RX_BP_DROP002" , 0x1180010000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX1_RX_BP_DROP003" , 0x1180010000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX0_RX_BP_OFF003" , 0x1180008000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX1_RX_BP_OFF000" , 0x1180010000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX1_RX_BP_OFF001" , 0x1180010000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX1_RX_BP_OFF002" , 0x1180010000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX1_RX_BP_OFF003" , 0x1180010000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX0_RX_BP_ON003" , 0x1180008000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX1_RX_BP_ON000" , 0x1180010000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX1_RX_BP_ON001" , 0x1180010000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX1_RX_BP_ON002" , 0x1180010000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX1_RX_BP_ON003" , 0x1180010000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX0_RX_PRT_INFO" , 0x11800080004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX1_RX_PRT_INFO" , 0x11800100004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX1_RX_PRTS" , 0x1180010000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX0_RX_XAUI_BAD_COL" , 0x1180008000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX1_RX_XAUI_BAD_COL" , 0x1180010000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX0_RX_XAUI_CTL" , 0x1180008000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX1_RX_XAUI_CTL" , 0x1180010000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX0_SMAC001" , 0x1180008000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX0_SMAC003" , 0x1180008001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX1_SMAC000" , 0x1180010000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX1_SMAC001" , 0x1180010000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX1_SMAC002" , 0x1180010001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX1_SMAC003" , 0x1180010001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX1_STAT_BP" , 0x1180010000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX0_TX001_APPEND" , 0x1180008000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX0_TX003_APPEND" , 0x1180008001A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX1_TX000_APPEND" , 0x1180010000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX1_TX001_APPEND" , 0x1180010000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX1_TX002_APPEND" , 0x1180010001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX1_TX003_APPEND" , 0x1180010001A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX0_TX001_BURST" , 0x1180008000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX0_TX003_BURST" , 0x1180008001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX1_TX000_BURST" , 0x1180010000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX1_TX001_BURST" , 0x1180010000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX1_TX002_BURST" , 0x1180010001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX1_TX003_BURST" , 0x1180010001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX0_TX001_CTL" , 0x1180008000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX0_TX003_CTL" , 0x1180008001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX1_TX000_CTL" , 0x1180010000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX1_TX001_CTL" , 0x1180010000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX1_TX002_CTL" , 0x1180010001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX1_TX003_CTL" , 0x1180010001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX0_TX001_MIN_PKT" , 0x1180008000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX0_TX003_MIN_PKT" , 0x1180008001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX1_TX000_MIN_PKT" , 0x1180010000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX1_TX001_MIN_PKT" , 0x1180010000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX1_TX002_MIN_PKT" , 0x1180010001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX1_TX003_MIN_PKT" , 0x1180010001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
|
|
{"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
|
|
{"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
|
|
{"GMX0_TX003_PAUSE_PKT_INTERVAL", 0x1180008001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
|
|
{"GMX1_TX000_PAUSE_PKT_INTERVAL", 0x1180010000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
|
|
{"GMX1_TX001_PAUSE_PKT_INTERVAL", 0x1180010000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
|
|
{"GMX1_TX002_PAUSE_PKT_INTERVAL", 0x1180010001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
|
|
{"GMX1_TX003_PAUSE_PKT_INTERVAL", 0x1180010001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
|
|
{"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX003_PAUSE_PKT_TIME" , 0x1180008001A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX000_PAUSE_PKT_TIME" , 0x1180010000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX001_PAUSE_PKT_TIME" , 0x1180010000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX002_PAUSE_PKT_TIME" , 0x1180010001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_TX003_PAUSE_PKT_TIME" , 0x1180010001A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
|
|
{"GMX0_TX001_PAUSE_TOGO" , 0x1180008000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
|
|
{"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
|
|
{"GMX0_TX003_PAUSE_TOGO" , 0x1180008001A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
|
|
{"GMX1_TX000_PAUSE_TOGO" , 0x1180010000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
|
|
{"GMX1_TX001_PAUSE_TOGO" , 0x1180010000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
|
|
{"GMX1_TX002_PAUSE_TOGO" , 0x1180010001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
|
|
{"GMX1_TX003_PAUSE_TOGO" , 0x1180010001A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
|
|
{"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
|
|
{"GMX0_TX001_PAUSE_ZERO" , 0x1180008000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
|
|
{"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
|
|
{"GMX0_TX003_PAUSE_ZERO" , 0x1180008001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
|
|
{"GMX1_TX000_PAUSE_ZERO" , 0x1180010000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
|
|
{"GMX1_TX001_PAUSE_ZERO" , 0x1180010000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
|
|
{"GMX1_TX002_PAUSE_ZERO" , 0x1180010001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
|
|
{"GMX1_TX003_PAUSE_ZERO" , 0x1180010001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
|
|
{"GMX0_TX000_SGMII_CTL" , 0x1180008000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
|
|
{"GMX0_TX001_SGMII_CTL" , 0x1180008000B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
|
|
{"GMX0_TX002_SGMII_CTL" , 0x1180008001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
|
|
{"GMX0_TX003_SGMII_CTL" , 0x1180008001B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
|
|
{"GMX1_TX000_SGMII_CTL" , 0x1180010000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
|
|
{"GMX1_TX001_SGMII_CTL" , 0x1180010000B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
|
|
{"GMX1_TX002_SGMII_CTL" , 0x1180010001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
|
|
{"GMX1_TX003_SGMII_CTL" , 0x1180010001B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
|
|
{"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
|
|
{"GMX0_TX001_SLOT" , 0x1180008000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
|
|
{"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
|
|
{"GMX0_TX003_SLOT" , 0x1180008001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
|
|
{"GMX1_TX000_SLOT" , 0x1180010000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
|
|
{"GMX1_TX001_SLOT" , 0x1180010000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
|
|
{"GMX1_TX002_SLOT" , 0x1180010001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
|
|
{"GMX1_TX003_SLOT" , 0x1180010001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
|
|
{"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
|
|
{"GMX0_TX001_SOFT_PAUSE" , 0x1180008000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
|
|
{"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
|
|
{"GMX0_TX003_SOFT_PAUSE" , 0x1180008001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
|
|
{"GMX1_TX000_SOFT_PAUSE" , 0x1180010000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
|
|
{"GMX1_TX001_SOFT_PAUSE" , 0x1180010000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
|
|
{"GMX1_TX002_SOFT_PAUSE" , 0x1180010001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
|
|
{"GMX1_TX003_SOFT_PAUSE" , 0x1180010001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
|
|
{"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX0_TX001_STAT0" , 0x1180008000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX0_TX003_STAT0" , 0x1180008001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX1_TX000_STAT0" , 0x1180010000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX1_TX001_STAT0" , 0x1180010000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX1_TX002_STAT0" , 0x1180010001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX1_TX003_STAT0" , 0x1180010001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX0_TX001_STAT1" , 0x1180008000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX0_TX003_STAT1" , 0x1180008001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX1_TX000_STAT1" , 0x1180010000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX1_TX001_STAT1" , 0x1180010000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX1_TX002_STAT1" , 0x1180010001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX1_TX003_STAT1" , 0x1180010001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX001_STAT2" , 0x1180008000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX003_STAT2" , 0x1180008001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX000_STAT2" , 0x1180010000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX001_STAT2" , 0x1180010000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX002_STAT2" , 0x1180010001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX003_STAT2" , 0x1180010001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
|
|
{"GMX0_TX001_STAT3" , 0x1180008000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
|
|
{"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
|
|
{"GMX0_TX003_STAT3" , 0x1180008001A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
|
|
{"GMX1_TX000_STAT3" , 0x1180010000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
|
|
{"GMX1_TX001_STAT3" , 0x1180010000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
|
|
{"GMX1_TX002_STAT3" , 0x1180010001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
|
|
{"GMX1_TX003_STAT3" , 0x1180010001A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
|
|
{"GMX0_TX000_STAT4" , 0x11800080002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"GMX0_TX001_STAT4" , 0x1180008000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"GMX0_TX002_STAT4" , 0x11800080012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"GMX0_TX003_STAT4" , 0x1180008001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"GMX1_TX000_STAT4" , 0x11800100002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"GMX1_TX001_STAT4" , 0x1180010000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"GMX1_TX002_STAT4" , 0x11800100012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"GMX1_TX003_STAT4" , 0x1180010001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"GMX0_TX000_STAT5" , 0x11800080002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"GMX0_TX001_STAT5" , 0x1180008000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"GMX0_TX002_STAT5" , 0x11800080012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"GMX0_TX003_STAT5" , 0x1180008001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"GMX1_TX000_STAT5" , 0x11800100002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"GMX1_TX001_STAT5" , 0x1180010000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"GMX1_TX002_STAT5" , 0x11800100012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"GMX1_TX003_STAT5" , 0x1180010001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"GMX0_TX000_STAT6" , 0x11800080002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"GMX0_TX001_STAT6" , 0x1180008000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"GMX0_TX002_STAT6" , 0x11800080012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"GMX0_TX003_STAT6" , 0x1180008001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"GMX1_TX000_STAT6" , 0x11800100002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"GMX1_TX001_STAT6" , 0x1180010000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"GMX1_TX002_STAT6" , 0x11800100012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"GMX1_TX003_STAT6" , 0x1180010001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"GMX0_TX000_STAT7" , 0x11800080002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"GMX0_TX001_STAT7" , 0x1180008000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"GMX0_TX002_STAT7" , 0x11800080012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"GMX0_TX003_STAT7" , 0x1180008001AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"GMX1_TX000_STAT7" , 0x11800100002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"GMX1_TX001_STAT7" , 0x1180010000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"GMX1_TX002_STAT7" , 0x11800100012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"GMX1_TX003_STAT7" , 0x1180010001AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"GMX0_TX000_STAT8" , 0x11800080002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"GMX0_TX001_STAT8" , 0x1180008000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"GMX0_TX002_STAT8" , 0x11800080012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"GMX0_TX003_STAT8" , 0x1180008001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"GMX1_TX000_STAT8" , 0x11800100002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"GMX1_TX001_STAT8" , 0x1180010000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"GMX1_TX002_STAT8" , 0x11800100012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"GMX1_TX003_STAT8" , 0x1180010001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"GMX0_TX000_STAT9" , 0x11800080002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"GMX0_TX001_STAT9" , 0x1180008000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"GMX0_TX002_STAT9" , 0x11800080012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"GMX0_TX003_STAT9" , 0x1180008001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"GMX1_TX000_STAT9" , 0x11800100002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"GMX1_TX001_STAT9" , 0x1180010000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"GMX1_TX002_STAT9" , 0x11800100012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"GMX1_TX003_STAT9" , 0x1180010001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"GMX0_TX001_STATS_CTL" , 0x1180008000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"GMX0_TX003_STATS_CTL" , 0x1180008001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"GMX1_TX000_STATS_CTL" , 0x1180010000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"GMX1_TX001_STATS_CTL" , 0x1180010000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"GMX1_TX002_STATS_CTL" , 0x1180010001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"GMX1_TX003_STATS_CTL" , 0x1180010001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"GMX0_TX001_THRESH" , 0x1180008000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"GMX0_TX003_THRESH" , 0x1180008001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"GMX1_TX000_THRESH" , 0x1180010000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"GMX1_TX001_THRESH" , 0x1180010000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"GMX1_TX002_THRESH" , 0x1180010001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"GMX1_TX003_THRESH" , 0x1180010001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"GMX0_TX_BP" , 0x11800080004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
|
|
{"GMX1_TX_BP" , 0x11800100004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
|
|
{"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
|
|
{"GMX1_TX_COL_ATTEMPT" , 0x1180010000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
|
|
{"GMX0_TX_CORRUPT" , 0x11800080004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
|
|
{"GMX1_TX_CORRUPT" , 0x11800100004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
|
|
{"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
|
|
{"GMX1_TX_IFG" , 0x1180010000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
|
|
{"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
|
|
{"GMX1_TX_INT_EN" , 0x1180010000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
|
|
{"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
|
|
{"GMX1_TX_INT_REG" , 0x1180010000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
|
|
{"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
|
|
{"GMX1_TX_JAM" , 0x1180010000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
|
|
{"GMX0_TX_LFSR" , 0x11800080004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
|
|
{"GMX1_TX_LFSR" , 0x11800100004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
|
|
{"GMX0_TX_OVR_BP" , 0x11800080004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
|
|
{"GMX1_TX_OVR_BP" , 0x11800100004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
|
|
{"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
|
|
{"GMX1_TX_PAUSE_PKT_DMAC" , 0x11800100004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
|
|
{"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
|
|
{"GMX1_TX_PAUSE_PKT_TYPE" , 0x11800100004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
|
|
{"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
|
|
{"GMX1_TX_PRTS" , 0x1180010000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
|
|
{"GMX0_TX_XAUI_CTL" , 0x1180008000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
|
|
{"GMX1_TX_XAUI_CTL" , 0x1180010000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
|
|
{"GMX0_XAUI_EXT_LOOPBACK" , 0x1180008000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
|
|
{"GMX1_XAUI_EXT_LOOPBACK" , 0x1180010000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
|
|
{"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_CLK_GEN0" , 0x10700000008C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
|
|
{"GPIO_CLK_GEN1" , 0x10700000008C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
|
|
{"GPIO_CLK_GEN2" , 0x10700000008D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
|
|
{"GPIO_CLK_GEN3" , 0x10700000008D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
|
|
{"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 193},
|
|
{"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 194},
|
|
{"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 195},
|
|
{"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IOB_BIST_STATUS" , 0x11800F00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
|
|
{"IOB_CTL_STATUS" , 0x11800F0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
|
|
{"IOB_DWB_PRI_CNT" , 0x11800F0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
|
|
{"IOB_FAU_TIMEOUT" , 0x11800F0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
|
|
{"IOB_I2C_PRI_CNT" , 0x11800F0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
|
|
{"IOB_INB_CONTROL_MATCH" , 0x11800F0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
|
|
{"IOB_INB_CONTROL_MATCH_ENB" , 0x11800F0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
|
|
{"IOB_INB_DATA_MATCH" , 0x11800F0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
|
|
{"IOB_INB_DATA_MATCH_ENB" , 0x11800F0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 205},
|
|
{"IOB_INT_ENB" , 0x11800F0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 206},
|
|
{"IOB_INT_SUM" , 0x11800F0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 207},
|
|
{"IOB_N2C_L2C_PRI_CNT" , 0x11800F0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 208},
|
|
{"IOB_N2C_RSP_PRI_CNT" , 0x11800F0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 209},
|
|
{"IOB_OUTB_COM_PRI_CNT" , 0x11800F0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 210},
|
|
{"IOB_OUTB_CONTROL_MATCH" , 0x11800F0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
|
|
{"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800F00000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
|
|
{"IOB_OUTB_DATA_MATCH" , 0x11800F0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
|
|
{"IOB_OUTB_DATA_MATCH_ENB" , 0x11800F00000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
|
|
{"IOB_OUTB_FPA_PRI_CNT" , 0x11800F0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
|
|
{"IOB_OUTB_REQ_PRI_CNT" , 0x11800F0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
|
|
{"IOB_P2C_REQ_PRI_CNT" , 0x11800F0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
|
|
{"IOB_PKT_ERR" , 0x11800F0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
|
|
{"IPD_1ST_MBUFF_SKIP" , 0x14F0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
|
|
{"IPD_1ST_NEXT_PTR_BACK" , 0x14F0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
|
|
{"IPD_2ND_NEXT_PTR_BACK" , 0x14F0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
|
|
{"IPD_BIST_STATUS" , 0x14F00000007F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
|
|
{"IPD_BP_PRT_RED_END" , 0x14F0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
|
|
{"IPD_CLK_COUNT" , 0x14F0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
|
|
{"IPD_CTL_STATUS" , 0x14F0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 225},
|
|
{"IPD_INT_ENB" , 0x14F0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 226},
|
|
{"IPD_INT_SUM" , 0x14F0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 227},
|
|
{"IPD_NOT_1ST_MBUFF_SKIP" , 0x14F0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 228},
|
|
{"IPD_PACKET_MBUFF_SIZE" , 0x14F0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 229},
|
|
{"IPD_PKT_PTR_VALID" , 0x14F0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 230},
|
|
{"IPD_PORT0_BP_PAGE_CNT" , 0x14F0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
|
|
{"IPD_PORT1_BP_PAGE_CNT" , 0x14F0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
|
|
{"IPD_PORT2_BP_PAGE_CNT" , 0x14F0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
|
|
{"IPD_PORT3_BP_PAGE_CNT" , 0x14F0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
|
|
{"IPD_PORT16_BP_PAGE_CNT" , 0x14F00000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
|
|
{"IPD_PORT17_BP_PAGE_CNT" , 0x14F00000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
|
|
{"IPD_PORT18_BP_PAGE_CNT" , 0x14F00000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
|
|
{"IPD_PORT19_BP_PAGE_CNT" , 0x14F00000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
|
|
{"IPD_PORT36_BP_PAGE_CNT2" , 0x14F0000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 232},
|
|
{"IPD_PORT37_BP_PAGE_CNT2" , 0x14F0000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 232},
|
|
{"IPD_PORT38_BP_PAGE_CNT2" , 0x14F0000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 232},
|
|
{"IPD_PORT39_BP_PAGE_CNT2" , 0x14F0000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 232},
|
|
{"IPD_PORT_BP_COUNTERS2_PAIR36", 0x14F0000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 233},
|
|
{"IPD_PORT_BP_COUNTERS2_PAIR37", 0x14F0000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 233},
|
|
{"IPD_PORT_BP_COUNTERS2_PAIR38", 0x14F0000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 233},
|
|
{"IPD_PORT_BP_COUNTERS2_PAIR39", 0x14F00000003A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 233},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14F00000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14F00000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14F00000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR3" , 0x14F00000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR16" , 0x14F0000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR17" , 0x14F0000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR18" , 0x14F0000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR19" , 0x14F0000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
|
|
{"IPD_PORT_QOS_0_CNT" , 0x14F0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_1_CNT" , 0x14F0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_2_CNT" , 0x14F0000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_3_CNT" , 0x14F00000008A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_4_CNT" , 0x14F00000008A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_5_CNT" , 0x14F00000008B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_6_CNT" , 0x14F00000008B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_7_CNT" , 0x14F00000008C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_8_CNT" , 0x14F00000008C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_9_CNT" , 0x14F00000008D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_10_CNT" , 0x14F00000008D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_11_CNT" , 0x14F00000008E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_12_CNT" , 0x14F00000008E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_13_CNT" , 0x14F00000008F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_14_CNT" , 0x14F00000008F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_15_CNT" , 0x14F0000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_16_CNT" , 0x14F0000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_17_CNT" , 0x14F0000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_18_CNT" , 0x14F0000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_19_CNT" , 0x14F0000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_20_CNT" , 0x14F0000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_21_CNT" , 0x14F0000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_22_CNT" , 0x14F0000000938ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_23_CNT" , 0x14F0000000940ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_24_CNT" , 0x14F0000000948ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_25_CNT" , 0x14F0000000950ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_26_CNT" , 0x14F0000000958ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_27_CNT" , 0x14F0000000960ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_28_CNT" , 0x14F0000000968ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_29_CNT" , 0x14F0000000970ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_30_CNT" , 0x14F0000000978ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_31_CNT" , 0x14F0000000980ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_128_CNT" , 0x14F0000000C88ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_129_CNT" , 0x14F0000000C90ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_130_CNT" , 0x14F0000000C98ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_131_CNT" , 0x14F0000000CA0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_132_CNT" , 0x14F0000000CA8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_133_CNT" , 0x14F0000000CB0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_134_CNT" , 0x14F0000000CB8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_135_CNT" , 0x14F0000000CC0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_136_CNT" , 0x14F0000000CC8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_137_CNT" , 0x14F0000000CD0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_138_CNT" , 0x14F0000000CD8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_139_CNT" , 0x14F0000000CE0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_140_CNT" , 0x14F0000000CE8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_141_CNT" , 0x14F0000000CF0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_142_CNT" , 0x14F0000000CF8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_143_CNT" , 0x14F0000000D00ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_144_CNT" , 0x14F0000000D08ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_145_CNT" , 0x14F0000000D10ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_146_CNT" , 0x14F0000000D18ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_147_CNT" , 0x14F0000000D20ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_148_CNT" , 0x14F0000000D28ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_149_CNT" , 0x14F0000000D30ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_150_CNT" , 0x14F0000000D38ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_151_CNT" , 0x14F0000000D40ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_152_CNT" , 0x14F0000000D48ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_153_CNT" , 0x14F0000000D50ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_154_CNT" , 0x14F0000000D58ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_155_CNT" , 0x14F0000000D60ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_156_CNT" , 0x14F0000000D68ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_157_CNT" , 0x14F0000000D70ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_158_CNT" , 0x14F0000000D78ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_159_CNT" , 0x14F0000000D80ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_288_CNT" , 0x14F0000001188ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_289_CNT" , 0x14F0000001190ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_290_CNT" , 0x14F0000001198ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_291_CNT" , 0x14F00000011A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_292_CNT" , 0x14F00000011A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_293_CNT" , 0x14F00000011B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_294_CNT" , 0x14F00000011B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_295_CNT" , 0x14F00000011C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_296_CNT" , 0x14F00000011C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_297_CNT" , 0x14F00000011D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_298_CNT" , 0x14F00000011D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_299_CNT" , 0x14F00000011E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_300_CNT" , 0x14F00000011E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_301_CNT" , 0x14F00000011F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_302_CNT" , 0x14F00000011F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_303_CNT" , 0x14F0000001200ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_304_CNT" , 0x14F0000001208ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_305_CNT" , 0x14F0000001210ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_306_CNT" , 0x14F0000001218ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_307_CNT" , 0x14F0000001220ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_308_CNT" , 0x14F0000001228ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_309_CNT" , 0x14F0000001230ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_310_CNT" , 0x14F0000001238ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_311_CNT" , 0x14F0000001240ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_312_CNT" , 0x14F0000001248ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_313_CNT" , 0x14F0000001250ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_314_CNT" , 0x14F0000001258ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_315_CNT" , 0x14F0000001260ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_316_CNT" , 0x14F0000001268ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_317_CNT" , 0x14F0000001270ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_318_CNT" , 0x14F0000001278ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_319_CNT" , 0x14F0000001280ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_INT0" , 0x14F0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
|
|
{"IPD_PORT_QOS_INT2" , 0x14F0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
|
|
{"IPD_PORT_QOS_INT4" , 0x14F0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
|
|
{"IPD_PORT_QOS_INT_ENB0" , 0x14F0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
|
|
{"IPD_PORT_QOS_INT_ENB2" , 0x14F0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
|
|
{"IPD_PORT_QOS_INT_ENB4" , 0x14F0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
|
|
{"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14F0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
|
|
{"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14F0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
|
|
{"IPD_PTR_COUNT" , 0x14F0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
|
|
{"IPD_PWP_PTR_FIFO_CTL" , 0x14F0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
|
|
{"IPD_QOS0_RED_MARKS" , 0x14F0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
|
|
{"IPD_QOS1_RED_MARKS" , 0x14F0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
|
|
{"IPD_QOS2_RED_MARKS" , 0x14F0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
|
|
{"IPD_QOS3_RED_MARKS" , 0x14F0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
|
|
{"IPD_QOS4_RED_MARKS" , 0x14F0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
|
|
{"IPD_QOS5_RED_MARKS" , 0x14F00000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
|
|
{"IPD_QOS6_RED_MARKS" , 0x14F00000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
|
|
{"IPD_QOS7_RED_MARKS" , 0x14F00000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
|
|
{"IPD_QUE0_FREE_PAGE_CNT" , 0x14F0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
|
|
{"IPD_RED_PORT_ENABLE" , 0x14F00000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
|
|
{"IPD_RED_PORT_ENABLE2" , 0x14F00000003A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
|
|
{"IPD_RED_QUE0_PARAM" , 0x14F00000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_RED_QUE1_PARAM" , 0x14F00000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_RED_QUE2_PARAM" , 0x14F00000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_RED_QUE3_PARAM" , 0x14F00000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_RED_QUE4_PARAM" , 0x14F0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_RED_QUE5_PARAM" , 0x14F0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_RED_QUE6_PARAM" , 0x14F0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_RED_QUE7_PARAM" , 0x14F0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14F0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_SUB_PORT_FCS" , 0x14F0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
|
|
{"IPD_SUB_PORT_QOS_CNT" , 0x14F0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
|
|
{"IPD_WQE_FPA_QUEUE" , 0x14F0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_WQE_PTR_VALID" , 0x14F0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
|
|
{"KEY_BIST_REG" , 0x1180020000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
|
|
{"KEY_CTL_STATUS" , 0x1180020000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
|
|
{"KEY_INT_ENB" , 0x1180020000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
|
|
{"KEY_INT_SUM" , 0x1180020000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
|
|
{"L2C_BST0" , 0x11800800007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
|
|
{"L2C_BST1" , 0x11800800007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
|
|
{"L2C_BST2" , 0x11800800007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
|
|
{"L2C_CFG" , 0x1180080000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
|
|
{"L2C_DBG" , 0x1180080000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
|
|
{"L2C_DUT" , 0x1180080000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
|
|
{"L2C_GRPWRR0" , 0x11800800000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
|
|
{"L2C_GRPWRR1" , 0x11800800000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
|
|
{"L2C_INT_EN" , 0x1180080000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
|
|
{"L2C_INT_STAT" , 0x11800800000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
|
|
{"L2C_LCKBASE" , 0x1180080000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
|
|
{"L2C_LCKOFF" , 0x1180080000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
|
|
{"L2C_LFB0" , 0x1180080000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
|
|
{"L2C_LFB1" , 0x1180080000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
|
|
{"L2C_LFB2" , 0x1180080000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
|
|
{"L2C_LFB3" , 0x11800800000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
|
|
{"L2C_OOB" , 0x11800800000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
|
|
{"L2C_OOB1" , 0x11800800000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
|
|
{"L2C_OOB2" , 0x11800800000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
|
|
{"L2C_OOB3" , 0x11800800000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
|
|
{"L2C_PFC0" , 0x1180080000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
|
|
{"L2C_PFC1" , 0x11800800000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
|
|
{"L2C_PFC2" , 0x11800800000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
|
|
{"L2C_PFC3" , 0x11800800000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
|
|
{"L2C_PFCTL" , 0x1180080000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
|
|
{"L2C_PPGRP" , 0x11800800000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
|
|
{"L2C_SPAR0" , 0x1180080000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
|
|
{"L2C_SPAR1" , 0x1180080000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
|
|
{"L2C_SPAR2" , 0x1180080000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
|
|
{"L2C_SPAR4" , 0x1180080000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
|
|
{"L2D_BST0" , 0x1180080000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
|
|
{"L2D_BST1" , 0x1180080000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
|
|
{"L2D_BST2" , 0x1180080000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
|
|
{"L2D_BST3" , 0x1180080000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
|
|
{"L2D_ERR" , 0x1180080000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
|
|
{"L2D_FADR" , 0x1180080000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
|
|
{"L2D_FSYN0" , 0x1180080000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 289},
|
|
{"L2D_FSYN1" , 0x1180080000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
|
|
{"L2D_FUS0" , 0x11800800007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
|
|
{"L2D_FUS1" , 0x11800800007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
|
|
{"L2D_FUS2" , 0x11800800007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
|
|
{"L2D_FUS3" , 0x11800800007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
|
|
{"L2T_ERR" , 0x1180080000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
|
|
{"LED_BLINK" , 0x1180000001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
|
|
{"LED_CLK_PHASE" , 0x1180000001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
|
|
{"LED_CYLON" , 0x1180000001AF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
|
|
{"LED_DBG" , 0x1180000001A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
|
|
{"LED_EN" , 0x1180000001A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
|
|
{"LED_POLARITY" , 0x1180000001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
|
|
{"LED_PRT" , 0x1180000001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
|
|
{"LED_PRT_FMT" , 0x1180000001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
|
|
{"LED_PRT_STATUS0" , 0x1180000001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
|
|
{"LED_PRT_STATUS1" , 0x1180000001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
|
|
{"LED_PRT_STATUS2" , 0x1180000001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
|
|
{"LED_PRT_STATUS3" , 0x1180000001A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
|
|
{"LED_PRT_STATUS4" , 0x1180000001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
|
|
{"LED_PRT_STATUS5" , 0x1180000001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
|
|
{"LED_PRT_STATUS6" , 0x1180000001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
|
|
{"LED_PRT_STATUS7" , 0x1180000001AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
|
|
{"LED_UDD_CNT0" , 0x1180000001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
|
|
{"LED_UDD_CNT1" , 0x1180000001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
|
|
{"LED_UDD_DAT0" , 0x1180000001A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
|
|
{"LED_UDD_DAT1" , 0x1180000001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
|
|
{"LED_UDD_DAT_CLR0" , 0x1180000001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
|
|
{"LED_UDD_DAT_CLR1" , 0x1180000001AD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
|
|
{"LED_UDD_DAT_SET0" , 0x1180000001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
|
|
{"LED_UDD_DAT_SET1" , 0x1180000001AD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
|
|
{"LMC0_BIST_CTL" , 0x11800880000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
|
|
{"LMC1_BIST_CTL" , 0x11800E80000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
|
|
{"LMC0_BIST_RESULT" , 0x11800880000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
|
|
{"LMC1_BIST_RESULT" , 0x11800E80000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
|
|
{"LMC0_COMP_CTL" , 0x1180088000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
|
|
{"LMC1_COMP_CTL" , 0x11800E8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
|
|
{"LMC0_CTL" , 0x1180088000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
|
|
{"LMC1_CTL" , 0x11800E8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
|
|
{"LMC0_CTL1" , 0x1180088000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
|
|
{"LMC1_CTL1" , 0x11800E8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
|
|
{"LMC0_DCLK_CNT_HI" , 0x1180088000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
|
|
{"LMC1_DCLK_CNT_HI" , 0x11800E8000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
|
|
{"LMC0_DCLK_CNT_LO" , 0x1180088000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
|
|
{"LMC1_DCLK_CNT_LO" , 0x11800E8000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
|
|
{"LMC0_DCLK_CTL" , 0x11800880000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
|
|
{"LMC1_DCLK_CTL" , 0x11800E80000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
|
|
{"LMC0_DDR2_CTL" , 0x1180088000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
|
|
{"LMC1_DDR2_CTL" , 0x11800E8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
|
|
{"LMC0_DELAY_CFG" , 0x1180088000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
|
|
{"LMC1_DELAY_CFG" , 0x11800E8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
|
|
{"LMC0_DLL_CTL" , 0x11800880000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
|
|
{"LMC1_DLL_CTL" , 0x11800E80000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
|
|
{"LMC0_DUAL_MEMCFG" , 0x1180088000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
|
|
{"LMC1_DUAL_MEMCFG" , 0x11800E8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
|
|
{"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
|
|
{"LMC1_ECC_SYND" , 0x11800E8000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
|
|
{"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
|
|
{"LMC1_FADR" , 0x11800E8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
|
|
{"LMC0_IFB_CNT_HI" , 0x1180088000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
|
|
{"LMC1_IFB_CNT_HI" , 0x11800E8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
|
|
{"LMC0_IFB_CNT_LO" , 0x1180088000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
|
|
{"LMC1_IFB_CNT_LO" , 0x11800E8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
|
|
{"LMC0_MEM_CFG0" , 0x1180088000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
|
|
{"LMC1_MEM_CFG0" , 0x11800E8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
|
|
{"LMC0_MEM_CFG1" , 0x1180088000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
|
|
{"LMC1_MEM_CFG1" , 0x11800E8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
|
|
{"LMC0_OPS_CNT_HI" , 0x1180088000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
|
|
{"LMC1_OPS_CNT_HI" , 0x11800E8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
|
|
{"LMC0_OPS_CNT_LO" , 0x1180088000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 328},
|
|
{"LMC1_OPS_CNT_LO" , 0x11800E8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 328},
|
|
{"LMC0_PLL_CTL" , 0x11800880000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
|
|
{"LMC1_PLL_CTL" , 0x11800E80000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
|
|
{"LMC0_PLL_STATUS" , 0x11800880000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
|
|
{"LMC1_PLL_STATUS" , 0x11800E80000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
|
|
{"LMC0_READ_LEVEL_CTL" , 0x1180088000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 331},
|
|
{"LMC1_READ_LEVEL_CTL" , 0x11800E8000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 331},
|
|
{"LMC0_READ_LEVEL_DBG" , 0x1180088000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
|
|
{"LMC1_READ_LEVEL_DBG" , 0x11800E8000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
|
|
{"LMC0_READ_LEVEL_RANK000" , 0x1180088000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
|
|
{"LMC0_READ_LEVEL_RANK001" , 0x1180088000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
|
|
{"LMC0_READ_LEVEL_RANK002" , 0x1180088000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
|
|
{"LMC0_READ_LEVEL_RANK003" , 0x1180088000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
|
|
{"LMC1_READ_LEVEL_RANK000" , 0x11800E8000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
|
|
{"LMC1_READ_LEVEL_RANK001" , 0x11800E8000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
|
|
{"LMC1_READ_LEVEL_RANK002" , 0x11800E8000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
|
|
{"LMC1_READ_LEVEL_RANK003" , 0x11800E8000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
|
|
{"LMC0_RODT_COMP_CTL" , 0x11800880000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 334},
|
|
{"LMC1_RODT_COMP_CTL" , 0x11800E80000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 334},
|
|
{"LMC0_RODT_CTL" , 0x1180088000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 335},
|
|
{"LMC1_RODT_CTL" , 0x11800E8000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 335},
|
|
{"LMC0_WODT_CTL0" , 0x1180088000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 336},
|
|
{"LMC1_WODT_CTL0" , 0x11800E8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 336},
|
|
{"LMC0_WODT_CTL1" , 0x1180088000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 337},
|
|
{"LMC1_WODT_CTL1" , 0x11800E8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 337},
|
|
{"MIO_BOOT_BIST_STAT" , 0x11800000000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 338},
|
|
{"MIO_BOOT_COMP" , 0x11800000000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 339},
|
|
{"MIO_BOOT_DMA_CFG0" , 0x1180000000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 340},
|
|
{"MIO_BOOT_DMA_CFG1" , 0x1180000000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 340},
|
|
{"MIO_BOOT_DMA_CFG2" , 0x1180000000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 340},
|
|
{"MIO_BOOT_DMA_INT0" , 0x1180000000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 341},
|
|
{"MIO_BOOT_DMA_INT1" , 0x1180000000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 341},
|
|
{"MIO_BOOT_DMA_INT2" , 0x1180000000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 341},
|
|
{"MIO_BOOT_DMA_INT_EN0" , 0x1180000000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 342},
|
|
{"MIO_BOOT_DMA_INT_EN1" , 0x1180000000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 342},
|
|
{"MIO_BOOT_DMA_INT_EN2" , 0x1180000000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 342},
|
|
{"MIO_BOOT_DMA_TIM0" , 0x1180000000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
|
|
{"MIO_BOOT_DMA_TIM1" , 0x1180000000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
|
|
{"MIO_BOOT_DMA_TIM2" , 0x1180000000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
|
|
{"MIO_BOOT_ERR" , 0x11800000000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
|
|
{"MIO_BOOT_INT" , 0x11800000000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 345},
|
|
{"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
|
|
{"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
|
|
{"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
|
|
{"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 348},
|
|
{"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
|
|
{"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
|
|
{"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
|
|
{"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
|
|
{"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
|
|
{"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
|
|
{"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
|
|
{"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
|
|
{"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
|
|
{"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
|
|
{"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
|
|
{"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
|
|
{"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
|
|
{"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
|
|
{"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
|
|
{"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
|
|
{"MIO_BOOT_THR" , 0x11800000000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 351},
|
|
{"MIO_FUS_BNK_DAT0" , 0x1180000001520ull, CVMX_CSR_DB_TYPE_RSL, 64, 352},
|
|
{"MIO_FUS_BNK_DAT1" , 0x1180000001528ull, CVMX_CSR_DB_TYPE_RSL, 64, 352},
|
|
{"MIO_FUS_BNK_DAT2" , 0x1180000001530ull, CVMX_CSR_DB_TYPE_RSL, 64, 352},
|
|
{"MIO_FUS_BNK_DAT3" , 0x1180000001538ull, CVMX_CSR_DB_TYPE_RSL, 64, 352},
|
|
{"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 353},
|
|
{"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 354},
|
|
{"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 355},
|
|
{"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
|
|
{"MIO_FUS_EMA" , 0x1180000001550ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
|
|
{"MIO_FUS_PDF" , 0x1180000001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
|
|
{"MIO_FUS_PLL" , 0x1180000001580ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
|
|
{"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 360},
|
|
{"MIO_FUS_PROG_TIMES" , 0x1180000001518ull, CVMX_CSR_DB_TYPE_RSL, 64, 361},
|
|
{"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 362},
|
|
{"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
|
|
{"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 364},
|
|
{"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
|
|
{"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
|
|
{"MIO_TWS1_INT" , 0x1180000001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
|
|
{"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
|
|
{"MIO_TWS1_SW_TWSI" , 0x1180000001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
|
|
{"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
|
|
{"MIO_TWS1_SW_TWSI_EXT" , 0x1180000001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
|
|
{"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
|
|
{"MIO_TWS1_TWSI_SW" , 0x1180000001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
|
|
{"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
|
|
{"MIO_UART1_DLH" , 0x1180000000C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
|
|
{"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
|
|
{"MIO_UART1_DLL" , 0x1180000000C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
|
|
{"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
|
|
{"MIO_UART1_FAR" , 0x1180000000D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
|
|
{"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
|
|
{"MIO_UART1_FCR" , 0x1180000000C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
|
|
{"MIO_UART0_HTX" , 0x1180000000B08ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
|
|
{"MIO_UART1_HTX" , 0x1180000000F08ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
|
|
{"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
|
|
{"MIO_UART1_IER" , 0x1180000000C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
|
|
{"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
|
|
{"MIO_UART1_IIR" , 0x1180000000C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
|
|
{"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
|
|
{"MIO_UART1_LCR" , 0x1180000000C18ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
|
|
{"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
|
|
{"MIO_UART1_LSR" , 0x1180000000C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
|
|
{"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
|
|
{"MIO_UART1_MCR" , 0x1180000000C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
|
|
{"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
|
|
{"MIO_UART1_MSR" , 0x1180000000C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
|
|
{"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
|
|
{"MIO_UART1_RBR" , 0x1180000000C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
|
|
{"MIO_UART0_RFL" , 0x1180000000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
|
|
{"MIO_UART1_RFL" , 0x1180000000E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
|
|
{"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
|
|
{"MIO_UART1_RFW" , 0x1180000000D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
|
|
{"MIO_UART0_SBCR" , 0x1180000000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
|
|
{"MIO_UART1_SBCR" , 0x1180000000E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
|
|
{"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
|
|
{"MIO_UART1_SCR" , 0x1180000000C38ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
|
|
{"MIO_UART0_SFE" , 0x1180000000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
|
|
{"MIO_UART1_SFE" , 0x1180000000E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
|
|
{"MIO_UART0_SRR" , 0x1180000000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
|
|
{"MIO_UART1_SRR" , 0x1180000000E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
|
|
{"MIO_UART0_SRT" , 0x1180000000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
|
|
{"MIO_UART1_SRT" , 0x1180000000E38ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
|
|
{"MIO_UART0_SRTS" , 0x1180000000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
|
|
{"MIO_UART1_SRTS" , 0x1180000000E18ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
|
|
{"MIO_UART0_STT" , 0x1180000000B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
|
|
{"MIO_UART1_STT" , 0x1180000000F00ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
|
|
{"MIO_UART0_TFL" , 0x1180000000A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
|
|
{"MIO_UART1_TFL" , 0x1180000000E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
|
|
{"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
|
|
{"MIO_UART1_TFR" , 0x1180000000D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
|
|
{"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
|
|
{"MIO_UART1_THR" , 0x1180000000C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
|
|
{"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
|
|
{"MIO_UART1_USR" , 0x1180000000D38ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
|
|
{"MIX0_BIST" , 0x1070000100078ull, CVMX_CSR_DB_TYPE_NCB, 64, 395},
|
|
{"MIX0_CTL" , 0x1070000100020ull, CVMX_CSR_DB_TYPE_NCB, 64, 396},
|
|
{"MIX0_INTENA" , 0x1070000100050ull, CVMX_CSR_DB_TYPE_NCB, 64, 397},
|
|
{"MIX0_IRCNT" , 0x1070000100030ull, CVMX_CSR_DB_TYPE_NCB, 64, 398},
|
|
{"MIX0_IRHWM" , 0x1070000100028ull, CVMX_CSR_DB_TYPE_NCB, 64, 399},
|
|
{"MIX0_IRING1" , 0x1070000100010ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
|
|
{"MIX0_IRING2" , 0x1070000100018ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
|
|
{"MIX0_ISR" , 0x1070000100048ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
|
|
{"MIX0_ORCNT" , 0x1070000100040ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
|
|
{"MIX0_ORHWM" , 0x1070000100038ull, CVMX_CSR_DB_TYPE_NCB, 64, 404},
|
|
{"MIX0_ORING1" , 0x1070000100000ull, CVMX_CSR_DB_TYPE_NCB, 64, 405},
|
|
{"MIX0_ORING2" , 0x1070000100008ull, CVMX_CSR_DB_TYPE_NCB, 64, 406},
|
|
{"MIX0_REMCNT" , 0x1070000100058ull, CVMX_CSR_DB_TYPE_NCB, 64, 407},
|
|
{"NPEI_BAR1_INDEX0" , 0x11F0000008000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX1" , 0x11F0000008010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX2" , 0x11F0000008020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX3" , 0x11F0000008030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX4" , 0x11F0000008040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX5" , 0x11F0000008050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX6" , 0x11F0000008060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX7" , 0x11F0000008070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX8" , 0x11F0000008080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX9" , 0x11F0000008090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX10" , 0x11F00000080A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX11" , 0x11F00000080B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX12" , 0x11F00000080C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX13" , 0x11F00000080D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX14" , 0x11F00000080E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX15" , 0x11F00000080F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX16" , 0x11F0000008100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX17" , 0x11F0000008110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX18" , 0x11F0000008120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX19" , 0x11F0000008130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX20" , 0x11F0000008140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX21" , 0x11F0000008150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX22" , 0x11F0000008160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX23" , 0x11F0000008170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX24" , 0x11F0000008180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX25" , 0x11F0000008190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX26" , 0x11F00000081A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX27" , 0x11F00000081B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX28" , 0x11F00000081C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX29" , 0x11F00000081D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX30" , 0x11F00000081E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BAR1_INDEX31" , 0x11F00000081F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 408},
|
|
{"NPEI_BIST_STATUS" , 0x11F0000008580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 409},
|
|
{"NPEI_CTL_PORT0" , 0x11F0000008250ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 410},
|
|
{"NPEI_CTL_PORT1" , 0x11F0000008260ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 411},
|
|
{"NPEI_CTL_STATUS" , 0x11F0000008570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 412},
|
|
{"NPEI_CTL_STATUS2" , 0x11F000000BC00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 413},
|
|
{"NPEI_DATA_OUT_CNT" , 0x11F00000085F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 414},
|
|
{"NPEI_DBG_DATA" , 0x11F0000008510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 415},
|
|
{"NPEI_DBG_SELECT" , 0x11F0000008500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 416},
|
|
{"NPEI_DMA0_COUNTS" , 0x11F0000008450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 417},
|
|
{"NPEI_DMA1_COUNTS" , 0x11F0000008460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 417},
|
|
{"NPEI_DMA2_COUNTS" , 0x11F0000008470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 417},
|
|
{"NPEI_DMA3_COUNTS" , 0x11F0000008480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 417},
|
|
{"NPEI_DMA4_COUNTS" , 0x11F0000008490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 417},
|
|
{"NPEI_DMA0_DBELL" , 0x11F00000083B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 418},
|
|
{"NPEI_DMA1_DBELL" , 0x11F00000083C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 418},
|
|
{"NPEI_DMA2_DBELL" , 0x11F00000083D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 418},
|
|
{"NPEI_DMA3_DBELL" , 0x11F00000083E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 418},
|
|
{"NPEI_DMA4_DBELL" , 0x11F00000083F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 418},
|
|
{"NPEI_DMA0_IBUFF_SADDR" , 0x11F0000008400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 419},
|
|
{"NPEI_DMA1_IBUFF_SADDR" , 0x11F0000008410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 419},
|
|
{"NPEI_DMA2_IBUFF_SADDR" , 0x11F0000008420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 419},
|
|
{"NPEI_DMA3_IBUFF_SADDR" , 0x11F0000008430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 419},
|
|
{"NPEI_DMA4_IBUFF_SADDR" , 0x11F0000008440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 419},
|
|
{"NPEI_DMA0_NADDR" , 0x11F00000084A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 420},
|
|
{"NPEI_DMA1_NADDR" , 0x11F00000084B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 420},
|
|
{"NPEI_DMA2_NADDR" , 0x11F00000084C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 420},
|
|
{"NPEI_DMA3_NADDR" , 0x11F00000084D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 420},
|
|
{"NPEI_DMA4_NADDR" , 0x11F00000084E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 420},
|
|
{"NPEI_DMA0_INT_LEVEL" , 0x11F00000085C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 421},
|
|
{"NPEI_DMA1_INT_LEVEL" , 0x11F00000085D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 422},
|
|
{"NPEI_DMA_CNTS" , 0x11F00000085E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 423},
|
|
{"NPEI_DMA_CONTROL" , 0x11F00000083A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 424},
|
|
{"NPEI_DMA_STATE1_P1" , 0x11F0000008680ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 425},
|
|
{"NPEI_DMA_STATE2_P1" , 0x11F0000008690ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 426},
|
|
{"NPEI_DMA_STATE3_P1" , 0x11F00000086A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 427},
|
|
{"NPEI_DMA_STATE4_P1" , 0x11F00000086B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 428},
|
|
{"NPEI_DMA_STATE5_P1" , 0x11F00000086C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 429},
|
|
{"NPEI_INT_ENB" , 0x11F0000008540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 430},
|
|
{"NPEI_INT_ENB2" , 0x11F000000BCD0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 431},
|
|
{"NPEI_INT_INFO" , 0x11F0000008590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 432},
|
|
{"NPEI_INT_SUM" , 0x11F0000008530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 433},
|
|
{"NPEI_LAST_WIN_RDATA0" , 0x11F0000008600ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 434},
|
|
{"NPEI_LAST_WIN_RDATA1" , 0x11F0000008610ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 435},
|
|
{"NPEI_MEM_ACCESS_CTL" , 0x11F00000084F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 436},
|
|
{"NPEI_MEM_ACCESS_SUBID12" , 0x11F0000008280ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
|
|
{"NPEI_MEM_ACCESS_SUBID13" , 0x11F0000008290ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
|
|
{"NPEI_MEM_ACCESS_SUBID14" , 0x11F00000082A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
|
|
{"NPEI_MEM_ACCESS_SUBID15" , 0x11F00000082B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
|
|
{"NPEI_MEM_ACCESS_SUBID16" , 0x11F00000082C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
|
|
{"NPEI_MEM_ACCESS_SUBID17" , 0x11F00000082D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
|
|
{"NPEI_MEM_ACCESS_SUBID18" , 0x11F00000082E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
|
|
{"NPEI_MEM_ACCESS_SUBID19" , 0x11F00000082F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
|
|
{"NPEI_MEM_ACCESS_SUBID20" , 0x11F0000008300ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
|
|
{"NPEI_MEM_ACCESS_SUBID21" , 0x11F0000008310ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
|
|
{"NPEI_MEM_ACCESS_SUBID22" , 0x11F0000008320ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
|
|
{"NPEI_MEM_ACCESS_SUBID23" , 0x11F0000008330ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
|
|
{"NPEI_MEM_ACCESS_SUBID24" , 0x11F0000008340ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
|
|
{"NPEI_MEM_ACCESS_SUBID25" , 0x11F0000008350ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
|
|
{"NPEI_MEM_ACCESS_SUBID26" , 0x11F0000008360ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
|
|
{"NPEI_MEM_ACCESS_SUBID27" , 0x11F0000008370ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
|
|
{"NPEI_MSI_ENB0" , 0x11F000000BC50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 438},
|
|
{"NPEI_MSI_ENB1" , 0x11F000000BC60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 439},
|
|
{"NPEI_MSI_ENB2" , 0x11F000000BC70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 440},
|
|
{"NPEI_MSI_ENB3" , 0x11F000000BC80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 441},
|
|
{"NPEI_MSI_RCV0" , 0x11F000000BC10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 442},
|
|
{"NPEI_MSI_RCV1" , 0x11F000000BC20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 443},
|
|
{"NPEI_MSI_RCV2" , 0x11F000000BC30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
|
|
{"NPEI_MSI_RCV3" , 0x11F000000BC40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 445},
|
|
{"NPEI_MSI_RD_MAP" , 0x11F000000BCA0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 446},
|
|
{"NPEI_MSI_WR_MAP" , 0x11F000000BC90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 447},
|
|
{"NPEI_PCIE_MSI_RCV" , 0x11F000000BCB0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 448},
|
|
{"NPEI_PCIE_MSI_RCV_B1" , 0x11F0000008650ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 449},
|
|
{"NPEI_PCIE_MSI_RCV_B2" , 0x11F0000008660ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 450},
|
|
{"NPEI_PCIE_MSI_RCV_B3" , 0x11F0000008670ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 451},
|
|
{"NPEI_RSL_INT_BLOCKS" , 0x11F0000008520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 452},
|
|
{"NPEI_SCRATCH_1" , 0x11F0000008270ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 453},
|
|
{"NPEI_STATE1" , 0x11F0000008620ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 454},
|
|
{"NPEI_STATE2" , 0x11F0000008630ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
|
|
{"NPEI_STATE3" , 0x11F0000008640ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 456},
|
|
{"NPEI_WIN_RD_ADDR" , 0x210ull, CVMX_CSR_DB_TYPE_PEXP, 64, 457},
|
|
{"NPEI_WIN_RD_DATA" , 0x240ull, CVMX_CSR_DB_TYPE_PEXP, 64, 458},
|
|
{"NPEI_WIN_WR_ADDR" , 0x200ull, CVMX_CSR_DB_TYPE_PEXP, 64, 459},
|
|
{"NPEI_WIN_WR_DATA" , 0x220ull, CVMX_CSR_DB_TYPE_PEXP, 64, 460},
|
|
{"NPEI_WIN_WR_MASK" , 0x230ull, CVMX_CSR_DB_TYPE_PEXP, 64, 461},
|
|
{"NPEI_WINDOW_CTL" , 0x11F0000008380ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 462},
|
|
{"PCIEEP_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 463},
|
|
{"PCIEEP_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 464},
|
|
{"PCIEEP_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 465},
|
|
{"PCIEEP_CFG003" , 0xCull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 466},
|
|
{"PCIEEP_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 467},
|
|
{"PCIEEP_CFG004_MASK" , 0x80000010ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 468},
|
|
{"PCIEEP_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 469},
|
|
{"PCIEEP_CFG005_MASK" , 0x80000014ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 470},
|
|
{"PCIEEP_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 471},
|
|
{"PCIEEP_CFG006_MASK" , 0x80000018ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 472},
|
|
{"PCIEEP_CFG007" , 0x1Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 473},
|
|
{"PCIEEP_CFG007_MASK" , 0x8000001Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 474},
|
|
{"PCIEEP_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 475},
|
|
{"PCIEEP_CFG008_MASK" , 0x80000020ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 476},
|
|
{"PCIEEP_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 477},
|
|
{"PCIEEP_CFG009_MASK" , 0x80000024ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 478},
|
|
{"PCIEEP_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 479},
|
|
{"PCIEEP_CFG011" , 0x2Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 480},
|
|
{"PCIEEP_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 481},
|
|
{"PCIEEP_CFG012_MASK" , 0x80000030ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 482},
|
|
{"PCIEEP_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 483},
|
|
{"PCIEEP_CFG015" , 0x3Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 484},
|
|
{"PCIEEP_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 485},
|
|
{"PCIEEP_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 486},
|
|
{"PCIEEP_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 487},
|
|
{"PCIEEP_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 488},
|
|
{"PCIEEP_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 489},
|
|
{"PCIEEP_CFG023" , 0x5Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 490},
|
|
{"PCIEEP_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 491},
|
|
{"PCIEEP_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 492},
|
|
{"PCIEEP_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 493},
|
|
{"PCIEEP_CFG031" , 0x7Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 494},
|
|
{"PCIEEP_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 495},
|
|
{"PCIEEP_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 496},
|
|
{"PCIEEP_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 497},
|
|
{"PCIEEP_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 498},
|
|
{"PCIEEP_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 499},
|
|
{"PCIEEP_CFG039" , 0x9Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 500},
|
|
{"PCIEEP_CFG040" , 0xA0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 501},
|
|
{"PCIEEP_CFG041" , 0xA4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 502},
|
|
{"PCIEEP_CFG042" , 0xA8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 503},
|
|
{"PCIEEP_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 504},
|
|
{"PCIEEP_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 505},
|
|
{"PCIEEP_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 506},
|
|
{"PCIEEP_CFG067" , 0x10Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 507},
|
|
{"PCIEEP_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 508},
|
|
{"PCIEEP_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 509},
|
|
{"PCIEEP_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 510},
|
|
{"PCIEEP_CFG071" , 0x11Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 511},
|
|
{"PCIEEP_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 512},
|
|
{"PCIEEP_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 513},
|
|
{"PCIEEP_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 514},
|
|
{"PCIEEP_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 515},
|
|
{"PCIEEP_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 516},
|
|
{"PCIEEP_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 517},
|
|
{"PCIEEP_CFG451" , 0x70Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 518},
|
|
{"PCIEEP_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 519},
|
|
{"PCIEEP_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 520},
|
|
{"PCIEEP_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 521},
|
|
{"PCIEEP_CFG455" , 0x71Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 522},
|
|
{"PCIEEP_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 523},
|
|
{"PCIEEP_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 524},
|
|
{"PCIEEP_CFG459" , 0x72Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 525},
|
|
{"PCIEEP_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 526},
|
|
{"PCIEEP_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 527},
|
|
{"PCIEEP_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 528},
|
|
{"PCIEEP_CFG463" , 0x73Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 529},
|
|
{"PCIEEP_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 530},
|
|
{"PCIEEP_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 531},
|
|
{"PCIEEP_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 532},
|
|
{"PCIEEP_CFG467" , 0x74Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 533},
|
|
{"PCIEEP_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 534},
|
|
{"PCIEEP_CFG490" , 0x7A8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 535},
|
|
{"PCIEEP_CFG491" , 0x7ACull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 536},
|
|
{"PCIEEP_CFG492" , 0x7B0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 537},
|
|
{"PCIEEP_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 538},
|
|
{"PCIEEP_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 539},
|
|
{"PCIERC0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 540},
|
|
{"PCIERC1_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 540},
|
|
{"PCIERC0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 541},
|
|
{"PCIERC1_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 541},
|
|
{"PCIERC0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 542},
|
|
{"PCIERC1_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 542},
|
|
{"PCIERC0_CFG003" , 0xCull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 543},
|
|
{"PCIERC1_CFG003" , 0xCull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 543},
|
|
{"PCIERC0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 544},
|
|
{"PCIERC1_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 544},
|
|
{"PCIERC0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 545},
|
|
{"PCIERC1_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 545},
|
|
{"PCIERC0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 546},
|
|
{"PCIERC1_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 546},
|
|
{"PCIERC0_CFG007" , 0x1Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 547},
|
|
{"PCIERC1_CFG007" , 0x1Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 547},
|
|
{"PCIERC0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 548},
|
|
{"PCIERC1_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 548},
|
|
{"PCIERC0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 549},
|
|
{"PCIERC1_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 549},
|
|
{"PCIERC0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 550},
|
|
{"PCIERC1_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 550},
|
|
{"PCIERC0_CFG011" , 0x2Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 551},
|
|
{"PCIERC1_CFG011" , 0x2Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 551},
|
|
{"PCIERC0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 552},
|
|
{"PCIERC1_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 552},
|
|
{"PCIERC0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 553},
|
|
{"PCIERC1_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 553},
|
|
{"PCIERC0_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 554},
|
|
{"PCIERC1_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 554},
|
|
{"PCIERC0_CFG015" , 0x3Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 555},
|
|
{"PCIERC1_CFG015" , 0x3Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 555},
|
|
{"PCIERC0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 556},
|
|
{"PCIERC1_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 556},
|
|
{"PCIERC0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 557},
|
|
{"PCIERC1_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 557},
|
|
{"PCIERC0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 558},
|
|
{"PCIERC1_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 558},
|
|
{"PCIERC0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 559},
|
|
{"PCIERC1_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 559},
|
|
{"PCIERC0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 560},
|
|
{"PCIERC1_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 560},
|
|
{"PCIERC0_CFG023" , 0x5Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 561},
|
|
{"PCIERC1_CFG023" , 0x5Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 561},
|
|
{"PCIERC0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 562},
|
|
{"PCIERC1_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 562},
|
|
{"PCIERC0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 563},
|
|
{"PCIERC1_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 563},
|
|
{"PCIERC0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 564},
|
|
{"PCIERC1_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 564},
|
|
{"PCIERC0_CFG031" , 0x7Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 565},
|
|
{"PCIERC1_CFG031" , 0x7Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 565},
|
|
{"PCIERC0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 566},
|
|
{"PCIERC1_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 566},
|
|
{"PCIERC0_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 567},
|
|
{"PCIERC1_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 567},
|
|
{"PCIERC0_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 568},
|
|
{"PCIERC1_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 568},
|
|
{"PCIERC0_CFG035" , 0x8Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 569},
|
|
{"PCIERC1_CFG035" , 0x8Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 569},
|
|
{"PCIERC0_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 570},
|
|
{"PCIERC1_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 570},
|
|
{"PCIERC0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 571},
|
|
{"PCIERC1_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 571},
|
|
{"PCIERC0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 572},
|
|
{"PCIERC1_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 572},
|
|
{"PCIERC0_CFG039" , 0x9Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 573},
|
|
{"PCIERC1_CFG039" , 0x9Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 573},
|
|
{"PCIERC0_CFG040" , 0xA0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 574},
|
|
{"PCIERC1_CFG040" , 0xA0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 574},
|
|
{"PCIERC0_CFG041" , 0xA4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 575},
|
|
{"PCIERC1_CFG041" , 0xA4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 575},
|
|
{"PCIERC0_CFG042" , 0xA8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 576},
|
|
{"PCIERC1_CFG042" , 0xA8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 576},
|
|
{"PCIERC0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 577},
|
|
{"PCIERC1_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 577},
|
|
{"PCIERC0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 578},
|
|
{"PCIERC1_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 578},
|
|
{"PCIERC0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 579},
|
|
{"PCIERC1_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 579},
|
|
{"PCIERC0_CFG067" , 0x10Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 580},
|
|
{"PCIERC1_CFG067" , 0x10Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 580},
|
|
{"PCIERC0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 581},
|
|
{"PCIERC1_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 581},
|
|
{"PCIERC0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 582},
|
|
{"PCIERC1_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 582},
|
|
{"PCIERC0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 583},
|
|
{"PCIERC1_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 583},
|
|
{"PCIERC0_CFG071" , 0x11Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 584},
|
|
{"PCIERC1_CFG071" , 0x11Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 584},
|
|
{"PCIERC0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 585},
|
|
{"PCIERC1_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 585},
|
|
{"PCIERC0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 586},
|
|
{"PCIERC1_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 586},
|
|
{"PCIERC0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 587},
|
|
{"PCIERC1_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 587},
|
|
{"PCIERC0_CFG075" , 0x12Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 588},
|
|
{"PCIERC1_CFG075" , 0x12Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 588},
|
|
{"PCIERC0_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 589},
|
|
{"PCIERC1_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 589},
|
|
{"PCIERC0_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 590},
|
|
{"PCIERC1_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 590},
|
|
{"PCIERC0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 591},
|
|
{"PCIERC1_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 591},
|
|
{"PCIERC0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 592},
|
|
{"PCIERC1_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 592},
|
|
{"PCIERC0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 593},
|
|
{"PCIERC1_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 593},
|
|
{"PCIERC0_CFG451" , 0x70Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 594},
|
|
{"PCIERC1_CFG451" , 0x70Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 594},
|
|
{"PCIERC0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 595},
|
|
{"PCIERC1_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 595},
|
|
{"PCIERC0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 596},
|
|
{"PCIERC1_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 596},
|
|
{"PCIERC0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 597},
|
|
{"PCIERC1_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 597},
|
|
{"PCIERC0_CFG455" , 0x71Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 598},
|
|
{"PCIERC1_CFG455" , 0x71Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 598},
|
|
{"PCIERC0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 599},
|
|
{"PCIERC1_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 599},
|
|
{"PCIERC0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 600},
|
|
{"PCIERC1_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 600},
|
|
{"PCIERC0_CFG459" , 0x72Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 601},
|
|
{"PCIERC1_CFG459" , 0x72Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 601},
|
|
{"PCIERC0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 602},
|
|
{"PCIERC1_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 602},
|
|
{"PCIERC0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 603},
|
|
{"PCIERC1_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 603},
|
|
{"PCIERC0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 604},
|
|
{"PCIERC1_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 604},
|
|
{"PCIERC0_CFG463" , 0x73Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 605},
|
|
{"PCIERC1_CFG463" , 0x73Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 605},
|
|
{"PCIERC0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 606},
|
|
{"PCIERC1_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 606},
|
|
{"PCIERC0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 607},
|
|
{"PCIERC1_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 607},
|
|
{"PCIERC0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 608},
|
|
{"PCIERC1_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 608},
|
|
{"PCIERC0_CFG467" , 0x74Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 609},
|
|
{"PCIERC1_CFG467" , 0x74Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 609},
|
|
{"PCIERC0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 610},
|
|
{"PCIERC1_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 610},
|
|
{"PCIERC0_CFG490" , 0x7A8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 611},
|
|
{"PCIERC1_CFG490" , 0x7A8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 611},
|
|
{"PCIERC0_CFG491" , 0x7ACull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 612},
|
|
{"PCIERC1_CFG491" , 0x7ACull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 612},
|
|
{"PCIERC0_CFG492" , 0x7B0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 613},
|
|
{"PCIERC1_CFG492" , 0x7B0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 613},
|
|
{"PCIERC0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 614},
|
|
{"PCIERC1_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 614},
|
|
{"PCIERC0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 615},
|
|
{"PCIERC1_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 615},
|
|
{"PCS0_AN000_ADV_REG" , 0x11800B0001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 616},
|
|
{"PCS0_AN001_ADV_REG" , 0x11800B0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 616},
|
|
{"PCS0_AN002_ADV_REG" , 0x11800B0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 616},
|
|
{"PCS0_AN003_ADV_REG" , 0x11800B0001C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 616},
|
|
{"PCS1_AN000_ADV_REG" , 0x11800B8001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 616},
|
|
{"PCS1_AN001_ADV_REG" , 0x11800B8001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 616},
|
|
{"PCS1_AN002_ADV_REG" , 0x11800B8001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 616},
|
|
{"PCS1_AN003_ADV_REG" , 0x11800B8001C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 616},
|
|
{"PCS0_AN000_EXT_ST_REG" , 0x11800B0001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
|
|
{"PCS0_AN001_EXT_ST_REG" , 0x11800B0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
|
|
{"PCS0_AN002_EXT_ST_REG" , 0x11800B0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
|
|
{"PCS0_AN003_EXT_ST_REG" , 0x11800B0001C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
|
|
{"PCS1_AN000_EXT_ST_REG" , 0x11800B8001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
|
|
{"PCS1_AN001_EXT_ST_REG" , 0x11800B8001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
|
|
{"PCS1_AN002_EXT_ST_REG" , 0x11800B8001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
|
|
{"PCS1_AN003_EXT_ST_REG" , 0x11800B8001C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 617},
|
|
{"PCS0_AN000_LP_ABIL_REG" , 0x11800B0001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 618},
|
|
{"PCS0_AN001_LP_ABIL_REG" , 0x11800B0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 618},
|
|
{"PCS0_AN002_LP_ABIL_REG" , 0x11800B0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 618},
|
|
{"PCS0_AN003_LP_ABIL_REG" , 0x11800B0001C18ull, CVMX_CSR_DB_TYPE_RSL, 64, 618},
|
|
{"PCS1_AN000_LP_ABIL_REG" , 0x11800B8001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 618},
|
|
{"PCS1_AN001_LP_ABIL_REG" , 0x11800B8001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 618},
|
|
{"PCS1_AN002_LP_ABIL_REG" , 0x11800B8001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 618},
|
|
{"PCS1_AN003_LP_ABIL_REG" , 0x11800B8001C18ull, CVMX_CSR_DB_TYPE_RSL, 64, 618},
|
|
{"PCS0_AN000_RESULTS_REG" , 0x11800B0001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 619},
|
|
{"PCS0_AN001_RESULTS_REG" , 0x11800B0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 619},
|
|
{"PCS0_AN002_RESULTS_REG" , 0x11800B0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 619},
|
|
{"PCS0_AN003_RESULTS_REG" , 0x11800B0001C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 619},
|
|
{"PCS1_AN000_RESULTS_REG" , 0x11800B8001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 619},
|
|
{"PCS1_AN001_RESULTS_REG" , 0x11800B8001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 619},
|
|
{"PCS1_AN002_RESULTS_REG" , 0x11800B8001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 619},
|
|
{"PCS1_AN003_RESULTS_REG" , 0x11800B8001C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 619},
|
|
{"PCS0_INT000_EN_REG" , 0x11800B0001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 620},
|
|
{"PCS0_INT001_EN_REG" , 0x11800B0001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 620},
|
|
{"PCS0_INT002_EN_REG" , 0x11800B0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 620},
|
|
{"PCS0_INT003_EN_REG" , 0x11800B0001C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 620},
|
|
{"PCS1_INT000_EN_REG" , 0x11800B8001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 620},
|
|
{"PCS1_INT001_EN_REG" , 0x11800B8001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 620},
|
|
{"PCS1_INT002_EN_REG" , 0x11800B8001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 620},
|
|
{"PCS1_INT003_EN_REG" , 0x11800B8001C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 620},
|
|
{"PCS0_INT000_REG" , 0x11800B0001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 621},
|
|
{"PCS0_INT001_REG" , 0x11800B0001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 621},
|
|
{"PCS0_INT002_REG" , 0x11800B0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 621},
|
|
{"PCS0_INT003_REG" , 0x11800B0001C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 621},
|
|
{"PCS1_INT000_REG" , 0x11800B8001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 621},
|
|
{"PCS1_INT001_REG" , 0x11800B8001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 621},
|
|
{"PCS1_INT002_REG" , 0x11800B8001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 621},
|
|
{"PCS1_INT003_REG" , 0x11800B8001C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 621},
|
|
{"PCS0_LINK000_TIMER_COUNT_REG", 0x11800B0001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 622},
|
|
{"PCS0_LINK001_TIMER_COUNT_REG", 0x11800B0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 622},
|
|
{"PCS0_LINK002_TIMER_COUNT_REG", 0x11800B0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 622},
|
|
{"PCS0_LINK003_TIMER_COUNT_REG", 0x11800B0001C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 622},
|
|
{"PCS1_LINK000_TIMER_COUNT_REG", 0x11800B8001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 622},
|
|
{"PCS1_LINK001_TIMER_COUNT_REG", 0x11800B8001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 622},
|
|
{"PCS1_LINK002_TIMER_COUNT_REG", 0x11800B8001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 622},
|
|
{"PCS1_LINK003_TIMER_COUNT_REG", 0x11800B8001C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 622},
|
|
{"PCS0_LOG_ANL000_REG" , 0x11800B0001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
|
|
{"PCS0_LOG_ANL001_REG" , 0x11800B0001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
|
|
{"PCS0_LOG_ANL002_REG" , 0x11800B0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
|
|
{"PCS0_LOG_ANL003_REG" , 0x11800B0001C90ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
|
|
{"PCS1_LOG_ANL000_REG" , 0x11800B8001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
|
|
{"PCS1_LOG_ANL001_REG" , 0x11800B8001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
|
|
{"PCS1_LOG_ANL002_REG" , 0x11800B8001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
|
|
{"PCS1_LOG_ANL003_REG" , 0x11800B8001C90ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
|
|
{"PCS0_MISC000_CTL_REG" , 0x11800B0001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
|
|
{"PCS0_MISC001_CTL_REG" , 0x11800B0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
|
|
{"PCS0_MISC002_CTL_REG" , 0x11800B0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
|
|
{"PCS0_MISC003_CTL_REG" , 0x11800B0001C78ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
|
|
{"PCS1_MISC000_CTL_REG" , 0x11800B8001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
|
|
{"PCS1_MISC001_CTL_REG" , 0x11800B8001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
|
|
{"PCS1_MISC002_CTL_REG" , 0x11800B8001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
|
|
{"PCS1_MISC003_CTL_REG" , 0x11800B8001C78ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
|
|
{"PCS0_MR000_CONTROL_REG" , 0x11800B0001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
|
|
{"PCS0_MR001_CONTROL_REG" , 0x11800B0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
|
|
{"PCS0_MR002_CONTROL_REG" , 0x11800B0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
|
|
{"PCS0_MR003_CONTROL_REG" , 0x11800B0001C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
|
|
{"PCS1_MR000_CONTROL_REG" , 0x11800B8001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
|
|
{"PCS1_MR001_CONTROL_REG" , 0x11800B8001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
|
|
{"PCS1_MR002_CONTROL_REG" , 0x11800B8001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
|
|
{"PCS1_MR003_CONTROL_REG" , 0x11800B8001C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
|
|
{"PCS0_MR000_STATUS_REG" , 0x11800B0001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
|
|
{"PCS0_MR001_STATUS_REG" , 0x11800B0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
|
|
{"PCS0_MR002_STATUS_REG" , 0x11800B0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
|
|
{"PCS0_MR003_STATUS_REG" , 0x11800B0001C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
|
|
{"PCS1_MR000_STATUS_REG" , 0x11800B8001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
|
|
{"PCS1_MR001_STATUS_REG" , 0x11800B8001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
|
|
{"PCS1_MR002_STATUS_REG" , 0x11800B8001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
|
|
{"PCS1_MR003_STATUS_REG" , 0x11800B8001C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
|
|
{"PCS0_RX000_STATES_REG" , 0x11800B0001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
|
|
{"PCS0_RX001_STATES_REG" , 0x11800B0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
|
|
{"PCS0_RX002_STATES_REG" , 0x11800B0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
|
|
{"PCS0_RX003_STATES_REG" , 0x11800B0001C58ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
|
|
{"PCS1_RX000_STATES_REG" , 0x11800B8001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
|
|
{"PCS1_RX001_STATES_REG" , 0x11800B8001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
|
|
{"PCS1_RX002_STATES_REG" , 0x11800B8001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
|
|
{"PCS1_RX003_STATES_REG" , 0x11800B8001C58ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
|
|
{"PCS0_RX000_SYNC_REG" , 0x11800B0001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
|
|
{"PCS0_RX001_SYNC_REG" , 0x11800B0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
|
|
{"PCS0_RX002_SYNC_REG" , 0x11800B0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
|
|
{"PCS0_RX003_SYNC_REG" , 0x11800B0001C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
|
|
{"PCS1_RX000_SYNC_REG" , 0x11800B8001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
|
|
{"PCS1_RX001_SYNC_REG" , 0x11800B8001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
|
|
{"PCS1_RX002_SYNC_REG" , 0x11800B8001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
|
|
{"PCS1_RX003_SYNC_REG" , 0x11800B8001C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
|
|
{"PCS0_SGM000_AN_ADV_REG" , 0x11800B0001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
|
|
{"PCS0_SGM001_AN_ADV_REG" , 0x11800B0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
|
|
{"PCS0_SGM002_AN_ADV_REG" , 0x11800B0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
|
|
{"PCS0_SGM003_AN_ADV_REG" , 0x11800B0001C68ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
|
|
{"PCS1_SGM000_AN_ADV_REG" , 0x11800B8001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
|
|
{"PCS1_SGM001_AN_ADV_REG" , 0x11800B8001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
|
|
{"PCS1_SGM002_AN_ADV_REG" , 0x11800B8001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
|
|
{"PCS1_SGM003_AN_ADV_REG" , 0x11800B8001C68ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
|
|
{"PCS0_SGM000_LP_ADV_REG" , 0x11800B0001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
|
|
{"PCS0_SGM001_LP_ADV_REG" , 0x11800B0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
|
|
{"PCS0_SGM002_LP_ADV_REG" , 0x11800B0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
|
|
{"PCS0_SGM003_LP_ADV_REG" , 0x11800B0001C70ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
|
|
{"PCS1_SGM000_LP_ADV_REG" , 0x11800B8001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
|
|
{"PCS1_SGM001_LP_ADV_REG" , 0x11800B8001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
|
|
{"PCS1_SGM002_LP_ADV_REG" , 0x11800B8001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
|
|
{"PCS1_SGM003_LP_ADV_REG" , 0x11800B8001C70ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
|
|
{"PCS0_TX000_STATES_REG" , 0x11800B0001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
|
|
{"PCS0_TX001_STATES_REG" , 0x11800B0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
|
|
{"PCS0_TX002_STATES_REG" , 0x11800B0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
|
|
{"PCS0_TX003_STATES_REG" , 0x11800B0001C60ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
|
|
{"PCS1_TX000_STATES_REG" , 0x11800B8001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
|
|
{"PCS1_TX001_STATES_REG" , 0x11800B8001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
|
|
{"PCS1_TX002_STATES_REG" , 0x11800B8001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
|
|
{"PCS1_TX003_STATES_REG" , 0x11800B8001C60ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
|
|
{"PCS0_TX_RX000_POLARITY_REG" , 0x11800B0001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
|
|
{"PCS0_TX_RX001_POLARITY_REG" , 0x11800B0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
|
|
{"PCS0_TX_RX002_POLARITY_REG" , 0x11800B0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
|
|
{"PCS0_TX_RX003_POLARITY_REG" , 0x11800B0001C48ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
|
|
{"PCS1_TX_RX000_POLARITY_REG" , 0x11800B8001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
|
|
{"PCS1_TX_RX001_POLARITY_REG" , 0x11800B8001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
|
|
{"PCS1_TX_RX002_POLARITY_REG" , 0x11800B8001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
|
|
{"PCS1_TX_RX003_POLARITY_REG" , 0x11800B8001C48ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
|
|
{"PCSX0_10GBX_STATUS_REG" , 0x11800B0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 633},
|
|
{"PCSX1_10GBX_STATUS_REG" , 0x11800B8000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 633},
|
|
{"PCSX0_BIST_STATUS_REG" , 0x11800B0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 634},
|
|
{"PCSX1_BIST_STATUS_REG" , 0x11800B8000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 634},
|
|
{"PCSX0_BIT_LOCK_STATUS_REG" , 0x11800B0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 635},
|
|
{"PCSX1_BIT_LOCK_STATUS_REG" , 0x11800B8000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 635},
|
|
{"PCSX0_CONTROL1_REG" , 0x11800B0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
|
|
{"PCSX1_CONTROL1_REG" , 0x11800B8000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
|
|
{"PCSX0_CONTROL2_REG" , 0x11800B0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 637},
|
|
{"PCSX1_CONTROL2_REG" , 0x11800B8000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 637},
|
|
{"PCSX0_INT_EN_REG" , 0x11800B0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
|
|
{"PCSX1_INT_EN_REG" , 0x11800B8000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
|
|
{"PCSX0_INT_REG" , 0x11800B0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 639},
|
|
{"PCSX1_INT_REG" , 0x11800B8000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 639},
|
|
{"PCSX0_LOG_ANL_REG" , 0x11800B0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
|
|
{"PCSX1_LOG_ANL_REG" , 0x11800B8000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
|
|
{"PCSX0_MISC_CTL_REG" , 0x11800B0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 641},
|
|
{"PCSX1_MISC_CTL_REG" , 0x11800B8000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 641},
|
|
{"PCSX0_RX_SYNC_STATES_REG" , 0x11800B0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
|
|
{"PCSX1_RX_SYNC_STATES_REG" , 0x11800B8000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
|
|
{"PCSX0_SPD_ABIL_REG" , 0x11800B0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 643},
|
|
{"PCSX1_SPD_ABIL_REG" , 0x11800B8000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 643},
|
|
{"PCSX0_STATUS1_REG" , 0x11800B0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
|
|
{"PCSX1_STATUS1_REG" , 0x11800B8000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
|
|
{"PCSX0_STATUS2_REG" , 0x11800B0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 645},
|
|
{"PCSX1_STATUS2_REG" , 0x11800B8000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 645},
|
|
{"PCSX0_TX_RX_POLARITY_REG" , 0x11800B0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
|
|
{"PCSX1_TX_RX_POLARITY_REG" , 0x11800B8000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
|
|
{"PCSX0_TX_RX_STATES_REG" , 0x11800B0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 647},
|
|
{"PCSX1_TX_RX_STATES_REG" , 0x11800B8000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 647},
|
|
{"PESC0_BIST_STATUS" , 0x11800C8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 648},
|
|
{"PESC1_BIST_STATUS" , 0x11800D0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 648},
|
|
{"PESC0_BIST_STATUS2" , 0x11800C8000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 649},
|
|
{"PESC1_BIST_STATUS2" , 0x11800D0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 649},
|
|
{"PESC0_CFG_RD" , 0x11800C8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 650},
|
|
{"PESC1_CFG_RD" , 0x11800D0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 650},
|
|
{"PESC0_CFG_WR" , 0x11800C8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 651},
|
|
{"PESC1_CFG_WR" , 0x11800D0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 651},
|
|
{"PESC0_CPL_LUT_VALID" , 0x11800C8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 652},
|
|
{"PESC1_CPL_LUT_VALID" , 0x11800D0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 652},
|
|
{"PESC0_CTL_STATUS" , 0x11800C8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 653},
|
|
{"PESC1_CTL_STATUS" , 0x11800D0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 653},
|
|
{"PESC0_CTL_STATUS2" , 0x11800C8000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 654},
|
|
{"PESC1_CTL_STATUS2" , 0x11800D0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 654},
|
|
{"PESC0_DBG_INFO" , 0x11800C8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 655},
|
|
{"PESC1_DBG_INFO" , 0x11800D0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 655},
|
|
{"PESC0_DBG_INFO_EN" , 0x11800C80000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 656},
|
|
{"PESC1_DBG_INFO_EN" , 0x11800D00000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 656},
|
|
{"PESC0_DIAG_STATUS" , 0x11800C8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 657},
|
|
{"PESC1_DIAG_STATUS" , 0x11800D0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 657},
|
|
{"PESC0_P2N_BAR0_START" , 0x11800C8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 658},
|
|
{"PESC1_P2N_BAR0_START" , 0x11800D0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 658},
|
|
{"PESC0_P2N_BAR1_START" , 0x11800C8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 659},
|
|
{"PESC1_P2N_BAR1_START" , 0x11800D0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 659},
|
|
{"PESC0_P2N_BAR2_START" , 0x11800C8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 660},
|
|
{"PESC1_P2N_BAR2_START" , 0x11800D0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 660},
|
|
{"PESC0_P2P_BAR000_END" , 0x11800C8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
|
|
{"PESC0_P2P_BAR001_END" , 0x11800C8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
|
|
{"PESC0_P2P_BAR002_END" , 0x11800C8000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
|
|
{"PESC0_P2P_BAR003_END" , 0x11800C8000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
|
|
{"PESC1_P2P_BAR000_END" , 0x11800D0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
|
|
{"PESC1_P2P_BAR001_END" , 0x11800D0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
|
|
{"PESC1_P2P_BAR002_END" , 0x11800D0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
|
|
{"PESC1_P2P_BAR003_END" , 0x11800D0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
|
|
{"PESC0_P2P_BAR000_START" , 0x11800C8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
|
|
{"PESC0_P2P_BAR001_START" , 0x11800C8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
|
|
{"PESC0_P2P_BAR002_START" , 0x11800C8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
|
|
{"PESC0_P2P_BAR003_START" , 0x11800C8000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
|
|
{"PESC1_P2P_BAR000_START" , 0x11800D0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
|
|
{"PESC1_P2P_BAR001_START" , 0x11800D0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
|
|
{"PESC1_P2P_BAR002_START" , 0x11800D0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
|
|
{"PESC1_P2P_BAR003_START" , 0x11800D0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
|
|
{"PESC0_TLP_CREDITS" , 0x11800C8000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 663},
|
|
{"PESC1_TLP_CREDITS" , 0x11800D0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 663},
|
|
{"PIP_BCK_PRS" , 0x11800A0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 664},
|
|
{"PIP_BIST_STATUS" , 0x11800A0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 665},
|
|
{"PIP_DEC_IPSEC0" , 0x11800A0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 666},
|
|
{"PIP_DEC_IPSEC1" , 0x11800A0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 666},
|
|
{"PIP_DEC_IPSEC2" , 0x11800A0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 666},
|
|
{"PIP_DEC_IPSEC3" , 0x11800A0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 666},
|
|
{"PIP_FRM_LEN_CHK0" , 0x11800A0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 667},
|
|
{"PIP_FRM_LEN_CHK1" , 0x11800A0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 667},
|
|
{"PIP_GBL_CFG" , 0x11800A0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
|
|
{"PIP_GBL_CTL" , 0x11800A0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
|
|
{"PIP_INT_EN" , 0x11800A0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 670},
|
|
{"PIP_INT_REG" , 0x11800A0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 671},
|
|
{"PIP_IP_OFFSET" , 0x11800A0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 672},
|
|
{"PIP_PRT_CFG0" , 0x11800A0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
|
|
{"PIP_PRT_CFG1" , 0x11800A0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
|
|
{"PIP_PRT_CFG2" , 0x11800A0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
|
|
{"PIP_PRT_CFG3" , 0x11800A0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
|
|
{"PIP_PRT_CFG16" , 0x11800A0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
|
|
{"PIP_PRT_CFG17" , 0x11800A0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
|
|
{"PIP_PRT_CFG18" , 0x11800A0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
|
|
{"PIP_PRT_CFG19" , 0x11800A0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
|
|
{"PIP_PRT_CFG36" , 0x11800A0000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
|
|
{"PIP_PRT_CFG37" , 0x11800A0000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
|
|
{"PIP_PRT_CFG38" , 0x11800A0000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
|
|
{"PIP_PRT_CFG39" , 0x11800A0000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
|
|
{"PIP_PRT_TAG0" , 0x11800A0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
|
|
{"PIP_PRT_TAG1" , 0x11800A0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
|
|
{"PIP_PRT_TAG2" , 0x11800A0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
|
|
{"PIP_PRT_TAG3" , 0x11800A0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
|
|
{"PIP_PRT_TAG16" , 0x11800A0000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
|
|
{"PIP_PRT_TAG17" , 0x11800A0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
|
|
{"PIP_PRT_TAG18" , 0x11800A0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
|
|
{"PIP_PRT_TAG19" , 0x11800A0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
|
|
{"PIP_PRT_TAG36" , 0x11800A0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
|
|
{"PIP_PRT_TAG37" , 0x11800A0000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
|
|
{"PIP_PRT_TAG38" , 0x11800A0000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
|
|
{"PIP_PRT_TAG39" , 0x11800A0000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
|
|
{"PIP_QOS_DIFF0" , 0x11800A0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF1" , 0x11800A0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF2" , 0x11800A0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF3" , 0x11800A0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF4" , 0x11800A0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF5" , 0x11800A0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF6" , 0x11800A0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF7" , 0x11800A0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF8" , 0x11800A0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF9" , 0x11800A0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF10" , 0x11800A0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF11" , 0x11800A0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF12" , 0x11800A0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF13" , 0x11800A0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF14" , 0x11800A0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF15" , 0x11800A0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF16" , 0x11800A0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF17" , 0x11800A0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF18" , 0x11800A0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF19" , 0x11800A0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF20" , 0x11800A00006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF21" , 0x11800A00006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF22" , 0x11800A00006B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF23" , 0x11800A00006B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF24" , 0x11800A00006C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF25" , 0x11800A00006C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF26" , 0x11800A00006D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF27" , 0x11800A00006D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF28" , 0x11800A00006E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF29" , 0x11800A00006E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF30" , 0x11800A00006F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF31" , 0x11800A00006F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF32" , 0x11800A0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF33" , 0x11800A0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF34" , 0x11800A0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF35" , 0x11800A0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF36" , 0x11800A0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF37" , 0x11800A0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF38" , 0x11800A0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF39" , 0x11800A0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF40" , 0x11800A0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF41" , 0x11800A0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF42" , 0x11800A0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF43" , 0x11800A0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF44" , 0x11800A0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF45" , 0x11800A0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF46" , 0x11800A0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF47" , 0x11800A0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF48" , 0x11800A0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF49" , 0x11800A0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF50" , 0x11800A0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF51" , 0x11800A0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF52" , 0x11800A00007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF53" , 0x11800A00007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF54" , 0x11800A00007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF55" , 0x11800A00007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF56" , 0x11800A00007C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF57" , 0x11800A00007C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF58" , 0x11800A00007D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF59" , 0x11800A00007D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF60" , 0x11800A00007E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF61" , 0x11800A00007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF62" , 0x11800A00007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_DIFF63" , 0x11800A00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_QOS_VLAN0" , 0x11800A00000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
|
|
{"PIP_QOS_VLAN1" , 0x11800A00000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
|
|
{"PIP_QOS_VLAN2" , 0x11800A00000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
|
|
{"PIP_QOS_VLAN3" , 0x11800A00000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
|
|
{"PIP_QOS_VLAN4" , 0x11800A00000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
|
|
{"PIP_QOS_VLAN5" , 0x11800A00000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
|
|
{"PIP_QOS_VLAN6" , 0x11800A00000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
|
|
{"PIP_QOS_VLAN7" , 0x11800A00000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
|
|
{"PIP_QOS_WATCH0" , 0x11800A0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
|
|
{"PIP_QOS_WATCH1" , 0x11800A0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
|
|
{"PIP_QOS_WATCH2" , 0x11800A0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
|
|
{"PIP_QOS_WATCH3" , 0x11800A0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
|
|
{"PIP_QOS_WATCH4" , 0x11800A0000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
|
|
{"PIP_QOS_WATCH5" , 0x11800A0000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
|
|
{"PIP_QOS_WATCH6" , 0x11800A0000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
|
|
{"PIP_QOS_WATCH7" , 0x11800A0000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
|
|
{"PIP_RAW_WORD" , 0x11800A00000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 678},
|
|
{"PIP_SFT_RST" , 0x11800A0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
|
|
{"PIP_STAT0_PRT0" , 0x11800A0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
|
|
{"PIP_STAT0_PRT1" , 0x11800A0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
|
|
{"PIP_STAT0_PRT2" , 0x11800A00008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
|
|
{"PIP_STAT0_PRT3" , 0x11800A00008F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
|
|
{"PIP_STAT0_PRT16" , 0x11800A0000D00ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
|
|
{"PIP_STAT0_PRT17" , 0x11800A0000D50ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
|
|
{"PIP_STAT0_PRT18" , 0x11800A0000DA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
|
|
{"PIP_STAT0_PRT19" , 0x11800A0000DF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
|
|
{"PIP_STAT0_PRT36" , 0x11800A0001340ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
|
|
{"PIP_STAT0_PRT37" , 0x11800A0001390ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
|
|
{"PIP_STAT0_PRT38" , 0x11800A00013E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
|
|
{"PIP_STAT0_PRT39" , 0x11800A0001430ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
|
|
{"PIP_STAT1_PRT0" , 0x11800A0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
|
|
{"PIP_STAT1_PRT1" , 0x11800A0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
|
|
{"PIP_STAT1_PRT2" , 0x11800A00008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
|
|
{"PIP_STAT1_PRT3" , 0x11800A00008F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
|
|
{"PIP_STAT1_PRT16" , 0x11800A0000D08ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
|
|
{"PIP_STAT1_PRT17" , 0x11800A0000D58ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
|
|
{"PIP_STAT1_PRT18" , 0x11800A0000DA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
|
|
{"PIP_STAT1_PRT19" , 0x11800A0000DF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
|
|
{"PIP_STAT1_PRT36" , 0x11800A0001348ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
|
|
{"PIP_STAT1_PRT37" , 0x11800A0001398ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
|
|
{"PIP_STAT1_PRT38" , 0x11800A00013E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
|
|
{"PIP_STAT1_PRT39" , 0x11800A0001438ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
|
|
{"PIP_STAT2_PRT0" , 0x11800A0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PIP_STAT2_PRT1" , 0x11800A0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PIP_STAT2_PRT2" , 0x11800A00008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PIP_STAT2_PRT3" , 0x11800A0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PIP_STAT2_PRT16" , 0x11800A0000D10ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PIP_STAT2_PRT17" , 0x11800A0000D60ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PIP_STAT2_PRT18" , 0x11800A0000DB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PIP_STAT2_PRT19" , 0x11800A0000E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PIP_STAT2_PRT36" , 0x11800A0001350ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PIP_STAT2_PRT37" , 0x11800A00013A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PIP_STAT2_PRT38" , 0x11800A00013F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PIP_STAT2_PRT39" , 0x11800A0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PIP_STAT3_PRT0" , 0x11800A0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PIP_STAT3_PRT1" , 0x11800A0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PIP_STAT3_PRT2" , 0x11800A00008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PIP_STAT3_PRT3" , 0x11800A0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PIP_STAT3_PRT16" , 0x11800A0000D18ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PIP_STAT3_PRT17" , 0x11800A0000D68ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PIP_STAT3_PRT18" , 0x11800A0000DB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PIP_STAT3_PRT19" , 0x11800A0000E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PIP_STAT3_PRT36" , 0x11800A0001358ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PIP_STAT3_PRT37" , 0x11800A00013A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PIP_STAT3_PRT38" , 0x11800A00013F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PIP_STAT3_PRT39" , 0x11800A0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PIP_STAT4_PRT0" , 0x11800A0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_STAT4_PRT1" , 0x11800A0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_STAT4_PRT2" , 0x11800A00008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_STAT4_PRT3" , 0x11800A0000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_STAT4_PRT16" , 0x11800A0000D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_STAT4_PRT17" , 0x11800A0000D70ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_STAT4_PRT18" , 0x11800A0000DC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_STAT4_PRT19" , 0x11800A0000E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_STAT4_PRT36" , 0x11800A0001360ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_STAT4_PRT37" , 0x11800A00013B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_STAT4_PRT38" , 0x11800A0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_STAT4_PRT39" , 0x11800A0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_STAT5_PRT0" , 0x11800A0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PIP_STAT5_PRT1" , 0x11800A0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PIP_STAT5_PRT2" , 0x11800A00008C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PIP_STAT5_PRT3" , 0x11800A0000918ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PIP_STAT5_PRT16" , 0x11800A0000D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PIP_STAT5_PRT17" , 0x11800A0000D78ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PIP_STAT5_PRT18" , 0x11800A0000DC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PIP_STAT5_PRT19" , 0x11800A0000E18ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PIP_STAT5_PRT36" , 0x11800A0001368ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PIP_STAT5_PRT37" , 0x11800A00013B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PIP_STAT5_PRT38" , 0x11800A0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PIP_STAT5_PRT39" , 0x11800A0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PIP_STAT6_PRT0" , 0x11800A0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PIP_STAT6_PRT1" , 0x11800A0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PIP_STAT6_PRT2" , 0x11800A00008D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PIP_STAT6_PRT3" , 0x11800A0000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PIP_STAT6_PRT16" , 0x11800A0000D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PIP_STAT6_PRT17" , 0x11800A0000D80ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PIP_STAT6_PRT18" , 0x11800A0000DD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PIP_STAT6_PRT19" , 0x11800A0000E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PIP_STAT6_PRT36" , 0x11800A0001370ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PIP_STAT6_PRT37" , 0x11800A00013C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PIP_STAT6_PRT38" , 0x11800A0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PIP_STAT6_PRT39" , 0x11800A0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PIP_STAT7_PRT0" , 0x11800A0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
|
|
{"PIP_STAT7_PRT1" , 0x11800A0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
|
|
{"PIP_STAT7_PRT2" , 0x11800A00008D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
|
|
{"PIP_STAT7_PRT3" , 0x11800A0000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
|
|
{"PIP_STAT7_PRT16" , 0x11800A0000D38ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
|
|
{"PIP_STAT7_PRT17" , 0x11800A0000D88ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
|
|
{"PIP_STAT7_PRT18" , 0x11800A0000DD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
|
|
{"PIP_STAT7_PRT19" , 0x11800A0000E28ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
|
|
{"PIP_STAT7_PRT36" , 0x11800A0001378ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
|
|
{"PIP_STAT7_PRT37" , 0x11800A00013C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
|
|
{"PIP_STAT7_PRT38" , 0x11800A0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
|
|
{"PIP_STAT7_PRT39" , 0x11800A0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
|
|
{"PIP_STAT8_PRT0" , 0x11800A0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
|
|
{"PIP_STAT8_PRT1" , 0x11800A0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
|
|
{"PIP_STAT8_PRT2" , 0x11800A00008E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
|
|
{"PIP_STAT8_PRT3" , 0x11800A0000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
|
|
{"PIP_STAT8_PRT16" , 0x11800A0000D40ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
|
|
{"PIP_STAT8_PRT17" , 0x11800A0000D90ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
|
|
{"PIP_STAT8_PRT18" , 0x11800A0000DE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
|
|
{"PIP_STAT8_PRT19" , 0x11800A0000E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
|
|
{"PIP_STAT8_PRT36" , 0x11800A0001380ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
|
|
{"PIP_STAT8_PRT37" , 0x11800A00013D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
|
|
{"PIP_STAT8_PRT38" , 0x11800A0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
|
|
{"PIP_STAT8_PRT39" , 0x11800A0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
|
|
{"PIP_STAT9_PRT0" , 0x11800A0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PIP_STAT9_PRT1" , 0x11800A0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PIP_STAT9_PRT2" , 0x11800A00008E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PIP_STAT9_PRT3" , 0x11800A0000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PIP_STAT9_PRT16" , 0x11800A0000D48ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PIP_STAT9_PRT17" , 0x11800A0000D98ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PIP_STAT9_PRT18" , 0x11800A0000DE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PIP_STAT9_PRT19" , 0x11800A0000E38ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PIP_STAT9_PRT36" , 0x11800A0001388ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PIP_STAT9_PRT37" , 0x11800A00013D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PIP_STAT9_PRT38" , 0x11800A0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PIP_STAT9_PRT39" , 0x11800A0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PIP_STAT_CTL" , 0x11800A0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
|
|
{"PIP_STAT_INB_ERRS0" , 0x11800A0001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PIP_STAT_INB_ERRS1" , 0x11800A0001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PIP_STAT_INB_ERRS2" , 0x11800A0001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PIP_STAT_INB_ERRS3" , 0x11800A0001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PIP_STAT_INB_ERRS16" , 0x11800A0001C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PIP_STAT_INB_ERRS17" , 0x11800A0001C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PIP_STAT_INB_ERRS18" , 0x11800A0001C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PIP_STAT_INB_ERRS19" , 0x11800A0001C70ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PIP_STAT_INB_ERRS36" , 0x11800A0001E90ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PIP_STAT_INB_ERRS37" , 0x11800A0001EB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PIP_STAT_INB_ERRS38" , 0x11800A0001ED0ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PIP_STAT_INB_ERRS39" , 0x11800A0001EF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PIP_STAT_INB_OCTS0" , 0x11800A0001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PIP_STAT_INB_OCTS1" , 0x11800A0001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PIP_STAT_INB_OCTS2" , 0x11800A0001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PIP_STAT_INB_OCTS3" , 0x11800A0001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PIP_STAT_INB_OCTS16" , 0x11800A0001C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PIP_STAT_INB_OCTS17" , 0x11800A0001C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PIP_STAT_INB_OCTS18" , 0x11800A0001C48ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PIP_STAT_INB_OCTS19" , 0x11800A0001C68ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PIP_STAT_INB_OCTS36" , 0x11800A0001E88ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PIP_STAT_INB_OCTS37" , 0x11800A0001EA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PIP_STAT_INB_OCTS38" , 0x11800A0001EC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PIP_STAT_INB_OCTS39" , 0x11800A0001EE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PIP_STAT_INB_PKTS0" , 0x11800A0001A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PIP_STAT_INB_PKTS1" , 0x11800A0001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PIP_STAT_INB_PKTS2" , 0x11800A0001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PIP_STAT_INB_PKTS3" , 0x11800A0001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PIP_STAT_INB_PKTS16" , 0x11800A0001C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PIP_STAT_INB_PKTS17" , 0x11800A0001C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PIP_STAT_INB_PKTS18" , 0x11800A0001C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PIP_STAT_INB_PKTS19" , 0x11800A0001C60ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PIP_STAT_INB_PKTS36" , 0x11800A0001E80ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PIP_STAT_INB_PKTS37" , 0x11800A0001EA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PIP_STAT_INB_PKTS38" , 0x11800A0001EC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PIP_STAT_INB_PKTS39" , 0x11800A0001EE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PIP_TAG_INC0" , 0x11800A0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC1" , 0x11800A0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC2" , 0x11800A0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC3" , 0x11800A0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC4" , 0x11800A0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC5" , 0x11800A0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC6" , 0x11800A0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC7" , 0x11800A0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC8" , 0x11800A0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC9" , 0x11800A0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC10" , 0x11800A0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC11" , 0x11800A0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC12" , 0x11800A0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC13" , 0x11800A0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC14" , 0x11800A0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC15" , 0x11800A0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC16" , 0x11800A0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC17" , 0x11800A0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC18" , 0x11800A0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC19" , 0x11800A0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC20" , 0x11800A00018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC21" , 0x11800A00018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC22" , 0x11800A00018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC23" , 0x11800A00018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC24" , 0x11800A00018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC25" , 0x11800A00018C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC26" , 0x11800A00018D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC27" , 0x11800A00018D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC28" , 0x11800A00018E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC29" , 0x11800A00018E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC30" , 0x11800A00018F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC31" , 0x11800A00018F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC32" , 0x11800A0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC33" , 0x11800A0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC34" , 0x11800A0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC35" , 0x11800A0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC36" , 0x11800A0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC37" , 0x11800A0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC38" , 0x11800A0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC39" , 0x11800A0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC40" , 0x11800A0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC41" , 0x11800A0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC42" , 0x11800A0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC43" , 0x11800A0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC44" , 0x11800A0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC45" , 0x11800A0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC46" , 0x11800A0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC47" , 0x11800A0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC48" , 0x11800A0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC49" , 0x11800A0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC50" , 0x11800A0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC51" , 0x11800A0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC52" , 0x11800A00019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC53" , 0x11800A00019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC54" , 0x11800A00019B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC55" , 0x11800A00019B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC56" , 0x11800A00019C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC57" , 0x11800A00019C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC58" , 0x11800A00019D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC59" , 0x11800A00019D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC60" , 0x11800A00019E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC61" , 0x11800A00019E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC62" , 0x11800A00019F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_INC63" , 0x11800A00019F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_TAG_MASK" , 0x11800A0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
|
|
{"PIP_TAG_SECRET" , 0x11800A0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
|
|
{"PIP_TODO_ENTRY" , 0x11800A0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
|
|
{"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
|
|
{"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
|
|
{"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
|
|
{"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
|
|
{"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
|
|
{"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
|
|
{"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
|
|
{"PKO_MEM_DEBUG14" , 0x1180050001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
|
|
{"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
|
|
{"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
|
|
{"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
|
|
{"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
|
|
{"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 711},
|
|
{"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 712},
|
|
{"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 713},
|
|
{"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 714},
|
|
{"PKO_MEM_PORT_PTRS" , 0x1180050001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 715},
|
|
{"PKO_MEM_PORT_QOS" , 0x1180050001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 716},
|
|
{"PKO_MEM_PORT_RATE0" , 0x1180050001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 717},
|
|
{"PKO_MEM_PORT_RATE1" , 0x1180050001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 718},
|
|
{"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 719},
|
|
{"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 720},
|
|
{"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 721},
|
|
{"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 722},
|
|
{"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 723},
|
|
{"PKO_REG_DEBUG1" , 0x11800500000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
|
|
{"PKO_REG_DEBUG2" , 0x11800500000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
|
|
{"PKO_REG_DEBUG3" , 0x11800500000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 726},
|
|
{"PKO_REG_ENGINE_INFLIGHT" , 0x1180050000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 727},
|
|
{"PKO_REG_ENGINE_THRESH" , 0x1180050000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 728},
|
|
{"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 729},
|
|
{"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
|
|
{"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 731},
|
|
{"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 732},
|
|
{"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 733},
|
|
{"PKO_REG_QUEUE_PTRS1" , 0x1180050000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 734},
|
|
{"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 735},
|
|
{"POW_BIST_STAT" , 0x16700000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 736},
|
|
{"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 737},
|
|
{"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 738},
|
|
{"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 739},
|
|
{"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 740},
|
|
{"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 740},
|
|
{"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 740},
|
|
{"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 740},
|
|
{"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 740},
|
|
{"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 740},
|
|
{"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 740},
|
|
{"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 740},
|
|
{"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 741},
|
|
{"POW_IQ_INT" , 0x1670000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 742},
|
|
{"POW_IQ_INT_EN" , 0x1670000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 743},
|
|
{"POW_IQ_THR0" , 0x16700000003A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 744},
|
|
{"POW_IQ_THR1" , 0x16700000003A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 744},
|
|
{"POW_IQ_THR2" , 0x16700000003B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 744},
|
|
{"POW_IQ_THR3" , 0x16700000003B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 744},
|
|
{"POW_IQ_THR4" , 0x16700000003C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 744},
|
|
{"POW_IQ_THR5" , 0x16700000003C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 744},
|
|
{"POW_IQ_THR6" , 0x16700000003D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 744},
|
|
{"POW_IQ_THR7" , 0x16700000003D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 744},
|
|
{"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 745},
|
|
{"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 746},
|
|
{"POW_PF_RST_MSK" , 0x1670000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 747},
|
|
{"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
|
|
{"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
|
|
{"POW_PP_GRP_MSK2" , 0x1670000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
|
|
{"POW_PP_GRP_MSK3" , 0x1670000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
|
|
{"POW_PP_GRP_MSK4" , 0x1670000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
|
|
{"POW_PP_GRP_MSK5" , 0x1670000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
|
|
{"POW_PP_GRP_MSK6" , 0x1670000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
|
|
{"POW_PP_GRP_MSK7" , 0x1670000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
|
|
{"POW_PP_GRP_MSK8" , 0x1670000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
|
|
{"POW_PP_GRP_MSK9" , 0x1670000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
|
|
{"POW_PP_GRP_MSK10" , 0x1670000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
|
|
{"POW_PP_GRP_MSK11" , 0x1670000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
|
|
{"POW_QOS_RND0" , 0x16700000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
|
|
{"POW_QOS_RND1" , 0x16700000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
|
|
{"POW_QOS_RND2" , 0x16700000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
|
|
{"POW_QOS_RND3" , 0x16700000001D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
|
|
{"POW_QOS_RND4" , 0x16700000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
|
|
{"POW_QOS_RND5" , 0x16700000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
|
|
{"POW_QOS_RND6" , 0x16700000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
|
|
{"POW_QOS_RND7" , 0x16700000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
|
|
{"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 750},
|
|
{"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 750},
|
|
{"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 750},
|
|
{"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 750},
|
|
{"POW_QOS_THR4" , 0x16700000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 750},
|
|
{"POW_QOS_THR5" , 0x16700000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 750},
|
|
{"POW_QOS_THR6" , 0x16700000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 750},
|
|
{"POW_QOS_THR7" , 0x16700000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 750},
|
|
{"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 751},
|
|
{"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 752},
|
|
{"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
|
|
{"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
|
|
{"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
|
|
{"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
|
|
{"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
|
|
{"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
|
|
{"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
|
|
{"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
|
|
{"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 754},
|
|
{"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
|
|
{"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
|
|
{"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
|
|
{"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
|
|
{"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
|
|
{"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
|
|
{"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
|
|
{"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
|
|
{"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
|
|
{"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
|
|
{"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
|
|
{"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
|
|
{"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
|
|
{"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
|
|
{"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
|
|
{"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
|
|
{"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 756},
|
|
{"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
|
|
{"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
|
|
{"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
|
|
{"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
|
|
{"POW_WQ_INT_THR4" , 0x16700000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
|
|
{"POW_WQ_INT_THR5" , 0x16700000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
|
|
{"POW_WQ_INT_THR6" , 0x16700000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
|
|
{"POW_WQ_INT_THR7" , 0x16700000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
|
|
{"POW_WQ_INT_THR8" , 0x16700000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
|
|
{"POW_WQ_INT_THR9" , 0x16700000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
|
|
{"POW_WQ_INT_THR10" , 0x16700000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
|
|
{"POW_WQ_INT_THR11" , 0x16700000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
|
|
{"POW_WQ_INT_THR12" , 0x16700000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
|
|
{"POW_WQ_INT_THR13" , 0x16700000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
|
|
{"POW_WQ_INT_THR14" , 0x16700000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
|
|
{"POW_WQ_INT_THR15" , 0x16700000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
|
|
{"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
|
|
{"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
|
|
{"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
|
|
{"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
|
|
{"POW_WS_PC4" , 0x16700000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
|
|
{"POW_WS_PC5" , 0x16700000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
|
|
{"POW_WS_PC6" , 0x16700000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
|
|
{"POW_WS_PC7" , 0x16700000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
|
|
{"POW_WS_PC8" , 0x16700000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
|
|
{"POW_WS_PC9" , 0x16700000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
|
|
{"POW_WS_PC10" , 0x16700000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
|
|
{"POW_WS_PC11" , 0x16700000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
|
|
{"POW_WS_PC12" , 0x16700000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
|
|
{"POW_WS_PC13" , 0x16700000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
|
|
{"POW_WS_PC14" , 0x16700000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
|
|
{"POW_WS_PC15" , 0x16700000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
|
|
{"RAD_MEM_DEBUG0" , 0x1180070001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
|
|
{"RAD_MEM_DEBUG1" , 0x1180070001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"RAD_MEM_DEBUG2" , 0x1180070001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
|
|
{"RAD_REG_BIST_RESULT" , 0x1180070000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
|
|
{"RAD_REG_CMD_BUF" , 0x1180070000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
|
|
{"RAD_REG_CTL" , 0x1180070000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
|
|
{"RAD_REG_DEBUG0" , 0x1180070000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
|
|
{"RAD_REG_DEBUG1" , 0x1180070000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
|
|
{"RAD_REG_DEBUG10" , 0x1180070000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
|
|
{"RAD_REG_DEBUG11" , 0x1180070000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
|
|
{"RAD_REG_DEBUG12" , 0x1180070000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
|
|
{"RAD_REG_DEBUG2" , 0x1180070000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
|
|
{"RAD_REG_DEBUG3" , 0x1180070000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
|
|
{"RAD_REG_DEBUG4" , 0x1180070000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
|
|
{"RAD_REG_DEBUG5" , 0x1180070000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
|
|
{"RAD_REG_DEBUG6" , 0x1180070000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"RAD_REG_DEBUG7" , 0x1180070000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
|
|
{"RAD_REG_DEBUG8" , 0x1180070000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
|
|
{"RAD_REG_DEBUG9" , 0x1180070000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
|
|
{"RAD_REG_ERROR" , 0x1180070000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
|
|
{"RAD_REG_INT_MASK" , 0x1180070000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
|
|
{"RAD_REG_POLYNOMIAL" , 0x1180070000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
|
|
{"RAD_REG_READ_IDX" , 0x1180070000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
|
|
{"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
|
|
{"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
|
|
{"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
|
|
{"SMI1_CLK" , 0x1180000001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
|
|
{"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
|
|
{"SMI1_CMD" , 0x1180000001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
|
|
{"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
|
|
{"SMI1_EN" , 0x1180000001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
|
|
{"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
|
|
{"SMI1_RD_DAT" , 0x1180000001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
|
|
{"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
|
|
{"SMI1_WR_DAT" , 0x1180000001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
|
|
{"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
|
|
{"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 790},
|
|
{"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
|
|
{"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
|
|
{"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
|
|
{"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
|
|
{"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 795},
|
|
{"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 796},
|
|
{"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 797},
|
|
{"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 798},
|
|
{"TRA_BIST_STATUS" , 0x11800A8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 799},
|
|
{"TRA_CTL" , 0x11800A8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 800},
|
|
{"TRA_CYCLES_SINCE" , 0x11800A8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 801},
|
|
{"TRA_CYCLES_SINCE1" , 0x11800A8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 802},
|
|
{"TRA_FILT_ADR_ADR" , 0x11800A8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 803},
|
|
{"TRA_FILT_ADR_MSK" , 0x11800A8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 804},
|
|
{"TRA_FILT_CMD" , 0x11800A8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 805},
|
|
{"TRA_FILT_DID" , 0x11800A8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 806},
|
|
{"TRA_FILT_SID" , 0x11800A8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 807},
|
|
{"TRA_INT_STATUS" , 0x11800A8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 808},
|
|
{"TRA_READ_DAT" , 0x11800A8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 809},
|
|
{"TRA_TRIG0_ADR_ADR" , 0x11800A8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 810},
|
|
{"TRA_TRIG0_ADR_MSK" , 0x11800A80000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 811},
|
|
{"TRA_TRIG0_CMD" , 0x11800A8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 812},
|
|
{"TRA_TRIG0_DID" , 0x11800A8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 813},
|
|
{"TRA_TRIG0_SID" , 0x11800A8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 814},
|
|
{"TRA_TRIG1_ADR_ADR" , 0x11800A80000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 815},
|
|
{"TRA_TRIG1_ADR_MSK" , 0x11800A80000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
|
|
{"TRA_TRIG1_CMD" , 0x11800A80000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 817},
|
|
{"TRA_TRIG1_DID" , 0x11800A80000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 818},
|
|
{"TRA_TRIG1_SID" , 0x11800A80000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 819},
|
|
{"USBC0_DAINT" , 0x16F0010000818ull, CVMX_CSR_DB_TYPE_NCB, 32, 820},
|
|
{"USBC0_DAINTMSK" , 0x16F001000081Cull, CVMX_CSR_DB_TYPE_NCB, 32, 821},
|
|
{"USBC0_DCFG" , 0x16F0010000800ull, CVMX_CSR_DB_TYPE_NCB, 32, 822},
|
|
{"USBC0_DCTL" , 0x16F0010000804ull, CVMX_CSR_DB_TYPE_NCB, 32, 823},
|
|
{"USBC0_DIEPCTL000" , 0x16F0010000900ull, CVMX_CSR_DB_TYPE_NCB, 32, 824},
|
|
{"USBC0_DIEPCTL001" , 0x16F0010000920ull, CVMX_CSR_DB_TYPE_NCB, 32, 824},
|
|
{"USBC0_DIEPCTL002" , 0x16F0010000940ull, CVMX_CSR_DB_TYPE_NCB, 32, 824},
|
|
{"USBC0_DIEPCTL003" , 0x16F0010000960ull, CVMX_CSR_DB_TYPE_NCB, 32, 824},
|
|
{"USBC0_DIEPCTL004" , 0x16F0010000980ull, CVMX_CSR_DB_TYPE_NCB, 32, 824},
|
|
{"USBC0_DIEPINT000" , 0x16F0010000908ull, CVMX_CSR_DB_TYPE_NCB, 32, 825},
|
|
{"USBC0_DIEPINT001" , 0x16F0010000928ull, CVMX_CSR_DB_TYPE_NCB, 32, 825},
|
|
{"USBC0_DIEPINT002" , 0x16F0010000948ull, CVMX_CSR_DB_TYPE_NCB, 32, 825},
|
|
{"USBC0_DIEPINT003" , 0x16F0010000968ull, CVMX_CSR_DB_TYPE_NCB, 32, 825},
|
|
{"USBC0_DIEPINT004" , 0x16F0010000988ull, CVMX_CSR_DB_TYPE_NCB, 32, 825},
|
|
{"USBC0_DIEPMSK" , 0x16F0010000810ull, CVMX_CSR_DB_TYPE_NCB, 32, 826},
|
|
{"USBC0_DIEPTSIZ000" , 0x16F0010000910ull, CVMX_CSR_DB_TYPE_NCB, 32, 827},
|
|
{"USBC0_DIEPTSIZ001" , 0x16F0010000930ull, CVMX_CSR_DB_TYPE_NCB, 32, 827},
|
|
{"USBC0_DIEPTSIZ002" , 0x16F0010000950ull, CVMX_CSR_DB_TYPE_NCB, 32, 827},
|
|
{"USBC0_DIEPTSIZ003" , 0x16F0010000970ull, CVMX_CSR_DB_TYPE_NCB, 32, 827},
|
|
{"USBC0_DIEPTSIZ004" , 0x16F0010000990ull, CVMX_CSR_DB_TYPE_NCB, 32, 827},
|
|
{"USBC0_DOEPCTL000" , 0x16F0010000B00ull, CVMX_CSR_DB_TYPE_NCB, 32, 828},
|
|
{"USBC0_DOEPCTL001" , 0x16F0010000B20ull, CVMX_CSR_DB_TYPE_NCB, 32, 828},
|
|
{"USBC0_DOEPCTL002" , 0x16F0010000B40ull, CVMX_CSR_DB_TYPE_NCB, 32, 828},
|
|
{"USBC0_DOEPCTL003" , 0x16F0010000B60ull, CVMX_CSR_DB_TYPE_NCB, 32, 828},
|
|
{"USBC0_DOEPCTL004" , 0x16F0010000B80ull, CVMX_CSR_DB_TYPE_NCB, 32, 828},
|
|
{"USBC0_DOEPINT000" , 0x16F0010000B08ull, CVMX_CSR_DB_TYPE_NCB, 32, 829},
|
|
{"USBC0_DOEPINT001" , 0x16F0010000B28ull, CVMX_CSR_DB_TYPE_NCB, 32, 829},
|
|
{"USBC0_DOEPINT002" , 0x16F0010000B48ull, CVMX_CSR_DB_TYPE_NCB, 32, 829},
|
|
{"USBC0_DOEPINT003" , 0x16F0010000B68ull, CVMX_CSR_DB_TYPE_NCB, 32, 829},
|
|
{"USBC0_DOEPINT004" , 0x16F0010000B88ull, CVMX_CSR_DB_TYPE_NCB, 32, 829},
|
|
{"USBC0_DOEPMSK" , 0x16F0010000814ull, CVMX_CSR_DB_TYPE_NCB, 32, 830},
|
|
{"USBC0_DOEPTSIZ000" , 0x16F0010000B10ull, CVMX_CSR_DB_TYPE_NCB, 32, 831},
|
|
{"USBC0_DOEPTSIZ001" , 0x16F0010000B30ull, CVMX_CSR_DB_TYPE_NCB, 32, 831},
|
|
{"USBC0_DOEPTSIZ002" , 0x16F0010000B50ull, CVMX_CSR_DB_TYPE_NCB, 32, 831},
|
|
{"USBC0_DOEPTSIZ003" , 0x16F0010000B70ull, CVMX_CSR_DB_TYPE_NCB, 32, 831},
|
|
{"USBC0_DOEPTSIZ004" , 0x16F0010000B90ull, CVMX_CSR_DB_TYPE_NCB, 32, 831},
|
|
{"USBC0_DPTXFSIZ001" , 0x16F0010000104ull, CVMX_CSR_DB_TYPE_NCB, 32, 832},
|
|
{"USBC0_DPTXFSIZ002" , 0x16F0010000108ull, CVMX_CSR_DB_TYPE_NCB, 32, 832},
|
|
{"USBC0_DPTXFSIZ003" , 0x16F001000010Cull, CVMX_CSR_DB_TYPE_NCB, 32, 832},
|
|
{"USBC0_DPTXFSIZ004" , 0x16F0010000110ull, CVMX_CSR_DB_TYPE_NCB, 32, 832},
|
|
{"USBC0_DSTS" , 0x16F0010000808ull, CVMX_CSR_DB_TYPE_NCB, 32, 833},
|
|
{"USBC0_DTKNQR1" , 0x16F0010000820ull, CVMX_CSR_DB_TYPE_NCB, 32, 834},
|
|
{"USBC0_DTKNQR2" , 0x16F0010000824ull, CVMX_CSR_DB_TYPE_NCB, 32, 835},
|
|
{"USBC0_DTKNQR3" , 0x16F0010000830ull, CVMX_CSR_DB_TYPE_NCB, 32, 836},
|
|
{"USBC0_DTKNQR4" , 0x16F0010000834ull, CVMX_CSR_DB_TYPE_NCB, 32, 837},
|
|
{"USBC0_GAHBCFG" , 0x16F0010000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 838},
|
|
{"USBC0_GHWCFG1" , 0x16F0010000044ull, CVMX_CSR_DB_TYPE_NCB, 32, 839},
|
|
{"USBC0_GHWCFG2" , 0x16F0010000048ull, CVMX_CSR_DB_TYPE_NCB, 32, 840},
|
|
{"USBC0_GHWCFG3" , 0x16F001000004Cull, CVMX_CSR_DB_TYPE_NCB, 32, 841},
|
|
{"USBC0_GHWCFG4" , 0x16F0010000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 842},
|
|
{"USBC0_GINTMSK" , 0x16F0010000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 843},
|
|
{"USBC0_GINTSTS" , 0x16F0010000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 844},
|
|
{"USBC0_GNPTXFSIZ" , 0x16F0010000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 845},
|
|
{"USBC0_GNPTXSTS" , 0x16F001000002Cull, CVMX_CSR_DB_TYPE_NCB, 32, 846},
|
|
{"USBC0_GOTGCTL" , 0x16F0010000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 847},
|
|
{"USBC0_GOTGINT" , 0x16F0010000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 848},
|
|
{"USBC0_GRSTCTL" , 0x16F0010000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 849},
|
|
{"USBC0_GRXFSIZ" , 0x16F0010000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 850},
|
|
{"USBC0_GRXSTSPD" , 0x16F0010040020ull, CVMX_CSR_DB_TYPE_NCB, 32, 851},
|
|
{"USBC0_GRXSTSPH" , 0x16F0010000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 852},
|
|
{"USBC0_GRXSTSRD" , 0x16F001004001Cull, CVMX_CSR_DB_TYPE_NCB, 32, 853},
|
|
{"USBC0_GRXSTSRH" , 0x16F001000001Cull, CVMX_CSR_DB_TYPE_NCB, 32, 854},
|
|
{"USBC0_GSNPSID" , 0x16F0010000040ull, CVMX_CSR_DB_TYPE_NCB, 32, 855},
|
|
{"USBC0_GUSBCFG" , 0x16F001000000Cull, CVMX_CSR_DB_TYPE_NCB, 32, 856},
|
|
{"USBC0_HAINT" , 0x16F0010000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 857},
|
|
{"USBC0_HAINTMSK" , 0x16F0010000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 858},
|
|
{"USBC0_HCCHAR000" , 0x16F0010000500ull, CVMX_CSR_DB_TYPE_NCB, 32, 859},
|
|
{"USBC0_HCCHAR001" , 0x16F0010000520ull, CVMX_CSR_DB_TYPE_NCB, 32, 859},
|
|
{"USBC0_HCCHAR002" , 0x16F0010000540ull, CVMX_CSR_DB_TYPE_NCB, 32, 859},
|
|
{"USBC0_HCCHAR003" , 0x16F0010000560ull, CVMX_CSR_DB_TYPE_NCB, 32, 859},
|
|
{"USBC0_HCCHAR004" , 0x16F0010000580ull, CVMX_CSR_DB_TYPE_NCB, 32, 859},
|
|
{"USBC0_HCCHAR005" , 0x16F00100005A0ull, CVMX_CSR_DB_TYPE_NCB, 32, 859},
|
|
{"USBC0_HCCHAR006" , 0x16F00100005C0ull, CVMX_CSR_DB_TYPE_NCB, 32, 859},
|
|
{"USBC0_HCCHAR007" , 0x16F00100005E0ull, CVMX_CSR_DB_TYPE_NCB, 32, 859},
|
|
{"USBC0_HCFG" , 0x16F0010000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 860},
|
|
{"USBC0_HCINT000" , 0x16F0010000508ull, CVMX_CSR_DB_TYPE_NCB, 32, 861},
|
|
{"USBC0_HCINT001" , 0x16F0010000528ull, CVMX_CSR_DB_TYPE_NCB, 32, 861},
|
|
{"USBC0_HCINT002" , 0x16F0010000548ull, CVMX_CSR_DB_TYPE_NCB, 32, 861},
|
|
{"USBC0_HCINT003" , 0x16F0010000568ull, CVMX_CSR_DB_TYPE_NCB, 32, 861},
|
|
{"USBC0_HCINT004" , 0x16F0010000588ull, CVMX_CSR_DB_TYPE_NCB, 32, 861},
|
|
{"USBC0_HCINT005" , 0x16F00100005A8ull, CVMX_CSR_DB_TYPE_NCB, 32, 861},
|
|
{"USBC0_HCINT006" , 0x16F00100005C8ull, CVMX_CSR_DB_TYPE_NCB, 32, 861},
|
|
{"USBC0_HCINT007" , 0x16F00100005E8ull, CVMX_CSR_DB_TYPE_NCB, 32, 861},
|
|
{"USBC0_HCINTMSK000" , 0x16F001000050Cull, CVMX_CSR_DB_TYPE_NCB, 32, 862},
|
|
{"USBC0_HCINTMSK001" , 0x16F001000052Cull, CVMX_CSR_DB_TYPE_NCB, 32, 862},
|
|
{"USBC0_HCINTMSK002" , 0x16F001000054Cull, CVMX_CSR_DB_TYPE_NCB, 32, 862},
|
|
{"USBC0_HCINTMSK003" , 0x16F001000056Cull, CVMX_CSR_DB_TYPE_NCB, 32, 862},
|
|
{"USBC0_HCINTMSK004" , 0x16F001000058Cull, CVMX_CSR_DB_TYPE_NCB, 32, 862},
|
|
{"USBC0_HCINTMSK005" , 0x16F00100005ACull, CVMX_CSR_DB_TYPE_NCB, 32, 862},
|
|
{"USBC0_HCINTMSK006" , 0x16F00100005CCull, CVMX_CSR_DB_TYPE_NCB, 32, 862},
|
|
{"USBC0_HCINTMSK007" , 0x16F00100005ECull, CVMX_CSR_DB_TYPE_NCB, 32, 862},
|
|
{"USBC0_HCSPLT000" , 0x16F0010000504ull, CVMX_CSR_DB_TYPE_NCB, 32, 863},
|
|
{"USBC0_HCSPLT001" , 0x16F0010000524ull, CVMX_CSR_DB_TYPE_NCB, 32, 863},
|
|
{"USBC0_HCSPLT002" , 0x16F0010000544ull, CVMX_CSR_DB_TYPE_NCB, 32, 863},
|
|
{"USBC0_HCSPLT003" , 0x16F0010000564ull, CVMX_CSR_DB_TYPE_NCB, 32, 863},
|
|
{"USBC0_HCSPLT004" , 0x16F0010000584ull, CVMX_CSR_DB_TYPE_NCB, 32, 863},
|
|
{"USBC0_HCSPLT005" , 0x16F00100005A4ull, CVMX_CSR_DB_TYPE_NCB, 32, 863},
|
|
{"USBC0_HCSPLT006" , 0x16F00100005C4ull, CVMX_CSR_DB_TYPE_NCB, 32, 863},
|
|
{"USBC0_HCSPLT007" , 0x16F00100005E4ull, CVMX_CSR_DB_TYPE_NCB, 32, 863},
|
|
{"USBC0_HCTSIZ000" , 0x16F0010000510ull, CVMX_CSR_DB_TYPE_NCB, 32, 864},
|
|
{"USBC0_HCTSIZ001" , 0x16F0010000530ull, CVMX_CSR_DB_TYPE_NCB, 32, 864},
|
|
{"USBC0_HCTSIZ002" , 0x16F0010000550ull, CVMX_CSR_DB_TYPE_NCB, 32, 864},
|
|
{"USBC0_HCTSIZ003" , 0x16F0010000570ull, CVMX_CSR_DB_TYPE_NCB, 32, 864},
|
|
{"USBC0_HCTSIZ004" , 0x16F0010000590ull, CVMX_CSR_DB_TYPE_NCB, 32, 864},
|
|
{"USBC0_HCTSIZ005" , 0x16F00100005B0ull, CVMX_CSR_DB_TYPE_NCB, 32, 864},
|
|
{"USBC0_HCTSIZ006" , 0x16F00100005D0ull, CVMX_CSR_DB_TYPE_NCB, 32, 864},
|
|
{"USBC0_HCTSIZ007" , 0x16F00100005F0ull, CVMX_CSR_DB_TYPE_NCB, 32, 864},
|
|
{"USBC0_HFIR" , 0x16F0010000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 865},
|
|
{"USBC0_HFNUM" , 0x16F0010000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 866},
|
|
{"USBC0_HPRT" , 0x16F0010000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 867},
|
|
{"USBC0_HPTXFSIZ" , 0x16F0010000100ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
|
|
{"USBC0_HPTXSTS" , 0x16F0010000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 869},
|
|
{"USBC0_NPTXDFIFO000" , 0x16F0010001000ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
|
|
{"USBC0_NPTXDFIFO001" , 0x16F0010002000ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
|
|
{"USBC0_NPTXDFIFO002" , 0x16F0010003000ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
|
|
{"USBC0_NPTXDFIFO003" , 0x16F0010004000ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
|
|
{"USBC0_NPTXDFIFO004" , 0x16F0010005000ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
|
|
{"USBC0_NPTXDFIFO005" , 0x16F0010006000ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
|
|
{"USBC0_NPTXDFIFO006" , 0x16F0010007000ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
|
|
{"USBC0_NPTXDFIFO007" , 0x16F0010008000ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
|
|
{"USBC0_PCGCCTL" , 0x16F0010000E00ull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
|
|
{"USBN0_BIST_STATUS" , 0x11800680007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
|
|
{"USBN0_CLK_CTL" , 0x1180068000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 873},
|
|
{"USBN0_CTL_STATUS" , 0x16F0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 874},
|
|
{"USBN0_DMA0_INB_CHN0" , 0x16F0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 875},
|
|
{"USBN0_DMA0_INB_CHN1" , 0x16F0000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 876},
|
|
{"USBN0_DMA0_INB_CHN2" , 0x16F0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 877},
|
|
{"USBN0_DMA0_INB_CHN3" , 0x16F0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 878},
|
|
{"USBN0_DMA0_INB_CHN4" , 0x16F0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 879},
|
|
{"USBN0_DMA0_INB_CHN5" , 0x16F0000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 880},
|
|
{"USBN0_DMA0_INB_CHN6" , 0x16F0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 881},
|
|
{"USBN0_DMA0_INB_CHN7" , 0x16F0000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 882},
|
|
{"USBN0_DMA0_OUTB_CHN0" , 0x16F0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 883},
|
|
{"USBN0_DMA0_OUTB_CHN1" , 0x16F0000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 884},
|
|
{"USBN0_DMA0_OUTB_CHN2" , 0x16F0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 885},
|
|
{"USBN0_DMA0_OUTB_CHN3" , 0x16F0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 886},
|
|
{"USBN0_DMA0_OUTB_CHN4" , 0x16F0000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 887},
|
|
{"USBN0_DMA0_OUTB_CHN5" , 0x16F0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 888},
|
|
{"USBN0_DMA0_OUTB_CHN6" , 0x16F0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 889},
|
|
{"USBN0_DMA0_OUTB_CHN7" , 0x16F0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 890},
|
|
{"USBN0_DMA_TEST" , 0x16F0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 891},
|
|
{"USBN0_INT_ENB" , 0x1180068000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 892},
|
|
{"USBN0_INT_SUM" , 0x1180068000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 893},
|
|
{"USBN0_USBP_CTL_STATUS" , 0x1180068000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 894},
|
|
{"ZIP_CMD_BIST_RESULT" , 0x1180038000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 895},
|
|
{"ZIP_CMD_BUF" , 0x1180038000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 896},
|
|
{"ZIP_CMD_CTL" , 0x1180038000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
|
|
{"ZIP_CONSTANTS" , 0x11800380000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 898},
|
|
{"ZIP_DEBUG0" , 0x1180038000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 899},
|
|
{"ZIP_ERROR" , 0x1180038000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 900},
|
|
{"ZIP_INT_MASK" , 0x1180038000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 901},
|
|
{NULL,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
|
|
/* name , bit, width, csr, type, rst un, typ un, reset, typical */
|
|
{"RESERVED_0_1" , 0, 2, 0, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OUT_OVR" , 2, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_21" , 3, 19, 0, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LOSTSTAT" , 22, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_25" , 23, 3, 0, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STATOVR" , 26, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_31" , 27, 5, 0, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OVRFLW" , 32, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXPOP" , 33, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXPSH" , 34, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_35_63" , 35, 29, 0, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 10, 1, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 1, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 5, 2, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 2, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL" , 8, 5, 2, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_13_15" , 13, 3, 2, "RAZ", 1, 1, 0, 0},
|
|
{"BYP_EN" , 16, 1, 2, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 2, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 3, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 1, 1, 3, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 3, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 4, "R/W", 0, 1, 0ull, 0},
|
|
{"SPEED" , 1, 1, 4, "RO", 0, 0, 0ull, 0ull},
|
|
{"DUPLEX" , 2, 1, 4, "R/W", 0, 1, 1ull, 0},
|
|
{"SLOTTIME" , 3, 1, 4, "RO", 0, 0, 0ull, 0ull},
|
|
{"RX_EN" , 4, 1, 4, "R/W", 0, 1, 0ull, 0},
|
|
{"TX_EN" , 5, 1, 4, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 4, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 64, 5, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 6, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 7, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 8, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 9, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 10, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 0, 8, 11, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 11, "RAZ", 1, 1, 0, 0},
|
|
{"BCST" , 0, 1, 12, "R/W", 0, 1, 1ull, 0},
|
|
{"MCST" , 1, 2, 12, "R/W", 0, 1, 0ull, 0},
|
|
{"CAM_MODE" , 3, 1, 12, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 12, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 5, 13, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_5_63" , 5, 59, 13, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_1" , 1, 1, 14, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 2, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"JABBER" , 3, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCSERR" , 4, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"ALNERR" , 5, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"LENERR" , 6, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RCVERR" , 7, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SKPERR" , 8, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_9_63" , 9, 55, 14, "RAZ", 1, 1, 0, 0},
|
|
{"PRE_CHK" , 0, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PRE_STRP" , 1, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_DRP" , 2, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_BCK" , 3, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_MCST" , 4, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_SMAC" , 5, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRE_FREE" , 6, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"VLAN_LEN" , 7, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PAD_LEN" , 8, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRE_ALIGN" , 9, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_10_63" , 10, 54, 15, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 16, 16, "R/W", 0, 0, 1536ull, 1536ull},
|
|
{"RESERVED_16_63" , 16, 48, 16, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 16, 17, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_16_63" , 16, 48, 17, "RAZ", 1, 1, 0, 0},
|
|
{"IFG" , 0, 4, 18, "R/W", 0, 0, 12ull, 12ull},
|
|
{"RESERVED_4_63" , 4, 60, 18, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 19, "RAZ", 1, 1, 0, 0},
|
|
{"MAXERR" , 2, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"JABBER" , 3, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ALNERR" , 5, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 6, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RCVERR" , 7, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 19, "RAZ", 1, 1, 0, 0},
|
|
{"OVRERR" , 10, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_18" , 16, 3, 19, "RAZ", 1, 1, 0, 0},
|
|
{"PAUSE_DRP" , 19, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 19, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 20, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 2, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"JABBER" , 3, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ALNERR" , 5, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 6, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RCVERR" , 7, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 20, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OVRERR" , 10, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_18" , 16, 3, 20, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PAUSE_DRP" , 19, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 20, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 21, "R/W", 0, 0, 10240ull, 10240ull},
|
|
{"RESERVED_16_63" , 16, 48, 21, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 16, 22, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 22, "RAZ", 1, 1, 0, 0},
|
|
{"RD_CLR" , 0, 1, 23, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 23, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 24, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 24, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 25, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 25, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 26, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 26, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 27, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 27, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 28, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 28, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 29, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 29, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 30, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 30, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 31, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 31, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 32, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 32, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 7, 33, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 33, "RAZ", 1, 1, 0, 0},
|
|
{"FCSSEL" , 8, 1, 33, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 33, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 34, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_6_63" , 6, 58, 34, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 35, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_6_63" , 6, 58, 35, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 9, 36, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_9_63" , 9, 55, 36, "RAZ", 1, 1, 0, 0},
|
|
{"COMMIT" , 0, 1, 37, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_15" , 1, 15, 37, "RAZ", 1, 1, 0, 0},
|
|
{"DROP" , 16, 1, 37, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 37, "RAZ", 1, 1, 0, 0},
|
|
{"RX" , 0, 1, 38, "RC", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_3" , 1, 3, 38, "RAZ", 1, 1, 0, 0},
|
|
{"TX" , 4, 1, 38, "RC", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 38, "RAZ", 1, 1, 0, 0},
|
|
{"SMAC" , 0, 48, 39, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 39, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 40, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP" , 16, 1, 40, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 40, "RAZ", 1, 1, 0, 0},
|
|
{"PREAMBLE" , 0, 1, 41, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PAD" , 1, 1, 41, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCS" , 2, 1, 41, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FORCE_FCS" , 3, 1, 41, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 41, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL_EN" , 0, 1, 42, "R/W", 0, 0, 1ull, 1ull},
|
|
{"XSDEF_EN" , 1, 1, 42, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 42, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_SIZE" , 0, 8, 43, "R/W", 0, 0, 59ull, 59ull},
|
|
{"RESERVED_8_63" , 8, 56, 43, "RAZ", 1, 1, 0, 0},
|
|
{"INTERVAL" , 0, 16, 44, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 44, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 45, "R/W", 0, 1, 96ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 45, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 46, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_16_63" , 16, 48, 46, "RAZ", 1, 1, 0, 0},
|
|
{"SEND" , 0, 1, 47, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 47, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 48, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 48, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL" , 0, 32, 49, "RC/W", 0, 1, 0ull, 0},
|
|
{"XSDEF" , 32, 32, 49, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCOL" , 0, 32, 50, "RC/W", 0, 1, 0ull, 0},
|
|
{"SCOL" , 32, 32, 50, "RC/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 51, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 51, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 52, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 52, "RAZ", 1, 1, 0, 0},
|
|
{"HIST0" , 0, 32, 53, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST1" , 32, 32, 53, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST2" , 0, 32, 54, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST3" , 32, 32, 54, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST4" , 0, 32, 55, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST5" , 32, 32, 55, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST6" , 0, 32, 56, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST7" , 32, 32, 56, "RC/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 0, 32, 57, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 32, 32, 57, "RC/W", 0, 1, 0ull, 0},
|
|
{"CTL" , 0, 32, 58, "RC/W", 0, 1, 0ull, 0},
|
|
{"UNDFLW" , 32, 32, 58, "RC/W", 0, 1, 0ull, 0},
|
|
{"RD_CLR" , 0, 1, 59, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 59, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 6, 60, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_6_63" , 6, 58, 60, "RAZ", 1, 1, 0, 0},
|
|
{"BP" , 0, 1, 61, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 61, "RAZ", 1, 1, 0, 0},
|
|
{"LIMIT" , 0, 5, 62, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_5_63" , 5, 59, 62, "RAZ", 1, 1, 0, 0},
|
|
{"IFG1" , 0, 4, 63, "R/W", 0, 1, 8ull, 0},
|
|
{"IFG2" , 4, 4, 63, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 63, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 64, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 1, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_7" , 3, 5, 64, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 1, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 64, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 1, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 64, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LATE_COL" , 16, 1, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 64, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PKO_NXA" , 0, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 65, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_7" , 3, 5, 65, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 65, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 65, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LATE_COL" , 16, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 65, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"JAM" , 0, 8, 66, "R/W", 0, 1, 238ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 66, "RAZ", 1, 1, 0, 0},
|
|
{"LFSR" , 0, 16, 67, "R/W", 0, 1, 65535ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 67, "RAZ", 1, 1, 0, 0},
|
|
{"IGN_FULL" , 0, 1, 68, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_3" , 1, 3, 68, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"BP" , 4, 1, 68, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_7" , 5, 3, 68, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EN" , 8, 1, 68, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 68, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DMAC" , 0, 48, 69, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
|
|
{"RESERVED_48_63" , 48, 16, 69, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 70, "R/W", 0, 0, 34824ull, 34824ull},
|
|
{"RESERVED_16_63" , 16, 48, 70, "RAZ", 1, 1, 0, 0},
|
|
{"BIST" , 0, 4, 71, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 71, "RAZ", 1, 1, 0, 0},
|
|
{"DINT" , 0, 12, 72, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 72, "RAZ", 1, 1, 0, 0},
|
|
{"FUSE" , 0, 12, 73, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_12_63" , 12, 52, 73, "RAZ", 1, 1, 0, 0},
|
|
{"GSTOP" , 0, 1, 74, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 74, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 75, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_57_58" , 57, 2, 75, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TWSI2" , 59, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POWIQ" , 60, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPDPPTHR" , 61, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MII" , 62, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BOOTDMA" , 63, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WDOG" , 0, 12, 76, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 76, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 77, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_57_58" , 57, 2, 77, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TWSI2" , 59, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POWIQ" , 60, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPDPPTHR" , 61, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MII" , 62, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BOOTDMA" , 63, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WDOG" , 0, 12, 78, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 78, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"WDOG_SUM" , 44, 1, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"TWSI" , 45, 1, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 79, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 79, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 79, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 79, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_57_58" , 57, 2, 79, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TWSI2" , 59, 1, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"POWIQ" , 60, 1, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPDPPTHR" , 61, 1, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"MII" , 62, 1, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"BOOTDMA" , 63, 1, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"WORKQ" , 0, 16, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"WDOG_SUM" , 44, 1, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"TWSI" , 45, 1, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 80, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 80, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 80, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 80, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_57_58" , 57, 2, 80, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TWSI2" , 59, 1, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"POWIQ" , 60, 1, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPDPPTHR" , 61, 1, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"MII" , 62, 1, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"BOOTDMA" , 63, 1, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"WDOG" , 0, 12, 81, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 81, "RAZ", 1, 1, 0, 0},
|
|
{"BITS" , 0, 32, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 82, "RAZ", 1, 1, 0, 0},
|
|
{"BITS" , 0, 32, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 83, "RAZ", 1, 1, 0, 0},
|
|
{"NMI" , 0, 12, 84, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 84, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 0, 2, 85, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 85, "RAZ", 1, 1, 0, 0},
|
|
{"PPDBG" , 0, 12, 86, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 86, "RAZ", 1, 1, 0, 0},
|
|
{"POKE" , 0, 64, 87, "RAZ", 1, 1, 0, 0},
|
|
{"RST0" , 0, 1, 88, "R/W", 1, 1, 0, 0},
|
|
{"RST" , 1, 11, 88, "R/W", 0, 0, 32767ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 88, "RAZ", 1, 1, 0, 0},
|
|
{"QLM_DCOK" , 0, 4, 89, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 89, "RAZ", 1, 1, 0, 0},
|
|
{"BYPASS" , 0, 4, 90, "R/W", 0, 1, 0ull, 0},
|
|
{"MUX_SEL" , 4, 2, 90, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_7" , 6, 2, 90, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_DIV" , 8, 3, 90, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_11_63" , 11, 53, 90, "RAZ", 1, 1, 0, 0},
|
|
{"SHFT_REG" , 0, 32, 91, "R/W", 0, 1, 0ull, 0},
|
|
{"SHFT_CNT" , 32, 5, 91, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_37_60" , 37, 24, 91, "RAZ", 1, 1, 0, 0},
|
|
{"UPDATE" , 61, 1, 91, "R/W", 0, 1, 0ull, 0},
|
|
{"SHIFT" , 62, 1, 91, "R/W", 0, 1, 0ull, 0},
|
|
{"CAPTURE" , 63, 1, 91, "R/W", 0, 1, 0ull, 0},
|
|
{"SOFT_BIST" , 0, 1, 92, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 92, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_PRST" , 0, 1, 93, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 93, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_PRST" , 0, 1, 94, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 94, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_RST" , 0, 1, 95, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 95, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 36, 96, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ONE_SHOT" , 36, 1, 96, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 96, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 0, 2, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STATE" , 2, 2, 97, "RO", 0, 0, 0ull, 0ull},
|
|
{"LEN" , 4, 16, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 20, 24, 97, "RO", 0, 0, 0ull, 0ull},
|
|
{"DSTOP" , 44, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GSTOPEN" , 45, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_46_63" , 46, 18, 97, "RAZ", 1, 1, 0, 0},
|
|
{"FDR" , 0, 1, 98, "RO", 0, 0, 0ull, 0ull},
|
|
{"FFR" , 1, 1, 98, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPF1" , 2, 1, 98, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPF0" , 3, 1, 98, "RO", 0, 0, 0ull, 0ull},
|
|
{"FRD" , 4, 1, 98, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 98, "RAZ", 1, 1, 0, 0},
|
|
{"MEM0_ERR" , 0, 7, 99, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM1_ERR" , 7, 7, 99, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 14, 1, 99, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USE_STT" , 15, 1, 99, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USE_LDT" , 16, 1, 99, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 17, 1, 99, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 99, "RAZ", 1, 1, 0, 0},
|
|
{"FPF_RD" , 0, 11, 100, "R/W", 0, 0, 64ull, 0ull},
|
|
{"FPF_WR" , 11, 11, 100, "R/W", 0, 0, 196ull, 0ull},
|
|
{"RESERVED_22_63" , 22, 42, 100, "RAZ", 1, 1, 0, 0},
|
|
{"FPF_SIZ" , 0, 11, 101, "R/W", 0, 0, 256ull, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 101, "RAZ", 1, 1, 0, 0},
|
|
{"FPF_RD" , 0, 12, 102, "R/W", 0, 0, 64ull, 0ull},
|
|
{"FPF_WR" , 12, 12, 102, "R/W", 0, 0, 196ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 102, "RAZ", 1, 1, 0, 0},
|
|
{"FPF_SIZ" , 0, 12, 103, "R/W", 0, 0, 256ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 103, "RAZ", 1, 1, 0, 0},
|
|
{"FED0_SBE" , 0, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED0_DBE" , 1, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED1_SBE" , 2, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED1_DBE" , 3, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_UND" , 4, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_COFF" , 5, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_PERR" , 6, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_UND" , 7, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_COFF" , 8, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_PERR" , 9, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_UND" , 10, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_COFF" , 11, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_PERR" , 12, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_UND" , 13, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_COFF" , 14, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_PERR" , 15, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_UND" , 16, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_COFF" , 17, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_PERR" , 18, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_UND" , 19, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_COFF" , 20, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_PERR" , 21, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_UND" , 22, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_COFF" , 23, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_PERR" , 24, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_UND" , 25, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_COFF" , 26, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_PERR" , 27, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 104, "RAZ", 1, 1, 0, 0},
|
|
{"FED0_SBE" , 0, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED0_DBE" , 1, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED1_SBE" , 2, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED1_DBE" , 3, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_UND" , 4, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_COFF" , 5, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_PERR" , 6, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_UND" , 7, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_COFF" , 8, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_PERR" , 9, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_UND" , 10, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_COFF" , 11, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_PERR" , 12, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_UND" , 13, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_COFF" , 14, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_PERR" , 15, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_UND" , 16, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_COFF" , 17, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_PERR" , 18, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_UND" , 19, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_COFF" , 20, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_PERR" , 21, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_UND" , 22, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_COFF" , 23, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_PERR" , 24, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_UND" , 25, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_COFF" , 26, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_PERR" , 27, 1, 105, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 105, "RAZ", 1, 1, 0, 0},
|
|
{"QUE_SIZ" , 0, 29, 106, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 106, "RAZ", 1, 1, 0, 0},
|
|
{"PG_NUM" , 0, 25, 107, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 107, "RAZ", 1, 1, 0, 0},
|
|
{"ACT_INDX" , 0, 26, 108, "RO", 0, 1, 0ull, 0},
|
|
{"ACT_QUE" , 26, 3, 108, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 108, "RAZ", 0, 0, 0ull, 7ull},
|
|
{"EXP_INDX" , 0, 26, 109, "RO", 0, 1, 0ull, 0},
|
|
{"EXP_QUE" , 26, 3, 109, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 109, "RAZ", 0, 0, 0ull, 7ull},
|
|
{"CTL" , 0, 16, 110, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 110, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 32, 111, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 111, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 112, "RAZ", 1, 1, 0, 0},
|
|
{"OUT_OVR" , 2, 4, 112, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_21" , 6, 16, 112, "RAZ", 1, 1, 0, 0},
|
|
{"LOSTSTAT" , 22, 4, 112, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"STATOVR" , 26, 1, 112, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INB_NXA" , 27, 4, 112, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 112, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 16, 113, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 113, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_EN" , 0, 1, 114, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 114, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 1, 115, "RO", 0, 1, 0ull, 0},
|
|
{"EN" , 1, 1, 115, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_3" , 2, 2, 115, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 4, 2, 115, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_7" , 6, 2, 115, "RAZ", 1, 1, 0, 0},
|
|
{"SPEED" , 8, 2, 115, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_10_63" , 10, 54, 115, "RAZ", 1, 1, 0, 0},
|
|
{"PRT" , 0, 6, 116, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 116, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 117, "R/W", 0, 1, 0ull, 0},
|
|
{"SPEED" , 1, 1, 117, "R/W", 0, 1, 1ull, 0},
|
|
{"DUPLEX" , 2, 1, 117, "R/W", 0, 1, 1ull, 0},
|
|
{"SLOTTIME" , 3, 1, 117, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_4_7" , 4, 4, 117, "RAZ", 1, 1, 0, 0},
|
|
{"SPEED_MSB" , 8, 1, 117, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_9_11" , 9, 3, 117, "RAZ", 1, 1, 0, 0},
|
|
{"RX_IDLE" , 12, 1, 117, "RO", 0, 1, 1ull, 0},
|
|
{"TX_IDLE" , 13, 1, 117, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_14_63" , 14, 50, 117, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 64, 118, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 119, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 120, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 121, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 122, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 123, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 0, 8, 124, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 124, "RAZ", 1, 1, 0, 0},
|
|
{"BCST" , 0, 1, 125, "R/W", 0, 1, 1ull, 0},
|
|
{"MCST" , 1, 2, 125, "R/W", 0, 1, 0ull, 0},
|
|
{"CAM_MODE" , 3, 1, 125, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 125, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 5, 126, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_5_63" , 5, 59, 126, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 127, "RAZ", 1, 1, 0, 0},
|
|
{"CAREXT" , 1, 1, 127, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_2" , 2, 1, 127, "RAZ", 1, 1, 0, 0},
|
|
{"JABBER" , 3, 1, 127, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCSERR" , 4, 1, 127, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_5_6" , 5, 2, 127, "RAZ", 1, 1, 0, 0},
|
|
{"RCVERR" , 7, 1, 127, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SKPERR" , 8, 1, 127, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_9_63" , 9, 55, 127, "RAZ", 1, 1, 0, 0},
|
|
{"PRE_CHK" , 0, 1, 128, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PRE_STRP" , 1, 1, 128, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_DRP" , 2, 1, 128, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_BCK" , 3, 1, 128, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_MCST" , 4, 1, 128, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_SMAC" , 5, 1, 128, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRE_FREE" , 6, 1, 128, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_7_8" , 7, 2, 128, "RAZ", 1, 1, 0, 0},
|
|
{"PRE_ALIGN" , 9, 1, 128, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 128, "RAZ", 1, 1, 0, 0},
|
|
{"IFG" , 0, 4, 129, "R/W", 0, 0, 8ull, 8ull},
|
|
{"RESERVED_4_63" , 4, 60, 129, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 130, "RAZ", 1, 1, 0, 0},
|
|
{"CAREXT" , 1, 1, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 130, "RAZ", 1, 1, 0, 0},
|
|
{"JABBER" , 3, 1, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_6" , 5, 2, 130, "RAZ", 1, 1, 0, 0},
|
|
{"RCVERR" , 7, 1, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 130, "RAZ", 1, 1, 0, 0},
|
|
{"OVRERR" , 10, 1, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_18" , 16, 3, 130, "RAZ", 1, 1, 0, 0},
|
|
{"PAUSE_DRP" , 19, 1, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LOC_FAULT" , 20, 1, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"REM_FAULT" , 21, 1, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAD_SEQ" , 22, 1, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAD_TERM" , 23, 1, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UNSOP" , 24, 1, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UNEOP" , 25, 1, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UNDAT" , 26, 1, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_63" , 27, 37, 130, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 131, "RAZ", 1, 1, 0, 0},
|
|
{"CAREXT" , 1, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 131, "RAZ", 1, 1, 0, 0},
|
|
{"JABBER" , 3, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_6" , 5, 2, 131, "RAZ", 1, 1, 0, 0},
|
|
{"RCVERR" , 7, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 131, "RAZ", 1, 1, 0, 0},
|
|
{"OVRERR" , 10, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_18" , 16, 3, 131, "RAZ", 1, 1, 0, 0},
|
|
{"PAUSE_DRP" , 19, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LOC_FAULT" , 20, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"REM_FAULT" , 21, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BAD_SEQ" , 22, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BAD_TERM" , 23, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UNSOP" , 24, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UNEOP" , 25, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UNDAT" , 26, 1, 131, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_63" , 27, 37, 131, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 132, "R/W", 0, 0, 10240ull, 10240ull},
|
|
{"RESERVED_16_63" , 16, 48, 132, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 16, 133, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 133, "RAZ", 1, 1, 0, 0},
|
|
{"RD_CLR" , 0, 1, 134, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 134, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 135, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 135, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 136, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 136, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 137, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 137, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 138, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 138, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 139, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 139, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 140, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 140, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 141, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 141, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 142, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 142, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 143, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 143, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 7, 144, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 144, "RAZ", 1, 1, 0, 0},
|
|
{"FCSSEL" , 8, 1, 144, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 144, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 145, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_6_63" , 6, 58, 145, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 146, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_6_63" , 6, 58, 146, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 9, 147, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_9_63" , 9, 55, 147, "RAZ", 1, 1, 0, 0},
|
|
{"COMMIT" , 0, 4, 148, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_15" , 4, 12, 148, "RAZ", 1, 1, 0, 0},
|
|
{"DROP" , 16, 4, 148, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 148, "RAZ", 1, 1, 0, 0},
|
|
{"PRTS" , 0, 3, 149, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_3_63" , 3, 61, 149, "RAZ", 1, 1, 0, 0},
|
|
{"LANE_RXD" , 0, 32, 150, "RO", 0, 1, 0ull, 0},
|
|
{"LANE_RXC" , 32, 4, 150, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 36, 3, 150, "RO", 0, 1, 0ull, 0},
|
|
{"VAL" , 39, 1, 150, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_40_63" , 40, 24, 150, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 2, 151, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 151, "RAZ", 1, 1, 0, 0},
|
|
{"SMAC" , 0, 48, 152, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 152, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 153, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP" , 16, 1, 153, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 153, "RAZ", 1, 1, 0, 0},
|
|
{"PREAMBLE" , 0, 1, 154, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PAD" , 1, 1, 154, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCS" , 2, 1, 154, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FORCE_FCS" , 3, 1, 154, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 154, "RAZ", 1, 1, 0, 0},
|
|
{"BURST" , 0, 16, 155, "R/W", 0, 0, 8192ull, 8192ull},
|
|
{"RESERVED_16_63" , 16, 48, 155, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL_EN" , 0, 1, 156, "R/W", 0, 0, 1ull, 1ull},
|
|
{"XSDEF_EN" , 1, 1, 156, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 156, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_SIZE" , 0, 8, 157, "R/W", 0, 0, 59ull, 59ull},
|
|
{"RESERVED_8_63" , 8, 56, 157, "RAZ", 1, 1, 0, 0},
|
|
{"INTERVAL" , 0, 16, 158, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 158, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 159, "R/W", 0, 1, 96ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 159, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 160, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_16_63" , 16, 48, 160, "RAZ", 1, 1, 0, 0},
|
|
{"SEND" , 0, 1, 161, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 161, "RAZ", 1, 1, 0, 0},
|
|
{"ALIGN" , 0, 1, 162, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 162, "RAZ", 1, 1, 0, 0},
|
|
{"SLOT" , 0, 10, 163, "R/W", 0, 0, 512ull, 512ull},
|
|
{"RESERVED_10_63" , 10, 54, 163, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 164, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 164, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL" , 0, 32, 165, "RC/W", 0, 1, 0ull, 0},
|
|
{"XSDEF" , 32, 32, 165, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCOL" , 0, 32, 166, "RC/W", 0, 1, 0ull, 0},
|
|
{"SCOL" , 32, 32, 166, "RC/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 167, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 167, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 168, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 168, "RAZ", 1, 1, 0, 0},
|
|
{"HIST0" , 0, 32, 169, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST1" , 32, 32, 169, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST2" , 0, 32, 170, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST3" , 32, 32, 170, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST4" , 0, 32, 171, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST5" , 32, 32, 171, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST6" , 0, 32, 172, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST7" , 32, 32, 172, "RC/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 0, 32, 173, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 32, 32, 173, "RC/W", 0, 1, 0ull, 0},
|
|
{"CTL" , 0, 32, 174, "RC/W", 0, 1, 0ull, 0},
|
|
{"UNDFLW" , 32, 32, 174, "RC/W", 0, 1, 0ull, 0},
|
|
{"RD_CLR" , 0, 1, 175, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 175, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 9, 176, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_9_63" , 9, 55, 176, "RAZ", 1, 1, 0, 0},
|
|
{"BP" , 0, 4, 177, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 177, "RAZ", 1, 1, 0, 0},
|
|
{"LIMIT" , 0, 5, 178, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_5_63" , 5, 59, 178, "RAZ", 1, 1, 0, 0},
|
|
{"CORRUPT" , 0, 4, 179, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_4_63" , 4, 60, 179, "RAZ", 1, 1, 0, 0},
|
|
{"IFG1" , 0, 4, 180, "R/W", 0, 1, 8ull, 0},
|
|
{"IFG2" , 4, 4, 180, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 180, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 181, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 181, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 4, 181, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 181, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 4, 181, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 4, 181, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LATE_COL" , 16, 4, 181, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 181, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 182, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 182, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 4, 182, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 182, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 4, 182, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 4, 182, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LATE_COL" , 16, 4, 182, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 182, "RAZ", 1, 1, 0, 0},
|
|
{"JAM" , 0, 8, 183, "R/W", 0, 1, 238ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 183, "RAZ", 1, 1, 0, 0},
|
|
{"LFSR" , 0, 16, 184, "R/W", 0, 1, 65535ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 184, "RAZ", 1, 1, 0, 0},
|
|
{"IGN_FULL" , 0, 4, 185, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP" , 4, 4, 185, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EN" , 8, 4, 185, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_31" , 12, 20, 185, "RAZ", 1, 1, 0, 0},
|
|
{"TX_PRT_BP" , 32, 16, 185, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 185, "RAZ", 1, 1, 0, 0},
|
|
{"DMAC" , 0, 48, 186, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
|
|
{"RESERVED_48_63" , 48, 16, 186, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 187, "R/W", 0, 0, 34824ull, 34824ull},
|
|
{"RESERVED_16_63" , 16, 48, 187, "RAZ", 1, 1, 0, 0},
|
|
{"PRTS" , 0, 5, 188, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 188, "RAZ", 1, 1, 0, 0},
|
|
{"DIC_EN" , 0, 1, 189, "R/W", 0, 0, 0ull, 1ull},
|
|
{"UNI_EN" , 1, 1, 189, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_3" , 2, 2, 189, "RAZ", 1, 1, 0, 0},
|
|
{"LS" , 4, 2, 189, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LS_BYP" , 6, 1, 189, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 189, "RAZ", 1, 1, 0, 0},
|
|
{"HG_EN" , 8, 1, 189, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HG_PAUSE_HGI" , 9, 2, 189, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_11_63" , 11, 53, 189, "RAZ", 1, 1, 0, 0},
|
|
{"THRESH" , 0, 4, 190, "R/W", 0, 0, 8ull, 8ull},
|
|
{"EN" , 4, 1, 190, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 190, "RAZ", 1, 1, 0, 0},
|
|
{"TX_OE" , 0, 1, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RX_XOR" , 1, 1, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_EN" , 2, 1, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_TYPE" , 3, 1, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_CNT" , 4, 4, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_SEL" , 8, 4, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLK_SEL" , 12, 2, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLK_GEN" , 14, 1, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 191, "RAZ", 1, 1, 0, 0},
|
|
{"N" , 0, 32, 192, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 192, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 193, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 193, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 194, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 194, "RAZ", 1, 1, 0, 0},
|
|
{"CLR" , 0, 16, 195, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 195, "RAZ", 1, 1, 0, 0},
|
|
{"SET" , 0, 16, 196, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 196, "RAZ", 1, 1, 0, 0},
|
|
{"ICD" , 0, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBD" , 1, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRP1" , 2, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRP0" , 3, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRN1" , 4, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRN0" , 5, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBRQ1" , 6, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBRQ0" , 7, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNRT" , 8, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBR1" , 9, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBR0" , 10, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBDR1" , 11, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBDR0" , 12, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNR0" , 13, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNR1" , 14, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICR1" , 15, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICR0" , 16, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNRCB" , 17, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 197, "RAZ", 1, 1, 0, 0},
|
|
{"FAU_END" , 0, 1, 198, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB_ENB" , 1, 1, 198, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PKO_ENB" , 2, 1, 198, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INB_MAT" , 3, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OUTB_MAT" , 4, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 198, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 199, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 199, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 199, "RAZ", 1, 1, 0, 0},
|
|
{"TOUT_VAL" , 0, 12, 200, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TOUT_ENB" , 12, 1, 200, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 200, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 201, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 201, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 201, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 8, 202, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 8, 9, 202, "R/W", 0, 1, 0ull, 0},
|
|
{"OPC" , 17, 4, 202, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 21, 8, 202, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 202, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 8, 203, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 8, 9, 203, "R/W", 0, 1, 0ull, 0},
|
|
{"OPC" , 17, 4, 203, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 21, 8, 203, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 203, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 204, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 205, "R/W", 0, 1, 0ull, 0},
|
|
{"NP_SOP" , 0, 1, 206, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NP_EOP" , 1, 1, 206, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_SOP" , 2, 1, 206, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_EOP" , 3, 1, 206, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NP_DAT" , 4, 1, 206, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_DAT" , 5, 1, 206, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 206, "RAZ", 1, 1, 0, 0},
|
|
{"NP_SOP" , 0, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NP_EOP" , 1, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_SOP" , 2, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_EOP" , 3, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NP_DAT" , 4, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_DAT" , 5, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 207, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 208, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 208, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 208, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 209, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 209, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 209, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 210, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 210, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 210, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 9, 211, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 9, 8, 211, "R/W", 0, 1, 0ull, 0},
|
|
{"EOT" , 17, 1, 211, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 18, 8, 211, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_26_63" , 26, 38, 211, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 9, 212, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 9, 8, 212, "R/W", 0, 1, 0ull, 0},
|
|
{"EOT" , 17, 1, 212, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 18, 8, 212, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_26_63" , 26, 38, 212, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 213, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 214, "R/W", 0, 1, 0ull, 0},
|
|
{"CNT_VAL" , 0, 15, 215, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 215, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 215, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 216, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 216, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 216, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 217, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 217, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 217, "RAZ", 1, 1, 0, 0},
|
|
{"PORT" , 0, 6, 218, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 218, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP_SZ" , 0, 6, 219, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 219, "RAZ", 1, 1, 0, 0},
|
|
{"BACK" , 0, 4, 220, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 220, "RAZ", 1, 1, 0, 0},
|
|
{"BACK" , 0, 4, 221, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 221, "RAZ", 1, 1, 0, 0},
|
|
{"PWP" , 0, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_NEW" , 1, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_OLD" , 2, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRC_OFF" , 3, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ0" , 4, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ1" , 5, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM_WORD" , 6, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM0" , 7, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM1" , 8, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM2" , 9, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM3" , 10, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPQ_PBE0" , 11, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPQ_PBE1" , 12, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_POW" , 13, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_WP1" , 14, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_WQED" , 15, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSR_NCMD" , 16, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSR_MEM" , 17, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 222, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_ENB" , 0, 40, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 223, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_CNT" , 0, 64, 224, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_EN" , 0, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OPC_MODE" , 1, 2, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PBP_EN" , 3, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WQE_LEND" , 4, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKT_LEND" , 5, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NADDBUF" , 6, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDPKT" , 7, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 8, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LEN_M8" , 9, 1, 225, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PKT_OFF" , 10, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPD_FULL" , 11, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PQ_NABUF" , 12, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PQ_APKT" , 13, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NO_WPTR" , 14, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 225, "RAZ", 1, 1, 0, 0},
|
|
{"PRC_PAR0" , 0, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR1" , 1, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR2" , 2, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR3" , 3, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_SUB" , 4, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DC_OVR" , 5, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CC_OVR" , 6, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C_COLL" , 7, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"D_COLL" , 8, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BC_OVR" , 9, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PQ_ADD" , 10, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PQ_SUB" , 11, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 226, "RAZ", 1, 1, 0, 0},
|
|
{"PRC_PAR0" , 0, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR1" , 1, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR2" , 2, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR3" , 3, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP_SUB" , 4, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DC_OVR" , 5, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CC_OVR" , 6, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C_COLL" , 7, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"D_COLL" , 8, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BC_OVR" , 9, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PQ_ADD" , 10, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PQ_SUB" , 11, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 227, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP_SZ" , 0, 6, 228, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 228, "RAZ", 1, 1, 0, 0},
|
|
{"MB_SIZE" , 0, 12, 229, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_12_63" , 12, 52, 229, "RAZ", 1, 1, 0, 0},
|
|
{"PTR" , 0, 29, 230, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 230, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 17, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_ENB" , 17, 1, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 231, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 17, 232, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_ENB" , 17, 1, 232, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 232, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 25, 233, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 233, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 25, 234, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 234, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 235, "RO", 0, 1, 0ull, 0},
|
|
{"WMARK" , 32, 32, 235, "R/W", 0, 1, 4294967295ull, 0},
|
|
{"INTR" , 0, 64, 236, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 0, 64, 237, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RADDR" , 0, 3, 238, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 3, 1, 238, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 4, 29, 238, "RO", 1, 1, 0, 0},
|
|
{"PRADDR" , 33, 3, 238, "RO", 1, 1, 0, 0},
|
|
{"MAX_PKT" , 36, 3, 238, "RO", 0, 0, 5ull, 5ull},
|
|
{"RESERVED_39_63" , 39, 25, 238, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 7, 239, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 7, 1, 239, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 8, 29, 239, "RO", 1, 1, 0, 0},
|
|
{"MAX_PKT" , 37, 7, 239, "RO", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_44_63" , 44, 20, 239, "RAZ", 1, 1, 0, 0},
|
|
{"WQE_PCNT" , 0, 7, 240, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_PCNT" , 7, 7, 240, "RO", 0, 0, 0ull, 0ull},
|
|
{"PFIF_CNT" , 14, 3, 240, "RO", 0, 0, 0ull, 0ull},
|
|
{"WQEV_CNT" , 17, 1, 240, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTV_CNT" , 18, 1, 240, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 240, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 8, 241, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 8, 1, 241, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 9, 29, 241, "RO", 1, 1, 0, 0},
|
|
{"PRADDR" , 38, 8, 241, "RO", 1, 1, 0, 0},
|
|
{"WRADDR" , 46, 8, 241, "RO", 1, 1, 0, 0},
|
|
{"MAX_CNTS" , 54, 7, 241, "RO", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_61_63" , 61, 3, 241, "RAZ", 1, 1, 0, 0},
|
|
{"PASS" , 0, 32, 242, "R/W", 0, 1, 0ull, 0},
|
|
{"DROP" , 32, 32, 242, "R/W", 0, 1, 0ull, 0},
|
|
{"Q0_PCNT" , 0, 32, 243, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 243, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_ENB" , 0, 36, 244, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AVG_DLY" , 36, 14, 244, "R/W", 0, 1, 0ull, 0},
|
|
{"PRB_DLY" , 50, 14, 244, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRT_ENB" , 0, 4, 245, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 245, "RAZ", 1, 1, 0, 0},
|
|
{"PRB_CON" , 0, 32, 246, "R/W", 0, 1, 0ull, 0},
|
|
{"AVG_CON" , 32, 8, 246, "R/W", 0, 1, 0ull, 0},
|
|
{"NEW_CON" , 40, 8, 246, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_PCNT" , 48, 1, 246, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 246, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 25, 247, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT" , 25, 6, 247, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 247, "RAZ", 1, 1, 0, 0},
|
|
{"PORT_BIT" , 0, 32, 248, "R/W", 0, 0, 4294967295ull, 4294967295ull},
|
|
{"RESERVED_32_35" , 32, 4, 248, "RAZ", 1, 1, 0, 0},
|
|
{"PORT_BIT2" , 36, 4, 248, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_40_63" , 40, 24, 248, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 249, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT_QOS" , 32, 9, 249, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_41_63" , 41, 23, 249, "RAZ", 1, 1, 0, 0},
|
|
{"WQE_POOL" , 0, 3, 250, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_3_63" , 3, 61, 250, "RAZ", 1, 1, 0, 0},
|
|
{"PTR" , 0, 29, 251, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 251, "RAZ", 1, 1, 0, 0},
|
|
{"MEM0" , 0, 1, 252, "RO", 0, 0, 0ull, 0ull},
|
|
{"MEM1" , 1, 1, 252, "RO", 0, 0, 0ull, 0ull},
|
|
{"RRC" , 2, 1, 252, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 252, "RAZ", 1, 1, 0, 0},
|
|
{"MEM0_ERR" , 0, 7, 253, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM1_ERR" , 7, 7, 253, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 253, "RAZ", 1, 1, 0, 0},
|
|
{"KED0_SBE" , 0, 1, 254, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KED0_DBE" , 1, 1, 254, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KED1_SBE" , 2, 1, 254, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KED1_DBE" , 3, 1, 254, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 254, "RAZ", 1, 1, 0, 0},
|
|
{"KED0_SBE" , 0, 1, 255, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KED0_DBE" , 1, 1, 255, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KED1_SBE" , 2, 1, 255, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KED1_DBE" , 3, 1, 255, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 255, "RAZ", 1, 1, 0, 0},
|
|
{"WLB_DAT" , 0, 4, 256, "RO", 0, 0, 0ull, 0ull},
|
|
{"STIN_MSK" , 4, 1, 256, "RO", 0, 0, 0ull, 0ull},
|
|
{"DT" , 5, 1, 256, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTCNT" , 6, 13, 256, "RO", 0, 0, 0ull, 0ull},
|
|
{"WLB_MSK" , 19, 4, 256, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTBNK" , 23, 1, 256, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 256, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"L2T" , 0, 9, 257, "RO", 0, 0, 0ull, 0ull},
|
|
{"VAB_VWCF0" , 9, 1, 257, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_10" , 10, 1, 257, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VAB_VWCF1" , 11, 1, 257, "RO", 0, 0, 0ull, 0ull},
|
|
{"VWDF0" , 12, 4, 257, "RO", 0, 0, 0ull, 0ull},
|
|
{"VWDF1" , 16, 4, 257, "RO", 0, 0, 0ull, 0ull},
|
|
{"ILC" , 20, 1, 257, "RO", 0, 0, 0ull, 0ull},
|
|
{"PLC0" , 21, 1, 257, "RO", 0, 0, 0ull, 0ull},
|
|
{"PLC1" , 22, 1, 257, "RO", 0, 0, 0ull, 0ull},
|
|
{"PLC2" , 23, 1, 257, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 257, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XRDDAT" , 0, 1, 258, "RO", 0, 0, 0ull, 0ull},
|
|
{"XRDMSK" , 1, 1, 258, "RO", 0, 0, 0ull, 0ull},
|
|
{"PICBST" , 2, 1, 258, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPCBST" , 3, 1, 258, "RO", 0, 0, 0ull, 0ull},
|
|
{"RHDB" , 4, 4, 258, "RO", 0, 0, 0ull, 0ull},
|
|
{"RMDB" , 8, 4, 258, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRB" , 12, 4, 258, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 258, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LRF_ARB_MODE" , 0, 1, 259, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RFB_ARB_MODE" , 1, 1, 259, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RSP_ARB_MODE" , 2, 1, 259, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MWF_CRD" , 3, 4, 259, "R/W", 0, 0, 2ull, 2ull},
|
|
{"IDXALIAS" , 7, 1, 259, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPEN" , 8, 1, 259, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FPEMPTY" , 9, 1, 259, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FPEXP" , 10, 4, 259, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DFILL_DIS" , 14, 1, 259, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DPRES0" , 15, 1, 259, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DPRES1" , 16, 1, 259, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XOR_BANK" , 17, 1, 259, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LBIST" , 18, 1, 259, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BSTRUN" , 19, 1, 259, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 259, "RAZ", 1, 1, 0, 0},
|
|
{"L2T" , 0, 1, 260, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2D" , 1, 1, 260, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FINV" , 2, 1, 260, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SET" , 3, 3, 260, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PPNUM" , 6, 4, 260, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LFB_DMP" , 10, 1, 260, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LFB_ENUM" , 11, 4, 260, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 260, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DT_TAG" , 0, 29, 261, "RO", 0, 0, 0ull, 0ull},
|
|
{"DT_VLD" , 29, 1, 261, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_30" , 30, 1, 261, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DTENA" , 31, 1, 261, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 261, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PLC0RMSK" , 0, 32, 262, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PLC1RMSK" , 32, 32, 262, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PLC2RMSK" , 0, 32, 263, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ILCRMSK" , 32, 32, 263, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OOB1EN" , 0, 1, 264, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OOB2EN" , 1, 1, 264, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OOB3EN" , 2, 1, 264, "R/W", 0, 0, 0ull, 1ull},
|
|
{"L2TSECEN" , 3, 1, 264, "R/W", 0, 0, 0ull, 1ull},
|
|
{"L2TDEDEN" , 4, 1, 264, "R/W", 0, 0, 0ull, 1ull},
|
|
{"L2DSECEN" , 5, 1, 264, "R/W", 0, 0, 0ull, 1ull},
|
|
{"L2DDEDEN" , 6, 1, 264, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LCKENA" , 7, 1, 264, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LCK2ENA" , 8, 1, 264, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_9_63" , 9, 55, 264, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OOB1" , 0, 1, 265, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OOB2" , 1, 1, 265, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OOB3" , 2, 1, 265, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"L2TSEC" , 3, 1, 265, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"L2TDED" , 4, 1, 265, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"L2DSEC" , 5, 1, 265, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"L2DDED" , 6, 1, 265, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK" , 7, 1, 265, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK2" , 8, 1, 265, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 265, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_ENA" , 0, 1, 266, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_3" , 1, 3, 266, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_BASE" , 4, 27, 266, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 266, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_OFFSET" , 0, 10, 267, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 267, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VLD" , 0, 1, 268, "RO", 0, 0, 0ull, 0ull},
|
|
{"CMD" , 1, 4, 268, "RO", 0, 0, 0ull, 0ull},
|
|
{"SID" , 5, 9, 268, "RO", 0, 0, 0ull, 0ull},
|
|
{"VABNUM" , 14, 4, 268, "RO", 0, 0, 0ull, 0ull},
|
|
{"SET" , 18, 3, 268, "RO", 0, 0, 0ull, 0ull},
|
|
{"IHD" , 21, 1, 268, "RO", 0, 0, 0ull, 0ull},
|
|
{"ITL" , 22, 1, 268, "RO", 0, 0, 0ull, 0ull},
|
|
{"INXT" , 23, 4, 268, "RO", 0, 0, 0ull, 0ull},
|
|
{"VAM" , 27, 1, 268, "RO", 0, 0, 0ull, 0ull},
|
|
{"STCFL" , 28, 1, 268, "RO", 0, 0, 0ull, 0ull},
|
|
{"STINV" , 29, 1, 268, "RO", 0, 0, 0ull, 0ull},
|
|
{"STPND" , 30, 1, 268, "RO", 0, 0, 0ull, 0ull},
|
|
{"STCPND" , 31, 1, 268, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 268, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VLD" , 0, 1, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTPRB" , 1, 1, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRBRTY" , 2, 1, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTMFL" , 3, 1, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTVTM" , 4, 1, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTRSC" , 5, 1, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTRSP" , 6, 1, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTDT" , 7, 1, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTRDA" , 8, 1, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTM" , 9, 1, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWRM" , 10, 1, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWHF" , 11, 1, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWHP" , 12, 1, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTDQ" , 13, 1, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTDW" , 14, 1, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTRSP" , 15, 1, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"BID" , 16, 2, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"DSGOING" , 18, 1, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 269, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_IDX" , 0, 11, 270, "RO", 0, 0, 0ull, 0ull},
|
|
{"LFB_TAG" , 11, 16, 270, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_63" , 27, 37, 270, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_HWM" , 0, 4, 271, "R/W", 0, 0, 15ull, 15ull},
|
|
{"STPARTDIS" , 4, 1, 271, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 271, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STENA" , 0, 1, 272, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWBENA" , 1, 1, 272, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 272, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 0, 14, 273, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_19" , 14, 6, 273, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SADR" , 20, 14, 273, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_35" , 34, 2, 273, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSRC" , 36, 1, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 37, 27, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 0, 14, 274, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_19" , 14, 6, 274, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SADR" , 20, 14, 274, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_35" , 34, 2, 274, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSRC" , 36, 1, 274, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 37, 27, 274, "RO", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 0, 14, 275, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_19" , 14, 6, 275, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SADR" , 20, 14, 275, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_35" , 34, 2, 275, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSRC" , 36, 1, 275, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 37, 27, 275, "RO", 0, 0, 0ull, 0ull},
|
|
{"PFCNT0" , 0, 36, 276, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 276, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT0SEL" , 0, 6, 277, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0CLR" , 6, 1, 277, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0ENA" , 7, 1, 277, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1SEL" , 8, 6, 277, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1CLR" , 14, 1, 277, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1ENA" , 15, 1, 277, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2SEL" , 16, 6, 277, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2CLR" , 22, 1, 277, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2ENA" , 23, 1, 277, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3SEL" , 24, 6, 277, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3CLR" , 30, 1, 277, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3ENA" , 31, 1, 277, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0RDCLR" , 32, 1, 277, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1RDCLR" , 33, 1, 277, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2RDCLR" , 34, 1, 277, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3RDCLR" , 35, 1, 277, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 277, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP0GRP" , 0, 2, 278, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP1GRP" , 2, 2, 278, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP2GRP" , 4, 2, 278, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP3GRP" , 6, 2, 278, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP4GRP" , 8, 2, 278, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP5GRP" , 10, 2, 278, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP6GRP" , 12, 2, 278, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP7GRP" , 14, 2, 278, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP8GRP" , 16, 2, 278, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP9GRP" , 18, 2, 278, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP10GRP" , 20, 2, 278, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP11GRP" , 22, 2, 278, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 278, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK0" , 0, 8, 279, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK1" , 8, 8, 279, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK2" , 16, 8, 279, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK3" , 24, 8, 279, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 279, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK4" , 0, 8, 280, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK5" , 8, 8, 280, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK6" , 16, 8, 280, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK7" , 24, 8, 280, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 280, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK8" , 0, 8, 281, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK9" , 8, 8, 281, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK10" , 16, 8, 281, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK11" , 24, 8, 281, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 281, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSKIOB" , 0, 8, 282, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 282, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q0STAT" , 0, 34, 283, "RO", 0, 0, 0ull, 0ull},
|
|
{"FTL" , 34, 1, 283, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_35_63" , 35, 29, 283, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q1STAT" , 0, 34, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 284, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q2STAT" , 0, 34, 285, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 285, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q3STAT" , 0, 34, 286, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 286, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 0, 1, 287, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_INTENA" , 1, 1, 287, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DED_INTENA" , 2, 1, 287, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 3, 1, 287, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 4, 1, 287, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BMHCLSEL" , 5, 1, 287, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 287, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 0, 11, 288, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSET" , 11, 3, 288, "RO", 0, 0, 0ull, 0ull},
|
|
{"FOWMSK" , 14, 4, 288, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADRU" , 18, 1, 288, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 288, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW0" , 0, 10, 289, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW1" , 10, 10, 289, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 289, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW2" , 0, 10, 290, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW3" , 10, 10, 290, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 290, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q0FUS" , 0, 34, 291, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 291, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q1FUS" , 0, 34, 292, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 292, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q2FUS" , 0, 34, 293, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 293, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q3FUS" , 0, 34, 294, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRIP_1024K" , 34, 1, 294, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRIP_512K" , 35, 1, 294, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_36" , 36, 1, 294, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EMA_CTL" , 37, 3, 294, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 294, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 0, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_INTENA" , 1, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DED_INTENA" , 2, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 3, 1, 295, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 4, 1, 295, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FSYN" , 5, 6, 295, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 11, 10, 295, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSET" , 21, 3, 295, "RO", 0, 0, 0ull, 0ull},
|
|
{"LCKERR" , 24, 1, 295, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK_INTENA" , 25, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LCKERR2" , 26, 1, 295, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK_INTENA2" , 27, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FADRU" , 28, 1, 295, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 295, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RATE" , 0, 8, 296, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_8_63" , 8, 56, 296, "RAZ", 1, 1, 0, 0},
|
|
{"PHASE" , 0, 7, 297, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_7_63" , 7, 57, 297, "RAZ", 1, 1, 0, 0},
|
|
{"RATE" , 0, 16, 298, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 298, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_EN" , 0, 1, 299, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 299, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 300, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 300, "RAZ", 1, 1, 0, 0},
|
|
{"POLARITY" , 0, 1, 301, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 301, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_EN" , 0, 8, 302, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 302, "RAZ", 1, 1, 0, 0},
|
|
{"FORMAT" , 0, 4, 303, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 303, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 6, 304, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 304, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 6, 305, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 305, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 32, 306, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 306, "RAZ", 1, 1, 0, 0},
|
|
{"CLR" , 0, 32, 307, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 307, "RAZ", 1, 1, 0, 0},
|
|
{"SET" , 0, 32, 308, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 308, "RAZ", 1, 1, 0, 0},
|
|
{"START" , 0, 1, 309, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 309, "RAZ", 1, 0, 0, 0ull},
|
|
{"MRD" , 0, 3, 310, "RO", 1, 0, 0, 0ull},
|
|
{"MRF" , 3, 1, 310, "RO", 1, 0, 0, 0ull},
|
|
{"MWC" , 4, 1, 310, "RO", 1, 0, 0, 0ull},
|
|
{"MWD" , 5, 3, 310, "RO", 1, 0, 0, 0ull},
|
|
{"MWF" , 8, 1, 310, "RO", 1, 0, 0, 0ull},
|
|
{"CSRE2D" , 9, 1, 310, "RO", 1, 0, 0, 0ull},
|
|
{"CSRD2E" , 10, 1, 310, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 310, "RAZ", 1, 0, 0, 0ull},
|
|
{"PCTL_DAT" , 0, 5, 311, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_11" , 5, 7, 311, "RAZ", 0, 1, 0ull, 0},
|
|
{"PCTL_CSR" , 12, 4, 311, "R/W", 0, 1, 15ull, 0},
|
|
{"NCTL_DAT" , 16, 4, 311, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_27" , 20, 8, 311, "RAZ", 0, 1, 0ull, 0},
|
|
{"NCTL_CSR" , 28, 4, 311, "R/W", 0, 1, 15ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 311, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DIC" , 0, 2, 312, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QS_DIC" , 2, 2, 312, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TSKW" , 4, 2, 312, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SIL_LAT" , 6, 2, 312, "R/W", 0, 0, 1ull, 1ull},
|
|
{"BPRCH" , 8, 1, 312, "R/W", 0, 1, 0ull, 0},
|
|
{"FPRCH2" , 9, 1, 312, "R/W", 0, 0, 0ull, 1ull},
|
|
{"MODE32B" , 10, 1, 312, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRESET" , 11, 1, 312, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INORDER_MRF" , 12, 1, 312, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INORDER_MWF" , 13, 1, 312, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"R2R_SLOT" , 14, 1, 312, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RDIMM_ENA" , 15, 1, 312, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_17" , 16, 2, 312, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX_WRITE_BATCH" , 18, 4, 312, "R/W", 0, 0, 8ull, 8ull},
|
|
{"XOR_BANK" , 22, 1, 312, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SLOW_SCF" , 23, 1, 312, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DDR__PCTL" , 24, 4, 312, "RO", 1, 1, 0, 0},
|
|
{"DDR__NCTL" , 28, 4, 312, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 312, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 313, "RAZ", 0, 1, 0ull, 0},
|
|
{"DCC_ENABLE" , 8, 1, 313, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SIL_MODE" , 9, 1, 313, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEQUENCE" , 10, 3, 313, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDLEPOWER" , 13, 3, 313, "R/W", 0, 0, 0ull, 6ull},
|
|
{"FORCEWRITE" , 16, 4, 313, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECC_ADR" , 20, 1, 313, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_21_63" , 21, 43, 313, "RAZ", 1, 1, 0, 0},
|
|
{"DCLKCNT_HI" , 0, 32, 314, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 314, "RAZ", 1, 1, 0, 0},
|
|
{"DCLKCNT_LO" , 0, 32, 315, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 315, "RAZ", 1, 1, 0, 0},
|
|
{"DCLK90_VLU" , 0, 5, 316, "R/W", 0, 1, 0ull, 0},
|
|
{"DCLK90_LD" , 5, 1, 316, "R/W", 0, 1, 0ull, 0},
|
|
{"DCLK90_BYP" , 6, 1, 316, "R/W", 0, 1, 0ull, 0},
|
|
{"OFF90_ENA" , 7, 1, 316, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 316, "RAZ", 1, 1, 0, 0},
|
|
{"DDR2" , 0, 1, 317, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RDQS" , 1, 1, 317, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLL90_BYP" , 2, 1, 317, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLL90_VLU" , 3, 5, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"QDLL_ENA" , 8, 1, 317, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ODT_ENA" , 9, 1, 317, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DDR2T" , 10, 1, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"CRIP_MODE" , 11, 1, 317, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TFAW" , 12, 5, 317, "R/W", 0, 0, 0ull, 9ull},
|
|
{"DDR_EOF" , 17, 4, 317, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SILO_HC" , 21, 1, 317, "R/W", 0, 1, 1ull, 0},
|
|
{"TWR" , 22, 3, 317, "R/W", 0, 0, 3ull, 1ull},
|
|
{"BWCNT" , 25, 1, 317, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POCAS" , 26, 1, 317, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDLAT" , 27, 3, 317, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BURST8" , 30, 1, 317, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BANK8" , 31, 1, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 317, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CLK" , 0, 4, 318, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_4" , 4, 1, 318, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CMD" , 5, 4, 318, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 318, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DQ" , 10, 4, 318, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 318, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DLL90_VLU" , 0, 5, 319, "R/W", 0, 1, 0ull, 0},
|
|
{"DLL90_ENA" , 5, 1, 319, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLL90_BYP" , 6, 1, 319, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRESET" , 7, 1, 319, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 319, "RAZ", 1, 1, 0, 0},
|
|
{"CS_MASK" , 0, 8, 320, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_15" , 8, 8, 320, "RAZ", 0, 1, 0ull, 0},
|
|
{"ROW_LSB" , 16, 3, 320, "R/W", 0, 1, 3ull, 0},
|
|
{"BANK8" , 19, 1, 320, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_63" , 20, 44, 320, "RAZ", 0, 1, 0ull, 0},
|
|
{"MRDSYN0" , 0, 8, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN1" , 8, 8, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN2" , 16, 8, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN3" , 24, 8, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 321, "RAZ", 1, 1, 0, 0},
|
|
{"FCOL" , 0, 12, 322, "RO", 0, 0, 0ull, 0ull},
|
|
{"FROW" , 12, 14, 322, "RO", 0, 0, 0ull, 0ull},
|
|
{"FBANK" , 26, 3, 322, "RO", 0, 0, 0ull, 0ull},
|
|
{"FBUNK" , 29, 1, 322, "RO", 0, 0, 0ull, 0ull},
|
|
{"FDIMM" , 30, 2, 322, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 322, "RAZ", 1, 1, 0, 0},
|
|
{"IFBCNT_HI" , 0, 32, 323, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 323, "RAZ", 1, 1, 0, 0},
|
|
{"IFBCNT_LO" , 0, 32, 324, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 324, "RAZ", 1, 1, 0, 0},
|
|
{"INIT_START" , 0, 1, 325, "WR0", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 1, 1, 325, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ROW_LSB" , 2, 3, 325, "R/W", 0, 1, 3ull, 0},
|
|
{"PBANK_LSB" , 5, 4, 325, "R/W", 0, 1, 5ull, 0},
|
|
{"REF_INT" , 9, 6, 325, "R/W", 0, 0, 1ull, 2ull},
|
|
{"TCL" , 15, 4, 325, "R/W", 0, 1, 3ull, 0},
|
|
{"INTR_SEC_ENA" , 19, 1, 325, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INTR_DED_ENA" , 20, 1, 325, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 21, 4, 325, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 25, 4, 325, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BUNK_ENA" , 29, 1, 325, "R/W", 0, 1, 0ull, 0},
|
|
{"SILO_QC" , 30, 1, 325, "R/W", 0, 1, 0ull, 0},
|
|
{"RESET" , 31, 1, 325, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 325, "RAZ", 1, 1, 0, 0},
|
|
{"TRAS" , 0, 5, 326, "R/W", 0, 0, 12ull, 12ull},
|
|
{"TRCD" , 5, 4, 326, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TWTR" , 9, 4, 326, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TRP" , 13, 4, 326, "R/W", 0, 0, 5ull, 4ull},
|
|
{"TRFC" , 17, 5, 326, "R/W", 0, 0, 6ull, 7ull},
|
|
{"TMRD" , 22, 3, 326, "R/W", 0, 0, 2ull, 2ull},
|
|
{"CASLAT" , 25, 3, 326, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TRRD" , 28, 3, 326, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_31_63" , 31, 33, 326, "RAZ", 1, 1, 0, 0},
|
|
{"OPSCNT_HI" , 0, 32, 327, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 327, "RAZ", 1, 1, 0, 0},
|
|
{"OPSCNT_LO" , 0, 32, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 328, "RAZ", 1, 1, 0, 0},
|
|
{"EN2" , 0, 1, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"EN4" , 1, 1, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"EN6" , 2, 1, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"EN8" , 3, 1, 329, "R/W", 0, 1, 1ull, 0},
|
|
{"EN12" , 4, 1, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"EN16" , 5, 1, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_7" , 6, 2, 329, "RAZ", 0, 1, 0ull, 0},
|
|
{"CLKR" , 8, 6, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"CLKF" , 14, 12, 329, "R/W", 0, 1, 31ull, 0},
|
|
{"RESET_N" , 26, 1, 329, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DIV_RESET" , 27, 1, 329, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 329, "RAZ", 0, 1, 0ull, 0},
|
|
{"FBSLIP" , 0, 1, 330, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RFSLIP" , 1, 1, 330, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_21" , 2, 20, 330, "RAZ", 1, 1, 0, 0},
|
|
{"DDR__PCTL" , 22, 5, 330, "RO", 1, 1, 0, 0},
|
|
{"DDR__NCTL" , 27, 5, 330, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 330, "RAZ", 1, 1, 0, 0},
|
|
{"BNK" , 0, 3, 331, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 331, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"COL" , 4, 12, 331, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROW" , 16, 16, 331, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PATTERN" , 32, 8, 331, "R/W", 0, 0, 170ull, 170ull},
|
|
{"RANKMASK" , 40, 4, 331, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_63" , 44, 20, 331, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"BYTE" , 0, 4, 332, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_15" , 4, 12, 332, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"BITMASK" , 16, 16, 332, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 332, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"BYTE0" , 0, 4, 333, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE1" , 4, 4, 333, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE2" , 8, 4, 333, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE3" , 12, 4, 333, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE4" , 16, 4, 333, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE5" , 20, 4, 333, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE6" , 24, 4, 333, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE7" , 28, 4, 333, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE8" , 32, 4, 333, "R/W", 0, 1, 0ull, 0},
|
|
{"STATUS" , 36, 2, 333, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_38_63" , 38, 26, 333, "RAZ", 1, 0, 0, 0ull},
|
|
{"PCTL" , 0, 5, 334, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 334, "RAZ", 0, 1, 0ull, 0},
|
|
{"NCTL" , 8, 4, 334, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_12_15" , 12, 4, 334, "RAZ", 0, 1, 0ull, 0},
|
|
{"ENABLE" , 16, 1, 334, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_17_63" , 17, 47, 334, "RAZ", 0, 1, 0ull, 0},
|
|
{"RODT_LO0" , 0, 4, 335, "R/W", 0, 0, 15ull, 0ull},
|
|
{"RODT_LO1" , 4, 4, 335, "R/W", 0, 0, 15ull, 0ull},
|
|
{"RODT_LO2" , 8, 4, 335, "R/W", 0, 0, 15ull, 0ull},
|
|
{"RODT_LO3" , 12, 4, 335, "R/W", 0, 0, 15ull, 0ull},
|
|
{"RODT_HI0" , 16, 4, 335, "R/W", 0, 0, 15ull, 0ull},
|
|
{"RODT_HI1" , 20, 4, 335, "R/W", 0, 0, 15ull, 0ull},
|
|
{"RODT_HI2" , 24, 4, 335, "R/W", 0, 0, 15ull, 0ull},
|
|
{"RODT_HI3" , 28, 4, 335, "R/W", 0, 0, 15ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 335, "RAZ", 1, 1, 0, 0},
|
|
{"WODT_D0_R0" , 0, 8, 336, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D0_R1" , 8, 8, 336, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D1_R0" , 16, 8, 336, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D1_R1" , 24, 8, 336, "R/W", 0, 0, 255ull, 255ull},
|
|
{"RESERVED_32_63" , 32, 32, 336, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WODT_D2_R0" , 0, 8, 337, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D2_R1" , 8, 8, 337, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D3_R0" , 16, 8, 337, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D3_R1" , 24, 8, 337, "R/W", 0, 0, 255ull, 255ull},
|
|
{"RESERVED_32_63" , 32, 32, 337, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"NCBI" , 0, 1, 338, "RO", 0, 0, 0ull, 0ull},
|
|
{"LOC" , 1, 1, 338, "RO", 0, 0, 0ull, 0ull},
|
|
{"DMA" , 2, 1, 338, "RO", 0, 0, 0ull, 0ull},
|
|
{"NCBO_0" , 3, 1, 338, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 338, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 5, 339, "R/W", 0, 1, 31ull, 0},
|
|
{"PCTL" , 5, 5, 339, "R/W", 0, 1, 31ull, 0},
|
|
{"RESERVED_10_63" , 10, 54, 339, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 36, 340, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 36, 20, 340, "R/W", 0, 1, 0ull, 0},
|
|
{"ENDIAN" , 56, 1, 340, "R/W", 0, 1, 0ull, 0},
|
|
{"SWAP8" , 57, 1, 340, "R/W", 0, 1, 0ull, 0},
|
|
{"SWAP16" , 58, 1, 340, "R/W", 0, 1, 0ull, 0},
|
|
{"SWAP32" , 59, 1, 340, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_60" , 60, 1, 340, "RAZ", 1, 1, 0, 0},
|
|
{"CLR" , 61, 1, 340, "R/W", 0, 1, 0ull, 0},
|
|
{"RW" , 62, 1, 340, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 63, 1, 340, "R/W", 0, 1, 0ull, 0},
|
|
{"DONE" , 0, 1, 341, "R/W1C", 0, 1, 0ull, 0},
|
|
{"DMARQ" , 1, 1, 341, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_2_63" , 2, 62, 341, "RAZ", 1, 1, 0, 0},
|
|
{"DONE" , 0, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"DMARQ" , 1, 1, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 342, "RAZ", 1, 1, 0, 0},
|
|
{"DMARQ" , 0, 6, 343, "R/W", 0, 1, 63ull, 0},
|
|
{"DMACK_S" , 6, 6, 343, "R/W", 0, 1, 63ull, 0},
|
|
{"OE_A" , 12, 6, 343, "R/W", 0, 1, 63ull, 0},
|
|
{"OE_N" , 18, 6, 343, "R/W", 0, 1, 63ull, 0},
|
|
{"WE_A" , 24, 6, 343, "R/W", 0, 1, 63ull, 0},
|
|
{"WE_N" , 30, 6, 343, "R/W", 0, 1, 63ull, 0},
|
|
{"DMACK_H" , 36, 6, 343, "R/W", 0, 1, 63ull, 0},
|
|
{"PAUSE" , 42, 6, 343, "R/W", 0, 1, 63ull, 0},
|
|
{"RESERVED_48_54" , 48, 7, 343, "RAZ", 1, 1, 0, 0},
|
|
{"WIDTH" , 55, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"DDR" , 56, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RD_DLY" , 57, 3, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"TIM_MULT" , 60, 2, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"DMARQ_PI" , 62, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"DMACK_PI" , 63, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR_ERR" , 0, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WAIT_ERR" , 1, 1, 344, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 344, "RAZ", 1, 1, 0, 0},
|
|
{"ADR_INT" , 0, 1, 345, "R/W", 0, 1, 0ull, 0},
|
|
{"WAIT_INT" , 1, 1, 345, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 345, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 346, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 3, 5, 346, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 346, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 347, "RAZ", 1, 1, 0, 0},
|
|
{"BASE" , 3, 25, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_30" , 28, 3, 347, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 31, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 347, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 348, "R/W", 1, 1, 0, 0},
|
|
{"BASE" , 0, 16, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 16, 12, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"WIDTH" , 28, 1, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"ALE" , 29, 1, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"ORBIT" , 30, 1, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 31, 1, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"OE_EXT" , 32, 2, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"WE_EXT" , 34, 2, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"SAM" , 36, 1, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"RD_DLY" , 37, 3, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"TIM_MULT" , 40, 2, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"DMACK" , 42, 2, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 349, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 6, 350, "R/W", 0, 1, 63ull, 0},
|
|
{"CE" , 6, 6, 350, "R/W", 0, 1, 63ull, 0},
|
|
{"OE" , 12, 6, 350, "R/W", 0, 1, 63ull, 0},
|
|
{"WE" , 18, 6, 350, "R/W", 0, 1, 63ull, 0},
|
|
{"RD_HLD" , 24, 6, 350, "R/W", 0, 1, 63ull, 0},
|
|
{"WR_HLD" , 30, 6, 350, "R/W", 0, 1, 63ull, 0},
|
|
{"PAUSE" , 36, 6, 350, "R/W", 0, 1, 63ull, 0},
|
|
{"WAIT" , 42, 6, 350, "R/W", 0, 1, 63ull, 0},
|
|
{"PAGE" , 48, 6, 350, "R/W", 0, 1, 63ull, 0},
|
|
{"ALE" , 54, 6, 350, "R/W", 0, 1, 63ull, 0},
|
|
{"PAGES" , 60, 2, 350, "R/W", 0, 1, 0ull, 0},
|
|
{"WAITM" , 62, 1, 350, "R/W", 0, 1, 0ull, 0},
|
|
{"PAGEM" , 63, 1, 350, "R/W", 0, 1, 0ull, 0},
|
|
{"FIF_THR" , 0, 6, 351, "R/W", 0, 0, 26ull, 26ull},
|
|
{"RESERVED_6_7" , 6, 2, 351, "RAZ", 1, 1, 0, 0},
|
|
{"FIF_CNT" , 8, 6, 351, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_15" , 14, 2, 351, "RAZ", 1, 1, 0, 0},
|
|
{"DMA_THR" , 16, 6, 351, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_22_63" , 22, 42, 351, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 64, 352, "R/W", 1, 1, 0, 0},
|
|
{"MAN_INFO" , 0, 32, 353, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 353, "RAZ", 1, 1, 0, 0},
|
|
{"MAN_INFO" , 0, 32, 354, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 354, "RAZ", 1, 1, 0, 0},
|
|
{"PP_DIS" , 0, 12, 355, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_12_15" , 12, 4, 355, "RO", 1, 1, 0, 0},
|
|
{"CHIP_ID" , 16, 8, 355, "RO", 1, 1, 0, 0},
|
|
{"BIST_DIS" , 24, 1, 355, "RO", 1, 1, 0, 0},
|
|
{"RST_SHT" , 25, 1, 355, "RO", 1, 1, 0, 0},
|
|
{"NOCRYPTO" , 26, 1, 355, "RO", 1, 1, 0, 0},
|
|
{"NOMUL" , 27, 1, 355, "RO", 1, 1, 0, 0},
|
|
{"NODFA_CP2" , 28, 1, 355, "RO", 1, 1, 0, 0},
|
|
{"NOKASU" , 29, 1, 355, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_30_31" , 30, 2, 355, "RAZ", 1, 1, 0, 0},
|
|
{"RAID_EN" , 32, 1, 355, "RO", 1, 1, 0, 0},
|
|
{"FUS318" , 33, 1, 355, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_34_63" , 34, 30, 355, "RAZ", 1, 1, 0, 0},
|
|
{"ICACHE" , 0, 24, 356, "RO", 1, 1, 0, 0},
|
|
{"NODFA_DTE" , 24, 1, 356, "RO", 1, 1, 0, 0},
|
|
{"NOZIP" , 25, 1, 356, "RO", 1, 1, 0, 0},
|
|
{"EFUS_IGN" , 26, 1, 356, "RO", 1, 1, 0, 0},
|
|
{"EFUS_LCK" , 27, 1, 356, "RO", 1, 1, 0, 0},
|
|
{"BAR2_EN" , 28, 1, 356, "RO", 1, 1, 0, 0},
|
|
{"ZIP_CRIP" , 29, 2, 356, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_31_63" , 31, 33, 356, "RAZ", 1, 1, 0, 0},
|
|
{"EMA" , 0, 3, 357, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 357, "RAZ", 1, 1, 0, 0},
|
|
{"EFF_EMA" , 4, 3, 357, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 357, "RAZ", 1, 1, 0, 0},
|
|
{"PDF" , 0, 64, 358, "RO", 1, 1, 0, 0},
|
|
{"FBSLIP" , 0, 1, 359, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RFSLIP" , 1, 1, 359, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 359, "RAZ", 1, 1, 0, 0},
|
|
{"PROG" , 0, 1, 360, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_1_63" , 1, 63, 360, "RAZ", 1, 1, 0, 0},
|
|
{"SETUP" , 0, 8, 361, "R/W", 0, 1, 3ull, 0},
|
|
{"SCLK_HI" , 8, 12, 361, "R/W", 0, 1, 100ull, 0},
|
|
{"SCLK_LO" , 20, 4, 361, "R/W", 0, 1, 2ull, 0},
|
|
{"OUT" , 24, 8, 361, "R/W", 0, 1, 3ull, 0},
|
|
{"PROG_PIN" , 32, 1, 361, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_33_63" , 33, 31, 361, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 8, 362, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EFUSE" , 8, 1, 362, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 362, "RAZ", 1, 1, 0, 0},
|
|
{"PEND" , 12, 1, 362, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 362, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 16, 8, 362, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_24_63" , 24, 40, 362, "RAZ", 1, 1, 0, 0},
|
|
{"REPAIR0" , 0, 14, 363, "RO", 0, 0, 0ull, 0ull},
|
|
{"REPAIR1" , 14, 14, 363, "RO", 0, 0, 0ull, 0ull},
|
|
{"REPAIR2" , 28, 14, 363, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_42_63" , 42, 22, 363, "RAZ", 1, 1, 0, 0},
|
|
{"TOO_MANY" , 0, 1, 364, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 364, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 3, 365, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_3_63" , 3, 61, 365, "RAZ", 1, 1, 0, 0},
|
|
{"ST_INT" , 0, 1, 366, "R/W1C", 0, 1, 0ull, 0},
|
|
{"TS_INT" , 1, 1, 366, "R/W1C", 0, 1, 0ull, 0},
|
|
{"CORE_INT" , 2, 1, 366, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_3" , 3, 1, 366, "RAZ", 1, 1, 0, 0},
|
|
{"ST_EN" , 4, 1, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"TS_EN" , 5, 1, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"CORE_EN" , 6, 1, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_7" , 7, 1, 366, "RAZ", 1, 1, 0, 0},
|
|
{"SDA_OVR" , 8, 1, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"SCL_OVR" , 9, 1, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"SDA" , 10, 1, 366, "RO", 1, 1, 0, 0},
|
|
{"SCL" , 11, 1, 366, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_12_63" , 12, 52, 366, "RAZ", 1, 1, 0, 0},
|
|
{"D" , 0, 32, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"EOP_IA" , 32, 3, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"IA" , 35, 5, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"A" , 40, 10, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"SCR" , 50, 2, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 52, 3, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"SOVR" , 55, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"R" , 56, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"OP" , 57, 4, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"EIA" , 61, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"SLONLY" , 62, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"V" , 63, 1, 367, "RC/W", 0, 1, 0ull, 0},
|
|
{"D" , 0, 32, 368, "R/W", 0, 1, 0ull, 0},
|
|
{"IA" , 32, 8, 368, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_40_63" , 40, 24, 368, "RAZ", 1, 1, 0, 0},
|
|
{"D" , 0, 32, 369, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_32_61" , 32, 30, 369, "RAZ", 1, 1, 0, 0},
|
|
{"V" , 62, 2, 369, "RC/W", 0, 1, 0ull, 0},
|
|
{"DLH" , 0, 8, 370, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 370, "RAZ", 1, 1, 0, 0},
|
|
{"DLL" , 0, 8, 371, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 371, "RAZ", 1, 1, 0, 0},
|
|
{"FAR" , 0, 1, 372, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 372, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 373, "WO", 0, 1, 0ull, 0},
|
|
{"RXFR" , 1, 1, 373, "WO", 0, 1, 0ull, 0},
|
|
{"TXFR" , 2, 1, 373, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_3" , 3, 1, 373, "RAZ", 0, 1, 0ull, 0},
|
|
{"TXTRIG" , 4, 2, 373, "WO", 0, 1, 0ull, 0},
|
|
{"RXTRIG" , 6, 2, 373, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 373, "RAZ", 1, 1, 0, 0},
|
|
{"HTX" , 0, 1, 374, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 374, "RAZ", 1, 1, 0, 0},
|
|
{"ERBFI" , 0, 1, 375, "R/W", 0, 1, 0ull, 0},
|
|
{"ETBEI" , 1, 1, 375, "R/W", 0, 1, 0ull, 0},
|
|
{"ELSI" , 2, 1, 375, "R/W", 0, 1, 0ull, 0},
|
|
{"EDSSI" , 3, 1, 375, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_6" , 4, 3, 375, "RAZ", 0, 1, 0ull, 0},
|
|
{"PTIME" , 7, 1, 375, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 375, "RAZ", 1, 1, 0, 0},
|
|
{"IID" , 0, 4, 376, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_4_5" , 4, 2, 376, "RAZ", 0, 1, 0ull, 0},
|
|
{"FEN" , 6, 2, 376, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 376, "RAZ", 1, 1, 0, 0},
|
|
{"CLS" , 0, 2, 377, "R/W", 0, 1, 0ull, 0},
|
|
{"STOP" , 2, 1, 377, "R/W", 0, 1, 0ull, 0},
|
|
{"PEN" , 3, 1, 377, "R/W", 0, 1, 0ull, 0},
|
|
{"EPS" , 4, 1, 377, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_5" , 5, 1, 377, "RAZ", 0, 1, 0ull, 0},
|
|
{"BRK" , 6, 1, 377, "R/W", 0, 1, 0ull, 0},
|
|
{"DLAB" , 7, 1, 377, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 377, "RAZ", 1, 1, 0, 0},
|
|
{"DR" , 0, 1, 378, "RO", 0, 1, 0ull, 0},
|
|
{"OE" , 1, 1, 378, "RC", 0, 1, 0ull, 0},
|
|
{"PE" , 2, 1, 378, "RC", 0, 1, 0ull, 0},
|
|
{"FE" , 3, 1, 378, "RC", 0, 1, 0ull, 0},
|
|
{"BI" , 4, 1, 378, "RC", 0, 1, 0ull, 0},
|
|
{"THRE" , 5, 1, 378, "RO", 0, 1, 1ull, 0},
|
|
{"TEMT" , 6, 1, 378, "RO", 0, 1, 1ull, 0},
|
|
{"FERR" , 7, 1, 378, "RC", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 378, "RAZ", 1, 1, 0, 0},
|
|
{"DTR" , 0, 1, 379, "R/W", 0, 1, 0ull, 0},
|
|
{"RTS" , 1, 1, 379, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT1" , 2, 1, 379, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT2" , 3, 1, 379, "R/W", 0, 1, 0ull, 0},
|
|
{"LOOP" , 4, 1, 379, "R/W", 0, 1, 0ull, 0},
|
|
{"AFCE" , 5, 1, 379, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 379, "RAZ", 0, 1, 0ull, 0},
|
|
{"DCTS" , 0, 1, 380, "RC", 0, 1, 0ull, 0},
|
|
{"DDSR" , 1, 1, 380, "RC", 0, 1, 0ull, 0},
|
|
{"TERI" , 2, 1, 380, "RC", 0, 1, 0ull, 0},
|
|
{"DDCD" , 3, 1, 380, "RC", 0, 1, 0ull, 0},
|
|
{"CTS" , 4, 1, 380, "RO", 1, 1, 0, 0},
|
|
{"DSR" , 5, 1, 380, "RO", 0, 1, 0ull, 0},
|
|
{"RI" , 6, 1, 380, "RO", 0, 1, 0ull, 0},
|
|
{"DCD" , 7, 1, 380, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 380, "RAZ", 1, 1, 0, 0},
|
|
{"RBR" , 0, 8, 381, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 381, "RAZ", 1, 1, 0, 0},
|
|
{"RFL" , 0, 7, 382, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 382, "RAZ", 1, 1, 0, 0},
|
|
{"RFWD" , 0, 8, 383, "WO", 0, 1, 0ull, 0},
|
|
{"RFPE" , 8, 1, 383, "WO", 0, 1, 0ull, 0},
|
|
{"RFFE" , 9, 1, 383, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_10_63" , 10, 54, 383, "RAZ", 1, 1, 0, 0},
|
|
{"SBCR" , 0, 1, 384, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 384, "RAZ", 1, 1, 0, 0},
|
|
{"SCR" , 0, 8, 385, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 385, "RAZ", 1, 1, 0, 0},
|
|
{"SFE" , 0, 1, 386, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 386, "RAZ", 1, 1, 0, 0},
|
|
{"USR" , 0, 1, 387, "WO", 0, 1, 0ull, 0},
|
|
{"SRFR" , 1, 1, 387, "WO", 0, 1, 0ull, 0},
|
|
{"STFR" , 2, 1, 387, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_63" , 3, 61, 387, "RAZ", 1, 1, 0, 0},
|
|
{"SRT" , 0, 2, 388, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 388, "RAZ", 1, 1, 0, 0},
|
|
{"SRTS" , 0, 1, 389, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 389, "RAZ", 1, 1, 0, 0},
|
|
{"STT" , 0, 2, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 390, "RAZ", 1, 1, 0, 0},
|
|
{"TFL" , 0, 7, 391, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 391, "RAZ", 1, 1, 0, 0},
|
|
{"TFR" , 0, 8, 392, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 392, "RAZ", 1, 1, 0, 0},
|
|
{"THR" , 0, 8, 393, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 393, "RAZ", 1, 1, 0, 0},
|
|
{"BUSY" , 0, 1, 394, "RO", 0, 1, 0ull, 0},
|
|
{"TFNF" , 1, 1, 394, "RO", 0, 1, 1ull, 0},
|
|
{"TFE" , 2, 1, 394, "RO", 0, 1, 1ull, 0},
|
|
{"RFNE" , 3, 1, 394, "RO", 0, 1, 0ull, 0},
|
|
{"RFF" , 4, 1, 394, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 394, "RAZ", 1, 1, 0, 0},
|
|
{"ORFDAT" , 0, 1, 395, "RO", 0, 0, 0ull, 0ull},
|
|
{"IRFDAT" , 1, 1, 395, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPFDAT" , 2, 1, 395, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRQDAT" , 3, 1, 395, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 395, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MRQ_HWM" , 0, 2, 396, "R/W", 0, 0, 1ull, 1ull},
|
|
{"NBTARB" , 2, 1, 396, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LENDIAN" , 3, 1, 396, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 4, 1, 396, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EN" , 5, 1, 396, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BUSY" , 6, 1, 396, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRC_STRIP" , 7, 1, 396, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 396, "RAZ", 1, 1, 0, 0},
|
|
{"OVFENA" , 0, 1, 397, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IVFENA" , 1, 1, 397, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OTHENA" , 2, 1, 397, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ITHENA" , 3, 1, 397, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DATA_DRPENA" , 4, 1, 397, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IRUNENA" , 5, 1, 397, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ORUNENA" , 6, 1, 397, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 397, "RAZ", 1, 1, 0, 0},
|
|
{"IRCNT" , 0, 20, 398, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 398, "RAZ", 1, 1, 0, 0},
|
|
{"IRHWM" , 0, 20, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IBPLWM" , 20, 20, 399, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 399, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 400, "RAZ", 1, 1, 0, 0},
|
|
{"IBASE" , 3, 33, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_39" , 36, 4, 400, "RAZ", 1, 1, 0, 0},
|
|
{"ISIZE" , 40, 20, 400, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 400, "RAZ", 1, 1, 0, 0},
|
|
{"IDBELL" , 0, 20, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_31" , 20, 12, 401, "RAZ", 1, 1, 0, 0},
|
|
{"ITLPTR" , 32, 20, 401, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_52_63" , 52, 12, 401, "RAZ", 1, 1, 0, 0},
|
|
{"ODBLOVF" , 0, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IDBLOVF" , 1, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ORTHRESH" , 2, 1, 402, "RO", 0, 0, 0ull, 0ull},
|
|
{"IRTHRESH" , 3, 1, 402, "RO", 0, 0, 0ull, 0ull},
|
|
{"DATA_DRP" , 4, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IRUN" , 5, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ORUN" , 6, 1, 402, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 402, "RAZ", 1, 1, 0, 0},
|
|
{"ORCNT" , 0, 20, 403, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 403, "RAZ", 1, 1, 0, 0},
|
|
{"ORHWM" , 0, 20, 404, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 404, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 405, "RAZ", 1, 1, 0, 0},
|
|
{"OBASE" , 3, 33, 405, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_39" , 36, 4, 405, "RAZ", 1, 1, 0, 0},
|
|
{"OSIZE" , 40, 20, 405, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 405, "RAZ", 1, 1, 0, 0},
|
|
{"ODBELL" , 0, 20, 406, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_31" , 20, 12, 406, "RAZ", 1, 1, 0, 0},
|
|
{"OTLPTR" , 32, 20, 406, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_52_63" , 52, 12, 406, "RAZ", 1, 1, 0, 0},
|
|
{"OREMCNT" , 0, 20, 407, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 407, "RAZ", 1, 1, 0, 0},
|
|
{"IREMCNT" , 32, 20, 407, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_52_63" , 52, 12, 407, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR_V" , 0, 1, 408, "R/W", 0, 1, 0ull, 0},
|
|
{"END_SWP" , 1, 2, 408, "R/W", 0, 1, 0ull, 0},
|
|
{"CA" , 3, 1, 408, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDR_IDX" , 4, 14, 408, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_31" , 18, 14, 408, "RAZ", 1, 1, 0, 0},
|
|
{"NCB_CMD" , 0, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSI" , 1, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF4" , 2, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF3" , 3, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF2" , 4, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF1" , 5, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF0" , 6, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSM1" , 7, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSM0" , 8, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_P1" , 9, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_P0" , 10, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_N" , 11, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_C1" , 12, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_C0" , 13, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_P1" , 14, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_P0" , 15, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_N" , 16, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_C1" , 17, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_C0" , 18, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_CO" , 19, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_NO" , 20, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_PO" , 21, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_CO" , 22, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_NO" , 23, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_PO" , 24, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"CPL_P1" , 25, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"CPL_P0" , 26, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"N2P1_O" , 27, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"N2P1_C" , 28, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"N2P0_O" , 29, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"N2P0_C" , 30, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"D4_PST" , 31, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"D3_PST" , 32, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"D2_PST" , 33, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"D1_PST" , 34, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"D0_PST" , 35, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"D4_MEM" , 36, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"D3_MEM" , 37, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"D2_MEM" , 38, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"D1_MEM" , 39, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"D0_MEM" , 40, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_S1" , 41, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_S0" , 42, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_I1" , 43, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_I0" , 44, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_OUT" , 45, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_OIF" , 46, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_ODF" , 47, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_SLM" , 48, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_IND" , 49, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_CNTM" , 50, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_IMEM" , 51, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_POUT" , 52, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCSR_SL" , 53, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCSR_ID" , 54, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCSR_CNT" , 55, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCSR_IM" , 56, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCSR_INT" , 57, 1, 409, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_58_63" , 58, 6, 409, "RAZ", 1, 1, 0, 0},
|
|
{"WAIT_COM" , 0, 1, 410, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAR2_CAX" , 1, 1, 410, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAR2_ESX" , 2, 2, 410, "R/W", 0, 1, 0ull, 0},
|
|
{"BAR2_ENB" , 4, 1, 410, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PTLP_RO" , 5, 1, 410, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_6_6" , 6, 1, 410, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CTLP_RO" , 7, 1, 410, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INTA_MAP" , 8, 2, 410, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTB_MAP" , 10, 2, 410, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INTC_MAP" , 12, 2, 410, "R/W", 0, 0, 2ull, 2ull},
|
|
{"INTD_MAP" , 14, 2, 410, "R/W", 0, 0, 3ull, 3ull},
|
|
{"INTA" , 16, 1, 410, "RO", 0, 0, 1ull, 1ull},
|
|
{"INTB" , 17, 1, 410, "RO", 0, 0, 1ull, 1ull},
|
|
{"INTC" , 18, 1, 410, "RO", 0, 0, 1ull, 1ull},
|
|
{"INTD" , 19, 1, 410, "RO", 0, 0, 1ull, 1ull},
|
|
{"WAITL_COM" , 20, 1, 410, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_21_63" , 21, 43, 410, "RAZ", 1, 1, 0, 0},
|
|
{"WAIT_COM" , 0, 1, 411, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAR2_CAX" , 1, 1, 411, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAR2_ESX" , 2, 2, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"BAR2_ENB" , 4, 1, 411, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PTLP_RO" , 5, 1, 411, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_6_6" , 6, 1, 411, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CTLP_RO" , 7, 1, 411, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INTA_MAP" , 8, 2, 411, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTB_MAP" , 10, 2, 411, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INTC_MAP" , 12, 2, 411, "R/W", 0, 0, 2ull, 2ull},
|
|
{"INTD_MAP" , 14, 2, 411, "R/W", 0, 0, 3ull, 3ull},
|
|
{"INTA" , 16, 1, 411, "RO", 0, 0, 1ull, 1ull},
|
|
{"INTB" , 17, 1, 411, "RO", 0, 0, 1ull, 1ull},
|
|
{"INTC" , 18, 1, 411, "RO", 0, 0, 1ull, 1ull},
|
|
{"INTD" , 19, 1, 411, "RO", 0, 0, 1ull, 1ull},
|
|
{"WAITL_COM" , 20, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_21_63" , 21, 43, 411, "RAZ", 1, 1, 0, 0},
|
|
{"CHIP_REV" , 0, 8, 412, "RO", 1, 1, 0, 0},
|
|
{"HOST_MODE" , 8, 1, 412, "RO", 1, 1, 0, 0},
|
|
{"PKT_BP" , 9, 4, 412, "R/W", 0, 0, 15ull, 15ull},
|
|
{"ARB" , 13, 1, 412, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LNK_RST" , 14, 1, 412, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 412, "RAZ", 1, 1, 0, 0},
|
|
{"C0_B0_D" , 0, 1, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C0_WI_D" , 1, 1, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C1_B0_D" , 2, 1, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C1_WI_D" , 3, 1, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C0_B1_S" , 4, 3, 413, "R/W", 0, 0, 1ull, 1ull},
|
|
{"C1_B1_S" , 7, 3, 413, "R/W", 0, 0, 1ull, 1ull},
|
|
{"C0_W_FLT" , 10, 1, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C1_W_FLT" , 11, 1, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRRS" , 12, 3, 413, "R/W", 0, 0, 2ull, 2ull},
|
|
{"MPS" , 15, 1, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 413, "RAZ", 1, 1, 0, 0},
|
|
{"P0_FCNT" , 0, 6, 414, "RO", 0, 1, 0ull, 0},
|
|
{"P0_UCNT" , 6, 16, 414, "RO", 0, 1, 0ull, 0},
|
|
{"P1_FCNT" , 22, 6, 414, "RO", 0, 1, 0ull, 0},
|
|
{"P1_UCNT" , 28, 16, 414, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 414, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 17, 415, "RO", 0, 1, 0ull, 0},
|
|
{"DSEL_EXT" , 17, 1, 415, "R/W", 0, 0, 1ull, 0ull},
|
|
{"C_MUL" , 18, 5, 415, "RO", 1, 1, 0, 0},
|
|
{"QLM1_SPD" , 23, 2, 415, "RO", 1, 1, 0, 0},
|
|
{"QLM3_SPD" , 25, 2, 415, "RO", 1, 1, 0, 0},
|
|
{"QLM0_REV_LANES" , 27, 1, 415, "RO", 1, 1, 0, 0},
|
|
{"QLM2_REV_LANES" , 28, 1, 415, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 415, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_SEL" , 0, 16, 416, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 416, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 32, 417, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 7, 417, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_39_63" , 39, 25, 417, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 16, 418, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_31" , 16, 16, 418, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_6" , 0, 7, 419, "RAZ", 1, 1, 0, 0},
|
|
{"SADDR" , 7, 29, 419, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 419, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 420, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 420, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"TIME" , 32, 32, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"CNT" , 0, 32, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"TIME" , 32, 32, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA0" , 0, 32, 423, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA1" , 32, 32, 423, "R/W", 0, 1, 0ull, 0},
|
|
{"CSIZE" , 0, 14, 424, "R/W", 0, 1, 0ull, 0},
|
|
{"O_MODE" , 14, 1, 424, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O_ES" , 15, 2, 424, "R/W", 0, 1, 0ull, 0},
|
|
{"O_NS" , 17, 1, 424, "R/W", 0, 1, 0ull, 0},
|
|
{"O_RO" , 18, 1, 424, "R/W", 0, 1, 0ull, 0},
|
|
{"O_ADD1" , 19, 1, 424, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA_QUE" , 20, 3, 424, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB_ICHK" , 23, 9, 424, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB_DENB" , 32, 1, 424, "R/W", 0, 0, 0ull, 1ull},
|
|
{"B0_LEND" , 33, 1, 424, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA0_ENB" , 34, 1, 424, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1_ENB" , 35, 1, 424, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA2_ENB" , 36, 1, 424, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA3_ENB" , 37, 1, 424, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA4_ENB" , 38, 1, 424, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_39_63" , 39, 25, 424, "RAZ", 1, 1, 0, 0},
|
|
{"D4_REQST" , 0, 5, 425, "RO", 0, 1, 0ull, 0},
|
|
{"D3_REQST" , 5, 5, 425, "RO", 0, 1, 0ull, 0},
|
|
{"D2_REQST" , 10, 5, 425, "RO", 0, 1, 0ull, 0},
|
|
{"D1_REQST" , 15, 5, 425, "RO", 0, 1, 0ull, 0},
|
|
{"D0_REQST" , 20, 5, 425, "RO", 0, 1, 0ull, 0},
|
|
{"D4_DIFST" , 25, 7, 425, "RO", 0, 1, 0ull, 0},
|
|
{"D3_DIFST" , 32, 7, 425, "RO", 0, 1, 0ull, 0},
|
|
{"D2_DIFST" , 39, 7, 425, "RO", 0, 1, 0ull, 0},
|
|
{"D1_DIFST" , 46, 7, 425, "RO", 0, 1, 0ull, 0},
|
|
{"D0_DIFST" , 53, 7, 425, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 425, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"D4_DFFST" , 0, 9, 426, "RO", 0, 1, 0ull, 0},
|
|
{"D3_DFFST" , 9, 9, 426, "RO", 0, 1, 0ull, 0},
|
|
{"D2_DFFST" , 18, 9, 426, "RO", 0, 1, 0ull, 0},
|
|
{"D1_DFFST" , 27, 9, 426, "RO", 0, 1, 0ull, 0},
|
|
{"D0_DFFST" , 36, 9, 426, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_45_63" , 45, 19, 426, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"D3_DREST" , 0, 15, 427, "RO", 0, 1, 0ull, 0},
|
|
{"D2_DREST" , 15, 15, 427, "RO", 0, 1, 0ull, 0},
|
|
{"D1_DREST" , 30, 15, 427, "RO", 0, 1, 0ull, 0},
|
|
{"D0_DREST" , 45, 15, 427, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 427, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"D3_DWEST" , 0, 13, 428, "RO", 0, 1, 0ull, 0},
|
|
{"D2_DWEST" , 13, 13, 428, "RO", 0, 1, 0ull, 0},
|
|
{"D1_DWEST" , 26, 13, 428, "RO", 0, 1, 0ull, 0},
|
|
{"D0_DWEST" , 39, 13, 428, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_52_63" , 52, 12, 428, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"D4_DWEST" , 0, 13, 429, "RO", 0, 1, 0ull, 0},
|
|
{"D4_DREST" , 13, 15, 429, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_63" , 28, 36, 429, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RML_RTO" , 0, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RML_WTO" , 1, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BAR0_TO" , 2, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOB2BIG" , 3, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA0DBO" , 4, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1DBO" , 5, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA2DBO" , 6, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA3DBO" , 7, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA4DBO" , 8, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA0FI" , 9, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1FI" , 10, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DCNT0" , 11, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DCNT1" , 12, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DTIME0" , 13, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DTIME1" , 14, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSLDBOF" , 15, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PIDBOF" , 16, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCNT" , 17, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PTIME" , 18, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_AERI" , 19, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_20_20" , 20, 1, 430, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"C0_SE" , 21, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_22_22" , 22, 1, 430, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"C0_WAKE" , 23, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_PMEI" , 24, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_HPINT" , 25, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_AERI" , 26, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_27_27" , 27, 1, 430, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"C1_SE" , 28, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_29_29" , 29, 1, 430, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"C1_WAKE" , 30, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_PMEI" , 31, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_HPINT" , 32, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_B0" , 33, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_B1" , 34, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_B2" , 35, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_WI" , 36, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_BX" , 37, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_B0" , 38, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_B1" , 39, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_B2" , 40, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_WI" , 41, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_BX" , 42, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_B0" , 43, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_B1" , 44, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_B2" , 45, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_WI" , 46, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_BX" , 47, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_B0" , 48, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_B1" , 49, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_B2" , 50, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_WI" , 51, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_BX" , 52, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_WF" , 53, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_WF" , 54, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_WF" , 55, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_WF" , 56, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_EXC" , 57, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_EXC" , 58, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_LDWN" , 59, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_LDWN" , 60, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_61_62" , 61, 2, 430, "RAZ", 0, 1, 0ull, 0},
|
|
{"MIO_INTA" , 63, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RML_RTO" , 0, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RML_WTO" , 1, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BAR0_TO" , 2, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOB2BIG" , 3, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA0DBO" , 4, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1DBO" , 5, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA2DBO" , 6, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA3DBO" , 7, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA4DBO" , 8, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA0FI" , 9, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1FI" , 10, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DCNT0" , 11, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DCNT1" , 12, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DTIME0" , 13, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DTIME1" , 14, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSLDBOF" , 15, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PIDBOF" , 16, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCNT" , 17, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PTIME" , 18, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_AERI" , 19, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_20_20" , 20, 1, 431, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"C0_SE" , 21, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_22_22" , 22, 1, 431, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"C0_WAKE" , 23, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_PMEI" , 24, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_HPINT" , 25, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_AERI" , 26, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_27_27" , 27, 1, 431, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"C1_SE" , 28, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_29_29" , 29, 1, 431, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"C1_WAKE" , 30, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_PMEI" , 31, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_HPINT" , 32, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_B0" , 33, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_B1" , 34, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_B2" , 35, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_WI" , 36, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_BX" , 37, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_B0" , 38, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_B1" , 39, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_B2" , 40, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_WI" , 41, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_BX" , 42, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_B0" , 43, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_B1" , 44, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_B2" , 45, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_WI" , 46, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_BX" , 47, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_B0" , 48, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_B1" , 49, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_B2" , 50, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_WI" , 51, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_BX" , 52, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_WF" , 53, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_WF" , 54, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_WF" , 55, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_WF" , 56, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_EXC" , 57, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_EXC" , 58, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_LDWN" , 59, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_LDWN" , 60, 1, 431, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_61_63" , 61, 3, 431, "RAZ", 0, 1, 0ull, 0},
|
|
{"PSLDBOF" , 0, 6, 432, "RO", 0, 1, 0ull, 0},
|
|
{"PIDBOF" , 6, 6, 432, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_12_63" , 12, 52, 432, "RAZ", 1, 1, 0, 0},
|
|
{"RML_RTO" , 0, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RML_WTO" , 1, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BAR0_TO" , 2, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IOB2BIG" , 3, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA0DBO" , 4, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1DBO" , 5, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA2DBO" , 6, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA3DBO" , 7, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA4DBO" , 8, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA0FI" , 9, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1FI" , 10, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT0" , 11, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT1" , 12, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME0" , 13, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME1" , 14, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_18" , 15, 4, 433, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"C0_AERI" , 19, 1, 433, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 433, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"C0_SE" , 21, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_22" , 22, 1, 433, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"C0_WAKE" , 23, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_PMEI" , 24, 1, 433, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_HPINT" , 25, 1, 433, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_AERI" , 26, 1, 433, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 433, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"C1_SE" , 28, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_29" , 29, 1, 433, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"C1_WAKE" , 30, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_PMEI" , 31, 1, 433, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_HPINT" , 32, 1, 433, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_B0" , 33, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_B1" , 34, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_B2" , 35, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_WI" , 36, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_BX" , 37, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_B0" , 38, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_B1" , 39, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_B2" , 40, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_WI" , 41, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_BX" , 42, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_B0" , 43, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_B1" , 44, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_B2" , 45, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_WI" , 46, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_BX" , 47, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_B0" , 48, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_B1" , 49, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_B2" , 50, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_WI" , 51, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_BX" , 52, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_WF" , 53, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_WF" , 54, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_WF" , 55, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_WF" , 56, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_EXC" , 57, 1, 433, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_EXC" , 58, 1, 433, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_LDWN" , 59, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_LDWN" , 60, 1, 433, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_61_62" , 61, 2, 433, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO_INTA" , 63, 1, 433, "RO", 0, 0, 0ull, 0ull},
|
|
{"DATA" , 0, 64, 434, "RO", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 435, "RO", 0, 1, 0ull, 0},
|
|
{"TIMER" , 0, 10, 436, "R/W", 0, 0, 0ull, 50ull},
|
|
{"MAX_WORD" , 10, 4, 436, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 436, "RAZ", 1, 1, 0, 0},
|
|
{"BA" , 0, 30, 437, "R/W", 0, 1, 0ull, 0},
|
|
{"ROW" , 30, 1, 437, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR" , 31, 1, 437, "R/W", 0, 1, 0ull, 0},
|
|
{"NSW" , 32, 1, 437, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR" , 33, 1, 437, "R/W", 0, 1, 0ull, 0},
|
|
{"ESW" , 34, 2, 437, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR" , 36, 2, 437, "R/W", 0, 1, 0ull, 0},
|
|
{"NMERGE" , 38, 1, 437, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PORT" , 39, 2, 437, "R/W", 0, 1, 0ull, 0},
|
|
{"ZERO" , 41, 1, 437, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_42_63" , 42, 22, 437, "RAZ", 1, 1, 0, 0},
|
|
{"ENB" , 0, 64, 438, "R/W", 0, 0, 0ull, 18446744073709551615ull},
|
|
{"ENB" , 0, 64, 439, "R/W", 0, 0, 0ull, 18446744073709551615ull},
|
|
{"ENB" , 0, 64, 440, "R/W", 0, 0, 0ull, 18446744073709551615ull},
|
|
{"ENB" , 0, 64, 441, "R/W", 0, 0, 0ull, 18446744073709551615ull},
|
|
{"INTR" , 0, 64, 442, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTR" , 0, 64, 443, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTR" , 0, 64, 444, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTR" , 0, 64, 445, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_INT" , 0, 8, 446, "R/W", 0, 1, 0ull, 0},
|
|
{"RD_INT" , 8, 8, 446, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 446, "RAZ", 1, 1, 0, 0},
|
|
{"MSI_INT" , 0, 8, 447, "R/W", 0, 1, 0ull, 0},
|
|
{"CIU_INT" , 8, 8, 447, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 447, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 0, 8, 448, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 448, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 449, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 8, 8, 449, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 449, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_15" , 0, 16, 450, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 16, 8, 450, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_24_63" , 24, 40, 450, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_23" , 0, 24, 451, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 24, 8, 451, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 451, "RAZ", 1, 1, 0, 0},
|
|
{"MIO" , 0, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX0" , 1, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX1" , 2, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPEI" , 3, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"KEY" , 4, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPA" , 5, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"DFA" , 6, 1, 452, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ZIP" , 7, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_8" , 8, 1, 452, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IPD" , 9, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 10, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"TIM" , 11, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"POW" , 12, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"USB" , 13, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"RAD" , 14, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"USB1" , 15, 1, 452, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"L2C" , 16, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"LMC0" , 17, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"SPX0" , 18, 1, 452, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SPX1" , 19, 1, 452, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PIP" , 20, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_21" , 21, 1, 452, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ASXPCS0" , 22, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASXPCS1" , 23, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_27" , 24, 4, 452, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"AGL" , 28, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"LMC1" , 29, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"IOB" , 30, 1, 452, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 452, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DATA" , 0, 64, 453, "R/W", 0, 1, 0ull, 0},
|
|
{"CSR" , 0, 39, 454, "RO", 0, 1, 1ull, 0},
|
|
{"ARB" , 39, 1, 454, "RO", 0, 1, 0ull, 0},
|
|
{"CPL0" , 40, 12, 454, "RO", 0, 1, 1ull, 0},
|
|
{"CPL1" , 52, 12, 454, "RO", 0, 1, 1ull, 0},
|
|
{"NND" , 0, 8, 455, "RO", 0, 1, 1ull, 0},
|
|
{"NNP0" , 8, 8, 455, "RO", 0, 1, 1ull, 0},
|
|
{"CSM0" , 16, 15, 455, "RO", 0, 1, 1ull, 0},
|
|
{"CSM1" , 31, 15, 455, "RO", 0, 1, 1ull, 0},
|
|
{"RAC" , 46, 1, 455, "RO", 0, 1, 1ull, 0},
|
|
{"NPEI" , 47, 1, 455, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 455, "RAZ", 1, 1, 0, 0},
|
|
{"NSM0" , 0, 13, 456, "RO", 0, 1, 1ull, 0},
|
|
{"NSM1" , 13, 13, 456, "RO", 0, 1, 1ull, 0},
|
|
{"PSM0" , 26, 15, 456, "RO", 0, 1, 1ull, 0},
|
|
{"PSM1" , 41, 15, 456, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_56_63" , 56, 8, 456, "RAZ", 1, 1, 0, 0},
|
|
{"RD_ADDR" , 0, 48, 457, "R/W", 0, 1, 0ull, 0},
|
|
{"IOBIT" , 48, 1, 457, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LD_CMD" , 49, 2, 457, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_51_63" , 51, 13, 457, "RAZ", 1, 1, 0, 0},
|
|
{"RD_DATA" , 0, 64, 458, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_0_1" , 0, 2, 459, "RAZ", 1, 1, 0, 0},
|
|
{"WR_ADDR" , 2, 46, 459, "R/W", 0, 1, 0ull, 0},
|
|
{"IOBIT" , 48, 1, 459, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 459, "RAZ", 1, 1, 0, 0},
|
|
{"WR_DATA" , 0, 64, 460, "R/W", 0, 1, 0ull, 0},
|
|
{"WR_MASK" , 0, 8, 461, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 461, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 32, 462, "R/W", 0, 0, 0ull, 2097152ull},
|
|
{"RESERVED_32_63" , 32, 32, 462, "RAZ", 1, 1, 0, 0},
|
|
{"VENDID" , 0, 16, 463, "RO/WRSL", 0, 0, 6013ull, 6013ull},
|
|
{"DEVID" , 16, 16, 463, "RO/WRSL", 0, 0, 80ull, 80ull},
|
|
{"ISAE" , 0, 1, 464, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSAE" , 1, 1, 464, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ME" , 2, 1, 464, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SCSE" , 3, 1, 464, "RO", 0, 0, 0ull, 0ull},
|
|
{"MWICE" , 4, 1, 464, "RO", 0, 0, 0ull, 0ull},
|
|
{"VPS" , 5, 1, 464, "RO", 0, 0, 0ull, 0ull},
|
|
{"PER" , 6, 1, 464, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDS_WCC" , 7, 1, 464, "RO", 0, 0, 0ull, 0ull},
|
|
{"SEE" , 8, 1, 464, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FBBE" , 9, 1, 464, "RO", 0, 0, 0ull, 0ull},
|
|
{"I_DIS" , 10, 1, 464, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_18" , 11, 8, 464, "RAZ", 1, 1, 0, 0},
|
|
{"I_STAT" , 19, 1, 464, "RO", 0, 0, 0ull, 0ull},
|
|
{"CL" , 20, 1, 464, "RO", 0, 0, 1ull, 1ull},
|
|
{"M66" , 21, 1, 464, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_22" , 22, 1, 464, "RAZ", 1, 1, 0, 0},
|
|
{"FBB" , 23, 1, 464, "RO", 0, 0, 0ull, 0ull},
|
|
{"MDPE" , 24, 1, 464, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DEVT" , 25, 2, 464, "RO", 0, 0, 0ull, 0ull},
|
|
{"STA" , 27, 1, 464, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTA" , 28, 1, 464, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RMA" , 29, 1, 464, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SSE" , 30, 1, 464, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPE" , 31, 1, 464, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RID" , 0, 8, 465, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PI" , 8, 8, 465, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"SC" , 16, 8, 465, "RO/WRSL", 0, 0, 48ull, 48ull},
|
|
{"BCC" , 24, 8, 465, "RO/WRSL", 0, 0, 11ull, 11ull},
|
|
{"CLS" , 0, 8, 466, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LT" , 8, 8, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"CHF" , 16, 7, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"MFD" , 23, 1, 466, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"BIST" , 24, 8, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSPC" , 0, 1, 467, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 467, "RO/WRSL", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 467, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_13" , 4, 10, 467, "RAZ", 1, 1, 0, 0},
|
|
{"LBAB" , 14, 18, 467, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 0, 1, 468, "WORSL", 0, 0, 1ull, 1ull},
|
|
{"LMASK" , 1, 31, 468, "WORSL", 0, 0, 8191ull, 8191ull},
|
|
{"UBAB" , 0, 32, 469, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMASK" , 0, 32, 470, "WORSL", 0, 0, 0ull, 0ull},
|
|
{"MSPC" , 0, 1, 471, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 471, "RO/WRSL", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 471, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_25" , 4, 22, 471, "RAZ", 1, 1, 0, 0},
|
|
{"LBAB" , 26, 6, 471, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 0, 1, 472, "WORSL", 0, 0, 1ull, 1ull},
|
|
{"LMASK" , 1, 31, 472, "WORSL", 0, 0, 33554431ull, 33554431ull},
|
|
{"UBAB" , 0, 32, 473, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMASK" , 0, 32, 474, "WORSL", 0, 0, 0ull, 0ull},
|
|
{"MSPC" , 0, 1, 475, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 475, "RO/WRSL", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 475, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_31" , 4, 28, 475, "RAZ", 1, 1, 0, 0},
|
|
{"ENB" , 0, 1, 476, "WORSL", 0, 0, 1ull, 1ull},
|
|
{"LMASK" , 1, 31, 476, "WORSL", 0, 0, 2147483647ull, 2147483647ull},
|
|
{"RESERVED_0_6" , 0, 7, 477, "RAZ", 1, 1, 0, 0},
|
|
{"UBAB" , 7, 25, 477, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMASK" , 0, 32, 478, "WORSL", 0, 0, 127ull, 127ull},
|
|
{"CISP" , 0, 32, 479, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"SSVID" , 0, 16, 480, "RO/WRSL", 0, 0, 6013ull, 6013ull},
|
|
{"SSID" , 16, 16, 480, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"ER_EN" , 0, 1, 481, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_15" , 1, 15, 481, "RAZ", 1, 1, 0, 0},
|
|
{"ERADDR" , 16, 16, 481, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 0, 1, 482, "WORSL", 0, 0, 1ull, 1ull},
|
|
{"MASK" , 1, 31, 482, "WORSL", 0, 0, 2147483647ull, 2147483647ull},
|
|
{"CP" , 0, 8, 483, "RO/WRSL", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_8_31" , 8, 24, 483, "RAZ", 1, 1, 0, 0},
|
|
{"IL" , 0, 8, 484, "R/W", 0, 0, 255ull, 255ull},
|
|
{"INTA" , 8, 8, 484, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"MG" , 16, 8, 484, "RO", 0, 0, 0ull, 0ull},
|
|
{"ML" , 24, 8, 484, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMCID" , 0, 8, 485, "RO", 0, 0, 1ull, 0ull},
|
|
{"NCP" , 8, 8, 485, "RO/WRSL", 0, 0, 80ull, 0ull},
|
|
{"PMSV" , 16, 3, 485, "RO/WRSL", 0, 0, 3ull, 0ull},
|
|
{"PME_CLOCK" , 19, 1, 485, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 485, "RAZ", 1, 1, 0, 0},
|
|
{"DSI" , 21, 1, 485, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"AUXC" , 22, 3, 485, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"D1S" , 25, 1, 485, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"D2S" , 26, 1, 485, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PMES" , 27, 5, 485, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PS" , 0, 2, 486, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 486, "RAZ", 1, 1, 0, 0},
|
|
{"NSR" , 3, 1, 486, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 486, "RAZ", 1, 1, 0, 0},
|
|
{"PMEENS" , 8, 1, 486, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMDS" , 9, 4, 486, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMEDSIA" , 13, 2, 486, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMESS" , 15, 1, 486, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_21" , 16, 6, 486, "RAZ", 1, 1, 0, 0},
|
|
{"BD3H" , 22, 1, 486, "RO", 0, 0, 0ull, 0ull},
|
|
{"BPCCEE" , 23, 1, 486, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMDIA" , 24, 8, 486, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSICID" , 0, 8, 487, "RO", 0, 0, 5ull, 5ull},
|
|
{"NCP" , 8, 8, 487, "RO/WRSL", 0, 0, 112ull, 112ull},
|
|
{"MSIEN" , 16, 1, 487, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MMC" , 17, 3, 487, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"MME" , 20, 3, 487, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M64" , 23, 1, 487, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_24_31" , 24, 8, 487, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 488, "RAZ", 1, 1, 0, 0},
|
|
{"LMSI" , 2, 30, 488, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSI" , 0, 32, 489, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSIMD" , 0, 16, 490, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_31" , 16, 16, 490, "RAZ", 1, 1, 0, 0},
|
|
{"PCIEID" , 0, 8, 491, "RO", 0, 0, 16ull, 16ull},
|
|
{"NCP" , 8, 8, 491, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PCIECV" , 16, 4, 491, "RO", 0, 0, 2ull, 2ull},
|
|
{"DPT" , 20, 4, 491, "RO", 0, 0, 0ull, 0ull},
|
|
{"SI" , 24, 1, 491, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"IMN" , 25, 5, 491, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_31" , 30, 2, 491, "RAZ", 1, 1, 0, 0},
|
|
{"MPSS" , 0, 3, 492, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"PFS" , 3, 2, 492, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"ETFS" , 5, 1, 492, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"EL0AL" , 6, 3, 492, "RO/WRSL", 0, 0, 4ull, 4ull},
|
|
{"EL1AL" , 9, 3, 492, "RO/WRSL", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_12_14" , 12, 3, 492, "RAZ", 1, 1, 0, 0},
|
|
{"RBER" , 15, 1, 492, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_16_17" , 16, 2, 492, "RAZ", 1, 1, 0, 0},
|
|
{"CSPLV" , 18, 8, 492, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSPLS" , 26, 2, 492, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_31" , 28, 4, 492, "RAZ", 1, 1, 0, 0},
|
|
{"CE_EN" , 0, 1, 493, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NFE_EN" , 1, 1, 493, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FE_EN" , 2, 1, 493, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UR_EN" , 3, 1, 493, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RO_EN" , 4, 1, 493, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MPS" , 5, 3, 493, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ETF_EN" , 8, 1, 493, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PF_EN" , 9, 1, 493, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AP_EN" , 10, 1, 493, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NS_EN" , 11, 1, 493, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MRRS" , 12, 3, 493, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_15_15" , 15, 1, 493, "RAZ", 1, 1, 0, 0},
|
|
{"CE_D" , 16, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NFE_D" , 17, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FE_D" , 18, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UR_D" , 19, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AP_D" , 20, 1, 493, "RO", 0, 0, 0ull, 0ull},
|
|
{"TP" , 21, 1, 493, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_31" , 22, 10, 493, "RAZ", 1, 1, 0, 0},
|
|
{"MLS" , 0, 4, 494, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"MLW" , 4, 6, 494, "RO/WRSL", 0, 0, 8ull, 8ull},
|
|
{"ASLPMS" , 10, 2, 494, "RO/WRSL", 0, 0, 3ull, 3ull},
|
|
{"L0EL" , 12, 3, 494, "RO/WRSL", 0, 0, 6ull, 6ull},
|
|
{"L1EL" , 15, 3, 494, "RO/WRSL", 0, 0, 6ull, 6ull},
|
|
{"CPM" , 18, 1, 494, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"SDERC" , 19, 1, 494, "RO", 0, 0, 0ull, 0ull},
|
|
{"DLLARC" , 20, 1, 494, "RO", 0, 0, 0ull, 0ull},
|
|
{"LBNC" , 21, 1, 494, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 494, "RAZ", 1, 1, 0, 0},
|
|
{"PNUM" , 24, 8, 494, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"ASLPC" , 0, 2, 495, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 495, "RAZ", 1, 1, 0, 0},
|
|
{"RCB" , 3, 1, 495, "RO", 0, 0, 0ull, 0ull},
|
|
{"LD" , 4, 1, 495, "RO", 0, 0, 0ull, 0ull},
|
|
{"RL" , 5, 1, 495, "RO", 0, 0, 0ull, 0ull},
|
|
{"CCC" , 6, 1, 495, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ES" , 7, 1, 495, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECPM" , 8, 1, 495, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HAWD" , 9, 1, 495, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_15" , 10, 6, 495, "RAZ", 1, 1, 0, 0},
|
|
{"LS" , 16, 4, 495, "RO", 0, 0, 1ull, 1ull},
|
|
{"NLW" , 20, 6, 495, "RO", 0, 0, 0ull, 8ull},
|
|
{"RESERVED_26_26" , 26, 1, 495, "RAZ", 1, 1, 0, 0},
|
|
{"LT" , 27, 1, 495, "RO", 0, 0, 0ull, 0ull},
|
|
{"SCC" , 28, 1, 495, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"DLLA" , 29, 1, 495, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_31" , 30, 2, 495, "RAZ", 1, 1, 0, 0},
|
|
{"ABP" , 0, 1, 496, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PCP" , 1, 1, 496, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"MRLSP" , 2, 1, 496, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"AIP" , 3, 1, 496, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PIP" , 4, 1, 496, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"HP_S" , 5, 1, 496, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"HP_C" , 6, 1, 496, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"SP_LV" , 7, 8, 496, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"SP_LS" , 15, 2, 496, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"EMIP" , 17, 1, 496, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"NCCS" , 18, 1, 496, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PS_NUM" , 19, 13, 496, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"ABP_EN" , 0, 1, 497, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PF_EN" , 1, 1, 497, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRLS_EN" , 2, 1, 497, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PD_EN" , 3, 1, 497, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CCINT_EN" , 4, 1, 497, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HPINT_EN" , 5, 1, 497, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AIC" , 6, 2, 497, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PIC" , 8, 2, 497, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCC" , 10, 1, 497, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EMIC" , 11, 1, 497, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLLS_EN" , 12, 1, 497, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 497, "RAZ", 1, 1, 0, 0},
|
|
{"ABP_D" , 16, 1, 497, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PF_D" , 17, 1, 497, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRLS_C" , 18, 1, 497, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PD_C" , 19, 1, 497, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CCINT_D" , 20, 1, 497, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRLSS" , 21, 1, 497, "RO", 0, 0, 0ull, 0ull},
|
|
{"PDS" , 22, 1, 497, "RO", 0, 0, 0ull, 0ull},
|
|
{"EMIS" , 23, 1, 497, "RO", 0, 0, 0ull, 0ull},
|
|
{"DLLS_C" , 24, 1, 497, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_31" , 25, 7, 497, "RAZ", 1, 1, 0, 0},
|
|
{"CTRS" , 0, 4, 498, "RO", 0, 0, 0ull, 0ull},
|
|
{"CTDS" , 4, 1, 498, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_5_31" , 5, 27, 498, "RAZ", 1, 1, 0, 0},
|
|
{"CTV" , 0, 4, 499, "RO", 0, 0, 0ull, 0ull},
|
|
{"CTD" , 4, 1, 499, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 499, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 500, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 501, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 502, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 503, "RAZ", 1, 1, 0, 0},
|
|
{"PCIEEC" , 0, 16, 504, "RO", 0, 0, 1ull, 0ull},
|
|
{"CV" , 16, 4, 504, "RO", 0, 0, 1ull, 0ull},
|
|
{"NCO" , 20, 12, 504, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_3" , 0, 4, 505, "RAZ", 1, 1, 0, 0},
|
|
{"DLPES" , 4, 1, 505, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SDES" , 5, 1, 505, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_11" , 6, 6, 505, "RAZ", 1, 1, 0, 0},
|
|
{"PTLPS" , 12, 1, 505, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCPES" , 13, 1, 505, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CTS" , 14, 1, 505, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CAS" , 15, 1, 505, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UCS" , 16, 1, 505, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ROS" , 17, 1, 505, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MTLPS" , 18, 1, 505, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ECRCES" , 19, 1, 505, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"URES" , 20, 1, 505, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 505, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_3" , 0, 4, 506, "RAZ", 1, 1, 0, 0},
|
|
{"DLPEM" , 4, 1, 506, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SDEM" , 5, 1, 506, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_11" , 6, 6, 506, "RAZ", 1, 1, 0, 0},
|
|
{"PTLPM" , 12, 1, 506, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCPEM" , 13, 1, 506, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CTM" , 14, 1, 506, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAM" , 15, 1, 506, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UCM" , 16, 1, 506, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROM" , 17, 1, 506, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MTLPM" , 18, 1, 506, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECRCEM" , 19, 1, 506, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UREM" , 20, 1, 506, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 506, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_3" , 0, 4, 507, "RAZ", 1, 1, 0, 0},
|
|
{"DLPES" , 4, 1, 507, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SDES" , 5, 1, 507, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_11" , 6, 6, 507, "RAZ", 1, 1, 0, 0},
|
|
{"PTLPS" , 12, 1, 507, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCPES" , 13, 1, 507, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTS" , 14, 1, 507, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAS" , 15, 1, 507, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UCS" , 16, 1, 507, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROS" , 17, 1, 507, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MTLPS" , 18, 1, 507, "R/W", 0, 0, 1ull, 1ull},
|
|
{"ECRCES" , 19, 1, 507, "R/W", 0, 0, 0ull, 0ull},
|
|
{"URES" , 20, 1, 507, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 507, "RAZ", 1, 1, 0, 0},
|
|
{"RES" , 0, 1, 508, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_5" , 1, 5, 508, "RAZ", 1, 1, 0, 0},
|
|
{"BTLPS" , 6, 1, 508, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BDLLPS" , 7, 1, 508, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RNRS" , 8, 1, 508, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 508, "RAZ", 1, 1, 0, 0},
|
|
{"RTTS" , 12, 1, 508, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ANFES" , 13, 1, 508, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_31" , 14, 18, 508, "RAZ", 1, 1, 0, 0},
|
|
{"REM" , 0, 1, 509, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_5" , 1, 5, 509, "RAZ", 1, 1, 0, 0},
|
|
{"BTLPM" , 6, 1, 509, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BDLLPM" , 7, 1, 509, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNRM" , 8, 1, 509, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 509, "RAZ", 1, 1, 0, 0},
|
|
{"RTTM" , 12, 1, 509, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ANFEM" , 13, 1, 509, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_14_31" , 14, 18, 509, "RAZ", 1, 1, 0, 0},
|
|
{"FEP" , 0, 5, 510, "RO", 0, 0, 0ull, 0ull},
|
|
{"GC" , 5, 1, 510, "RO", 0, 0, 1ull, 1ull},
|
|
{"GE" , 6, 1, 510, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CC" , 7, 1, 510, "RO", 0, 0, 1ull, 1ull},
|
|
{"CE" , 8, 1, 510, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_31" , 9, 23, 510, "RAZ", 1, 1, 0, 0},
|
|
{"DWORD1" , 0, 32, 511, "RO", 0, 0, 0ull, 0ull},
|
|
{"DWORD2" , 0, 32, 512, "RO", 0, 0, 0ull, 0ull},
|
|
{"DWORD3" , 0, 32, 513, "RO", 0, 0, 0ull, 0ull},
|
|
{"DWORD4" , 0, 32, 514, "RO", 0, 0, 0ull, 0ull},
|
|
{"RTLTL" , 0, 16, 515, "R/W", 0, 0, 4143ull, 4143ull},
|
|
{"RTL" , 16, 16, 515, "R/W", 0, 0, 12429ull, 12429ull},
|
|
{"OMR" , 0, 32, 516, "R/W", 0, 1, 4294967295ull, 0},
|
|
{"LINK_NUM" , 0, 8, 517, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_14" , 8, 7, 517, "RAZ", 1, 1, 0, 0},
|
|
{"FORCE_LINK" , 15, 1, 517, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LINK_STATE" , 16, 6, 517, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 517, "RAZ", 1, 1, 0, 0},
|
|
{"LPEC" , 24, 8, 517, "R/W", 0, 0, 7ull, 7ull},
|
|
{"ACK_FREQ" , 0, 8, 518, "R/W", 0, 0, 0ull, 0ull},
|
|
{"N_FTS" , 8, 8, 518, "R/W", 0, 0, 128ull, 128ull},
|
|
{"N_FTS_CC" , 16, 8, 518, "R/W", 0, 0, 128ull, 128ull},
|
|
{"L0EL" , 24, 3, 518, "R/W", 0, 0, 3ull, 3ull},
|
|
{"L1EL" , 27, 3, 518, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_30_31" , 30, 2, 518, "RAZ", 1, 1, 0, 0},
|
|
{"OMR" , 0, 1, 519, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SD" , 1, 1, 519, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LE" , 2, 1, 519, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RA" , 3, 1, 519, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_4" , 4, 1, 519, "RAZ", 1, 1, 0, 0},
|
|
{"DLLLE" , 5, 1, 519, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_6" , 6, 1, 519, "RAZ", 1, 1, 0, 0},
|
|
{"FLM" , 7, 1, 519, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_15" , 8, 8, 519, "RO", 0, 0, 1ull, 1ull},
|
|
{"LME" , 16, 6, 519, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_22_24" , 22, 3, 519, "RAZ", 1, 1, 0, 0},
|
|
{"ECCRC" , 25, 1, 519, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_31" , 26, 6, 519, "RAZ", 1, 1, 0, 0},
|
|
{"ILST" , 0, 24, 520, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCD" , 24, 1, 520, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ACK_NAK" , 25, 1, 520, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_30" , 26, 5, 520, "RAZ", 1, 1, 0, 0},
|
|
{"DLLD" , 31, 1, 520, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NTSS" , 0, 4, 521, "R/W", 0, 0, 10ull, 10ull},
|
|
{"RESERVED_4_7" , 4, 4, 521, "RO", 1, 1, 0, 0},
|
|
{"NSKPS" , 8, 3, 521, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_11_13" , 11, 3, 521, "RAZ", 1, 1, 0, 0},
|
|
{"TMRT" , 14, 5, 521, "R/W", 0, 0, 8ull, 8ull},
|
|
{"TMANLT" , 19, 5, 521, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TMFCWT" , 24, 5, 521, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_31" , 29, 3, 521, "RO", 1, 1, 0, 0},
|
|
{"SKPIV" , 0, 11, 522, "R/W", 0, 0, 1280ull, 1280ull},
|
|
{"RESERVED_11_14" , 11, 4, 522, "RAZ", 1, 1, 0, 0},
|
|
{"DFCWT" , 15, 1, 522, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_FUN" , 16, 1, 522, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_POIS_FILT" , 17, 1, 522, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_BAR_MATCH" , 18, 1, 522, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CFG1_FILT" , 19, 1, 522, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_LK_FILT" , 20, 1, 522, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_TAG_ERR" , 21, 1, 522, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_RID_ERR" , 22, 1, 522, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_FUN_ERR" , 23, 1, 522, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_TC_ERR" , 24, 1, 522, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_ATTR_ERR" , 25, 1, 522, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_LEN_ERR" , 26, 1, 522, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_ECRC_FILT" , 27, 1, 522, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_ECRC_FILT" , 28, 1, 522, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSG_CTRL" , 29, 1, 522, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_IO_FILT" , 30, 1, 522, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CFG0_FILT" , 31, 1, 522, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_VEND0_DRP" , 0, 1, 523, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_VEND1_DRP" , 1, 1, 523, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_31" , 2, 30, 523, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_INFO_L32" , 0, 32, 524, "RO", 0, 0, 0ull, 0ull},
|
|
{"DBG_INFO_U32" , 0, 32, 525, "RO", 0, 0, 0ull, 0ull},
|
|
{"TPDFCC" , 0, 12, 526, "RO", 0, 0, 0ull, 0ull},
|
|
{"TPHFCC" , 12, 8, 526, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 526, "RAZ", 1, 1, 0, 0},
|
|
{"TCDFCC" , 0, 12, 527, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCHFCC" , 12, 8, 527, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 527, "RAZ", 1, 1, 0, 0},
|
|
{"TCDFCC" , 0, 12, 528, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCHFCC" , 12, 8, 528, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 528, "RAZ", 1, 1, 0, 0},
|
|
{"RTLPFCCNR" , 0, 1, 529, "RO", 0, 0, 0ull, 0ull},
|
|
{"TRBNE" , 1, 1, 529, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQNE" , 2, 1, 529, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_31" , 3, 29, 529, "RAZ", 1, 1, 0, 0},
|
|
{"WRR_VC0" , 0, 8, 530, "RO", 0, 0, 15ull, 15ull},
|
|
{"WRR_VC1" , 8, 8, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC2" , 16, 8, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC3" , 24, 8, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC4" , 0, 8, 531, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC5" , 8, 8, 531, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC6" , 16, 8, 531, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC7" , 24, 8, 531, "RO", 0, 0, 0ull, 0ull},
|
|
{"DATA_CREDITS" , 0, 12, 532, "RO/WRSL", 0, 0, 72ull, 72ull},
|
|
{"HEADER_CREDITS" , 12, 8, 532, "RO/WRSL", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_20_20" , 20, 1, 532, "RAZ", 1, 1, 0, 0},
|
|
{"QUEUE_MODE" , 21, 3, 532, "RO/WRSL", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_24_29" , 24, 6, 532, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE_ORDERING" , 30, 1, 532, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"RX_QUEUE_ORDER" , 31, 1, 532, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"DATA_CREDITS" , 0, 12, 533, "RO/WRSL", 0, 0, 4ull, 4ull},
|
|
{"HEADER_CREDITS" , 12, 8, 533, "RO/WRSL", 0, 0, 8ull, 8ull},
|
|
{"RESERVED_20_20" , 20, 1, 533, "RAZ", 1, 1, 0, 0},
|
|
{"QUEUE_MODE" , 21, 3, 533, "RO/WRSL", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_24_31" , 24, 8, 533, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_CREDITS" , 0, 12, 534, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"HEADER_CREDITS" , 12, 8, 534, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 534, "RAZ", 1, 1, 0, 0},
|
|
{"QUEUE_MODE" , 21, 3, 534, "RO/WRSL", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_24_31" , 24, 8, 534, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_DEPTH" , 0, 14, 535, "RO/WRSL", 0, 0, 216ull, 216ull},
|
|
{"RESERVED_14_15" , 14, 2, 535, "RAZ", 1, 1, 0, 0},
|
|
{"HEADER_DEPTH" , 16, 10, 535, "RO/WRSL", 0, 0, 38ull, 38ull},
|
|
{"RESERVED_26_31" , 26, 6, 535, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_DEPTH" , 0, 14, 536, "RO/WRSL", 0, 0, 56ull, 56ull},
|
|
{"RESERVED_14_15" , 14, 2, 536, "RAZ", 1, 1, 0, 0},
|
|
{"HEADER_DEPTH" , 16, 10, 536, "RO/WRSL", 0, 0, 14ull, 14ull},
|
|
{"RESERVED_26_31" , 26, 6, 536, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_DEPTH" , 0, 14, 537, "RO/WRSL", 0, 0, 360ull, 360ull},
|
|
{"RESERVED_14_15" , 14, 2, 537, "RAZ", 1, 1, 0, 0},
|
|
{"HEADER_DEPTH" , 16, 10, 537, "RO/WRSL", 0, 0, 70ull, 70ull},
|
|
{"RESERVED_26_31" , 26, 6, 537, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_STAT" , 0, 32, 538, "RO", 0, 0, 0ull, 0ull},
|
|
{"PHY_CTRL" , 0, 32, 539, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VENDID" , 0, 16, 540, "R/W", 0, 0, 6013ull, 6013ull},
|
|
{"DEVID" , 16, 16, 540, "R/W", 0, 0, 80ull, 80ull},
|
|
{"ISAE" , 0, 1, 541, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSAE" , 1, 1, 541, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ME" , 2, 1, 541, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SCSE" , 3, 1, 541, "RO", 0, 0, 0ull, 0ull},
|
|
{"MWICE" , 4, 1, 541, "RO", 0, 0, 0ull, 0ull},
|
|
{"VPS" , 5, 1, 541, "RO", 0, 0, 0ull, 0ull},
|
|
{"PER" , 6, 1, 541, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDS_WCC" , 7, 1, 541, "RO", 0, 0, 0ull, 0ull},
|
|
{"SEE" , 8, 1, 541, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FBBE" , 9, 1, 541, "RO", 0, 0, 0ull, 0ull},
|
|
{"I_DIS" , 10, 1, 541, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_18" , 11, 8, 541, "RAZ", 1, 1, 0, 0},
|
|
{"I_STAT" , 19, 1, 541, "RO", 0, 0, 0ull, 0ull},
|
|
{"CL" , 20, 1, 541, "RO", 0, 0, 1ull, 1ull},
|
|
{"M66" , 21, 1, 541, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_22" , 22, 1, 541, "RO", 1, 1, 0, 0},
|
|
{"FBB" , 23, 1, 541, "RO", 0, 0, 0ull, 0ull},
|
|
{"MDPE" , 24, 1, 541, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DEVT" , 25, 2, 541, "RO", 0, 0, 0ull, 0ull},
|
|
{"STA" , 27, 1, 541, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTA" , 28, 1, 541, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RMA" , 29, 1, 541, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SSE" , 30, 1, 541, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPE" , 31, 1, 541, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RID" , 0, 8, 542, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PI" , 8, 8, 542, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SC" , 16, 8, 542, "R/W", 0, 0, 48ull, 48ull},
|
|
{"BCC" , 24, 8, 542, "R/W", 0, 0, 11ull, 11ull},
|
|
{"CLS" , 0, 8, 543, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LT" , 8, 8, 543, "RO", 0, 0, 0ull, 0ull},
|
|
{"CHF" , 16, 7, 543, "RO", 0, 0, 1ull, 1ull},
|
|
{"MFD" , 23, 1, 543, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BIST" , 24, 8, 543, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_31" , 0, 32, 544, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 545, "RO", 1, 1, 0, 0},
|
|
{"PBNUM" , 0, 8, 546, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SBNUM" , 8, 8, 546, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SUBBNUM" , 16, 8, 546, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SLT" , 24, 8, 546, "RO", 0, 0, 0ull, 0ull},
|
|
{"IO32A" , 0, 1, 547, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_3" , 1, 3, 547, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LIO_BASE" , 4, 4, 547, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IO32B" , 8, 1, 547, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_9_11" , 9, 3, 547, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LIO_LIMI" , 12, 4, 547, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_20" , 16, 5, 547, "RAZ", 1, 1, 0, 0},
|
|
{"M66" , 21, 1, 547, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_22" , 22, 1, 547, "RO", 1, 1, 0, 0},
|
|
{"FBB" , 23, 1, 547, "RO", 0, 0, 0ull, 0ull},
|
|
{"MDPE" , 24, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DEVT" , 25, 2, 547, "RO", 0, 0, 0ull, 0ull},
|
|
{"STA" , 27, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTA" , 28, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RMA" , 29, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SSE" , 30, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPE" , 31, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_3" , 0, 4, 548, "RO", 1, 1, 0, 0},
|
|
{"MB_ADDR" , 4, 12, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_19" , 16, 4, 548, "RO", 1, 1, 0, 0},
|
|
{"ML_ADDR" , 20, 12, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM64A" , 0, 1, 549, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_3" , 1, 3, 549, "RO", 1, 1, 0, 0},
|
|
{"LMEM_BASE" , 4, 12, 549, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM64B" , 16, 1, 549, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_17_19" , 17, 3, 549, "RO", 1, 1, 0, 0},
|
|
{"LMEM_LIMIT" , 20, 12, 549, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMEM_BASE" , 0, 32, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMEM_LIMIT" , 0, 32, 551, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UIO_BASE" , 0, 16, 552, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UIO_LIMIT" , 16, 16, 552, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP" , 0, 8, 553, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_8_31" , 8, 24, 553, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 554, "RAZ", 1, 1, 0, 0},
|
|
{"IL" , 0, 8, 555, "R/W", 0, 0, 255ull, 255ull},
|
|
{"INTA" , 8, 8, 555, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PERE" , 16, 1, 555, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SEE" , 17, 1, 555, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ISAE" , 18, 1, 555, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VGAE" , 19, 1, 555, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VGA16D" , 20, 1, 555, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAM" , 21, 1, 555, "RO", 0, 0, 0ull, 0ull},
|
|
{"SBRST" , 22, 1, 555, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FBBE" , 23, 1, 555, "RO", 0, 0, 0ull, 0ull},
|
|
{"PDT" , 24, 1, 555, "RO", 0, 0, 0ull, 0ull},
|
|
{"SDT" , 25, 1, 555, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTS" , 26, 1, 555, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTSEES" , 27, 1, 555, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_31" , 28, 4, 555, "RO", 1, 1, 0, 0},
|
|
{"PMCID" , 0, 8, 556, "RO", 0, 0, 1ull, 1ull},
|
|
{"NCP" , 8, 8, 556, "R/W", 0, 0, 80ull, 80ull},
|
|
{"PMSV" , 16, 3, 556, "R/W", 0, 0, 3ull, 3ull},
|
|
{"PME_CLOCK" , 19, 1, 556, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 556, "RAZ", 1, 1, 0, 0},
|
|
{"DSI" , 21, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AUXC" , 22, 3, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"D1S" , 25, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"D2S" , 26, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMES" , 27, 5, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PS" , 0, 2, 557, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 557, "RAZ", 1, 1, 0, 0},
|
|
{"NSR" , 3, 1, 557, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 557, "RAZ", 1, 1, 0, 0},
|
|
{"PMEENS" , 8, 1, 557, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMDS" , 9, 4, 557, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMEDSIA" , 13, 2, 557, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMESS" , 15, 1, 557, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_21" , 16, 6, 557, "RAZ", 1, 1, 0, 0},
|
|
{"BD3H" , 22, 1, 557, "RO", 0, 0, 0ull, 0ull},
|
|
{"BPCCEE" , 23, 1, 557, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMDIA" , 24, 8, 557, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSICID" , 0, 8, 558, "RO", 0, 0, 5ull, 5ull},
|
|
{"NCP" , 8, 8, 558, "R/W", 0, 0, 112ull, 112ull},
|
|
{"MSIEN" , 16, 1, 558, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MMC" , 17, 3, 558, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MME" , 20, 3, 558, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M64" , 23, 1, 558, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_24_31" , 24, 8, 558, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 559, "RAZ", 1, 1, 0, 0},
|
|
{"LMSI" , 2, 30, 559, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSI" , 0, 32, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSIMD" , 0, 16, 561, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_31" , 16, 16, 561, "RAZ", 1, 1, 0, 0},
|
|
{"PCIEID" , 0, 8, 562, "RO", 0, 0, 16ull, 16ull},
|
|
{"NCP" , 8, 8, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCIECV" , 16, 4, 562, "RO", 0, 0, 2ull, 2ull},
|
|
{"DPT" , 20, 4, 562, "RO", 0, 0, 4ull, 4ull},
|
|
{"SI" , 24, 1, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IMN" , 25, 5, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_31" , 30, 2, 562, "RAZ", 1, 1, 0, 0},
|
|
{"MPSS" , 0, 3, 563, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PFS" , 3, 2, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ETFS" , 5, 1, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EL0AL" , 6, 3, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EL1AL" , 9, 3, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_14" , 12, 3, 563, "RAZ", 1, 1, 0, 0},
|
|
{"RBER" , 15, 1, 563, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_16_17" , 16, 2, 563, "RAZ", 1, 1, 0, 0},
|
|
{"CSPLV" , 18, 8, 563, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSPLS" , 26, 2, 563, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_31" , 28, 4, 563, "RAZ", 1, 1, 0, 0},
|
|
{"CE_EN" , 0, 1, 564, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NFE_EN" , 1, 1, 564, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FE_EN" , 2, 1, 564, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UR_EN" , 3, 1, 564, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RO_EN" , 4, 1, 564, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MPS" , 5, 3, 564, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ETF_EN" , 8, 1, 564, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PF_EN" , 9, 1, 564, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AP_EN" , 10, 1, 564, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NS_EN" , 11, 1, 564, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MRRS" , 12, 3, 564, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_15_15" , 15, 1, 564, "RAZ", 1, 1, 0, 0},
|
|
{"CE_D" , 16, 1, 564, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NFE_D" , 17, 1, 564, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FE_D" , 18, 1, 564, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UR_D" , 19, 1, 564, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AP_D" , 20, 1, 564, "RO", 0, 0, 0ull, 0ull},
|
|
{"TP" , 21, 1, 564, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_31" , 22, 10, 564, "RAZ", 1, 1, 0, 0},
|
|
{"MLS" , 0, 4, 565, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MLW" , 4, 6, 565, "R/W", 0, 0, 8ull, 8ull},
|
|
{"ASLPMS" , 10, 2, 565, "R/W", 0, 0, 3ull, 3ull},
|
|
{"L0EL" , 12, 3, 565, "R/W", 0, 0, 6ull, 6ull},
|
|
{"L1EL" , 15, 3, 565, "R/W", 0, 0, 6ull, 6ull},
|
|
{"CPM" , 18, 1, 565, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SDERC" , 19, 1, 565, "RO", 0, 0, 0ull, 0ull},
|
|
{"DLLARC" , 20, 1, 565, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBNC" , 21, 1, 565, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_22_23" , 22, 2, 565, "RAZ", 1, 1, 0, 0},
|
|
{"PNUM" , 24, 8, 565, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ASLPC" , 0, 2, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 566, "RAZ", 1, 1, 0, 0},
|
|
{"RCB" , 3, 1, 566, "R/W", 0, 0, 1ull, 1ull},
|
|
{"LD" , 4, 1, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RL" , 5, 1, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CCC" , 6, 1, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ES" , 7, 1, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECPM" , 8, 1, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HAWD" , 9, 1, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LBM_INT_ENB" , 10, 1, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LAB_INT_ENB" , 11, 1, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_15" , 12, 4, 566, "RAZ", 1, 1, 0, 0},
|
|
{"LS" , 16, 4, 566, "RO", 0, 0, 1ull, 1ull},
|
|
{"NLW" , 20, 6, 566, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_26" , 26, 1, 566, "RAZ", 1, 1, 0, 0},
|
|
{"LT" , 27, 1, 566, "RO", 0, 0, 0ull, 0ull},
|
|
{"SCC" , 28, 1, 566, "R/W", 0, 0, 1ull, 0ull},
|
|
{"DLLA" , 29, 1, 566, "RO", 0, 0, 0ull, 1ull},
|
|
{"LBM" , 30, 1, 566, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LAB" , 31, 1, 566, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ABP" , 0, 1, 567, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCP" , 1, 1, 567, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRLSP" , 2, 1, 567, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AIP" , 3, 1, 567, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PIP" , 4, 1, 567, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HP_S" , 5, 1, 567, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HP_C" , 6, 1, 567, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SP_LV" , 7, 8, 567, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SP_LS" , 15, 2, 567, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EMIP" , 17, 1, 567, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NCCS" , 18, 1, 567, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PS_NUM" , 19, 13, 567, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ABP_EN" , 0, 1, 568, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PF_EN" , 1, 1, 568, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRLS_EN" , 2, 1, 568, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PD_EN" , 3, 1, 568, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CCINT_EN" , 4, 1, 568, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HPINT_EN" , 5, 1, 568, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AIC" , 6, 2, 568, "R/W", 0, 0, 3ull, 3ull},
|
|
{"PIC" , 8, 2, 568, "R/W", 0, 0, 3ull, 3ull},
|
|
{"PCC" , 10, 1, 568, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EMIC" , 11, 1, 568, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLLS_EN" , 12, 1, 568, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 568, "RAZ", 1, 1, 0, 0},
|
|
{"ABP_D" , 16, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PF_D" , 17, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRLS_C" , 18, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PD_C" , 19, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CCINT_D" , 20, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRLSS" , 21, 1, 568, "RO", 0, 0, 0ull, 0ull},
|
|
{"PDS" , 22, 1, 568, "RO", 0, 0, 1ull, 1ull},
|
|
{"EMIS" , 23, 1, 568, "RO", 0, 0, 0ull, 0ull},
|
|
{"DLLS_C" , 24, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_31" , 25, 7, 568, "RAZ", 1, 1, 0, 0},
|
|
{"SECEE" , 0, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SENFEE" , 1, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SEFEE" , 2, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMEIE" , 3, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CRSSVE" , 4, 1, 569, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_15" , 5, 11, 569, "RAZ", 1, 1, 0, 0},
|
|
{"CRSSV" , 16, 1, 569, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 569, "RAZ", 1, 1, 0, 0},
|
|
{"PME_RID" , 0, 16, 570, "RO", 0, 0, 0ull, 0ull},
|
|
{"PME_STAT" , 16, 1, 570, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PME_PEND" , 17, 1, 570, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_31" , 18, 14, 570, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CTRS" , 0, 4, 571, "RO", 0, 0, 0ull, 0ull},
|
|
{"CTDS" , 4, 1, 571, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_5_31" , 5, 27, 571, "RAZ", 1, 1, 0, 0},
|
|
{"CTV" , 0, 4, 572, "RO", 0, 0, 0ull, 0ull},
|
|
{"CTD" , 4, 1, 572, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 572, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 573, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 574, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 575, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 576, "RAZ", 1, 1, 0, 0},
|
|
{"PCIEEC" , 0, 16, 577, "RO", 0, 0, 1ull, 1ull},
|
|
{"CV" , 16, 4, 577, "RO", 0, 0, 1ull, 1ull},
|
|
{"NCO" , 20, 12, 577, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_3" , 0, 4, 578, "RAZ", 1, 1, 0, 0},
|
|
{"DLPES" , 4, 1, 578, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SDES" , 5, 1, 578, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_11" , 6, 6, 578, "RAZ", 1, 1, 0, 0},
|
|
{"PTLPS" , 12, 1, 578, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCPES" , 13, 1, 578, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CTS" , 14, 1, 578, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CAS" , 15, 1, 578, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UCS" , 16, 1, 578, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ROS" , 17, 1, 578, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MTLPS" , 18, 1, 578, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ECRCES" , 19, 1, 578, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"URES" , 20, 1, 578, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 578, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_3" , 0, 4, 579, "RAZ", 1, 1, 0, 0},
|
|
{"DLPEM" , 4, 1, 579, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SDEM" , 5, 1, 579, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_11" , 6, 6, 579, "RAZ", 1, 1, 0, 0},
|
|
{"PTLPM" , 12, 1, 579, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCPEM" , 13, 1, 579, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CTM" , 14, 1, 579, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAM" , 15, 1, 579, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UCM" , 16, 1, 579, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROM" , 17, 1, 579, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MTLPM" , 18, 1, 579, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECRCEM" , 19, 1, 579, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UREM" , 20, 1, 579, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 579, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_3" , 0, 4, 580, "RAZ", 1, 1, 0, 0},
|
|
{"DLPES" , 4, 1, 580, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SDES" , 5, 1, 580, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_11" , 6, 6, 580, "RAZ", 1, 1, 0, 0},
|
|
{"PTLPS" , 12, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCPES" , 13, 1, 580, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTS" , 14, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAS" , 15, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UCS" , 16, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROS" , 17, 1, 580, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MTLPS" , 18, 1, 580, "R/W", 0, 0, 1ull, 1ull},
|
|
{"ECRCES" , 19, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"URES" , 20, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 580, "RAZ", 1, 1, 0, 0},
|
|
{"RES" , 0, 1, 581, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_5" , 1, 5, 581, "RAZ", 1, 1, 0, 0},
|
|
{"BTLPS" , 6, 1, 581, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BDLLPS" , 7, 1, 581, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RNRS" , 8, 1, 581, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 581, "RAZ", 1, 1, 0, 0},
|
|
{"RTTS" , 12, 1, 581, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ANFES" , 13, 1, 581, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_31" , 14, 18, 581, "RAZ", 1, 1, 0, 0},
|
|
{"REM" , 0, 1, 582, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_5" , 1, 5, 582, "RAZ", 1, 1, 0, 0},
|
|
{"BTLPM" , 6, 1, 582, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BDLLPM" , 7, 1, 582, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNRM" , 8, 1, 582, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 582, "RAZ", 1, 1, 0, 0},
|
|
{"RTTM" , 12, 1, 582, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ANFEM" , 13, 1, 582, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_14_31" , 14, 18, 582, "RAZ", 1, 1, 0, 0},
|
|
{"FEP" , 0, 5, 583, "RO", 0, 0, 0ull, 0ull},
|
|
{"GC" , 5, 1, 583, "RO", 0, 0, 1ull, 1ull},
|
|
{"GE" , 6, 1, 583, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CC" , 7, 1, 583, "RO", 0, 0, 1ull, 1ull},
|
|
{"CE" , 8, 1, 583, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_31" , 9, 23, 583, "RAZ", 1, 1, 0, 0},
|
|
{"DWORD1" , 0, 32, 584, "RO", 0, 0, 0ull, 0ull},
|
|
{"DWORD2" , 0, 32, 585, "RO", 0, 0, 0ull, 0ull},
|
|
{"DWORD3" , 0, 32, 586, "RO", 0, 0, 0ull, 0ull},
|
|
{"DWORD4" , 0, 32, 587, "RO", 0, 0, 0ull, 0ull},
|
|
{"CERE" , 0, 1, 588, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NFERE" , 1, 1, 588, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FERE" , 2, 1, 588, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_31" , 3, 29, 588, "RAZ", 1, 1, 0, 0},
|
|
{"ECR" , 0, 1, 589, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MULTI_ECR" , 1, 1, 589, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EFNFR" , 2, 1, 589, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MULTI_EFNFR" , 3, 1, 589, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FUF" , 4, 1, 589, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NFEMR" , 5, 1, 589, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FEMR" , 6, 1, 589, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_26" , 7, 20, 589, "RAZ", 1, 1, 0, 0},
|
|
{"AEIMN" , 27, 5, 589, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECSI" , 0, 16, 590, "RO", 0, 0, 0ull, 0ull},
|
|
{"EFNFSI" , 16, 16, 590, "RO", 0, 0, 0ull, 0ull},
|
|
{"RTLTL" , 0, 16, 591, "R/W", 0, 0, 4143ull, 4143ull},
|
|
{"RTL" , 16, 16, 591, "R/W", 0, 0, 12429ull, 12429ull},
|
|
{"OMR" , 0, 32, 592, "R/W", 0, 1, 4294967295ull, 0},
|
|
{"LINK_NUM" , 0, 8, 593, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_8_14" , 8, 7, 593, "RAZ", 1, 1, 0, 0},
|
|
{"FORCE_LINK" , 15, 1, 593, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LINK_STATE" , 16, 6, 593, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 593, "RAZ", 1, 1, 0, 0},
|
|
{"LPEC" , 24, 8, 593, "RO", 0, 0, 7ull, 7ull},
|
|
{"ACK_FREQ" , 0, 8, 594, "R/W", 0, 0, 0ull, 0ull},
|
|
{"N_FTS" , 8, 8, 594, "R/W", 0, 0, 128ull, 128ull},
|
|
{"N_FTS_CC" , 16, 8, 594, "R/W", 0, 0, 128ull, 128ull},
|
|
{"L0EL" , 24, 3, 594, "R/W", 0, 0, 3ull, 3ull},
|
|
{"L1EL" , 27, 3, 594, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_30_31" , 30, 2, 594, "RAZ", 1, 1, 0, 0},
|
|
{"OMR" , 0, 1, 595, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SD" , 1, 1, 595, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LE" , 2, 1, 595, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RA" , 3, 1, 595, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_4" , 4, 1, 595, "RAZ", 1, 1, 0, 0},
|
|
{"DLLLE" , 5, 1, 595, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_6" , 6, 1, 595, "RAZ", 1, 1, 0, 0},
|
|
{"FLM" , 7, 1, 595, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_15" , 8, 8, 595, "RO", 0, 0, 1ull, 1ull},
|
|
{"LME" , 16, 6, 595, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_22_24" , 22, 3, 595, "RAZ", 1, 1, 0, 0},
|
|
{"ECCRC" , 25, 1, 595, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_31" , 26, 6, 595, "RAZ", 1, 1, 0, 0},
|
|
{"ILST" , 0, 24, 596, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCD" , 24, 1, 596, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ACK_NAK" , 25, 1, 596, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_30" , 26, 5, 596, "RAZ", 1, 1, 0, 0},
|
|
{"DLLD" , 31, 1, 596, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NTSS" , 0, 4, 597, "R/W", 0, 0, 10ull, 10ull},
|
|
{"RESERVED_4_7" , 4, 4, 597, "RO", 1, 1, 0, 0},
|
|
{"NSKPS" , 8, 3, 597, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_11_13" , 11, 3, 597, "RAZ", 1, 1, 0, 0},
|
|
{"TMRT" , 14, 5, 597, "R/W", 0, 0, 8ull, 8ull},
|
|
{"TMANLT" , 19, 5, 597, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TMFCWT" , 24, 5, 597, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_31" , 29, 3, 597, "RO", 1, 1, 0, 0},
|
|
{"SKPIV" , 0, 11, 598, "R/W", 0, 0, 1280ull, 1280ull},
|
|
{"RESERVED_11_14" , 11, 4, 598, "RAZ", 1, 1, 0, 0},
|
|
{"DFCWT" , 15, 1, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_FUN" , 16, 1, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_POIS_FILT" , 17, 1, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_BAR_MATCH" , 18, 1, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CFG1_FILT" , 19, 1, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_LK_FILT" , 20, 1, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_TAG_ERR" , 21, 1, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_RID_ERR" , 22, 1, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_FUN_ERR" , 23, 1, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_TC_ERR" , 24, 1, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_ATTR_ERR" , 25, 1, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_LEN_ERR" , 26, 1, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_ECRC_FILT" , 27, 1, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_ECRC_FILT" , 28, 1, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSG_CTRL" , 29, 1, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_IO_FILT" , 30, 1, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CFG0_FILT" , 31, 1, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_VEND0_DRP" , 0, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_VEND1_DRP" , 1, 1, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_31" , 2, 30, 599, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_INFO_L32" , 0, 32, 600, "RO", 0, 0, 0ull, 0ull},
|
|
{"DBG_INFO_U32" , 0, 32, 601, "RO", 0, 0, 0ull, 0ull},
|
|
{"TPDFCC" , 0, 12, 602, "RO", 0, 0, 0ull, 0ull},
|
|
{"TPHFCC" , 12, 8, 602, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 602, "RAZ", 1, 1, 0, 0},
|
|
{"TCDFCC" , 0, 12, 603, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCHFCC" , 12, 8, 603, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 603, "RAZ", 1, 1, 0, 0},
|
|
{"TCDFCC" , 0, 12, 604, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCHFCC" , 12, 8, 604, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 604, "RAZ", 1, 1, 0, 0},
|
|
{"RTLPFCCNR" , 0, 1, 605, "RO", 0, 0, 0ull, 0ull},
|
|
{"TRBNE" , 1, 1, 605, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQNE" , 2, 1, 605, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_31" , 3, 29, 605, "RAZ", 1, 1, 0, 0},
|
|
{"WRR_VC0" , 0, 8, 606, "RO", 0, 0, 15ull, 15ull},
|
|
{"WRR_VC1" , 8, 8, 606, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC2" , 16, 8, 606, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC3" , 24, 8, 606, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC4" , 0, 8, 607, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC5" , 8, 8, 607, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC6" , 16, 8, 607, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC7" , 24, 8, 607, "RO", 0, 0, 0ull, 0ull},
|
|
{"DATA_CREDITS" , 0, 12, 608, "R/W", 0, 0, 72ull, 72ull},
|
|
{"HEADER_CREDITS" , 12, 8, 608, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_20_20" , 20, 1, 608, "RAZ", 1, 1, 0, 0},
|
|
{"QUEUE_MODE" , 21, 3, 608, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_24_29" , 24, 6, 608, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE_ORDERING" , 30, 1, 608, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RX_QUEUE_ORDER" , 31, 1, 608, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DATA_CREDITS" , 0, 12, 609, "R/W", 0, 0, 4ull, 4ull},
|
|
{"HEADER_CREDITS" , 12, 8, 609, "R/W", 0, 0, 8ull, 8ull},
|
|
{"RESERVED_20_20" , 20, 1, 609, "RAZ", 1, 1, 0, 0},
|
|
{"QUEUE_MODE" , 21, 3, 609, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_24_31" , 24, 8, 609, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_CREDITS" , 0, 12, 610, "R/W", 0, 0, 128ull, 128ull},
|
|
{"HEADER_CREDITS" , 12, 8, 610, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_20_20" , 20, 1, 610, "RAZ", 1, 1, 0, 0},
|
|
{"QUEUE_MODE" , 21, 3, 610, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_24_31" , 24, 8, 610, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_DEPTH" , 0, 14, 611, "R/W", 0, 0, 216ull, 216ull},
|
|
{"RESERVED_14_15" , 14, 2, 611, "RAZ", 1, 1, 0, 0},
|
|
{"HEADER_DEPTH" , 16, 10, 611, "R/W", 0, 0, 38ull, 38ull},
|
|
{"RESERVED_26_31" , 26, 6, 611, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_DEPTH" , 0, 14, 612, "R/W", 0, 0, 56ull, 56ull},
|
|
{"RESERVED_14_15" , 14, 2, 612, "RAZ", 1, 1, 0, 0},
|
|
{"HEADER_DEPTH" , 16, 10, 612, "R/W", 0, 0, 14ull, 14ull},
|
|
{"RESERVED_26_31" , 26, 6, 612, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_DEPTH" , 0, 14, 613, "R/W", 0, 0, 360ull, 360ull},
|
|
{"RESERVED_14_15" , 14, 2, 613, "RAZ", 1, 1, 0, 0},
|
|
{"HEADER_DEPTH" , 16, 10, 613, "R/W", 0, 0, 70ull, 70ull},
|
|
{"RESERVED_26_31" , 26, 6, 613, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_STAT" , 0, 32, 614, "RO", 0, 0, 0ull, 0ull},
|
|
{"PHY_CTRL" , 0, 32, 615, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_4" , 0, 5, 616, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FD" , 5, 1, 616, "R/W", 0, 0, 1ull, 1ull},
|
|
{"HFD" , 6, 1, 616, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PAUSE" , 7, 2, 616, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 616, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"REM_FLT" , 12, 2, 616, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_14" , 14, 1, 616, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"NP" , 15, 1, 616, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 616, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_11" , 0, 12, 617, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"THOU_THD" , 12, 1, 617, "RO", 0, 0, 0ull, 0ull},
|
|
{"THOU_TFD" , 13, 1, 617, "RO", 0, 0, 0ull, 0ull},
|
|
{"THOU_XHD" , 14, 1, 617, "RO", 0, 0, 1ull, 1ull},
|
|
{"THOU_XFD" , 15, 1, 617, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_16_63" , 16, 48, 617, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_4" , 0, 5, 618, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FD" , 5, 1, 618, "RO", 0, 0, 0ull, 0ull},
|
|
{"HFD" , 6, 1, 618, "RO", 0, 0, 0ull, 0ull},
|
|
{"PAUSE" , 7, 2, 618, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 618, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"REM_FLT" , 12, 2, 618, "RO", 0, 0, 0ull, 0ull},
|
|
{"ACK" , 14, 1, 618, "RO", 0, 1, 0ull, 0},
|
|
{"NP" , 15, 1, 618, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 618, "RAZ", 1, 1, 0, 0},
|
|
{"LINK_OK" , 0, 1, 619, "RO", 0, 0, 0ull, 0ull},
|
|
{"DUP" , 1, 1, 619, "RO", 0, 0, 0ull, 0ull},
|
|
{"AN_CPT" , 2, 1, 619, "RO", 0, 0, 0ull, 1ull},
|
|
{"SPD" , 3, 2, 619, "RO", 0, 0, 0ull, 0ull},
|
|
{"PAUSE" , 5, 2, 619, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 619, "RAZ", 1, 1, 0, 0},
|
|
{"LNKSPD_EN" , 0, 1, 620, "R/W", 0, 0, 0ull, 1ull},
|
|
{"XMIT_EN" , 1, 1, 620, "R/W", 0, 0, 0ull, 1ull},
|
|
{"AN_ERR_EN" , 2, 1, 620, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXFIFU_EN" , 3, 1, 620, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXFIFO_EN" , 4, 1, 620, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXBAD_EN" , 5, 1, 620, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXERR_EN" , 6, 1, 620, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXBAD_EN" , 7, 1, 620, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXLOCK_EN" , 8, 1, 620, "R/W", 0, 0, 0ull, 1ull},
|
|
{"AN_BAD_EN" , 9, 1, 620, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SYNC_BAD_EN" , 10, 1, 620, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DUP" , 11, 1, 620, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_12_63" , 12, 52, 620, "RAZ", 1, 1, 0, 0},
|
|
{"LNKSPD" , 0, 1, 621, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"XMIT" , 1, 1, 621, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AN_ERR" , 2, 1, 621, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXFIFU" , 3, 1, 621, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXFIFO" , 4, 1, 621, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXBAD" , 5, 1, 621, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXERR" , 6, 1, 621, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXBAD" , 7, 1, 621, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXLOCK" , 8, 1, 621, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AN_BAD" , 9, 1, 621, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SYNC_BAD" , 10, 1, 621, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DUP" , 11, 1, 621, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 621, "RAZ", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 16, 622, "R/W", 0, 1, 1094ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 622, "RAZ", 1, 1, 0, 0},
|
|
{"PKT_SZ" , 0, 2, 623, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LA_EN" , 2, 1, 623, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LAFIFOVFL" , 3, 1, 623, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 623, "RAZ", 1, 1, 0, 0},
|
|
{"SAMP_PT" , 0, 7, 624, "R/W", 0, 1, 1ull, 0},
|
|
{"AN_OVRD" , 7, 1, 624, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MODE" , 8, 1, 624, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAC_PHY" , 9, 1, 624, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LOOPBCK2" , 10, 1, 624, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GMXENO" , 11, 1, 624, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SGMII" , 12, 1, 624, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_13_63" , 13, 51, 624, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_4" , 0, 5, 625, "RAZ", 1, 1, 0, 0},
|
|
{"UNI" , 5, 1, 625, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SPDMSB" , 6, 1, 625, "R/W", 0, 0, 1ull, 1ull},
|
|
{"COLTST" , 7, 1, 625, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DUP" , 8, 1, 625, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RST_AN" , 9, 1, 625, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_10" , 10, 1, 625, "RAZ", 1, 1, 0, 0},
|
|
{"PWR_DN" , 11, 1, 625, "R/W", 0, 0, 1ull, 0ull},
|
|
{"AN_EN" , 12, 1, 625, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SPDLSB" , 13, 1, 625, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LOOPBCK1" , 14, 1, 625, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 15, 1, 625, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 625, "RAZ", 1, 1, 0, 0},
|
|
{"EXTND" , 0, 1, 626, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 626, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LNK_ST" , 2, 1, 626, "RO", 0, 0, 0ull, 1ull},
|
|
{"AN_ABIL" , 3, 1, 626, "RO", 0, 0, 1ull, 1ull},
|
|
{"RM_FLT" , 4, 1, 626, "RO", 0, 0, 0ull, 0ull},
|
|
{"AN_CPT" , 5, 1, 626, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRB_SUP" , 6, 1, 626, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_7_7" , 7, 1, 626, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EXT_ST" , 8, 1, 626, "RO", 0, 0, 1ull, 1ull},
|
|
{"HUN_T2HD" , 9, 1, 626, "RO", 0, 0, 0ull, 0ull},
|
|
{"HUN_T2FD" , 10, 1, 626, "RO", 0, 0, 0ull, 0ull},
|
|
{"TEN_HD" , 11, 1, 626, "RO", 0, 0, 0ull, 0ull},
|
|
{"TEN_FD" , 12, 1, 626, "RO", 0, 0, 0ull, 0ull},
|
|
{"HUN_XHD" , 13, 1, 626, "RO", 0, 0, 0ull, 0ull},
|
|
{"HUN_XFD" , 14, 1, 626, "RO", 0, 0, 0ull, 0ull},
|
|
{"HUN_T4" , 15, 1, 626, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 626, "RAZ", 1, 1, 0, 0},
|
|
{"AN_ST" , 0, 4, 627, "RO", 0, 0, 0ull, 0ull},
|
|
{"AN_BAD" , 4, 1, 627, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYNC" , 5, 4, 627, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYNC_BAD" , 9, 1, 627, "RO", 0, 0, 0ull, 0ull},
|
|
{"RX_ST" , 10, 5, 627, "RO", 0, 0, 0ull, 0ull},
|
|
{"RX_BAD" , 15, 1, 627, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 627, "RAZ", 1, 1, 0, 0},
|
|
{"BIT_LOCK" , 0, 1, 628, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYNC" , 1, 1, 628, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 628, "RAZ", 1, 1, 0, 0},
|
|
{"ONE" , 0, 1, 629, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_9" , 1, 9, 629, "RAZ", 0, 1, 0ull, 0},
|
|
{"SPEED" , 10, 2, 629, "R/W", 0, 0, 2ull, 2ull},
|
|
{"DUP" , 12, 1, 629, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_13_13" , 13, 1, 629, "RAZ", 0, 1, 0ull, 0},
|
|
{"ACK" , 14, 1, 629, "RO", 0, 0, 0ull, 0ull},
|
|
{"LINK" , 15, 1, 629, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_16_63" , 16, 48, 629, "RAZ", 1, 1, 0, 0},
|
|
{"ONE" , 0, 1, 630, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_9" , 1, 9, 630, "RAZ", 0, 1, 0ull, 0},
|
|
{"SPEED" , 10, 2, 630, "RO", 0, 0, 0ull, 2ull},
|
|
{"DUP" , 12, 1, 630, "RO", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_13_14" , 13, 2, 630, "RAZ", 0, 1, 0ull, 0},
|
|
{"LINK" , 15, 1, 630, "RO", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_16_63" , 16, 48, 630, "RAZ", 1, 1, 0, 0},
|
|
{"ORD_ST" , 0, 4, 631, "RO", 0, 0, 0ull, 0ull},
|
|
{"TX_BAD" , 4, 1, 631, "RO", 0, 0, 0ull, 0ull},
|
|
{"XMIT" , 5, 2, 631, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 631, "RAZ", 1, 1, 0, 0},
|
|
{"TXPLRT" , 0, 1, 632, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RXPLRT" , 1, 1, 632, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AUTORXPL" , 2, 1, 632, "RO", 0, 0, 0ull, 0ull},
|
|
{"RXOVRD" , 3, 1, 632, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 632, "RAZ", 1, 1, 0, 0},
|
|
{"L0SYNC" , 0, 1, 633, "RO", 0, 0, 0ull, 1ull},
|
|
{"L1SYNC" , 1, 1, 633, "RO", 0, 0, 0ull, 1ull},
|
|
{"L2SYNC" , 2, 1, 633, "RO", 0, 0, 0ull, 1ull},
|
|
{"L3SYNC" , 3, 1, 633, "RO", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_4_10" , 4, 7, 633, "RAZ", 1, 1, 0, 0},
|
|
{"PATTST" , 11, 1, 633, "RO", 0, 0, 0ull, 0ull},
|
|
{"ALIGND" , 12, 1, 633, "RO", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_13_63" , 13, 51, 633, "RAZ", 1, 1, 0, 0},
|
|
{"BIST_STATUS" , 0, 1, 634, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 634, "RAZ", 1, 1, 0, 0},
|
|
{"BITLCK0" , 0, 1, 635, "RO", 0, 1, 0ull, 0},
|
|
{"BITLCK1" , 1, 1, 635, "RO", 0, 1, 0ull, 0},
|
|
{"BITLCK2" , 2, 1, 635, "RO", 0, 1, 0ull, 0},
|
|
{"BITLCK3" , 3, 1, 635, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 635, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 636, "RAZ", 1, 1, 0, 0},
|
|
{"SPD" , 2, 4, 636, "RO", 0, 0, 0ull, 0ull},
|
|
{"SPDSEL0" , 6, 1, 636, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_7_10" , 7, 4, 636, "RAZ", 1, 1, 0, 0},
|
|
{"LO_PWR" , 11, 1, 636, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_12" , 12, 1, 636, "RAZ", 1, 1, 0, 0},
|
|
{"SPDSEL1" , 13, 1, 636, "RO", 0, 0, 1ull, 1ull},
|
|
{"LOOPBCK1" , 14, 1, 636, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 15, 1, 636, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 636, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 2, 637, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 637, "RAZ", 1, 1, 0, 0},
|
|
{"TXFLT_EN" , 0, 1, 638, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXBAD_EN" , 1, 1, 638, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXSYNBAD_EN" , 2, 1, 638, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BITLCKLS_EN" , 3, 1, 638, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SYNLOS_EN" , 4, 1, 638, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ALGNLOS_EN" , 5, 1, 638, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_6_63" , 6, 58, 638, "RAZ", 1, 1, 0, 0},
|
|
{"TXFLT" , 0, 1, 639, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXBAD" , 1, 1, 639, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXSYNBAD" , 2, 1, 639, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BITLCKLS" , 3, 1, 639, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SYNLOS" , 4, 1, 639, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ALGNLOS" , 5, 1, 639, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 639, "RAZ", 1, 1, 0, 0},
|
|
{"PKT_SZ" , 0, 2, 640, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LA_EN" , 2, 1, 640, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LAFIFOVFL" , 3, 1, 640, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DROP_LN" , 4, 2, 640, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENC_MODE" , 6, 1, 640, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 640, "RAZ", 1, 1, 0, 0},
|
|
{"GMXENO" , 0, 1, 641, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XAUI" , 1, 1, 641, "RO", 1, 1, 0, 0},
|
|
{"RX_SWAP" , 2, 1, 641, "R/W", 0, 1, 0ull, 0},
|
|
{"TX_SWAP" , 3, 1, 641, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 641, "RAZ", 1, 1, 0, 0},
|
|
{"SYNC0ST" , 0, 4, 642, "RO", 0, 1, 0ull, 0},
|
|
{"SYNC1ST" , 4, 4, 642, "RO", 0, 1, 0ull, 0},
|
|
{"SYNC2ST" , 8, 4, 642, "RO", 0, 1, 0ull, 0},
|
|
{"SYNC3ST" , 12, 4, 642, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 642, "RAZ", 1, 1, 0, 0},
|
|
{"TENGB" , 0, 1, 643, "RO", 0, 0, 1ull, 1ull},
|
|
{"TENPASST" , 1, 1, 643, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 643, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 644, "RAZ", 1, 1, 0, 0},
|
|
{"LPABLE" , 1, 1, 644, "RO", 0, 0, 1ull, 1ull},
|
|
{"RCV_LNK" , 2, 1, 644, "RO", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_3_6" , 3, 4, 644, "RAZ", 1, 1, 0, 0},
|
|
{"FLT" , 7, 1, 644, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 644, "RAZ", 1, 1, 0, 0},
|
|
{"TENGB_R" , 0, 1, 645, "RO", 0, 0, 0ull, 0ull},
|
|
{"TENGB_X" , 1, 1, 645, "RO", 0, 0, 1ull, 1ull},
|
|
{"TENGB_W" , 2, 1, 645, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_9" , 3, 7, 645, "RAZ", 1, 1, 0, 0},
|
|
{"RCVFLT" , 10, 1, 645, "RC", 0, 0, 0ull, 0ull},
|
|
{"XMTFLT" , 11, 1, 645, "RC", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_13" , 12, 2, 645, "RAZ", 1, 1, 0, 0},
|
|
{"DEV" , 14, 2, 645, "RO", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_16_63" , 16, 48, 645, "RAZ", 1, 1, 0, 0},
|
|
{"TXPLRT" , 0, 1, 646, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RXPLRT" , 1, 1, 646, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 646, "RAZ", 1, 1, 0, 0},
|
|
{"TX_ST" , 0, 3, 647, "RO", 0, 1, 0ull, 0},
|
|
{"RX_ST" , 3, 2, 647, "RO", 0, 1, 0ull, 0},
|
|
{"ALGN_ST" , 5, 3, 647, "RO", 0, 1, 0ull, 0},
|
|
{"RXBAD" , 8, 1, 647, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYN0BAD" , 9, 1, 647, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYN1BAD" , 10, 1, 647, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYN2BAD" , 11, 1, 647, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYN3BAD" , 12, 1, 647, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 647, "RAZ", 1, 1, 0, 0},
|
|
{"SOT" , 0, 1, 648, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQHDR0" , 1, 1, 648, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQHDR1" , 2, 1, 648, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQDATA4" , 3, 1, 648, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQDATA3" , 4, 1, 648, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQDATA2" , 5, 1, 648, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQDATA1" , 6, 1, 648, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQDATA0" , 7, 1, 648, "RO", 0, 0, 0ull, 0ull},
|
|
{"RETRY" , 8, 1, 648, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTLP_OR" , 9, 1, 648, "RO", 0, 0, 0ull, 0ull},
|
|
{"NTLP_OR" , 10, 1, 648, "RO", 0, 0, 0ull, 0ull},
|
|
{"CTLP_OR" , 11, 1, 648, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 648, "RAZ", 1, 1, 0, 0},
|
|
{"PPF" , 0, 1, 649, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEF_TC0" , 1, 1, 649, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEF_TCF1" , 2, 1, 649, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEF_TNF" , 3, 1, 649, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEF_TPF0" , 4, 1, 649, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEF_TPF1" , 5, 1, 649, "RO", 0, 0, 0ull, 0ull},
|
|
{"RSL_P2E" , 6, 1, 649, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEAI_P2E" , 7, 1, 649, "RO", 0, 0, 0ull, 0ull},
|
|
{"DBG_P2E" , 8, 1, 649, "RO", 0, 0, 0ull, 0ull},
|
|
{"E2P_RSL" , 9, 1, 649, "RO", 0, 0, 0ull, 0ull},
|
|
{"E2P_P" , 10, 1, 649, "RO", 0, 0, 0ull, 0ull},
|
|
{"E2P_N" , 11, 1, 649, "RO", 0, 0, 0ull, 0ull},
|
|
{"E2P_CPL" , 12, 1, 649, "RO", 0, 0, 0ull, 0ull},
|
|
{"CTO_P2E" , 13, 1, 649, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 649, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 32, 650, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 32, 32, 650, "R/W", 0, 1, 0ull, 0},
|
|
{"ADDR" , 0, 32, 651, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 32, 32, 651, "R/W", 0, 1, 0ull, 0},
|
|
{"TAG" , 0, 32, 652, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 652, "RAZ", 1, 1, 0, 0},
|
|
{"INV_LCRC" , 0, 1, 653, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INV_ECRC" , 1, 1, 653, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 653, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RO_CTLP" , 3, 1, 653, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LNK_ENB" , 4, 1, 653, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLY_ONE" , 5, 1, 653, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NF_ECRC" , 6, 1, 653, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_8" , 7, 2, 653, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OB_P_CMD" , 9, 1, 653, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PM_XPME" , 10, 1, 653, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PM_XTOFF" , 11, 1, 653, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_12" , 12, 1, 653, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"QLM_CFG" , 13, 2, 653, "RO", 1, 1, 0, 0},
|
|
{"PBUS" , 15, 8, 653, "RO", 1, 1, 0, 0},
|
|
{"DNUM" , 23, 5, 653, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_28_63" , 28, 36, 653, "RAZ", 1, 1, 0, 0},
|
|
{"PCIERST" , 0, 1, 654, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 654, "RAZ", 1, 1, 0, 0},
|
|
{"SPOISON" , 0, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTLPMAL" , 1, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTLPLLE" , 2, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RECRCE" , 3, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPOISON" , 4, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RCEMRC" , 5, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RNFEMRC" , 6, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RFEMRC" , 7, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPMERC" , 8, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPTAMRC" , 9, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RUMEP" , 10, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RVDM" , 11, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ACTO" , 12, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTE" , 13, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRE" , 14, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RDWDLE" , 15, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTWDLE" , 16, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPEOOSD" , 17, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCPVWT" , 18, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPE" , 19, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCUV" , 20, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQO" , 21, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RAUC" , 22, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RACUR" , 23, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RACCA" , 24, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CAAR" , 25, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RARWDNS" , 26, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RAMTLP" , 27, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RACPP" , 28, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RAWWPP" , 29, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ECRC_E" , 30, 1, 655, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 655, "RAZ", 1, 1, 0, 0},
|
|
{"SPOISON" , 0, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RTLPMAL" , 1, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RTLPLLE" , 2, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RECRCE" , 3, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RPOISON" , 4, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RCEMRC" , 5, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNFEMRC" , 6, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RFEMRC" , 7, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RPMERC" , 8, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RPTAMRC" , 9, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RUMEP" , 10, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RVDM" , 11, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ACTO" , 12, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RTE" , 13, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRE" , 14, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RDWDLE" , 15, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RTWDLE" , 16, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DPEOOSD" , 17, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCPVWT" , 18, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RPE" , 19, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCUV" , 20, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQO" , 21, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RAUC" , 22, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RACUR" , 23, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RACCA" , 24, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAAR" , 25, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RARWDNS" , 26, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RAMTLP" , 27, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RACPP" , 28, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RAWWPP" , 29, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECRC_E" , 30, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 656, "RAZ", 1, 1, 0, 0},
|
|
{"AUX_EN" , 0, 1, 657, "RO", 0, 0, 0ull, 0ull},
|
|
{"PM_EN" , 1, 1, 657, "RO", 0, 0, 0ull, 0ull},
|
|
{"PM_STAT" , 2, 1, 657, "RO", 0, 0, 0ull, 0ull},
|
|
{"PM_DST" , 3, 1, 657, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 657, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_0_13" , 0, 14, 658, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 14, 50, 658, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_25" , 0, 26, 659, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 26, 38, 659, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_38" , 0, 39, 660, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 39, 25, 660, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_11" , 0, 12, 661, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 12, 52, 661, "R/W", 0, 1, 4503599627370495ull, 0},
|
|
{"RESERVED_0_11" , 0, 12, 662, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 12, 52, 662, "R/W", 0, 1, 4503599627370495ull, 0},
|
|
{"NPEI_P" , 0, 5, 663, "R/W", 0, 0, 2ull, 2ull},
|
|
{"NPEI_NP" , 5, 5, 663, "R/W", 0, 0, 2ull, 2ull},
|
|
{"NPEI_CPL" , 10, 5, 663, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PESC_P" , 15, 5, 663, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PESC_NP" , 20, 5, 663, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PESC_CPL" , 25, 5, 663, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PEAI_PPF" , 30, 8, 663, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_38_63" , 38, 26, 663, "RAZ", 1, 1, 0, 0},
|
|
{"LOWATER" , 0, 5, 664, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_5_7" , 5, 3, 664, "RAZ", 0, 1, 0ull, 0},
|
|
{"HIWATER" , 8, 5, 664, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_13_62" , 13, 50, 664, "RAZ", 0, 1, 0ull, 0},
|
|
{"BCKPRS" , 63, 1, 664, "RO", 0, 0, 0ull, 0ull},
|
|
{"BIST" , 0, 18, 665, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 665, "RAZ", 1, 1, 0, 0},
|
|
{"DPRT" , 0, 16, 666, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UDP" , 16, 1, 666, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP" , 17, 1, 666, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 666, "RAZ", 1, 1, 0, 0},
|
|
{"MINLEN" , 0, 16, 667, "R/W", 0, 0, 64ull, 64ull},
|
|
{"MAXLEN" , 16, 16, 667, "R/W", 0, 0, 1536ull, 1536ull},
|
|
{"RESERVED_32_63" , 32, 32, 667, "RAZ", 1, 1, 0, 0},
|
|
{"NIP_SHF" , 0, 3, 668, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_7" , 3, 5, 668, "RAZ", 1, 1, 0, 0},
|
|
{"RAW_SHF" , 8, 3, 668, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_15" , 11, 5, 668, "RAZ", 1, 1, 0, 0},
|
|
{"MAX_L2" , 16, 1, 668, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_UDP" , 17, 1, 668, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TAG_SYN" , 18, 1, 668, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 668, "RAZ", 1, 1, 0, 0},
|
|
{"IP_CHK" , 0, 1, 669, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP_MAL" , 1, 1, 669, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP_HOP" , 2, 1, 669, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP4_OPTS" , 3, 1, 669, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP6_EEXT" , 4, 2, 669, "R/W", 0, 0, 1ull, 3ull},
|
|
{"RESERVED_6_7" , 6, 2, 669, "RAZ", 1, 1, 0, 0},
|
|
{"L4_MAL" , 8, 1, 669, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_PRT" , 9, 1, 669, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_CHK" , 10, 1, 669, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_LEN" , 11, 1, 669, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TCP_FLAG" , 12, 1, 669, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L2_MAL" , 13, 1, 669, "R/W", 0, 0, 1ull, 1ull},
|
|
{"VS_QOS" , 14, 1, 669, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VS_WQE" , 15, 1, 669, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IGNRS" , 16, 1, 669, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_19" , 17, 3, 669, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RING_EN" , 20, 1, 669, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_21_63" , 21, 43, 669, "RAZ", 1, 1, 0, 0},
|
|
{"PKTDRP" , 0, 1, 670, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CRCERR" , 1, 1, 670, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BCKPRS" , 2, 1, 670, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 3, 1, 670, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BADTAG" , 4, 1, 670, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPRUNT" , 5, 1, 670, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TODOOVR" , 6, 1, 670, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FEPERR" , 7, 1, 670, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BEPERR" , 8, 1, 670, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MINERR" , 9, 1, 670, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 10, 1, 670, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 11, 1, 670, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 670, "RAZ", 1, 1, 0, 0},
|
|
{"PKTDRP" , 0, 1, 671, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CRCERR" , 1, 1, 671, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BCKPRS" , 2, 1, 671, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 3, 1, 671, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BADTAG" , 4, 1, 671, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPRUNT" , 5, 1, 671, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TODOOVR" , 6, 1, 671, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FEPERR" , 7, 1, 671, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BEPERR" , 8, 1, 671, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MINERR" , 9, 1, 671, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 10, 1, 671, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 11, 1, 671, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 671, "RAZ", 1, 1, 0, 0},
|
|
{"OFFSET" , 0, 3, 672, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 672, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP" , 0, 7, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 673, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 8, 2, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_11" , 10, 2, 673, "RAZ", 1, 1, 0, 0},
|
|
{"CRC_EN" , 12, 1, 673, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 673, "RAZ", 1, 1, 0, 0},
|
|
{"QOS_VLAN" , 16, 1, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS_DIFF" , 17, 1, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS_VOD" , 18, 1, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_19" , 19, 1, 673, "RAZ", 1, 1, 0, 0},
|
|
{"QOS_WAT" , 20, 4, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS" , 24, 3, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 673, "RAZ", 1, 1, 0, 0},
|
|
{"GRP_WAT" , 28, 4, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INST_HDR" , 32, 1, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DYN_RS" , 33, 1, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TAG_INC" , 34, 2, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RAWDRP" , 36, 1, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_39" , 37, 3, 673, "RAZ", 1, 1, 0, 0},
|
|
{"QOS_WAT_47" , 40, 4, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRP_WAT_47" , 44, 4, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MINERR_EN" , 48, 1, 673, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MAXERR_EN" , 49, 1, 673, "R/W", 0, 0, 1ull, 1ull},
|
|
{"LENERR_EN" , 50, 1, 673, "R/W", 0, 0, 1ull, 1ull},
|
|
{"VLAN_LEN" , 51, 1, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PAD_LEN" , 52, 1, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_53_63" , 53, 11, 673, "RAZ", 1, 1, 0, 0},
|
|
{"GRP" , 0, 4, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NON_TAG_TYPE" , 4, 2, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_TAG_TYPE" , 6, 2, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_TAG_TYPE" , 8, 2, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP4_TAG_TYPE" , 10, 2, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP6_TAG_TYPE" , 12, 2, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_SRC_FLAG" , 14, 1, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_SRC_FLAG" , 15, 1, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_DST_FLAG" , 16, 1, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_DST_FLAG" , 17, 1, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_PCTL_FLAG" , 18, 1, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_NXTH_FLAG" , 19, 1, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_SPRT_FLAG" , 20, 1, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_SPRT_FLAG" , 21, 1, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_DPRT_FLAG" , 22, 1, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_DPRT_FLAG" , 23, 1, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_PRT_FLAG" , 24, 1, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_VLAN" , 25, 1, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_VS" , 26, 2, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TAG_MODE" , 28, 2, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAG_MSKIP" , 30, 1, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAG" , 31, 1, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAGMASK" , 32, 4, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAGBASE" , 36, 4, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 674, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 0, 3, 675, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 675, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 0, 3, 676, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 676, "RAZ", 1, 1, 0, 0},
|
|
{"MATCH_VALUE" , 0, 16, 677, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MATCH_TYPE" , 16, 3, 677, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_19" , 19, 1, 677, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 20, 3, 677, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 677, "RAZ", 1, 1, 0, 0},
|
|
{"GRP" , 24, 4, 677, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_31" , 28, 4, 677, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 32, 16, 677, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 677, "RAZ", 1, 1, 0, 0},
|
|
{"WORD" , 0, 56, 678, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 678, "RAZ", 1, 1, 0, 0},
|
|
{"RST" , 0, 1, 679, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 679, "RAZ", 1, 1, 0, 0},
|
|
{"DRP_OCTS" , 0, 32, 680, "R/W", 0, 1, 0ull, 0},
|
|
{"DRP_PKTS" , 32, 32, 680, "R/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 681, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 681, "RAZ", 1, 1, 0, 0},
|
|
{"RAW" , 0, 32, 682, "R/W", 0, 1, 0ull, 0},
|
|
{"PKTS" , 32, 32, 682, "R/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 0, 32, 683, "R/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 32, 32, 683, "R/W", 0, 1, 0ull, 0},
|
|
{"H64" , 0, 32, 684, "R/W", 0, 1, 0ull, 0},
|
|
{"H65TO127" , 32, 32, 684, "R/W", 0, 1, 0ull, 0},
|
|
{"H128TO255" , 0, 32, 685, "R/W", 0, 1, 0ull, 0},
|
|
{"H256TO511" , 32, 32, 685, "R/W", 0, 1, 0ull, 0},
|
|
{"H512TO1023" , 0, 32, 686, "R/W", 0, 1, 0ull, 0},
|
|
{"H1024TO1518" , 32, 32, 686, "R/W", 0, 1, 0ull, 0},
|
|
{"H1519" , 0, 32, 687, "R/W", 0, 1, 0ull, 0},
|
|
{"FCS" , 32, 32, 687, "R/W", 0, 1, 0ull, 0},
|
|
{"UNDERSZ" , 0, 32, 688, "R/W", 0, 1, 0ull, 0},
|
|
{"FRAG" , 32, 32, 688, "R/W", 0, 1, 0ull, 0},
|
|
{"OVERSZ" , 0, 32, 689, "R/W", 0, 1, 0ull, 0},
|
|
{"JABBER" , 32, 32, 689, "R/W", 0, 1, 0ull, 0},
|
|
{"RDCLR" , 0, 1, 690, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 690, "RAZ", 1, 1, 0, 0},
|
|
{"ERRS" , 0, 16, 691, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 691, "RAZ", 1, 1, 0, 0},
|
|
{"OCTS" , 0, 48, 692, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 692, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 693, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 693, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 8, 694, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 694, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 0, 16, 695, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 695, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 16, 696, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DST" , 16, 16, 696, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 696, "RAZ", 1, 1, 0, 0},
|
|
{"ENTRY" , 0, 62, 697, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_62_62" , 62, 1, 697, "RAZ", 1, 1, 0, 0},
|
|
{"VAL" , 63, 1, 697, "RO", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 32, 698, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 698, "RAZ", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 48, 699, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 699, "RAZ", 1, 1, 0, 0},
|
|
{"SIZE" , 0, 16, 700, "RO", 1, 0, 0, 0ull},
|
|
{"SEGS" , 16, 6, 700, "RO", 1, 0, 0, 0ull},
|
|
{"CMD" , 22, 14, 700, "RO", 1, 0, 0, 0ull},
|
|
{"FAU" , 36, 28, 700, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 701, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 701, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 701, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 701, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 701, "RO", 1, 0, 0, 0ull},
|
|
{"PTRS2" , 0, 17, 702, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 702, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTRS1" , 32, 17, 702, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 702, "RAZ", 1, 0, 0, 0ull},
|
|
{"MOD" , 0, 3, 703, "RO", 1, 0, 0, 0ull},
|
|
{"CNT" , 3, 13, 703, "RO", 1, 0, 0, 0ull},
|
|
{"CHK" , 16, 1, 703, "RO", 1, 0, 0, 0ull},
|
|
{"LEN" , 17, 1, 703, "RO", 1, 0, 0, 0ull},
|
|
{"SOP" , 18, 1, 703, "RO", 1, 0, 0, 0ull},
|
|
{"UID" , 19, 3, 703, "RO", 1, 0, 0, 0ull},
|
|
{"MAJ" , 22, 1, 703, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 703, "RAZ", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 16, 704, "RO", 1, 0, 0, 0ull},
|
|
{"SEGS" , 16, 6, 704, "RO", 1, 0, 0, 0ull},
|
|
{"CMD" , 22, 14, 704, "RO", 1, 0, 0, 0ull},
|
|
{"FAU" , 36, 28, 704, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 705, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 705, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 705, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 705, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 705, "RO", 1, 0, 0, 0ull},
|
|
{"DATA" , 0, 64, 706, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 707, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 707, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 707, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 707, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 707, "RO", 1, 0, 0, 0ull},
|
|
{"DATA" , 0, 64, 708, "RO", 1, 0, 0, 0ull},
|
|
{"MAJOR" , 0, 3, 709, "RO", 1, 0, 0, 0ull},
|
|
{"MINOR" , 3, 2, 709, "RO", 1, 0, 0, 0ull},
|
|
{"WAIT" , 5, 1, 709, "RO", 1, 0, 0, 0ull},
|
|
{"CHK_MODE" , 6, 1, 709, "RO", 1, 0, 0, 0ull},
|
|
{"CHK_ONCE" , 7, 1, 709, "RO", 1, 0, 0, 0ull},
|
|
{"INIT_DWRITE" , 8, 1, 709, "RO", 1, 0, 0, 0ull},
|
|
{"DREAD_SOP" , 9, 1, 709, "RO", 1, 0, 0, 0ull},
|
|
{"UID" , 10, 2, 709, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_OFF" , 12, 6, 709, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_SIZ" , 18, 16, 709, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_SEGS" , 34, 6, 709, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_OFF" , 40, 16, 709, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_SIZ" , 56, 8, 709, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_SIZ" , 0, 8, 710, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_PTR" , 8, 40, 710, "RO", 1, 0, 0, 0ull},
|
|
{"NXT_INFLT" , 48, 6, 710, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_54_63" , 54, 10, 710, "RAZ", 1, 0, 0, 0ull},
|
|
{"QID_BASE" , 0, 8, 711, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFF" , 8, 4, 711, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFFMAX" , 12, 4, 711, "RO", 1, 0, 0, 0ull},
|
|
{"QCB_RIDX" , 16, 5, 711, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 21, 3, 711, "RO", 1, 0, 0, 0ull},
|
|
{"STATC" , 24, 1, 711, "RO", 1, 0, 0, 0ull},
|
|
{"ACTIVE" , 25, 1, 711, "RO", 1, 0, 0, 0ull},
|
|
{"PREEMPTED" , 26, 1, 711, "RO", 1, 0, 0, 0ull},
|
|
{"PREEMPTEE" , 27, 1, 711, "RO", 1, 0, 0, 0ull},
|
|
{"PREEMPTER" , 28, 1, 711, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFFTHS" , 29, 4, 711, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFFRES" , 33, 4, 711, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 711, "RAZ", 1, 0, 0, 0ull},
|
|
{"QCB_RIDX" , 0, 6, 712, "RO", 1, 0, 0, 0ull},
|
|
{"QCB_WIDX" , 6, 6, 712, "RO", 1, 0, 0, 0ull},
|
|
{"BUF_PTR" , 12, 33, 712, "RO", 1, 0, 0, 0ull},
|
|
{"BUF_SIZ" , 45, 13, 712, "RO", 1, 0, 0, 0ull},
|
|
{"TAIL" , 58, 1, 712, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 59, 5, 712, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 0, 3, 713, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_Q" , 3, 1, 713, "RO", 1, 0, 0, 0ull},
|
|
{"S_TAIL" , 4, 1, 713, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 5, 1, 713, "RO", 1, 0, 0, 0ull},
|
|
{"PREEMPTEE" , 6, 1, 713, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 713, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 8, 20, 713, "RO", 1, 0, 0, 0ull},
|
|
{"PREEMPTER" , 28, 1, 713, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 713, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTRS3" , 0, 17, 714, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 714, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTRS0" , 32, 17, 714, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 714, "RAZ", 1, 0, 0, 0ull},
|
|
{"PID" , 0, 6, 715, "R/W", 1, 0, 0, 0ull},
|
|
{"EID" , 6, 4, 715, "R/W", 1, 0, 0, 0ull},
|
|
{"BP_PORT" , 10, 6, 715, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_16_52" , 16, 37, 715, "RAZ", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 715, "R/W", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 61, 1, 715, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_62_63" , 62, 2, 715, "RAZ", 1, 0, 0, 0ull},
|
|
{"PID" , 0, 6, 716, "R/W", 1, 0, 0, 0ull},
|
|
{"EID" , 6, 4, 716, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_10_52" , 10, 43, 716, "RAZ", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 716, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_61_63" , 61, 3, 716, "RAZ", 1, 0, 0, 0ull},
|
|
{"PID" , 0, 6, 717, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 717, "RAZ", 1, 0, 0, 0ull},
|
|
{"RATE_PKT" , 8, 24, 717, "R/W", 1, 0, 0, 0ull},
|
|
{"RATE_WORD" , 32, 19, 717, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_51_63" , 51, 13, 717, "RAZ", 1, 0, 0, 0ull},
|
|
{"PID" , 0, 6, 718, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 718, "RAZ", 1, 0, 0, 0ull},
|
|
{"RATE_LIM" , 8, 24, 718, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 718, "RAZ", 1, 0, 0, 0ull},
|
|
{"QUEUE" , 0, 7, 719, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT" , 7, 6, 719, "WR0", 1, 0, 0, 0ull},
|
|
{"INDEX" , 13, 3, 719, "WR0", 1, 0, 0, 0ull},
|
|
{"TAIL" , 16, 1, 719, "R/W", 1, 0, 0, 0ull},
|
|
{"BUF_PTR" , 17, 36, 719, "R/W", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 719, "R/W", 1, 0, 0, 0ull},
|
|
{"STATIC_Q" , 61, 1, 719, "R/W", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 62, 1, 719, "R/W", 1, 0, 0, 0ull},
|
|
{"S_TAIL" , 63, 1, 719, "R/W", 1, 0, 0, 0ull},
|
|
{"QID" , 0, 7, 720, "R/W", 1, 0, 0, 0ull},
|
|
{"PID" , 7, 6, 720, "WR0", 1, 0, 0, 0ull},
|
|
{"RESERVED_13_52" , 13, 40, 720, "RAZ", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 720, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_61_63" , 61, 3, 720, "RAZ", 1, 0, 0, 0ull},
|
|
{"DAT_PTR" , 0, 4, 721, "RO", 1, 0, 0, 0ull},
|
|
{"DAT_DAT" , 4, 2, 721, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_CTL" , 6, 2, 721, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_QSB" , 8, 3, 721, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_QCB" , 11, 2, 721, "RO", 1, 0, 0, 0ull},
|
|
{"NCB_INB" , 13, 2, 721, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_PSB" , 15, 8, 721, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_NXT" , 23, 1, 721, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_CHK" , 24, 3, 721, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_WIF" , 27, 1, 721, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_STA" , 28, 1, 721, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_CTL" , 29, 3, 721, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_DAT" , 32, 1, 721, "RO", 1, 0, 0, 0ull},
|
|
{"IOB" , 33, 1, 721, "RO", 1, 0, 0, 0ull},
|
|
{"CSR" , 34, 1, 721, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_35_63" , 35, 29, 721, "RAZ", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 13, 722, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_19" , 13, 7, 722, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 20, 3, 722, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 722, "RAZ", 1, 0, 0, 0ull},
|
|
{"ASSERTS" , 0, 64, 723, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 64, 724, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 64, 725, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 64, 726, "RO", 0, 0, 0ull, 0ull},
|
|
{"ENGINE0" , 0, 4, 727, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE1" , 4, 4, 727, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE2" , 8, 4, 727, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE3" , 12, 4, 727, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE4" , 16, 4, 727, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE5" , 20, 4, 727, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE6" , 24, 4, 727, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE7" , 28, 4, 727, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE8" , 32, 4, 727, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE9" , 36, 4, 727, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_40_63" , 40, 24, 727, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 10, 728, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 728, "RAZ", 1, 0, 0, 0ull},
|
|
{"PARITY" , 0, 1, 729, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 1, 1, 729, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CURRZERO" , 2, 1, 729, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 729, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENA_PKO" , 0, 1, 730, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENA_DWB" , 1, 1, 730, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STORE_BE" , 2, 1, 730, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 3, 1, 730, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 730, "RAZ", 1, 0, 0, 0ull},
|
|
{"MODE0" , 0, 3, 731, "R/W", 0, 0, 2ull, 2ull},
|
|
{"MODE1" , 3, 3, 731, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_6_63" , 6, 58, 731, "RAZ", 1, 0, 0, 0ull},
|
|
{"PARITY" , 0, 1, 732, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 1, 1, 732, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CURRZERO" , 2, 1, 732, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 732, "RAZ", 1, 0, 0, 0ull},
|
|
{"MODE" , 0, 2, 733, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 733, "RAZ", 1, 0, 0, 0ull},
|
|
{"QID7" , 0, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDX3" , 1, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 734, "RAZ", 1, 0, 0, 0ull},
|
|
{"INDEX" , 0, 8, 735, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 8, 8, 735, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 735, "RAZ", 1, 0, 0, 0ull},
|
|
{"ADR0" , 0, 1, 736, "RO", 0, 0, 0ull, 0ull},
|
|
{"ADR1" , 1, 1, 736, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEND0" , 2, 1, 736, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEND1" , 3, 1, 736, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBR0" , 4, 1, 736, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBR1" , 5, 1, 736, "RO", 0, 0, 0ull, 0ull},
|
|
{"FIDX" , 6, 1, 736, "RO", 0, 0, 0ull, 0ull},
|
|
{"INDEX" , 7, 1, 736, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBT" , 8, 1, 736, "RO", 0, 0, 0ull, 0ull},
|
|
{"CAM" , 9, 1, 736, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_15" , 10, 6, 736, "RAZ", 1, 1, 0, 0},
|
|
{"PP" , 16, 12, 736, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 736, "RAZ", 1, 1, 0, 0},
|
|
{"DS_PC" , 0, 32, 737, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 737, "RAZ", 1, 1, 0, 0},
|
|
{"SBE" , 0, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DBE" , 1, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SBE_IE" , 2, 1, 738, "R/W", 0, 1, 0ull, 0},
|
|
{"DBE_IE" , 3, 1, 738, "R/W", 0, 1, 0ull, 0},
|
|
{"SYN" , 4, 5, 738, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_9_11" , 9, 3, 738, "RAZ", 1, 1, 0, 0},
|
|
{"RPE" , 12, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPE_IE" , 13, 1, 738, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_15" , 14, 2, 738, "RAZ", 1, 1, 0, 0},
|
|
{"IOP" , 16, 13, 738, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_31" , 29, 3, 738, "RAZ", 1, 1, 0, 0},
|
|
{"IOP_IE" , 32, 13, 738, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_45_63" , 45, 19, 738, "RAZ", 1, 1, 0, 0},
|
|
{"NBR_THR" , 0, 5, 739, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PFR_DIS" , 5, 1, 739, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 739, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 32, 740, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 740, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 32, 741, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 741, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_INT" , 0, 8, 742, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 742, "RAZ", 1, 1, 0, 0},
|
|
{"INT_EN" , 0, 8, 743, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 743, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_THR" , 0, 32, 744, "R/W", 0, 1, 4294967295ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 744, "RAZ", 1, 1, 0, 0},
|
|
{"NOS_CNT" , 0, 12, 745, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_12_63" , 12, 52, 745, "RAZ", 1, 1, 0, 0},
|
|
{"NW_TIM" , 0, 10, 746, "R/W", 0, 0, 0ull, 1023ull},
|
|
{"RESERVED_10_63" , 10, 54, 746, "RAZ", 1, 1, 0, 0},
|
|
{"RST_MSK" , 0, 8, 747, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 747, "RAZ", 1, 1, 0, 0},
|
|
{"GRP_MSK" , 0, 16, 748, "R/W", 0, 0, 65535ull, 65535ull},
|
|
{"QOS0_PRI" , 16, 4, 748, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS1_PRI" , 20, 4, 748, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS2_PRI" , 24, 4, 748, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS3_PRI" , 28, 4, 748, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS4_PRI" , 32, 4, 748, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS5_PRI" , 36, 4, 748, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS6_PRI" , 40, 4, 748, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS7_PRI" , 44, 4, 748, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 748, "RAZ", 1, 1, 0, 0},
|
|
{"RND" , 0, 8, 749, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P1" , 8, 8, 749, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P2" , 16, 8, 749, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P3" , 24, 8, 749, "R/W", 0, 1, 255ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 749, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_THR" , 0, 11, 750, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_11_11" , 11, 1, 750, "RAZ", 1, 1, 0, 0},
|
|
{"MAX_THR" , 12, 11, 750, "R/W", 0, 1, 2047ull, 0},
|
|
{"RESERVED_23_23" , 23, 1, 750, "RAZ", 1, 1, 0, 0},
|
|
{"FREE_CNT" , 24, 12, 750, "RO", 0, 1, 2027ull, 0},
|
|
{"BUF_CNT" , 36, 12, 750, "RO", 0, 1, 0ull, 0},
|
|
{"DES_CNT" , 48, 12, 750, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 750, "RAZ", 1, 1, 0, 0},
|
|
{"TS_PC" , 0, 32, 751, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 751, "RAZ", 1, 1, 0, 0},
|
|
{"WA_PC" , 0, 32, 752, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 752, "RAZ", 1, 1, 0, 0},
|
|
{"WA_PC" , 0, 32, 753, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 753, "RAZ", 1, 1, 0, 0},
|
|
{"WQ_INT" , 0, 16, 754, "R/W1C", 0, 1, 0ull, 0},
|
|
{"IQ_DIS" , 16, 16, 754, "R/W1", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 754, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 12, 755, "RO", 0, 1, 0ull, 0},
|
|
{"DS_CNT" , 12, 12, 755, "RO", 0, 1, 0ull, 0},
|
|
{"TC_CNT" , 24, 4, 755, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_63" , 28, 36, 755, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 756, "RAZ", 1, 1, 0, 0},
|
|
{"PC_THR" , 8, 20, 756, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_31" , 28, 4, 756, "RAZ", 1, 1, 0, 0},
|
|
{"PC" , 32, 28, 756, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 756, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_THR" , 0, 11, 757, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_11_11" , 11, 1, 757, "RAZ", 1, 1, 0, 0},
|
|
{"DS_THR" , 12, 11, 757, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_23_23" , 23, 1, 757, "RAZ", 1, 1, 0, 0},
|
|
{"TC_THR" , 24, 4, 757, "R/W", 0, 1, 0ull, 0},
|
|
{"TC_EN" , 28, 1, 757, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 757, "RAZ", 1, 1, 0, 0},
|
|
{"WS_PC" , 0, 32, 758, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 758, "RAZ", 1, 1, 0, 0},
|
|
{"IWORD" , 0, 64, 759, "RO", 1, 1, 0, 0},
|
|
{"P_DAT" , 0, 64, 760, "RO", 1, 1, 0, 0},
|
|
{"Q_DAT" , 0, 64, 761, "RO", 1, 1, 0, 0},
|
|
{"DAT" , 0, 2, 762, "RO", 1, 0, 0, 0ull},
|
|
{"NCB_INB" , 2, 2, 762, "RO", 1, 0, 0, 0ull},
|
|
{"NCB_OUB" , 4, 1, 762, "RO", 1, 0, 0, 0ull},
|
|
{"STA" , 5, 1, 762, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 762, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PTR" , 0, 33, 763, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 33, 13, 763, "R/W", 0, 1, 0ull, 0},
|
|
{"POOL" , 46, 3, 763, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB" , 49, 9, 763, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_58_63" , 58, 6, 763, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 0, 1, 764, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STORE_LE" , 1, 1, 764, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAX_READ" , 2, 4, 764, "R/W", 0, 0, 8ull, 8ull},
|
|
{"RESERVED_6_63" , 6, 58, 764, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STATE" , 0, 5, 765, "RO", 1, 1, 0, 0},
|
|
{"COMMIT" , 5, 1, 765, "RO", 1, 1, 0, 0},
|
|
{"OWORDPV" , 6, 1, 765, "RO", 1, 1, 0, 0},
|
|
{"OWORDQV" , 7, 1, 765, "RO", 1, 1, 0, 0},
|
|
{"IWIDX" , 8, 6, 765, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_14_15" , 14, 2, 765, "RAZ", 1, 1, 0, 0},
|
|
{"IRIDX" , 16, 6, 765, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_22_31" , 22, 10, 765, "RAZ", 1, 1, 0, 0},
|
|
{"LOOP" , 32, 25, 765, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_57_63" , 57, 7, 765, "RAZ", 1, 1, 0, 0},
|
|
{"CWORD" , 0, 64, 766, "RO", 1, 1, 0, 0},
|
|
{"PTR" , 0, 40, 767, "RO", 1, 1, 0, 0},
|
|
{"SIZE" , 40, 16, 767, "RO", 1, 1, 0, 0},
|
|
{"FLAGS" , 56, 8, 767, "RO", 1, 1, 0, 0},
|
|
{"INDEX" , 0, 8, 768, "RO", 1, 1, 0, 0},
|
|
{"SOD" , 8, 1, 768, "RO", 1, 1, 0, 0},
|
|
{"EOD" , 9, 1, 768, "RO", 1, 1, 0, 0},
|
|
{"WC" , 10, 1, 768, "RO", 1, 1, 0, 0},
|
|
{"P" , 11, 1, 768, "RO", 1, 1, 0, 0},
|
|
{"Q" , 12, 1, 768, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_13_63" , 13, 51, 768, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 15, 769, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_15_63" , 15, 49, 769, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OWORDP" , 0, 64, 770, "RO", 1, 1, 0, 0},
|
|
{"OWORDQ" , 0, 64, 771, "RO", 1, 1, 0, 0},
|
|
{"RWORD" , 0, 64, 772, "RO", 1, 1, 0, 0},
|
|
{"N0CREDS" , 0, 4, 773, "RO", 0, 0, 8ull, 0ull},
|
|
{"N1CREDS" , 4, 4, 773, "RO", 0, 0, 8ull, 0ull},
|
|
{"POWCREDS" , 8, 2, 773, "RO", 0, 0, 2ull, 0ull},
|
|
{"RESERVED_10_11" , 10, 2, 773, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FPACREDS" , 12, 2, 773, "RO", 0, 0, 1ull, 0ull},
|
|
{"WCCREDS" , 14, 2, 773, "RO", 0, 0, 0ull, 0ull},
|
|
{"NIWIDX0" , 16, 4, 773, "RO", 1, 1, 0, 0},
|
|
{"NIRIDX0" , 20, 4, 773, "RO", 1, 1, 0, 0},
|
|
{"NIWIDX1" , 24, 4, 773, "RO", 1, 1, 0, 0},
|
|
{"NIRIDX1" , 28, 4, 773, "RO", 1, 1, 0, 0},
|
|
{"NIRVAL6" , 32, 5, 773, "RO", 1, 1, 0, 0},
|
|
{"NIRARB6" , 37, 1, 773, "RO", 1, 1, 0, 0},
|
|
{"NIRQUE6" , 38, 2, 773, "RO", 1, 1, 0, 0},
|
|
{"NIROPC6" , 40, 3, 773, "RO", 1, 1, 0, 0},
|
|
{"NIRVAL7" , 43, 5, 773, "RO", 1, 1, 0, 0},
|
|
{"NIRQUE7" , 48, 2, 773, "RO", 1, 1, 0, 0},
|
|
{"NIROPC7" , 50, 3, 773, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_53_63" , 53, 11, 773, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PTR" , 0, 40, 774, "RO", 1, 1, 0, 0},
|
|
{"SIZE" , 40, 16, 774, "RO", 1, 1, 0, 0},
|
|
{"CNT" , 56, 8, 774, "RO", 1, 1, 0, 0},
|
|
{"CNT" , 0, 15, 775, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_15_63" , 15, 49, 775, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PTR" , 0, 40, 776, "RO", 1, 1, 0, 0},
|
|
{"SIZE" , 40, 16, 776, "RO", 1, 1, 0, 0},
|
|
{"FLAGS" , 56, 8, 776, "RO", 1, 1, 0, 0},
|
|
{"INDEX" , 0, 8, 777, "RO", 1, 1, 0, 0},
|
|
{"MUL" , 8, 8, 777, "RO", 1, 1, 0, 0},
|
|
{"P" , 16, 1, 777, "RO", 1, 1, 0, 0},
|
|
{"Q" , 17, 1, 777, "RO", 1, 1, 0, 0},
|
|
{"INI" , 18, 1, 777, "RO", 1, 1, 0, 0},
|
|
{"EOD" , 19, 1, 777, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_20_63" , 20, 44, 777, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 0, 1, 778, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 778, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 0, 1, 779, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 779, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"COEFFS" , 0, 8, 780, "R/W", 0, 0, 29ull, 29ull},
|
|
{"RESERVED_8_63" , 8, 56, 780, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"INDEX" , 0, 16, 781, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 16, 16, 781, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 781, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MEM" , 0, 1, 782, "RO", 0, 0, 0ull, 0ull},
|
|
{"RRC" , 1, 1, 782, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 782, "RAZ", 1, 1, 0, 0},
|
|
{"ENT_EN" , 0, 1, 783, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNG_EN" , 1, 1, 783, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNM_RST" , 2, 1, 783, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNG_RST" , 3, 1, 783, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EXP_ENT" , 4, 1, 783, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENT_SEL" , 5, 4, 783, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 783, "RAZ", 1, 1, 0, 0},
|
|
{"PHASE" , 0, 8, 784, "R/W", 0, 0, 100ull, 100ull},
|
|
{"SAMPLE" , 8, 4, 784, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PREAMBLE" , 12, 1, 784, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CLK_IDLE" , 13, 1, 784, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_14" , 14, 1, 784, "RAZ", 1, 1, 0, 0},
|
|
{"SAMPLE_MODE" , 15, 1, 784, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SAMPLE_HI" , 16, 5, 784, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_23" , 21, 3, 784, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 24, 1, 784, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_63" , 25, 39, 784, "RAZ", 1, 1, 0, 0},
|
|
{"REG_ADR" , 0, 5, 785, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 785, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_ADR" , 8, 5, 785, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_13_15" , 13, 3, 785, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_OP" , 16, 2, 785, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 785, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 786, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 786, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 787, "RO", 0, 1, 0ull, 0},
|
|
{"VAL" , 16, 1, 787, "RO", 0, 1, 0ull, 0},
|
|
{"PENDING" , 17, 1, 787, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 787, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 788, "R/W", 0, 1, 0ull, 0},
|
|
{"VAL" , 16, 1, 788, "RO", 0, 1, 0ull, 0},
|
|
{"PENDING" , 17, 1, 788, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 788, "RAZ", 1, 1, 0, 0},
|
|
{"INTERVAL" , 0, 22, 789, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 789, "RAZ", 1, 0, 0, 0ull},
|
|
{"COUNT" , 24, 22, 789, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_46_46" , 46, 1, 789, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENA" , 47, 1, 789, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 789, "RAZ", 1, 0, 0, 0ull},
|
|
{"BSIZE" , 0, 20, 790, "RO", 1, 0, 0, 0ull},
|
|
{"BASE" , 20, 31, 790, "RO", 1, 0, 0, 0ull},
|
|
{"BUCKET" , 51, 13, 790, "RO", 1, 0, 0, 0ull},
|
|
{"BUCKET" , 0, 7, 791, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 791, "RAZ", 1, 0, 0, 0ull},
|
|
{"CSIZE" , 8, 13, 791, "RO", 1, 0, 0, 0ull},
|
|
{"CPOOL" , 21, 3, 791, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 791, "RAZ", 1, 0, 0, 0ull},
|
|
{"RING" , 0, 4, 792, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NUM_BUCKETS" , 4, 20, 792, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIRST_BUCKET" , 24, 31, 792, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_55_63" , 55, 9, 792, "RAZ", 1, 0, 0, 0ull},
|
|
{"RING" , 0, 4, 793, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTERVAL" , 4, 22, 793, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WORDS_PER_CHUNK" , 26, 13, 793, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 39, 3, 793, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENABLE" , 42, 1, 793, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_43_63" , 43, 21, 793, "RAZ", 1, 0, 0, 0ull},
|
|
{"CTL" , 0, 1, 794, "RO", 1, 0, 0, 0ull},
|
|
{"NCB" , 1, 1, 794, "RO", 1, 0, 0, 0ull},
|
|
{"STA" , 2, 2, 794, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 794, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 16, 795, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 795, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENABLE_TIMERS" , 0, 1, 796, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENABLE_DWB" , 1, 1, 796, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 2, 1, 796, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 796, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 16, 797, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 797, "RAZ", 1, 0, 0, 0ull},
|
|
{"INDEX" , 0, 8, 798, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 8, 8, 798, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 798, "RAZ", 1, 0, 0, 0ull},
|
|
{"TDF0" , 0, 1, 799, "RO", 0, 0, 0ull, 0ull},
|
|
{"TDF1" , 1, 1, 799, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCF" , 2, 1, 799, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 799, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ENA" , 0, 1, 800, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WRAP" , 1, 1, 800, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRIG_CTL" , 2, 2, 800, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIME_GRN" , 4, 3, 800, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FULL_THR" , 7, 2, 800, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CIU_TRG" , 9, 1, 800, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CIU_THR" , 10, 1, 800, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_TRG" , 11, 1, 800, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_THR" , 12, 1, 800, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_ENA" , 13, 1, 800, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IGNORE_O" , 14, 1, 800, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 800, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WPTR" , 0, 8, 801, "RO", 0, 0, 0ull, 0ull},
|
|
{"RPTR" , 8, 8, 801, "RO", 0, 0, 0ull, 0ull},
|
|
{"CYCLES" , 16, 48, 801, "RO", 0, 0, 0ull, 0ull},
|
|
{"WPTR" , 0, 10, 802, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_11" , 10, 2, 802, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RPTR" , 12, 10, 802, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 802, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CYCLES" , 24, 40, 802, "RO", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 803, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 803, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 804, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 804, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 805, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 805, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 805, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 805, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 805, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 805, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 805, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 805, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 805, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 805, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 805, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 805, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 805, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 805, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 805, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 805, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SAA" , 16, 1, 805, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_17_63" , 17, 47, 805, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 806, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 806, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 806, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 806, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 806, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 806, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 806, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 806, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 806, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 806, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 806, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 806, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 807, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 807, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 807, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 807, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 807, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 807, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CIU_TRG" , 0, 1, 808, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CIU_THR" , 1, 1, 808, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MCD0_TRG" , 2, 1, 808, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MCD0_THR" , 3, 1, 808, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 808, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DATA" , 0, 64, 809, "RO", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 810, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 810, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 811, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 811, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 812, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 812, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 812, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 812, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 812, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 812, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 812, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 812, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 812, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 812, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 812, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 812, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 812, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 812, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 812, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 812, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SAA" , 16, 1, 812, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_17_63" , 17, 47, 812, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 813, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 813, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 813, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 813, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 813, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 813, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 813, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 813, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 813, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 813, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 813, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 813, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 814, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 814, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 814, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 814, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 814, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 814, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 815, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 815, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 816, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 816, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 817, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 817, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 817, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 817, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 817, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 817, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 817, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 817, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 817, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 817, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 817, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 817, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 817, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 817, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 817, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 817, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SAA" , 16, 1, 817, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_17_63" , 17, 47, 817, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 818, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 818, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 818, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 818, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 818, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 818, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 818, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 818, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 818, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 818, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 818, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 818, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 819, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 819, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 819, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 819, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 819, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 819, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"INEPINT" , 0, 16, 820, "RO", 0, 0, 0ull, 0ull},
|
|
{"OUTEPINT" , 16, 16, 820, "RO", 0, 0, 0ull, 0ull},
|
|
{"INEPMSK" , 0, 16, 821, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OUTEPMSK" , 16, 16, 821, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DEVSPD" , 0, 2, 822, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NZSTSOUTHSHK" , 2, 1, 822, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 822, "RAZ", 1, 1, 0, 0},
|
|
{"DEVADDR" , 4, 7, 822, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PERFRINT" , 11, 2, 822, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_17" , 13, 5, 822, "RAZ", 1, 1, 0, 0},
|
|
{"EPMISCNT" , 18, 5, 822, "R/W", 0, 0, 8ull, 0ull},
|
|
{"RESERVED_23_31" , 23, 9, 822, "RAZ", 1, 1, 0, 0},
|
|
{"RMTWKUPSIG" , 0, 1, 823, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SFTDISCON" , 1, 1, 823, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GNPINNAKSTS" , 2, 1, 823, "RO", 0, 0, 0ull, 0ull},
|
|
{"GOUTNAKSTS" , 3, 1, 823, "RO", 0, 0, 0ull, 0ull},
|
|
{"TSTCTL" , 4, 3, 823, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SGNPINNAK" , 7, 1, 823, "WO", 0, 0, 0ull, 0ull},
|
|
{"CGNPINNAK" , 8, 1, 823, "WO", 0, 0, 0ull, 0ull},
|
|
{"SGOUTNAK" , 9, 1, 823, "WO", 0, 0, 0ull, 0ull},
|
|
{"CGOUTNAK" , 10, 1, 823, "WO", 0, 0, 0ull, 0ull},
|
|
{"PWRONPRGDONE" , 11, 1, 823, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_31" , 12, 20, 823, "RAZ", 1, 1, 0, 0},
|
|
{"MPS" , 0, 11, 824, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NEXTEP" , 11, 4, 824, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBACTEP" , 15, 1, 824, "R/W", 0, 0, 1ull, 0ull},
|
|
{"DPID" , 16, 1, 824, "RO", 0, 0, 0ull, 0ull},
|
|
{"NAKSTS" , 17, 1, 824, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTYPE" , 18, 2, 824, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 824, "RAZ", 1, 1, 0, 0},
|
|
{"STALL" , 21, 1, 824, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFNUM" , 22, 4, 824, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNAK" , 26, 1, 824, "WO", 0, 0, 0ull, 0ull},
|
|
{"SNAK" , 27, 1, 824, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD0PID" , 28, 1, 824, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD1PID" , 29, 1, 824, "WO", 0, 0, 0ull, 0ull},
|
|
{"EPDIS" , 30, 1, 824, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPENA" , 31, 1, 824, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XFERCOMPL" , 0, 1, 825, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLD" , 1, 1, 825, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AHBERR" , 2, 1, 825, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TIMEOUT" , 3, 1, 825, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTKNTXFEMP" , 4, 1, 825, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTKNEPMIS" , 5, 1, 825, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INEPNAKEFF" , 6, 1, 825, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_31" , 7, 25, 825, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPLMSK" , 0, 1, 826, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLDMSK" , 1, 1, 826, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AHBERRMSK" , 2, 1, 826, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMEOUTMSK" , 3, 1, 826, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTKNTXFEMPMSK" , 4, 1, 826, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTKNEPMISMSK" , 5, 1, 826, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INEPNAKEFFMSK" , 6, 1, 826, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_31" , 7, 25, 826, "RAZ", 1, 1, 0, 0},
|
|
{"XFERSIZE" , 0, 19, 827, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKTCNT" , 19, 10, 827, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MC" , 29, 2, 827, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_31" , 31, 1, 827, "RAZ", 1, 1, 0, 0},
|
|
{"MPS" , 0, 11, 828, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_14" , 11, 4, 828, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"USBACTEP" , 15, 1, 828, "R/W", 0, 0, 1ull, 0ull},
|
|
{"DPID" , 16, 1, 828, "RO", 0, 0, 0ull, 0ull},
|
|
{"NAKSTS" , 17, 1, 828, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTYPE" , 18, 2, 828, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SNP" , 20, 1, 828, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STALL" , 21, 1, 828, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_25" , 22, 4, 828, "RAZ", 1, 1, 0, 0},
|
|
{"CNAK" , 26, 1, 828, "WO", 0, 0, 0ull, 0ull},
|
|
{"SNAK" , 27, 1, 828, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD0PID" , 28, 1, 828, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD1PID" , 29, 1, 828, "WO", 0, 0, 0ull, 0ull},
|
|
{"EPDIS" , 30, 1, 828, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPENA" , 31, 1, 828, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XFERCOMPL" , 0, 1, 829, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLD" , 1, 1, 829, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AHBERR" , 2, 1, 829, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SETUP" , 3, 1, 829, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OUTTKNEPDIS" , 4, 1, 829, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 829, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPLMSK" , 0, 1, 830, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLDMSK" , 1, 1, 830, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AHBERRMSK" , 2, 1, 830, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SETUPMSK" , 3, 1, 830, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OUTTKNEPDISMSK" , 4, 1, 830, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 830, "RAZ", 1, 1, 0, 0},
|
|
{"XFERSIZE" , 0, 19, 831, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKTCNT" , 19, 10, 831, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MC" , 29, 2, 831, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_31" , 31, 1, 831, "RAZ", 1, 1, 0, 0},
|
|
{"DPTXFSTADDR" , 0, 16, 832, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPTXFSIZE" , 16, 16, 832, "RO", 0, 0, 1896ull, 1896ull},
|
|
{"SUSPSTS" , 0, 1, 833, "RO", 0, 0, 0ull, 0ull},
|
|
{"ENUMSPD" , 1, 2, 833, "RO", 0, 0, 0ull, 0ull},
|
|
{"ERRTICERR" , 3, 1, 833, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 833, "RAZ", 1, 1, 0, 0},
|
|
{"SOFFN" , 8, 14, 833, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_31" , 22, 10, 833, "RAZ", 1, 1, 0, 0},
|
|
{"INTKNWPTR" , 0, 5, 834, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_6" , 5, 2, 834, "RAZ", 1, 1, 0, 0},
|
|
{"WRAPBIT" , 7, 1, 834, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 8, 24, 834, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 0, 32, 835, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 0, 32, 836, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 0, 32, 837, "RO", 0, 0, 0ull, 0ull},
|
|
{"GLBLINTRMSK" , 0, 1, 838, "R/W", 0, 0, 0ull, 1ull},
|
|
{"HBSTLEN" , 1, 4, 838, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMAEN" , 5, 1, 838, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_6" , 6, 1, 838, "RAZ", 1, 1, 0, 0},
|
|
{"NPTXFEMPLVL" , 7, 1, 838, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PTXFEMPLVL" , 8, 1, 838, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_9_31" , 9, 23, 838, "RAZ", 1, 1, 0, 0},
|
|
{"EPDIR" , 0, 32, 839, "RO", 0, 0, 0ull, 0ull},
|
|
{"OTGMODE" , 0, 3, 840, "RO", 0, 0, 2ull, 2ull},
|
|
{"OTGARCH" , 3, 2, 840, "RO", 0, 0, 1ull, 1ull},
|
|
{"SINGPNT" , 5, 1, 840, "RO", 0, 0, 0ull, 0ull},
|
|
{"HSPHYTYPE" , 6, 2, 840, "RO", 0, 0, 1ull, 1ull},
|
|
{"FSPHYTYPE" , 8, 2, 840, "RO", 0, 0, 0ull, 0ull},
|
|
{"NUMDEVEPS" , 10, 4, 840, "RO", 0, 0, 4ull, 4ull},
|
|
{"NUMHSTCHNL" , 14, 4, 840, "RO", 0, 0, 7ull, 7ull},
|
|
{"PERIOSUPPORT" , 18, 1, 840, "RO", 0, 0, 1ull, 1ull},
|
|
{"DYNFIFOSIZING" , 19, 1, 840, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_20_21" , 20, 2, 840, "RAZ", 1, 1, 0, 0},
|
|
{"NPTXQDEPTH" , 22, 2, 840, "RO", 0, 0, 2ull, 2ull},
|
|
{"PTXQDEPTH" , 24, 2, 840, "RO", 0, 0, 2ull, 2ull},
|
|
{"TKNQDEPTH" , 26, 5, 840, "RO", 0, 0, 30ull, 30ull},
|
|
{"RESERVED_31_31" , 31, 1, 840, "RAZ", 1, 1, 0, 0},
|
|
{"XFERSIZEWIDTH" , 0, 4, 841, "RO", 0, 0, 8ull, 8ull},
|
|
{"PKTSIZEWIDTH" , 4, 3, 841, "RO", 0, 0, 6ull, 6ull},
|
|
{"OTGEN" , 7, 1, 841, "RO", 0, 0, 1ull, 1ull},
|
|
{"I2C_SELECTION" , 8, 1, 841, "RO", 0, 0, 0ull, 0ull},
|
|
{"VENDOR_CONTROL_INTERFACE_SUPPORT", 9, 1, 841, "RO", 0, 0, 0ull, 0ull},
|
|
{"OPTFEATURE" , 10, 1, 841, "RO", 0, 0, 1ull, 1ull},
|
|
{"RSTTYPE" , 11, 1, 841, "RO", 0, 0, 1ull, 1ull},
|
|
{"AHBPHYSYNC" , 12, 1, 841, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 841, "RAZ", 1, 1, 0, 0},
|
|
{"DFIFODEPTH" , 16, 16, 841, "RO", 0, 0, 1824ull, 1824ull},
|
|
{"NUMDEVPERIOEPS" , 0, 4, 842, "RO", 0, 0, 4ull, 4ull},
|
|
{"ENABLEPWROPT" , 4, 1, 842, "RO", 0, 0, 0ull, 0ull},
|
|
{"AHBFREQ" , 5, 1, 842, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_13" , 6, 8, 842, "RAZ", 1, 1, 0, 0},
|
|
{"PHYDATAWIDTH" , 14, 2, 842, "RO", 0, 0, 1ull, 1ull},
|
|
{"NUMCTLEPS" , 16, 4, 842, "RO", 0, 0, 4ull, 4ull},
|
|
{"IDDGFLTR" , 20, 1, 842, "RO", 0, 0, 1ull, 1ull},
|
|
{"VBUSVALIDFLTR" , 21, 1, 842, "RO", 0, 0, 1ull, 1ull},
|
|
{"AVALIDFLTR" , 22, 1, 842, "RO", 0, 0, 0ull, 0ull},
|
|
{"BVALIDFLTR" , 23, 1, 842, "RO", 0, 0, 0ull, 0ull},
|
|
{"SESSENDFLTR" , 24, 1, 842, "RO", 0, 0, 0ull, 0ull},
|
|
{"ENDEDTRFIFO" , 25, 1, 842, "RO", 0, 0, 0ull, 0ull},
|
|
{"NUMDEVMODINEND" , 26, 4, 842, "RO", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_30_31" , 30, 2, 842, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 843, "RAZ", 1, 1, 0, 0},
|
|
{"MODEMISMSK" , 1, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OTGINTMSK" , 2, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SOFMSK" , 3, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RXFLVLMSK" , 4, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NPTXFEMPMSK" , 5, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GINNAKEFFMSK" , 6, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GOUTNAKEFFMSK" , 7, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ULPICKINTMSK" , 8, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"I2CINT" , 9, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ERLYSUSPMSK" , 10, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBSUSPMSK" , 11, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBRSTMSK" , 12, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENUMDONEMSK" , 13, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ISOOUTDROPMSK" , 14, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EOPFMSK" , 15, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 843, "RAZ", 1, 1, 0, 0},
|
|
{"EPMISMSK" , 17, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INEPINTMSK" , 18, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OEPINTMSK" , 19, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INCOMPISOINMSK" , 20, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INCOMPLPMSK" , 21, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FETSUSPMSK" , 22, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 843, "RAZ", 1, 1, 0, 0},
|
|
{"PRTINTMSK" , 24, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HCHINTMSK" , 25, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PTXFEMPMSK" , 26, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 843, "RAZ", 1, 1, 0, 0},
|
|
{"CONIDSTSCHNGMSK" , 28, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DISCONNINTMSK" , 29, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SESSREQINTMSK" , 30, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WKUPINTMSK" , 31, 1, 843, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CURMOD" , 0, 1, 844, "RO", 0, 0, 0ull, 0ull},
|
|
{"MODEMIS" , 1, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OTGINT" , 2, 1, 844, "RO", 0, 0, 0ull, 0ull},
|
|
{"SOF" , 3, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXFLVL" , 4, 1, 844, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPTXFEMP" , 5, 1, 844, "RO", 0, 0, 0ull, 0ull},
|
|
{"GINNAKEFF" , 6, 1, 844, "RO", 0, 0, 0ull, 0ull},
|
|
{"GOUTNAKEFF" , 7, 1, 844, "RO", 0, 0, 0ull, 0ull},
|
|
{"ULPICKINT" , 8, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I2CINT" , 9, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ERLYSUSP" , 10, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USBSUSP" , 11, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USBRST" , 12, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ENUMDONE" , 13, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ISOOUTDROP" , 14, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EOPF" , 15, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 844, "RAZ", 1, 1, 0, 0},
|
|
{"EPMIS" , 17, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IEPINT" , 18, 1, 844, "RO", 0, 0, 0ull, 0ull},
|
|
{"OEPINT" , 19, 1, 844, "RO", 0, 0, 0ull, 0ull},
|
|
{"INCOMPISOIN" , 20, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INCOMPLP" , 21, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FETSUSP" , 22, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 844, "RAZ", 1, 1, 0, 0},
|
|
{"PRTINT" , 24, 1, 844, "RO", 0, 0, 0ull, 0ull},
|
|
{"HCHINT" , 25, 1, 844, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTXFEMP" , 26, 1, 844, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 844, "RAZ", 1, 1, 0, 0},
|
|
{"CONIDSTSCHNG" , 28, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DISCONNINT" , 29, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SESSREQINT" , 30, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WKUPINT" , 31, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NPTXFSTADDR" , 0, 16, 845, "R/W", 0, 0, 1824ull, 456ull},
|
|
{"NPTXFDEP" , 16, 16, 845, "R/W", 0, 0, 1824ull, 912ull},
|
|
{"NPTXFSPCAVAIL" , 0, 16, 846, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPTXQSPCAVAIL" , 16, 8, 846, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPTXQTOP" , 24, 7, 846, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_31" , 31, 1, 846, "RAZ", 1, 1, 0, 0},
|
|
{"SESREQSCS" , 0, 1, 847, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SESREQ" , 1, 1, 847, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_7" , 2, 6, 847, "RAZ", 1, 1, 0, 0},
|
|
{"HSTNEGSCS" , 8, 1, 847, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HNPREQ" , 9, 1, 847, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HSTSETHNPEN" , 10, 1, 847, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DEVHNPEN" , 11, 1, 847, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_15" , 12, 4, 847, "RAZ", 1, 1, 0, 0},
|
|
{"CONIDSTS" , 16, 1, 847, "RO", 1, 1, 0, 0},
|
|
{"DBNCTIME" , 17, 1, 847, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASESVLD" , 18, 1, 847, "RO", 1, 1, 0, 0},
|
|
{"BSESVLD" , 19, 1, 847, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_20_31" , 20, 12, 847, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 848, "RAZ", 1, 1, 0, 0},
|
|
{"SESENDDET" , 2, 1, 848, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_7" , 3, 5, 848, "RAZ", 1, 1, 0, 0},
|
|
{"SESREQSUCSTSCHNG" , 8, 1, 848, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"HSTNEGSUCSTSCHNG" , 9, 1, 848, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_16" , 10, 7, 848, "RAZ", 1, 1, 0, 0},
|
|
{"HSTNEGDET" , 17, 1, 848, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ADEVTOUTCHG" , 18, 1, 848, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DBNCEDONE" , 19, 1, 848, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 848, "RAZ", 1, 1, 0, 0},
|
|
{"CSFTRST" , 0, 1, 849, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HSFTRST" , 1, 1, 849, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMCNTRRST" , 2, 1, 849, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTKNQFLSH" , 3, 1, 849, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RXFFLSH" , 4, 1, 849, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFFLSH" , 5, 1, 849, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFNUM" , 6, 5, 849, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_29" , 11, 19, 849, "RAZ", 1, 1, 0, 0},
|
|
{"DMAREQ" , 30, 1, 849, "RO", 0, 0, 0ull, 0ull},
|
|
{"AHBIDLE" , 31, 1, 849, "RO", 0, 0, 1ull, 1ull},
|
|
{"RXFDEP" , 0, 16, 850, "R/W", 0, 0, 1824ull, 456ull},
|
|
{"RESERVED_16_31" , 16, 16, 850, "RAZ", 1, 1, 0, 0},
|
|
{"EPNUM" , 0, 4, 851, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 851, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 851, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 851, "RO", 0, 0, 0ull, 0ull},
|
|
{"FN" , 21, 4, 851, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_31" , 25, 7, 851, "RAZ", 1, 1, 0, 0},
|
|
{"CHNUM" , 0, 4, 852, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 852, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 852, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 852, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 852, "RAZ", 1, 1, 0, 0},
|
|
{"EPNUM" , 0, 4, 853, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 853, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 853, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 853, "RO", 0, 0, 0ull, 0ull},
|
|
{"FN" , 21, 4, 853, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_31" , 25, 7, 853, "RAZ", 1, 1, 0, 0},
|
|
{"CHNUM" , 0, 4, 854, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 854, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 854, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 854, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 854, "RAZ", 1, 1, 0, 0},
|
|
{"SYNOPSYSID" , 0, 32, 855, "RO", 1, 1, 0, 0},
|
|
{"TOUTCAL" , 0, 3, 856, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHYIF" , 3, 1, 856, "RO", 0, 0, 1ull, 1ull},
|
|
{"ULPI_UTMI_SEL" , 4, 1, 856, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSINTF" , 5, 1, 856, "WO", 0, 0, 0ull, 0ull},
|
|
{"PHYSEL" , 6, 1, 856, "WO", 0, 0, 0ull, 0ull},
|
|
{"DDRSEL" , 7, 1, 856, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SRPCAP" , 8, 1, 856, "RO", 0, 0, 0ull, 0ull},
|
|
{"HNPCAP" , 9, 1, 856, "RO", 0, 0, 0ull, 0ull},
|
|
{"USBTRDTIM" , 10, 4, 856, "R/W", 0, 0, 5ull, 5ull},
|
|
{"RESERVED_14_14" , 14, 1, 856, "RAZ", 1, 1, 0, 0},
|
|
{"PHYLPWRCLKSEL" , 15, 1, 856, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OTGI2CSEL" , 16, 1, 856, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 856, "RAZ", 1, 1, 0, 0},
|
|
{"HAINT" , 0, 16, 857, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_31" , 16, 16, 857, "RAZ", 1, 1, 0, 0},
|
|
{"HAINTMSK" , 0, 16, 858, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_31" , 16, 16, 858, "RAZ", 1, 1, 0, 0},
|
|
{"MPS" , 0, 11, 859, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPNUM" , 11, 4, 859, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPDIR" , 15, 1, 859, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 859, "RAZ", 1, 1, 0, 0},
|
|
{"LSPDDEV" , 17, 1, 859, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPTYPE" , 18, 2, 859, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EC" , 20, 2, 859, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DEVADDR" , 22, 7, 859, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ODDFRM" , 29, 1, 859, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHDIS" , 30, 1, 859, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHENA" , 31, 1, 859, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSLSPCLKSEL" , 0, 2, 860, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSLSSUPP" , 2, 1, 860, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_31" , 3, 29, 860, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPL" , 0, 1, 861, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CHHLTD" , 1, 1, 861, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AHBERR" , 2, 1, 861, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"STALL" , 3, 1, 861, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NAK" , 4, 1, 861, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ACK" , 5, 1, 861, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NYET" , 6, 1, 861, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"XACTERR" , 7, 1, 861, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BBLERR" , 8, 1, 861, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FRMOVRUN" , 9, 1, 861, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DATATGLERR" , 10, 1, 861, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_31" , 11, 21, 861, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPLMSK" , 0, 1, 862, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHHLTDMSK" , 1, 1, 862, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AHBERRMSK" , 2, 1, 862, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STALLMSK" , 3, 1, 862, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NAKMSK" , 4, 1, 862, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ACKMSK" , 5, 1, 862, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NYETMSK" , 6, 1, 862, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XACTERRMSK" , 7, 1, 862, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BBLERRMSK" , 8, 1, 862, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMOVRUNMSK" , 9, 1, 862, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DATATGLERRMSK" , 10, 1, 862, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_31" , 11, 21, 862, "RAZ", 1, 1, 0, 0},
|
|
{"PRTADDR" , 0, 7, 863, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HUBADDR" , 7, 7, 863, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XACTPOS" , 14, 2, 863, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COMPSPLT" , 16, 1, 863, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_30" , 17, 14, 863, "RAZ", 1, 1, 0, 0},
|
|
{"SPLTENA" , 31, 1, 863, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XFERSIZE" , 0, 19, 864, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKTCNT" , 19, 10, 864, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PID" , 29, 2, 864, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DOPNG" , 31, 1, 864, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRINT" , 0, 16, 865, "R/W", 0, 0, 2959ull, 3750ull},
|
|
{"RESERVED_16_31" , 16, 16, 865, "RAZ", 1, 1, 0, 0},
|
|
{"FRNUM" , 0, 16, 866, "RO", 0, 0, 16383ull, 0ull},
|
|
{"FRREM" , 16, 16, 866, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTCONNSTS" , 0, 1, 867, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTCONNDET" , 1, 1, 867, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTENA" , 2, 1, 867, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTENCHNG" , 3, 1, 867, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTOVRCURRACT" , 4, 1, 867, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTOVRCURRCHNG" , 5, 1, 867, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTRES" , 6, 1, 867, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTSUSP" , 7, 1, 867, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTRST" , 8, 1, 867, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 867, "RAZ", 1, 1, 0, 0},
|
|
{"PRTLNSTS" , 10, 2, 867, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTPWR" , 12, 1, 867, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTTSTCTL" , 13, 4, 867, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTSPD" , 17, 2, 867, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_31" , 19, 13, 867, "RAZ", 1, 1, 0, 0},
|
|
{"PTXFSTADDR" , 0, 16, 868, "R/W", 0, 0, 3648ull, 912ull},
|
|
{"PTXFSIZE" , 16, 16, 868, "R/W", 0, 0, 256ull, 456ull},
|
|
{"PTXFSPCAVAIL" , 0, 16, 869, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTXQSPCAVAIL" , 16, 8, 869, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTXQTOP" , 24, 8, 869, "RO", 0, 0, 0ull, 0ull},
|
|
{"DATA" , 0, 32, 870, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STOPPCLK" , 0, 1, 871, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GATEHCLK" , 1, 1, 871, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PWRCLMP" , 2, 1, 871, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSTPDWNMODULE" , 3, 1, 871, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHYSUSPENDED" , 4, 1, 871, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 871, "RAZ", 1, 1, 0, 0},
|
|
{"NOF_BIS" , 0, 1, 872, "RO", 0, 0, 0ull, 0ull},
|
|
{"NIF_BIS" , 1, 1, 872, "RO", 0, 0, 0ull, 0ull},
|
|
{"USBC_BIS" , 2, 1, 872, "RO", 0, 0, 0ull, 0ull},
|
|
{"N2UF_BIS" , 3, 1, 872, "RO", 0, 0, 0ull, 0ull},
|
|
{"E2HC_BIS" , 4, 1, 872, "RO", 0, 0, 0ull, 0ull},
|
|
{"U2NF_BIS" , 5, 1, 872, "RO", 0, 0, 0ull, 0ull},
|
|
{"U2NC_BIS" , 6, 1, 872, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 872, "RAZ", 1, 1, 0, 0},
|
|
{"DIVIDE" , 0, 3, 873, "R/W", 0, 0, 4ull, 0ull},
|
|
{"HRST" , 3, 1, 873, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PRST" , 4, 1, 873, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ENABLE" , 5, 1, 873, "R/W", 0, 0, 1ull, 1ull},
|
|
{"POR" , 6, 1, 873, "R/W", 0, 0, 1ull, 0ull},
|
|
{"S_BIST" , 7, 1, 873, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SD_MODE" , 8, 2, 873, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CDIV_BYP" , 10, 1, 873, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_C_SEL" , 11, 2, 873, "R/W", 0, 0, 2ull, 0ull},
|
|
{"P_COM_ON" , 13, 1, 873, "R/W", 0, 0, 1ull, 1ull},
|
|
{"P_RTYPE" , 14, 2, 873, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 873, "RAZ", 1, 1, 0, 0},
|
|
{"HCLK_RST" , 17, 1, 873, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DIVIDE2" , 18, 2, 873, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_20_63" , 20, 44, 873, "RAZ", 1, 1, 0, 0},
|
|
{"L2C_EMOD" , 0, 2, 874, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INV_A2" , 2, 1, 874, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_TEST" , 3, 1, 874, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_STT" , 4, 1, 874, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_0PAG" , 5, 1, 874, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 874, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 875, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 875, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 876, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 876, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 877, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 877, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 878, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 878, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 879, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 879, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 880, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 880, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 881, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 881, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 882, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 882, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 883, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 883, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 884, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 884, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 885, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 885, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 886, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 886, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 887, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 887, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 888, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 888, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 889, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 889, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 890, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 890, "RAZ", 1, 1, 0, 0},
|
|
{"BURST" , 0, 4, 891, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHANNEL" , 4, 5, 891, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COUNT" , 9, 11, 891, "R/W", 0, 0, 0ull, 0ull},
|
|
{"F_ADDR" , 20, 18, 891, "R/W", 0, 0, 0ull, 0ull},
|
|
{"REQ" , 38, 1, 891, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DONE" , 39, 1, 891, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 891, "RAZ", 1, 1, 0, 0},
|
|
{"PR_PO_E" , 0, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PR_PU_F" , 1, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NR_PO_E" , 2, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NR_PU_F" , 3, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LR_PO_E" , 4, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LR_PU_F" , 5, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PT_PO_E" , 6, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PT_PU_F" , 7, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NT_PO_E" , 8, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NT_PU_F" , 9, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LT_PO_E" , 10, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LT_PU_F" , 11, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DCRED_E" , 12, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DCRED_F" , 13, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2C_S_E" , 14, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2C_A_F" , 15, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2_FI_E" , 16, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2_FI_F" , 17, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_E" , 18, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_F" , 19, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_F" , 20, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_E" , 21, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_F" , 22, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_E" , 23, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UOD_PE" , 24, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UOD_PF" , 25, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_31" , 26, 6, 892, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LTL_F_PE" , 32, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LTL_F_PF" , 33, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_RPE" , 34, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_RPF" , 35, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_DPE" , 36, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_DPF" , 37, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 892, "RAZ", 1, 1, 0, 0},
|
|
{"PR_PO_E" , 0, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PR_PU_F" , 1, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NR_PO_E" , 2, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NR_PU_F" , 3, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LR_PO_E" , 4, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LR_PU_F" , 5, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PT_PO_E" , 6, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PT_PU_F" , 7, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NT_PO_E" , 8, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NT_PU_F" , 9, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LT_PO_E" , 10, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LT_PU_F" , 11, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCRED_E" , 12, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCRED_F" , 13, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"L2C_S_E" , 14, 1, 893, "R/W1C", 1, 0, 0, 0ull},
|
|
{"L2C_A_F" , 15, 1, 893, "R/W1C", 1, 0, 0, 0ull},
|
|
{"LT_FI_E" , 16, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LT_FI_F" , 17, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_E" , 18, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_F" , 19, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_F" , 20, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_E" , 21, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_F" , 22, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_E" , 23, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UOD_PE" , 24, 1, 893, "R/W1C", 1, 0, 0, 0ull},
|
|
{"UOD_PF" , 25, 1, 893, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_26_31" , 26, 6, 893, "RAZ", 1, 0, 0, 0ull},
|
|
{"LTL_F_PE" , 32, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LTL_F_PF" , 33, 1, 893, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ND4O_RPE" , 34, 1, 893, "R/W1C", 1, 0, 0, 0ull},
|
|
{"ND4O_RPF" , 35, 1, 893, "R/W1C", 1, 0, 0, 0ull},
|
|
{"ND4O_DPE" , 36, 1, 893, "R/W1C", 1, 0, 0, 0ull},
|
|
{"ND4O_DPF" , 37, 1, 893, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 893, "RAZ", 1, 1, 0, 0},
|
|
{"ATE_RESET" , 0, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TDATA_IN" , 1, 8, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TADDR_IN" , 9, 4, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TDATA_SEL" , 13, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BIST_ENB" , 14, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VTEST_ENB" , 15, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LOOP_ENB" , 16, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TX_BS_EN" , 17, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TX_BS_ENH" , 18, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_22" , 19, 4, 894, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"HST_MODE" , 23, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DM_PULLD" , 24, 1, 894, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DP_PULLD" , 25, 1, 894, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TCLK" , 26, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBP_BIST" , 27, 1, 894, "R/W", 0, 0, 1ull, 1ull},
|
|
{"USBC_END" , 28, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_BMODE" , 29, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXPREEMPHASISTUNE" , 30, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_31" , 31, 1, 894, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TDATA_OUT" , 32, 4, 894, "RO", 1, 1, 0, 0},
|
|
{"BIST_ERR" , 36, 1, 894, "RO", 0, 0, 0ull, 0ull},
|
|
{"BIST_DONE" , 37, 1, 894, "RO", 0, 0, 0ull, 0ull},
|
|
{"HSBIST" , 38, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSBIST" , 39, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LSBIST" , 40, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRVVBUS" , 41, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PORTRESET" , 42, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OTGDISABLE" , 43, 1, 894, "R/W", 0, 0, 1ull, 1ull},
|
|
{"OTGTUNE" , 44, 3, 894, "R/W", 0, 0, 2ull, 2ull},
|
|
{"COMPDISTUNE" , 47, 3, 894, "R/W", 0, 0, 2ull, 2ull},
|
|
{"SQRXTUNE" , 50, 3, 894, "R/W", 0, 0, 3ull, 3ull},
|
|
{"TXHSXVTUNE" , 53, 2, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFSLSTUNE" , 55, 4, 894, "R/W", 0, 0, 3ull, 3ull},
|
|
{"TXVREFTUNE" , 59, 4, 894, "R/W", 0, 0, 7ull, 7ull},
|
|
{"TXRISETUNE" , 63, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ZIP_CTL" , 0, 4, 895, "RO", 1, 0, 0, 0ull},
|
|
{"ZIP_CORE" , 4, 27, 895, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 895, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 33, 896, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 33, 13, 896, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 46, 3, 896, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 49, 9, 896, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_58_63" , 58, 6, 896, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 0, 1, 897, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FORCECLK" , 1, 1, 897, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 897, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DISABLED" , 0, 1, 898, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_7" , 1, 7, 898, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CTXSIZE" , 8, 12, 898, "RO", 0, 0, 1536ull, 1536ull},
|
|
{"ONFSIZE" , 20, 12, 898, "RO", 0, 0, 512ull, 512ull},
|
|
{"DEPTH" , 32, 16, 898, "RO", 0, 0, 31744ull, 31744ull},
|
|
{"RESERVED_48_63" , 48, 16, 898, "RAZ", 1, 0, 0, 0ull},
|
|
{"ASSERTS" , 0, 14, 899, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 899, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 0, 1, 900, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 900, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 0, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 901, "RAZ", 1, 0, 0, 0ull},
|
|
{NULL,0,0,0,0,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn56xx[] = {
|
|
/* name , ---------------type, bits, off, #field, fld of */
|
|
{"cvmx_agl_gmx_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 11, 0},
|
|
{"cvmx_agl_gmx_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 1, 2, 11},
|
|
{"cvmx_agl_gmx_drv_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 6, 13},
|
|
{"cvmx_agl_gmx_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 3, 3, 19},
|
|
{"cvmx_agl_gmx_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 7, 22},
|
|
{"cvmx_agl_gmx_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 5, 1, 29},
|
|
{"cvmx_agl_gmx_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 1, 30},
|
|
{"cvmx_agl_gmx_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 7, 1, 31},
|
|
{"cvmx_agl_gmx_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 8, 1, 32},
|
|
{"cvmx_agl_gmx_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 9, 1, 33},
|
|
{"cvmx_agl_gmx_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 1, 34},
|
|
{"cvmx_agl_gmx_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 11, 2, 35},
|
|
{"cvmx_agl_gmx_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 4, 37},
|
|
{"cvmx_agl_gmx_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 13, 2, 41},
|
|
{"cvmx_agl_gmx_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 10, 43},
|
|
{"cvmx_agl_gmx_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 15, 11, 53},
|
|
{"cvmx_agl_gmx_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 2, 64},
|
|
{"cvmx_agl_gmx_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 17, 2, 66},
|
|
{"cvmx_agl_gmx_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 18, 2, 68},
|
|
{"cvmx_agl_gmx_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 19, 19, 70},
|
|
{"cvmx_agl_gmx_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 20, 19, 89},
|
|
{"cvmx_agl_gmx_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 21, 2, 108},
|
|
{"cvmx_agl_gmx_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 22, 2, 110},
|
|
{"cvmx_agl_gmx_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 23, 2, 112},
|
|
{"cvmx_agl_gmx_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 24, 2, 114},
|
|
{"cvmx_agl_gmx_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 25, 2, 116},
|
|
{"cvmx_agl_gmx_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 26, 2, 118},
|
|
{"cvmx_agl_gmx_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 27, 2, 120},
|
|
{"cvmx_agl_gmx_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 28, 2, 122},
|
|
{"cvmx_agl_gmx_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 29, 2, 124},
|
|
{"cvmx_agl_gmx_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 30, 2, 126},
|
|
{"cvmx_agl_gmx_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 31, 2, 128},
|
|
{"cvmx_agl_gmx_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 32, 2, 130},
|
|
{"cvmx_agl_gmx_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 33, 4, 132},
|
|
{"cvmx_agl_gmx_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 34, 2, 136},
|
|
{"cvmx_agl_gmx_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 35, 2, 138},
|
|
{"cvmx_agl_gmx_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 36, 2, 140},
|
|
{"cvmx_agl_gmx_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 37, 4, 142},
|
|
{"cvmx_agl_gmx_rx_tx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 38, 4, 146},
|
|
{"cvmx_agl_gmx_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 39, 2, 150},
|
|
{"cvmx_agl_gmx_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 40, 3, 152},
|
|
{"cvmx_agl_gmx_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 41, 5, 155},
|
|
{"cvmx_agl_gmx_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 42, 3, 160},
|
|
{"cvmx_agl_gmx_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 43, 2, 163},
|
|
{"cvmx_agl_gmx_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 44, 2, 165},
|
|
{"cvmx_agl_gmx_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 45, 2, 167},
|
|
{"cvmx_agl_gmx_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 46, 2, 169},
|
|
{"cvmx_agl_gmx_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 47, 2, 171},
|
|
{"cvmx_agl_gmx_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 48, 2, 173},
|
|
{"cvmx_agl_gmx_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 49, 2, 175},
|
|
{"cvmx_agl_gmx_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 50, 2, 177},
|
|
{"cvmx_agl_gmx_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 51, 2, 179},
|
|
{"cvmx_agl_gmx_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 2, 181},
|
|
{"cvmx_agl_gmx_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 53, 2, 183},
|
|
{"cvmx_agl_gmx_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 54, 2, 185},
|
|
{"cvmx_agl_gmx_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 55, 2, 187},
|
|
{"cvmx_agl_gmx_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 56, 2, 189},
|
|
{"cvmx_agl_gmx_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 57, 2, 191},
|
|
{"cvmx_agl_gmx_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 58, 2, 193},
|
|
{"cvmx_agl_gmx_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 59, 2, 195},
|
|
{"cvmx_agl_gmx_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 60, 2, 197},
|
|
{"cvmx_agl_gmx_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 61, 2, 199},
|
|
{"cvmx_agl_gmx_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 62, 2, 201},
|
|
{"cvmx_agl_gmx_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 63, 3, 203},
|
|
{"cvmx_agl_gmx_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 64, 10, 206},
|
|
{"cvmx_agl_gmx_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 65, 10, 216},
|
|
{"cvmx_agl_gmx_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 66, 2, 226},
|
|
{"cvmx_agl_gmx_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 67, 2, 228},
|
|
{"cvmx_agl_gmx_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 68, 6, 230},
|
|
{"cvmx_agl_gmx_tx_pause_pkt_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 69, 2, 236},
|
|
{"cvmx_agl_gmx_tx_pause_pkt_type", CVMX_CSR_DB_TYPE_RSL, 64, 70, 2, 238},
|
|
{"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 71, 2, 240},
|
|
{"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 72, 2, 242},
|
|
{"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 73, 2, 244},
|
|
{"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 74, 2, 246},
|
|
{"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 75, 21, 248},
|
|
{"cvmx_ciu_int#_en0_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 100, 21, 269},
|
|
{"cvmx_ciu_int#_en0_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 125, 21, 290},
|
|
{"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 150, 2, 311},
|
|
{"cvmx_ciu_int#_en1_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 175, 2, 313},
|
|
{"cvmx_ciu_int#_en1_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 200, 2, 315},
|
|
{"cvmx_ciu_int#_en4_0" , CVMX_CSR_DB_TYPE_NCB, 64, 225, 21, 317},
|
|
{"cvmx_ciu_int#_en4_0_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 237, 21, 338},
|
|
{"cvmx_ciu_int#_en4_0_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 249, 21, 359},
|
|
{"cvmx_ciu_int#_en4_1" , CVMX_CSR_DB_TYPE_NCB, 64, 261, 2, 380},
|
|
{"cvmx_ciu_int#_en4_1_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 273, 2, 382},
|
|
{"cvmx_ciu_int#_en4_1_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 285, 2, 384},
|
|
{"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 297, 21, 386},
|
|
{"cvmx_ciu_int#_sum4" , CVMX_CSR_DB_TYPE_NCB, 64, 322, 21, 407},
|
|
{"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 334, 2, 428},
|
|
{"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 335, 2, 430},
|
|
{"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 347, 2, 432},
|
|
{"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 359, 2, 434},
|
|
{"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 360, 2, 436},
|
|
{"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 361, 2, 438},
|
|
{"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 362, 1, 440},
|
|
{"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 374, 3, 441},
|
|
{"cvmx_ciu_qlm_dcok" , CVMX_CSR_DB_TYPE_NCB, 64, 375, 2, 444},
|
|
{"cvmx_ciu_qlm_jtgc" , CVMX_CSR_DB_TYPE_NCB, 64, 376, 5, 446},
|
|
{"cvmx_ciu_qlm_jtgd" , CVMX_CSR_DB_TYPE_NCB, 64, 377, 8, 451},
|
|
{"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 378, 2, 459},
|
|
{"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 379, 2, 461},
|
|
{"cvmx_ciu_soft_prst1" , CVMX_CSR_DB_TYPE_NCB, 64, 380, 2, 463},
|
|
{"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 381, 2, 465},
|
|
{"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 382, 3, 467},
|
|
{"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 386, 7, 470},
|
|
{"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 398, 6, 477},
|
|
{"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 399, 7, 483},
|
|
{"cvmx_fpa_fpf#_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 400, 3, 490},
|
|
{"cvmx_fpa_fpf#_size" , CVMX_CSR_DB_TYPE_RSL, 64, 407, 2, 493},
|
|
{"cvmx_fpa_fpf0_marks" , CVMX_CSR_DB_TYPE_RSL, 64, 414, 3, 495},
|
|
{"cvmx_fpa_fpf0_size" , CVMX_CSR_DB_TYPE_RSL, 64, 415, 2, 498},
|
|
{"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 416, 29, 500},
|
|
{"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 417, 29, 529},
|
|
{"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 418, 2, 558},
|
|
{"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 426, 2, 560},
|
|
{"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 434, 3, 562},
|
|
{"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 435, 3, 565},
|
|
{"cvmx_fpa_wart_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 436, 2, 568},
|
|
{"cvmx_fpa_wart_status" , CVMX_CSR_DB_TYPE_RSL, 64, 437, 2, 570},
|
|
{"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 438, 7, 572},
|
|
{"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 440, 2, 579},
|
|
{"cvmx_gmx#_clk_en" , CVMX_CSR_DB_TYPE_RSL, 64, 442, 2, 581},
|
|
{"cvmx_gmx#_hg2_control" , CVMX_CSR_DB_TYPE_RSL, 64, 444, 5, 583},
|
|
{"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 446, 7, 588},
|
|
{"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 448, 2, 595},
|
|
{"cvmx_gmx#_prt#_cbfc_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 450, 8, 597},
|
|
{"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 452, 10, 605},
|
|
{"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 460, 1, 615},
|
|
{"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 468, 1, 616},
|
|
{"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 476, 1, 617},
|
|
{"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 484, 1, 618},
|
|
{"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 492, 1, 619},
|
|
{"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 500, 1, 620},
|
|
{"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 508, 2, 621},
|
|
{"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 516, 4, 623},
|
|
{"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 524, 2, 627},
|
|
{"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 532, 9, 629},
|
|
{"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 540, 11, 638},
|
|
{"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 548, 2, 649},
|
|
{"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 556, 27, 651},
|
|
{"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 564, 27, 678},
|
|
{"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 572, 2, 705},
|
|
{"cvmx_gmx#_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 580, 2, 707},
|
|
{"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 588, 2, 709},
|
|
{"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 596, 2, 711},
|
|
{"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 604, 2, 713},
|
|
{"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 612, 2, 715},
|
|
{"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 620, 2, 717},
|
|
{"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 628, 2, 719},
|
|
{"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 636, 2, 721},
|
|
{"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 644, 2, 723},
|
|
{"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 652, 2, 725},
|
|
{"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 660, 2, 727},
|
|
{"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 668, 4, 729},
|
|
{"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 676, 2, 733},
|
|
{"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 684, 2, 735},
|
|
{"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 692, 2, 737},
|
|
{"cvmx_gmx#_rx_hg2_status" , CVMX_CSR_DB_TYPE_RSL, 64, 700, 4, 739},
|
|
{"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 702, 4, 743},
|
|
{"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 704, 2, 747},
|
|
{"cvmx_gmx#_rx_xaui_bad_col" , CVMX_CSR_DB_TYPE_RSL, 64, 706, 5, 749},
|
|
{"cvmx_gmx#_rx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 708, 2, 754},
|
|
{"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 710, 2, 756},
|
|
{"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 718, 3, 758},
|
|
{"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 720, 5, 761},
|
|
{"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 728, 2, 766},
|
|
{"cvmx_gmx#_tx#_cbfc_xoff" , CVMX_CSR_DB_TYPE_RSL, 64, 736, 2, 768},
|
|
{"cvmx_gmx#_tx#_cbfc_xon" , CVMX_CSR_DB_TYPE_RSL, 64, 738, 2, 770},
|
|
{"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 740, 3, 772},
|
|
{"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 748, 2, 775},
|
|
{"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 756, 2, 777},
|
|
{"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 764, 2, 779},
|
|
{"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 772, 3, 781},
|
|
{"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 780, 2, 784},
|
|
{"cvmx_gmx#_tx#_sgmii_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 788, 2, 786},
|
|
{"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 796, 2, 788},
|
|
{"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 804, 2, 790},
|
|
{"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 812, 2, 792},
|
|
{"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 820, 2, 794},
|
|
{"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 828, 2, 796},
|
|
{"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 836, 2, 798},
|
|
{"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 844, 2, 800},
|
|
{"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 852, 2, 802},
|
|
{"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 860, 2, 804},
|
|
{"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 868, 2, 806},
|
|
{"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 876, 2, 808},
|
|
{"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 884, 2, 810},
|
|
{"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 892, 2, 812},
|
|
{"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 900, 2, 814},
|
|
{"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 908, 2, 816},
|
|
{"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 910, 2, 818},
|
|
{"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 912, 2, 820},
|
|
{"cvmx_gmx#_tx_hg2_reg1" , CVMX_CSR_DB_TYPE_RSL, 64, 914, 2, 822},
|
|
{"cvmx_gmx#_tx_hg2_reg2" , CVMX_CSR_DB_TYPE_RSL, 64, 916, 2, 824},
|
|
{"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 918, 3, 826},
|
|
{"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 920, 8, 829},
|
|
{"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 922, 8, 837},
|
|
{"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 924, 2, 845},
|
|
{"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 926, 2, 847},
|
|
{"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 928, 6, 849},
|
|
{"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 930, 2, 855},
|
|
{"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 932, 2, 857},
|
|
{"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 934, 2, 859},
|
|
{"cvmx_gmx#_tx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 936, 9, 861},
|
|
{"cvmx_gmx#_xaui_ext_loopback" , CVMX_CSR_DB_TYPE_RSL, 64, 938, 3, 870},
|
|
{"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 940, 9, 873},
|
|
{"cvmx_gpio_clk_gen#" , CVMX_CSR_DB_TYPE_NCB, 64, 956, 2, 882},
|
|
{"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 960, 2, 884},
|
|
{"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 961, 2, 886},
|
|
{"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 962, 2, 888},
|
|
{"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 963, 2, 890},
|
|
{"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 964, 19, 892},
|
|
{"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 965, 6, 911},
|
|
{"cvmx_iob_dwb_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 966, 3, 917},
|
|
{"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 967, 3, 920},
|
|
{"cvmx_iob_i2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 968, 3, 923},
|
|
{"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 969, 5, 926},
|
|
{"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 970, 5, 931},
|
|
{"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 971, 1, 936},
|
|
{"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 972, 1, 937},
|
|
{"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 973, 7, 938},
|
|
{"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 974, 7, 945},
|
|
{"cvmx_iob_n2c_l2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 975, 3, 952},
|
|
{"cvmx_iob_n2c_rsp_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 976, 3, 955},
|
|
{"cvmx_iob_outb_com_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 977, 3, 958},
|
|
{"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 978, 5, 961},
|
|
{"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 979, 5, 966},
|
|
{"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 980, 1, 971},
|
|
{"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 981, 1, 972},
|
|
{"cvmx_iob_outb_fpa_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 982, 3, 973},
|
|
{"cvmx_iob_outb_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 983, 3, 976},
|
|
{"cvmx_iob_p2c_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 984, 3, 979},
|
|
{"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 985, 2, 982},
|
|
{"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 986, 2, 984},
|
|
{"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 987, 2, 986},
|
|
{"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 988, 2, 988},
|
|
{"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 989, 19, 990},
|
|
{"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 990, 2, 1009},
|
|
{"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 991, 1, 1011},
|
|
{"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 992, 15, 1012},
|
|
{"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 993, 13, 1027},
|
|
{"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 994, 13, 1040},
|
|
{"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 995, 2, 1053},
|
|
{"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 996, 2, 1055},
|
|
{"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 997, 2, 1057},
|
|
{"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 998, 3, 1059},
|
|
{"cvmx_ipd_port#_bp_page_cnt2" , CVMX_CSR_DB_TYPE_NCB, 64, 1010, 3, 1062},
|
|
{"cvmx_ipd_port_bp_counters2_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 1014, 2, 1065},
|
|
{"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 1018, 2, 1067},
|
|
{"cvmx_ipd_port_qos_#_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1030, 2, 1069},
|
|
{"cvmx_ipd_port_qos_int#" , CVMX_CSR_DB_TYPE_NCB, 64, 1158, 1, 1071},
|
|
{"cvmx_ipd_port_qos_int_enb#" , CVMX_CSR_DB_TYPE_NCB, 64, 1161, 1, 1072},
|
|
{"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 1164, 6, 1073},
|
|
{"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 1165, 5, 1079},
|
|
{"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 1166, 6, 1084},
|
|
{"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1167, 7, 1090},
|
|
{"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 1168, 2, 1097},
|
|
{"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1176, 2, 1099},
|
|
{"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 1177, 3, 1101},
|
|
{"cvmx_ipd_red_port_enable2" , CVMX_CSR_DB_TYPE_NCB, 64, 1178, 2, 1104},
|
|
{"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 1179, 5, 1106},
|
|
{"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 1187, 3, 1111},
|
|
{"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 1188, 4, 1114},
|
|
{"cvmx_ipd_sub_port_qos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1189, 3, 1118},
|
|
{"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 1190, 2, 1121},
|
|
{"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 1191, 2, 1123},
|
|
{"cvmx_key_bist_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1192, 4, 1125},
|
|
{"cvmx_key_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1193, 3, 1129},
|
|
{"cvmx_key_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1194, 5, 1132},
|
|
{"cvmx_key_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1195, 5, 1137},
|
|
{"cvmx_l2c_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 1196, 7, 1142},
|
|
{"cvmx_l2c_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 1197, 11, 1149},
|
|
{"cvmx_l2c_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 1198, 8, 1160},
|
|
{"cvmx_l2c_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1199, 15, 1168},
|
|
{"cvmx_l2c_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1200, 8, 1183},
|
|
{"cvmx_l2c_dut" , CVMX_CSR_DB_TYPE_RSL, 64, 1201, 5, 1191},
|
|
{"cvmx_l2c_grpwrr0" , CVMX_CSR_DB_TYPE_RSL, 64, 1202, 2, 1196},
|
|
{"cvmx_l2c_grpwrr1" , CVMX_CSR_DB_TYPE_RSL, 64, 1203, 2, 1198},
|
|
{"cvmx_l2c_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1204, 10, 1200},
|
|
{"cvmx_l2c_int_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 1205, 10, 1210},
|
|
{"cvmx_l2c_lckbase" , CVMX_CSR_DB_TYPE_RSL, 64, 1206, 4, 1220},
|
|
{"cvmx_l2c_lckoff" , CVMX_CSR_DB_TYPE_RSL, 64, 1207, 2, 1224},
|
|
{"cvmx_l2c_lfb0" , CVMX_CSR_DB_TYPE_RSL, 64, 1208, 14, 1226},
|
|
{"cvmx_l2c_lfb1" , CVMX_CSR_DB_TYPE_RSL, 64, 1209, 19, 1240},
|
|
{"cvmx_l2c_lfb2" , CVMX_CSR_DB_TYPE_RSL, 64, 1210, 3, 1259},
|
|
{"cvmx_l2c_lfb3" , CVMX_CSR_DB_TYPE_RSL, 64, 1211, 3, 1262},
|
|
{"cvmx_l2c_oob" , CVMX_CSR_DB_TYPE_RSL, 64, 1212, 3, 1265},
|
|
{"cvmx_l2c_oob1" , CVMX_CSR_DB_TYPE_RSL, 64, 1213, 6, 1268},
|
|
{"cvmx_l2c_oob2" , CVMX_CSR_DB_TYPE_RSL, 64, 1214, 6, 1274},
|
|
{"cvmx_l2c_oob3" , CVMX_CSR_DB_TYPE_RSL, 64, 1215, 6, 1280},
|
|
{"cvmx_l2c_pfc#" , CVMX_CSR_DB_TYPE_RSL, 64, 1216, 2, 1286},
|
|
{"cvmx_l2c_pfctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1220, 17, 1288},
|
|
{"cvmx_l2c_ppgrp" , CVMX_CSR_DB_TYPE_RSL, 64, 1221, 13, 1305},
|
|
{"cvmx_l2c_spar0" , CVMX_CSR_DB_TYPE_RSL, 64, 1222, 5, 1318},
|
|
{"cvmx_l2c_spar1" , CVMX_CSR_DB_TYPE_RSL, 64, 1223, 5, 1323},
|
|
{"cvmx_l2c_spar2" , CVMX_CSR_DB_TYPE_RSL, 64, 1224, 5, 1328},
|
|
{"cvmx_l2c_spar4" , CVMX_CSR_DB_TYPE_RSL, 64, 1225, 2, 1333},
|
|
{"cvmx_l2d_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 1226, 3, 1335},
|
|
{"cvmx_l2d_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 1227, 2, 1338},
|
|
{"cvmx_l2d_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 1228, 2, 1340},
|
|
{"cvmx_l2d_bst3" , CVMX_CSR_DB_TYPE_RSL, 64, 1229, 2, 1342},
|
|
{"cvmx_l2d_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1230, 7, 1344},
|
|
{"cvmx_l2d_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1231, 5, 1351},
|
|
{"cvmx_l2d_fsyn0" , CVMX_CSR_DB_TYPE_RSL, 64, 1232, 3, 1356},
|
|
{"cvmx_l2d_fsyn1" , CVMX_CSR_DB_TYPE_RSL, 64, 1233, 3, 1359},
|
|
{"cvmx_l2d_fus0" , CVMX_CSR_DB_TYPE_RSL, 64, 1234, 2, 1362},
|
|
{"cvmx_l2d_fus1" , CVMX_CSR_DB_TYPE_RSL, 64, 1235, 2, 1364},
|
|
{"cvmx_l2d_fus2" , CVMX_CSR_DB_TYPE_RSL, 64, 1236, 2, 1366},
|
|
{"cvmx_l2d_fus3" , CVMX_CSR_DB_TYPE_RSL, 64, 1237, 6, 1368},
|
|
{"cvmx_l2t_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1238, 14, 1374},
|
|
{"cvmx_led_blink" , CVMX_CSR_DB_TYPE_RSL, 64, 1239, 2, 1388},
|
|
{"cvmx_led_clk_phase" , CVMX_CSR_DB_TYPE_RSL, 64, 1240, 2, 1390},
|
|
{"cvmx_led_cylon" , CVMX_CSR_DB_TYPE_RSL, 64, 1241, 2, 1392},
|
|
{"cvmx_led_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1242, 2, 1394},
|
|
{"cvmx_led_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1243, 2, 1396},
|
|
{"cvmx_led_polarity" , CVMX_CSR_DB_TYPE_RSL, 64, 1244, 2, 1398},
|
|
{"cvmx_led_prt" , CVMX_CSR_DB_TYPE_RSL, 64, 1245, 2, 1400},
|
|
{"cvmx_led_prt_fmt" , CVMX_CSR_DB_TYPE_RSL, 64, 1246, 2, 1402},
|
|
{"cvmx_led_prt_status#" , CVMX_CSR_DB_TYPE_RSL, 64, 1247, 2, 1404},
|
|
{"cvmx_led_udd_cnt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1255, 2, 1406},
|
|
{"cvmx_led_udd_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 1257, 2, 1408},
|
|
{"cvmx_led_udd_dat_clr#" , CVMX_CSR_DB_TYPE_RSL, 64, 1259, 2, 1410},
|
|
{"cvmx_led_udd_dat_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 1261, 2, 1412},
|
|
{"cvmx_lmc#_bist_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1263, 2, 1414},
|
|
{"cvmx_lmc#_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1265, 8, 1416},
|
|
{"cvmx_lmc#_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1267, 7, 1424},
|
|
{"cvmx_lmc#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1269, 19, 1431},
|
|
{"cvmx_lmc#_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 1271, 8, 1450},
|
|
{"cvmx_lmc#_dclk_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1273, 2, 1458},
|
|
{"cvmx_lmc#_dclk_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1275, 2, 1460},
|
|
{"cvmx_lmc#_dclk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1277, 5, 1462},
|
|
{"cvmx_lmc#_ddr2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1279, 18, 1467},
|
|
{"cvmx_lmc#_delay_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1281, 6, 1485},
|
|
{"cvmx_lmc#_dll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1283, 5, 1491},
|
|
{"cvmx_lmc#_dual_memcfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1285, 5, 1496},
|
|
{"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 1287, 5, 1501},
|
|
{"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1289, 6, 1506},
|
|
{"cvmx_lmc#_ifb_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1291, 2, 1512},
|
|
{"cvmx_lmc#_ifb_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1293, 2, 1514},
|
|
{"cvmx_lmc#_mem_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 1295, 14, 1516},
|
|
{"cvmx_lmc#_mem_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 1297, 9, 1530},
|
|
{"cvmx_lmc#_nxm" , CVMX_CSR_DB_TYPE_RSL, 64, 1299, 2, 1539},
|
|
{"cvmx_lmc#_ops_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 1301, 2, 1541},
|
|
{"cvmx_lmc#_ops_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 1303, 2, 1543},
|
|
{"cvmx_lmc#_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1305, 13, 1545},
|
|
{"cvmx_lmc#_pll_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1307, 6, 1558},
|
|
{"cvmx_lmc#_read_level_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1309, 7, 1564},
|
|
{"cvmx_lmc#_read_level_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 1311, 4, 1571},
|
|
{"cvmx_lmc#_read_level_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 1313, 11, 1575},
|
|
{"cvmx_lmc#_rodt_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1321, 6, 1586},
|
|
{"cvmx_lmc#_rodt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1323, 9, 1592},
|
|
{"cvmx_lmc#_wodt_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 1325, 5, 1601},
|
|
{"cvmx_lmc#_wodt_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 1327, 5, 1606},
|
|
{"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 1329, 5, 1611},
|
|
{"cvmx_mio_boot_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 1330, 3, 1616},
|
|
{"cvmx_mio_boot_dma_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1331, 10, 1619},
|
|
{"cvmx_mio_boot_dma_int#" , CVMX_CSR_DB_TYPE_RSL, 64, 1334, 3, 1629},
|
|
{"cvmx_mio_boot_dma_int_en#" , CVMX_CSR_DB_TYPE_RSL, 64, 1337, 3, 1632},
|
|
{"cvmx_mio_boot_dma_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 1340, 15, 1635},
|
|
{"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 1343, 3, 1650},
|
|
{"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1344, 3, 1653},
|
|
{"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1345, 3, 1656},
|
|
{"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1346, 5, 1659},
|
|
{"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1348, 1, 1664},
|
|
{"cvmx_mio_boot_pin_defs" , CVMX_CSR_DB_TYPE_RSL, 64, 1349, 8, 1665},
|
|
{"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1350, 13, 1673},
|
|
{"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 1358, 13, 1686},
|
|
{"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1366, 6, 1699},
|
|
{"cvmx_mio_fus_bnk_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 1367, 1, 1705},
|
|
{"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 1371, 2, 1706},
|
|
{"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 1372, 2, 1708},
|
|
{"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 1373, 13, 1710},
|
|
{"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 1374, 8, 1723},
|
|
{"cvmx_mio_fus_ema" , CVMX_CSR_DB_TYPE_RSL, 64, 1375, 4, 1731},
|
|
{"cvmx_mio_fus_pdf" , CVMX_CSR_DB_TYPE_RSL, 64, 1376, 1, 1735},
|
|
{"cvmx_mio_fus_pll" , CVMX_CSR_DB_TYPE_RSL, 64, 1377, 3, 1736},
|
|
{"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 1378, 2, 1739},
|
|
{"cvmx_mio_fus_prog_times" , CVMX_CSR_DB_TYPE_RSL, 64, 1379, 6, 1741},
|
|
{"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1380, 7, 1747},
|
|
{"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 1381, 4, 1754},
|
|
{"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1382, 2, 1758},
|
|
{"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 1383, 2, 1760},
|
|
{"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 1384, 13, 1762},
|
|
{"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 1386, 12, 1775},
|
|
{"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 1388, 3, 1787},
|
|
{"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 1390, 3, 1790},
|
|
{"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 1392, 2, 1793},
|
|
{"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 1394, 2, 1795},
|
|
{"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 1396, 2, 1797},
|
|
{"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1398, 7, 1799},
|
|
{"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 1400, 2, 1806},
|
|
{"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 1402, 7, 1808},
|
|
{"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 1404, 4, 1815},
|
|
{"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1406, 8, 1819},
|
|
{"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 1408, 9, 1827},
|
|
{"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1410, 7, 1836},
|
|
{"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 1412, 9, 1843},
|
|
{"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 1414, 2, 1852},
|
|
{"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1416, 2, 1854},
|
|
{"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 1418, 4, 1856},
|
|
{"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 1420, 2, 1860},
|
|
{"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 1422, 2, 1862},
|
|
{"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 1424, 2, 1864},
|
|
{"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 1426, 4, 1866},
|
|
{"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 1428, 2, 1870},
|
|
{"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 1430, 2, 1872},
|
|
{"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 1432, 2, 1874},
|
|
{"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 1434, 2, 1876},
|
|
{"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 1436, 2, 1878},
|
|
{"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 1438, 2, 1880},
|
|
{"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 1440, 6, 1882},
|
|
{"cvmx_mix#_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 1442, 5, 1888},
|
|
{"cvmx_mix#_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1443, 8, 1893},
|
|
{"cvmx_mix#_intena" , CVMX_CSR_DB_TYPE_NCB, 64, 1444, 8, 1901},
|
|
{"cvmx_mix#_ircnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1445, 2, 1909},
|
|
{"cvmx_mix#_irhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 1446, 3, 1911},
|
|
{"cvmx_mix#_iring1" , CVMX_CSR_DB_TYPE_NCB, 64, 1447, 5, 1914},
|
|
{"cvmx_mix#_iring2" , CVMX_CSR_DB_TYPE_NCB, 64, 1448, 4, 1919},
|
|
{"cvmx_mix#_isr" , CVMX_CSR_DB_TYPE_NCB, 64, 1449, 8, 1923},
|
|
{"cvmx_mix#_orcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1450, 2, 1931},
|
|
{"cvmx_mix#_orhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 1451, 2, 1933},
|
|
{"cvmx_mix#_oring1" , CVMX_CSR_DB_TYPE_NCB, 64, 1452, 5, 1935},
|
|
{"cvmx_mix#_oring2" , CVMX_CSR_DB_TYPE_NCB, 64, 1453, 4, 1940},
|
|
{"cvmx_mix#_remcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1454, 4, 1944},
|
|
{"cvmx_npei_bar1_index#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 1455, 5, 1948},
|
|
{"cvmx_npei_bist_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1487, 58, 1953},
|
|
{"cvmx_npei_bist_status2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1488, 15, 2011},
|
|
{"cvmx_npei_ctl_port0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1489, 17, 2026},
|
|
{"cvmx_npei_ctl_port1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1490, 17, 2043},
|
|
{"cvmx_npei_ctl_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1491, 10, 2060},
|
|
{"cvmx_npei_ctl_status2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1492, 11, 2070},
|
|
{"cvmx_npei_data_out_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1493, 5, 2081},
|
|
{"cvmx_npei_dbg_data" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1494, 8, 2086},
|
|
{"cvmx_npei_dbg_select" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1495, 2, 2094},
|
|
{"cvmx_npei_dma#_counts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1496, 3, 2096},
|
|
{"cvmx_npei_dma#_dbell" , CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 1501, 2, 2099},
|
|
{"cvmx_npei_dma#_ibuff_saddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1506, 4, 2101},
|
|
{"cvmx_npei_dma#_naddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1511, 2, 2105},
|
|
{"cvmx_npei_dma0_int_level" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1516, 2, 2107},
|
|
{"cvmx_npei_dma1_int_level" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1517, 2, 2109},
|
|
{"cvmx_npei_dma_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1518, 2, 2111},
|
|
{"cvmx_npei_dma_control" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1519, 17, 2113},
|
|
{"cvmx_npei_dma_pcie_req_num" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1520, 15, 2130},
|
|
{"cvmx_npei_int_a_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1521, 11, 2145},
|
|
{"cvmx_npei_int_a_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1522, 11, 2156},
|
|
{"cvmx_npei_int_a_sum" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1523, 11, 2167},
|
|
{"cvmx_npei_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1524, 64, 2178},
|
|
{"cvmx_npei_int_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1525, 63, 2242},
|
|
{"cvmx_npei_int_info" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1526, 3, 2305},
|
|
{"cvmx_npei_int_sum" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1527, 64, 2308},
|
|
{"cvmx_npei_int_sum2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1528, 61, 2372},
|
|
{"cvmx_npei_last_win_rdata0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1529, 1, 2433},
|
|
{"cvmx_npei_last_win_rdata1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1530, 1, 2434},
|
|
{"cvmx_npei_mem_access_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1531, 3, 2435},
|
|
{"cvmx_npei_mem_access_subid#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1532, 11, 2438},
|
|
{"cvmx_npei_msi_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1548, 1, 2449},
|
|
{"cvmx_npei_msi_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1549, 1, 2450},
|
|
{"cvmx_npei_msi_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1550, 1, 2451},
|
|
{"cvmx_npei_msi_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1551, 1, 2452},
|
|
{"cvmx_npei_msi_rcv0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1552, 1, 2453},
|
|
{"cvmx_npei_msi_rcv1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1553, 1, 2454},
|
|
{"cvmx_npei_msi_rcv2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1554, 1, 2455},
|
|
{"cvmx_npei_msi_rcv3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1555, 1, 2456},
|
|
{"cvmx_npei_msi_rd_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1556, 3, 2457},
|
|
{"cvmx_npei_msi_w1c_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1557, 1, 2460},
|
|
{"cvmx_npei_msi_w1c_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1558, 1, 2461},
|
|
{"cvmx_npei_msi_w1c_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1559, 1, 2462},
|
|
{"cvmx_npei_msi_w1c_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1560, 1, 2463},
|
|
{"cvmx_npei_msi_w1s_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1561, 1, 2464},
|
|
{"cvmx_npei_msi_w1s_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1562, 1, 2465},
|
|
{"cvmx_npei_msi_w1s_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1563, 1, 2466},
|
|
{"cvmx_npei_msi_w1s_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1564, 1, 2467},
|
|
{"cvmx_npei_msi_wr_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1565, 3, 2468},
|
|
{"cvmx_npei_pcie_credit_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1566, 7, 2471},
|
|
{"cvmx_npei_pcie_msi_rcv" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1567, 2, 2478},
|
|
{"cvmx_npei_pcie_msi_rcv_b1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1568, 3, 2480},
|
|
{"cvmx_npei_pcie_msi_rcv_b2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1569, 3, 2483},
|
|
{"cvmx_npei_pcie_msi_rcv_b3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1570, 3, 2486},
|
|
{"cvmx_npei_pkt#_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1571, 3, 2489},
|
|
{"cvmx_npei_pkt#_in_bp" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1603, 2, 2492},
|
|
{"cvmx_npei_pkt#_instr_baddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1635, 2, 2494},
|
|
{"cvmx_npei_pkt#_instr_baoff_dbell", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1667, 2, 2496},
|
|
{"cvmx_npei_pkt#_instr_fifo_rsize", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1699, 5, 2498},
|
|
{"cvmx_npei_pkt#_instr_header" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1731, 13, 2503},
|
|
{"cvmx_npei_pkt#_slist_baddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1763, 2, 2516},
|
|
{"cvmx_npei_pkt#_slist_baoff_dbell", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1795, 2, 2518},
|
|
{"cvmx_npei_pkt#_slist_fifo_rsize", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1827, 2, 2520},
|
|
{"cvmx_npei_pkt_cnt_int" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1859, 2, 2522},
|
|
{"cvmx_npei_pkt_cnt_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1860, 2, 2524},
|
|
{"cvmx_npei_pkt_data_out_es" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1861, 1, 2526},
|
|
{"cvmx_npei_pkt_data_out_ns" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1862, 2, 2527},
|
|
{"cvmx_npei_pkt_data_out_ror" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1863, 2, 2529},
|
|
{"cvmx_npei_pkt_dpaddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1864, 2, 2531},
|
|
{"cvmx_npei_pkt_in_bp" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1865, 2, 2533},
|
|
{"cvmx_npei_pkt_in_done#_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1866, 2, 2535},
|
|
{"cvmx_npei_pkt_in_instr_counts", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1898, 2, 2537},
|
|
{"cvmx_npei_pkt_in_pcie_port" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1899, 1, 2539},
|
|
{"cvmx_npei_pkt_input_control" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1900, 10, 2540},
|
|
{"cvmx_npei_pkt_instr_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1901, 2, 2550},
|
|
{"cvmx_npei_pkt_instr_rd_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1902, 1, 2552},
|
|
{"cvmx_npei_pkt_instr_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1903, 2, 2553},
|
|
{"cvmx_npei_pkt_int_levels" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1904, 3, 2555},
|
|
{"cvmx_npei_pkt_iptr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1905, 2, 2558},
|
|
{"cvmx_npei_pkt_out_bmode" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1906, 2, 2560},
|
|
{"cvmx_npei_pkt_out_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1907, 2, 2562},
|
|
{"cvmx_npei_pkt_output_wmark" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1908, 2, 2564},
|
|
{"cvmx_npei_pkt_pcie_port" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1909, 1, 2566},
|
|
{"cvmx_npei_pkt_port_in_rst" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1910, 2, 2567},
|
|
{"cvmx_npei_pkt_slist_es" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1911, 1, 2569},
|
|
{"cvmx_npei_pkt_slist_id_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1912, 3, 2570},
|
|
{"cvmx_npei_pkt_slist_ns" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1913, 2, 2573},
|
|
{"cvmx_npei_pkt_slist_ror" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1914, 2, 2575},
|
|
{"cvmx_npei_pkt_time_int" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1915, 2, 2577},
|
|
{"cvmx_npei_pkt_time_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1916, 2, 2579},
|
|
{"cvmx_npei_rsl_int_blocks" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1917, 29, 2581},
|
|
{"cvmx_npei_scratch_1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1918, 1, 2610},
|
|
{"cvmx_npei_state1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1919, 4, 2611},
|
|
{"cvmx_npei_state2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1920, 7, 2615},
|
|
{"cvmx_npei_state3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1921, 5, 2622},
|
|
{"cvmx_npei_win_rd_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 1922, 4, 2627},
|
|
{"cvmx_npei_win_rd_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 1923, 1, 2631},
|
|
{"cvmx_npei_win_wr_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 1924, 4, 2632},
|
|
{"cvmx_npei_win_wr_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 1925, 1, 2636},
|
|
{"cvmx_npei_win_wr_mask" , CVMX_CSR_DB_TYPE_PEXP, 64, 1926, 2, 2637},
|
|
{"cvmx_npei_window_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1927, 2, 2639},
|
|
{"cvmx_pcieep_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1928, 2, 2641},
|
|
{"cvmx_pcieep_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1929, 24, 2643},
|
|
{"cvmx_pcieep_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1930, 4, 2667},
|
|
{"cvmx_pcieep_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1931, 5, 2671},
|
|
{"cvmx_pcieep_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1932, 5, 2676},
|
|
{"cvmx_pcieep_cfg004_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1933, 2, 2681},
|
|
{"cvmx_pcieep_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1934, 1, 2683},
|
|
{"cvmx_pcieep_cfg005_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1935, 1, 2684},
|
|
{"cvmx_pcieep_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1936, 5, 2685},
|
|
{"cvmx_pcieep_cfg006_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1937, 2, 2690},
|
|
{"cvmx_pcieep_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1938, 1, 2692},
|
|
{"cvmx_pcieep_cfg007_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1939, 1, 2693},
|
|
{"cvmx_pcieep_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1940, 4, 2694},
|
|
{"cvmx_pcieep_cfg008_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1941, 2, 2698},
|
|
{"cvmx_pcieep_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1942, 2, 2700},
|
|
{"cvmx_pcieep_cfg009_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1943, 1, 2702},
|
|
{"cvmx_pcieep_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1944, 1, 2703},
|
|
{"cvmx_pcieep_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1945, 2, 2704},
|
|
{"cvmx_pcieep_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1946, 3, 2706},
|
|
{"cvmx_pcieep_cfg012_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1947, 2, 2709},
|
|
{"cvmx_pcieep_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1948, 2, 2711},
|
|
{"cvmx_pcieep_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1949, 4, 2713},
|
|
{"cvmx_pcieep_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1950, 10, 2717},
|
|
{"cvmx_pcieep_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1951, 12, 2727},
|
|
{"cvmx_pcieep_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1952, 7, 2739},
|
|
{"cvmx_pcieep_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1953, 2, 2746},
|
|
{"cvmx_pcieep_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1954, 1, 2748},
|
|
{"cvmx_pcieep_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1955, 2, 2749},
|
|
{"cvmx_pcieep_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1956, 7, 2751},
|
|
{"cvmx_pcieep_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1957, 11, 2758},
|
|
{"cvmx_pcieep_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1958, 19, 2769},
|
|
{"cvmx_pcieep_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1959, 11, 2788},
|
|
{"cvmx_pcieep_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1960, 17, 2799},
|
|
{"cvmx_pcieep_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1961, 12, 2816},
|
|
{"cvmx_pcieep_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1962, 22, 2828},
|
|
{"cvmx_pcieep_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1963, 3, 2850},
|
|
{"cvmx_pcieep_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1964, 3, 2853},
|
|
{"cvmx_pcieep_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1965, 1, 2856},
|
|
{"cvmx_pcieep_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1966, 1, 2857},
|
|
{"cvmx_pcieep_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1967, 1, 2858},
|
|
{"cvmx_pcieep_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1968, 1, 2859},
|
|
{"cvmx_pcieep_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1969, 3, 2860},
|
|
{"cvmx_pcieep_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1970, 14, 2863},
|
|
{"cvmx_pcieep_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1971, 14, 2877},
|
|
{"cvmx_pcieep_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1972, 14, 2891},
|
|
{"cvmx_pcieep_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1973, 9, 2905},
|
|
{"cvmx_pcieep_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1974, 9, 2914},
|
|
{"cvmx_pcieep_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1975, 6, 2923},
|
|
{"cvmx_pcieep_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1976, 1, 2929},
|
|
{"cvmx_pcieep_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1977, 1, 2930},
|
|
{"cvmx_pcieep_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1978, 1, 2931},
|
|
{"cvmx_pcieep_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1979, 1, 2932},
|
|
{"cvmx_pcieep_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1980, 2, 2933},
|
|
{"cvmx_pcieep_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1981, 1, 2935},
|
|
{"cvmx_pcieep_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1982, 6, 2936},
|
|
{"cvmx_pcieep_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1983, 6, 2942},
|
|
{"cvmx_pcieep_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1984, 13, 2948},
|
|
{"cvmx_pcieep_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1985, 5, 2961},
|
|
{"cvmx_pcieep_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1986, 8, 2966},
|
|
{"cvmx_pcieep_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1987, 19, 2974},
|
|
{"cvmx_pcieep_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1988, 3, 2993},
|
|
{"cvmx_pcieep_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1989, 1, 2996},
|
|
{"cvmx_pcieep_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1990, 1, 2997},
|
|
{"cvmx_pcieep_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1991, 3, 2998},
|
|
{"cvmx_pcieep_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1992, 3, 3001},
|
|
{"cvmx_pcieep_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1993, 3, 3004},
|
|
{"cvmx_pcieep_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1994, 4, 3007},
|
|
{"cvmx_pcieep_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1995, 4, 3011},
|
|
{"cvmx_pcieep_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1996, 4, 3015},
|
|
{"cvmx_pcieep_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1997, 7, 3019},
|
|
{"cvmx_pcieep_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1998, 5, 3026},
|
|
{"cvmx_pcieep_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1999, 5, 3031},
|
|
{"cvmx_pcieep_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 2000, 4, 3036},
|
|
{"cvmx_pcieep_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 2001, 4, 3040},
|
|
{"cvmx_pcieep_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 2002, 4, 3044},
|
|
{"cvmx_pcieep_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 2003, 1, 3048},
|
|
{"cvmx_pcieep_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 2004, 1, 3049},
|
|
{"cvmx_pcierc#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2005, 2, 3050},
|
|
{"cvmx_pcierc#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2007, 24, 3052},
|
|
{"cvmx_pcierc#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2009, 4, 3076},
|
|
{"cvmx_pcierc#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2011, 5, 3080},
|
|
{"cvmx_pcierc#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2013, 1, 3085},
|
|
{"cvmx_pcierc#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2015, 1, 3086},
|
|
{"cvmx_pcierc#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2017, 4, 3087},
|
|
{"cvmx_pcierc#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2019, 17, 3091},
|
|
{"cvmx_pcierc#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2021, 4, 3108},
|
|
{"cvmx_pcierc#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2023, 6, 3112},
|
|
{"cvmx_pcierc#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2025, 1, 3118},
|
|
{"cvmx_pcierc#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2027, 1, 3119},
|
|
{"cvmx_pcierc#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2029, 2, 3120},
|
|
{"cvmx_pcierc#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2031, 2, 3122},
|
|
{"cvmx_pcierc#_cfg014" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2033, 1, 3124},
|
|
{"cvmx_pcierc#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2035, 15, 3125},
|
|
{"cvmx_pcierc#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2037, 10, 3140},
|
|
{"cvmx_pcierc#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2039, 12, 3150},
|
|
{"cvmx_pcierc#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2041, 7, 3162},
|
|
{"cvmx_pcierc#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2043, 2, 3169},
|
|
{"cvmx_pcierc#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2045, 1, 3171},
|
|
{"cvmx_pcierc#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2047, 2, 3172},
|
|
{"cvmx_pcierc#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2049, 7, 3174},
|
|
{"cvmx_pcierc#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2051, 11, 3181},
|
|
{"cvmx_pcierc#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2053, 19, 3192},
|
|
{"cvmx_pcierc#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2055, 11, 3211},
|
|
{"cvmx_pcierc#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2057, 20, 3222},
|
|
{"cvmx_pcierc#_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2059, 12, 3242},
|
|
{"cvmx_pcierc#_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2061, 22, 3254},
|
|
{"cvmx_pcierc#_cfg035" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2063, 8, 3276},
|
|
{"cvmx_pcierc#_cfg036" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2065, 4, 3284},
|
|
{"cvmx_pcierc#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2067, 3, 3288},
|
|
{"cvmx_pcierc#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2069, 3, 3291},
|
|
{"cvmx_pcierc#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2071, 1, 3294},
|
|
{"cvmx_pcierc#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2073, 1, 3295},
|
|
{"cvmx_pcierc#_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2075, 1, 3296},
|
|
{"cvmx_pcierc#_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2077, 1, 3297},
|
|
{"cvmx_pcierc#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2079, 3, 3298},
|
|
{"cvmx_pcierc#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2081, 14, 3301},
|
|
{"cvmx_pcierc#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2083, 14, 3315},
|
|
{"cvmx_pcierc#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2085, 14, 3329},
|
|
{"cvmx_pcierc#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2087, 9, 3343},
|
|
{"cvmx_pcierc#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2089, 9, 3352},
|
|
{"cvmx_pcierc#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2091, 6, 3361},
|
|
{"cvmx_pcierc#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2093, 1, 3367},
|
|
{"cvmx_pcierc#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2095, 1, 3368},
|
|
{"cvmx_pcierc#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2097, 1, 3369},
|
|
{"cvmx_pcierc#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2099, 1, 3370},
|
|
{"cvmx_pcierc#_cfg075" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2101, 4, 3371},
|
|
{"cvmx_pcierc#_cfg076" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2103, 9, 3375},
|
|
{"cvmx_pcierc#_cfg077" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2105, 2, 3384},
|
|
{"cvmx_pcierc#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2107, 2, 3386},
|
|
{"cvmx_pcierc#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2109, 1, 3388},
|
|
{"cvmx_pcierc#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2111, 6, 3389},
|
|
{"cvmx_pcierc#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2113, 6, 3395},
|
|
{"cvmx_pcierc#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2115, 13, 3401},
|
|
{"cvmx_pcierc#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2117, 5, 3414},
|
|
{"cvmx_pcierc#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2119, 8, 3419},
|
|
{"cvmx_pcierc#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2121, 19, 3427},
|
|
{"cvmx_pcierc#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2123, 3, 3446},
|
|
{"cvmx_pcierc#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2125, 1, 3449},
|
|
{"cvmx_pcierc#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2127, 1, 3450},
|
|
{"cvmx_pcierc#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2129, 3, 3451},
|
|
{"cvmx_pcierc#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2131, 3, 3454},
|
|
{"cvmx_pcierc#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2133, 3, 3457},
|
|
{"cvmx_pcierc#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2135, 4, 3460},
|
|
{"cvmx_pcierc#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2137, 4, 3464},
|
|
{"cvmx_pcierc#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2139, 4, 3468},
|
|
{"cvmx_pcierc#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2141, 7, 3472},
|
|
{"cvmx_pcierc#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2143, 5, 3479},
|
|
{"cvmx_pcierc#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2145, 5, 3484},
|
|
{"cvmx_pcierc#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2147, 4, 3489},
|
|
{"cvmx_pcierc#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2149, 4, 3493},
|
|
{"cvmx_pcierc#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2151, 4, 3497},
|
|
{"cvmx_pcierc#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2153, 1, 3501},
|
|
{"cvmx_pcierc#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 2155, 1, 3502},
|
|
{"cvmx_pcs#_an#_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2157, 9, 3503},
|
|
{"cvmx_pcs#_an#_ext_st_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2165, 6, 3512},
|
|
{"cvmx_pcs#_an#_lp_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2173, 9, 3518},
|
|
{"cvmx_pcs#_an#_results_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2181, 6, 3527},
|
|
{"cvmx_pcs#_int#_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2189, 13, 3533},
|
|
{"cvmx_pcs#_int#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2197, 13, 3546},
|
|
{"cvmx_pcs#_link#_timer_count_reg", CVMX_CSR_DB_TYPE_RSL, 64, 2205, 2, 3559},
|
|
{"cvmx_pcs#_log_anl#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2213, 4, 3561},
|
|
{"cvmx_pcs#_misc#_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2221, 8, 3565},
|
|
{"cvmx_pcs#_mr#_control_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2229, 13, 3573},
|
|
{"cvmx_pcs#_mr#_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2237, 17, 3586},
|
|
{"cvmx_pcs#_rx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2245, 7, 3603},
|
|
{"cvmx_pcs#_rx#_sync_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2253, 3, 3610},
|
|
{"cvmx_pcs#_sgm#_an_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2261, 8, 3613},
|
|
{"cvmx_pcs#_sgm#_lp_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2269, 7, 3621},
|
|
{"cvmx_pcs#_tx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2277, 4, 3628},
|
|
{"cvmx_pcs#_tx_rx#_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 2285, 5, 3632},
|
|
{"cvmx_pcsx#_10gbx_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2293, 8, 3637},
|
|
{"cvmx_pcsx#_bist_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2295, 2, 3645},
|
|
{"cvmx_pcsx#_bit_lock_status_reg", CVMX_CSR_DB_TYPE_RSL, 64, 2297, 5, 3647},
|
|
{"cvmx_pcsx#_control1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2299, 10, 3652},
|
|
{"cvmx_pcsx#_control2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2301, 2, 3662},
|
|
{"cvmx_pcsx#_int_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2303, 7, 3664},
|
|
{"cvmx_pcsx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2305, 7, 3671},
|
|
{"cvmx_pcsx#_log_anl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2307, 6, 3678},
|
|
{"cvmx_pcsx#_misc_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2309, 5, 3684},
|
|
{"cvmx_pcsx#_rx_sync_states_reg", CVMX_CSR_DB_TYPE_RSL, 64, 2311, 5, 3689},
|
|
{"cvmx_pcsx#_spd_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2313, 3, 3694},
|
|
{"cvmx_pcsx#_status1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2315, 6, 3697},
|
|
{"cvmx_pcsx#_status2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2317, 9, 3703},
|
|
{"cvmx_pcsx#_tx_rx_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 2319, 5, 3712},
|
|
{"cvmx_pcsx#_tx_rx_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2321, 10, 3717},
|
|
{"cvmx_pesc#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2323, 14, 3727},
|
|
{"cvmx_pesc#_bist_status2" , CVMX_CSR_DB_TYPE_RSL, 64, 2325, 15, 3741},
|
|
{"cvmx_pesc#_cfg_rd" , CVMX_CSR_DB_TYPE_RSL, 64, 2327, 2, 3756},
|
|
{"cvmx_pesc#_cfg_wr" , CVMX_CSR_DB_TYPE_RSL, 64, 2329, 2, 3758},
|
|
{"cvmx_pesc#_cpl_lut_valid" , CVMX_CSR_DB_TYPE_RSL, 64, 2331, 2, 3760},
|
|
{"cvmx_pesc#_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2333, 16, 3762},
|
|
{"cvmx_pesc#_ctl_status2" , CVMX_CSR_DB_TYPE_RSL, 64, 2335, 3, 3778},
|
|
{"cvmx_pesc#_dbg_info" , CVMX_CSR_DB_TYPE_RSL, 64, 2337, 32, 3781},
|
|
{"cvmx_pesc#_dbg_info_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2339, 32, 3813},
|
|
{"cvmx_pesc#_diag_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2341, 5, 3845},
|
|
{"cvmx_pesc#_p2n_bar0_start" , CVMX_CSR_DB_TYPE_RSL, 64, 2343, 2, 3850},
|
|
{"cvmx_pesc#_p2n_bar1_start" , CVMX_CSR_DB_TYPE_RSL, 64, 2345, 2, 3852},
|
|
{"cvmx_pesc#_p2n_bar2_start" , CVMX_CSR_DB_TYPE_RSL, 64, 2347, 2, 3854},
|
|
{"cvmx_pesc#_p2p_bar#_end" , CVMX_CSR_DB_TYPE_RSL, 64, 2349, 2, 3856},
|
|
{"cvmx_pesc#_p2p_bar#_start" , CVMX_CSR_DB_TYPE_RSL, 64, 2357, 2, 3858},
|
|
{"cvmx_pesc#_tlp_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 2365, 8, 3860},
|
|
{"cvmx_pip_bck_prs" , CVMX_CSR_DB_TYPE_RSL, 64, 2367, 5, 3868},
|
|
{"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2368, 2, 3873},
|
|
{"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 2369, 4, 3875},
|
|
{"cvmx_pip_dsa_src_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 2373, 16, 3879},
|
|
{"cvmx_pip_dsa_vid_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 2374, 16, 3895},
|
|
{"cvmx_pip_frm_len_chk#" , CVMX_CSR_DB_TYPE_RSL, 64, 2375, 3, 3911},
|
|
{"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 2377, 8, 3914},
|
|
{"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2378, 22, 3922},
|
|
{"cvmx_pip_hg_pri_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 2379, 6, 3944},
|
|
{"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2380, 14, 3950},
|
|
{"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 2381, 14, 3964},
|
|
{"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 2382, 2, 3978},
|
|
{"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 2383, 28, 3980},
|
|
{"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 2399, 25, 4008},
|
|
{"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 2415, 2, 4033},
|
|
{"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 2479, 4, 4035},
|
|
{"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 2487, 9, 4039},
|
|
{"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 2495, 2, 4048},
|
|
{"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 2496, 2, 4050},
|
|
{"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2497, 2, 4052},
|
|
{"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2513, 2, 4054},
|
|
{"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2529, 2, 4056},
|
|
{"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2545, 2, 4058},
|
|
{"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2561, 2, 4060},
|
|
{"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2577, 2, 4062},
|
|
{"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2593, 2, 4064},
|
|
{"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2609, 2, 4066},
|
|
{"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2625, 2, 4068},
|
|
{"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2641, 2, 4070},
|
|
{"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2657, 2, 4072},
|
|
{"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 2658, 2, 4074},
|
|
{"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 2674, 2, 4076},
|
|
{"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 2690, 2, 4078},
|
|
{"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 2706, 2, 4080},
|
|
{"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2770, 2, 4082},
|
|
{"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 2771, 3, 4084},
|
|
{"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 2772, 3, 4087},
|
|
{"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 2773, 2, 4090},
|
|
{"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 2774, 2, 4092},
|
|
{"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2775, 4, 4094},
|
|
{"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2776, 5, 4098},
|
|
{"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 2777, 4, 4103},
|
|
{"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 2778, 8, 4107},
|
|
{"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 2779, 4, 4115},
|
|
{"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 2780, 5, 4119},
|
|
{"cvmx_pko_mem_debug14" , CVMX_CSR_DB_TYPE_RSL, 64, 2781, 1, 4124},
|
|
{"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2782, 5, 4125},
|
|
{"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2783, 1, 4130},
|
|
{"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 2784, 13, 4131},
|
|
{"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 2785, 4, 4144},
|
|
{"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 2786, 13, 4148},
|
|
{"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 2787, 6, 4161},
|
|
{"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 2788, 9, 4167},
|
|
{"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 2789, 4, 4176},
|
|
{"cvmx_pko_mem_port_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 2790, 7, 4180},
|
|
{"cvmx_pko_mem_port_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 2791, 5, 4187},
|
|
{"cvmx_pko_mem_port_rate0" , CVMX_CSR_DB_TYPE_RSL, 64, 2792, 5, 4192},
|
|
{"cvmx_pko_mem_port_rate1" , CVMX_CSR_DB_TYPE_RSL, 64, 2793, 4, 4197},
|
|
{"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 2794, 9, 4201},
|
|
{"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 2795, 5, 4210},
|
|
{"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2796, 16, 4215},
|
|
{"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2797, 4, 4231},
|
|
{"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2798, 1, 4235},
|
|
{"cvmx_pko_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2799, 1, 4236},
|
|
{"cvmx_pko_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2800, 1, 4237},
|
|
{"cvmx_pko_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2801, 1, 4238},
|
|
{"cvmx_pko_reg_engine_inflight", CVMX_CSR_DB_TYPE_RSL, 64, 2802, 11, 4239},
|
|
{"cvmx_pko_reg_engine_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 2803, 2, 4250},
|
|
{"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2804, 4, 4252},
|
|
{"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2805, 5, 4256},
|
|
{"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2806, 3, 4261},
|
|
{"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2807, 4, 4264},
|
|
{"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2808, 2, 4268},
|
|
{"cvmx_pko_reg_queue_ptrs1" , CVMX_CSR_DB_TYPE_RSL, 64, 2809, 3, 4270},
|
|
{"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2810, 3, 4273},
|
|
{"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 2811, 13, 4276},
|
|
{"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2812, 2, 4289},
|
|
{"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 2813, 13, 4291},
|
|
{"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 2814, 3, 4304},
|
|
{"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2815, 2, 4307},
|
|
{"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2823, 2, 4309},
|
|
{"cvmx_pow_iq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 2824, 2, 4311},
|
|
{"cvmx_pow_iq_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 2825, 2, 4313},
|
|
{"cvmx_pow_iq_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2826, 2, 4315},
|
|
{"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2834, 2, 4317},
|
|
{"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 2835, 2, 4319},
|
|
{"cvmx_pow_pf_rst_msk" , CVMX_CSR_DB_TYPE_NCB, 64, 2836, 2, 4321},
|
|
{"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 2837, 10, 4323},
|
|
{"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 2849, 5, 4333},
|
|
{"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2857, 8, 4338},
|
|
{"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2865, 2, 4346},
|
|
{"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2866, 2, 4348},
|
|
{"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2867, 2, 4350},
|
|
{"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 2875, 3, 4352},
|
|
{"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2876, 4, 4355},
|
|
{"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2892, 5, 4359},
|
|
{"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2893, 7, 4364},
|
|
{"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2909, 2, 4371},
|
|
{"cvmx_rad_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2925, 1, 4373},
|
|
{"cvmx_rad_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2926, 1, 4374},
|
|
{"cvmx_rad_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2927, 1, 4375},
|
|
{"cvmx_rad_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2928, 5, 4376},
|
|
{"cvmx_rad_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2929, 5, 4381},
|
|
{"cvmx_rad_reg_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2930, 4, 4386},
|
|
{"cvmx_rad_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2931, 10, 4390},
|
|
{"cvmx_rad_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2932, 1, 4400},
|
|
{"cvmx_rad_reg_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 2933, 3, 4401},
|
|
{"cvmx_rad_reg_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 2934, 7, 4404},
|
|
{"cvmx_rad_reg_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 2935, 2, 4411},
|
|
{"cvmx_rad_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2936, 1, 4413},
|
|
{"cvmx_rad_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2937, 1, 4414},
|
|
{"cvmx_rad_reg_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 2938, 1, 4415},
|
|
{"cvmx_rad_reg_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 2939, 18, 4416},
|
|
{"cvmx_rad_reg_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 2940, 3, 4434},
|
|
{"cvmx_rad_reg_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 2941, 2, 4437},
|
|
{"cvmx_rad_reg_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 2942, 3, 4439},
|
|
{"cvmx_rad_reg_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 2943, 7, 4442},
|
|
{"cvmx_rad_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2944, 2, 4449},
|
|
{"cvmx_rad_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2945, 2, 4451},
|
|
{"cvmx_rad_reg_polynomial" , CVMX_CSR_DB_TYPE_RSL, 64, 2946, 2, 4453},
|
|
{"cvmx_rad_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2947, 3, 4455},
|
|
{"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2948, 3, 4458},
|
|
{"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2949, 7, 4461},
|
|
{"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 2950, 10, 4468},
|
|
{"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2952, 6, 4478},
|
|
{"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2954, 2, 4484},
|
|
{"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2956, 4, 4486},
|
|
{"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2958, 4, 4490},
|
|
{"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2960, 6, 4494},
|
|
{"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2961, 3, 4500},
|
|
{"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2962, 5, 4503},
|
|
{"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 2963, 4, 4508},
|
|
{"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 2964, 6, 4512},
|
|
{"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2965, 4, 4518},
|
|
{"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2966, 2, 4522},
|
|
{"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2967, 4, 4524},
|
|
{"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2968, 2, 4528},
|
|
{"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2969, 3, 4530},
|
|
{"cvmx_tra_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2970, 4, 4533},
|
|
{"cvmx_tra_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2971, 12, 4537},
|
|
{"cvmx_tra_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 2972, 3, 4549},
|
|
{"cvmx_tra_cycles_since1" , CVMX_CSR_DB_TYPE_RSL, 64, 2973, 5, 4552},
|
|
{"cvmx_tra_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2974, 2, 4557},
|
|
{"cvmx_tra_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2975, 2, 4559},
|
|
{"cvmx_tra_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2976, 18, 4561},
|
|
{"cvmx_tra_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2977, 12, 4579},
|
|
{"cvmx_tra_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2978, 6, 4591},
|
|
{"cvmx_tra_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2979, 5, 4597},
|
|
{"cvmx_tra_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2980, 1, 4602},
|
|
{"cvmx_tra_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2981, 2, 4603},
|
|
{"cvmx_tra_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2982, 2, 4605},
|
|
{"cvmx_tra_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2983, 18, 4607},
|
|
{"cvmx_tra_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2984, 12, 4625},
|
|
{"cvmx_tra_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2985, 6, 4637},
|
|
{"cvmx_tra_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2986, 2, 4643},
|
|
{"cvmx_tra_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2987, 2, 4645},
|
|
{"cvmx_tra_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2988, 18, 4647},
|
|
{"cvmx_tra_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2989, 12, 4665},
|
|
{"cvmx_tra_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2990, 6, 4677},
|
|
{"cvmx_usbc#_daint" , CVMX_CSR_DB_TYPE_NCB, 32, 2991, 2, 4683},
|
|
{"cvmx_usbc#_daintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 2992, 2, 4685},
|
|
{"cvmx_usbc#_dcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 2993, 8, 4687},
|
|
{"cvmx_usbc#_dctl" , CVMX_CSR_DB_TYPE_NCB, 32, 2994, 11, 4695},
|
|
{"cvmx_usbc#_diepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 2995, 15, 4706},
|
|
{"cvmx_usbc#_diepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 3000, 8, 4721},
|
|
{"cvmx_usbc#_diepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 3005, 8, 4729},
|
|
{"cvmx_usbc#_dieptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 3006, 4, 4737},
|
|
{"cvmx_usbc#_doepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 3011, 15, 4741},
|
|
{"cvmx_usbc#_doepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 3016, 6, 4756},
|
|
{"cvmx_usbc#_doepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 3021, 6, 4762},
|
|
{"cvmx_usbc#_doeptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 3022, 4, 4768},
|
|
{"cvmx_usbc#_dptxfsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 3027, 2, 4772},
|
|
{"cvmx_usbc#_dsts" , CVMX_CSR_DB_TYPE_NCB, 32, 3031, 6, 4774},
|
|
{"cvmx_usbc#_dtknqr1" , CVMX_CSR_DB_TYPE_NCB, 32, 3032, 4, 4780},
|
|
{"cvmx_usbc#_dtknqr2" , CVMX_CSR_DB_TYPE_NCB, 32, 3033, 1, 4784},
|
|
{"cvmx_usbc#_dtknqr3" , CVMX_CSR_DB_TYPE_NCB, 32, 3034, 1, 4785},
|
|
{"cvmx_usbc#_dtknqr4" , CVMX_CSR_DB_TYPE_NCB, 32, 3035, 1, 4786},
|
|
{"cvmx_usbc#_gahbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 3036, 7, 4787},
|
|
{"cvmx_usbc#_ghwcfg1" , CVMX_CSR_DB_TYPE_NCB, 32, 3037, 1, 4794},
|
|
{"cvmx_usbc#_ghwcfg2" , CVMX_CSR_DB_TYPE_NCB, 32, 3038, 14, 4795},
|
|
{"cvmx_usbc#_ghwcfg3" , CVMX_CSR_DB_TYPE_NCB, 32, 3039, 10, 4809},
|
|
{"cvmx_usbc#_ghwcfg4" , CVMX_CSR_DB_TYPE_NCB, 32, 3040, 14, 4819},
|
|
{"cvmx_usbc#_gintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 3041, 32, 4833},
|
|
{"cvmx_usbc#_gintsts" , CVMX_CSR_DB_TYPE_NCB, 32, 3042, 32, 4865},
|
|
{"cvmx_usbc#_gnptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 3043, 2, 4897},
|
|
{"cvmx_usbc#_gnptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 3044, 4, 4899},
|
|
{"cvmx_usbc#_gotgctl" , CVMX_CSR_DB_TYPE_NCB, 32, 3045, 13, 4903},
|
|
{"cvmx_usbc#_gotgint" , CVMX_CSR_DB_TYPE_NCB, 32, 3046, 10, 4916},
|
|
{"cvmx_usbc#_grstctl" , CVMX_CSR_DB_TYPE_NCB, 32, 3047, 10, 4926},
|
|
{"cvmx_usbc#_grxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 3048, 2, 4936},
|
|
{"cvmx_usbc#_grxstspd" , CVMX_CSR_DB_TYPE_NCB, 32, 3049, 6, 4938},
|
|
{"cvmx_usbc#_grxstsph" , CVMX_CSR_DB_TYPE_NCB, 32, 3050, 5, 4944},
|
|
{"cvmx_usbc#_grxstsrd" , CVMX_CSR_DB_TYPE_NCB, 32, 3051, 6, 4949},
|
|
{"cvmx_usbc#_grxstsrh" , CVMX_CSR_DB_TYPE_NCB, 32, 3052, 5, 4955},
|
|
{"cvmx_usbc#_gsnpsid" , CVMX_CSR_DB_TYPE_NCB, 32, 3053, 1, 4960},
|
|
{"cvmx_usbc#_gusbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 3054, 13, 4961},
|
|
{"cvmx_usbc#_haint" , CVMX_CSR_DB_TYPE_NCB, 32, 3055, 2, 4974},
|
|
{"cvmx_usbc#_haintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 3056, 2, 4976},
|
|
{"cvmx_usbc#_hcchar#" , CVMX_CSR_DB_TYPE_NCB, 32, 3057, 11, 4978},
|
|
{"cvmx_usbc#_hcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 3065, 3, 4989},
|
|
{"cvmx_usbc#_hcint#" , CVMX_CSR_DB_TYPE_NCB, 32, 3066, 12, 4992},
|
|
{"cvmx_usbc#_hcintmsk#" , CVMX_CSR_DB_TYPE_NCB, 32, 3074, 12, 5004},
|
|
{"cvmx_usbc#_hcsplt#" , CVMX_CSR_DB_TYPE_NCB, 32, 3082, 6, 5016},
|
|
{"cvmx_usbc#_hctsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 3090, 4, 5022},
|
|
{"cvmx_usbc#_hfir" , CVMX_CSR_DB_TYPE_NCB, 32, 3098, 2, 5026},
|
|
{"cvmx_usbc#_hfnum" , CVMX_CSR_DB_TYPE_NCB, 32, 3099, 2, 5028},
|
|
{"cvmx_usbc#_hprt" , CVMX_CSR_DB_TYPE_NCB, 32, 3100, 15, 5030},
|
|
{"cvmx_usbc#_hptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 3101, 2, 5045},
|
|
{"cvmx_usbc#_hptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 3102, 3, 5047},
|
|
{"cvmx_usbc#_nptxdfifo#" , CVMX_CSR_DB_TYPE_NCB, 32, 3103, 1, 5050},
|
|
{"cvmx_usbc#_pcgcctl" , CVMX_CSR_DB_TYPE_NCB, 32, 3111, 6, 5051},
|
|
{"cvmx_usbn#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 3112, 8, 5057},
|
|
{"cvmx_usbn#_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 3113, 15, 5065},
|
|
{"cvmx_usbn#_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 3114, 6, 5080},
|
|
{"cvmx_usbn#_dma0_inb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 3115, 2, 5086},
|
|
{"cvmx_usbn#_dma0_inb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 3116, 2, 5088},
|
|
{"cvmx_usbn#_dma0_inb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 3117, 2, 5090},
|
|
{"cvmx_usbn#_dma0_inb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 3118, 2, 5092},
|
|
{"cvmx_usbn#_dma0_inb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 3119, 2, 5094},
|
|
{"cvmx_usbn#_dma0_inb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 3120, 2, 5096},
|
|
{"cvmx_usbn#_dma0_inb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 3121, 2, 5098},
|
|
{"cvmx_usbn#_dma0_inb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 3122, 2, 5100},
|
|
{"cvmx_usbn#_dma0_outb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 3123, 2, 5102},
|
|
{"cvmx_usbn#_dma0_outb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 3124, 2, 5104},
|
|
{"cvmx_usbn#_dma0_outb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 3125, 2, 5106},
|
|
{"cvmx_usbn#_dma0_outb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 3126, 2, 5108},
|
|
{"cvmx_usbn#_dma0_outb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 3127, 2, 5110},
|
|
{"cvmx_usbn#_dma0_outb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 3128, 2, 5112},
|
|
{"cvmx_usbn#_dma0_outb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 3129, 2, 5114},
|
|
{"cvmx_usbn#_dma0_outb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 3130, 2, 5116},
|
|
{"cvmx_usbn#_dma_test" , CVMX_CSR_DB_TYPE_NCB, 64, 3131, 7, 5118},
|
|
{"cvmx_usbn#_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 3132, 34, 5125},
|
|
{"cvmx_usbn#_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 3133, 34, 5159},
|
|
{"cvmx_usbn#_usbp_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 3134, 35, 5193},
|
|
{"cvmx_zip_cmd_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 3135, 3, 5228},
|
|
{"cvmx_zip_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 3136, 5, 5231},
|
|
{"cvmx_zip_cmd_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 3137, 3, 5236},
|
|
{"cvmx_zip_constants" , CVMX_CSR_DB_TYPE_RSL, 64, 3138, 6, 5239},
|
|
{"cvmx_zip_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 3139, 2, 5245},
|
|
{"cvmx_zip_error" , CVMX_CSR_DB_TYPE_RSL, 64, 3140, 2, 5247},
|
|
{"cvmx_zip_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 3141, 2, 5249},
|
|
{NULL,0,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
|
|
/* name , --------------address, ---------------type, bits, csr offset */
|
|
{"AGL_GMX_BAD_REG" , 0x11800E0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
|
|
{"AGL_GMX_BIST" , 0x11800E0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
|
|
{"AGL_GMX_DRV_CTL" , 0x11800E00007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
|
|
{"AGL_GMX_INF_MODE" , 0x11800E00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
|
|
{"AGL_GMX_PRT0_CFG" , 0x11800E0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
|
|
{"AGL_GMX_RX0_ADR_CAM0" , 0x11800E0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
|
|
{"AGL_GMX_RX0_ADR_CAM1" , 0x11800E0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
|
|
{"AGL_GMX_RX0_ADR_CAM2" , 0x11800E0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
|
|
{"AGL_GMX_RX0_ADR_CAM3" , 0x11800E0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
|
|
{"AGL_GMX_RX0_ADR_CAM4" , 0x11800E00001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
|
|
{"AGL_GMX_RX0_ADR_CAM5" , 0x11800E00001A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
|
|
{"AGL_GMX_RX0_ADR_CAM_EN" , 0x11800E0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
|
|
{"AGL_GMX_RX0_ADR_CTL" , 0x11800E0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"AGL_GMX_RX0_DECISION" , 0x11800E0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"AGL_GMX_RX0_FRM_CHK" , 0x11800E0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"AGL_GMX_RX0_FRM_CTL" , 0x11800E0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
|
|
{"AGL_GMX_RX0_FRM_MAX" , 0x11800E0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"AGL_GMX_RX0_FRM_MIN" , 0x11800E0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
|
|
{"AGL_GMX_RX0_IFG" , 0x11800E0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
|
|
{"AGL_GMX_RX0_INT_EN" , 0x11800E0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
|
|
{"AGL_GMX_RX0_INT_REG" , 0x11800E0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
|
|
{"AGL_GMX_RX0_JABBER" , 0x11800E0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
|
|
{"AGL_GMX_RX0_PAUSE_DROP_TIME" , 0x11800E0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
|
|
{"AGL_GMX_RX0_STATS_CTL" , 0x11800E0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
|
|
{"AGL_GMX_RX0_STATS_OCTS" , 0x11800E0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
|
|
{"AGL_GMX_RX0_STATS_OCTS_CTL" , 0x11800E0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 25},
|
|
{"AGL_GMX_RX0_STATS_OCTS_DMAC" , 0x11800E00000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 26},
|
|
{"AGL_GMX_RX0_STATS_OCTS_DRP" , 0x11800E00000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 27},
|
|
{"AGL_GMX_RX0_STATS_PKTS" , 0x11800E0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 28},
|
|
{"AGL_GMX_RX0_STATS_PKTS_BAD" , 0x11800E00000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 29},
|
|
{"AGL_GMX_RX0_STATS_PKTS_CTL" , 0x11800E0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 30},
|
|
{"AGL_GMX_RX0_STATS_PKTS_DMAC" , 0x11800E00000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 31},
|
|
{"AGL_GMX_RX0_STATS_PKTS_DRP" , 0x11800E00000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
|
|
{"AGL_GMX_RX0_UDD_SKP" , 0x11800E0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
|
|
{"AGL_GMX_RX_BP_DROP0" , 0x11800E0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 34},
|
|
{"AGL_GMX_RX_BP_OFF0" , 0x11800E0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
|
|
{"AGL_GMX_RX_BP_ON0" , 0x11800E0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
|
|
{"AGL_GMX_RX_PRT_INFO" , 0x11800E00004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
|
|
{"AGL_GMX_RX_TX_STATUS" , 0x11800E00007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
|
|
{"AGL_GMX_SMAC0" , 0x11800E0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
|
|
{"AGL_GMX_STAT_BP" , 0x11800E0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
|
|
{"AGL_GMX_TX0_APPEND" , 0x11800E0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
|
|
{"AGL_GMX_TX0_CTL" , 0x11800E0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
|
|
{"AGL_GMX_TX0_MIN_PKT" , 0x11800E0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
|
|
{"AGL_GMX_TX0_PAUSE_PKT_INTERVAL", 0x11800E0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
|
|
{"AGL_GMX_TX0_PAUSE_PKT_TIME" , 0x11800E0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
|
|
{"AGL_GMX_TX0_PAUSE_TOGO" , 0x11800E0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
|
|
{"AGL_GMX_TX0_PAUSE_ZERO" , 0x11800E0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
|
|
{"AGL_GMX_TX0_SOFT_PAUSE" , 0x11800E0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
|
|
{"AGL_GMX_TX0_STAT0" , 0x11800E0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
|
|
{"AGL_GMX_TX0_STAT1" , 0x11800E0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
|
|
{"AGL_GMX_TX0_STAT2" , 0x11800E0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
|
|
{"AGL_GMX_TX0_STAT3" , 0x11800E0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
|
|
{"AGL_GMX_TX0_STAT4" , 0x11800E00002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
|
|
{"AGL_GMX_TX0_STAT5" , 0x11800E00002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
|
|
{"AGL_GMX_TX0_STAT6" , 0x11800E00002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
|
|
{"AGL_GMX_TX0_STAT7" , 0x11800E00002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
|
|
{"AGL_GMX_TX0_STAT8" , 0x11800E00002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
|
|
{"AGL_GMX_TX0_STAT9" , 0x11800E00002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
|
|
{"AGL_GMX_TX0_STATS_CTL" , 0x11800E0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
|
|
{"AGL_GMX_TX0_THRESH" , 0x11800E0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
|
|
{"AGL_GMX_TX_BP" , 0x11800E00004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
|
|
{"AGL_GMX_TX_COL_ATTEMPT" , 0x11800E0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
|
|
{"AGL_GMX_TX_IFG" , 0x11800E0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
|
|
{"AGL_GMX_TX_INT_EN" , 0x11800E0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
|
|
{"AGL_GMX_TX_INT_REG" , 0x11800E0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
|
|
{"AGL_GMX_TX_JAM" , 0x11800E0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"AGL_GMX_TX_LFSR" , 0x11800E00004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"AGL_GMX_TX_OVR_BP" , 0x11800E00004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
|
|
{"AGL_GMX_TX_PAUSE_PKT_DMAC" , 0x11800E00004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
|
|
{"AGL_GMX_TX_PAUSE_PKT_TYPE" , 0x11800E00004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
|
|
{"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 71},
|
|
{"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 72},
|
|
{"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
|
|
{"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
|
|
{"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT4_EN0" , 0x1070000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT5_EN0" , 0x1070000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT6_EN0" , 0x1070000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT7_EN0" , 0x1070000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT8_EN0" , 0x1070000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT9_EN0" , 0x1070000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT10_EN0" , 0x10700000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT11_EN0" , 0x10700000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT12_EN0" , 0x10700000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT13_EN0" , 0x10700000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT14_EN0" , 0x10700000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT15_EN0" , 0x10700000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT16_EN0" , 0x1070000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT17_EN0" , 0x1070000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT18_EN0" , 0x1070000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT19_EN0" , 0x1070000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT20_EN0" , 0x1070000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT21_EN0" , 0x1070000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT22_EN0" , 0x1070000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT23_EN0" , 0x1070000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT0_EN0_W1C" , 0x1070000002200ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT1_EN0_W1C" , 0x1070000002210ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT2_EN0_W1C" , 0x1070000002220ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT3_EN0_W1C" , 0x1070000002230ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT4_EN0_W1C" , 0x1070000002240ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT5_EN0_W1C" , 0x1070000002250ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT6_EN0_W1C" , 0x1070000002260ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT7_EN0_W1C" , 0x1070000002270ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT8_EN0_W1C" , 0x1070000002280ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT9_EN0_W1C" , 0x1070000002290ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT10_EN0_W1C" , 0x10700000022A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT11_EN0_W1C" , 0x10700000022B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT12_EN0_W1C" , 0x10700000022C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT13_EN0_W1C" , 0x10700000022D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT14_EN0_W1C" , 0x10700000022E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT15_EN0_W1C" , 0x10700000022F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT16_EN0_W1C" , 0x1070000002300ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT17_EN0_W1C" , 0x1070000002310ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT18_EN0_W1C" , 0x1070000002320ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT19_EN0_W1C" , 0x1070000002330ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT20_EN0_W1C" , 0x1070000002340ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT21_EN0_W1C" , 0x1070000002350ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT22_EN0_W1C" , 0x1070000002360ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT23_EN0_W1C" , 0x1070000002370ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT32_EN0_W1C" , 0x1070000002400ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT0_EN0_W1S" , 0x1070000006200ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT1_EN0_W1S" , 0x1070000006210ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT2_EN0_W1S" , 0x1070000006220ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT3_EN0_W1S" , 0x1070000006230ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT4_EN0_W1S" , 0x1070000006240ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT5_EN0_W1S" , 0x1070000006250ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT6_EN0_W1S" , 0x1070000006260ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT7_EN0_W1S" , 0x1070000006270ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT8_EN0_W1S" , 0x1070000006280ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT9_EN0_W1S" , 0x1070000006290ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT10_EN0_W1S" , 0x10700000062A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT11_EN0_W1S" , 0x10700000062B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT12_EN0_W1S" , 0x10700000062C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT13_EN0_W1S" , 0x10700000062D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT14_EN0_W1S" , 0x10700000062E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT15_EN0_W1S" , 0x10700000062F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT16_EN0_W1S" , 0x1070000006300ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT17_EN0_W1S" , 0x1070000006310ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT18_EN0_W1S" , 0x1070000006320ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT19_EN0_W1S" , 0x1070000006330ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT20_EN0_W1S" , 0x1070000006340ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT21_EN0_W1S" , 0x1070000006350ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT22_EN0_W1S" , 0x1070000006360ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT23_EN0_W1S" , 0x1070000006370ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT32_EN0_W1S" , 0x1070000006400ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT4_EN1" , 0x1070000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT5_EN1" , 0x1070000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT6_EN1" , 0x1070000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT7_EN1" , 0x1070000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT8_EN1" , 0x1070000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT9_EN1" , 0x1070000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT10_EN1" , 0x10700000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT11_EN1" , 0x10700000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT12_EN1" , 0x10700000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT13_EN1" , 0x10700000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT14_EN1" , 0x10700000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT15_EN1" , 0x10700000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT16_EN1" , 0x1070000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT17_EN1" , 0x1070000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT18_EN1" , 0x1070000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT19_EN1" , 0x1070000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT20_EN1" , 0x1070000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT21_EN1" , 0x1070000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT22_EN1" , 0x1070000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT23_EN1" , 0x1070000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT0_EN1_W1C" , 0x1070000002208ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT1_EN1_W1C" , 0x1070000002218ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT2_EN1_W1C" , 0x1070000002228ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT3_EN1_W1C" , 0x1070000002238ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT4_EN1_W1C" , 0x1070000002248ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT5_EN1_W1C" , 0x1070000002258ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT6_EN1_W1C" , 0x1070000002268ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT7_EN1_W1C" , 0x1070000002278ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT8_EN1_W1C" , 0x1070000002288ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT9_EN1_W1C" , 0x1070000002298ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT10_EN1_W1C" , 0x10700000022A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT11_EN1_W1C" , 0x10700000022B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT12_EN1_W1C" , 0x10700000022C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT13_EN1_W1C" , 0x10700000022D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT14_EN1_W1C" , 0x10700000022E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT15_EN1_W1C" , 0x10700000022F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT16_EN1_W1C" , 0x1070000002308ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT17_EN1_W1C" , 0x1070000002318ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT18_EN1_W1C" , 0x1070000002328ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT19_EN1_W1C" , 0x1070000002338ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT20_EN1_W1C" , 0x1070000002348ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT21_EN1_W1C" , 0x1070000002358ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT22_EN1_W1C" , 0x1070000002368ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT23_EN1_W1C" , 0x1070000002378ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT32_EN1_W1C" , 0x1070000002408ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT0_EN1_W1S" , 0x1070000006208ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT1_EN1_W1S" , 0x1070000006218ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT2_EN1_W1S" , 0x1070000006228ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT3_EN1_W1S" , 0x1070000006238ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT4_EN1_W1S" , 0x1070000006248ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT5_EN1_W1S" , 0x1070000006258ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT6_EN1_W1S" , 0x1070000006268ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT7_EN1_W1S" , 0x1070000006278ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT8_EN1_W1S" , 0x1070000006288ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT9_EN1_W1S" , 0x1070000006298ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT10_EN1_W1S" , 0x10700000062A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT11_EN1_W1S" , 0x10700000062B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT12_EN1_W1S" , 0x10700000062C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT13_EN1_W1S" , 0x10700000062D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT14_EN1_W1S" , 0x10700000062E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT15_EN1_W1S" , 0x10700000062F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT16_EN1_W1S" , 0x1070000006308ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT17_EN1_W1S" , 0x1070000006318ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT18_EN1_W1S" , 0x1070000006328ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT19_EN1_W1S" , 0x1070000006338ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT20_EN1_W1S" , 0x1070000006348ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT21_EN1_W1S" , 0x1070000006358ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT22_EN1_W1S" , 0x1070000006368ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT23_EN1_W1S" , 0x1070000006378ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT32_EN1_W1S" , 0x1070000006408ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT0_EN4_0" , 0x1070000000C80ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
|
|
{"CIU_INT1_EN4_0" , 0x1070000000C90ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
|
|
{"CIU_INT2_EN4_0" , 0x1070000000CA0ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
|
|
{"CIU_INT3_EN4_0" , 0x1070000000CB0ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
|
|
{"CIU_INT4_EN4_0" , 0x1070000000CC0ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
|
|
{"CIU_INT5_EN4_0" , 0x1070000000CD0ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
|
|
{"CIU_INT6_EN4_0" , 0x1070000000CE0ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
|
|
{"CIU_INT7_EN4_0" , 0x1070000000CF0ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
|
|
{"CIU_INT8_EN4_0" , 0x1070000000D00ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
|
|
{"CIU_INT9_EN4_0" , 0x1070000000D10ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
|
|
{"CIU_INT10_EN4_0" , 0x1070000000D20ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
|
|
{"CIU_INT11_EN4_0" , 0x1070000000D30ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
|
|
{"CIU_INT0_EN4_0_W1C" , 0x1070000002C80ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_INT1_EN4_0_W1C" , 0x1070000002C90ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_INT2_EN4_0_W1C" , 0x1070000002CA0ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_INT3_EN4_0_W1C" , 0x1070000002CB0ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_INT4_EN4_0_W1C" , 0x1070000002CC0ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_INT5_EN4_0_W1C" , 0x1070000002CD0ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_INT6_EN4_0_W1C" , 0x1070000002CE0ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_INT7_EN4_0_W1C" , 0x1070000002CF0ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_INT8_EN4_0_W1C" , 0x1070000002D00ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_INT9_EN4_0_W1C" , 0x1070000002D10ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_INT10_EN4_0_W1C" , 0x1070000002D20ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_INT11_EN4_0_W1C" , 0x1070000002D30ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_INT0_EN4_0_W1S" , 0x1070000006C80ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_INT1_EN4_0_W1S" , 0x1070000006C90ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_INT2_EN4_0_W1S" , 0x1070000006CA0ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_INT3_EN4_0_W1S" , 0x1070000006CB0ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_INT4_EN4_0_W1S" , 0x1070000006CC0ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_INT5_EN4_0_W1S" , 0x1070000006CD0ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_INT6_EN4_0_W1S" , 0x1070000006CE0ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_INT7_EN4_0_W1S" , 0x1070000006CF0ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_INT8_EN4_0_W1S" , 0x1070000006D00ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_INT9_EN4_0_W1S" , 0x1070000006D10ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_INT10_EN4_0_W1S" , 0x1070000006D20ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_INT11_EN4_0_W1S" , 0x1070000006D30ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_INT0_EN4_1" , 0x1070000000C88ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
|
|
{"CIU_INT1_EN4_1" , 0x1070000000C98ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
|
|
{"CIU_INT2_EN4_1" , 0x1070000000CA8ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
|
|
{"CIU_INT3_EN4_1" , 0x1070000000CB8ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
|
|
{"CIU_INT4_EN4_1" , 0x1070000000CC8ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
|
|
{"CIU_INT5_EN4_1" , 0x1070000000CD8ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
|
|
{"CIU_INT6_EN4_1" , 0x1070000000CE8ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
|
|
{"CIU_INT7_EN4_1" , 0x1070000000CF8ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
|
|
{"CIU_INT8_EN4_1" , 0x1070000000D08ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
|
|
{"CIU_INT9_EN4_1" , 0x1070000000D18ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
|
|
{"CIU_INT10_EN4_1" , 0x1070000000D28ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
|
|
{"CIU_INT11_EN4_1" , 0x1070000000D38ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
|
|
{"CIU_INT0_EN4_1_W1C" , 0x1070000002C88ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
|
|
{"CIU_INT1_EN4_1_W1C" , 0x1070000002C98ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
|
|
{"CIU_INT2_EN4_1_W1C" , 0x1070000002CA8ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
|
|
{"CIU_INT3_EN4_1_W1C" , 0x1070000002CB8ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
|
|
{"CIU_INT4_EN4_1_W1C" , 0x1070000002CC8ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
|
|
{"CIU_INT5_EN4_1_W1C" , 0x1070000002CD8ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
|
|
{"CIU_INT6_EN4_1_W1C" , 0x1070000002CE8ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
|
|
{"CIU_INT7_EN4_1_W1C" , 0x1070000002CF8ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
|
|
{"CIU_INT8_EN4_1_W1C" , 0x1070000002D08ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
|
|
{"CIU_INT9_EN4_1_W1C" , 0x1070000002D18ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
|
|
{"CIU_INT10_EN4_1_W1C" , 0x1070000002D28ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
|
|
{"CIU_INT11_EN4_1_W1C" , 0x1070000002D38ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
|
|
{"CIU_INT0_EN4_1_W1S" , 0x1070000006C88ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
|
|
{"CIU_INT1_EN4_1_W1S" , 0x1070000006C98ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
|
|
{"CIU_INT2_EN4_1_W1S" , 0x1070000006CA8ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
|
|
{"CIU_INT3_EN4_1_W1S" , 0x1070000006CB8ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
|
|
{"CIU_INT4_EN4_1_W1S" , 0x1070000006CC8ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
|
|
{"CIU_INT5_EN4_1_W1S" , 0x1070000006CD8ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
|
|
{"CIU_INT6_EN4_1_W1S" , 0x1070000006CE8ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
|
|
{"CIU_INT7_EN4_1_W1S" , 0x1070000006CF8ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
|
|
{"CIU_INT8_EN4_1_W1S" , 0x1070000006D08ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
|
|
{"CIU_INT9_EN4_1_W1S" , 0x1070000006D18ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
|
|
{"CIU_INT10_EN4_1_W1S" , 0x1070000006D28ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
|
|
{"CIU_INT11_EN4_1_W1S" , 0x1070000006D38ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
|
|
{"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT4_SUM0" , 0x1070000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT5_SUM0" , 0x1070000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT6_SUM0" , 0x1070000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT7_SUM0" , 0x1070000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT8_SUM0" , 0x1070000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT9_SUM0" , 0x1070000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT10_SUM0" , 0x1070000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT11_SUM0" , 0x1070000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT12_SUM0" , 0x1070000000060ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT13_SUM0" , 0x1070000000068ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT14_SUM0" , 0x1070000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT15_SUM0" , 0x1070000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT16_SUM0" , 0x1070000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT17_SUM0" , 0x1070000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT18_SUM0" , 0x1070000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT19_SUM0" , 0x1070000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT20_SUM0" , 0x10700000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT21_SUM0" , 0x10700000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT22_SUM0" , 0x10700000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT23_SUM0" , 0x10700000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT0_SUM4" , 0x1070000000C00ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
|
|
{"CIU_INT1_SUM4" , 0x1070000000C08ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
|
|
{"CIU_INT2_SUM4" , 0x1070000000C10ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
|
|
{"CIU_INT3_SUM4" , 0x1070000000C18ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
|
|
{"CIU_INT4_SUM4" , 0x1070000000C20ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
|
|
{"CIU_INT5_SUM4" , 0x1070000000C28ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
|
|
{"CIU_INT6_SUM4" , 0x1070000000C30ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
|
|
{"CIU_INT7_SUM4" , 0x1070000000C38ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
|
|
{"CIU_INT8_SUM4" , 0x1070000000C40ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
|
|
{"CIU_INT9_SUM4" , 0x1070000000C48ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
|
|
{"CIU_INT10_SUM4" , 0x1070000000C50ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
|
|
{"CIU_INT11_SUM4" , 0x1070000000C58ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
|
|
{"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
|
|
{"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
|
|
{"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
|
|
{"CIU_MBOX_CLR2" , 0x1070000000690ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
|
|
{"CIU_MBOX_CLR3" , 0x1070000000698ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
|
|
{"CIU_MBOX_CLR4" , 0x10700000006A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
|
|
{"CIU_MBOX_CLR5" , 0x10700000006A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
|
|
{"CIU_MBOX_CLR6" , 0x10700000006B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
|
|
{"CIU_MBOX_CLR7" , 0x10700000006B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
|
|
{"CIU_MBOX_CLR8" , 0x10700000006C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
|
|
{"CIU_MBOX_CLR9" , 0x10700000006C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
|
|
{"CIU_MBOX_CLR10" , 0x10700000006D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
|
|
{"CIU_MBOX_CLR11" , 0x10700000006D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
|
|
{"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
|
|
{"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
|
|
{"CIU_MBOX_SET2" , 0x1070000000610ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
|
|
{"CIU_MBOX_SET3" , 0x1070000000618ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
|
|
{"CIU_MBOX_SET4" , 0x1070000000620ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
|
|
{"CIU_MBOX_SET5" , 0x1070000000628ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
|
|
{"CIU_MBOX_SET6" , 0x1070000000630ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
|
|
{"CIU_MBOX_SET7" , 0x1070000000638ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
|
|
{"CIU_MBOX_SET8" , 0x1070000000640ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
|
|
{"CIU_MBOX_SET9" , 0x1070000000648ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
|
|
{"CIU_MBOX_SET10" , 0x1070000000650ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
|
|
{"CIU_MBOX_SET11" , 0x1070000000658ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
|
|
{"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
|
|
{"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
|
|
{"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
|
|
{"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
|
|
{"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
|
|
{"CIU_PP_POKE2" , 0x1070000000590ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
|
|
{"CIU_PP_POKE3" , 0x1070000000598ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
|
|
{"CIU_PP_POKE4" , 0x10700000005A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
|
|
{"CIU_PP_POKE5" , 0x10700000005A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
|
|
{"CIU_PP_POKE6" , 0x10700000005B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
|
|
{"CIU_PP_POKE7" , 0x10700000005B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
|
|
{"CIU_PP_POKE8" , 0x10700000005C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
|
|
{"CIU_PP_POKE9" , 0x10700000005C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
|
|
{"CIU_PP_POKE10" , 0x10700000005D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
|
|
{"CIU_PP_POKE11" , 0x10700000005D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
|
|
{"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
|
|
{"CIU_QLM_DCOK" , 0x1070000000760ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
|
|
{"CIU_QLM_JTGC" , 0x1070000000768ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
|
|
{"CIU_QLM_JTGD" , 0x1070000000770ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
|
|
{"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 100},
|
|
{"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
|
|
{"CIU_SOFT_PRST1" , 0x1070000000758ull, CVMX_CSR_DB_TYPE_NCB, 64, 102},
|
|
{"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
|
|
{"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
|
|
{"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
|
|
{"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
|
|
{"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
|
|
{"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
|
|
{"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
|
|
{"CIU_WDOG2" , 0x1070000000510ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
|
|
{"CIU_WDOG3" , 0x1070000000518ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
|
|
{"CIU_WDOG4" , 0x1070000000520ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
|
|
{"CIU_WDOG5" , 0x1070000000528ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
|
|
{"CIU_WDOG6" , 0x1070000000530ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
|
|
{"CIU_WDOG7" , 0x1070000000538ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
|
|
{"CIU_WDOG8" , 0x1070000000540ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
|
|
{"CIU_WDOG9" , 0x1070000000548ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
|
|
{"CIU_WDOG10" , 0x1070000000550ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
|
|
{"CIU_WDOG11" , 0x1070000000558ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
|
|
{"FPA_BIST_STATUS" , 0x11800280000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"FPA_FPF1_MARKS" , 0x1180028000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"FPA_FPF2_MARKS" , 0x1180028000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"FPA_FPF3_MARKS" , 0x1180028000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"FPA_FPF4_MARKS" , 0x1180028000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"FPA_FPF5_MARKS" , 0x1180028000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"FPA_FPF6_MARKS" , 0x1180028000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"FPA_FPF7_MARKS" , 0x1180028000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"FPA_FPF1_SIZE" , 0x1180028000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"FPA_FPF2_SIZE" , 0x1180028000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"FPA_FPF3_SIZE" , 0x1180028000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"FPA_FPF4_SIZE" , 0x1180028000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"FPA_FPF5_SIZE" , 0x1180028000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"FPA_FPF6_SIZE" , 0x1180028000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"FPA_FPF7_SIZE" , 0x1180028000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"FPA_FPF0_MARKS" , 0x1180028000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"FPA_FPF0_SIZE" , 0x1180028000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"FPA_QUE1_AVAILABLE" , 0x11800280000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"FPA_QUE2_AVAILABLE" , 0x11800280000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"FPA_QUE3_AVAILABLE" , 0x11800280000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"FPA_QUE4_AVAILABLE" , 0x11800280000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"FPA_QUE5_AVAILABLE" , 0x11800280000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"FPA_QUE6_AVAILABLE" , 0x11800280000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"FPA_QUE7_AVAILABLE" , 0x11800280000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"FPA_QUE0_PAGE_INDEX" , 0x11800280000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"FPA_QUE1_PAGE_INDEX" , 0x11800280000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"FPA_WART_CTL" , 0x11800280000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"FPA_WART_STATUS" , 0x11800280000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX1_BAD_REG" , 0x1180010000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX1_BIST" , 0x1180010000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_CLK_EN" , 0x11800080007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX1_CLK_EN" , 0x11800100007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_HG2_CONTROL" , 0x1180008000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX1_HG2_CONTROL" , 0x1180010000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_INF_MODE" , 0x11800080007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX1_INF_MODE" , 0x11800100007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX1_NXA_ADR" , 0x1180010000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_PRT000_CBFC_CTL" , 0x1180008000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX1_PRT000_CBFC_CTL" , 0x1180010000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_PRT003_CFG" , 0x1180008001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX1_PRT000_CFG" , 0x1180010000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX1_PRT001_CFG" , 0x1180010000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX1_PRT002_CFG" , 0x1180010001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX1_PRT003_CFG" , 0x1180010001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_RX003_ADR_CAM0" , 0x1180008001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX1_RX000_ADR_CAM0" , 0x1180010000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX1_RX001_ADR_CAM0" , 0x1180010000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX1_RX002_ADR_CAM0" , 0x1180010001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX1_RX003_ADR_CAM0" , 0x1180010001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_RX003_ADR_CAM1" , 0x1180008001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX1_RX000_ADR_CAM1" , 0x1180010000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX1_RX001_ADR_CAM1" , 0x1180010000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX1_RX002_ADR_CAM1" , 0x1180010001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX1_RX003_ADR_CAM1" , 0x1180010001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_RX003_ADR_CAM2" , 0x1180008001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX1_RX000_ADR_CAM2" , 0x1180010000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX1_RX001_ADR_CAM2" , 0x1180010000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX1_RX002_ADR_CAM2" , 0x1180010001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX1_RX003_ADR_CAM2" , 0x1180010001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_RX003_ADR_CAM3" , 0x1180008001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX1_RX000_ADR_CAM3" , 0x1180010000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX1_RX001_ADR_CAM3" , 0x1180010000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX1_RX002_ADR_CAM3" , 0x1180010001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX1_RX003_ADR_CAM3" , 0x1180010001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_RX000_ADR_CAM4" , 0x11800080001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_RX001_ADR_CAM4" , 0x11800080009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_RX002_ADR_CAM4" , 0x11800080011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_RX003_ADR_CAM4" , 0x11800080019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX1_RX000_ADR_CAM4" , 0x11800100001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX1_RX001_ADR_CAM4" , 0x11800100009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX1_RX002_ADR_CAM4" , 0x11800100011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX1_RX003_ADR_CAM4" , 0x11800100019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_RX000_ADR_CAM5" , 0x11800080001A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_RX001_ADR_CAM5" , 0x11800080009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_RX002_ADR_CAM5" , 0x11800080011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_RX003_ADR_CAM5" , 0x11800080019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX1_RX000_ADR_CAM5" , 0x11800100001A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX1_RX001_ADR_CAM5" , 0x11800100009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX1_RX002_ADR_CAM5" , 0x11800100011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX1_RX003_ADR_CAM5" , 0x11800100019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_RX003_ADR_CAM_EN" , 0x1180008001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX1_RX000_ADR_CAM_EN" , 0x1180010000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX1_RX001_ADR_CAM_EN" , 0x1180010000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX1_RX002_ADR_CAM_EN" , 0x1180010001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX1_RX003_ADR_CAM_EN" , 0x1180010001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_RX003_ADR_CTL" , 0x1180008001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX1_RX000_ADR_CTL" , 0x1180010000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX1_RX001_ADR_CTL" , 0x1180010000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX1_RX002_ADR_CTL" , 0x1180010001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX1_RX003_ADR_CTL" , 0x1180010001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_RX003_DECISION" , 0x1180008001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX1_RX000_DECISION" , 0x1180010000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX1_RX001_DECISION" , 0x1180010000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX1_RX002_DECISION" , 0x1180010001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX1_RX003_DECISION" , 0x1180010001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_RX003_FRM_CHK" , 0x1180008001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX1_RX000_FRM_CHK" , 0x1180010000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX1_RX001_FRM_CHK" , 0x1180010000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX1_RX002_FRM_CHK" , 0x1180010001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX1_RX003_FRM_CHK" , 0x1180010001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_RX003_FRM_CTL" , 0x1180008001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX1_RX000_FRM_CTL" , 0x1180010000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX1_RX001_FRM_CTL" , 0x1180010000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX1_RX002_FRM_CTL" , 0x1180010001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX1_RX003_FRM_CTL" , 0x1180010001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_RX003_IFG" , 0x1180008001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX1_RX000_IFG" , 0x1180010000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX1_RX001_IFG" , 0x1180010000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX1_RX002_IFG" , 0x1180010001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX1_RX003_IFG" , 0x1180010001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_RX003_INT_EN" , 0x1180008001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX1_RX000_INT_EN" , 0x1180010000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX1_RX001_INT_EN" , 0x1180010000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX1_RX002_INT_EN" , 0x1180010001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX1_RX003_INT_EN" , 0x1180010001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_RX003_INT_REG" , 0x1180008001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX1_RX000_INT_REG" , 0x1180010000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX1_RX001_INT_REG" , 0x1180010000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX1_RX002_INT_REG" , 0x1180010001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX1_RX003_INT_REG" , 0x1180010001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_RX003_JABBER" , 0x1180008001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX1_RX000_JABBER" , 0x1180010000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX1_RX001_JABBER" , 0x1180010000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX1_RX002_JABBER" , 0x1180010001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX1_RX003_JABBER" , 0x1180010001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_RX000_PAUSE_DROP_TIME" , 0x1180008000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_RX001_PAUSE_DROP_TIME" , 0x1180008000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_RX002_PAUSE_DROP_TIME" , 0x1180008001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_RX003_PAUSE_DROP_TIME" , 0x1180008001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX1_RX000_PAUSE_DROP_TIME" , 0x1180010000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX1_RX001_PAUSE_DROP_TIME" , 0x1180010000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX1_RX002_PAUSE_DROP_TIME" , 0x1180010001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX1_RX003_PAUSE_DROP_TIME" , 0x1180010001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX0_RX003_STATS_CTL" , 0x1180008001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX1_RX000_STATS_CTL" , 0x1180010000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX1_RX001_STATS_CTL" , 0x1180010000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX1_RX002_STATS_CTL" , 0x1180010001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX1_RX003_STATS_CTL" , 0x1180010001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX0_RX003_STATS_OCTS" , 0x1180008001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX1_RX000_STATS_OCTS" , 0x1180010000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX1_RX001_STATS_OCTS" , 0x1180010000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX1_RX002_STATS_OCTS" , 0x1180010001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX1_RX003_STATS_OCTS" , 0x1180010001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX0_RX003_STATS_OCTS_CTL" , 0x1180008001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX1_RX000_STATS_OCTS_CTL" , 0x1180010000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX1_RX001_STATS_OCTS_CTL" , 0x1180010000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX1_RX002_STATS_OCTS_CTL" , 0x1180010001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX1_RX003_STATS_OCTS_CTL" , 0x1180010001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX0_RX003_STATS_OCTS_DMAC" , 0x11800080018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX1_RX000_STATS_OCTS_DMAC" , 0x11800100000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX1_RX001_STATS_OCTS_DMAC" , 0x11800100008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX1_RX002_STATS_OCTS_DMAC" , 0x11800100010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX1_RX003_STATS_OCTS_DMAC" , 0x11800100018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX0_RX003_STATS_OCTS_DRP" , 0x11800080018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX1_RX000_STATS_OCTS_DRP" , 0x11800100000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX1_RX001_STATS_OCTS_DRP" , 0x11800100008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX1_RX002_STATS_OCTS_DRP" , 0x11800100010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX1_RX003_STATS_OCTS_DRP" , 0x11800100018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX0_RX003_STATS_PKTS" , 0x1180008001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX1_RX000_STATS_PKTS" , 0x1180010000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX1_RX001_STATS_PKTS" , 0x1180010000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX1_RX002_STATS_PKTS" , 0x1180010001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX1_RX003_STATS_PKTS" , 0x1180010001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX0_RX003_STATS_PKTS_BAD" , 0x11800080018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX1_RX000_STATS_PKTS_BAD" , 0x11800100000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX1_RX001_STATS_PKTS_BAD" , 0x11800100008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX1_RX002_STATS_PKTS_BAD" , 0x11800100010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX1_RX003_STATS_PKTS_BAD" , 0x11800100018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX0_RX003_STATS_PKTS_CTL" , 0x1180008001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX1_RX000_STATS_PKTS_CTL" , 0x1180010000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX1_RX001_STATS_PKTS_CTL" , 0x1180010000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX1_RX002_STATS_PKTS_CTL" , 0x1180010001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX1_RX003_STATS_PKTS_CTL" , 0x1180010001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX0_RX003_STATS_PKTS_DMAC" , 0x11800080018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX1_RX000_STATS_PKTS_DMAC" , 0x11800100000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX1_RX001_STATS_PKTS_DMAC" , 0x11800100008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX1_RX002_STATS_PKTS_DMAC" , 0x11800100010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX1_RX003_STATS_PKTS_DMAC" , 0x11800100018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX0_RX003_STATS_PKTS_DRP" , 0x11800080018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX1_RX000_STATS_PKTS_DRP" , 0x11800100000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX1_RX001_STATS_PKTS_DRP" , 0x11800100008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX1_RX002_STATS_PKTS_DRP" , 0x11800100010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX1_RX003_STATS_PKTS_DRP" , 0x11800100018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX0_RX003_UDD_SKP" , 0x1180008001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX1_RX000_UDD_SKP" , 0x1180010000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX1_RX001_UDD_SKP" , 0x1180010000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX1_RX002_UDD_SKP" , 0x1180010001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX1_RX003_UDD_SKP" , 0x1180010001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX0_RX_BP_DROP003" , 0x1180008000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX1_RX_BP_DROP000" , 0x1180010000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX1_RX_BP_DROP001" , 0x1180010000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX1_RX_BP_DROP002" , 0x1180010000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX1_RX_BP_DROP003" , 0x1180010000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX0_RX_BP_OFF003" , 0x1180008000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX1_RX_BP_OFF000" , 0x1180010000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX1_RX_BP_OFF001" , 0x1180010000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX1_RX_BP_OFF002" , 0x1180010000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX1_RX_BP_OFF003" , 0x1180010000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX0_RX_BP_ON003" , 0x1180008000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX1_RX_BP_ON000" , 0x1180010000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX1_RX_BP_ON001" , 0x1180010000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX1_RX_BP_ON002" , 0x1180010000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX1_RX_BP_ON003" , 0x1180010000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX0_RX_HG2_STATUS" , 0x1180008000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
|
|
{"GMX1_RX_HG2_STATUS" , 0x1180010000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
|
|
{"GMX0_RX_PRT_INFO" , 0x11800080004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX1_RX_PRT_INFO" , 0x11800100004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
|
|
{"GMX1_RX_PRTS" , 0x1180010000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
|
|
{"GMX0_RX_XAUI_BAD_COL" , 0x1180008000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
|
|
{"GMX1_RX_XAUI_BAD_COL" , 0x1180010000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
|
|
{"GMX0_RX_XAUI_CTL" , 0x1180008000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
|
|
{"GMX1_RX_XAUI_CTL" , 0x1180010000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
|
|
{"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
|
|
{"GMX0_SMAC001" , 0x1180008000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
|
|
{"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
|
|
{"GMX0_SMAC003" , 0x1180008001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
|
|
{"GMX1_SMAC000" , 0x1180010000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
|
|
{"GMX1_SMAC001" , 0x1180010000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
|
|
{"GMX1_SMAC002" , 0x1180010001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
|
|
{"GMX1_SMAC003" , 0x1180010001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
|
|
{"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
|
|
{"GMX1_STAT_BP" , 0x1180010000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
|
|
{"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX0_TX001_APPEND" , 0x1180008000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX0_TX003_APPEND" , 0x1180008001A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX1_TX000_APPEND" , 0x1180010000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX1_TX001_APPEND" , 0x1180010000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX1_TX002_APPEND" , 0x1180010001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX1_TX003_APPEND" , 0x1180010001A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX0_TX001_BURST" , 0x1180008000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX0_TX003_BURST" , 0x1180008001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX1_TX000_BURST" , 0x1180010000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX1_TX001_BURST" , 0x1180010000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX1_TX002_BURST" , 0x1180010001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX1_TX003_BURST" , 0x1180010001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX0_TX000_CBFC_XOFF" , 0x11800080005A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX1_TX000_CBFC_XOFF" , 0x11800100005A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX000_CBFC_XON" , 0x11800080005C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
|
|
{"GMX1_TX000_CBFC_XON" , 0x11800100005C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
|
|
{"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"GMX0_TX001_CTL" , 0x1180008000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"GMX0_TX003_CTL" , 0x1180008001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"GMX1_TX000_CTL" , 0x1180010000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"GMX1_TX001_CTL" , 0x1180010000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"GMX1_TX002_CTL" , 0x1180010001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"GMX1_TX003_CTL" , 0x1180010001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"GMX0_TX001_MIN_PKT" , 0x1180008000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"GMX0_TX003_MIN_PKT" , 0x1180008001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"GMX1_TX000_MIN_PKT" , 0x1180010000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"GMX1_TX001_MIN_PKT" , 0x1180010000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"GMX1_TX002_MIN_PKT" , 0x1180010001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"GMX1_TX003_MIN_PKT" , 0x1180010001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"GMX0_TX003_PAUSE_PKT_INTERVAL", 0x1180008001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"GMX1_TX000_PAUSE_PKT_INTERVAL", 0x1180010000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"GMX1_TX001_PAUSE_PKT_INTERVAL", 0x1180010000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"GMX1_TX002_PAUSE_PKT_INTERVAL", 0x1180010001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"GMX1_TX003_PAUSE_PKT_INTERVAL", 0x1180010001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"GMX0_TX003_PAUSE_PKT_TIME" , 0x1180008001A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"GMX1_TX000_PAUSE_PKT_TIME" , 0x1180010000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"GMX1_TX001_PAUSE_PKT_TIME" , 0x1180010000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"GMX1_TX002_PAUSE_PKT_TIME" , 0x1180010001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"GMX1_TX003_PAUSE_PKT_TIME" , 0x1180010001A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"GMX0_TX001_PAUSE_TOGO" , 0x1180008000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"GMX0_TX003_PAUSE_TOGO" , 0x1180008001A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"GMX1_TX000_PAUSE_TOGO" , 0x1180010000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"GMX1_TX001_PAUSE_TOGO" , 0x1180010000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"GMX1_TX002_PAUSE_TOGO" , 0x1180010001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"GMX1_TX003_PAUSE_TOGO" , 0x1180010001A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"GMX0_TX001_PAUSE_ZERO" , 0x1180008000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"GMX0_TX003_PAUSE_ZERO" , 0x1180008001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"GMX1_TX000_PAUSE_ZERO" , 0x1180010000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"GMX1_TX001_PAUSE_ZERO" , 0x1180010000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"GMX1_TX002_PAUSE_ZERO" , 0x1180010001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"GMX1_TX003_PAUSE_ZERO" , 0x1180010001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"GMX0_TX000_SGMII_CTL" , 0x1180008000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"GMX0_TX001_SGMII_CTL" , 0x1180008000B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"GMX0_TX002_SGMII_CTL" , 0x1180008001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"GMX0_TX003_SGMII_CTL" , 0x1180008001B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"GMX1_TX000_SGMII_CTL" , 0x1180010000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"GMX1_TX001_SGMII_CTL" , 0x1180010000B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"GMX1_TX002_SGMII_CTL" , 0x1180010001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"GMX1_TX003_SGMII_CTL" , 0x1180010001B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"GMX0_TX001_SLOT" , 0x1180008000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"GMX0_TX003_SLOT" , 0x1180008001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"GMX1_TX000_SLOT" , 0x1180010000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"GMX1_TX001_SLOT" , 0x1180010000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"GMX1_TX002_SLOT" , 0x1180010001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"GMX1_TX003_SLOT" , 0x1180010001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
|
|
{"GMX0_TX001_SOFT_PAUSE" , 0x1180008000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
|
|
{"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
|
|
{"GMX0_TX003_SOFT_PAUSE" , 0x1180008001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
|
|
{"GMX1_TX000_SOFT_PAUSE" , 0x1180010000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
|
|
{"GMX1_TX001_SOFT_PAUSE" , 0x1180010000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
|
|
{"GMX1_TX002_SOFT_PAUSE" , 0x1180010001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
|
|
{"GMX1_TX003_SOFT_PAUSE" , 0x1180010001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
|
|
{"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
|
|
{"GMX0_TX001_STAT0" , 0x1180008000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
|
|
{"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
|
|
{"GMX0_TX003_STAT0" , 0x1180008001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
|
|
{"GMX1_TX000_STAT0" , 0x1180010000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
|
|
{"GMX1_TX001_STAT0" , 0x1180010000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
|
|
{"GMX1_TX002_STAT0" , 0x1180010001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
|
|
{"GMX1_TX003_STAT0" , 0x1180010001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
|
|
{"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
|
|
{"GMX0_TX001_STAT1" , 0x1180008000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
|
|
{"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
|
|
{"GMX0_TX003_STAT1" , 0x1180008001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
|
|
{"GMX1_TX000_STAT1" , 0x1180010000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
|
|
{"GMX1_TX001_STAT1" , 0x1180010000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
|
|
{"GMX1_TX002_STAT1" , 0x1180010001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
|
|
{"GMX1_TX003_STAT1" , 0x1180010001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
|
|
{"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
|
|
{"GMX0_TX001_STAT2" , 0x1180008000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
|
|
{"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
|
|
{"GMX0_TX003_STAT2" , 0x1180008001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
|
|
{"GMX1_TX000_STAT2" , 0x1180010000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
|
|
{"GMX1_TX001_STAT2" , 0x1180010000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
|
|
{"GMX1_TX002_STAT2" , 0x1180010001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
|
|
{"GMX1_TX003_STAT2" , 0x1180010001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
|
|
{"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
|
|
{"GMX0_TX001_STAT3" , 0x1180008000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
|
|
{"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
|
|
{"GMX0_TX003_STAT3" , 0x1180008001A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
|
|
{"GMX1_TX000_STAT3" , 0x1180010000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
|
|
{"GMX1_TX001_STAT3" , 0x1180010000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
|
|
{"GMX1_TX002_STAT3" , 0x1180010001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
|
|
{"GMX1_TX003_STAT3" , 0x1180010001A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
|
|
{"GMX0_TX000_STAT4" , 0x11800080002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
|
|
{"GMX0_TX001_STAT4" , 0x1180008000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
|
|
{"GMX0_TX002_STAT4" , 0x11800080012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
|
|
{"GMX0_TX003_STAT4" , 0x1180008001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
|
|
{"GMX1_TX000_STAT4" , 0x11800100002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
|
|
{"GMX1_TX001_STAT4" , 0x1180010000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
|
|
{"GMX1_TX002_STAT4" , 0x11800100012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
|
|
{"GMX1_TX003_STAT4" , 0x1180010001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
|
|
{"GMX0_TX000_STAT5" , 0x11800080002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
|
|
{"GMX0_TX001_STAT5" , 0x1180008000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
|
|
{"GMX0_TX002_STAT5" , 0x11800080012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
|
|
{"GMX0_TX003_STAT5" , 0x1180008001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
|
|
{"GMX1_TX000_STAT5" , 0x11800100002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
|
|
{"GMX1_TX001_STAT5" , 0x1180010000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
|
|
{"GMX1_TX002_STAT5" , 0x11800100012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
|
|
{"GMX1_TX003_STAT5" , 0x1180010001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
|
|
{"GMX0_TX000_STAT6" , 0x11800080002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
|
|
{"GMX0_TX001_STAT6" , 0x1180008000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
|
|
{"GMX0_TX002_STAT6" , 0x11800080012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
|
|
{"GMX0_TX003_STAT6" , 0x1180008001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
|
|
{"GMX1_TX000_STAT6" , 0x11800100002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
|
|
{"GMX1_TX001_STAT6" , 0x1180010000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
|
|
{"GMX1_TX002_STAT6" , 0x11800100012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
|
|
{"GMX1_TX003_STAT6" , 0x1180010001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
|
|
{"GMX0_TX000_STAT7" , 0x11800080002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
|
|
{"GMX0_TX001_STAT7" , 0x1180008000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
|
|
{"GMX0_TX002_STAT7" , 0x11800080012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
|
|
{"GMX0_TX003_STAT7" , 0x1180008001AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
|
|
{"GMX1_TX000_STAT7" , 0x11800100002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
|
|
{"GMX1_TX001_STAT7" , 0x1180010000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
|
|
{"GMX1_TX002_STAT7" , 0x11800100012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
|
|
{"GMX1_TX003_STAT7" , 0x1180010001AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
|
|
{"GMX0_TX000_STAT8" , 0x11800080002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
|
|
{"GMX0_TX001_STAT8" , 0x1180008000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
|
|
{"GMX0_TX002_STAT8" , 0x11800080012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
|
|
{"GMX0_TX003_STAT8" , 0x1180008001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
|
|
{"GMX1_TX000_STAT8" , 0x11800100002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
|
|
{"GMX1_TX001_STAT8" , 0x1180010000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
|
|
{"GMX1_TX002_STAT8" , 0x11800100012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
|
|
{"GMX1_TX003_STAT8" , 0x1180010001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
|
|
{"GMX0_TX000_STAT9" , 0x11800080002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
|
|
{"GMX0_TX001_STAT9" , 0x1180008000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
|
|
{"GMX0_TX002_STAT9" , 0x11800080012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
|
|
{"GMX0_TX003_STAT9" , 0x1180008001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
|
|
{"GMX1_TX000_STAT9" , 0x11800100002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
|
|
{"GMX1_TX001_STAT9" , 0x1180010000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
|
|
{"GMX1_TX002_STAT9" , 0x11800100012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
|
|
{"GMX1_TX003_STAT9" , 0x1180010001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
|
|
{"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
|
|
{"GMX0_TX001_STATS_CTL" , 0x1180008000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
|
|
{"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
|
|
{"GMX0_TX003_STATS_CTL" , 0x1180008001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
|
|
{"GMX1_TX000_STATS_CTL" , 0x1180010000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
|
|
{"GMX1_TX001_STATS_CTL" , 0x1180010000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
|
|
{"GMX1_TX002_STATS_CTL" , 0x1180010001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
|
|
{"GMX1_TX003_STATS_CTL" , 0x1180010001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
|
|
{"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
|
|
{"GMX0_TX001_THRESH" , 0x1180008000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
|
|
{"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
|
|
{"GMX0_TX003_THRESH" , 0x1180008001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
|
|
{"GMX1_TX000_THRESH" , 0x1180010000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
|
|
{"GMX1_TX001_THRESH" , 0x1180010000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
|
|
{"GMX1_TX002_THRESH" , 0x1180010001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
|
|
{"GMX1_TX003_THRESH" , 0x1180010001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
|
|
{"GMX0_TX_BP" , 0x11800080004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
|
|
{"GMX1_TX_BP" , 0x11800100004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
|
|
{"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 191},
|
|
{"GMX1_TX_COL_ATTEMPT" , 0x1180010000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 191},
|
|
{"GMX0_TX_CORRUPT" , 0x11800080004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 192},
|
|
{"GMX1_TX_CORRUPT" , 0x11800100004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 192},
|
|
{"GMX0_TX_HG2_REG1" , 0x1180008000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 193},
|
|
{"GMX1_TX_HG2_REG1" , 0x1180010000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 193},
|
|
{"GMX0_TX_HG2_REG2" , 0x1180008000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 194},
|
|
{"GMX1_TX_HG2_REG2" , 0x1180010000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 194},
|
|
{"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 195},
|
|
{"GMX1_TX_IFG" , 0x1180010000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 195},
|
|
{"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
|
|
{"GMX1_TX_INT_EN" , 0x1180010000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
|
|
{"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
|
|
{"GMX1_TX_INT_REG" , 0x1180010000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
|
|
{"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
|
|
{"GMX1_TX_JAM" , 0x1180010000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
|
|
{"GMX0_TX_LFSR" , 0x11800080004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
|
|
{"GMX1_TX_LFSR" , 0x11800100004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
|
|
{"GMX0_TX_OVR_BP" , 0x11800080004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
|
|
{"GMX1_TX_OVR_BP" , 0x11800100004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
|
|
{"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
|
|
{"GMX1_TX_PAUSE_PKT_DMAC" , 0x11800100004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
|
|
{"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
|
|
{"GMX1_TX_PAUSE_PKT_TYPE" , 0x11800100004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
|
|
{"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
|
|
{"GMX1_TX_PRTS" , 0x1180010000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
|
|
{"GMX0_TX_XAUI_CTL" , 0x1180008000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
|
|
{"GMX1_TX_XAUI_CTL" , 0x1180010000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
|
|
{"GMX0_XAUI_EXT_LOOPBACK" , 0x1180008000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 205},
|
|
{"GMX1_XAUI_EXT_LOOPBACK" , 0x1180010000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 205},
|
|
{"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"GPIO_CLK_GEN0" , 0x10700000008C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
|
|
{"GPIO_CLK_GEN1" , 0x10700000008C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
|
|
{"GPIO_CLK_GEN2" , 0x10700000008D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
|
|
{"GPIO_CLK_GEN3" , 0x10700000008D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
|
|
{"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 208},
|
|
{"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 209},
|
|
{"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 210},
|
|
{"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 211},
|
|
{"IOB_BIST_STATUS" , 0x11800F00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
|
|
{"IOB_CTL_STATUS" , 0x11800F0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
|
|
{"IOB_DWB_PRI_CNT" , 0x11800F0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
|
|
{"IOB_FAU_TIMEOUT" , 0x11800F0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
|
|
{"IOB_I2C_PRI_CNT" , 0x11800F0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
|
|
{"IOB_INB_CONTROL_MATCH" , 0x11800F0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
|
|
{"IOB_INB_CONTROL_MATCH_ENB" , 0x11800F0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
|
|
{"IOB_INB_DATA_MATCH" , 0x11800F0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
|
|
{"IOB_INB_DATA_MATCH_ENB" , 0x11800F0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
|
|
{"IOB_INT_ENB" , 0x11800F0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
|
|
{"IOB_INT_SUM" , 0x11800F0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
|
|
{"IOB_N2C_L2C_PRI_CNT" , 0x11800F0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
|
|
{"IOB_N2C_RSP_PRI_CNT" , 0x11800F0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
|
|
{"IOB_OUTB_COM_PRI_CNT" , 0x11800F0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
|
|
{"IOB_OUTB_CONTROL_MATCH" , 0x11800F0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
|
|
{"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800F00000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
|
|
{"IOB_OUTB_DATA_MATCH" , 0x11800F0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
|
|
{"IOB_OUTB_DATA_MATCH_ENB" , 0x11800F00000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
|
|
{"IOB_OUTB_FPA_PRI_CNT" , 0x11800F0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
|
|
{"IOB_OUTB_REQ_PRI_CNT" , 0x11800F0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
|
|
{"IOB_P2C_REQ_PRI_CNT" , 0x11800F0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
|
|
{"IOB_PKT_ERR" , 0x11800F0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
|
|
{"IPD_1ST_MBUFF_SKIP" , 0x14F0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
|
|
{"IPD_1ST_NEXT_PTR_BACK" , 0x14F0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_2ND_NEXT_PTR_BACK" , 0x14F0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
|
|
{"IPD_BIST_STATUS" , 0x14F00000007F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
|
|
{"IPD_BP_PRT_RED_END" , 0x14F0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
|
|
{"IPD_CLK_COUNT" , 0x14F0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
|
|
{"IPD_CTL_STATUS" , 0x14F0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
|
|
{"IPD_INT_ENB" , 0x14F0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
|
|
{"IPD_INT_SUM" , 0x14F0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
|
|
{"IPD_NOT_1ST_MBUFF_SKIP" , 0x14F0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
|
|
{"IPD_PACKET_MBUFF_SIZE" , 0x14F0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
|
|
{"IPD_PKT_PTR_VALID" , 0x14F0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
|
|
{"IPD_PORT0_BP_PAGE_CNT" , 0x14F0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_PORT1_BP_PAGE_CNT" , 0x14F0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_PORT2_BP_PAGE_CNT" , 0x14F0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_PORT3_BP_PAGE_CNT" , 0x14F0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_PORT16_BP_PAGE_CNT" , 0x14F00000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_PORT17_BP_PAGE_CNT" , 0x14F00000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_PORT18_BP_PAGE_CNT" , 0x14F00000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_PORT19_BP_PAGE_CNT" , 0x14F00000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_PORT32_BP_PAGE_CNT" , 0x14F0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_PORT33_BP_PAGE_CNT" , 0x14F0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_PORT34_BP_PAGE_CNT" , 0x14F0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_PORT35_BP_PAGE_CNT" , 0x14F0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_PORT36_BP_PAGE_CNT2" , 0x14F0000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT37_BP_PAGE_CNT2" , 0x14F0000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT38_BP_PAGE_CNT2" , 0x14F0000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT39_BP_PAGE_CNT2" , 0x14F0000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_BP_COUNTERS2_PAIR36", 0x14F0000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
|
|
{"IPD_PORT_BP_COUNTERS2_PAIR37", 0x14F0000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
|
|
{"IPD_PORT_BP_COUNTERS2_PAIR38", 0x14F0000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
|
|
{"IPD_PORT_BP_COUNTERS2_PAIR39", 0x14F00000003A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14F00000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14F00000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14F00000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR3" , 0x14F00000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR16" , 0x14F0000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR17" , 0x14F0000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR18" , 0x14F0000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR19" , 0x14F0000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14F00000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR33" , 0x14F00000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR34" , 0x14F00000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR35" , 0x14F00000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
|
|
{"IPD_PORT_QOS_0_CNT" , 0x14F0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_1_CNT" , 0x14F0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_2_CNT" , 0x14F0000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_3_CNT" , 0x14F00000008A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_4_CNT" , 0x14F00000008A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_5_CNT" , 0x14F00000008B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_6_CNT" , 0x14F00000008B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_7_CNT" , 0x14F00000008C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_8_CNT" , 0x14F00000008C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_9_CNT" , 0x14F00000008D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_10_CNT" , 0x14F00000008D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_11_CNT" , 0x14F00000008E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_12_CNT" , 0x14F00000008E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_13_CNT" , 0x14F00000008F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_14_CNT" , 0x14F00000008F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_15_CNT" , 0x14F0000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_16_CNT" , 0x14F0000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_17_CNT" , 0x14F0000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_18_CNT" , 0x14F0000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_19_CNT" , 0x14F0000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_20_CNT" , 0x14F0000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_21_CNT" , 0x14F0000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_22_CNT" , 0x14F0000000938ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_23_CNT" , 0x14F0000000940ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_24_CNT" , 0x14F0000000948ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_25_CNT" , 0x14F0000000950ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_26_CNT" , 0x14F0000000958ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_27_CNT" , 0x14F0000000960ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_28_CNT" , 0x14F0000000968ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_29_CNT" , 0x14F0000000970ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_30_CNT" , 0x14F0000000978ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_31_CNT" , 0x14F0000000980ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_128_CNT" , 0x14F0000000C88ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_129_CNT" , 0x14F0000000C90ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_130_CNT" , 0x14F0000000C98ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_131_CNT" , 0x14F0000000CA0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_132_CNT" , 0x14F0000000CA8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_133_CNT" , 0x14F0000000CB0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_134_CNT" , 0x14F0000000CB8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_135_CNT" , 0x14F0000000CC0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_136_CNT" , 0x14F0000000CC8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_137_CNT" , 0x14F0000000CD0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_138_CNT" , 0x14F0000000CD8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_139_CNT" , 0x14F0000000CE0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_140_CNT" , 0x14F0000000CE8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_141_CNT" , 0x14F0000000CF0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_142_CNT" , 0x14F0000000CF8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_143_CNT" , 0x14F0000000D00ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_144_CNT" , 0x14F0000000D08ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_145_CNT" , 0x14F0000000D10ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_146_CNT" , 0x14F0000000D18ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_147_CNT" , 0x14F0000000D20ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_148_CNT" , 0x14F0000000D28ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_149_CNT" , 0x14F0000000D30ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_150_CNT" , 0x14F0000000D38ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_151_CNT" , 0x14F0000000D40ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_152_CNT" , 0x14F0000000D48ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_153_CNT" , 0x14F0000000D50ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_154_CNT" , 0x14F0000000D58ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_155_CNT" , 0x14F0000000D60ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_156_CNT" , 0x14F0000000D68ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_157_CNT" , 0x14F0000000D70ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_158_CNT" , 0x14F0000000D78ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_159_CNT" , 0x14F0000000D80ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_256_CNT" , 0x14F0000001088ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_257_CNT" , 0x14F0000001090ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_258_CNT" , 0x14F0000001098ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_259_CNT" , 0x14F00000010A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_260_CNT" , 0x14F00000010A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_261_CNT" , 0x14F00000010B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_262_CNT" , 0x14F00000010B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_263_CNT" , 0x14F00000010C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_264_CNT" , 0x14F00000010C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_265_CNT" , 0x14F00000010D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_266_CNT" , 0x14F00000010D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_267_CNT" , 0x14F00000010E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_268_CNT" , 0x14F00000010E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_269_CNT" , 0x14F00000010F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_270_CNT" , 0x14F00000010F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_271_CNT" , 0x14F0000001100ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_272_CNT" , 0x14F0000001108ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_273_CNT" , 0x14F0000001110ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_274_CNT" , 0x14F0000001118ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_275_CNT" , 0x14F0000001120ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_276_CNT" , 0x14F0000001128ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_277_CNT" , 0x14F0000001130ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_278_CNT" , 0x14F0000001138ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_279_CNT" , 0x14F0000001140ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_280_CNT" , 0x14F0000001148ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_281_CNT" , 0x14F0000001150ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_282_CNT" , 0x14F0000001158ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_283_CNT" , 0x14F0000001160ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_284_CNT" , 0x14F0000001168ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_285_CNT" , 0x14F0000001170ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_286_CNT" , 0x14F0000001178ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_287_CNT" , 0x14F0000001180ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_288_CNT" , 0x14F0000001188ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_289_CNT" , 0x14F0000001190ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_290_CNT" , 0x14F0000001198ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_291_CNT" , 0x14F00000011A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_292_CNT" , 0x14F00000011A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_293_CNT" , 0x14F00000011B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_294_CNT" , 0x14F00000011B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_295_CNT" , 0x14F00000011C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_296_CNT" , 0x14F00000011C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_297_CNT" , 0x14F00000011D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_298_CNT" , 0x14F00000011D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_299_CNT" , 0x14F00000011E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_300_CNT" , 0x14F00000011E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_301_CNT" , 0x14F00000011F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_302_CNT" , 0x14F00000011F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_303_CNT" , 0x14F0000001200ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_304_CNT" , 0x14F0000001208ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_305_CNT" , 0x14F0000001210ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_306_CNT" , 0x14F0000001218ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_307_CNT" , 0x14F0000001220ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_308_CNT" , 0x14F0000001228ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_309_CNT" , 0x14F0000001230ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_310_CNT" , 0x14F0000001238ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_311_CNT" , 0x14F0000001240ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_312_CNT" , 0x14F0000001248ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_313_CNT" , 0x14F0000001250ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_314_CNT" , 0x14F0000001258ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_315_CNT" , 0x14F0000001260ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_316_CNT" , 0x14F0000001268ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_317_CNT" , 0x14F0000001270ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_318_CNT" , 0x14F0000001278ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_319_CNT" , 0x14F0000001280ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PORT_QOS_INT0" , 0x14F0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
|
|
{"IPD_PORT_QOS_INT2" , 0x14F0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
|
|
{"IPD_PORT_QOS_INT4" , 0x14F0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
|
|
{"IPD_PORT_QOS_INT_ENB0" , 0x14F0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
|
|
{"IPD_PORT_QOS_INT_ENB2" , 0x14F0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
|
|
{"IPD_PORT_QOS_INT_ENB4" , 0x14F0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
|
|
{"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14F0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
|
|
{"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14F0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
|
|
{"IPD_PTR_COUNT" , 0x14F0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
|
|
{"IPD_PWP_PTR_FIFO_CTL" , 0x14F0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
|
|
{"IPD_QOS0_RED_MARKS" , 0x14F0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
|
|
{"IPD_QOS1_RED_MARKS" , 0x14F0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
|
|
{"IPD_QOS2_RED_MARKS" , 0x14F0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
|
|
{"IPD_QOS3_RED_MARKS" , 0x14F0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
|
|
{"IPD_QOS4_RED_MARKS" , 0x14F0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
|
|
{"IPD_QOS5_RED_MARKS" , 0x14F00000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
|
|
{"IPD_QOS6_RED_MARKS" , 0x14F00000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
|
|
{"IPD_QOS7_RED_MARKS" , 0x14F00000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
|
|
{"IPD_QUE0_FREE_PAGE_CNT" , 0x14F0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
|
|
{"IPD_RED_PORT_ENABLE" , 0x14F00000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
|
|
{"IPD_RED_PORT_ENABLE2" , 0x14F00000003A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
|
|
{"IPD_RED_QUE0_PARAM" , 0x14F00000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 261},
|
|
{"IPD_RED_QUE1_PARAM" , 0x14F00000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 261},
|
|
{"IPD_RED_QUE2_PARAM" , 0x14F00000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 261},
|
|
{"IPD_RED_QUE3_PARAM" , 0x14F00000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 261},
|
|
{"IPD_RED_QUE4_PARAM" , 0x14F0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 261},
|
|
{"IPD_RED_QUE5_PARAM" , 0x14F0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 261},
|
|
{"IPD_RED_QUE6_PARAM" , 0x14F0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 261},
|
|
{"IPD_RED_QUE7_PARAM" , 0x14F0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 261},
|
|
{"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14F0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
|
|
{"IPD_SUB_PORT_FCS" , 0x14F0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
|
|
{"IPD_SUB_PORT_QOS_CNT" , 0x14F0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 264},
|
|
{"IPD_WQE_FPA_QUEUE" , 0x14F0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 265},
|
|
{"IPD_WQE_PTR_VALID" , 0x14F0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 266},
|
|
{"KEY_BIST_REG" , 0x1180020000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
|
|
{"KEY_CTL_STATUS" , 0x1180020000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
|
|
{"KEY_INT_ENB" , 0x1180020000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
|
|
{"KEY_INT_SUM" , 0x1180020000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
|
|
{"L2C_BST0" , 0x11800800007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
|
|
{"L2C_BST1" , 0x11800800007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
|
|
{"L2C_BST2" , 0x11800800007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
|
|
{"L2C_CFG" , 0x1180080000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
|
|
{"L2C_DBG" , 0x1180080000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
|
|
{"L2C_DUT" , 0x1180080000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
|
|
{"L2C_GRPWRR0" , 0x11800800000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
|
|
{"L2C_GRPWRR1" , 0x11800800000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
|
|
{"L2C_INT_EN" , 0x1180080000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
|
|
{"L2C_INT_STAT" , 0x11800800000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
|
|
{"L2C_LCKBASE" , 0x1180080000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
|
|
{"L2C_LCKOFF" , 0x1180080000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
|
|
{"L2C_LFB0" , 0x1180080000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
|
|
{"L2C_LFB1" , 0x1180080000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
|
|
{"L2C_LFB2" , 0x1180080000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
|
|
{"L2C_LFB3" , 0x11800800000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
|
|
{"L2C_OOB" , 0x11800800000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
|
|
{"L2C_OOB1" , 0x11800800000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
|
|
{"L2C_OOB2" , 0x11800800000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 289},
|
|
{"L2C_OOB3" , 0x11800800000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
|
|
{"L2C_PFC0" , 0x1180080000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
|
|
{"L2C_PFC1" , 0x11800800000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
|
|
{"L2C_PFC2" , 0x11800800000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
|
|
{"L2C_PFC3" , 0x11800800000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
|
|
{"L2C_PFCTL" , 0x1180080000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
|
|
{"L2C_PPGRP" , 0x11800800000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
|
|
{"L2C_SPAR0" , 0x1180080000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
|
|
{"L2C_SPAR1" , 0x1180080000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
|
|
{"L2C_SPAR2" , 0x1180080000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
|
|
{"L2C_SPAR4" , 0x1180080000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
|
|
{"L2D_BST0" , 0x1180080000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
|
|
{"L2D_BST1" , 0x1180080000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
|
|
{"L2D_BST2" , 0x1180080000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
|
|
{"L2D_BST3" , 0x1180080000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
|
|
{"L2D_ERR" , 0x1180080000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
|
|
{"L2D_FADR" , 0x1180080000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
|
|
{"L2D_FSYN0" , 0x1180080000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
|
|
{"L2D_FSYN1" , 0x1180080000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
|
|
{"L2D_FUS0" , 0x11800800007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
|
|
{"L2D_FUS1" , 0x11800800007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
|
|
{"L2D_FUS2" , 0x11800800007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
|
|
{"L2D_FUS3" , 0x11800800007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
|
|
{"L2T_ERR" , 0x1180080000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
|
|
{"LED_BLINK" , 0x1180000001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
|
|
{"LED_CLK_PHASE" , 0x1180000001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
|
|
{"LED_CYLON" , 0x1180000001AF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
|
|
{"LED_DBG" , 0x1180000001A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
|
|
{"LED_EN" , 0x1180000001A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
|
|
{"LED_POLARITY" , 0x1180000001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
|
|
{"LED_PRT" , 0x1180000001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
|
|
{"LED_PRT_FMT" , 0x1180000001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
|
|
{"LED_PRT_STATUS0" , 0x1180000001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
|
|
{"LED_PRT_STATUS1" , 0x1180000001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
|
|
{"LED_PRT_STATUS2" , 0x1180000001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
|
|
{"LED_PRT_STATUS3" , 0x1180000001A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
|
|
{"LED_PRT_STATUS4" , 0x1180000001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
|
|
{"LED_PRT_STATUS5" , 0x1180000001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
|
|
{"LED_PRT_STATUS6" , 0x1180000001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
|
|
{"LED_PRT_STATUS7" , 0x1180000001AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
|
|
{"LED_UDD_CNT0" , 0x1180000001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
|
|
{"LED_UDD_CNT1" , 0x1180000001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
|
|
{"LED_UDD_DAT0" , 0x1180000001A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
|
|
{"LED_UDD_DAT1" , 0x1180000001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
|
|
{"LED_UDD_DAT_CLR0" , 0x1180000001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
|
|
{"LED_UDD_DAT_CLR1" , 0x1180000001AD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
|
|
{"LED_UDD_DAT_SET0" , 0x1180000001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
|
|
{"LED_UDD_DAT_SET1" , 0x1180000001AD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
|
|
{"LMC0_BIST_CTL" , 0x11800880000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
|
|
{"LMC1_BIST_CTL" , 0x11800E80000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
|
|
{"LMC0_BIST_RESULT" , 0x11800880000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
|
|
{"LMC1_BIST_RESULT" , 0x11800E80000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
|
|
{"LMC0_COMP_CTL" , 0x1180088000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
|
|
{"LMC1_COMP_CTL" , 0x11800E8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
|
|
{"LMC0_CTL" , 0x1180088000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
|
|
{"LMC1_CTL" , 0x11800E8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
|
|
{"LMC0_CTL1" , 0x1180088000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 328},
|
|
{"LMC1_CTL1" , 0x11800E8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 328},
|
|
{"LMC0_DCLK_CNT_HI" , 0x1180088000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
|
|
{"LMC1_DCLK_CNT_HI" , 0x11800E8000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
|
|
{"LMC0_DCLK_CNT_LO" , 0x1180088000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
|
|
{"LMC1_DCLK_CNT_LO" , 0x11800E8000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
|
|
{"LMC0_DCLK_CTL" , 0x11800880000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 331},
|
|
{"LMC1_DCLK_CTL" , 0x11800E80000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 331},
|
|
{"LMC0_DDR2_CTL" , 0x1180088000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
|
|
{"LMC1_DDR2_CTL" , 0x11800E8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
|
|
{"LMC0_DELAY_CFG" , 0x1180088000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
|
|
{"LMC1_DELAY_CFG" , 0x11800E8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
|
|
{"LMC0_DLL_CTL" , 0x11800880000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 334},
|
|
{"LMC1_DLL_CTL" , 0x11800E80000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 334},
|
|
{"LMC0_DUAL_MEMCFG" , 0x1180088000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 335},
|
|
{"LMC1_DUAL_MEMCFG" , 0x11800E8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 335},
|
|
{"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 336},
|
|
{"LMC1_ECC_SYND" , 0x11800E8000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 336},
|
|
{"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 337},
|
|
{"LMC1_FADR" , 0x11800E8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 337},
|
|
{"LMC0_IFB_CNT_HI" , 0x1180088000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 338},
|
|
{"LMC1_IFB_CNT_HI" , 0x11800E8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 338},
|
|
{"LMC0_IFB_CNT_LO" , 0x1180088000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 339},
|
|
{"LMC1_IFB_CNT_LO" , 0x11800E8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 339},
|
|
{"LMC0_MEM_CFG0" , 0x1180088000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 340},
|
|
{"LMC1_MEM_CFG0" , 0x11800E8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 340},
|
|
{"LMC0_MEM_CFG1" , 0x1180088000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 341},
|
|
{"LMC1_MEM_CFG1" , 0x11800E8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 341},
|
|
{"LMC0_NXM" , 0x11800880000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 342},
|
|
{"LMC1_NXM" , 0x11800E80000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 342},
|
|
{"LMC0_OPS_CNT_HI" , 0x1180088000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
|
|
{"LMC1_OPS_CNT_HI" , 0x11800E8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
|
|
{"LMC0_OPS_CNT_LO" , 0x1180088000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
|
|
{"LMC1_OPS_CNT_LO" , 0x11800E8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
|
|
{"LMC0_PLL_CTL" , 0x11800880000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 345},
|
|
{"LMC1_PLL_CTL" , 0x11800E80000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 345},
|
|
{"LMC0_PLL_STATUS" , 0x11800880000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
|
|
{"LMC1_PLL_STATUS" , 0x11800E80000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
|
|
{"LMC0_READ_LEVEL_CTL" , 0x1180088000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
|
|
{"LMC1_READ_LEVEL_CTL" , 0x11800E8000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
|
|
{"LMC0_READ_LEVEL_DBG" , 0x1180088000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 348},
|
|
{"LMC1_READ_LEVEL_DBG" , 0x11800E8000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 348},
|
|
{"LMC0_READ_LEVEL_RANK000" , 0x1180088000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
|
|
{"LMC0_READ_LEVEL_RANK001" , 0x1180088000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
|
|
{"LMC0_READ_LEVEL_RANK002" , 0x1180088000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
|
|
{"LMC0_READ_LEVEL_RANK003" , 0x1180088000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
|
|
{"LMC1_READ_LEVEL_RANK000" , 0x11800E8000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
|
|
{"LMC1_READ_LEVEL_RANK001" , 0x11800E8000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
|
|
{"LMC1_READ_LEVEL_RANK002" , 0x11800E8000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
|
|
{"LMC1_READ_LEVEL_RANK003" , 0x11800E8000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
|
|
{"LMC0_RODT_COMP_CTL" , 0x11800880000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
|
|
{"LMC1_RODT_COMP_CTL" , 0x11800E80000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
|
|
{"LMC0_RODT_CTL" , 0x1180088000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 351},
|
|
{"LMC1_RODT_CTL" , 0x11800E8000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 351},
|
|
{"LMC0_WODT_CTL0" , 0x1180088000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 352},
|
|
{"LMC1_WODT_CTL0" , 0x11800E8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 352},
|
|
{"LMC0_WODT_CTL1" , 0x1180088000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 353},
|
|
{"LMC1_WODT_CTL1" , 0x11800E8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 353},
|
|
{"MIO_BOOT_BIST_STAT" , 0x11800000000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 354},
|
|
{"MIO_BOOT_COMP" , 0x11800000000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 355},
|
|
{"MIO_BOOT_DMA_CFG0" , 0x1180000000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
|
|
{"MIO_BOOT_DMA_CFG1" , 0x1180000000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
|
|
{"MIO_BOOT_DMA_CFG2" , 0x1180000000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
|
|
{"MIO_BOOT_DMA_INT0" , 0x1180000000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
|
|
{"MIO_BOOT_DMA_INT1" , 0x1180000000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
|
|
{"MIO_BOOT_DMA_INT2" , 0x1180000000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
|
|
{"MIO_BOOT_DMA_INT_EN0" , 0x1180000000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
|
|
{"MIO_BOOT_DMA_INT_EN1" , 0x1180000000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
|
|
{"MIO_BOOT_DMA_INT_EN2" , 0x1180000000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
|
|
{"MIO_BOOT_DMA_TIM0" , 0x1180000000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
|
|
{"MIO_BOOT_DMA_TIM1" , 0x1180000000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
|
|
{"MIO_BOOT_DMA_TIM2" , 0x1180000000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
|
|
{"MIO_BOOT_ERR" , 0x11800000000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 360},
|
|
{"MIO_BOOT_INT" , 0x11800000000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 361},
|
|
{"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 362},
|
|
{"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
|
|
{"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
|
|
{"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 364},
|
|
{"MIO_BOOT_PIN_DEFS" , 0x11800000000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
|
|
{"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
|
|
{"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
|
|
{"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
|
|
{"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
|
|
{"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
|
|
{"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
|
|
{"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
|
|
{"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
|
|
{"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
|
|
{"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
|
|
{"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
|
|
{"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
|
|
{"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
|
|
{"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
|
|
{"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
|
|
{"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
|
|
{"MIO_BOOT_THR" , 0x11800000000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
|
|
{"MIO_FUS_BNK_DAT0" , 0x1180000001520ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
|
|
{"MIO_FUS_BNK_DAT1" , 0x1180000001528ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
|
|
{"MIO_FUS_BNK_DAT2" , 0x1180000001530ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
|
|
{"MIO_FUS_BNK_DAT3" , 0x1180000001538ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
|
|
{"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
|
|
{"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
|
|
{"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
|
|
{"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
|
|
{"MIO_FUS_EMA" , 0x1180000001550ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
|
|
{"MIO_FUS_PDF" , 0x1180000001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
|
|
{"MIO_FUS_PLL" , 0x1180000001580ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
|
|
{"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
|
|
{"MIO_FUS_PROG_TIMES" , 0x1180000001518ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
|
|
{"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
|
|
{"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
|
|
{"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
|
|
{"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
|
|
{"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
|
|
{"MIO_TWS1_INT" , 0x1180000001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
|
|
{"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
|
|
{"MIO_TWS1_SW_TWSI" , 0x1180000001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
|
|
{"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
|
|
{"MIO_TWS1_SW_TWSI_EXT" , 0x1180000001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
|
|
{"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
|
|
{"MIO_TWS1_TWSI_SW" , 0x1180000001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
|
|
{"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
|
|
{"MIO_UART1_DLH" , 0x1180000000C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
|
|
{"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
|
|
{"MIO_UART1_DLL" , 0x1180000000C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
|
|
{"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
|
|
{"MIO_UART1_FAR" , 0x1180000000D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
|
|
{"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
|
|
{"MIO_UART1_FCR" , 0x1180000000C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
|
|
{"MIO_UART0_HTX" , 0x1180000000B08ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
|
|
{"MIO_UART1_HTX" , 0x1180000000F08ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
|
|
{"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
|
|
{"MIO_UART1_IER" , 0x1180000000C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
|
|
{"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
|
|
{"MIO_UART1_IIR" , 0x1180000000C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
|
|
{"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
|
|
{"MIO_UART1_LCR" , 0x1180000000C18ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
|
|
{"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
|
|
{"MIO_UART1_LSR" , 0x1180000000C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
|
|
{"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
|
|
{"MIO_UART1_MCR" , 0x1180000000C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
|
|
{"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
|
|
{"MIO_UART1_MSR" , 0x1180000000C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
|
|
{"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
|
|
{"MIO_UART1_RBR" , 0x1180000000C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
|
|
{"MIO_UART0_RFL" , 0x1180000000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
|
|
{"MIO_UART1_RFL" , 0x1180000000E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
|
|
{"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
|
|
{"MIO_UART1_RFW" , 0x1180000000D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
|
|
{"MIO_UART0_SBCR" , 0x1180000000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"MIO_UART1_SBCR" , 0x1180000000E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
|
|
{"MIO_UART1_SCR" , 0x1180000000C38ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
|
|
{"MIO_UART0_SFE" , 0x1180000000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
|
|
{"MIO_UART1_SFE" , 0x1180000000E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
|
|
{"MIO_UART0_SRR" , 0x1180000000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
|
|
{"MIO_UART1_SRR" , 0x1180000000E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
|
|
{"MIO_UART0_SRT" , 0x1180000000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
|
|
{"MIO_UART1_SRT" , 0x1180000000E38ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
|
|
{"MIO_UART0_SRTS" , 0x1180000000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
|
|
{"MIO_UART1_SRTS" , 0x1180000000E18ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
|
|
{"MIO_UART0_STT" , 0x1180000000B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
|
|
{"MIO_UART1_STT" , 0x1180000000F00ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
|
|
{"MIO_UART0_TFL" , 0x1180000000A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
|
|
{"MIO_UART1_TFL" , 0x1180000000E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
|
|
{"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
|
|
{"MIO_UART1_TFR" , 0x1180000000D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
|
|
{"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
|
|
{"MIO_UART1_THR" , 0x1180000000C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
|
|
{"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
|
|
{"MIO_UART1_USR" , 0x1180000000D38ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
|
|
{"MIX0_BIST" , 0x1070000100078ull, CVMX_CSR_DB_TYPE_NCB, 64, 412},
|
|
{"MIX0_CTL" , 0x1070000100020ull, CVMX_CSR_DB_TYPE_NCB, 64, 413},
|
|
{"MIX0_INTENA" , 0x1070000100050ull, CVMX_CSR_DB_TYPE_NCB, 64, 414},
|
|
{"MIX0_IRCNT" , 0x1070000100030ull, CVMX_CSR_DB_TYPE_NCB, 64, 415},
|
|
{"MIX0_IRHWM" , 0x1070000100028ull, CVMX_CSR_DB_TYPE_NCB, 64, 416},
|
|
{"MIX0_IRING1" , 0x1070000100010ull, CVMX_CSR_DB_TYPE_NCB, 64, 417},
|
|
{"MIX0_IRING2" , 0x1070000100018ull, CVMX_CSR_DB_TYPE_NCB, 64, 418},
|
|
{"MIX0_ISR" , 0x1070000100048ull, CVMX_CSR_DB_TYPE_NCB, 64, 419},
|
|
{"MIX0_ORCNT" , 0x1070000100040ull, CVMX_CSR_DB_TYPE_NCB, 64, 420},
|
|
{"MIX0_ORHWM" , 0x1070000100038ull, CVMX_CSR_DB_TYPE_NCB, 64, 421},
|
|
{"MIX0_ORING1" , 0x1070000100000ull, CVMX_CSR_DB_TYPE_NCB, 64, 422},
|
|
{"MIX0_ORING2" , 0x1070000100008ull, CVMX_CSR_DB_TYPE_NCB, 64, 423},
|
|
{"MIX0_REMCNT" , 0x1070000100058ull, CVMX_CSR_DB_TYPE_NCB, 64, 424},
|
|
{"NPEI_BAR1_INDEX0" , 0x11F0000008000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX1" , 0x11F0000008010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX2" , 0x11F0000008020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX3" , 0x11F0000008030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX4" , 0x11F0000008040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX5" , 0x11F0000008050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX6" , 0x11F0000008060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX7" , 0x11F0000008070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX8" , 0x11F0000008080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX9" , 0x11F0000008090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX10" , 0x11F00000080A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX11" , 0x11F00000080B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX12" , 0x11F00000080C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX13" , 0x11F00000080D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX14" , 0x11F00000080E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX15" , 0x11F00000080F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX16" , 0x11F0000008100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX17" , 0x11F0000008110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX18" , 0x11F0000008120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX19" , 0x11F0000008130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX20" , 0x11F0000008140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX21" , 0x11F0000008150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX22" , 0x11F0000008160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX23" , 0x11F0000008170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX24" , 0x11F0000008180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX25" , 0x11F0000008190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX26" , 0x11F00000081A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX27" , 0x11F00000081B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX28" , 0x11F00000081C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX29" , 0x11F00000081D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX30" , 0x11F00000081E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BAR1_INDEX31" , 0x11F00000081F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 425},
|
|
{"NPEI_BIST_STATUS" , 0x11F0000008580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 426},
|
|
{"NPEI_BIST_STATUS2" , 0x11F0000008680ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 427},
|
|
{"NPEI_CTL_PORT0" , 0x11F0000008250ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 428},
|
|
{"NPEI_CTL_PORT1" , 0x11F0000008260ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 429},
|
|
{"NPEI_CTL_STATUS" , 0x11F0000008570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 430},
|
|
{"NPEI_CTL_STATUS2" , 0x11F000000BC00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 431},
|
|
{"NPEI_DATA_OUT_CNT" , 0x11F00000085F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 432},
|
|
{"NPEI_DBG_DATA" , 0x11F0000008510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 433},
|
|
{"NPEI_DBG_SELECT" , 0x11F0000008500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 434},
|
|
{"NPEI_DMA0_COUNTS" , 0x11F0000008450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 435},
|
|
{"NPEI_DMA1_COUNTS" , 0x11F0000008460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 435},
|
|
{"NPEI_DMA2_COUNTS" , 0x11F0000008470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 435},
|
|
{"NPEI_DMA3_COUNTS" , 0x11F0000008480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 435},
|
|
{"NPEI_DMA4_COUNTS" , 0x11F0000008490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 435},
|
|
{"NPEI_DMA0_DBELL" , 0x11F00000083B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 436},
|
|
{"NPEI_DMA1_DBELL" , 0x11F00000083C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 436},
|
|
{"NPEI_DMA2_DBELL" , 0x11F00000083D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 436},
|
|
{"NPEI_DMA3_DBELL" , 0x11F00000083E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 436},
|
|
{"NPEI_DMA4_DBELL" , 0x11F00000083F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 436},
|
|
{"NPEI_DMA0_IBUFF_SADDR" , 0x11F0000008400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
|
|
{"NPEI_DMA1_IBUFF_SADDR" , 0x11F0000008410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
|
|
{"NPEI_DMA2_IBUFF_SADDR" , 0x11F0000008420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
|
|
{"NPEI_DMA3_IBUFF_SADDR" , 0x11F0000008430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
|
|
{"NPEI_DMA4_IBUFF_SADDR" , 0x11F0000008440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
|
|
{"NPEI_DMA0_NADDR" , 0x11F00000084A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 438},
|
|
{"NPEI_DMA1_NADDR" , 0x11F00000084B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 438},
|
|
{"NPEI_DMA2_NADDR" , 0x11F00000084C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 438},
|
|
{"NPEI_DMA3_NADDR" , 0x11F00000084D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 438},
|
|
{"NPEI_DMA4_NADDR" , 0x11F00000084E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 438},
|
|
{"NPEI_DMA0_INT_LEVEL" , 0x11F00000085C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 439},
|
|
{"NPEI_DMA1_INT_LEVEL" , 0x11F00000085D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 440},
|
|
{"NPEI_DMA_CNTS" , 0x11F00000085E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 441},
|
|
{"NPEI_DMA_CONTROL" , 0x11F00000083A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 442},
|
|
{"NPEI_DMA_PCIE_REQ_NUM" , 0x11F00000085B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 443},
|
|
{"NPEI_INT_A_ENB" , 0x11F0000008560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
|
|
{"NPEI_INT_A_ENB2" , 0x11F000000BCE0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 445},
|
|
{"NPEI_INT_A_SUM" , 0x11F0000008550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 446},
|
|
{"NPEI_INT_ENB" , 0x11F0000008540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 447},
|
|
{"NPEI_INT_ENB2" , 0x11F000000BCD0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 448},
|
|
{"NPEI_INT_INFO" , 0x11F0000008590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 449},
|
|
{"NPEI_INT_SUM" , 0x11F0000008530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 450},
|
|
{"NPEI_INT_SUM2" , 0x11F000000BCC0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 451},
|
|
{"NPEI_LAST_WIN_RDATA0" , 0x11F0000008600ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 452},
|
|
{"NPEI_LAST_WIN_RDATA1" , 0x11F0000008610ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 453},
|
|
{"NPEI_MEM_ACCESS_CTL" , 0x11F00000084F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 454},
|
|
{"NPEI_MEM_ACCESS_SUBID12" , 0x11F0000008280ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
|
|
{"NPEI_MEM_ACCESS_SUBID13" , 0x11F0000008290ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
|
|
{"NPEI_MEM_ACCESS_SUBID14" , 0x11F00000082A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
|
|
{"NPEI_MEM_ACCESS_SUBID15" , 0x11F00000082B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
|
|
{"NPEI_MEM_ACCESS_SUBID16" , 0x11F00000082C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
|
|
{"NPEI_MEM_ACCESS_SUBID17" , 0x11F00000082D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
|
|
{"NPEI_MEM_ACCESS_SUBID18" , 0x11F00000082E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
|
|
{"NPEI_MEM_ACCESS_SUBID19" , 0x11F00000082F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
|
|
{"NPEI_MEM_ACCESS_SUBID20" , 0x11F0000008300ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
|
|
{"NPEI_MEM_ACCESS_SUBID21" , 0x11F0000008310ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
|
|
{"NPEI_MEM_ACCESS_SUBID22" , 0x11F0000008320ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
|
|
{"NPEI_MEM_ACCESS_SUBID23" , 0x11F0000008330ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
|
|
{"NPEI_MEM_ACCESS_SUBID24" , 0x11F0000008340ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
|
|
{"NPEI_MEM_ACCESS_SUBID25" , 0x11F0000008350ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
|
|
{"NPEI_MEM_ACCESS_SUBID26" , 0x11F0000008360ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
|
|
{"NPEI_MEM_ACCESS_SUBID27" , 0x11F0000008370ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
|
|
{"NPEI_MSI_ENB0" , 0x11F000000BC50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 456},
|
|
{"NPEI_MSI_ENB1" , 0x11F000000BC60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 457},
|
|
{"NPEI_MSI_ENB2" , 0x11F000000BC70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 458},
|
|
{"NPEI_MSI_ENB3" , 0x11F000000BC80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 459},
|
|
{"NPEI_MSI_RCV0" , 0x11F000000BC10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 460},
|
|
{"NPEI_MSI_RCV1" , 0x11F000000BC20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 461},
|
|
{"NPEI_MSI_RCV2" , 0x11F000000BC30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 462},
|
|
{"NPEI_MSI_RCV3" , 0x11F000000BC40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 463},
|
|
{"NPEI_MSI_RD_MAP" , 0x11F000000BCA0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 464},
|
|
{"NPEI_MSI_W1C_ENB0" , 0x11F000000BCF0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 465},
|
|
{"NPEI_MSI_W1C_ENB1" , 0x11F000000BD00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 466},
|
|
{"NPEI_MSI_W1C_ENB2" , 0x11F000000BD10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 467},
|
|
{"NPEI_MSI_W1C_ENB3" , 0x11F000000BD20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 468},
|
|
{"NPEI_MSI_W1S_ENB0" , 0x11F000000BD30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 469},
|
|
{"NPEI_MSI_W1S_ENB1" , 0x11F000000BD40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
|
|
{"NPEI_MSI_W1S_ENB2" , 0x11F000000BD50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 471},
|
|
{"NPEI_MSI_W1S_ENB3" , 0x11F000000BD60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 472},
|
|
{"NPEI_MSI_WR_MAP" , 0x11F000000BC90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 473},
|
|
{"NPEI_PCIE_CREDIT_CNT" , 0x11F000000BD70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 474},
|
|
{"NPEI_PCIE_MSI_RCV" , 0x11F000000BCB0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 475},
|
|
{"NPEI_PCIE_MSI_RCV_B1" , 0x11F0000008650ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 476},
|
|
{"NPEI_PCIE_MSI_RCV_B2" , 0x11F0000008660ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 477},
|
|
{"NPEI_PCIE_MSI_RCV_B3" , 0x11F0000008670ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 478},
|
|
{"NPEI_PKT0_CNTS" , 0x11F000000A400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT1_CNTS" , 0x11F000000A410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT2_CNTS" , 0x11F000000A420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT3_CNTS" , 0x11F000000A430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT4_CNTS" , 0x11F000000A440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT5_CNTS" , 0x11F000000A450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT6_CNTS" , 0x11F000000A460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT7_CNTS" , 0x11F000000A470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT8_CNTS" , 0x11F000000A480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT9_CNTS" , 0x11F000000A490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT10_CNTS" , 0x11F000000A4A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT11_CNTS" , 0x11F000000A4B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT12_CNTS" , 0x11F000000A4C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT13_CNTS" , 0x11F000000A4D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT14_CNTS" , 0x11F000000A4E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT15_CNTS" , 0x11F000000A4F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT16_CNTS" , 0x11F000000A500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT17_CNTS" , 0x11F000000A510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT18_CNTS" , 0x11F000000A520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT19_CNTS" , 0x11F000000A530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT20_CNTS" , 0x11F000000A540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT21_CNTS" , 0x11F000000A550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT22_CNTS" , 0x11F000000A560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT23_CNTS" , 0x11F000000A570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT24_CNTS" , 0x11F000000A580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT25_CNTS" , 0x11F000000A590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT26_CNTS" , 0x11F000000A5A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT27_CNTS" , 0x11F000000A5B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT28_CNTS" , 0x11F000000A5C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT29_CNTS" , 0x11F000000A5D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT30_CNTS" , 0x11F000000A5E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT31_CNTS" , 0x11F000000A5F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_PKT0_IN_BP" , 0x11F000000B800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT1_IN_BP" , 0x11F000000B810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT2_IN_BP" , 0x11F000000B820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT3_IN_BP" , 0x11F000000B830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT4_IN_BP" , 0x11F000000B840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT5_IN_BP" , 0x11F000000B850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT6_IN_BP" , 0x11F000000B860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT7_IN_BP" , 0x11F000000B870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT8_IN_BP" , 0x11F000000B880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT9_IN_BP" , 0x11F000000B890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT10_IN_BP" , 0x11F000000B8A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT11_IN_BP" , 0x11F000000B8B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT12_IN_BP" , 0x11F000000B8C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT13_IN_BP" , 0x11F000000B8D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT14_IN_BP" , 0x11F000000B8E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT15_IN_BP" , 0x11F000000B8F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT16_IN_BP" , 0x11F000000B900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT17_IN_BP" , 0x11F000000B910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT18_IN_BP" , 0x11F000000B920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT19_IN_BP" , 0x11F000000B930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT20_IN_BP" , 0x11F000000B940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT21_IN_BP" , 0x11F000000B950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT22_IN_BP" , 0x11F000000B960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT23_IN_BP" , 0x11F000000B970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT24_IN_BP" , 0x11F000000B980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT25_IN_BP" , 0x11F000000B990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT26_IN_BP" , 0x11F000000B9A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT27_IN_BP" , 0x11F000000B9B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT28_IN_BP" , 0x11F000000B9C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT29_IN_BP" , 0x11F000000B9D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT30_IN_BP" , 0x11F000000B9E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT31_IN_BP" , 0x11F000000B9F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_PKT0_INSTR_BADDR" , 0x11F000000A800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT1_INSTR_BADDR" , 0x11F000000A810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT2_INSTR_BADDR" , 0x11F000000A820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT3_INSTR_BADDR" , 0x11F000000A830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT4_INSTR_BADDR" , 0x11F000000A840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT5_INSTR_BADDR" , 0x11F000000A850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT6_INSTR_BADDR" , 0x11F000000A860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT7_INSTR_BADDR" , 0x11F000000A870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT8_INSTR_BADDR" , 0x11F000000A880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT9_INSTR_BADDR" , 0x11F000000A890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT10_INSTR_BADDR" , 0x11F000000A8A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT11_INSTR_BADDR" , 0x11F000000A8B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT12_INSTR_BADDR" , 0x11F000000A8C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT13_INSTR_BADDR" , 0x11F000000A8D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT14_INSTR_BADDR" , 0x11F000000A8E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT15_INSTR_BADDR" , 0x11F000000A8F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT16_INSTR_BADDR" , 0x11F000000A900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT17_INSTR_BADDR" , 0x11F000000A910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT18_INSTR_BADDR" , 0x11F000000A920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT19_INSTR_BADDR" , 0x11F000000A930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT20_INSTR_BADDR" , 0x11F000000A940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT21_INSTR_BADDR" , 0x11F000000A950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT22_INSTR_BADDR" , 0x11F000000A960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT23_INSTR_BADDR" , 0x11F000000A970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT24_INSTR_BADDR" , 0x11F000000A980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT25_INSTR_BADDR" , 0x11F000000A990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT26_INSTR_BADDR" , 0x11F000000A9A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT27_INSTR_BADDR" , 0x11F000000A9B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT28_INSTR_BADDR" , 0x11F000000A9C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT29_INSTR_BADDR" , 0x11F000000A9D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT30_INSTR_BADDR" , 0x11F000000A9E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT31_INSTR_BADDR" , 0x11F000000A9F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_PKT0_INSTR_BAOFF_DBELL" , 0x11F000000AC00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT1_INSTR_BAOFF_DBELL" , 0x11F000000AC10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT2_INSTR_BAOFF_DBELL" , 0x11F000000AC20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT3_INSTR_BAOFF_DBELL" , 0x11F000000AC30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT4_INSTR_BAOFF_DBELL" , 0x11F000000AC40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT5_INSTR_BAOFF_DBELL" , 0x11F000000AC50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT6_INSTR_BAOFF_DBELL" , 0x11F000000AC60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT7_INSTR_BAOFF_DBELL" , 0x11F000000AC70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT8_INSTR_BAOFF_DBELL" , 0x11F000000AC80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT9_INSTR_BAOFF_DBELL" , 0x11F000000AC90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT10_INSTR_BAOFF_DBELL", 0x11F000000ACA0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT11_INSTR_BAOFF_DBELL", 0x11F000000ACB0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT12_INSTR_BAOFF_DBELL", 0x11F000000ACC0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT13_INSTR_BAOFF_DBELL", 0x11F000000ACD0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT14_INSTR_BAOFF_DBELL", 0x11F000000ACE0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT15_INSTR_BAOFF_DBELL", 0x11F000000ACF0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT16_INSTR_BAOFF_DBELL", 0x11F000000AD00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT17_INSTR_BAOFF_DBELL", 0x11F000000AD10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT18_INSTR_BAOFF_DBELL", 0x11F000000AD20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT19_INSTR_BAOFF_DBELL", 0x11F000000AD30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT20_INSTR_BAOFF_DBELL", 0x11F000000AD40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT21_INSTR_BAOFF_DBELL", 0x11F000000AD50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT22_INSTR_BAOFF_DBELL", 0x11F000000AD60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT23_INSTR_BAOFF_DBELL", 0x11F000000AD70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT24_INSTR_BAOFF_DBELL", 0x11F000000AD80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT25_INSTR_BAOFF_DBELL", 0x11F000000AD90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT26_INSTR_BAOFF_DBELL", 0x11F000000ADA0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT27_INSTR_BAOFF_DBELL", 0x11F000000ADB0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT28_INSTR_BAOFF_DBELL", 0x11F000000ADC0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT29_INSTR_BAOFF_DBELL", 0x11F000000ADD0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT30_INSTR_BAOFF_DBELL", 0x11F000000ADE0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT31_INSTR_BAOFF_DBELL", 0x11F000000ADF0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_PKT0_INSTR_FIFO_RSIZE" , 0x11F000000B000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT1_INSTR_FIFO_RSIZE" , 0x11F000000B010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT2_INSTR_FIFO_RSIZE" , 0x11F000000B020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT3_INSTR_FIFO_RSIZE" , 0x11F000000B030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT4_INSTR_FIFO_RSIZE" , 0x11F000000B040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT5_INSTR_FIFO_RSIZE" , 0x11F000000B050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT6_INSTR_FIFO_RSIZE" , 0x11F000000B060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT7_INSTR_FIFO_RSIZE" , 0x11F000000B070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT8_INSTR_FIFO_RSIZE" , 0x11F000000B080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT9_INSTR_FIFO_RSIZE" , 0x11F000000B090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT10_INSTR_FIFO_RSIZE" , 0x11F000000B0A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT11_INSTR_FIFO_RSIZE" , 0x11F000000B0B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT12_INSTR_FIFO_RSIZE" , 0x11F000000B0C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT13_INSTR_FIFO_RSIZE" , 0x11F000000B0D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT14_INSTR_FIFO_RSIZE" , 0x11F000000B0E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT15_INSTR_FIFO_RSIZE" , 0x11F000000B0F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT16_INSTR_FIFO_RSIZE" , 0x11F000000B100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT17_INSTR_FIFO_RSIZE" , 0x11F000000B110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT18_INSTR_FIFO_RSIZE" , 0x11F000000B120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT19_INSTR_FIFO_RSIZE" , 0x11F000000B130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT20_INSTR_FIFO_RSIZE" , 0x11F000000B140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT21_INSTR_FIFO_RSIZE" , 0x11F000000B150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT22_INSTR_FIFO_RSIZE" , 0x11F000000B160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT23_INSTR_FIFO_RSIZE" , 0x11F000000B170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT24_INSTR_FIFO_RSIZE" , 0x11F000000B180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT25_INSTR_FIFO_RSIZE" , 0x11F000000B190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT26_INSTR_FIFO_RSIZE" , 0x11F000000B1A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT27_INSTR_FIFO_RSIZE" , 0x11F000000B1B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT28_INSTR_FIFO_RSIZE" , 0x11F000000B1C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT29_INSTR_FIFO_RSIZE" , 0x11F000000B1D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT30_INSTR_FIFO_RSIZE" , 0x11F000000B1E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT31_INSTR_FIFO_RSIZE" , 0x11F000000B1F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_PKT0_INSTR_HEADER" , 0x11F000000B400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT1_INSTR_HEADER" , 0x11F000000B410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT2_INSTR_HEADER" , 0x11F000000B420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT3_INSTR_HEADER" , 0x11F000000B430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT4_INSTR_HEADER" , 0x11F000000B440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT5_INSTR_HEADER" , 0x11F000000B450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT6_INSTR_HEADER" , 0x11F000000B460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT7_INSTR_HEADER" , 0x11F000000B470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT8_INSTR_HEADER" , 0x11F000000B480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT9_INSTR_HEADER" , 0x11F000000B490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT10_INSTR_HEADER" , 0x11F000000B4A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT11_INSTR_HEADER" , 0x11F000000B4B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT12_INSTR_HEADER" , 0x11F000000B4C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT13_INSTR_HEADER" , 0x11F000000B4D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT14_INSTR_HEADER" , 0x11F000000B4E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT15_INSTR_HEADER" , 0x11F000000B4F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT16_INSTR_HEADER" , 0x11F000000B500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT17_INSTR_HEADER" , 0x11F000000B510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT18_INSTR_HEADER" , 0x11F000000B520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT19_INSTR_HEADER" , 0x11F000000B530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT20_INSTR_HEADER" , 0x11F000000B540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT21_INSTR_HEADER" , 0x11F000000B550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT22_INSTR_HEADER" , 0x11F000000B560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT23_INSTR_HEADER" , 0x11F000000B570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT24_INSTR_HEADER" , 0x11F000000B580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT25_INSTR_HEADER" , 0x11F000000B590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT26_INSTR_HEADER" , 0x11F000000B5A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT27_INSTR_HEADER" , 0x11F000000B5B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT28_INSTR_HEADER" , 0x11F000000B5C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT29_INSTR_HEADER" , 0x11F000000B5D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT30_INSTR_HEADER" , 0x11F000000B5E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT31_INSTR_HEADER" , 0x11F000000B5F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_PKT0_SLIST_BADDR" , 0x11F0000009400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT1_SLIST_BADDR" , 0x11F0000009410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT2_SLIST_BADDR" , 0x11F0000009420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT3_SLIST_BADDR" , 0x11F0000009430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT4_SLIST_BADDR" , 0x11F0000009440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT5_SLIST_BADDR" , 0x11F0000009450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT6_SLIST_BADDR" , 0x11F0000009460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT7_SLIST_BADDR" , 0x11F0000009470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT8_SLIST_BADDR" , 0x11F0000009480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT9_SLIST_BADDR" , 0x11F0000009490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT10_SLIST_BADDR" , 0x11F00000094A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT11_SLIST_BADDR" , 0x11F00000094B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT12_SLIST_BADDR" , 0x11F00000094C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT13_SLIST_BADDR" , 0x11F00000094D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT14_SLIST_BADDR" , 0x11F00000094E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT15_SLIST_BADDR" , 0x11F00000094F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT16_SLIST_BADDR" , 0x11F0000009500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT17_SLIST_BADDR" , 0x11F0000009510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT18_SLIST_BADDR" , 0x11F0000009520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT19_SLIST_BADDR" , 0x11F0000009530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT20_SLIST_BADDR" , 0x11F0000009540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT21_SLIST_BADDR" , 0x11F0000009550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT22_SLIST_BADDR" , 0x11F0000009560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT23_SLIST_BADDR" , 0x11F0000009570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT24_SLIST_BADDR" , 0x11F0000009580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT25_SLIST_BADDR" , 0x11F0000009590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT26_SLIST_BADDR" , 0x11F00000095A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT27_SLIST_BADDR" , 0x11F00000095B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT28_SLIST_BADDR" , 0x11F00000095C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT29_SLIST_BADDR" , 0x11F00000095D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT30_SLIST_BADDR" , 0x11F00000095E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT31_SLIST_BADDR" , 0x11F00000095F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_PKT0_SLIST_BAOFF_DBELL" , 0x11F0000009800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT1_SLIST_BAOFF_DBELL" , 0x11F0000009810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT2_SLIST_BAOFF_DBELL" , 0x11F0000009820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT3_SLIST_BAOFF_DBELL" , 0x11F0000009830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT4_SLIST_BAOFF_DBELL" , 0x11F0000009840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT5_SLIST_BAOFF_DBELL" , 0x11F0000009850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT6_SLIST_BAOFF_DBELL" , 0x11F0000009860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT7_SLIST_BAOFF_DBELL" , 0x11F0000009870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT8_SLIST_BAOFF_DBELL" , 0x11F0000009880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT9_SLIST_BAOFF_DBELL" , 0x11F0000009890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT10_SLIST_BAOFF_DBELL", 0x11F00000098A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT11_SLIST_BAOFF_DBELL", 0x11F00000098B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT12_SLIST_BAOFF_DBELL", 0x11F00000098C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT13_SLIST_BAOFF_DBELL", 0x11F00000098D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT14_SLIST_BAOFF_DBELL", 0x11F00000098E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT15_SLIST_BAOFF_DBELL", 0x11F00000098F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT16_SLIST_BAOFF_DBELL", 0x11F0000009900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT17_SLIST_BAOFF_DBELL", 0x11F0000009910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT18_SLIST_BAOFF_DBELL", 0x11F0000009920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT19_SLIST_BAOFF_DBELL", 0x11F0000009930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT20_SLIST_BAOFF_DBELL", 0x11F0000009940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT21_SLIST_BAOFF_DBELL", 0x11F0000009950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT22_SLIST_BAOFF_DBELL", 0x11F0000009960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT23_SLIST_BAOFF_DBELL", 0x11F0000009970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT24_SLIST_BAOFF_DBELL", 0x11F0000009980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT25_SLIST_BAOFF_DBELL", 0x11F0000009990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT26_SLIST_BAOFF_DBELL", 0x11F00000099A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT27_SLIST_BAOFF_DBELL", 0x11F00000099B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT28_SLIST_BAOFF_DBELL", 0x11F00000099C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT29_SLIST_BAOFF_DBELL", 0x11F00000099D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT30_SLIST_BAOFF_DBELL", 0x11F00000099E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT31_SLIST_BAOFF_DBELL", 0x11F00000099F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_PKT0_SLIST_FIFO_RSIZE" , 0x11F0000009C00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT1_SLIST_FIFO_RSIZE" , 0x11F0000009C10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT2_SLIST_FIFO_RSIZE" , 0x11F0000009C20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT3_SLIST_FIFO_RSIZE" , 0x11F0000009C30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT4_SLIST_FIFO_RSIZE" , 0x11F0000009C40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT5_SLIST_FIFO_RSIZE" , 0x11F0000009C50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT6_SLIST_FIFO_RSIZE" , 0x11F0000009C60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT7_SLIST_FIFO_RSIZE" , 0x11F0000009C70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT8_SLIST_FIFO_RSIZE" , 0x11F0000009C80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT9_SLIST_FIFO_RSIZE" , 0x11F0000009C90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT10_SLIST_FIFO_RSIZE" , 0x11F0000009CA0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT11_SLIST_FIFO_RSIZE" , 0x11F0000009CB0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT12_SLIST_FIFO_RSIZE" , 0x11F0000009CC0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT13_SLIST_FIFO_RSIZE" , 0x11F0000009CD0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT14_SLIST_FIFO_RSIZE" , 0x11F0000009CE0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT15_SLIST_FIFO_RSIZE" , 0x11F0000009CF0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT16_SLIST_FIFO_RSIZE" , 0x11F0000009D00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT17_SLIST_FIFO_RSIZE" , 0x11F0000009D10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT18_SLIST_FIFO_RSIZE" , 0x11F0000009D20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT19_SLIST_FIFO_RSIZE" , 0x11F0000009D30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT20_SLIST_FIFO_RSIZE" , 0x11F0000009D40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT21_SLIST_FIFO_RSIZE" , 0x11F0000009D50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT22_SLIST_FIFO_RSIZE" , 0x11F0000009D60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT23_SLIST_FIFO_RSIZE" , 0x11F0000009D70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT24_SLIST_FIFO_RSIZE" , 0x11F0000009D80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT25_SLIST_FIFO_RSIZE" , 0x11F0000009D90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT26_SLIST_FIFO_RSIZE" , 0x11F0000009DA0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT27_SLIST_FIFO_RSIZE" , 0x11F0000009DB0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT28_SLIST_FIFO_RSIZE" , 0x11F0000009DC0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT29_SLIST_FIFO_RSIZE" , 0x11F0000009DD0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT30_SLIST_FIFO_RSIZE" , 0x11F0000009DE0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT31_SLIST_FIFO_RSIZE" , 0x11F0000009DF0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_PKT_CNT_INT" , 0x11F0000009110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 488},
|
|
{"NPEI_PKT_CNT_INT_ENB" , 0x11F0000009130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 489},
|
|
{"NPEI_PKT_DATA_OUT_ES" , 0x11F00000090B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 490},
|
|
{"NPEI_PKT_DATA_OUT_NS" , 0x11F00000090A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 491},
|
|
{"NPEI_PKT_DATA_OUT_ROR" , 0x11F0000009090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 492},
|
|
{"NPEI_PKT_DPADDR" , 0x11F0000009080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 493},
|
|
{"NPEI_PKT_IN_BP" , 0x11F00000086B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT_IN_DONE0_CNTS" , 0x11F000000A000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE1_CNTS" , 0x11F000000A010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE2_CNTS" , 0x11F000000A020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE3_CNTS" , 0x11F000000A030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE4_CNTS" , 0x11F000000A040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE5_CNTS" , 0x11F000000A050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE6_CNTS" , 0x11F000000A060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE7_CNTS" , 0x11F000000A070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE8_CNTS" , 0x11F000000A080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE9_CNTS" , 0x11F000000A090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE10_CNTS" , 0x11F000000A0A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE11_CNTS" , 0x11F000000A0B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE12_CNTS" , 0x11F000000A0C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE13_CNTS" , 0x11F000000A0D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE14_CNTS" , 0x11F000000A0E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE15_CNTS" , 0x11F000000A0F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE16_CNTS" , 0x11F000000A100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE17_CNTS" , 0x11F000000A110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE18_CNTS" , 0x11F000000A120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE19_CNTS" , 0x11F000000A130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE20_CNTS" , 0x11F000000A140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE21_CNTS" , 0x11F000000A150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE22_CNTS" , 0x11F000000A160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE23_CNTS" , 0x11F000000A170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE24_CNTS" , 0x11F000000A180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE25_CNTS" , 0x11F000000A190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE26_CNTS" , 0x11F000000A1A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE27_CNTS" , 0x11F000000A1B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE28_CNTS" , 0x11F000000A1C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE29_CNTS" , 0x11F000000A1D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE30_CNTS" , 0x11F000000A1E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_DONE31_CNTS" , 0x11F000000A1F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT_IN_INSTR_COUNTS" , 0x11F00000086A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT_IN_PCIE_PORT" , 0x11F00000091A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT_INPUT_CONTROL" , 0x11F0000009150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT_INSTR_ENB" , 0x11F0000009000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT_INSTR_RD_SIZE" , 0x11F0000009190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT_INSTR_SIZE" , 0x11F0000009020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT_INT_LEVELS" , 0x11F0000009100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT_IPTR" , 0x11F0000009070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 503},
|
|
{"NPEI_PKT_OUT_BMODE" , 0x11F00000090D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 504},
|
|
{"NPEI_PKT_OUT_ENB" , 0x11F0000009010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 505},
|
|
{"NPEI_PKT_OUTPUT_WMARK" , 0x11F0000009160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 506},
|
|
{"NPEI_PKT_PCIE_PORT" , 0x11F00000090E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 507},
|
|
{"NPEI_PKT_PORT_IN_RST" , 0x11F0000008690ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 508},
|
|
{"NPEI_PKT_SLIST_ES" , 0x11F0000009050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 509},
|
|
{"NPEI_PKT_SLIST_ID_SIZE" , 0x11F0000009180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_SLIST_NS" , 0x11F0000009040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 511},
|
|
{"NPEI_PKT_SLIST_ROR" , 0x11F0000009030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 512},
|
|
{"NPEI_PKT_TIME_INT" , 0x11F0000009120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 513},
|
|
{"NPEI_PKT_TIME_INT_ENB" , 0x11F0000009140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 514},
|
|
{"NPEI_RSL_INT_BLOCKS" , 0x11F0000008520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 515},
|
|
{"NPEI_SCRATCH_1" , 0x11F0000008270ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 516},
|
|
{"NPEI_STATE1" , 0x11F0000008620ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 517},
|
|
{"NPEI_STATE2" , 0x11F0000008630ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 518},
|
|
{"NPEI_STATE3" , 0x11F0000008640ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 519},
|
|
{"NPEI_WIN_RD_ADDR" , 0x210ull, CVMX_CSR_DB_TYPE_PEXP, 64, 520},
|
|
{"NPEI_WIN_RD_DATA" , 0x240ull, CVMX_CSR_DB_TYPE_PEXP, 64, 521},
|
|
{"NPEI_WIN_WR_ADDR" , 0x200ull, CVMX_CSR_DB_TYPE_PEXP, 64, 522},
|
|
{"NPEI_WIN_WR_DATA" , 0x220ull, CVMX_CSR_DB_TYPE_PEXP, 64, 523},
|
|
{"NPEI_WIN_WR_MASK" , 0x230ull, CVMX_CSR_DB_TYPE_PEXP, 64, 524},
|
|
{"NPEI_WINDOW_CTL" , 0x11F0000008380ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 525},
|
|
{"PCIEEP_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 526},
|
|
{"PCIEEP_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 527},
|
|
{"PCIEEP_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 528},
|
|
{"PCIEEP_CFG003" , 0xCull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 529},
|
|
{"PCIEEP_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 530},
|
|
{"PCIEEP_CFG004_MASK" , 0x80000010ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 531},
|
|
{"PCIEEP_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 532},
|
|
{"PCIEEP_CFG005_MASK" , 0x80000014ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 533},
|
|
{"PCIEEP_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 534},
|
|
{"PCIEEP_CFG006_MASK" , 0x80000018ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 535},
|
|
{"PCIEEP_CFG007" , 0x1Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 536},
|
|
{"PCIEEP_CFG007_MASK" , 0x8000001Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 537},
|
|
{"PCIEEP_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 538},
|
|
{"PCIEEP_CFG008_MASK" , 0x80000020ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 539},
|
|
{"PCIEEP_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 540},
|
|
{"PCIEEP_CFG009_MASK" , 0x80000024ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 541},
|
|
{"PCIEEP_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 542},
|
|
{"PCIEEP_CFG011" , 0x2Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 543},
|
|
{"PCIEEP_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 544},
|
|
{"PCIEEP_CFG012_MASK" , 0x80000030ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 545},
|
|
{"PCIEEP_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 546},
|
|
{"PCIEEP_CFG015" , 0x3Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 547},
|
|
{"PCIEEP_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 548},
|
|
{"PCIEEP_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 549},
|
|
{"PCIEEP_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 550},
|
|
{"PCIEEP_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 551},
|
|
{"PCIEEP_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 552},
|
|
{"PCIEEP_CFG023" , 0x5Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 553},
|
|
{"PCIEEP_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 554},
|
|
{"PCIEEP_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 555},
|
|
{"PCIEEP_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 556},
|
|
{"PCIEEP_CFG031" , 0x7Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 557},
|
|
{"PCIEEP_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 558},
|
|
{"PCIEEP_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 559},
|
|
{"PCIEEP_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 560},
|
|
{"PCIEEP_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 561},
|
|
{"PCIEEP_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 562},
|
|
{"PCIEEP_CFG039" , 0x9Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 563},
|
|
{"PCIEEP_CFG040" , 0xA0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 564},
|
|
{"PCIEEP_CFG041" , 0xA4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 565},
|
|
{"PCIEEP_CFG042" , 0xA8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 566},
|
|
{"PCIEEP_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 567},
|
|
{"PCIEEP_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 568},
|
|
{"PCIEEP_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 569},
|
|
{"PCIEEP_CFG067" , 0x10Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 570},
|
|
{"PCIEEP_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 571},
|
|
{"PCIEEP_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 572},
|
|
{"PCIEEP_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 573},
|
|
{"PCIEEP_CFG071" , 0x11Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 574},
|
|
{"PCIEEP_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 575},
|
|
{"PCIEEP_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 576},
|
|
{"PCIEEP_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 577},
|
|
{"PCIEEP_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 578},
|
|
{"PCIEEP_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 579},
|
|
{"PCIEEP_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 580},
|
|
{"PCIEEP_CFG451" , 0x70Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 581},
|
|
{"PCIEEP_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 582},
|
|
{"PCIEEP_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 583},
|
|
{"PCIEEP_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 584},
|
|
{"PCIEEP_CFG455" , 0x71Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 585},
|
|
{"PCIEEP_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 586},
|
|
{"PCIEEP_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 587},
|
|
{"PCIEEP_CFG459" , 0x72Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 588},
|
|
{"PCIEEP_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 589},
|
|
{"PCIEEP_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 590},
|
|
{"PCIEEP_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 591},
|
|
{"PCIEEP_CFG463" , 0x73Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 592},
|
|
{"PCIEEP_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 593},
|
|
{"PCIEEP_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 594},
|
|
{"PCIEEP_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 595},
|
|
{"PCIEEP_CFG467" , 0x74Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 596},
|
|
{"PCIEEP_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 597},
|
|
{"PCIEEP_CFG490" , 0x7A8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 598},
|
|
{"PCIEEP_CFG491" , 0x7ACull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 599},
|
|
{"PCIEEP_CFG492" , 0x7B0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 600},
|
|
{"PCIEEP_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 601},
|
|
{"PCIEEP_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 602},
|
|
{"PCIERC0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 603},
|
|
{"PCIERC1_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 603},
|
|
{"PCIERC0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 604},
|
|
{"PCIERC1_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 604},
|
|
{"PCIERC0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 605},
|
|
{"PCIERC1_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 605},
|
|
{"PCIERC0_CFG003" , 0xCull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 606},
|
|
{"PCIERC1_CFG003" , 0xCull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 606},
|
|
{"PCIERC0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 607},
|
|
{"PCIERC1_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 607},
|
|
{"PCIERC0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 608},
|
|
{"PCIERC1_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 608},
|
|
{"PCIERC0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 609},
|
|
{"PCIERC1_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 609},
|
|
{"PCIERC0_CFG007" , 0x1Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 610},
|
|
{"PCIERC1_CFG007" , 0x1Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 610},
|
|
{"PCIERC0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 611},
|
|
{"PCIERC1_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 611},
|
|
{"PCIERC0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 612},
|
|
{"PCIERC1_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 612},
|
|
{"PCIERC0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 613},
|
|
{"PCIERC1_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 613},
|
|
{"PCIERC0_CFG011" , 0x2Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 614},
|
|
{"PCIERC1_CFG011" , 0x2Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 614},
|
|
{"PCIERC0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 615},
|
|
{"PCIERC1_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 615},
|
|
{"PCIERC0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 616},
|
|
{"PCIERC1_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 616},
|
|
{"PCIERC0_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 617},
|
|
{"PCIERC1_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 617},
|
|
{"PCIERC0_CFG015" , 0x3Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 618},
|
|
{"PCIERC1_CFG015" , 0x3Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 618},
|
|
{"PCIERC0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 619},
|
|
{"PCIERC1_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 619},
|
|
{"PCIERC0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 620},
|
|
{"PCIERC1_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 620},
|
|
{"PCIERC0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 621},
|
|
{"PCIERC1_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 621},
|
|
{"PCIERC0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 622},
|
|
{"PCIERC1_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 622},
|
|
{"PCIERC0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 623},
|
|
{"PCIERC1_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 623},
|
|
{"PCIERC0_CFG023" , 0x5Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 624},
|
|
{"PCIERC1_CFG023" , 0x5Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 624},
|
|
{"PCIERC0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 625},
|
|
{"PCIERC1_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 625},
|
|
{"PCIERC0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 626},
|
|
{"PCIERC1_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 626},
|
|
{"PCIERC0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 627},
|
|
{"PCIERC1_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 627},
|
|
{"PCIERC0_CFG031" , 0x7Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 628},
|
|
{"PCIERC1_CFG031" , 0x7Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 628},
|
|
{"PCIERC0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 629},
|
|
{"PCIERC1_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 629},
|
|
{"PCIERC0_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 630},
|
|
{"PCIERC1_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 630},
|
|
{"PCIERC0_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 631},
|
|
{"PCIERC1_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 631},
|
|
{"PCIERC0_CFG035" , 0x8Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 632},
|
|
{"PCIERC1_CFG035" , 0x8Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 632},
|
|
{"PCIERC0_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 633},
|
|
{"PCIERC1_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 633},
|
|
{"PCIERC0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 634},
|
|
{"PCIERC1_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 634},
|
|
{"PCIERC0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 635},
|
|
{"PCIERC1_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 635},
|
|
{"PCIERC0_CFG039" , 0x9Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 636},
|
|
{"PCIERC1_CFG039" , 0x9Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 636},
|
|
{"PCIERC0_CFG040" , 0xA0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 637},
|
|
{"PCIERC1_CFG040" , 0xA0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 637},
|
|
{"PCIERC0_CFG041" , 0xA4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 638},
|
|
{"PCIERC1_CFG041" , 0xA4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 638},
|
|
{"PCIERC0_CFG042" , 0xA8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 639},
|
|
{"PCIERC1_CFG042" , 0xA8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 639},
|
|
{"PCIERC0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 640},
|
|
{"PCIERC1_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 640},
|
|
{"PCIERC0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 641},
|
|
{"PCIERC1_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 641},
|
|
{"PCIERC0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 642},
|
|
{"PCIERC1_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 642},
|
|
{"PCIERC0_CFG067" , 0x10Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 643},
|
|
{"PCIERC1_CFG067" , 0x10Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 643},
|
|
{"PCIERC0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 644},
|
|
{"PCIERC1_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 644},
|
|
{"PCIERC0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 645},
|
|
{"PCIERC1_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 645},
|
|
{"PCIERC0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 646},
|
|
{"PCIERC1_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 646},
|
|
{"PCIERC0_CFG071" , 0x11Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 647},
|
|
{"PCIERC1_CFG071" , 0x11Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 647},
|
|
{"PCIERC0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 648},
|
|
{"PCIERC1_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 648},
|
|
{"PCIERC0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 649},
|
|
{"PCIERC1_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 649},
|
|
{"PCIERC0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 650},
|
|
{"PCIERC1_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 650},
|
|
{"PCIERC0_CFG075" , 0x12Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 651},
|
|
{"PCIERC1_CFG075" , 0x12Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 651},
|
|
{"PCIERC0_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 652},
|
|
{"PCIERC1_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 652},
|
|
{"PCIERC0_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 653},
|
|
{"PCIERC1_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 653},
|
|
{"PCIERC0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 654},
|
|
{"PCIERC1_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 654},
|
|
{"PCIERC0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 655},
|
|
{"PCIERC1_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 655},
|
|
{"PCIERC0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 656},
|
|
{"PCIERC1_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 656},
|
|
{"PCIERC0_CFG451" , 0x70Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 657},
|
|
{"PCIERC1_CFG451" , 0x70Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 657},
|
|
{"PCIERC0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 658},
|
|
{"PCIERC1_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 658},
|
|
{"PCIERC0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 659},
|
|
{"PCIERC1_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 659},
|
|
{"PCIERC0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 660},
|
|
{"PCIERC1_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 660},
|
|
{"PCIERC0_CFG455" , 0x71Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 661},
|
|
{"PCIERC1_CFG455" , 0x71Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 661},
|
|
{"PCIERC0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 662},
|
|
{"PCIERC1_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 662},
|
|
{"PCIERC0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 663},
|
|
{"PCIERC1_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 663},
|
|
{"PCIERC0_CFG459" , 0x72Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 664},
|
|
{"PCIERC1_CFG459" , 0x72Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 664},
|
|
{"PCIERC0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 665},
|
|
{"PCIERC1_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 665},
|
|
{"PCIERC0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 666},
|
|
{"PCIERC1_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 666},
|
|
{"PCIERC0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 667},
|
|
{"PCIERC1_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 667},
|
|
{"PCIERC0_CFG463" , 0x73Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 668},
|
|
{"PCIERC1_CFG463" , 0x73Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 668},
|
|
{"PCIERC0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 669},
|
|
{"PCIERC1_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 669},
|
|
{"PCIERC0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 670},
|
|
{"PCIERC1_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 670},
|
|
{"PCIERC0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 671},
|
|
{"PCIERC1_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 671},
|
|
{"PCIERC0_CFG467" , 0x74Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 672},
|
|
{"PCIERC1_CFG467" , 0x74Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 672},
|
|
{"PCIERC0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 673},
|
|
{"PCIERC1_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 673},
|
|
{"PCIERC0_CFG490" , 0x7A8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 674},
|
|
{"PCIERC1_CFG490" , 0x7A8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 674},
|
|
{"PCIERC0_CFG491" , 0x7ACull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 675},
|
|
{"PCIERC1_CFG491" , 0x7ACull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 675},
|
|
{"PCIERC0_CFG492" , 0x7B0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 676},
|
|
{"PCIERC1_CFG492" , 0x7B0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 676},
|
|
{"PCIERC0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 677},
|
|
{"PCIERC1_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 677},
|
|
{"PCIERC0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 678},
|
|
{"PCIERC1_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 678},
|
|
{"PCS0_AN000_ADV_REG" , 0x11800B0001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
|
|
{"PCS0_AN001_ADV_REG" , 0x11800B0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
|
|
{"PCS0_AN002_ADV_REG" , 0x11800B0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
|
|
{"PCS0_AN003_ADV_REG" , 0x11800B0001C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
|
|
{"PCS1_AN000_ADV_REG" , 0x11800B8001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
|
|
{"PCS1_AN001_ADV_REG" , 0x11800B8001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
|
|
{"PCS1_AN002_ADV_REG" , 0x11800B8001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
|
|
{"PCS1_AN003_ADV_REG" , 0x11800B8001C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
|
|
{"PCS0_AN000_EXT_ST_REG" , 0x11800B0001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
|
|
{"PCS0_AN001_EXT_ST_REG" , 0x11800B0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
|
|
{"PCS0_AN002_EXT_ST_REG" , 0x11800B0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
|
|
{"PCS0_AN003_EXT_ST_REG" , 0x11800B0001C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
|
|
{"PCS1_AN000_EXT_ST_REG" , 0x11800B8001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
|
|
{"PCS1_AN001_EXT_ST_REG" , 0x11800B8001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
|
|
{"PCS1_AN002_EXT_ST_REG" , 0x11800B8001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
|
|
{"PCS1_AN003_EXT_ST_REG" , 0x11800B8001C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
|
|
{"PCS0_AN000_LP_ABIL_REG" , 0x11800B0001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
|
|
{"PCS0_AN001_LP_ABIL_REG" , 0x11800B0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
|
|
{"PCS0_AN002_LP_ABIL_REG" , 0x11800B0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
|
|
{"PCS0_AN003_LP_ABIL_REG" , 0x11800B0001C18ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
|
|
{"PCS1_AN000_LP_ABIL_REG" , 0x11800B8001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
|
|
{"PCS1_AN001_LP_ABIL_REG" , 0x11800B8001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
|
|
{"PCS1_AN002_LP_ABIL_REG" , 0x11800B8001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
|
|
{"PCS1_AN003_LP_ABIL_REG" , 0x11800B8001C18ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
|
|
{"PCS0_AN000_RESULTS_REG" , 0x11800B0001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PCS0_AN001_RESULTS_REG" , 0x11800B0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PCS0_AN002_RESULTS_REG" , 0x11800B0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PCS0_AN003_RESULTS_REG" , 0x11800B0001C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PCS1_AN000_RESULTS_REG" , 0x11800B8001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PCS1_AN001_RESULTS_REG" , 0x11800B8001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PCS1_AN002_RESULTS_REG" , 0x11800B8001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PCS1_AN003_RESULTS_REG" , 0x11800B8001C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PCS0_INT000_EN_REG" , 0x11800B0001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PCS0_INT001_EN_REG" , 0x11800B0001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PCS0_INT002_EN_REG" , 0x11800B0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PCS0_INT003_EN_REG" , 0x11800B0001C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PCS1_INT000_EN_REG" , 0x11800B8001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PCS1_INT001_EN_REG" , 0x11800B8001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PCS1_INT002_EN_REG" , 0x11800B8001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PCS1_INT003_EN_REG" , 0x11800B8001C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PCS0_INT000_REG" , 0x11800B0001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PCS0_INT001_REG" , 0x11800B0001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PCS0_INT002_REG" , 0x11800B0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PCS0_INT003_REG" , 0x11800B0001C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PCS1_INT000_REG" , 0x11800B8001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PCS1_INT001_REG" , 0x11800B8001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PCS1_INT002_REG" , 0x11800B8001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PCS1_INT003_REG" , 0x11800B8001C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PCS0_LINK000_TIMER_COUNT_REG", 0x11800B0001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PCS0_LINK001_TIMER_COUNT_REG", 0x11800B0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PCS0_LINK002_TIMER_COUNT_REG", 0x11800B0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PCS0_LINK003_TIMER_COUNT_REG", 0x11800B0001C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PCS1_LINK000_TIMER_COUNT_REG", 0x11800B8001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PCS1_LINK001_TIMER_COUNT_REG", 0x11800B8001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PCS1_LINK002_TIMER_COUNT_REG", 0x11800B8001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PCS1_LINK003_TIMER_COUNT_REG", 0x11800B8001C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PCS0_LOG_ANL000_REG" , 0x11800B0001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PCS0_LOG_ANL001_REG" , 0x11800B0001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PCS0_LOG_ANL002_REG" , 0x11800B0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PCS0_LOG_ANL003_REG" , 0x11800B0001C90ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PCS1_LOG_ANL000_REG" , 0x11800B8001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PCS1_LOG_ANL001_REG" , 0x11800B8001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PCS1_LOG_ANL002_REG" , 0x11800B8001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PCS1_LOG_ANL003_REG" , 0x11800B8001C90ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PCS0_MISC000_CTL_REG" , 0x11800B0001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
|
|
{"PCS0_MISC001_CTL_REG" , 0x11800B0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
|
|
{"PCS0_MISC002_CTL_REG" , 0x11800B0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
|
|
{"PCS0_MISC003_CTL_REG" , 0x11800B0001C78ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
|
|
{"PCS1_MISC000_CTL_REG" , 0x11800B8001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
|
|
{"PCS1_MISC001_CTL_REG" , 0x11800B8001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
|
|
{"PCS1_MISC002_CTL_REG" , 0x11800B8001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
|
|
{"PCS1_MISC003_CTL_REG" , 0x11800B8001C78ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
|
|
{"PCS0_MR000_CONTROL_REG" , 0x11800B0001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
|
|
{"PCS0_MR001_CONTROL_REG" , 0x11800B0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
|
|
{"PCS0_MR002_CONTROL_REG" , 0x11800B0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
|
|
{"PCS0_MR003_CONTROL_REG" , 0x11800B0001C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
|
|
{"PCS1_MR000_CONTROL_REG" , 0x11800B8001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
|
|
{"PCS1_MR001_CONTROL_REG" , 0x11800B8001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
|
|
{"PCS1_MR002_CONTROL_REG" , 0x11800B8001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
|
|
{"PCS1_MR003_CONTROL_REG" , 0x11800B8001C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
|
|
{"PCS0_MR000_STATUS_REG" , 0x11800B0001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PCS0_MR001_STATUS_REG" , 0x11800B0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PCS0_MR002_STATUS_REG" , 0x11800B0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PCS0_MR003_STATUS_REG" , 0x11800B0001C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PCS1_MR000_STATUS_REG" , 0x11800B8001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PCS1_MR001_STATUS_REG" , 0x11800B8001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PCS1_MR002_STATUS_REG" , 0x11800B8001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PCS1_MR003_STATUS_REG" , 0x11800B8001C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PCS0_RX000_STATES_REG" , 0x11800B0001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
|
|
{"PCS0_RX001_STATES_REG" , 0x11800B0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
|
|
{"PCS0_RX002_STATES_REG" , 0x11800B0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
|
|
{"PCS0_RX003_STATES_REG" , 0x11800B0001C58ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
|
|
{"PCS1_RX000_STATES_REG" , 0x11800B8001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
|
|
{"PCS1_RX001_STATES_REG" , 0x11800B8001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
|
|
{"PCS1_RX002_STATES_REG" , 0x11800B8001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
|
|
{"PCS1_RX003_STATES_REG" , 0x11800B8001C58ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
|
|
{"PCS0_RX000_SYNC_REG" , 0x11800B0001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PCS0_RX001_SYNC_REG" , 0x11800B0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PCS0_RX002_SYNC_REG" , 0x11800B0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PCS0_RX003_SYNC_REG" , 0x11800B0001C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PCS1_RX000_SYNC_REG" , 0x11800B8001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PCS1_RX001_SYNC_REG" , 0x11800B8001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PCS1_RX002_SYNC_REG" , 0x11800B8001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PCS1_RX003_SYNC_REG" , 0x11800B8001C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PCS0_SGM000_AN_ADV_REG" , 0x11800B0001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PCS0_SGM001_AN_ADV_REG" , 0x11800B0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PCS0_SGM002_AN_ADV_REG" , 0x11800B0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PCS0_SGM003_AN_ADV_REG" , 0x11800B0001C68ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PCS1_SGM000_AN_ADV_REG" , 0x11800B8001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PCS1_SGM001_AN_ADV_REG" , 0x11800B8001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PCS1_SGM002_AN_ADV_REG" , 0x11800B8001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PCS1_SGM003_AN_ADV_REG" , 0x11800B8001C68ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PCS0_SGM000_LP_ADV_REG" , 0x11800B0001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PCS0_SGM001_LP_ADV_REG" , 0x11800B0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PCS0_SGM002_LP_ADV_REG" , 0x11800B0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PCS0_SGM003_LP_ADV_REG" , 0x11800B0001C70ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PCS1_SGM000_LP_ADV_REG" , 0x11800B8001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PCS1_SGM001_LP_ADV_REG" , 0x11800B8001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PCS1_SGM002_LP_ADV_REG" , 0x11800B8001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PCS1_SGM003_LP_ADV_REG" , 0x11800B8001C70ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PCS0_TX000_STATES_REG" , 0x11800B0001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PCS0_TX001_STATES_REG" , 0x11800B0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PCS0_TX002_STATES_REG" , 0x11800B0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PCS0_TX003_STATES_REG" , 0x11800B0001C60ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PCS1_TX000_STATES_REG" , 0x11800B8001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PCS1_TX001_STATES_REG" , 0x11800B8001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PCS1_TX002_STATES_REG" , 0x11800B8001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PCS1_TX003_STATES_REG" , 0x11800B8001C60ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PCS0_TX_RX000_POLARITY_REG" , 0x11800B0001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
|
|
{"PCS0_TX_RX001_POLARITY_REG" , 0x11800B0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
|
|
{"PCS0_TX_RX002_POLARITY_REG" , 0x11800B0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
|
|
{"PCS0_TX_RX003_POLARITY_REG" , 0x11800B0001C48ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
|
|
{"PCS1_TX_RX000_POLARITY_REG" , 0x11800B8001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
|
|
{"PCS1_TX_RX001_POLARITY_REG" , 0x11800B8001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
|
|
{"PCS1_TX_RX002_POLARITY_REG" , 0x11800B8001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
|
|
{"PCS1_TX_RX003_POLARITY_REG" , 0x11800B8001C48ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
|
|
{"PCSX0_10GBX_STATUS_REG" , 0x11800B0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
|
|
{"PCSX1_10GBX_STATUS_REG" , 0x11800B8000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
|
|
{"PCSX0_BIST_STATUS_REG" , 0x11800B0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
|
|
{"PCSX1_BIST_STATUS_REG" , 0x11800B8000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
|
|
{"PCSX0_BIT_LOCK_STATUS_REG" , 0x11800B0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
|
|
{"PCSX1_BIT_LOCK_STATUS_REG" , 0x11800B8000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
|
|
{"PCSX0_CONTROL1_REG" , 0x11800B0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
|
|
{"PCSX1_CONTROL1_REG" , 0x11800B8000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
|
|
{"PCSX0_CONTROL2_REG" , 0x11800B0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
|
|
{"PCSX1_CONTROL2_REG" , 0x11800B8000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
|
|
{"PCSX0_INT_EN_REG" , 0x11800B0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
|
|
{"PCSX1_INT_EN_REG" , 0x11800B8000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
|
|
{"PCSX0_INT_REG" , 0x11800B0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
|
|
{"PCSX1_INT_REG" , 0x11800B8000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
|
|
{"PCSX0_LOG_ANL_REG" , 0x11800B0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PCSX1_LOG_ANL_REG" , 0x11800B8000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PCSX0_MISC_CTL_REG" , 0x11800B0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
|
|
{"PCSX1_MISC_CTL_REG" , 0x11800B8000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
|
|
{"PCSX0_RX_SYNC_STATES_REG" , 0x11800B0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
|
|
{"PCSX1_RX_SYNC_STATES_REG" , 0x11800B8000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
|
|
{"PCSX0_SPD_ABIL_REG" , 0x11800B0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
|
|
{"PCSX1_SPD_ABIL_REG" , 0x11800B8000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
|
|
{"PCSX0_STATUS1_REG" , 0x11800B0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
|
|
{"PCSX1_STATUS1_REG" , 0x11800B8000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
|
|
{"PCSX0_STATUS2_REG" , 0x11800B0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
|
|
{"PCSX1_STATUS2_REG" , 0x11800B8000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
|
|
{"PCSX0_TX_RX_POLARITY_REG" , 0x11800B0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
|
|
{"PCSX1_TX_RX_POLARITY_REG" , 0x11800B8000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
|
|
{"PCSX0_TX_RX_STATES_REG" , 0x11800B0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
|
|
{"PCSX1_TX_RX_STATES_REG" , 0x11800B8000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
|
|
{"PESC0_BIST_STATUS" , 0x11800C8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 711},
|
|
{"PESC1_BIST_STATUS" , 0x11800D0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 711},
|
|
{"PESC0_BIST_STATUS2" , 0x11800C8000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 712},
|
|
{"PESC1_BIST_STATUS2" , 0x11800D0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 712},
|
|
{"PESC0_CFG_RD" , 0x11800C8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 713},
|
|
{"PESC1_CFG_RD" , 0x11800D0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 713},
|
|
{"PESC0_CFG_WR" , 0x11800C8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 714},
|
|
{"PESC1_CFG_WR" , 0x11800D0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 714},
|
|
{"PESC0_CPL_LUT_VALID" , 0x11800C8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 715},
|
|
{"PESC1_CPL_LUT_VALID" , 0x11800D0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 715},
|
|
{"PESC0_CTL_STATUS" , 0x11800C8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 716},
|
|
{"PESC1_CTL_STATUS" , 0x11800D0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 716},
|
|
{"PESC0_CTL_STATUS2" , 0x11800C8000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 717},
|
|
{"PESC1_CTL_STATUS2" , 0x11800D0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 717},
|
|
{"PESC0_DBG_INFO" , 0x11800C8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 718},
|
|
{"PESC1_DBG_INFO" , 0x11800D0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 718},
|
|
{"PESC0_DBG_INFO_EN" , 0x11800C80000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 719},
|
|
{"PESC1_DBG_INFO_EN" , 0x11800D00000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 719},
|
|
{"PESC0_DIAG_STATUS" , 0x11800C8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 720},
|
|
{"PESC1_DIAG_STATUS" , 0x11800D0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 720},
|
|
{"PESC0_P2N_BAR0_START" , 0x11800C8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 721},
|
|
{"PESC1_P2N_BAR0_START" , 0x11800D0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 721},
|
|
{"PESC0_P2N_BAR1_START" , 0x11800C8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 722},
|
|
{"PESC1_P2N_BAR1_START" , 0x11800D0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 722},
|
|
{"PESC0_P2N_BAR2_START" , 0x11800C8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 723},
|
|
{"PESC1_P2N_BAR2_START" , 0x11800D0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 723},
|
|
{"PESC0_P2P_BAR000_END" , 0x11800C8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
|
|
{"PESC0_P2P_BAR001_END" , 0x11800C8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
|
|
{"PESC0_P2P_BAR002_END" , 0x11800C8000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
|
|
{"PESC0_P2P_BAR003_END" , 0x11800C8000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
|
|
{"PESC1_P2P_BAR000_END" , 0x11800D0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
|
|
{"PESC1_P2P_BAR001_END" , 0x11800D0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
|
|
{"PESC1_P2P_BAR002_END" , 0x11800D0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
|
|
{"PESC1_P2P_BAR003_END" , 0x11800D0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
|
|
{"PESC0_P2P_BAR000_START" , 0x11800C8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
|
|
{"PESC0_P2P_BAR001_START" , 0x11800C8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
|
|
{"PESC0_P2P_BAR002_START" , 0x11800C8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
|
|
{"PESC0_P2P_BAR003_START" , 0x11800C8000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
|
|
{"PESC1_P2P_BAR000_START" , 0x11800D0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
|
|
{"PESC1_P2P_BAR001_START" , 0x11800D0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
|
|
{"PESC1_P2P_BAR002_START" , 0x11800D0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
|
|
{"PESC1_P2P_BAR003_START" , 0x11800D0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
|
|
{"PESC0_TLP_CREDITS" , 0x11800C8000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 726},
|
|
{"PESC1_TLP_CREDITS" , 0x11800D0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 726},
|
|
{"PIP_BCK_PRS" , 0x11800A0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 727},
|
|
{"PIP_BIST_STATUS" , 0x11800A0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 728},
|
|
{"PIP_DEC_IPSEC0" , 0x11800A0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 729},
|
|
{"PIP_DEC_IPSEC1" , 0x11800A0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 729},
|
|
{"PIP_DEC_IPSEC2" , 0x11800A0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 729},
|
|
{"PIP_DEC_IPSEC3" , 0x11800A0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 729},
|
|
{"PIP_DSA_SRC_GRP" , 0x11800A0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
|
|
{"PIP_DSA_VID_GRP" , 0x11800A0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 731},
|
|
{"PIP_FRM_LEN_CHK0" , 0x11800A0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 732},
|
|
{"PIP_FRM_LEN_CHK1" , 0x11800A0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 732},
|
|
{"PIP_GBL_CFG" , 0x11800A0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 733},
|
|
{"PIP_GBL_CTL" , 0x11800A0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 734},
|
|
{"PIP_HG_PRI_QOS" , 0x11800A00001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 735},
|
|
{"PIP_INT_EN" , 0x11800A0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 736},
|
|
{"PIP_INT_REG" , 0x11800A0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 737},
|
|
{"PIP_IP_OFFSET" , 0x11800A0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
|
|
{"PIP_PRT_CFG0" , 0x11800A0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PIP_PRT_CFG1" , 0x11800A0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PIP_PRT_CFG2" , 0x11800A0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PIP_PRT_CFG3" , 0x11800A0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PIP_PRT_CFG16" , 0x11800A0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PIP_PRT_CFG17" , 0x11800A0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PIP_PRT_CFG18" , 0x11800A0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PIP_PRT_CFG19" , 0x11800A0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PIP_PRT_CFG32" , 0x11800A0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PIP_PRT_CFG33" , 0x11800A0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PIP_PRT_CFG34" , 0x11800A0000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PIP_PRT_CFG35" , 0x11800A0000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PIP_PRT_CFG36" , 0x11800A0000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PIP_PRT_CFG37" , 0x11800A0000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PIP_PRT_CFG38" , 0x11800A0000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PIP_PRT_CFG39" , 0x11800A0000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PIP_PRT_TAG0" , 0x11800A0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PIP_PRT_TAG1" , 0x11800A0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PIP_PRT_TAG2" , 0x11800A0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PIP_PRT_TAG3" , 0x11800A0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PIP_PRT_TAG16" , 0x11800A0000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PIP_PRT_TAG17" , 0x11800A0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PIP_PRT_TAG18" , 0x11800A0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PIP_PRT_TAG19" , 0x11800A0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PIP_PRT_TAG32" , 0x11800A0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PIP_PRT_TAG33" , 0x11800A0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PIP_PRT_TAG34" , 0x11800A0000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PIP_PRT_TAG35" , 0x11800A0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PIP_PRT_TAG36" , 0x11800A0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PIP_PRT_TAG37" , 0x11800A0000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PIP_PRT_TAG38" , 0x11800A0000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PIP_PRT_TAG39" , 0x11800A0000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PIP_QOS_DIFF0" , 0x11800A0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF1" , 0x11800A0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF2" , 0x11800A0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF3" , 0x11800A0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF4" , 0x11800A0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF5" , 0x11800A0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF6" , 0x11800A0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF7" , 0x11800A0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF8" , 0x11800A0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF9" , 0x11800A0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF10" , 0x11800A0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF11" , 0x11800A0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF12" , 0x11800A0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF13" , 0x11800A0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF14" , 0x11800A0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF15" , 0x11800A0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF16" , 0x11800A0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF17" , 0x11800A0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF18" , 0x11800A0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF19" , 0x11800A0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF20" , 0x11800A00006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF21" , 0x11800A00006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF22" , 0x11800A00006B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF23" , 0x11800A00006B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF24" , 0x11800A00006C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF25" , 0x11800A00006C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF26" , 0x11800A00006D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF27" , 0x11800A00006D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF28" , 0x11800A00006E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF29" , 0x11800A00006E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF30" , 0x11800A00006F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF31" , 0x11800A00006F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF32" , 0x11800A0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF33" , 0x11800A0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF34" , 0x11800A0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF35" , 0x11800A0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF36" , 0x11800A0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF37" , 0x11800A0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF38" , 0x11800A0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF39" , 0x11800A0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF40" , 0x11800A0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF41" , 0x11800A0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF42" , 0x11800A0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF43" , 0x11800A0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF44" , 0x11800A0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF45" , 0x11800A0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF46" , 0x11800A0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF47" , 0x11800A0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF48" , 0x11800A0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF49" , 0x11800A0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF50" , 0x11800A0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF51" , 0x11800A0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF52" , 0x11800A00007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF53" , 0x11800A00007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF54" , 0x11800A00007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF55" , 0x11800A00007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF56" , 0x11800A00007C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF57" , 0x11800A00007C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF58" , 0x11800A00007D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF59" , 0x11800A00007D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF60" , 0x11800A00007E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF61" , 0x11800A00007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF62" , 0x11800A00007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_DIFF63" , 0x11800A00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_QOS_VLAN0" , 0x11800A00000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
|
|
{"PIP_QOS_VLAN1" , 0x11800A00000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
|
|
{"PIP_QOS_VLAN2" , 0x11800A00000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
|
|
{"PIP_QOS_VLAN3" , 0x11800A00000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
|
|
{"PIP_QOS_VLAN4" , 0x11800A00000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
|
|
{"PIP_QOS_VLAN5" , 0x11800A00000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
|
|
{"PIP_QOS_VLAN6" , 0x11800A00000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
|
|
{"PIP_QOS_VLAN7" , 0x11800A00000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
|
|
{"PIP_QOS_WATCH0" , 0x11800A0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
|
|
{"PIP_QOS_WATCH1" , 0x11800A0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
|
|
{"PIP_QOS_WATCH2" , 0x11800A0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
|
|
{"PIP_QOS_WATCH3" , 0x11800A0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
|
|
{"PIP_QOS_WATCH4" , 0x11800A0000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
|
|
{"PIP_QOS_WATCH5" , 0x11800A0000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
|
|
{"PIP_QOS_WATCH6" , 0x11800A0000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
|
|
{"PIP_QOS_WATCH7" , 0x11800A0000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
|
|
{"PIP_RAW_WORD" , 0x11800A00000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 744},
|
|
{"PIP_SFT_RST" , 0x11800A0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 745},
|
|
{"PIP_STAT0_PRT0" , 0x11800A0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
|
|
{"PIP_STAT0_PRT1" , 0x11800A0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
|
|
{"PIP_STAT0_PRT2" , 0x11800A00008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
|
|
{"PIP_STAT0_PRT3" , 0x11800A00008F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
|
|
{"PIP_STAT0_PRT16" , 0x11800A0000D00ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
|
|
{"PIP_STAT0_PRT17" , 0x11800A0000D50ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
|
|
{"PIP_STAT0_PRT18" , 0x11800A0000DA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
|
|
{"PIP_STAT0_PRT19" , 0x11800A0000DF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
|
|
{"PIP_STAT0_PRT32" , 0x11800A0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
|
|
{"PIP_STAT0_PRT33" , 0x11800A0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
|
|
{"PIP_STAT0_PRT34" , 0x11800A00012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
|
|
{"PIP_STAT0_PRT35" , 0x11800A00012F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
|
|
{"PIP_STAT0_PRT36" , 0x11800A0001340ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
|
|
{"PIP_STAT0_PRT37" , 0x11800A0001390ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
|
|
{"PIP_STAT0_PRT38" , 0x11800A00013E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
|
|
{"PIP_STAT0_PRT39" , 0x11800A0001430ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
|
|
{"PIP_STAT1_PRT0" , 0x11800A0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
|
|
{"PIP_STAT1_PRT1" , 0x11800A0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
|
|
{"PIP_STAT1_PRT2" , 0x11800A00008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
|
|
{"PIP_STAT1_PRT3" , 0x11800A00008F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
|
|
{"PIP_STAT1_PRT16" , 0x11800A0000D08ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
|
|
{"PIP_STAT1_PRT17" , 0x11800A0000D58ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
|
|
{"PIP_STAT1_PRT18" , 0x11800A0000DA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
|
|
{"PIP_STAT1_PRT19" , 0x11800A0000DF8ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
|
|
{"PIP_STAT1_PRT32" , 0x11800A0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
|
|
{"PIP_STAT1_PRT33" , 0x11800A0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
|
|
{"PIP_STAT1_PRT34" , 0x11800A00012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
|
|
{"PIP_STAT1_PRT35" , 0x11800A00012F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
|
|
{"PIP_STAT1_PRT36" , 0x11800A0001348ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
|
|
{"PIP_STAT1_PRT37" , 0x11800A0001398ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
|
|
{"PIP_STAT1_PRT38" , 0x11800A00013E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
|
|
{"PIP_STAT1_PRT39" , 0x11800A0001438ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
|
|
{"PIP_STAT2_PRT0" , 0x11800A0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
|
|
{"PIP_STAT2_PRT1" , 0x11800A0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
|
|
{"PIP_STAT2_PRT2" , 0x11800A00008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
|
|
{"PIP_STAT2_PRT3" , 0x11800A0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
|
|
{"PIP_STAT2_PRT16" , 0x11800A0000D10ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
|
|
{"PIP_STAT2_PRT17" , 0x11800A0000D60ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
|
|
{"PIP_STAT2_PRT18" , 0x11800A0000DB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
|
|
{"PIP_STAT2_PRT19" , 0x11800A0000E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
|
|
{"PIP_STAT2_PRT32" , 0x11800A0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
|
|
{"PIP_STAT2_PRT33" , 0x11800A0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
|
|
{"PIP_STAT2_PRT34" , 0x11800A00012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
|
|
{"PIP_STAT2_PRT35" , 0x11800A0001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
|
|
{"PIP_STAT2_PRT36" , 0x11800A0001350ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
|
|
{"PIP_STAT2_PRT37" , 0x11800A00013A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
|
|
{"PIP_STAT2_PRT38" , 0x11800A00013F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
|
|
{"PIP_STAT2_PRT39" , 0x11800A0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
|
|
{"PIP_STAT3_PRT0" , 0x11800A0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
|
|
{"PIP_STAT3_PRT1" , 0x11800A0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
|
|
{"PIP_STAT3_PRT2" , 0x11800A00008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
|
|
{"PIP_STAT3_PRT3" , 0x11800A0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
|
|
{"PIP_STAT3_PRT16" , 0x11800A0000D18ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
|
|
{"PIP_STAT3_PRT17" , 0x11800A0000D68ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
|
|
{"PIP_STAT3_PRT18" , 0x11800A0000DB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
|
|
{"PIP_STAT3_PRT19" , 0x11800A0000E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
|
|
{"PIP_STAT3_PRT32" , 0x11800A0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
|
|
{"PIP_STAT3_PRT33" , 0x11800A0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
|
|
{"PIP_STAT3_PRT34" , 0x11800A00012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
|
|
{"PIP_STAT3_PRT35" , 0x11800A0001308ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
|
|
{"PIP_STAT3_PRT36" , 0x11800A0001358ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
|
|
{"PIP_STAT3_PRT37" , 0x11800A00013A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
|
|
{"PIP_STAT3_PRT38" , 0x11800A00013F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
|
|
{"PIP_STAT3_PRT39" , 0x11800A0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
|
|
{"PIP_STAT4_PRT0" , 0x11800A0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
|
|
{"PIP_STAT4_PRT1" , 0x11800A0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
|
|
{"PIP_STAT4_PRT2" , 0x11800A00008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
|
|
{"PIP_STAT4_PRT3" , 0x11800A0000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
|
|
{"PIP_STAT4_PRT16" , 0x11800A0000D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
|
|
{"PIP_STAT4_PRT17" , 0x11800A0000D70ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
|
|
{"PIP_STAT4_PRT18" , 0x11800A0000DC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
|
|
{"PIP_STAT4_PRT19" , 0x11800A0000E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
|
|
{"PIP_STAT4_PRT32" , 0x11800A0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
|
|
{"PIP_STAT4_PRT33" , 0x11800A0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
|
|
{"PIP_STAT4_PRT34" , 0x11800A00012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
|
|
{"PIP_STAT4_PRT35" , 0x11800A0001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
|
|
{"PIP_STAT4_PRT36" , 0x11800A0001360ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
|
|
{"PIP_STAT4_PRT37" , 0x11800A00013B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
|
|
{"PIP_STAT4_PRT38" , 0x11800A0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
|
|
{"PIP_STAT4_PRT39" , 0x11800A0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
|
|
{"PIP_STAT5_PRT0" , 0x11800A0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
|
|
{"PIP_STAT5_PRT1" , 0x11800A0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
|
|
{"PIP_STAT5_PRT2" , 0x11800A00008C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
|
|
{"PIP_STAT5_PRT3" , 0x11800A0000918ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
|
|
{"PIP_STAT5_PRT16" , 0x11800A0000D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
|
|
{"PIP_STAT5_PRT17" , 0x11800A0000D78ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
|
|
{"PIP_STAT5_PRT18" , 0x11800A0000DC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
|
|
{"PIP_STAT5_PRT19" , 0x11800A0000E18ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
|
|
{"PIP_STAT5_PRT32" , 0x11800A0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
|
|
{"PIP_STAT5_PRT33" , 0x11800A0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
|
|
{"PIP_STAT5_PRT34" , 0x11800A00012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
|
|
{"PIP_STAT5_PRT35" , 0x11800A0001318ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
|
|
{"PIP_STAT5_PRT36" , 0x11800A0001368ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
|
|
{"PIP_STAT5_PRT37" , 0x11800A00013B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
|
|
{"PIP_STAT5_PRT38" , 0x11800A0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
|
|
{"PIP_STAT5_PRT39" , 0x11800A0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
|
|
{"PIP_STAT6_PRT0" , 0x11800A0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
|
|
{"PIP_STAT6_PRT1" , 0x11800A0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
|
|
{"PIP_STAT6_PRT2" , 0x11800A00008D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
|
|
{"PIP_STAT6_PRT3" , 0x11800A0000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
|
|
{"PIP_STAT6_PRT16" , 0x11800A0000D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
|
|
{"PIP_STAT6_PRT17" , 0x11800A0000D80ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
|
|
{"PIP_STAT6_PRT18" , 0x11800A0000DD0ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
|
|
{"PIP_STAT6_PRT19" , 0x11800A0000E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
|
|
{"PIP_STAT6_PRT32" , 0x11800A0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
|
|
{"PIP_STAT6_PRT33" , 0x11800A0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
|
|
{"PIP_STAT6_PRT34" , 0x11800A00012D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
|
|
{"PIP_STAT6_PRT35" , 0x11800A0001320ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
|
|
{"PIP_STAT6_PRT36" , 0x11800A0001370ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
|
|
{"PIP_STAT6_PRT37" , 0x11800A00013C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
|
|
{"PIP_STAT6_PRT38" , 0x11800A0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
|
|
{"PIP_STAT6_PRT39" , 0x11800A0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
|
|
{"PIP_STAT7_PRT0" , 0x11800A0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_STAT7_PRT1" , 0x11800A0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_STAT7_PRT2" , 0x11800A00008D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_STAT7_PRT3" , 0x11800A0000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_STAT7_PRT16" , 0x11800A0000D38ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_STAT7_PRT17" , 0x11800A0000D88ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_STAT7_PRT18" , 0x11800A0000DD8ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_STAT7_PRT19" , 0x11800A0000E28ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_STAT7_PRT32" , 0x11800A0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_STAT7_PRT33" , 0x11800A0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_STAT7_PRT34" , 0x11800A00012D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_STAT7_PRT35" , 0x11800A0001328ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_STAT7_PRT36" , 0x11800A0001378ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_STAT7_PRT37" , 0x11800A00013C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_STAT7_PRT38" , 0x11800A0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_STAT7_PRT39" , 0x11800A0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_STAT8_PRT0" , 0x11800A0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_STAT8_PRT1" , 0x11800A0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_STAT8_PRT2" , 0x11800A00008E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_STAT8_PRT3" , 0x11800A0000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_STAT8_PRT16" , 0x11800A0000D40ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_STAT8_PRT17" , 0x11800A0000D90ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_STAT8_PRT18" , 0x11800A0000DE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_STAT8_PRT19" , 0x11800A0000E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_STAT8_PRT32" , 0x11800A0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_STAT8_PRT33" , 0x11800A0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_STAT8_PRT34" , 0x11800A00012E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_STAT8_PRT35" , 0x11800A0001330ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_STAT8_PRT36" , 0x11800A0001380ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_STAT8_PRT37" , 0x11800A00013D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_STAT8_PRT38" , 0x11800A0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_STAT8_PRT39" , 0x11800A0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_STAT9_PRT0" , 0x11800A0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_STAT9_PRT1" , 0x11800A0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_STAT9_PRT2" , 0x11800A00008E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_STAT9_PRT3" , 0x11800A0000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_STAT9_PRT16" , 0x11800A0000D48ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_STAT9_PRT17" , 0x11800A0000D98ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_STAT9_PRT18" , 0x11800A0000DE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_STAT9_PRT19" , 0x11800A0000E38ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_STAT9_PRT32" , 0x11800A0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_STAT9_PRT33" , 0x11800A0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_STAT9_PRT34" , 0x11800A00012E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_STAT9_PRT35" , 0x11800A0001338ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_STAT9_PRT36" , 0x11800A0001388ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_STAT9_PRT37" , 0x11800A00013D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_STAT9_PRT38" , 0x11800A0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_STAT9_PRT39" , 0x11800A0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_STAT_CTL" , 0x11800A0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
|
|
{"PIP_STAT_INB_ERRS0" , 0x11800A0001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
|
|
{"PIP_STAT_INB_ERRS1" , 0x11800A0001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
|
|
{"PIP_STAT_INB_ERRS2" , 0x11800A0001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
|
|
{"PIP_STAT_INB_ERRS3" , 0x11800A0001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
|
|
{"PIP_STAT_INB_ERRS16" , 0x11800A0001C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
|
|
{"PIP_STAT_INB_ERRS17" , 0x11800A0001C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
|
|
{"PIP_STAT_INB_ERRS18" , 0x11800A0001C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
|
|
{"PIP_STAT_INB_ERRS19" , 0x11800A0001C70ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
|
|
{"PIP_STAT_INB_ERRS32" , 0x11800A0001E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
|
|
{"PIP_STAT_INB_ERRS33" , 0x11800A0001E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
|
|
{"PIP_STAT_INB_ERRS34" , 0x11800A0001E50ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
|
|
{"PIP_STAT_INB_ERRS35" , 0x11800A0001E70ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
|
|
{"PIP_STAT_INB_ERRS36" , 0x11800A0001E90ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
|
|
{"PIP_STAT_INB_ERRS37" , 0x11800A0001EB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
|
|
{"PIP_STAT_INB_ERRS38" , 0x11800A0001ED0ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
|
|
{"PIP_STAT_INB_ERRS39" , 0x11800A0001EF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
|
|
{"PIP_STAT_INB_OCTS0" , 0x11800A0001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
|
|
{"PIP_STAT_INB_OCTS1" , 0x11800A0001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
|
|
{"PIP_STAT_INB_OCTS2" , 0x11800A0001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
|
|
{"PIP_STAT_INB_OCTS3" , 0x11800A0001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
|
|
{"PIP_STAT_INB_OCTS16" , 0x11800A0001C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
|
|
{"PIP_STAT_INB_OCTS17" , 0x11800A0001C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
|
|
{"PIP_STAT_INB_OCTS18" , 0x11800A0001C48ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
|
|
{"PIP_STAT_INB_OCTS19" , 0x11800A0001C68ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
|
|
{"PIP_STAT_INB_OCTS32" , 0x11800A0001E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
|
|
{"PIP_STAT_INB_OCTS33" , 0x11800A0001E28ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
|
|
{"PIP_STAT_INB_OCTS34" , 0x11800A0001E48ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
|
|
{"PIP_STAT_INB_OCTS35" , 0x11800A0001E68ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
|
|
{"PIP_STAT_INB_OCTS36" , 0x11800A0001E88ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
|
|
{"PIP_STAT_INB_OCTS37" , 0x11800A0001EA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
|
|
{"PIP_STAT_INB_OCTS38" , 0x11800A0001EC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
|
|
{"PIP_STAT_INB_OCTS39" , 0x11800A0001EE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
|
|
{"PIP_STAT_INB_PKTS0" , 0x11800A0001A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
|
|
{"PIP_STAT_INB_PKTS1" , 0x11800A0001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
|
|
{"PIP_STAT_INB_PKTS2" , 0x11800A0001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
|
|
{"PIP_STAT_INB_PKTS3" , 0x11800A0001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
|
|
{"PIP_STAT_INB_PKTS16" , 0x11800A0001C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
|
|
{"PIP_STAT_INB_PKTS17" , 0x11800A0001C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
|
|
{"PIP_STAT_INB_PKTS18" , 0x11800A0001C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
|
|
{"PIP_STAT_INB_PKTS19" , 0x11800A0001C60ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
|
|
{"PIP_STAT_INB_PKTS32" , 0x11800A0001E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
|
|
{"PIP_STAT_INB_PKTS33" , 0x11800A0001E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
|
|
{"PIP_STAT_INB_PKTS34" , 0x11800A0001E40ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
|
|
{"PIP_STAT_INB_PKTS35" , 0x11800A0001E60ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
|
|
{"PIP_STAT_INB_PKTS36" , 0x11800A0001E80ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
|
|
{"PIP_STAT_INB_PKTS37" , 0x11800A0001EA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
|
|
{"PIP_STAT_INB_PKTS38" , 0x11800A0001EC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
|
|
{"PIP_STAT_INB_PKTS39" , 0x11800A0001EE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
|
|
{"PIP_TAG_INC0" , 0x11800A0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC1" , 0x11800A0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC2" , 0x11800A0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC3" , 0x11800A0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC4" , 0x11800A0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC5" , 0x11800A0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC6" , 0x11800A0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC7" , 0x11800A0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC8" , 0x11800A0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC9" , 0x11800A0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC10" , 0x11800A0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC11" , 0x11800A0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC12" , 0x11800A0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC13" , 0x11800A0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC14" , 0x11800A0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC15" , 0x11800A0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC16" , 0x11800A0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC17" , 0x11800A0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC18" , 0x11800A0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC19" , 0x11800A0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC20" , 0x11800A00018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC21" , 0x11800A00018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC22" , 0x11800A00018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC23" , 0x11800A00018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC24" , 0x11800A00018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC25" , 0x11800A00018C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC26" , 0x11800A00018D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC27" , 0x11800A00018D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC28" , 0x11800A00018E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC29" , 0x11800A00018E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC30" , 0x11800A00018F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC31" , 0x11800A00018F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC32" , 0x11800A0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC33" , 0x11800A0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC34" , 0x11800A0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC35" , 0x11800A0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC36" , 0x11800A0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC37" , 0x11800A0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC38" , 0x11800A0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC39" , 0x11800A0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC40" , 0x11800A0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC41" , 0x11800A0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC42" , 0x11800A0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC43" , 0x11800A0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC44" , 0x11800A0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC45" , 0x11800A0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC46" , 0x11800A0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC47" , 0x11800A0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC48" , 0x11800A0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC49" , 0x11800A0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC50" , 0x11800A0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC51" , 0x11800A0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC52" , 0x11800A00019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC53" , 0x11800A00019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC54" , 0x11800A00019B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC55" , 0x11800A00019B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC56" , 0x11800A00019C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC57" , 0x11800A00019C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC58" , 0x11800A00019D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC59" , 0x11800A00019D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC60" , 0x11800A00019E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC61" , 0x11800A00019E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC62" , 0x11800A00019F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_INC63" , 0x11800A00019F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_TAG_MASK" , 0x11800A0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
|
|
{"PIP_TAG_SECRET" , 0x11800A0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
|
|
{"PIP_TODO_ENTRY" , 0x11800A0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
|
|
{"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
|
|
{"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
|
|
{"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
|
|
{"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
|
|
{"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
|
|
{"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
|
|
{"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
|
|
{"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
|
|
{"PKO_MEM_DEBUG14" , 0x1180050001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
|
|
{"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
|
|
{"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
|
|
{"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
|
|
{"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
|
|
{"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
|
|
{"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
|
|
{"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
|
|
{"PKO_MEM_PORT_PTRS" , 0x1180050001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
|
|
{"PKO_MEM_PORT_QOS" , 0x1180050001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
|
|
{"PKO_MEM_PORT_RATE0" , 0x1180050001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
|
|
{"PKO_MEM_PORT_RATE1" , 0x1180050001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
|
|
{"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
|
|
{"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
|
|
{"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
|
|
{"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
|
|
{"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
|
|
{"PKO_REG_DEBUG1" , 0x11800500000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 790},
|
|
{"PKO_REG_DEBUG2" , 0x11800500000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
|
|
{"PKO_REG_DEBUG3" , 0x11800500000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
|
|
{"PKO_REG_ENGINE_INFLIGHT" , 0x1180050000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
|
|
{"PKO_REG_ENGINE_THRESH" , 0x1180050000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
|
|
{"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 795},
|
|
{"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 796},
|
|
{"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 797},
|
|
{"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 798},
|
|
{"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 799},
|
|
{"PKO_REG_QUEUE_PTRS1" , 0x1180050000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 800},
|
|
{"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 801},
|
|
{"POW_BIST_STAT" , 0x16700000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 802},
|
|
{"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 803},
|
|
{"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 804},
|
|
{"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 805},
|
|
{"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 806},
|
|
{"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 806},
|
|
{"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 806},
|
|
{"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 806},
|
|
{"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 806},
|
|
{"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 806},
|
|
{"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 806},
|
|
{"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 806},
|
|
{"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 807},
|
|
{"POW_IQ_INT" , 0x1670000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 808},
|
|
{"POW_IQ_INT_EN" , 0x1670000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 809},
|
|
{"POW_IQ_THR0" , 0x16700000003A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 810},
|
|
{"POW_IQ_THR1" , 0x16700000003A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 810},
|
|
{"POW_IQ_THR2" , 0x16700000003B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 810},
|
|
{"POW_IQ_THR3" , 0x16700000003B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 810},
|
|
{"POW_IQ_THR4" , 0x16700000003C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 810},
|
|
{"POW_IQ_THR5" , 0x16700000003C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 810},
|
|
{"POW_IQ_THR6" , 0x16700000003D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 810},
|
|
{"POW_IQ_THR7" , 0x16700000003D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 810},
|
|
{"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 811},
|
|
{"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 812},
|
|
{"POW_PF_RST_MSK" , 0x1670000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 813},
|
|
{"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 814},
|
|
{"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 814},
|
|
{"POW_PP_GRP_MSK2" , 0x1670000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 814},
|
|
{"POW_PP_GRP_MSK3" , 0x1670000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 814},
|
|
{"POW_PP_GRP_MSK4" , 0x1670000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 814},
|
|
{"POW_PP_GRP_MSK5" , 0x1670000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 814},
|
|
{"POW_PP_GRP_MSK6" , 0x1670000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 814},
|
|
{"POW_PP_GRP_MSK7" , 0x1670000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 814},
|
|
{"POW_PP_GRP_MSK8" , 0x1670000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 814},
|
|
{"POW_PP_GRP_MSK9" , 0x1670000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 814},
|
|
{"POW_PP_GRP_MSK10" , 0x1670000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 814},
|
|
{"POW_PP_GRP_MSK11" , 0x1670000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 814},
|
|
{"POW_QOS_RND0" , 0x16700000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 815},
|
|
{"POW_QOS_RND1" , 0x16700000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 815},
|
|
{"POW_QOS_RND2" , 0x16700000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 815},
|
|
{"POW_QOS_RND3" , 0x16700000001D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 815},
|
|
{"POW_QOS_RND4" , 0x16700000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 815},
|
|
{"POW_QOS_RND5" , 0x16700000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 815},
|
|
{"POW_QOS_RND6" , 0x16700000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 815},
|
|
{"POW_QOS_RND7" , 0x16700000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 815},
|
|
{"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 816},
|
|
{"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 816},
|
|
{"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 816},
|
|
{"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 816},
|
|
{"POW_QOS_THR4" , 0x16700000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 816},
|
|
{"POW_QOS_THR5" , 0x16700000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 816},
|
|
{"POW_QOS_THR6" , 0x16700000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 816},
|
|
{"POW_QOS_THR7" , 0x16700000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 816},
|
|
{"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 817},
|
|
{"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 818},
|
|
{"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 819},
|
|
{"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 819},
|
|
{"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 819},
|
|
{"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 819},
|
|
{"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 819},
|
|
{"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 819},
|
|
{"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 819},
|
|
{"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 819},
|
|
{"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 820},
|
|
{"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
|
|
{"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
|
|
{"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
|
|
{"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
|
|
{"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
|
|
{"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
|
|
{"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
|
|
{"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
|
|
{"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
|
|
{"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
|
|
{"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
|
|
{"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
|
|
{"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
|
|
{"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
|
|
{"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
|
|
{"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
|
|
{"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 822},
|
|
{"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
|
|
{"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
|
|
{"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
|
|
{"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
|
|
{"POW_WQ_INT_THR4" , 0x16700000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
|
|
{"POW_WQ_INT_THR5" , 0x16700000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
|
|
{"POW_WQ_INT_THR6" , 0x16700000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
|
|
{"POW_WQ_INT_THR7" , 0x16700000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
|
|
{"POW_WQ_INT_THR8" , 0x16700000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
|
|
{"POW_WQ_INT_THR9" , 0x16700000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
|
|
{"POW_WQ_INT_THR10" , 0x16700000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
|
|
{"POW_WQ_INT_THR11" , 0x16700000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
|
|
{"POW_WQ_INT_THR12" , 0x16700000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
|
|
{"POW_WQ_INT_THR13" , 0x16700000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
|
|
{"POW_WQ_INT_THR14" , 0x16700000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
|
|
{"POW_WQ_INT_THR15" , 0x16700000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
|
|
{"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
|
|
{"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
|
|
{"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
|
|
{"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
|
|
{"POW_WS_PC4" , 0x16700000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
|
|
{"POW_WS_PC5" , 0x16700000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
|
|
{"POW_WS_PC6" , 0x16700000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
|
|
{"POW_WS_PC7" , 0x16700000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
|
|
{"POW_WS_PC8" , 0x16700000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
|
|
{"POW_WS_PC9" , 0x16700000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
|
|
{"POW_WS_PC10" , 0x16700000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
|
|
{"POW_WS_PC11" , 0x16700000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
|
|
{"POW_WS_PC12" , 0x16700000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
|
|
{"POW_WS_PC13" , 0x16700000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
|
|
{"POW_WS_PC14" , 0x16700000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
|
|
{"POW_WS_PC15" , 0x16700000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
|
|
{"RAD_MEM_DEBUG0" , 0x1180070001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
|
|
{"RAD_MEM_DEBUG1" , 0x1180070001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
|
|
{"RAD_MEM_DEBUG2" , 0x1180070001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
|
|
{"RAD_REG_BIST_RESULT" , 0x1180070000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
|
|
{"RAD_REG_CMD_BUF" , 0x1180070000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 829},
|
|
{"RAD_REG_CTL" , 0x1180070000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 830},
|
|
{"RAD_REG_DEBUG0" , 0x1180070000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 831},
|
|
{"RAD_REG_DEBUG1" , 0x1180070000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 832},
|
|
{"RAD_REG_DEBUG10" , 0x1180070000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 833},
|
|
{"RAD_REG_DEBUG11" , 0x1180070000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 834},
|
|
{"RAD_REG_DEBUG12" , 0x1180070000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 835},
|
|
{"RAD_REG_DEBUG2" , 0x1180070000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 836},
|
|
{"RAD_REG_DEBUG3" , 0x1180070000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 837},
|
|
{"RAD_REG_DEBUG4" , 0x1180070000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 838},
|
|
{"RAD_REG_DEBUG5" , 0x1180070000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
|
|
{"RAD_REG_DEBUG6" , 0x1180070000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
|
|
{"RAD_REG_DEBUG7" , 0x1180070000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
|
|
{"RAD_REG_DEBUG8" , 0x1180070000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
|
|
{"RAD_REG_DEBUG9" , 0x1180070000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
|
|
{"RAD_REG_ERROR" , 0x1180070000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 844},
|
|
{"RAD_REG_INT_MASK" , 0x1180070000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
|
|
{"RAD_REG_POLYNOMIAL" , 0x1180070000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
|
|
{"RAD_REG_READ_IDX" , 0x1180070000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
|
|
{"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
|
|
{"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 849},
|
|
{"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 850},
|
|
{"SMI1_CLK" , 0x1180000001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 850},
|
|
{"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 851},
|
|
{"SMI1_CMD" , 0x1180000001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 851},
|
|
{"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
|
|
{"SMI1_EN" , 0x1180000001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
|
|
{"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 853},
|
|
{"SMI1_RD_DAT" , 0x1180000001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 853},
|
|
{"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 854},
|
|
{"SMI1_WR_DAT" , 0x1180000001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 854},
|
|
{"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 855},
|
|
{"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 856},
|
|
{"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 857},
|
|
{"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 858},
|
|
{"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 859},
|
|
{"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 860},
|
|
{"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 861},
|
|
{"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 862},
|
|
{"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 863},
|
|
{"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 864},
|
|
{"TRA_BIST_STATUS" , 0x11800A8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 865},
|
|
{"TRA_CTL" , 0x11800A8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 866},
|
|
{"TRA_CYCLES_SINCE" , 0x11800A8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 867},
|
|
{"TRA_CYCLES_SINCE1" , 0x11800A8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 868},
|
|
{"TRA_FILT_ADR_ADR" , 0x11800A8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 869},
|
|
{"TRA_FILT_ADR_MSK" , 0x11800A8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 870},
|
|
{"TRA_FILT_CMD" , 0x11800A8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 871},
|
|
{"TRA_FILT_DID" , 0x11800A8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
|
|
{"TRA_FILT_SID" , 0x11800A8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 873},
|
|
{"TRA_INT_STATUS" , 0x11800A8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 874},
|
|
{"TRA_READ_DAT" , 0x11800A8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 875},
|
|
{"TRA_TRIG0_ADR_ADR" , 0x11800A8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 876},
|
|
{"TRA_TRIG0_ADR_MSK" , 0x11800A80000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 877},
|
|
{"TRA_TRIG0_CMD" , 0x11800A8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 878},
|
|
{"TRA_TRIG0_DID" , 0x11800A8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 879},
|
|
{"TRA_TRIG0_SID" , 0x11800A8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 880},
|
|
{"TRA_TRIG1_ADR_ADR" , 0x11800A80000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 881},
|
|
{"TRA_TRIG1_ADR_MSK" , 0x11800A80000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 882},
|
|
{"TRA_TRIG1_CMD" , 0x11800A80000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 883},
|
|
{"TRA_TRIG1_DID" , 0x11800A80000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 884},
|
|
{"TRA_TRIG1_SID" , 0x11800A80000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 885},
|
|
{"USBC0_DAINT" , 0x16F0010000818ull, CVMX_CSR_DB_TYPE_NCB, 32, 886},
|
|
{"USBC0_DAINTMSK" , 0x16F001000081Cull, CVMX_CSR_DB_TYPE_NCB, 32, 887},
|
|
{"USBC0_DCFG" , 0x16F0010000800ull, CVMX_CSR_DB_TYPE_NCB, 32, 888},
|
|
{"USBC0_DCTL" , 0x16F0010000804ull, CVMX_CSR_DB_TYPE_NCB, 32, 889},
|
|
{"USBC0_DIEPCTL000" , 0x16F0010000900ull, CVMX_CSR_DB_TYPE_NCB, 32, 890},
|
|
{"USBC0_DIEPCTL001" , 0x16F0010000920ull, CVMX_CSR_DB_TYPE_NCB, 32, 890},
|
|
{"USBC0_DIEPCTL002" , 0x16F0010000940ull, CVMX_CSR_DB_TYPE_NCB, 32, 890},
|
|
{"USBC0_DIEPCTL003" , 0x16F0010000960ull, CVMX_CSR_DB_TYPE_NCB, 32, 890},
|
|
{"USBC0_DIEPCTL004" , 0x16F0010000980ull, CVMX_CSR_DB_TYPE_NCB, 32, 890},
|
|
{"USBC0_DIEPINT000" , 0x16F0010000908ull, CVMX_CSR_DB_TYPE_NCB, 32, 891},
|
|
{"USBC0_DIEPINT001" , 0x16F0010000928ull, CVMX_CSR_DB_TYPE_NCB, 32, 891},
|
|
{"USBC0_DIEPINT002" , 0x16F0010000948ull, CVMX_CSR_DB_TYPE_NCB, 32, 891},
|
|
{"USBC0_DIEPINT003" , 0x16F0010000968ull, CVMX_CSR_DB_TYPE_NCB, 32, 891},
|
|
{"USBC0_DIEPINT004" , 0x16F0010000988ull, CVMX_CSR_DB_TYPE_NCB, 32, 891},
|
|
{"USBC0_DIEPMSK" , 0x16F0010000810ull, CVMX_CSR_DB_TYPE_NCB, 32, 892},
|
|
{"USBC0_DIEPTSIZ000" , 0x16F0010000910ull, CVMX_CSR_DB_TYPE_NCB, 32, 893},
|
|
{"USBC0_DIEPTSIZ001" , 0x16F0010000930ull, CVMX_CSR_DB_TYPE_NCB, 32, 893},
|
|
{"USBC0_DIEPTSIZ002" , 0x16F0010000950ull, CVMX_CSR_DB_TYPE_NCB, 32, 893},
|
|
{"USBC0_DIEPTSIZ003" , 0x16F0010000970ull, CVMX_CSR_DB_TYPE_NCB, 32, 893},
|
|
{"USBC0_DIEPTSIZ004" , 0x16F0010000990ull, CVMX_CSR_DB_TYPE_NCB, 32, 893},
|
|
{"USBC0_DOEPCTL000" , 0x16F0010000B00ull, CVMX_CSR_DB_TYPE_NCB, 32, 894},
|
|
{"USBC0_DOEPCTL001" , 0x16F0010000B20ull, CVMX_CSR_DB_TYPE_NCB, 32, 894},
|
|
{"USBC0_DOEPCTL002" , 0x16F0010000B40ull, CVMX_CSR_DB_TYPE_NCB, 32, 894},
|
|
{"USBC0_DOEPCTL003" , 0x16F0010000B60ull, CVMX_CSR_DB_TYPE_NCB, 32, 894},
|
|
{"USBC0_DOEPCTL004" , 0x16F0010000B80ull, CVMX_CSR_DB_TYPE_NCB, 32, 894},
|
|
{"USBC0_DOEPINT000" , 0x16F0010000B08ull, CVMX_CSR_DB_TYPE_NCB, 32, 895},
|
|
{"USBC0_DOEPINT001" , 0x16F0010000B28ull, CVMX_CSR_DB_TYPE_NCB, 32, 895},
|
|
{"USBC0_DOEPINT002" , 0x16F0010000B48ull, CVMX_CSR_DB_TYPE_NCB, 32, 895},
|
|
{"USBC0_DOEPINT003" , 0x16F0010000B68ull, CVMX_CSR_DB_TYPE_NCB, 32, 895},
|
|
{"USBC0_DOEPINT004" , 0x16F0010000B88ull, CVMX_CSR_DB_TYPE_NCB, 32, 895},
|
|
{"USBC0_DOEPMSK" , 0x16F0010000814ull, CVMX_CSR_DB_TYPE_NCB, 32, 896},
|
|
{"USBC0_DOEPTSIZ000" , 0x16F0010000B10ull, CVMX_CSR_DB_TYPE_NCB, 32, 897},
|
|
{"USBC0_DOEPTSIZ001" , 0x16F0010000B30ull, CVMX_CSR_DB_TYPE_NCB, 32, 897},
|
|
{"USBC0_DOEPTSIZ002" , 0x16F0010000B50ull, CVMX_CSR_DB_TYPE_NCB, 32, 897},
|
|
{"USBC0_DOEPTSIZ003" , 0x16F0010000B70ull, CVMX_CSR_DB_TYPE_NCB, 32, 897},
|
|
{"USBC0_DOEPTSIZ004" , 0x16F0010000B90ull, CVMX_CSR_DB_TYPE_NCB, 32, 897},
|
|
{"USBC0_DPTXFSIZ001" , 0x16F0010000104ull, CVMX_CSR_DB_TYPE_NCB, 32, 898},
|
|
{"USBC0_DPTXFSIZ002" , 0x16F0010000108ull, CVMX_CSR_DB_TYPE_NCB, 32, 898},
|
|
{"USBC0_DPTXFSIZ003" , 0x16F001000010Cull, CVMX_CSR_DB_TYPE_NCB, 32, 898},
|
|
{"USBC0_DPTXFSIZ004" , 0x16F0010000110ull, CVMX_CSR_DB_TYPE_NCB, 32, 898},
|
|
{"USBC0_DSTS" , 0x16F0010000808ull, CVMX_CSR_DB_TYPE_NCB, 32, 899},
|
|
{"USBC0_DTKNQR1" , 0x16F0010000820ull, CVMX_CSR_DB_TYPE_NCB, 32, 900},
|
|
{"USBC0_DTKNQR2" , 0x16F0010000824ull, CVMX_CSR_DB_TYPE_NCB, 32, 901},
|
|
{"USBC0_DTKNQR3" , 0x16F0010000830ull, CVMX_CSR_DB_TYPE_NCB, 32, 902},
|
|
{"USBC0_DTKNQR4" , 0x16F0010000834ull, CVMX_CSR_DB_TYPE_NCB, 32, 903},
|
|
{"USBC0_GAHBCFG" , 0x16F0010000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 904},
|
|
{"USBC0_GHWCFG1" , 0x16F0010000044ull, CVMX_CSR_DB_TYPE_NCB, 32, 905},
|
|
{"USBC0_GHWCFG2" , 0x16F0010000048ull, CVMX_CSR_DB_TYPE_NCB, 32, 906},
|
|
{"USBC0_GHWCFG3" , 0x16F001000004Cull, CVMX_CSR_DB_TYPE_NCB, 32, 907},
|
|
{"USBC0_GHWCFG4" , 0x16F0010000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 908},
|
|
{"USBC0_GINTMSK" , 0x16F0010000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 909},
|
|
{"USBC0_GINTSTS" , 0x16F0010000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 910},
|
|
{"USBC0_GNPTXFSIZ" , 0x16F0010000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 911},
|
|
{"USBC0_GNPTXSTS" , 0x16F001000002Cull, CVMX_CSR_DB_TYPE_NCB, 32, 912},
|
|
{"USBC0_GOTGCTL" , 0x16F0010000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 913},
|
|
{"USBC0_GOTGINT" , 0x16F0010000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 914},
|
|
{"USBC0_GRSTCTL" , 0x16F0010000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 915},
|
|
{"USBC0_GRXFSIZ" , 0x16F0010000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 916},
|
|
{"USBC0_GRXSTSPD" , 0x16F0010040020ull, CVMX_CSR_DB_TYPE_NCB, 32, 917},
|
|
{"USBC0_GRXSTSPH" , 0x16F0010000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 918},
|
|
{"USBC0_GRXSTSRD" , 0x16F001004001Cull, CVMX_CSR_DB_TYPE_NCB, 32, 919},
|
|
{"USBC0_GRXSTSRH" , 0x16F001000001Cull, CVMX_CSR_DB_TYPE_NCB, 32, 920},
|
|
{"USBC0_GSNPSID" , 0x16F0010000040ull, CVMX_CSR_DB_TYPE_NCB, 32, 921},
|
|
{"USBC0_GUSBCFG" , 0x16F001000000Cull, CVMX_CSR_DB_TYPE_NCB, 32, 922},
|
|
{"USBC0_HAINT" , 0x16F0010000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 923},
|
|
{"USBC0_HAINTMSK" , 0x16F0010000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 924},
|
|
{"USBC0_HCCHAR000" , 0x16F0010000500ull, CVMX_CSR_DB_TYPE_NCB, 32, 925},
|
|
{"USBC0_HCCHAR001" , 0x16F0010000520ull, CVMX_CSR_DB_TYPE_NCB, 32, 925},
|
|
{"USBC0_HCCHAR002" , 0x16F0010000540ull, CVMX_CSR_DB_TYPE_NCB, 32, 925},
|
|
{"USBC0_HCCHAR003" , 0x16F0010000560ull, CVMX_CSR_DB_TYPE_NCB, 32, 925},
|
|
{"USBC0_HCCHAR004" , 0x16F0010000580ull, CVMX_CSR_DB_TYPE_NCB, 32, 925},
|
|
{"USBC0_HCCHAR005" , 0x16F00100005A0ull, CVMX_CSR_DB_TYPE_NCB, 32, 925},
|
|
{"USBC0_HCCHAR006" , 0x16F00100005C0ull, CVMX_CSR_DB_TYPE_NCB, 32, 925},
|
|
{"USBC0_HCCHAR007" , 0x16F00100005E0ull, CVMX_CSR_DB_TYPE_NCB, 32, 925},
|
|
{"USBC0_HCFG" , 0x16F0010000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 926},
|
|
{"USBC0_HCINT000" , 0x16F0010000508ull, CVMX_CSR_DB_TYPE_NCB, 32, 927},
|
|
{"USBC0_HCINT001" , 0x16F0010000528ull, CVMX_CSR_DB_TYPE_NCB, 32, 927},
|
|
{"USBC0_HCINT002" , 0x16F0010000548ull, CVMX_CSR_DB_TYPE_NCB, 32, 927},
|
|
{"USBC0_HCINT003" , 0x16F0010000568ull, CVMX_CSR_DB_TYPE_NCB, 32, 927},
|
|
{"USBC0_HCINT004" , 0x16F0010000588ull, CVMX_CSR_DB_TYPE_NCB, 32, 927},
|
|
{"USBC0_HCINT005" , 0x16F00100005A8ull, CVMX_CSR_DB_TYPE_NCB, 32, 927},
|
|
{"USBC0_HCINT006" , 0x16F00100005C8ull, CVMX_CSR_DB_TYPE_NCB, 32, 927},
|
|
{"USBC0_HCINT007" , 0x16F00100005E8ull, CVMX_CSR_DB_TYPE_NCB, 32, 927},
|
|
{"USBC0_HCINTMSK000" , 0x16F001000050Cull, CVMX_CSR_DB_TYPE_NCB, 32, 928},
|
|
{"USBC0_HCINTMSK001" , 0x16F001000052Cull, CVMX_CSR_DB_TYPE_NCB, 32, 928},
|
|
{"USBC0_HCINTMSK002" , 0x16F001000054Cull, CVMX_CSR_DB_TYPE_NCB, 32, 928},
|
|
{"USBC0_HCINTMSK003" , 0x16F001000056Cull, CVMX_CSR_DB_TYPE_NCB, 32, 928},
|
|
{"USBC0_HCINTMSK004" , 0x16F001000058Cull, CVMX_CSR_DB_TYPE_NCB, 32, 928},
|
|
{"USBC0_HCINTMSK005" , 0x16F00100005ACull, CVMX_CSR_DB_TYPE_NCB, 32, 928},
|
|
{"USBC0_HCINTMSK006" , 0x16F00100005CCull, CVMX_CSR_DB_TYPE_NCB, 32, 928},
|
|
{"USBC0_HCINTMSK007" , 0x16F00100005ECull, CVMX_CSR_DB_TYPE_NCB, 32, 928},
|
|
{"USBC0_HCSPLT000" , 0x16F0010000504ull, CVMX_CSR_DB_TYPE_NCB, 32, 929},
|
|
{"USBC0_HCSPLT001" , 0x16F0010000524ull, CVMX_CSR_DB_TYPE_NCB, 32, 929},
|
|
{"USBC0_HCSPLT002" , 0x16F0010000544ull, CVMX_CSR_DB_TYPE_NCB, 32, 929},
|
|
{"USBC0_HCSPLT003" , 0x16F0010000564ull, CVMX_CSR_DB_TYPE_NCB, 32, 929},
|
|
{"USBC0_HCSPLT004" , 0x16F0010000584ull, CVMX_CSR_DB_TYPE_NCB, 32, 929},
|
|
{"USBC0_HCSPLT005" , 0x16F00100005A4ull, CVMX_CSR_DB_TYPE_NCB, 32, 929},
|
|
{"USBC0_HCSPLT006" , 0x16F00100005C4ull, CVMX_CSR_DB_TYPE_NCB, 32, 929},
|
|
{"USBC0_HCSPLT007" , 0x16F00100005E4ull, CVMX_CSR_DB_TYPE_NCB, 32, 929},
|
|
{"USBC0_HCTSIZ000" , 0x16F0010000510ull, CVMX_CSR_DB_TYPE_NCB, 32, 930},
|
|
{"USBC0_HCTSIZ001" , 0x16F0010000530ull, CVMX_CSR_DB_TYPE_NCB, 32, 930},
|
|
{"USBC0_HCTSIZ002" , 0x16F0010000550ull, CVMX_CSR_DB_TYPE_NCB, 32, 930},
|
|
{"USBC0_HCTSIZ003" , 0x16F0010000570ull, CVMX_CSR_DB_TYPE_NCB, 32, 930},
|
|
{"USBC0_HCTSIZ004" , 0x16F0010000590ull, CVMX_CSR_DB_TYPE_NCB, 32, 930},
|
|
{"USBC0_HCTSIZ005" , 0x16F00100005B0ull, CVMX_CSR_DB_TYPE_NCB, 32, 930},
|
|
{"USBC0_HCTSIZ006" , 0x16F00100005D0ull, CVMX_CSR_DB_TYPE_NCB, 32, 930},
|
|
{"USBC0_HCTSIZ007" , 0x16F00100005F0ull, CVMX_CSR_DB_TYPE_NCB, 32, 930},
|
|
{"USBC0_HFIR" , 0x16F0010000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 931},
|
|
{"USBC0_HFNUM" , 0x16F0010000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 932},
|
|
{"USBC0_HPRT" , 0x16F0010000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 933},
|
|
{"USBC0_HPTXFSIZ" , 0x16F0010000100ull, CVMX_CSR_DB_TYPE_NCB, 32, 934},
|
|
{"USBC0_HPTXSTS" , 0x16F0010000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 935},
|
|
{"USBC0_NPTXDFIFO000" , 0x16F0010001000ull, CVMX_CSR_DB_TYPE_NCB, 32, 936},
|
|
{"USBC0_NPTXDFIFO001" , 0x16F0010002000ull, CVMX_CSR_DB_TYPE_NCB, 32, 936},
|
|
{"USBC0_NPTXDFIFO002" , 0x16F0010003000ull, CVMX_CSR_DB_TYPE_NCB, 32, 936},
|
|
{"USBC0_NPTXDFIFO003" , 0x16F0010004000ull, CVMX_CSR_DB_TYPE_NCB, 32, 936},
|
|
{"USBC0_NPTXDFIFO004" , 0x16F0010005000ull, CVMX_CSR_DB_TYPE_NCB, 32, 936},
|
|
{"USBC0_NPTXDFIFO005" , 0x16F0010006000ull, CVMX_CSR_DB_TYPE_NCB, 32, 936},
|
|
{"USBC0_NPTXDFIFO006" , 0x16F0010007000ull, CVMX_CSR_DB_TYPE_NCB, 32, 936},
|
|
{"USBC0_NPTXDFIFO007" , 0x16F0010008000ull, CVMX_CSR_DB_TYPE_NCB, 32, 936},
|
|
{"USBC0_PCGCCTL" , 0x16F0010000E00ull, CVMX_CSR_DB_TYPE_NCB, 32, 937},
|
|
{"USBN0_BIST_STATUS" , 0x11800680007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 938},
|
|
{"USBN0_CLK_CTL" , 0x1180068000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 939},
|
|
{"USBN0_CTL_STATUS" , 0x16F0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 940},
|
|
{"USBN0_DMA0_INB_CHN0" , 0x16F0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 941},
|
|
{"USBN0_DMA0_INB_CHN1" , 0x16F0000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 942},
|
|
{"USBN0_DMA0_INB_CHN2" , 0x16F0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 943},
|
|
{"USBN0_DMA0_INB_CHN3" , 0x16F0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 944},
|
|
{"USBN0_DMA0_INB_CHN4" , 0x16F0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 945},
|
|
{"USBN0_DMA0_INB_CHN5" , 0x16F0000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 946},
|
|
{"USBN0_DMA0_INB_CHN6" , 0x16F0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 947},
|
|
{"USBN0_DMA0_INB_CHN7" , 0x16F0000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 948},
|
|
{"USBN0_DMA0_OUTB_CHN0" , 0x16F0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 949},
|
|
{"USBN0_DMA0_OUTB_CHN1" , 0x16F0000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 950},
|
|
{"USBN0_DMA0_OUTB_CHN2" , 0x16F0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 951},
|
|
{"USBN0_DMA0_OUTB_CHN3" , 0x16F0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 952},
|
|
{"USBN0_DMA0_OUTB_CHN4" , 0x16F0000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 953},
|
|
{"USBN0_DMA0_OUTB_CHN5" , 0x16F0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 954},
|
|
{"USBN0_DMA0_OUTB_CHN6" , 0x16F0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 955},
|
|
{"USBN0_DMA0_OUTB_CHN7" , 0x16F0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 956},
|
|
{"USBN0_DMA_TEST" , 0x16F0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 957},
|
|
{"USBN0_INT_ENB" , 0x1180068000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 958},
|
|
{"USBN0_INT_SUM" , 0x1180068000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 959},
|
|
{"USBN0_USBP_CTL_STATUS" , 0x1180068000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 960},
|
|
{"ZIP_CMD_BIST_RESULT" , 0x1180038000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 961},
|
|
{"ZIP_CMD_BUF" , 0x1180038000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 962},
|
|
{"ZIP_CMD_CTL" , 0x1180038000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 963},
|
|
{"ZIP_CONSTANTS" , 0x11800380000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 964},
|
|
{"ZIP_DEBUG0" , 0x1180038000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 965},
|
|
{"ZIP_ERROR" , 0x1180038000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 966},
|
|
{"ZIP_INT_MASK" , 0x1180038000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 967},
|
|
{NULL,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
|
|
/* name , bit, width, csr, type, rst un, typ un, reset, typical */
|
|
{"RESERVED_0_1" , 0, 2, 0, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OUT_OVR" , 2, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_21" , 3, 19, 0, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LOSTSTAT" , 22, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_25" , 23, 3, 0, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STATOVR" , 26, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_31" , 27, 5, 0, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OVRFLW" , 32, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXPOP" , 33, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXPSH" , 34, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_35_63" , 35, 29, 0, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 10, 1, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 1, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 5, 2, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 2, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL" , 8, 5, 2, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_13_15" , 13, 3, 2, "RAZ", 1, 1, 0, 0},
|
|
{"BYP_EN" , 16, 1, 2, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 2, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 3, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 1, 1, 3, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 3, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 4, "R/W", 0, 1, 0ull, 0},
|
|
{"SPEED" , 1, 1, 4, "RO", 0, 0, 0ull, 0ull},
|
|
{"DUPLEX" , 2, 1, 4, "R/W", 0, 1, 1ull, 0},
|
|
{"SLOTTIME" , 3, 1, 4, "RO", 0, 0, 0ull, 0ull},
|
|
{"RX_EN" , 4, 1, 4, "R/W", 0, 1, 0ull, 0},
|
|
{"TX_EN" , 5, 1, 4, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 4, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 64, 5, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 6, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 7, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 8, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 9, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 10, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 0, 8, 11, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 11, "RAZ", 1, 1, 0, 0},
|
|
{"BCST" , 0, 1, 12, "R/W", 0, 1, 1ull, 0},
|
|
{"MCST" , 1, 2, 12, "R/W", 0, 1, 0ull, 0},
|
|
{"CAM_MODE" , 3, 1, 12, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 12, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 5, 13, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_5_63" , 5, 59, 13, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_1" , 1, 1, 14, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 2, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"JABBER" , 3, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCSERR" , 4, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"ALNERR" , 5, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"LENERR" , 6, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RCVERR" , 7, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SKPERR" , 8, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_9_63" , 9, 55, 14, "RAZ", 1, 1, 0, 0},
|
|
{"PRE_CHK" , 0, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PRE_STRP" , 1, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_DRP" , 2, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_BCK" , 3, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_MCST" , 4, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_SMAC" , 5, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRE_FREE" , 6, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"VLAN_LEN" , 7, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PAD_LEN" , 8, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRE_ALIGN" , 9, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_10_63" , 10, 54, 15, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 16, 16, "R/W", 0, 0, 1536ull, 1536ull},
|
|
{"RESERVED_16_63" , 16, 48, 16, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 16, 17, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_16_63" , 16, 48, 17, "RAZ", 1, 1, 0, 0},
|
|
{"IFG" , 0, 4, 18, "R/W", 0, 0, 12ull, 12ull},
|
|
{"RESERVED_4_63" , 4, 60, 18, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 19, "RAZ", 1, 1, 0, 0},
|
|
{"MAXERR" , 2, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"JABBER" , 3, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ALNERR" , 5, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 6, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RCVERR" , 7, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 19, "RAZ", 1, 1, 0, 0},
|
|
{"OVRERR" , 10, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_18" , 16, 3, 19, "RAZ", 1, 1, 0, 0},
|
|
{"PAUSE_DRP" , 19, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 19, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 20, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 2, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"JABBER" , 3, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ALNERR" , 5, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 6, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RCVERR" , 7, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 20, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OVRERR" , 10, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_18" , 16, 3, 20, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PAUSE_DRP" , 19, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 20, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 21, "R/W", 0, 0, 10240ull, 10240ull},
|
|
{"RESERVED_16_63" , 16, 48, 21, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 16, 22, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 22, "RAZ", 1, 1, 0, 0},
|
|
{"RD_CLR" , 0, 1, 23, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 23, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 24, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 24, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 25, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 25, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 26, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 26, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 27, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 27, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 28, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 28, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 29, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 29, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 30, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 30, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 31, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 31, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 32, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 32, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 7, 33, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 33, "RAZ", 1, 1, 0, 0},
|
|
{"FCSSEL" , 8, 1, 33, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 33, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 34, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_6_63" , 6, 58, 34, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 35, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_6_63" , 6, 58, 35, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 9, 36, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_9_63" , 9, 55, 36, "RAZ", 1, 1, 0, 0},
|
|
{"COMMIT" , 0, 1, 37, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_15" , 1, 15, 37, "RAZ", 1, 1, 0, 0},
|
|
{"DROP" , 16, 1, 37, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 37, "RAZ", 1, 1, 0, 0},
|
|
{"RX" , 0, 1, 38, "RC", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_3" , 1, 3, 38, "RAZ", 1, 1, 0, 0},
|
|
{"TX" , 4, 1, 38, "RC", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 38, "RAZ", 1, 1, 0, 0},
|
|
{"SMAC" , 0, 48, 39, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 39, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 40, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP" , 16, 1, 40, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 40, "RAZ", 1, 1, 0, 0},
|
|
{"PREAMBLE" , 0, 1, 41, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PAD" , 1, 1, 41, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCS" , 2, 1, 41, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FORCE_FCS" , 3, 1, 41, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 41, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL_EN" , 0, 1, 42, "R/W", 0, 0, 1ull, 1ull},
|
|
{"XSDEF_EN" , 1, 1, 42, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 42, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_SIZE" , 0, 8, 43, "R/W", 0, 0, 59ull, 59ull},
|
|
{"RESERVED_8_63" , 8, 56, 43, "RAZ", 1, 1, 0, 0},
|
|
{"INTERVAL" , 0, 16, 44, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 44, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 45, "R/W", 0, 1, 96ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 45, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 46, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_16_63" , 16, 48, 46, "RAZ", 1, 1, 0, 0},
|
|
{"SEND" , 0, 1, 47, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 47, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 48, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 48, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL" , 0, 32, 49, "RC/W", 0, 1, 0ull, 0},
|
|
{"XSDEF" , 32, 32, 49, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCOL" , 0, 32, 50, "RC/W", 0, 1, 0ull, 0},
|
|
{"SCOL" , 32, 32, 50, "RC/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 51, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 51, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 52, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 52, "RAZ", 1, 1, 0, 0},
|
|
{"HIST0" , 0, 32, 53, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST1" , 32, 32, 53, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST2" , 0, 32, 54, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST3" , 32, 32, 54, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST4" , 0, 32, 55, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST5" , 32, 32, 55, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST6" , 0, 32, 56, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST7" , 32, 32, 56, "RC/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 0, 32, 57, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 32, 32, 57, "RC/W", 0, 1, 0ull, 0},
|
|
{"CTL" , 0, 32, 58, "RC/W", 0, 1, 0ull, 0},
|
|
{"UNDFLW" , 32, 32, 58, "RC/W", 0, 1, 0ull, 0},
|
|
{"RD_CLR" , 0, 1, 59, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 59, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 6, 60, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_6_63" , 6, 58, 60, "RAZ", 1, 1, 0, 0},
|
|
{"BP" , 0, 1, 61, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 61, "RAZ", 1, 1, 0, 0},
|
|
{"LIMIT" , 0, 5, 62, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_5_63" , 5, 59, 62, "RAZ", 1, 1, 0, 0},
|
|
{"IFG1" , 0, 4, 63, "R/W", 0, 1, 8ull, 0},
|
|
{"IFG2" , 4, 4, 63, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 63, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 64, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 1, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_7" , 3, 5, 64, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 1, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 64, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 1, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 64, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LATE_COL" , 16, 1, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 64, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PKO_NXA" , 0, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 65, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_7" , 3, 5, 65, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 65, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 65, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LATE_COL" , 16, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 65, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"JAM" , 0, 8, 66, "R/W", 0, 1, 238ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 66, "RAZ", 1, 1, 0, 0},
|
|
{"LFSR" , 0, 16, 67, "R/W", 0, 1, 65535ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 67, "RAZ", 1, 1, 0, 0},
|
|
{"IGN_FULL" , 0, 1, 68, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_3" , 1, 3, 68, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"BP" , 4, 1, 68, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_7" , 5, 3, 68, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EN" , 8, 1, 68, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 68, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DMAC" , 0, 48, 69, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
|
|
{"RESERVED_48_63" , 48, 16, 69, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 70, "R/W", 0, 0, 34824ull, 34824ull},
|
|
{"RESERVED_16_63" , 16, 48, 70, "RAZ", 1, 1, 0, 0},
|
|
{"BIST" , 0, 4, 71, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 71, "RAZ", 1, 1, 0, 0},
|
|
{"DINT" , 0, 12, 72, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 72, "RAZ", 1, 1, 0, 0},
|
|
{"FUSE" , 0, 12, 73, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_12_63" , 12, 52, 73, "RAZ", 1, 1, 0, 0},
|
|
{"GSTOP" , 0, 1, 74, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 74, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 75, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_57_58" , 57, 2, 75, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TWSI2" , 59, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POWIQ" , 60, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPDPPTHR" , 61, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MII" , 62, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BOOTDMA" , 63, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WORKQ" , 0, 16, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 76, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_57_58" , 57, 2, 76, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TWSI2" , 59, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"POWIQ" , 60, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IPDPPTHR" , 61, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MII" , 62, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BOOTDMA" , 63, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WORKQ" , 0, 16, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 77, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_57_58" , 57, 2, 77, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TWSI2" , 59, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"POWIQ" , 60, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"IPDPPTHR" , 61, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"MII" , 62, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"BOOTDMA" , 63, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"WDOG" , 0, 12, 78, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 78, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 12, 79, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 79, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 12, 80, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 80, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 81, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_57_58" , 57, 2, 81, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TWSI2" , 59, 1, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POWIQ" , 60, 1, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPDPPTHR" , 61, 1, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MII" , 62, 1, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BOOTDMA" , 63, 1, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WORKQ" , 0, 16, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 82, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_57_58" , 57, 2, 82, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TWSI2" , 59, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"POWIQ" , 60, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IPDPPTHR" , 61, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MII" , 62, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BOOTDMA" , 63, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WORKQ" , 0, 16, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 83, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_57_58" , 57, 2, 83, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TWSI2" , 59, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"POWIQ" , 60, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"IPDPPTHR" , 61, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"MII" , 62, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"BOOTDMA" , 63, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"WDOG" , 0, 12, 84, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 84, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 12, 85, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 85, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 12, 86, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 86, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"WDOG_SUM" , 44, 1, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"TWSI" , 45, 1, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 87, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 87, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_57_58" , 57, 2, 87, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TWSI2" , 59, 1, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"POWIQ" , 60, 1, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPDPPTHR" , 61, 1, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"MII" , 62, 1, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"BOOTDMA" , 63, 1, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"WORKQ" , 0, 16, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"WDOG_SUM" , 44, 1, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"TWSI" , 45, 1, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 2, 88, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 88, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KEY_ZERO" , 51, 1, 88, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 88, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_57_58" , 57, 2, 88, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TWSI2" , 59, 1, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"POWIQ" , 60, 1, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPDPPTHR" , 61, 1, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"MII" , 62, 1, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"BOOTDMA" , 63, 1, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"WDOG" , 0, 12, 89, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 89, "RAZ", 1, 1, 0, 0},
|
|
{"BITS" , 0, 32, 90, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 90, "RAZ", 1, 1, 0, 0},
|
|
{"BITS" , 0, 32, 91, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 91, "RAZ", 1, 1, 0, 0},
|
|
{"NMI" , 0, 12, 92, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 92, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 0, 2, 93, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 93, "RAZ", 1, 1, 0, 0},
|
|
{"PPDBG" , 0, 12, 94, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 94, "RAZ", 1, 1, 0, 0},
|
|
{"POKE" , 0, 64, 95, "RAZ", 1, 1, 0, 0},
|
|
{"RST0" , 0, 1, 96, "R/W", 1, 1, 0, 0},
|
|
{"RST" , 1, 11, 96, "R/W", 0, 0, 32767ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 96, "RAZ", 1, 1, 0, 0},
|
|
{"QLM_DCOK" , 0, 4, 97, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 97, "RAZ", 1, 1, 0, 0},
|
|
{"BYPASS" , 0, 4, 98, "R/W", 0, 1, 0ull, 0},
|
|
{"MUX_SEL" , 4, 2, 98, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_7" , 6, 2, 98, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_DIV" , 8, 3, 98, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_11_63" , 11, 53, 98, "RAZ", 1, 1, 0, 0},
|
|
{"SHFT_REG" , 0, 32, 99, "R/W", 0, 1, 0ull, 0},
|
|
{"SHFT_CNT" , 32, 5, 99, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_37_39" , 37, 3, 99, "RAZ", 1, 1, 0, 0},
|
|
{"SELECT" , 40, 4, 99, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_60" , 44, 17, 99, "RAZ", 1, 1, 0, 0},
|
|
{"UPDATE" , 61, 1, 99, "R/W", 0, 1, 0ull, 0},
|
|
{"SHIFT" , 62, 1, 99, "R/W", 0, 1, 0ull, 0},
|
|
{"CAPTURE" , 63, 1, 99, "R/W", 0, 1, 0ull, 0},
|
|
{"SOFT_BIST" , 0, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 100, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_PRST" , 0, 1, 101, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 101, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_PRST" , 0, 1, 102, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 102, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_RST" , 0, 1, 103, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 103, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 36, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ONE_SHOT" , 36, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 104, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 0, 2, 105, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STATE" , 2, 2, 105, "RO", 0, 0, 0ull, 0ull},
|
|
{"LEN" , 4, 16, 105, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 20, 24, 105, "RO", 0, 0, 0ull, 0ull},
|
|
{"DSTOP" , 44, 1, 105, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GSTOPEN" , 45, 1, 105, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_46_63" , 46, 18, 105, "RAZ", 1, 1, 0, 0},
|
|
{"FDR" , 0, 1, 106, "RO", 0, 0, 0ull, 0ull},
|
|
{"FFR" , 1, 1, 106, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPF1" , 2, 1, 106, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPF0" , 3, 1, 106, "RO", 0, 0, 0ull, 0ull},
|
|
{"FRD" , 4, 1, 106, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 106, "RAZ", 1, 1, 0, 0},
|
|
{"MEM0_ERR" , 0, 7, 107, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM1_ERR" , 7, 7, 107, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 14, 1, 107, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USE_STT" , 15, 1, 107, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USE_LDT" , 16, 1, 107, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 17, 1, 107, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 107, "RAZ", 1, 1, 0, 0},
|
|
{"FPF_RD" , 0, 11, 108, "R/W", 0, 0, 64ull, 0ull},
|
|
{"FPF_WR" , 11, 11, 108, "R/W", 0, 0, 196ull, 0ull},
|
|
{"RESERVED_22_63" , 22, 42, 108, "RAZ", 1, 1, 0, 0},
|
|
{"FPF_SIZ" , 0, 11, 109, "R/W", 0, 0, 256ull, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 109, "RAZ", 1, 1, 0, 0},
|
|
{"FPF_RD" , 0, 12, 110, "R/W", 0, 0, 64ull, 0ull},
|
|
{"FPF_WR" , 12, 12, 110, "R/W", 0, 0, 196ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 110, "RAZ", 1, 1, 0, 0},
|
|
{"FPF_SIZ" , 0, 12, 111, "R/W", 0, 0, 256ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 111, "RAZ", 1, 1, 0, 0},
|
|
{"FED0_SBE" , 0, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED0_DBE" , 1, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED1_SBE" , 2, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED1_DBE" , 3, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_UND" , 4, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_COFF" , 5, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_PERR" , 6, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_UND" , 7, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_COFF" , 8, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_PERR" , 9, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_UND" , 10, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_COFF" , 11, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_PERR" , 12, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_UND" , 13, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_COFF" , 14, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_PERR" , 15, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_UND" , 16, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_COFF" , 17, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_PERR" , 18, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_UND" , 19, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_COFF" , 20, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_PERR" , 21, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_UND" , 22, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_COFF" , 23, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_PERR" , 24, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_UND" , 25, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_COFF" , 26, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_PERR" , 27, 1, 112, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 112, "RAZ", 1, 1, 0, 0},
|
|
{"FED0_SBE" , 0, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED0_DBE" , 1, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED1_SBE" , 2, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED1_DBE" , 3, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_UND" , 4, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_COFF" , 5, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_PERR" , 6, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_UND" , 7, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_COFF" , 8, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_PERR" , 9, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_UND" , 10, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_COFF" , 11, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_PERR" , 12, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_UND" , 13, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_COFF" , 14, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_PERR" , 15, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_UND" , 16, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_COFF" , 17, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_PERR" , 18, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_UND" , 19, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_COFF" , 20, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_PERR" , 21, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_UND" , 22, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_COFF" , 23, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_PERR" , 24, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_UND" , 25, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_COFF" , 26, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_PERR" , 27, 1, 113, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 113, "RAZ", 1, 1, 0, 0},
|
|
{"QUE_SIZ" , 0, 29, 114, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 114, "RAZ", 1, 1, 0, 0},
|
|
{"PG_NUM" , 0, 25, 115, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 115, "RAZ", 1, 1, 0, 0},
|
|
{"ACT_INDX" , 0, 26, 116, "RO", 0, 1, 0ull, 0},
|
|
{"ACT_QUE" , 26, 3, 116, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 116, "RAZ", 0, 0, 0ull, 7ull},
|
|
{"EXP_INDX" , 0, 26, 117, "RO", 0, 1, 0ull, 0},
|
|
{"EXP_QUE" , 26, 3, 117, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 117, "RAZ", 0, 0, 0ull, 7ull},
|
|
{"CTL" , 0, 16, 118, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 118, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 32, 119, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 119, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 120, "RAZ", 1, 1, 0, 0},
|
|
{"OUT_OVR" , 2, 4, 120, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_21" , 6, 16, 120, "RAZ", 1, 1, 0, 0},
|
|
{"LOSTSTAT" , 22, 4, 120, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"STATOVR" , 26, 1, 120, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INB_NXA" , 27, 4, 120, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 120, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 16, 121, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 121, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_EN" , 0, 1, 122, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 122, "RAZ", 1, 1, 0, 0},
|
|
{"LOGL_EN" , 0, 16, 123, "R/W", 0, 1, 65535ull, 0},
|
|
{"PHYS_EN" , 16, 1, 123, "R/W", 0, 1, 1ull, 0},
|
|
{"HG2RX_EN" , 17, 1, 123, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HG2TX_EN" , 18, 1, 123, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 123, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 1, 124, "RO", 0, 1, 0ull, 0},
|
|
{"EN" , 1, 1, 124, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_3" , 2, 2, 124, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 4, 2, 124, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_7" , 6, 2, 124, "RAZ", 1, 1, 0, 0},
|
|
{"SPEED" , 8, 2, 124, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_10_63" , 10, 54, 124, "RAZ", 1, 1, 0, 0},
|
|
{"PRT" , 0, 6, 125, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 125, "RAZ", 1, 1, 0, 0},
|
|
{"RX_EN" , 0, 1, 126, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TX_EN" , 1, 1, 126, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRP_EN" , 2, 1, 126, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BCK_EN" , 3, 1, 126, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_15" , 4, 12, 126, "RAZ", 1, 1, 0, 0},
|
|
{"PHYS_BP" , 16, 16, 126, "R/W", 0, 1, 0ull, 0},
|
|
{"LOGL_EN" , 32, 16, 126, "R/W", 0, 0, 255ull, 255ull},
|
|
{"PHYS_EN" , 48, 16, 126, "R/W", 0, 0, 255ull, 255ull},
|
|
{"EN" , 0, 1, 127, "R/W", 0, 1, 0ull, 0},
|
|
{"SPEED" , 1, 1, 127, "R/W", 0, 1, 1ull, 0},
|
|
{"DUPLEX" , 2, 1, 127, "R/W", 0, 1, 1ull, 0},
|
|
{"SLOTTIME" , 3, 1, 127, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_4_7" , 4, 4, 127, "RAZ", 1, 1, 0, 0},
|
|
{"SPEED_MSB" , 8, 1, 127, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_9_11" , 9, 3, 127, "RAZ", 1, 1, 0, 0},
|
|
{"RX_IDLE" , 12, 1, 127, "RO", 0, 1, 1ull, 0},
|
|
{"TX_IDLE" , 13, 1, 127, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_14_63" , 14, 50, 127, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 64, 128, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 129, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 130, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 131, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 132, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 133, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 0, 8, 134, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 134, "RAZ", 1, 1, 0, 0},
|
|
{"BCST" , 0, 1, 135, "R/W", 0, 1, 1ull, 0},
|
|
{"MCST" , 1, 2, 135, "R/W", 0, 1, 0ull, 0},
|
|
{"CAM_MODE" , 3, 1, 135, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 135, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 5, 136, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_5_63" , 5, 59, 136, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 137, "RAZ", 1, 1, 0, 0},
|
|
{"CAREXT" , 1, 1, 137, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_2" , 2, 1, 137, "RAZ", 1, 1, 0, 0},
|
|
{"JABBER" , 3, 1, 137, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCSERR" , 4, 1, 137, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_5_6" , 5, 2, 137, "RAZ", 1, 1, 0, 0},
|
|
{"RCVERR" , 7, 1, 137, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SKPERR" , 8, 1, 137, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_9_63" , 9, 55, 137, "RAZ", 1, 1, 0, 0},
|
|
{"PRE_CHK" , 0, 1, 138, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PRE_STRP" , 1, 1, 138, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_DRP" , 2, 1, 138, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_BCK" , 3, 1, 138, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_MCST" , 4, 1, 138, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_SMAC" , 5, 1, 138, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRE_FREE" , 6, 1, 138, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_7_8" , 7, 2, 138, "RAZ", 1, 1, 0, 0},
|
|
{"PRE_ALIGN" , 9, 1, 138, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NULL_DIS" , 10, 1, 138, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 138, "RAZ", 1, 1, 0, 0},
|
|
{"IFG" , 0, 4, 139, "R/W", 0, 0, 8ull, 8ull},
|
|
{"RESERVED_4_63" , 4, 60, 139, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 140, "RAZ", 1, 1, 0, 0},
|
|
{"CAREXT" , 1, 1, 140, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 140, "RAZ", 1, 1, 0, 0},
|
|
{"JABBER" , 3, 1, 140, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 140, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_6" , 5, 2, 140, "RAZ", 1, 1, 0, 0},
|
|
{"RCVERR" , 7, 1, 140, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 140, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 140, "RAZ", 1, 1, 0, 0},
|
|
{"OVRERR" , 10, 1, 140, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 140, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 140, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 140, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 140, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 140, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_18" , 16, 3, 140, "RAZ", 1, 1, 0, 0},
|
|
{"PAUSE_DRP" , 19, 1, 140, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LOC_FAULT" , 20, 1, 140, "R/W", 0, 0, 0ull, 0ull},
|
|
{"REM_FAULT" , 21, 1, 140, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAD_SEQ" , 22, 1, 140, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAD_TERM" , 23, 1, 140, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UNSOP" , 24, 1, 140, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UNEOP" , 25, 1, 140, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UNDAT" , 26, 1, 140, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HG2FLD" , 27, 1, 140, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HG2CC" , 28, 1, 140, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 140, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 141, "RAZ", 1, 1, 0, 0},
|
|
{"CAREXT" , 1, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 141, "RAZ", 1, 1, 0, 0},
|
|
{"JABBER" , 3, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_6" , 5, 2, 141, "RAZ", 1, 1, 0, 0},
|
|
{"RCVERR" , 7, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 141, "RAZ", 1, 1, 0, 0},
|
|
{"OVRERR" , 10, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_18" , 16, 3, 141, "RAZ", 1, 1, 0, 0},
|
|
{"PAUSE_DRP" , 19, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LOC_FAULT" , 20, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"REM_FAULT" , 21, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BAD_SEQ" , 22, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BAD_TERM" , 23, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UNSOP" , 24, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UNEOP" , 25, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UNDAT" , 26, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"HG2FLD" , 27, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"HG2CC" , 28, 1, 141, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 141, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 142, "R/W", 0, 0, 10240ull, 10240ull},
|
|
{"RESERVED_16_63" , 16, 48, 142, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 16, 143, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 143, "RAZ", 1, 1, 0, 0},
|
|
{"RD_CLR" , 0, 1, 144, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 144, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 145, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 145, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 146, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 146, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 147, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 147, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 148, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 148, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 149, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 149, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 150, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 150, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 151, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 151, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 152, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 152, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 153, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 153, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 7, 154, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 154, "RAZ", 1, 1, 0, 0},
|
|
{"FCSSEL" , 8, 1, 154, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 154, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 155, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_6_63" , 6, 58, 155, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 156, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_6_63" , 6, 58, 156, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 9, 157, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_9_63" , 9, 55, 157, "RAZ", 1, 1, 0, 0},
|
|
{"LGTIM2GO" , 0, 16, 158, "RO", 0, 1, 0ull, 0},
|
|
{"XOF" , 16, 16, 158, "RO", 0, 0, 0ull, 0ull},
|
|
{"PHTIM2GO" , 32, 16, 158, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 158, "RAZ", 1, 1, 0, 0},
|
|
{"COMMIT" , 0, 4, 159, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_15" , 4, 12, 159, "RAZ", 1, 1, 0, 0},
|
|
{"DROP" , 16, 4, 159, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 159, "RAZ", 1, 1, 0, 0},
|
|
{"PRTS" , 0, 3, 160, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_3_63" , 3, 61, 160, "RAZ", 1, 1, 0, 0},
|
|
{"LANE_RXD" , 0, 32, 161, "RO", 0, 1, 0ull, 0},
|
|
{"LANE_RXC" , 32, 4, 161, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 36, 3, 161, "RO", 0, 1, 0ull, 0},
|
|
{"VAL" , 39, 1, 161, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_40_63" , 40, 24, 161, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 2, 162, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 162, "RAZ", 1, 1, 0, 0},
|
|
{"SMAC" , 0, 48, 163, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 163, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 164, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP" , 16, 1, 164, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 164, "RAZ", 1, 1, 0, 0},
|
|
{"PREAMBLE" , 0, 1, 165, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PAD" , 1, 1, 165, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCS" , 2, 1, 165, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FORCE_FCS" , 3, 1, 165, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 165, "RAZ", 1, 1, 0, 0},
|
|
{"BURST" , 0, 16, 166, "R/W", 0, 0, 8192ull, 8192ull},
|
|
{"RESERVED_16_63" , 16, 48, 166, "RAZ", 1, 1, 0, 0},
|
|
{"XOFF" , 0, 16, 167, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 167, "RAZ", 1, 1, 0, 0},
|
|
{"XON" , 0, 16, 168, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 168, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL_EN" , 0, 1, 169, "R/W", 0, 0, 1ull, 1ull},
|
|
{"XSDEF_EN" , 1, 1, 169, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 169, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_SIZE" , 0, 8, 170, "R/W", 0, 0, 59ull, 59ull},
|
|
{"RESERVED_8_63" , 8, 56, 170, "RAZ", 1, 1, 0, 0},
|
|
{"INTERVAL" , 0, 16, 171, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 171, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 172, "R/W", 0, 1, 96ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 172, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 173, "RO", 1, 1, 0, 0},
|
|
{"MSG_TIME" , 16, 16, 173, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 173, "RAZ", 1, 1, 0, 0},
|
|
{"SEND" , 0, 1, 174, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 174, "RAZ", 1, 1, 0, 0},
|
|
{"ALIGN" , 0, 1, 175, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 175, "RAZ", 1, 1, 0, 0},
|
|
{"SLOT" , 0, 10, 176, "R/W", 0, 0, 512ull, 512ull},
|
|
{"RESERVED_10_63" , 10, 54, 176, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 177, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 177, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL" , 0, 32, 178, "RC/W", 0, 1, 0ull, 0},
|
|
{"XSDEF" , 32, 32, 178, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCOL" , 0, 32, 179, "RC/W", 0, 1, 0ull, 0},
|
|
{"SCOL" , 32, 32, 179, "RC/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 180, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 180, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 181, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 181, "RAZ", 1, 1, 0, 0},
|
|
{"HIST0" , 0, 32, 182, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST1" , 32, 32, 182, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST2" , 0, 32, 183, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST3" , 32, 32, 183, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST4" , 0, 32, 184, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST5" , 32, 32, 184, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST6" , 0, 32, 185, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST7" , 32, 32, 185, "RC/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 0, 32, 186, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 32, 32, 186, "RC/W", 0, 1, 0ull, 0},
|
|
{"CTL" , 0, 32, 187, "RC/W", 0, 1, 0ull, 0},
|
|
{"UNDFLW" , 32, 32, 187, "RC/W", 0, 1, 0ull, 0},
|
|
{"RD_CLR" , 0, 1, 188, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 188, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 9, 189, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_9_63" , 9, 55, 189, "RAZ", 1, 1, 0, 0},
|
|
{"BP" , 0, 4, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 190, "RAZ", 1, 1, 0, 0},
|
|
{"LIMIT" , 0, 5, 191, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_5_63" , 5, 59, 191, "RAZ", 1, 1, 0, 0},
|
|
{"CORRUPT" , 0, 4, 192, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_4_63" , 4, 60, 192, "RAZ", 1, 1, 0, 0},
|
|
{"TX_XOF" , 0, 16, 193, "R/W1", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 193, "RAZ", 1, 1, 0, 0},
|
|
{"TX_XON" , 0, 16, 194, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 194, "RAZ", 1, 1, 0, 0},
|
|
{"IFG1" , 0, 4, 195, "R/W", 0, 1, 8ull, 0},
|
|
{"IFG2" , 4, 4, 195, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 195, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 196, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 196, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 4, 196, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 196, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 4, 196, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 4, 196, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LATE_COL" , 16, 4, 196, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 196, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 197, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 197, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 4, 197, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 197, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 4, 197, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 4, 197, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LATE_COL" , 16, 4, 197, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 197, "RAZ", 1, 1, 0, 0},
|
|
{"JAM" , 0, 8, 198, "R/W", 0, 1, 238ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 198, "RAZ", 1, 1, 0, 0},
|
|
{"LFSR" , 0, 16, 199, "R/W", 0, 1, 65535ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 199, "RAZ", 1, 1, 0, 0},
|
|
{"IGN_FULL" , 0, 4, 200, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP" , 4, 4, 200, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EN" , 8, 4, 200, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_31" , 12, 20, 200, "RAZ", 1, 1, 0, 0},
|
|
{"TX_PRT_BP" , 32, 16, 200, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 200, "RAZ", 1, 1, 0, 0},
|
|
{"DMAC" , 0, 48, 201, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
|
|
{"RESERVED_48_63" , 48, 16, 201, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 202, "R/W", 0, 0, 34824ull, 34824ull},
|
|
{"RESERVED_16_63" , 16, 48, 202, "RAZ", 1, 1, 0, 0},
|
|
{"PRTS" , 0, 5, 203, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 203, "RAZ", 1, 1, 0, 0},
|
|
{"DIC_EN" , 0, 1, 204, "R/W", 0, 0, 0ull, 1ull},
|
|
{"UNI_EN" , 1, 1, 204, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_3" , 2, 2, 204, "RAZ", 1, 1, 0, 0},
|
|
{"LS" , 4, 2, 204, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LS_BYP" , 6, 1, 204, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 204, "RAZ", 1, 1, 0, 0},
|
|
{"HG_EN" , 8, 1, 204, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HG_PAUSE_HGI" , 9, 2, 204, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_11_63" , 11, 53, 204, "RAZ", 1, 1, 0, 0},
|
|
{"THRESH" , 0, 4, 205, "R/W", 0, 0, 6ull, 6ull},
|
|
{"EN" , 4, 1, 205, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 205, "RAZ", 1, 1, 0, 0},
|
|
{"TX_OE" , 0, 1, 206, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RX_XOR" , 1, 1, 206, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_EN" , 2, 1, 206, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_TYPE" , 3, 1, 206, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_CNT" , 4, 4, 206, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_SEL" , 8, 4, 206, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLK_SEL" , 12, 2, 206, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLK_GEN" , 14, 1, 206, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 206, "RAZ", 1, 1, 0, 0},
|
|
{"N" , 0, 32, 207, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 207, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 208, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 208, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 209, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 209, "RAZ", 1, 1, 0, 0},
|
|
{"CLR" , 0, 16, 210, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 210, "RAZ", 1, 1, 0, 0},
|
|
{"SET" , 0, 16, 211, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 211, "RAZ", 1, 1, 0, 0},
|
|
{"ICD" , 0, 1, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBD" , 1, 1, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRP1" , 2, 1, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRP0" , 3, 1, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRN1" , 4, 1, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRN0" , 5, 1, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBRQ1" , 6, 1, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBRQ0" , 7, 1, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNRT" , 8, 1, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBR1" , 9, 1, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBR0" , 10, 1, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBDR1" , 11, 1, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBDR0" , 12, 1, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNR0" , 13, 1, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNR1" , 14, 1, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICR1" , 15, 1, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICR0" , 16, 1, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNRCB" , 17, 1, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 212, "RAZ", 1, 1, 0, 0},
|
|
{"FAU_END" , 0, 1, 213, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB_ENB" , 1, 1, 213, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PKO_ENB" , 2, 1, 213, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INB_MAT" , 3, 1, 213, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OUTB_MAT" , 4, 1, 213, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 213, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 214, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 214, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 214, "RAZ", 1, 1, 0, 0},
|
|
{"TOUT_VAL" , 0, 12, 215, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TOUT_ENB" , 12, 1, 215, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 215, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 216, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 216, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 216, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 8, 217, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 8, 9, 217, "R/W", 0, 1, 0ull, 0},
|
|
{"OPC" , 17, 4, 217, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 21, 8, 217, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 217, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 8, 218, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 8, 9, 218, "R/W", 0, 1, 0ull, 0},
|
|
{"OPC" , 17, 4, 218, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 21, 8, 218, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 218, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 219, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 220, "R/W", 0, 1, 0ull, 0},
|
|
{"NP_SOP" , 0, 1, 221, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NP_EOP" , 1, 1, 221, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_SOP" , 2, 1, 221, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_EOP" , 3, 1, 221, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NP_DAT" , 4, 1, 221, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_DAT" , 5, 1, 221, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 221, "RAZ", 1, 1, 0, 0},
|
|
{"NP_SOP" , 0, 1, 222, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NP_EOP" , 1, 1, 222, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_SOP" , 2, 1, 222, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_EOP" , 3, 1, 222, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NP_DAT" , 4, 1, 222, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_DAT" , 5, 1, 222, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 222, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 223, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 224, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 224, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 224, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 225, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 9, 226, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 9, 8, 226, "R/W", 0, 1, 0ull, 0},
|
|
{"EOT" , 17, 1, 226, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 18, 8, 226, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_26_63" , 26, 38, 226, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 9, 227, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 9, 8, 227, "R/W", 0, 1, 0ull, 0},
|
|
{"EOT" , 17, 1, 227, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 18, 8, 227, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_26_63" , 26, 38, 227, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 228, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 229, "R/W", 0, 1, 0ull, 0},
|
|
{"CNT_VAL" , 0, 15, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 230, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 230, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 231, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 232, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 232, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 232, "RAZ", 1, 1, 0, 0},
|
|
{"PORT" , 0, 6, 233, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 233, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP_SZ" , 0, 6, 234, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 234, "RAZ", 1, 1, 0, 0},
|
|
{"BACK" , 0, 4, 235, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 235, "RAZ", 1, 1, 0, 0},
|
|
{"BACK" , 0, 4, 236, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 236, "RAZ", 1, 1, 0, 0},
|
|
{"PWP" , 0, 1, 237, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_NEW" , 1, 1, 237, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_OLD" , 2, 1, 237, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRC_OFF" , 3, 1, 237, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ0" , 4, 1, 237, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ1" , 5, 1, 237, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM_WORD" , 6, 1, 237, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM0" , 7, 1, 237, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM1" , 8, 1, 237, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM2" , 9, 1, 237, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM3" , 10, 1, 237, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPQ_PBE0" , 11, 1, 237, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPQ_PBE1" , 12, 1, 237, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_POW" , 13, 1, 237, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_WP1" , 14, 1, 237, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_WQED" , 15, 1, 237, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSR_NCMD" , 16, 1, 237, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSR_MEM" , 17, 1, 237, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 237, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_ENB" , 0, 40, 238, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 238, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_CNT" , 0, 64, 239, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_EN" , 0, 1, 240, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OPC_MODE" , 1, 2, 240, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PBP_EN" , 3, 1, 240, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WQE_LEND" , 4, 1, 240, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKT_LEND" , 5, 1, 240, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NADDBUF" , 6, 1, 240, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDPKT" , 7, 1, 240, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 8, 1, 240, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LEN_M8" , 9, 1, 240, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PKT_OFF" , 10, 1, 240, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPD_FULL" , 11, 1, 240, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PQ_NABUF" , 12, 1, 240, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PQ_APKT" , 13, 1, 240, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NO_WPTR" , 14, 1, 240, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 240, "RAZ", 1, 1, 0, 0},
|
|
{"PRC_PAR0" , 0, 1, 241, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR1" , 1, 1, 241, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR2" , 2, 1, 241, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR3" , 3, 1, 241, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_SUB" , 4, 1, 241, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DC_OVR" , 5, 1, 241, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CC_OVR" , 6, 1, 241, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C_COLL" , 7, 1, 241, "R/W", 0, 0, 0ull, 0ull},
|
|
{"D_COLL" , 8, 1, 241, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BC_OVR" , 9, 1, 241, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PQ_ADD" , 10, 1, 241, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PQ_SUB" , 11, 1, 241, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 241, "RAZ", 1, 1, 0, 0},
|
|
{"PRC_PAR0" , 0, 1, 242, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR1" , 1, 1, 242, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR2" , 2, 1, 242, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR3" , 3, 1, 242, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP_SUB" , 4, 1, 242, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DC_OVR" , 5, 1, 242, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CC_OVR" , 6, 1, 242, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C_COLL" , 7, 1, 242, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"D_COLL" , 8, 1, 242, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BC_OVR" , 9, 1, 242, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PQ_ADD" , 10, 1, 242, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PQ_SUB" , 11, 1, 242, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 242, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP_SZ" , 0, 6, 243, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 243, "RAZ", 1, 1, 0, 0},
|
|
{"MB_SIZE" , 0, 12, 244, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_12_63" , 12, 52, 244, "RAZ", 1, 1, 0, 0},
|
|
{"PTR" , 0, 29, 245, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 245, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 17, 246, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_ENB" , 17, 1, 246, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 246, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 17, 247, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_ENB" , 17, 1, 247, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 247, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 25, 248, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 248, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 25, 249, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 249, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 250, "RO", 0, 1, 0ull, 0},
|
|
{"WMARK" , 32, 32, 250, "R/W", 0, 1, 4294967295ull, 0},
|
|
{"INTR" , 0, 64, 251, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 0, 64, 252, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RADDR" , 0, 3, 253, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 3, 1, 253, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 4, 29, 253, "RO", 1, 1, 0, 0},
|
|
{"PRADDR" , 33, 3, 253, "RO", 1, 1, 0, 0},
|
|
{"MAX_PKT" , 36, 3, 253, "RO", 0, 0, 5ull, 5ull},
|
|
{"RESERVED_39_63" , 39, 25, 253, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 7, 254, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 7, 1, 254, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 8, 29, 254, "RO", 1, 1, 0, 0},
|
|
{"MAX_PKT" , 37, 7, 254, "RO", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_44_63" , 44, 20, 254, "RAZ", 1, 1, 0, 0},
|
|
{"WQE_PCNT" , 0, 7, 255, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_PCNT" , 7, 7, 255, "RO", 0, 0, 0ull, 0ull},
|
|
{"PFIF_CNT" , 14, 3, 255, "RO", 0, 0, 0ull, 0ull},
|
|
{"WQEV_CNT" , 17, 1, 255, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTV_CNT" , 18, 1, 255, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 255, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 8, 256, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 8, 1, 256, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 9, 29, 256, "RO", 1, 1, 0, 0},
|
|
{"PRADDR" , 38, 8, 256, "RO", 1, 1, 0, 0},
|
|
{"WRADDR" , 46, 8, 256, "RO", 1, 1, 0, 0},
|
|
{"MAX_CNTS" , 54, 7, 256, "RO", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_61_63" , 61, 3, 256, "RAZ", 1, 1, 0, 0},
|
|
{"PASS" , 0, 32, 257, "R/W", 0, 1, 0ull, 0},
|
|
{"DROP" , 32, 32, 257, "R/W", 0, 1, 0ull, 0},
|
|
{"Q0_PCNT" , 0, 32, 258, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 258, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_ENB" , 0, 36, 259, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AVG_DLY" , 36, 14, 259, "R/W", 0, 1, 0ull, 0},
|
|
{"PRB_DLY" , 50, 14, 259, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRT_ENB" , 0, 4, 260, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 260, "RAZ", 1, 1, 0, 0},
|
|
{"PRB_CON" , 0, 32, 261, "R/W", 0, 1, 0ull, 0},
|
|
{"AVG_CON" , 32, 8, 261, "R/W", 0, 1, 0ull, 0},
|
|
{"NEW_CON" , 40, 8, 261, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_PCNT" , 48, 1, 261, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 261, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 25, 262, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT" , 25, 6, 262, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 262, "RAZ", 1, 1, 0, 0},
|
|
{"PORT_BIT" , 0, 32, 263, "R/W", 0, 0, 4294967295ull, 4294967295ull},
|
|
{"RESERVED_32_35" , 32, 4, 263, "RAZ", 1, 1, 0, 0},
|
|
{"PORT_BIT2" , 36, 4, 263, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_40_63" , 40, 24, 263, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 264, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT_QOS" , 32, 9, 264, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_41_63" , 41, 23, 264, "RAZ", 1, 1, 0, 0},
|
|
{"WQE_POOL" , 0, 3, 265, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_3_63" , 3, 61, 265, "RAZ", 1, 1, 0, 0},
|
|
{"PTR" , 0, 29, 266, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 266, "RAZ", 1, 1, 0, 0},
|
|
{"MEM0" , 0, 1, 267, "RO", 0, 0, 0ull, 0ull},
|
|
{"MEM1" , 1, 1, 267, "RO", 0, 0, 0ull, 0ull},
|
|
{"RRC" , 2, 1, 267, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 267, "RAZ", 1, 1, 0, 0},
|
|
{"MEM0_ERR" , 0, 7, 268, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM1_ERR" , 7, 7, 268, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 268, "RAZ", 1, 1, 0, 0},
|
|
{"KED0_SBE" , 0, 1, 269, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KED0_DBE" , 1, 1, 269, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KED1_SBE" , 2, 1, 269, "R/W", 0, 0, 0ull, 0ull},
|
|
{"KED1_DBE" , 3, 1, 269, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 269, "RAZ", 1, 1, 0, 0},
|
|
{"KED0_SBE" , 0, 1, 270, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KED0_DBE" , 1, 1, 270, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KED1_SBE" , 2, 1, 270, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"KED1_DBE" , 3, 1, 270, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 270, "RAZ", 1, 1, 0, 0},
|
|
{"WLB_DAT" , 0, 4, 271, "RO", 0, 0, 0ull, 0ull},
|
|
{"STIN_MSK" , 4, 1, 271, "RO", 0, 0, 0ull, 0ull},
|
|
{"DT" , 5, 1, 271, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTCNT" , 6, 13, 271, "RO", 0, 0, 0ull, 0ull},
|
|
{"WLB_MSK" , 19, 4, 271, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTBNK" , 23, 1, 271, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 271, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"L2T" , 0, 9, 272, "RO", 0, 0, 0ull, 0ull},
|
|
{"VAB_VWCF0" , 9, 1, 272, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_10" , 10, 1, 272, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VAB_VWCF1" , 11, 1, 272, "RO", 0, 0, 0ull, 0ull},
|
|
{"VWDF0" , 12, 4, 272, "RO", 0, 0, 0ull, 0ull},
|
|
{"VWDF1" , 16, 4, 272, "RO", 0, 0, 0ull, 0ull},
|
|
{"ILC" , 20, 1, 272, "RO", 0, 0, 0ull, 0ull},
|
|
{"PLC0" , 21, 1, 272, "RO", 0, 0, 0ull, 0ull},
|
|
{"PLC1" , 22, 1, 272, "RO", 0, 0, 0ull, 0ull},
|
|
{"PLC2" , 23, 1, 272, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 272, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XRDDAT" , 0, 1, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"XRDMSK" , 1, 1, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"PICBST" , 2, 1, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPCBST" , 3, 1, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"RHDB" , 4, 4, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"RMDB" , 8, 4, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRB" , 12, 4, 273, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 273, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LRF_ARB_MODE" , 0, 1, 274, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RFB_ARB_MODE" , 1, 1, 274, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RSP_ARB_MODE" , 2, 1, 274, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MWF_CRD" , 3, 4, 274, "R/W", 0, 0, 2ull, 2ull},
|
|
{"IDXALIAS" , 7, 1, 274, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPEN" , 8, 1, 274, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FPEMPTY" , 9, 1, 274, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FPEXP" , 10, 4, 274, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DFILL_DIS" , 14, 1, 274, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DPRES0" , 15, 1, 274, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DPRES1" , 16, 1, 274, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XOR_BANK" , 17, 1, 274, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LBIST" , 18, 1, 274, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BSTRUN" , 19, 1, 274, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 274, "RAZ", 1, 1, 0, 0},
|
|
{"L2T" , 0, 1, 275, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2D" , 1, 1, 275, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FINV" , 2, 1, 275, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SET" , 3, 3, 275, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PPNUM" , 6, 4, 275, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LFB_DMP" , 10, 1, 275, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LFB_ENUM" , 11, 4, 275, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 275, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DT_TAG" , 0, 29, 276, "RO", 0, 0, 0ull, 0ull},
|
|
{"DT_VLD" , 29, 1, 276, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_30" , 30, 1, 276, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DTENA" , 31, 1, 276, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 276, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PLC0RMSK" , 0, 32, 277, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PLC1RMSK" , 32, 32, 277, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PLC2RMSK" , 0, 32, 278, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ILCRMSK" , 32, 32, 278, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OOB1EN" , 0, 1, 279, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OOB2EN" , 1, 1, 279, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OOB3EN" , 2, 1, 279, "R/W", 0, 0, 0ull, 1ull},
|
|
{"L2TSECEN" , 3, 1, 279, "R/W", 0, 0, 0ull, 1ull},
|
|
{"L2TDEDEN" , 4, 1, 279, "R/W", 0, 0, 0ull, 1ull},
|
|
{"L2DSECEN" , 5, 1, 279, "R/W", 0, 0, 0ull, 1ull},
|
|
{"L2DDEDEN" , 6, 1, 279, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LCKENA" , 7, 1, 279, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LCK2ENA" , 8, 1, 279, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_9_63" , 9, 55, 279, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OOB1" , 0, 1, 280, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OOB2" , 1, 1, 280, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OOB3" , 2, 1, 280, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"L2TSEC" , 3, 1, 280, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"L2TDED" , 4, 1, 280, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"L2DSEC" , 5, 1, 280, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"L2DDED" , 6, 1, 280, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK" , 7, 1, 280, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK2" , 8, 1, 280, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 280, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_ENA" , 0, 1, 281, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_3" , 1, 3, 281, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_BASE" , 4, 27, 281, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 281, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_OFFSET" , 0, 10, 282, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 282, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VLD" , 0, 1, 283, "RO", 0, 0, 0ull, 0ull},
|
|
{"CMD" , 1, 4, 283, "RO", 0, 0, 0ull, 0ull},
|
|
{"SID" , 5, 9, 283, "RO", 0, 0, 0ull, 0ull},
|
|
{"VABNUM" , 14, 4, 283, "RO", 0, 0, 0ull, 0ull},
|
|
{"SET" , 18, 3, 283, "RO", 0, 0, 0ull, 0ull},
|
|
{"IHD" , 21, 1, 283, "RO", 0, 0, 0ull, 0ull},
|
|
{"ITL" , 22, 1, 283, "RO", 0, 0, 0ull, 0ull},
|
|
{"INXT" , 23, 4, 283, "RO", 0, 0, 0ull, 0ull},
|
|
{"VAM" , 27, 1, 283, "RO", 0, 0, 0ull, 0ull},
|
|
{"STCFL" , 28, 1, 283, "RO", 0, 0, 0ull, 0ull},
|
|
{"STINV" , 29, 1, 283, "RO", 0, 0, 0ull, 0ull},
|
|
{"STPND" , 30, 1, 283, "RO", 0, 0, 0ull, 0ull},
|
|
{"STCPND" , 31, 1, 283, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 283, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VLD" , 0, 1, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTPRB" , 1, 1, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRBRTY" , 2, 1, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTMFL" , 3, 1, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTVTM" , 4, 1, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTRSC" , 5, 1, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTRSP" , 6, 1, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTDT" , 7, 1, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTRDA" , 8, 1, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTM" , 9, 1, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWRM" , 10, 1, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWHF" , 11, 1, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWHP" , 12, 1, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTDQ" , 13, 1, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTDW" , 14, 1, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTRSP" , 15, 1, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"BID" , 16, 2, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"DSGOING" , 18, 1, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 284, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_IDX" , 0, 11, 285, "RO", 0, 0, 0ull, 0ull},
|
|
{"LFB_TAG" , 11, 16, 285, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_63" , 27, 37, 285, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_HWM" , 0, 4, 286, "R/W", 0, 0, 15ull, 15ull},
|
|
{"STPARTDIS" , 4, 1, 286, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 286, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STENA" , 0, 1, 287, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWBENA" , 1, 1, 287, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 287, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 0, 14, 288, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_19" , 14, 6, 288, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SADR" , 20, 14, 288, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_35" , 34, 2, 288, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSRC" , 36, 1, 288, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 37, 27, 288, "RO", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 0, 14, 289, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_19" , 14, 6, 289, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SADR" , 20, 14, 289, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_35" , 34, 2, 289, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSRC" , 36, 1, 289, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 37, 27, 289, "RO", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 0, 14, 290, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_19" , 14, 6, 290, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SADR" , 20, 14, 290, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_35" , 34, 2, 290, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSRC" , 36, 1, 290, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 37, 27, 290, "RO", 0, 0, 0ull, 0ull},
|
|
{"PFCNT0" , 0, 36, 291, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 291, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT0SEL" , 0, 6, 292, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0CLR" , 6, 1, 292, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0ENA" , 7, 1, 292, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1SEL" , 8, 6, 292, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1CLR" , 14, 1, 292, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1ENA" , 15, 1, 292, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2SEL" , 16, 6, 292, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2CLR" , 22, 1, 292, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2ENA" , 23, 1, 292, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3SEL" , 24, 6, 292, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3CLR" , 30, 1, 292, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3ENA" , 31, 1, 292, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0RDCLR" , 32, 1, 292, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1RDCLR" , 33, 1, 292, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2RDCLR" , 34, 1, 292, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3RDCLR" , 35, 1, 292, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 292, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP0GRP" , 0, 2, 293, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP1GRP" , 2, 2, 293, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP2GRP" , 4, 2, 293, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP3GRP" , 6, 2, 293, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP4GRP" , 8, 2, 293, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP5GRP" , 10, 2, 293, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP6GRP" , 12, 2, 293, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP7GRP" , 14, 2, 293, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP8GRP" , 16, 2, 293, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP9GRP" , 18, 2, 293, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP10GRP" , 20, 2, 293, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP11GRP" , 22, 2, 293, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 293, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK0" , 0, 8, 294, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK1" , 8, 8, 294, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK2" , 16, 8, 294, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK3" , 24, 8, 294, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 294, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK4" , 0, 8, 295, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK5" , 8, 8, 295, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK6" , 16, 8, 295, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK7" , 24, 8, 295, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 295, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK8" , 0, 8, 296, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK9" , 8, 8, 296, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK10" , 16, 8, 296, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK11" , 24, 8, 296, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 296, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSKIOB" , 0, 8, 297, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 297, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q0STAT" , 0, 34, 298, "RO", 0, 0, 0ull, 0ull},
|
|
{"FTL" , 34, 1, 298, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_35_63" , 35, 29, 298, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q1STAT" , 0, 34, 299, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 299, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q2STAT" , 0, 34, 300, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 300, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q3STAT" , 0, 34, 301, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 301, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 0, 1, 302, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_INTENA" , 1, 1, 302, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DED_INTENA" , 2, 1, 302, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 3, 1, 302, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 4, 1, 302, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BMHCLSEL" , 5, 1, 302, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 302, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 0, 11, 303, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSET" , 11, 3, 303, "RO", 0, 0, 0ull, 0ull},
|
|
{"FOWMSK" , 14, 4, 303, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADRU" , 18, 1, 303, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 303, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW0" , 0, 10, 304, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW1" , 10, 10, 304, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 304, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW2" , 0, 10, 305, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW3" , 10, 10, 305, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 305, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q0FUS" , 0, 34, 306, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 306, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q1FUS" , 0, 34, 307, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 307, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q2FUS" , 0, 34, 308, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 308, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q3FUS" , 0, 34, 309, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRIP_1024K" , 34, 1, 309, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRIP_512K" , 35, 1, 309, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_36" , 36, 1, 309, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EMA_CTL" , 37, 3, 309, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 309, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 0, 1, 310, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_INTENA" , 1, 1, 310, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DED_INTENA" , 2, 1, 310, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 3, 1, 310, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 4, 1, 310, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FSYN" , 5, 6, 310, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 11, 10, 310, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSET" , 21, 3, 310, "RO", 0, 0, 0ull, 0ull},
|
|
{"LCKERR" , 24, 1, 310, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK_INTENA" , 25, 1, 310, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LCKERR2" , 26, 1, 310, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK_INTENA2" , 27, 1, 310, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FADRU" , 28, 1, 310, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 310, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RATE" , 0, 8, 311, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_8_63" , 8, 56, 311, "RAZ", 1, 1, 0, 0},
|
|
{"PHASE" , 0, 7, 312, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_7_63" , 7, 57, 312, "RAZ", 1, 1, 0, 0},
|
|
{"RATE" , 0, 16, 313, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 313, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_EN" , 0, 1, 314, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 314, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 315, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 315, "RAZ", 1, 1, 0, 0},
|
|
{"POLARITY" , 0, 1, 316, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 316, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_EN" , 0, 8, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 317, "RAZ", 1, 1, 0, 0},
|
|
{"FORMAT" , 0, 4, 318, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 318, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 6, 319, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 319, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 6, 320, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 320, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 32, 321, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 321, "RAZ", 1, 1, 0, 0},
|
|
{"CLR" , 0, 32, 322, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 322, "RAZ", 1, 1, 0, 0},
|
|
{"SET" , 0, 32, 323, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 323, "RAZ", 1, 1, 0, 0},
|
|
{"START" , 0, 1, 324, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 324, "RAZ", 1, 0, 0, 0ull},
|
|
{"MRD" , 0, 3, 325, "RO", 1, 0, 0, 0ull},
|
|
{"MRF" , 3, 1, 325, "RO", 1, 0, 0, 0ull},
|
|
{"MWC" , 4, 1, 325, "RO", 1, 0, 0, 0ull},
|
|
{"MWD" , 5, 3, 325, "RO", 1, 0, 0, 0ull},
|
|
{"MWF" , 8, 1, 325, "RO", 1, 0, 0, 0ull},
|
|
{"CSRE2D" , 9, 1, 325, "RO", 1, 0, 0, 0ull},
|
|
{"CSRD2E" , 10, 1, 325, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 325, "RAZ", 1, 0, 0, 0ull},
|
|
{"PCTL_DAT" , 0, 5, 326, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_11" , 5, 7, 326, "RAZ", 0, 1, 0ull, 0},
|
|
{"PCTL_CSR" , 12, 4, 326, "R/W", 0, 1, 15ull, 0},
|
|
{"NCTL_DAT" , 16, 4, 326, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_27" , 20, 8, 326, "RAZ", 0, 1, 0ull, 0},
|
|
{"NCTL_CSR" , 28, 4, 326, "R/W", 0, 1, 15ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 326, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DIC" , 0, 2, 327, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QS_DIC" , 2, 2, 327, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TSKW" , 4, 2, 327, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SIL_LAT" , 6, 2, 327, "R/W", 0, 0, 1ull, 1ull},
|
|
{"BPRCH" , 8, 1, 327, "R/W", 0, 1, 0ull, 0},
|
|
{"FPRCH2" , 9, 1, 327, "R/W", 0, 0, 0ull, 1ull},
|
|
{"MODE32B" , 10, 1, 327, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRESET" , 11, 1, 327, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INORDER_MRF" , 12, 1, 327, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INORDER_MWF" , 13, 1, 327, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"R2R_SLOT" , 14, 1, 327, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RDIMM_ENA" , 15, 1, 327, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_17" , 16, 2, 327, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX_WRITE_BATCH" , 18, 4, 327, "R/W", 0, 0, 8ull, 8ull},
|
|
{"XOR_BANK" , 22, 1, 327, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SLOW_SCF" , 23, 1, 327, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DDR__PCTL" , 24, 4, 327, "RO", 1, 1, 0, 0},
|
|
{"DDR__NCTL" , 28, 4, 327, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 327, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 328, "RAZ", 0, 1, 0ull, 0},
|
|
{"DCC_ENABLE" , 8, 1, 328, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SIL_MODE" , 9, 1, 328, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEQUENCE" , 10, 3, 328, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDLEPOWER" , 13, 3, 328, "R/W", 0, 0, 0ull, 6ull},
|
|
{"FORCEWRITE" , 16, 4, 328, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECC_ADR" , 20, 1, 328, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_21_63" , 21, 43, 328, "RAZ", 1, 1, 0, 0},
|
|
{"DCLKCNT_HI" , 0, 32, 329, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 329, "RAZ", 1, 1, 0, 0},
|
|
{"DCLKCNT_LO" , 0, 32, 330, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 330, "RAZ", 1, 1, 0, 0},
|
|
{"DCLK90_VLU" , 0, 5, 331, "R/W", 0, 1, 0ull, 0},
|
|
{"DCLK90_LD" , 5, 1, 331, "R/W", 0, 1, 0ull, 0},
|
|
{"DCLK90_BYP" , 6, 1, 331, "R/W", 0, 1, 0ull, 0},
|
|
{"OFF90_ENA" , 7, 1, 331, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 331, "RAZ", 1, 1, 0, 0},
|
|
{"DDR2" , 0, 1, 332, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RDQS" , 1, 1, 332, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLL90_BYP" , 2, 1, 332, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLL90_VLU" , 3, 5, 332, "R/W", 0, 1, 0ull, 0},
|
|
{"QDLL_ENA" , 8, 1, 332, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ODT_ENA" , 9, 1, 332, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DDR2T" , 10, 1, 332, "R/W", 0, 1, 0ull, 0},
|
|
{"CRIP_MODE" , 11, 1, 332, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TFAW" , 12, 5, 332, "R/W", 0, 0, 0ull, 9ull},
|
|
{"DDR_EOF" , 17, 4, 332, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SILO_HC" , 21, 1, 332, "R/W", 0, 1, 1ull, 0},
|
|
{"TWR" , 22, 3, 332, "R/W", 0, 0, 3ull, 1ull},
|
|
{"BWCNT" , 25, 1, 332, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POCAS" , 26, 1, 332, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDLAT" , 27, 3, 332, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BURST8" , 30, 1, 332, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BANK8" , 31, 1, 332, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 332, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CLK" , 0, 4, 333, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_4" , 4, 1, 333, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CMD" , 5, 4, 333, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 333, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DQ" , 10, 4, 333, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 333, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DLL90_VLU" , 0, 5, 334, "R/W", 0, 1, 0ull, 0},
|
|
{"DLL90_ENA" , 5, 1, 334, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLL90_BYP" , 6, 1, 334, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRESET" , 7, 1, 334, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 334, "RAZ", 1, 1, 0, 0},
|
|
{"CS_MASK" , 0, 8, 335, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_15" , 8, 8, 335, "RAZ", 0, 1, 0ull, 0},
|
|
{"ROW_LSB" , 16, 3, 335, "R/W", 0, 1, 3ull, 0},
|
|
{"BANK8" , 19, 1, 335, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_63" , 20, 44, 335, "RAZ", 0, 1, 0ull, 0},
|
|
{"MRDSYN0" , 0, 8, 336, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN1" , 8, 8, 336, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN2" , 16, 8, 336, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN3" , 24, 8, 336, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 336, "RAZ", 1, 1, 0, 0},
|
|
{"FCOL" , 0, 12, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"FROW" , 12, 14, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"FBANK" , 26, 3, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"FBUNK" , 29, 1, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"FDIMM" , 30, 2, 337, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 337, "RAZ", 1, 1, 0, 0},
|
|
{"IFBCNT_HI" , 0, 32, 338, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 338, "RAZ", 1, 1, 0, 0},
|
|
{"IFBCNT_LO" , 0, 32, 339, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 339, "RAZ", 1, 1, 0, 0},
|
|
{"INIT_START" , 0, 1, 340, "WR0", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 1, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ROW_LSB" , 2, 3, 340, "R/W", 0, 1, 3ull, 0},
|
|
{"PBANK_LSB" , 5, 4, 340, "R/W", 0, 1, 5ull, 0},
|
|
{"REF_INT" , 9, 6, 340, "R/W", 0, 0, 1ull, 2ull},
|
|
{"TCL" , 15, 4, 340, "R/W", 0, 1, 3ull, 0},
|
|
{"INTR_SEC_ENA" , 19, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INTR_DED_ENA" , 20, 1, 340, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 21, 4, 340, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 25, 4, 340, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BUNK_ENA" , 29, 1, 340, "R/W", 0, 1, 0ull, 0},
|
|
{"SILO_QC" , 30, 1, 340, "R/W", 0, 1, 0ull, 0},
|
|
{"RESET" , 31, 1, 340, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 340, "RAZ", 1, 1, 0, 0},
|
|
{"TRAS" , 0, 5, 341, "R/W", 0, 0, 12ull, 12ull},
|
|
{"TRCD" , 5, 4, 341, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TWTR" , 9, 4, 341, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TRP" , 13, 4, 341, "R/W", 0, 0, 5ull, 4ull},
|
|
{"TRFC" , 17, 5, 341, "R/W", 0, 0, 6ull, 7ull},
|
|
{"TMRD" , 22, 3, 341, "R/W", 0, 0, 2ull, 2ull},
|
|
{"CASLAT" , 25, 3, 341, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TRRD" , 28, 3, 341, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_31_63" , 31, 33, 341, "RAZ", 1, 1, 0, 0},
|
|
{"CS_MASK" , 0, 8, 342, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 342, "RAZ", 1, 1, 0, 0},
|
|
{"OPSCNT_HI" , 0, 32, 343, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 343, "RAZ", 1, 1, 0, 0},
|
|
{"OPSCNT_LO" , 0, 32, 344, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 344, "RAZ", 1, 1, 0, 0},
|
|
{"EN2" , 0, 1, 345, "R/W", 0, 1, 0ull, 0},
|
|
{"EN4" , 1, 1, 345, "R/W", 0, 1, 0ull, 0},
|
|
{"EN6" , 2, 1, 345, "R/W", 0, 1, 0ull, 0},
|
|
{"EN8" , 3, 1, 345, "R/W", 0, 1, 1ull, 0},
|
|
{"EN12" , 4, 1, 345, "R/W", 0, 1, 0ull, 0},
|
|
{"EN16" , 5, 1, 345, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_7" , 6, 2, 345, "RAZ", 0, 1, 0ull, 0},
|
|
{"CLKR" , 8, 6, 345, "R/W", 0, 1, 0ull, 0},
|
|
{"CLKF" , 14, 12, 345, "R/W", 0, 1, 31ull, 0},
|
|
{"RESET_N" , 26, 1, 345, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DIV_RESET" , 27, 1, 345, "R/W", 0, 0, 1ull, 0ull},
|
|
{"FASTEN_N" , 28, 1, 345, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_29_63" , 29, 35, 345, "RAZ", 0, 1, 0ull, 0},
|
|
{"FBSLIP" , 0, 1, 346, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RFSLIP" , 1, 1, 346, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_21" , 2, 20, 346, "RAZ", 1, 1, 0, 0},
|
|
{"DDR__PCTL" , 22, 5, 346, "RO", 1, 1, 0, 0},
|
|
{"DDR__NCTL" , 27, 5, 346, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 346, "RAZ", 1, 1, 0, 0},
|
|
{"BNK" , 0, 3, 347, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 347, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"COL" , 4, 12, 347, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROW" , 16, 16, 347, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PATTERN" , 32, 8, 347, "R/W", 0, 0, 170ull, 170ull},
|
|
{"RANKMASK" , 40, 4, 347, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_63" , 44, 20, 347, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"BYTE" , 0, 4, 348, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_15" , 4, 12, 348, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"BITMASK" , 16, 16, 348, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 348, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"BYTE0" , 0, 4, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE1" , 4, 4, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE2" , 8, 4, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE3" , 12, 4, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE4" , 16, 4, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE5" , 20, 4, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE6" , 24, 4, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE7" , 28, 4, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE8" , 32, 4, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"STATUS" , 36, 2, 349, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_38_63" , 38, 26, 349, "RAZ", 1, 0, 0, 0ull},
|
|
{"PCTL" , 0, 5, 350, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 350, "RAZ", 0, 1, 0ull, 0},
|
|
{"NCTL" , 8, 4, 350, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_12_15" , 12, 4, 350, "RAZ", 0, 1, 0ull, 0},
|
|
{"ENABLE" , 16, 1, 350, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_17_63" , 17, 47, 350, "RAZ", 0, 1, 0ull, 0},
|
|
{"RODT_LO0" , 0, 4, 351, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_LO1" , 4, 4, 351, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_LO2" , 8, 4, 351, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_LO3" , 12, 4, 351, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI0" , 16, 4, 351, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI1" , 20, 4, 351, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI2" , 24, 4, 351, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI3" , 28, 4, 351, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_32_63" , 32, 32, 351, "RAZ", 1, 1, 0, 0},
|
|
{"WODT_D0_R0" , 0, 8, 352, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D0_R1" , 8, 8, 352, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D1_R0" , 16, 8, 352, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D1_R1" , 24, 8, 352, "R/W", 0, 0, 255ull, 255ull},
|
|
{"RESERVED_32_63" , 32, 32, 352, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WODT_D2_R0" , 0, 8, 353, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D2_R1" , 8, 8, 353, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D3_R0" , 16, 8, 353, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D3_R1" , 24, 8, 353, "R/W", 0, 0, 255ull, 255ull},
|
|
{"RESERVED_32_63" , 32, 32, 353, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"NCBI" , 0, 1, 354, "RO", 0, 0, 0ull, 0ull},
|
|
{"LOC" , 1, 1, 354, "RO", 0, 0, 0ull, 0ull},
|
|
{"DMA" , 2, 1, 354, "RO", 0, 0, 0ull, 0ull},
|
|
{"NCBO_0" , 3, 1, 354, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 354, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 5, 355, "R/W", 1, 1, 0, 0},
|
|
{"PCTL" , 5, 5, 355, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_10_63" , 10, 54, 355, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 36, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 36, 20, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"ENDIAN" , 56, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"SWAP8" , 57, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"SWAP16" , 58, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"SWAP32" , 59, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_60" , 60, 1, 356, "RAZ", 1, 1, 0, 0},
|
|
{"CLR" , 61, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RW" , 62, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 63, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"DONE" , 0, 1, 357, "R/W1C", 0, 1, 0ull, 0},
|
|
{"DMARQ" , 1, 1, 357, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_2_63" , 2, 62, 357, "RAZ", 1, 1, 0, 0},
|
|
{"DONE" , 0, 1, 358, "R/W", 0, 1, 0ull, 0},
|
|
{"DMARQ" , 1, 1, 358, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 358, "RAZ", 1, 1, 0, 0},
|
|
{"DMARQ" , 0, 6, 359, "R/W", 0, 1, 63ull, 0},
|
|
{"DMACK_S" , 6, 6, 359, "R/W", 0, 1, 63ull, 0},
|
|
{"OE_A" , 12, 6, 359, "R/W", 0, 1, 63ull, 0},
|
|
{"OE_N" , 18, 6, 359, "R/W", 0, 1, 63ull, 0},
|
|
{"WE_A" , 24, 6, 359, "R/W", 0, 1, 63ull, 0},
|
|
{"WE_N" , 30, 6, 359, "R/W", 0, 1, 63ull, 0},
|
|
{"DMACK_H" , 36, 6, 359, "R/W", 0, 1, 63ull, 0},
|
|
{"PAUSE" , 42, 6, 359, "R/W", 0, 1, 63ull, 0},
|
|
{"RESERVED_48_54" , 48, 7, 359, "RAZ", 1, 1, 0, 0},
|
|
{"WIDTH" , 55, 1, 359, "R/W", 0, 1, 0ull, 0},
|
|
{"DDR" , 56, 1, 359, "R/W", 0, 1, 0ull, 0},
|
|
{"RD_DLY" , 57, 3, 359, "R/W", 0, 1, 0ull, 0},
|
|
{"TIM_MULT" , 60, 2, 359, "R/W", 0, 1, 0ull, 0},
|
|
{"DMARQ_PI" , 62, 1, 359, "R/W", 0, 1, 0ull, 0},
|
|
{"DMACK_PI" , 63, 1, 359, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR_ERR" , 0, 1, 360, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WAIT_ERR" , 1, 1, 360, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 360, "RAZ", 1, 1, 0, 0},
|
|
{"ADR_INT" , 0, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"WAIT_INT" , 1, 1, 361, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 361, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 362, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 3, 5, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 362, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 363, "RAZ", 1, 1, 0, 0},
|
|
{"BASE" , 3, 25, 363, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_30" , 28, 3, 363, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 31, 1, 363, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 363, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 364, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_0_8" , 0, 9, 365, "RAZ", 1, 1, 0, 0},
|
|
{"TERM" , 9, 2, 365, "RO", 1, 1, 0, 0},
|
|
{"DMACK_P0" , 11, 1, 365, "RO", 1, 1, 0, 0},
|
|
{"DMACK_P1" , 12, 1, 365, "RO", 1, 1, 0, 0},
|
|
{"DMACK_P2" , 13, 1, 365, "RO", 1, 1, 0, 0},
|
|
{"WIDTH" , 14, 1, 365, "RO", 1, 1, 0, 0},
|
|
{"ALE" , 15, 1, 365, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_16_63" , 16, 48, 365, "RAZ", 1, 1, 0, 0},
|
|
{"BASE" , 0, 16, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 16, 12, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"WIDTH" , 28, 1, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"ALE" , 29, 1, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"ORBIT" , 30, 1, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 31, 1, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"OE_EXT" , 32, 2, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"WE_EXT" , 34, 2, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"SAM" , 36, 1, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"RD_DLY" , 37, 3, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"TIM_MULT" , 40, 2, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"DMACK" , 42, 2, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 366, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 6, 367, "R/W", 0, 1, 63ull, 0},
|
|
{"CE" , 6, 6, 367, "R/W", 0, 1, 63ull, 0},
|
|
{"OE" , 12, 6, 367, "R/W", 0, 1, 63ull, 0},
|
|
{"WE" , 18, 6, 367, "R/W", 0, 1, 63ull, 0},
|
|
{"RD_HLD" , 24, 6, 367, "R/W", 0, 1, 63ull, 0},
|
|
{"WR_HLD" , 30, 6, 367, "R/W", 0, 1, 63ull, 0},
|
|
{"PAUSE" , 36, 6, 367, "R/W", 0, 1, 63ull, 0},
|
|
{"WAIT" , 42, 6, 367, "R/W", 0, 1, 63ull, 0},
|
|
{"PAGE" , 48, 6, 367, "R/W", 0, 1, 63ull, 0},
|
|
{"ALE" , 54, 6, 367, "R/W", 0, 1, 63ull, 0},
|
|
{"PAGES" , 60, 2, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"WAITM" , 62, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"PAGEM" , 63, 1, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"FIF_THR" , 0, 6, 368, "R/W", 0, 0, 26ull, 26ull},
|
|
{"RESERVED_6_7" , 6, 2, 368, "RAZ", 1, 1, 0, 0},
|
|
{"FIF_CNT" , 8, 6, 368, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_15" , 14, 2, 368, "RAZ", 1, 1, 0, 0},
|
|
{"DMA_THR" , 16, 6, 368, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_22_63" , 22, 42, 368, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 64, 369, "R/W", 1, 1, 0, 0},
|
|
{"MAN_INFO" , 0, 32, 370, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 370, "RAZ", 1, 1, 0, 0},
|
|
{"MAN_INFO" , 0, 32, 371, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 371, "RAZ", 1, 1, 0, 0},
|
|
{"PP_DIS" , 0, 12, 372, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_12_15" , 12, 4, 372, "RO", 1, 1, 0, 0},
|
|
{"CHIP_ID" , 16, 8, 372, "RO", 1, 1, 0, 0},
|
|
{"BIST_DIS" , 24, 1, 372, "RO", 1, 1, 0, 0},
|
|
{"RST_SHT" , 25, 1, 372, "RO", 1, 1, 0, 0},
|
|
{"NOCRYPTO" , 26, 1, 372, "RO", 1, 1, 0, 0},
|
|
{"NOMUL" , 27, 1, 372, "RO", 1, 1, 0, 0},
|
|
{"NODFA_CP2" , 28, 1, 372, "RO", 1, 1, 0, 0},
|
|
{"NOKASU" , 29, 1, 372, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_30_31" , 30, 2, 372, "RAZ", 1, 1, 0, 0},
|
|
{"RAID_EN" , 32, 1, 372, "RO", 1, 1, 0, 0},
|
|
{"FUS318" , 33, 1, 372, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_34_63" , 34, 30, 372, "RAZ", 1, 1, 0, 0},
|
|
{"ICACHE" , 0, 24, 373, "RO", 1, 1, 0, 0},
|
|
{"NODFA_DTE" , 24, 1, 373, "RO", 1, 1, 0, 0},
|
|
{"NOZIP" , 25, 1, 373, "RO", 1, 1, 0, 0},
|
|
{"EFUS_IGN" , 26, 1, 373, "RO", 1, 1, 0, 0},
|
|
{"EFUS_LCK" , 27, 1, 373, "RO", 1, 1, 0, 0},
|
|
{"BAR2_EN" , 28, 1, 373, "RO", 1, 1, 0, 0},
|
|
{"ZIP_CRIP" , 29, 2, 373, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_31_63" , 31, 33, 373, "RAZ", 1, 1, 0, 0},
|
|
{"EMA" , 0, 3, 374, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 374, "RAZ", 1, 1, 0, 0},
|
|
{"EFF_EMA" , 4, 3, 374, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 374, "RAZ", 1, 1, 0, 0},
|
|
{"PDF" , 0, 64, 375, "RO", 1, 1, 0, 0},
|
|
{"FBSLIP" , 0, 1, 376, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RFSLIP" , 1, 1, 376, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 376, "RAZ", 1, 1, 0, 0},
|
|
{"PROG" , 0, 1, 377, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_1_63" , 1, 63, 377, "RAZ", 1, 1, 0, 0},
|
|
{"SETUP" , 0, 8, 378, "R/W", 0, 1, 3ull, 0},
|
|
{"SCLK_HI" , 8, 12, 378, "R/W", 0, 1, 100ull, 0},
|
|
{"SCLK_LO" , 20, 4, 378, "R/W", 0, 1, 2ull, 0},
|
|
{"OUT" , 24, 8, 378, "R/W", 0, 1, 3ull, 0},
|
|
{"PROG_PIN" , 32, 1, 378, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_33_63" , 33, 31, 378, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 8, 379, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EFUSE" , 8, 1, 379, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 379, "RAZ", 1, 1, 0, 0},
|
|
{"PEND" , 12, 1, 379, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 379, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 16, 8, 379, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_24_63" , 24, 40, 379, "RAZ", 1, 1, 0, 0},
|
|
{"REPAIR0" , 0, 14, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"REPAIR1" , 14, 14, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"REPAIR2" , 28, 14, 380, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_42_63" , 42, 22, 380, "RAZ", 1, 1, 0, 0},
|
|
{"TOO_MANY" , 0, 1, 381, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 381, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 3, 382, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_3_63" , 3, 61, 382, "RAZ", 1, 1, 0, 0},
|
|
{"ST_INT" , 0, 1, 383, "R/W1C", 0, 1, 0ull, 0},
|
|
{"TS_INT" , 1, 1, 383, "R/W1C", 0, 1, 0ull, 0},
|
|
{"CORE_INT" , 2, 1, 383, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_3" , 3, 1, 383, "RAZ", 1, 1, 0, 0},
|
|
{"ST_EN" , 4, 1, 383, "R/W", 0, 1, 0ull, 0},
|
|
{"TS_EN" , 5, 1, 383, "R/W", 0, 1, 0ull, 0},
|
|
{"CORE_EN" , 6, 1, 383, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_7" , 7, 1, 383, "RAZ", 1, 1, 0, 0},
|
|
{"SDA_OVR" , 8, 1, 383, "R/W", 0, 1, 0ull, 0},
|
|
{"SCL_OVR" , 9, 1, 383, "R/W", 0, 1, 0ull, 0},
|
|
{"SDA" , 10, 1, 383, "RO", 1, 1, 0, 0},
|
|
{"SCL" , 11, 1, 383, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_12_63" , 12, 52, 383, "RAZ", 1, 1, 0, 0},
|
|
{"D" , 0, 32, 384, "R/W", 0, 1, 0ull, 0},
|
|
{"EOP_IA" , 32, 3, 384, "R/W", 0, 1, 0ull, 0},
|
|
{"IA" , 35, 5, 384, "R/W", 0, 1, 0ull, 0},
|
|
{"A" , 40, 10, 384, "R/W", 0, 1, 0ull, 0},
|
|
{"SCR" , 50, 2, 384, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 52, 3, 384, "R/W", 0, 1, 0ull, 0},
|
|
{"SOVR" , 55, 1, 384, "R/W", 0, 1, 0ull, 0},
|
|
{"R" , 56, 1, 384, "R/W", 0, 1, 0ull, 0},
|
|
{"OP" , 57, 4, 384, "R/W", 0, 1, 0ull, 0},
|
|
{"EIA" , 61, 1, 384, "R/W", 0, 1, 0ull, 0},
|
|
{"SLONLY" , 62, 1, 384, "R/W", 0, 1, 0ull, 0},
|
|
{"V" , 63, 1, 384, "RC/W", 0, 1, 0ull, 0},
|
|
{"D" , 0, 32, 385, "R/W", 0, 1, 0ull, 0},
|
|
{"IA" , 32, 8, 385, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_40_63" , 40, 24, 385, "RAZ", 1, 1, 0, 0},
|
|
{"D" , 0, 32, 386, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_32_61" , 32, 30, 386, "RAZ", 1, 1, 0, 0},
|
|
{"V" , 62, 2, 386, "RC/W", 0, 1, 0ull, 0},
|
|
{"DLH" , 0, 8, 387, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 387, "RAZ", 1, 1, 0, 0},
|
|
{"DLL" , 0, 8, 388, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 388, "RAZ", 1, 1, 0, 0},
|
|
{"FAR" , 0, 1, 389, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 389, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 390, "WO", 0, 1, 0ull, 0},
|
|
{"RXFR" , 1, 1, 390, "WO", 0, 1, 0ull, 0},
|
|
{"TXFR" , 2, 1, 390, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_3" , 3, 1, 390, "RAZ", 0, 1, 0ull, 0},
|
|
{"TXTRIG" , 4, 2, 390, "WO", 0, 1, 0ull, 0},
|
|
{"RXTRIG" , 6, 2, 390, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 390, "RAZ", 1, 1, 0, 0},
|
|
{"HTX" , 0, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 391, "RAZ", 1, 1, 0, 0},
|
|
{"ERBFI" , 0, 1, 392, "R/W", 0, 1, 0ull, 0},
|
|
{"ETBEI" , 1, 1, 392, "R/W", 0, 1, 0ull, 0},
|
|
{"ELSI" , 2, 1, 392, "R/W", 0, 1, 0ull, 0},
|
|
{"EDSSI" , 3, 1, 392, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_6" , 4, 3, 392, "RAZ", 0, 1, 0ull, 0},
|
|
{"PTIME" , 7, 1, 392, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 392, "RAZ", 1, 1, 0, 0},
|
|
{"IID" , 0, 4, 393, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_4_5" , 4, 2, 393, "RAZ", 0, 1, 0ull, 0},
|
|
{"FEN" , 6, 2, 393, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 393, "RAZ", 1, 1, 0, 0},
|
|
{"CLS" , 0, 2, 394, "R/W", 0, 1, 0ull, 0},
|
|
{"STOP" , 2, 1, 394, "R/W", 0, 1, 0ull, 0},
|
|
{"PEN" , 3, 1, 394, "R/W", 0, 1, 0ull, 0},
|
|
{"EPS" , 4, 1, 394, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_5" , 5, 1, 394, "RAZ", 0, 1, 0ull, 0},
|
|
{"BRK" , 6, 1, 394, "R/W", 0, 1, 0ull, 0},
|
|
{"DLAB" , 7, 1, 394, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 394, "RAZ", 1, 1, 0, 0},
|
|
{"DR" , 0, 1, 395, "RO", 0, 1, 0ull, 0},
|
|
{"OE" , 1, 1, 395, "RC", 0, 1, 0ull, 0},
|
|
{"PE" , 2, 1, 395, "RC", 0, 1, 0ull, 0},
|
|
{"FE" , 3, 1, 395, "RC", 0, 1, 0ull, 0},
|
|
{"BI" , 4, 1, 395, "RC", 0, 1, 0ull, 0},
|
|
{"THRE" , 5, 1, 395, "RO", 0, 1, 1ull, 0},
|
|
{"TEMT" , 6, 1, 395, "RO", 0, 1, 1ull, 0},
|
|
{"FERR" , 7, 1, 395, "RC", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 395, "RAZ", 1, 1, 0, 0},
|
|
{"DTR" , 0, 1, 396, "R/W", 0, 1, 0ull, 0},
|
|
{"RTS" , 1, 1, 396, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT1" , 2, 1, 396, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT2" , 3, 1, 396, "R/W", 0, 1, 0ull, 0},
|
|
{"LOOP" , 4, 1, 396, "R/W", 0, 1, 0ull, 0},
|
|
{"AFCE" , 5, 1, 396, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 396, "RAZ", 0, 1, 0ull, 0},
|
|
{"DCTS" , 0, 1, 397, "RC", 0, 1, 0ull, 0},
|
|
{"DDSR" , 1, 1, 397, "RC", 0, 1, 0ull, 0},
|
|
{"TERI" , 2, 1, 397, "RC", 0, 1, 0ull, 0},
|
|
{"DDCD" , 3, 1, 397, "RC", 0, 1, 0ull, 0},
|
|
{"CTS" , 4, 1, 397, "RO", 1, 1, 0, 0},
|
|
{"DSR" , 5, 1, 397, "RO", 0, 1, 0ull, 0},
|
|
{"RI" , 6, 1, 397, "RO", 0, 1, 0ull, 0},
|
|
{"DCD" , 7, 1, 397, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 397, "RAZ", 1, 1, 0, 0},
|
|
{"RBR" , 0, 8, 398, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 398, "RAZ", 1, 1, 0, 0},
|
|
{"RFL" , 0, 7, 399, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 399, "RAZ", 1, 1, 0, 0},
|
|
{"RFWD" , 0, 8, 400, "WO", 0, 1, 0ull, 0},
|
|
{"RFPE" , 8, 1, 400, "WO", 0, 1, 0ull, 0},
|
|
{"RFFE" , 9, 1, 400, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_10_63" , 10, 54, 400, "RAZ", 1, 1, 0, 0},
|
|
{"SBCR" , 0, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 401, "RAZ", 1, 1, 0, 0},
|
|
{"SCR" , 0, 8, 402, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 402, "RAZ", 1, 1, 0, 0},
|
|
{"SFE" , 0, 1, 403, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 403, "RAZ", 1, 1, 0, 0},
|
|
{"USR" , 0, 1, 404, "WO", 0, 1, 0ull, 0},
|
|
{"SRFR" , 1, 1, 404, "WO", 0, 1, 0ull, 0},
|
|
{"STFR" , 2, 1, 404, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_63" , 3, 61, 404, "RAZ", 1, 1, 0, 0},
|
|
{"SRT" , 0, 2, 405, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 405, "RAZ", 1, 1, 0, 0},
|
|
{"SRTS" , 0, 1, 406, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 406, "RAZ", 1, 1, 0, 0},
|
|
{"STT" , 0, 2, 407, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 407, "RAZ", 1, 1, 0, 0},
|
|
{"TFL" , 0, 7, 408, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 408, "RAZ", 1, 1, 0, 0},
|
|
{"TFR" , 0, 8, 409, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 409, "RAZ", 1, 1, 0, 0},
|
|
{"THR" , 0, 8, 410, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 410, "RAZ", 1, 1, 0, 0},
|
|
{"BUSY" , 0, 1, 411, "RO", 0, 1, 0ull, 0},
|
|
{"TFNF" , 1, 1, 411, "RO", 0, 1, 1ull, 0},
|
|
{"TFE" , 2, 1, 411, "RO", 0, 1, 1ull, 0},
|
|
{"RFNE" , 3, 1, 411, "RO", 0, 1, 0ull, 0},
|
|
{"RFF" , 4, 1, 411, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 411, "RAZ", 1, 1, 0, 0},
|
|
{"ORFDAT" , 0, 1, 412, "RO", 0, 0, 0ull, 0ull},
|
|
{"IRFDAT" , 1, 1, 412, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPFDAT" , 2, 1, 412, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRQDAT" , 3, 1, 412, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 412, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MRQ_HWM" , 0, 2, 413, "R/W", 0, 0, 1ull, 1ull},
|
|
{"NBTARB" , 2, 1, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LENDIAN" , 3, 1, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 4, 1, 413, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EN" , 5, 1, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BUSY" , 6, 1, 413, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRC_STRIP" , 7, 1, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 413, "RAZ", 1, 1, 0, 0},
|
|
{"OVFENA" , 0, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IVFENA" , 1, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OTHENA" , 2, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ITHENA" , 3, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DATA_DRPENA" , 4, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IRUNENA" , 5, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ORUNENA" , 6, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 414, "RAZ", 1, 1, 0, 0},
|
|
{"IRCNT" , 0, 20, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 415, "RAZ", 1, 1, 0, 0},
|
|
{"IRHWM" , 0, 20, 416, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IBPLWM" , 20, 20, 416, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 416, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 417, "RAZ", 1, 1, 0, 0},
|
|
{"IBASE" , 3, 33, 417, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_39" , 36, 4, 417, "RAZ", 1, 1, 0, 0},
|
|
{"ISIZE" , 40, 20, 417, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 417, "RAZ", 1, 1, 0, 0},
|
|
{"IDBELL" , 0, 20, 418, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_31" , 20, 12, 418, "RAZ", 1, 1, 0, 0},
|
|
{"ITLPTR" , 32, 20, 418, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_52_63" , 52, 12, 418, "RAZ", 1, 1, 0, 0},
|
|
{"ODBLOVF" , 0, 1, 419, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IDBLOVF" , 1, 1, 419, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ORTHRESH" , 2, 1, 419, "RO", 0, 0, 0ull, 0ull},
|
|
{"IRTHRESH" , 3, 1, 419, "RO", 0, 0, 0ull, 0ull},
|
|
{"DATA_DRP" , 4, 1, 419, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IRUN" , 5, 1, 419, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ORUN" , 6, 1, 419, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 419, "RAZ", 1, 1, 0, 0},
|
|
{"ORCNT" , 0, 20, 420, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 420, "RAZ", 1, 1, 0, 0},
|
|
{"ORHWM" , 0, 20, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 421, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 422, "RAZ", 1, 1, 0, 0},
|
|
{"OBASE" , 3, 33, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_39" , 36, 4, 422, "RAZ", 1, 1, 0, 0},
|
|
{"OSIZE" , 40, 20, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 422, "RAZ", 1, 1, 0, 0},
|
|
{"ODBELL" , 0, 20, 423, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_31" , 20, 12, 423, "RAZ", 1, 1, 0, 0},
|
|
{"OTLPTR" , 32, 20, 423, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_52_63" , 52, 12, 423, "RAZ", 1, 1, 0, 0},
|
|
{"OREMCNT" , 0, 20, 424, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 424, "RAZ", 1, 1, 0, 0},
|
|
{"IREMCNT" , 32, 20, 424, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_52_63" , 52, 12, 424, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR_V" , 0, 1, 425, "R/W", 0, 1, 0ull, 0},
|
|
{"END_SWP" , 1, 2, 425, "R/W", 0, 1, 0ull, 0},
|
|
{"CA" , 3, 1, 425, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDR_IDX" , 4, 14, 425, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_31" , 18, 14, 425, "RAZ", 1, 1, 0, 0},
|
|
{"NCB_CMD" , 0, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSI" , 1, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF4" , 2, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF3" , 3, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF2" , 4, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF1" , 5, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF0" , 6, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSM1" , 7, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSM0" , 8, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_P1" , 9, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_P0" , 10, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_N" , 11, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_C1" , 12, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_C0" , 13, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_P1" , 14, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_P0" , 15, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_N" , 16, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_C1" , 17, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_C0" , 18, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_CO" , 19, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_NO" , 20, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_PO" , 21, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_CO" , 22, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_NO" , 23, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_PO" , 24, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"CPL_P1" , 25, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"CPL_P0" , 26, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"N2P1_O" , 27, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"N2P1_C" , 28, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"N2P0_O" , 29, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"N2P0_C" , 30, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"D4_PST" , 31, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"D3_PST" , 32, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"D2_PST" , 33, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"D1_PST" , 34, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"D0_PST" , 35, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_39" , 36, 4, 426, "RAZ", 1, 1, 0, 0},
|
|
{"DS_MEM" , 40, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"D4_MEM" , 41, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"D3_MEM" , 42, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"D2_MEM" , 43, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"D1_MEM" , 44, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"D0_MEM" , 45, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_POP1" , 46, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_POP0" , 47, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_48_49" , 48, 2, 426, "RAZ", 1, 1, 0, 0},
|
|
{"PKT_POF" , 50, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_PFM" , 51, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_IMEM" , 52, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCSR_SL" , 53, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCSR_ID" , 54, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCSR_CNT" , 55, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCSR_IM" , 56, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCSR_INT" , 57, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_PIF" , 58, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCR_GIM" , 59, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_60_62" , 60, 3, 426, "RAZ", 1, 1, 0, 0},
|
|
{"PKT_RDF" , 63, 1, 426, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_BLK" , 0, 1, 427, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_GL" , 1, 1, 427, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_GD" , 2, 1, 427, "RO", 0, 0, 0ull, 0ull},
|
|
{"PSC_P1" , 3, 1, 427, "RO", 0, 0, 0ull, 0ull},
|
|
{"PSC_P0" , 4, 1, 427, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_RD" , 5, 1, 427, "RO", 0, 0, 0ull, 0ull},
|
|
{"NWE_WR1" , 6, 1, 427, "RO", 0, 0, 0ull, 0ull},
|
|
{"NWE_WR0" , 7, 1, 427, "RO", 0, 0, 0ull, 0ull},
|
|
{"NWE_ST" , 8, 1, 427, "RO", 0, 0, 0ull, 0ull},
|
|
{"NRD_ST" , 9, 1, 427, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRD_ERR" , 10, 1, 427, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRD_ST1" , 11, 1, 427, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRD_ST0" , 12, 1, 427, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRD_TAG" , 13, 1, 427, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 427, "RAZ", 1, 1, 0, 0},
|
|
{"WAIT_COM" , 0, 1, 428, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAR2_CAX" , 1, 1, 428, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAR2_ESX" , 2, 2, 428, "R/W", 0, 1, 0ull, 0},
|
|
{"BAR2_ENB" , 4, 1, 428, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PTLP_RO" , 5, 1, 428, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_6_6" , 6, 1, 428, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CTLP_RO" , 7, 1, 428, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INTA_MAP" , 8, 2, 428, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTB_MAP" , 10, 2, 428, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INTC_MAP" , 12, 2, 428, "R/W", 0, 0, 2ull, 2ull},
|
|
{"INTD_MAP" , 14, 2, 428, "R/W", 0, 0, 3ull, 3ull},
|
|
{"INTA" , 16, 1, 428, "RO", 0, 0, 1ull, 1ull},
|
|
{"INTB" , 17, 1, 428, "RO", 0, 0, 1ull, 1ull},
|
|
{"INTC" , 18, 1, 428, "RO", 0, 0, 1ull, 1ull},
|
|
{"INTD" , 19, 1, 428, "RO", 0, 0, 1ull, 1ull},
|
|
{"WAITL_COM" , 20, 1, 428, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_21_63" , 21, 43, 428, "RAZ", 1, 1, 0, 0},
|
|
{"WAIT_COM" , 0, 1, 429, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAR2_CAX" , 1, 1, 429, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAR2_ESX" , 2, 2, 429, "R/W", 0, 1, 0ull, 0},
|
|
{"BAR2_ENB" , 4, 1, 429, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PTLP_RO" , 5, 1, 429, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_6_6" , 6, 1, 429, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CTLP_RO" , 7, 1, 429, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INTA_MAP" , 8, 2, 429, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTB_MAP" , 10, 2, 429, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INTC_MAP" , 12, 2, 429, "R/W", 0, 0, 2ull, 2ull},
|
|
{"INTD_MAP" , 14, 2, 429, "R/W", 0, 0, 3ull, 3ull},
|
|
{"INTA" , 16, 1, 429, "RO", 0, 0, 1ull, 1ull},
|
|
{"INTB" , 17, 1, 429, "RO", 0, 0, 1ull, 1ull},
|
|
{"INTC" , 18, 1, 429, "RO", 0, 0, 1ull, 1ull},
|
|
{"INTD" , 19, 1, 429, "RO", 0, 0, 1ull, 1ull},
|
|
{"WAITL_COM" , 20, 1, 429, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_21_63" , 21, 43, 429, "RAZ", 1, 1, 0, 0},
|
|
{"CHIP_REV" , 0, 8, 430, "RO", 1, 1, 0, 0},
|
|
{"HOST_MODE" , 8, 1, 430, "RO", 1, 1, 0, 0},
|
|
{"PKT_BP" , 9, 4, 430, "R/W", 0, 0, 15ull, 15ull},
|
|
{"ARB" , 13, 1, 430, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LNK_RST" , 14, 1, 430, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RING_EN" , 15, 1, 430, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CFG_RTRY" , 16, 16, 430, "R/W", 0, 0, 0ull, 32ull},
|
|
{"P0_NTAGS" , 32, 6, 430, "R/W", 0, 0, 32ull, 32ull},
|
|
{"P1_NTAGS" , 38, 6, 430, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_44_63" , 44, 20, 430, "RAZ", 1, 1, 0, 0},
|
|
{"C0_B0_D" , 0, 1, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C0_WI_D" , 1, 1, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C1_B0_D" , 2, 1, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C1_WI_D" , 3, 1, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C0_B1_S" , 4, 3, 431, "R/W", 0, 0, 1ull, 1ull},
|
|
{"C1_B1_S" , 7, 3, 431, "R/W", 0, 0, 1ull, 1ull},
|
|
{"C0_W_FLT" , 10, 1, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C1_W_FLT" , 11, 1, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRRS" , 12, 3, 431, "R/W", 0, 0, 2ull, 2ull},
|
|
{"MPS" , 15, 1, 431, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 431, "RAZ", 1, 1, 0, 0},
|
|
{"P0_FCNT" , 0, 6, 432, "RO", 0, 1, 0ull, 0},
|
|
{"P0_UCNT" , 6, 16, 432, "RO", 0, 1, 0ull, 0},
|
|
{"P1_FCNT" , 22, 6, 432, "RO", 0, 1, 0ull, 0},
|
|
{"P1_UCNT" , 28, 16, 432, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 432, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 17, 433, "RO", 0, 1, 0ull, 0},
|
|
{"DSEL_EXT" , 17, 1, 433, "R/W", 0, 0, 1ull, 0ull},
|
|
{"C_MUL" , 18, 5, 433, "RO", 1, 1, 0, 0},
|
|
{"QLM1_SPD" , 23, 2, 433, "RO", 1, 1, 0, 0},
|
|
{"QLM3_SPD" , 25, 2, 433, "RO", 1, 1, 0, 0},
|
|
{"QLM0_REV_LANES" , 27, 1, 433, "RO", 1, 1, 0, 0},
|
|
{"QLM2_REV_LANES" , 28, 1, 433, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 433, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_SEL" , 0, 16, 434, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 434, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 32, 435, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 7, 435, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_39_63" , 39, 25, 435, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 16, 436, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_31" , 16, 16, 436, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_6" , 0, 7, 437, "RAZ", 1, 1, 0, 0},
|
|
{"SADDR" , 7, 29, 437, "R/W", 0, 1, 0ull, 0},
|
|
{"IDLE" , 36, 1, 437, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_37_63" , 37, 27, 437, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 438, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 438, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 439, "R/W", 0, 1, 0ull, 0},
|
|
{"TIME" , 32, 32, 439, "R/W", 0, 1, 0ull, 0},
|
|
{"CNT" , 0, 32, 440, "R/W", 0, 1, 0ull, 0},
|
|
{"TIME" , 32, 32, 440, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA0" , 0, 32, 441, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA1" , 32, 32, 441, "R/W", 0, 1, 0ull, 0},
|
|
{"CSIZE" , 0, 14, 442, "R/W", 0, 1, 0ull, 0},
|
|
{"O_MODE" , 14, 1, 442, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O_ES" , 15, 2, 442, "R/W", 0, 1, 0ull, 0},
|
|
{"O_NS" , 17, 1, 442, "R/W", 0, 1, 0ull, 0},
|
|
{"O_RO" , 18, 1, 442, "R/W", 0, 1, 0ull, 0},
|
|
{"O_ADD1" , 19, 1, 442, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA_QUE" , 20, 3, 442, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB_ICHK" , 23, 9, 442, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB_DENB" , 32, 1, 442, "R/W", 0, 0, 0ull, 1ull},
|
|
{"B0_LEND" , 33, 1, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA0_ENB" , 34, 1, 442, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1_ENB" , 35, 1, 442, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA2_ENB" , 36, 1, 442, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA3_ENB" , 37, 1, 442, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA4_ENB" , 38, 1, 442, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P_32B_M" , 39, 1, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 442, "RAZ", 1, 1, 0, 0},
|
|
{"DMA_CNT" , 0, 5, 443, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 443, "RAZ", 1, 1, 0, 0},
|
|
{"DMA0_CNT" , 8, 5, 443, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_13_15" , 13, 3, 443, "RAZ", 1, 1, 0, 0},
|
|
{"DMA1_CNT" , 16, 5, 443, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_21_23" , 21, 3, 443, "RAZ", 1, 1, 0, 0},
|
|
{"DMA2_CNT" , 24, 5, 443, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_29_31" , 29, 3, 443, "RAZ", 1, 1, 0, 0},
|
|
{"DMA3_CNT" , 32, 5, 443, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_37_39" , 37, 3, 443, "RAZ", 1, 1, 0, 0},
|
|
{"DMA4_CNT" , 40, 5, 443, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_45_47" , 45, 3, 443, "RAZ", 1, 1, 0, 0},
|
|
{"PKT_CNT" , 48, 5, 443, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_53_62" , 53, 10, 443, "RAZ", 1, 1, 0, 0},
|
|
{"DMA_ARB" , 63, 1, 443, "R/W", 0, 1, 1ull, 0},
|
|
{"DMA0_CPL" , 0, 1, 444, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1_CPL" , 1, 1, 444, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PINS_ERR" , 2, 1, 444, "R/W", 0, 0, 0ull, 1ull},
|
|
{"POP_ERR" , 3, 1, 444, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PDI_ERR" , 4, 1, 444, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PGL_ERR" , 5, 1, 444, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P0_RDLK" , 6, 1, 444, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_RDLK" , 7, 1, 444, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PIN_BP" , 8, 1, 444, "R/W", 0, 0, 0ull, 1ull},
|
|
{"POUT_ERR" , 9, 1, 444, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_10_63" , 10, 54, 444, "RAZ", 0, 1, 0ull, 0},
|
|
{"DMA0_CPL" , 0, 1, 445, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1_CPL" , 1, 1, 445, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PINS_ERR" , 2, 1, 445, "R/W", 0, 0, 0ull, 1ull},
|
|
{"POP_ERR" , 3, 1, 445, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PDI_ERR" , 4, 1, 445, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PGL_ERR" , 5, 1, 445, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P0_RDLK" , 6, 1, 445, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_RDLK" , 7, 1, 445, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PIN_BP" , 8, 1, 445, "R/W", 0, 0, 0ull, 1ull},
|
|
{"POUT_ERR" , 9, 1, 445, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_10_63" , 10, 54, 445, "RAZ", 0, 1, 0ull, 0},
|
|
{"DMA0_CPL" , 0, 1, 446, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1_CPL" , 1, 1, 446, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PINS_ERR" , 2, 1, 446, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"POP_ERR" , 3, 1, 446, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PDI_ERR" , 4, 1, 446, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PGL_ERR" , 5, 1, 446, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P0_RDLK" , 6, 1, 446, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_RDLK" , 7, 1, 446, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PIN_BP" , 8, 1, 446, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"POUT_ERR" , 9, 1, 446, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 446, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RML_RTO" , 0, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RML_WTO" , 1, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BAR0_TO" , 2, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOB2BIG" , 3, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA0DBO" , 4, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1DBO" , 5, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA2DBO" , 6, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA3DBO" , 7, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA4DBO" , 8, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA0FI" , 9, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1FI" , 10, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DCNT0" , 11, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DCNT1" , 12, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DTIME0" , 13, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DTIME1" , 14, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSLDBOF" , 15, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PIDBOF" , 16, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCNT" , 17, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PTIME" , 18, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_AERI" , 19, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CRS0_ER" , 20, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_SE" , 21, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CRS0_DR" , 22, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_WAKE" , 23, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_PMEI" , 24, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_HPINT" , 25, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_AERI" , 26, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CRS1_ER" , 27, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_SE" , 28, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CRS1_DR" , 29, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_WAKE" , 30, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_PMEI" , 31, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_HPINT" , 32, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_B0" , 33, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_B1" , 34, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_B2" , 35, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_WI" , 36, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_BX" , 37, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_B0" , 38, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_B1" , 39, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_B2" , 40, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_WI" , 41, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_BX" , 42, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_B0" , 43, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_B1" , 44, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_B2" , 45, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_WI" , 46, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_BX" , 47, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_B0" , 48, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_B1" , 49, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_B2" , 50, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_WI" , 51, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_BX" , 52, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_WF" , 53, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_WF" , 54, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_WF" , 55, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_WF" , 56, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_EXC" , 57, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_EXC" , 58, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_LDWN" , 59, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_LDWN" , 60, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INT_A" , 61, 1, 447, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_62_62" , 62, 1, 447, "RAZ", 0, 1, 0ull, 0},
|
|
{"MIO_INTA" , 63, 1, 447, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RML_RTO" , 0, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RML_WTO" , 1, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BAR0_TO" , 2, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOB2BIG" , 3, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA0DBO" , 4, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1DBO" , 5, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA2DBO" , 6, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA3DBO" , 7, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA4DBO" , 8, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA0FI" , 9, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1FI" , 10, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DCNT0" , 11, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DCNT1" , 12, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DTIME0" , 13, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DTIME1" , 14, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSLDBOF" , 15, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PIDBOF" , 16, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCNT" , 17, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PTIME" , 18, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_AERI" , 19, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CRS0_ER" , 20, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_SE" , 21, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CRS0_DR" , 22, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_WAKE" , 23, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_PMEI" , 24, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_HPINT" , 25, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_AERI" , 26, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CRS1_ER" , 27, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_SE" , 28, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CRS1_DR" , 29, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_WAKE" , 30, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_PMEI" , 31, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_HPINT" , 32, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_B0" , 33, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_B1" , 34, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_B2" , 35, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_WI" , 36, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_BX" , 37, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_B0" , 38, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_B1" , 39, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_B2" , 40, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_WI" , 41, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_BX" , 42, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_B0" , 43, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_B1" , 44, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_B2" , 45, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_WI" , 46, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_BX" , 47, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_B0" , 48, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_B1" , 49, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_B2" , 50, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_WI" , 51, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_BX" , 52, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_WF" , 53, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_WF" , 54, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_WF" , 55, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_WF" , 56, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_EXC" , 57, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_EXC" , 58, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_LDWN" , 59, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_LDWN" , 60, 1, 448, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INT_A" , 61, 1, 448, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_62_63" , 62, 2, 448, "RAZ", 0, 1, 0ull, 0},
|
|
{"PSLDBOF" , 0, 6, 449, "RO", 0, 1, 0ull, 0},
|
|
{"PIDBOF" , 6, 6, 449, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_12_63" , 12, 52, 449, "RAZ", 1, 1, 0, 0},
|
|
{"RML_RTO" , 0, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RML_WTO" , 1, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BAR0_TO" , 2, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IOB2BIG" , 3, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA0DBO" , 4, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1DBO" , 5, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA2DBO" , 6, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA3DBO" , 7, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA4DBO" , 8, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA0FI" , 9, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1FI" , 10, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT0" , 11, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT1" , 12, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME0" , 13, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME1" , 14, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PSLDBOF" , 15, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PIDBOF" , 16, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT" , 17, 1, 450, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTIME" , 18, 1, 450, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_AERI" , 19, 1, 450, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRS0_ER" , 20, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_SE" , 21, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CRS0_DR" , 22, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_WAKE" , 23, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_PMEI" , 24, 1, 450, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_HPINT" , 25, 1, 450, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_AERI" , 26, 1, 450, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRS1_ER" , 27, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_SE" , 28, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CRS1_DR" , 29, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_WAKE" , 30, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_PMEI" , 31, 1, 450, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_HPINT" , 32, 1, 450, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_B0" , 33, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_B1" , 34, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_B2" , 35, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_WI" , 36, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_BX" , 37, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_B0" , 38, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_B1" , 39, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_B2" , 40, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_WI" , 41, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_BX" , 42, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_B0" , 43, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_B1" , 44, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_B2" , 45, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_WI" , 46, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_BX" , 47, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_B0" , 48, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_B1" , 49, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_B2" , 50, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_WI" , 51, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_BX" , 52, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_WF" , 53, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_WF" , 54, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_WF" , 55, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_WF" , 56, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_EXC" , 57, 1, 450, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_EXC" , 58, 1, 450, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_LDWN" , 59, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_LDWN" , 60, 1, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INT_A" , 61, 1, 450, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_62_62" , 62, 1, 450, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO_INTA" , 63, 1, 450, "RO", 0, 0, 0ull, 0ull},
|
|
{"RML_RTO" , 0, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"RML_WTO" , 1, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"BAR0_TO" , 2, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"IOB2BIG" , 3, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"DMA0DBO" , 4, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"DMA1DBO" , 5, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"DMA2DBO" , 6, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"DMA3DBO" , 7, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_8" , 8, 1, 451, "RAZ", 1, 1, 0, 0},
|
|
{"DMA0FI" , 9, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"DMA1FI" , 10, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"DCNT0" , 11, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"DCNT1" , 12, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTIME0" , 13, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTIME1" , 14, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_18" , 15, 4, 451, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"C0_AERI" , 19, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRS0_ER" , 20, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_SE" , 21, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRS0_DR" , 22, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_WAKE" , 23, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_PMEI" , 24, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_HPINT" , 25, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_AERI" , 26, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRS1_ER" , 27, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_SE" , 28, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRS1_DR" , 29, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_WAKE" , 30, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_PMEI" , 31, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_HPINT" , 32, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_B0" , 33, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_B1" , 34, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_B2" , 35, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_WI" , 36, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_BX" , 37, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_B0" , 38, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_B1" , 39, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_B2" , 40, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_WI" , 41, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_BX" , 42, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_B0" , 43, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_B1" , 44, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_B2" , 45, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_WI" , 46, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_BX" , 47, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_B0" , 48, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_B1" , 49, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_B2" , 50, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_WI" , 51, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_BX" , 52, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_WF" , 53, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_WF" , 54, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_WF" , 55, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_WF" , 56, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_EXC" , 57, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_EXC" , 58, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_LDWN" , 59, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_LDWN" , 60, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"INT_A" , 61, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_62_62" , 62, 1, 451, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO_INTA" , 63, 1, 451, "RO", 0, 0, 0ull, 0ull},
|
|
{"DATA" , 0, 64, 452, "RO", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 453, "RO", 0, 1, 0ull, 0},
|
|
{"TIMER" , 0, 10, 454, "R/W", 0, 0, 0ull, 50ull},
|
|
{"MAX_WORD" , 10, 4, 454, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 454, "RAZ", 1, 1, 0, 0},
|
|
{"BA" , 0, 30, 455, "R/W", 0, 1, 0ull, 0},
|
|
{"ROW" , 30, 1, 455, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR" , 31, 1, 455, "R/W", 0, 1, 0ull, 0},
|
|
{"NSW" , 32, 1, 455, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR" , 33, 1, 455, "R/W", 0, 1, 0ull, 0},
|
|
{"ESW" , 34, 2, 455, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR" , 36, 2, 455, "R/W", 0, 1, 0ull, 0},
|
|
{"NMERGE" , 38, 1, 455, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PORT" , 39, 2, 455, "R/W", 0, 1, 0ull, 0},
|
|
{"ZERO" , 41, 1, 455, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_42_63" , 42, 22, 455, "RAZ", 1, 1, 0, 0},
|
|
{"ENB" , 0, 64, 456, "R/W", 0, 0, 0ull, 18446744073709551615ull},
|
|
{"ENB" , 0, 64, 457, "R/W", 0, 0, 0ull, 18446744073709551615ull},
|
|
{"ENB" , 0, 64, 458, "R/W", 0, 0, 0ull, 18446744073709551615ull},
|
|
{"ENB" , 0, 64, 459, "R/W", 0, 0, 0ull, 18446744073709551615ull},
|
|
{"INTR" , 0, 64, 460, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTR" , 0, 64, 461, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTR" , 0, 64, 462, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTR" , 0, 64, 463, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_INT" , 0, 8, 464, "R/W", 0, 1, 0ull, 0},
|
|
{"RD_INT" , 8, 8, 464, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 464, "RAZ", 1, 1, 0, 0},
|
|
{"CLR" , 0, 64, 465, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLR" , 0, 64, 466, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLR" , 0, 64, 467, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLR" , 0, 64, 468, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SET" , 0, 64, 469, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SET" , 0, 64, 470, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SET" , 0, 64, 471, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SET" , 0, 64, 472, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSI_INT" , 0, 8, 473, "R/W", 0, 1, 0ull, 0},
|
|
{"CIU_INT" , 8, 8, 473, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 473, "RAZ", 1, 1, 0, 0},
|
|
{"P0_PCNT" , 0, 8, 474, "R/W", 0, 0, 128ull, 128ull},
|
|
{"P0_NCNT" , 8, 8, 474, "R/W", 0, 0, 16ull, 16ull},
|
|
{"P0_CCNT" , 16, 8, 474, "R/W", 0, 0, 128ull, 128ull},
|
|
{"P1_PCNT" , 24, 8, 474, "R/W", 0, 0, 128ull, 128ull},
|
|
{"P1_NCNT" , 32, 8, 474, "R/W", 0, 0, 16ull, 16ull},
|
|
{"P1_CCNT" , 40, 8, 474, "R/W", 0, 0, 128ull, 128ull},
|
|
{"RESERVED_48_63" , 48, 16, 474, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 0, 8, 475, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 475, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 476, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 8, 8, 476, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 476, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_15" , 0, 16, 477, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 16, 8, 477, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_24_63" , 24, 40, 477, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_23" , 0, 24, 478, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 24, 8, 478, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 478, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 479, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 32, 22, 479, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_54_63" , 54, 10, 479, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 480, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WMARK" , 32, 32, 480, "R/W", 0, 1, 4294967295ull, 0},
|
|
{"RESERVED_0_2" , 0, 3, 481, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 3, 61, 481, "R/W", 0, 1, 0ull, 0},
|
|
{"DBELL" , 0, 32, 482, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AOFF" , 32, 32, 482, "RO", 0, 1, 0ull, 0},
|
|
{"RSIZE" , 0, 32, 483, "R/W", 0, 1, 0ull, 0},
|
|
{"FCNT" , 32, 5, 483, "RO", 0, 1, 0ull, 0},
|
|
{"WRP" , 37, 9, 483, "RO", 0, 1, 0ull, 0},
|
|
{"RRP" , 46, 9, 483, "RO", 0, 1, 0ull, 0},
|
|
{"MAX" , 55, 9, 483, "RO", 0, 1, 16ull, 0},
|
|
{"RESERVED_0_5" , 0, 6, 484, "RAZ", 0, 1, 0ull, 0},
|
|
{"SKP_LEN" , 6, 7, 484, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_13_13" , 13, 1, 484, "RAZ", 0, 1, 0ull, 0},
|
|
{"PAR_MODE" , 14, 2, 484, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_20" , 16, 5, 484, "RAZ", 0, 1, 0ull, 0},
|
|
{"USE_IHDR" , 21, 1, 484, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_22_27" , 22, 6, 484, "R/W", 0, 1, 0ull, 0},
|
|
{"RSKP_LEN" , 28, 7, 484, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_35_35" , 35, 1, 484, "RAZ", 0, 1, 0ull, 0},
|
|
{"RPARMODE" , 36, 2, 484, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_38_42" , 38, 5, 484, "RAZ", 0, 1, 0ull, 0},
|
|
{"PBP" , 43, 1, 484, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 484, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_3" , 0, 4, 485, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 4, 60, 485, "R/W", 0, 1, 0ull, 0},
|
|
{"DBELL" , 0, 32, 486, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AOFF" , 32, 32, 486, "RO", 0, 1, 0ull, 0},
|
|
{"RSIZE" , 0, 32, 487, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 487, "RAZ", 0, 1, 0ull, 0},
|
|
{"PORT" , 0, 32, 488, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 488, "RAZ", 1, 1, 0, 0},
|
|
{"PORT" , 0, 32, 489, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 489, "RAZ", 1, 1, 0, 0},
|
|
{"ES" , 0, 64, 490, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR" , 0, 32, 491, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 491, "RAZ", 1, 1, 0, 0},
|
|
{"ROR" , 0, 32, 492, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 492, "RAZ", 1, 1, 0, 0},
|
|
{"DPTR" , 0, 32, 493, "R/W", 0, 0, 0ull, 4294967295ull},
|
|
{"RESERVED_32_63" , 32, 32, 493, "RAZ", 1, 1, 0, 0},
|
|
{"BP" , 0, 32, 494, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 494, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 495, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 495, "RAZ", 0, 1, 0ull, 0},
|
|
{"RD_CNT" , 0, 32, 496, "RO", 0, 1, 0ull, 0},
|
|
{"WR_CNT" , 32, 32, 496, "RO", 0, 1, 0ull, 0},
|
|
{"PP" , 0, 64, 497, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR" , 0, 1, 498, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR" , 1, 2, 498, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR" , 3, 1, 498, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_CSR" , 4, 1, 498, "R/W", 0, 0, 0ull, 1ull},
|
|
{"D_ROR" , 5, 1, 498, "R/W", 0, 1, 0ull, 0},
|
|
{"D_ESR" , 6, 2, 498, "R/W", 0, 1, 0ull, 0},
|
|
{"D_NSR" , 8, 1, 498, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP_DHI" , 9, 13, 498, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKT_RR" , 22, 1, 498, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_23_63" , 23, 41, 498, "RAZ", 1, 1, 0, 0},
|
|
{"ENB" , 0, 32, 499, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 499, "RAZ", 1, 1, 0, 0},
|
|
{"RDSIZE" , 0, 64, 500, "R/W", 0, 1, 0ull, 0},
|
|
{"IS_64B" , 0, 32, 501, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 501, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 502, "R/W", 0, 1, 0ull, 0},
|
|
{"TIME" , 32, 22, 502, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_54_63" , 54, 10, 502, "RAZ", 1, 1, 0, 0},
|
|
{"IPTR" , 0, 32, 503, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 503, "RAZ", 1, 1, 0, 0},
|
|
{"BMODE" , 0, 32, 504, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 504, "RAZ", 1, 1, 0, 0},
|
|
{"ENB" , 0, 32, 505, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 505, "RAZ", 1, 1, 0, 0},
|
|
{"WMARK" , 0, 32, 506, "R/W", 0, 0, 0ull, 14ull},
|
|
{"RESERVED_32_63" , 32, 32, 506, "RAZ", 1, 1, 0, 0},
|
|
{"PP" , 0, 64, 507, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT_RST" , 0, 32, 508, "RO", 0, 1, 0ull, 0},
|
|
{"IN_RST" , 32, 32, 508, "RO", 0, 1, 0ull, 0},
|
|
{"ES" , 0, 64, 509, "R/W", 0, 1, 0ull, 0},
|
|
{"BSIZE" , 0, 16, 510, "R/W", 0, 1, 0ull, 0},
|
|
{"ISIZE" , 16, 7, 510, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_23_63" , 23, 41, 510, "RAZ", 1, 1, 0, 0},
|
|
{"NSR" , 0, 32, 511, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 511, "RAZ", 1, 1, 0, 0},
|
|
{"ROR" , 0, 32, 512, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 512, "RAZ", 1, 1, 0, 0},
|
|
{"PORT" , 0, 32, 513, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 513, "RAZ", 1, 1, 0, 0},
|
|
{"PORT" , 0, 32, 514, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 514, "RAZ", 1, 1, 0, 0},
|
|
{"MIO" , 0, 1, 515, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX0" , 1, 1, 515, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX1" , 2, 1, 515, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPEI" , 3, 1, 515, "RO", 0, 0, 0ull, 0ull},
|
|
{"KEY" , 4, 1, 515, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPA" , 5, 1, 515, "RO", 0, 0, 0ull, 0ull},
|
|
{"DFA" , 6, 1, 515, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ZIP" , 7, 1, 515, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_8" , 8, 1, 515, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IPD" , 9, 1, 515, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 10, 1, 515, "RO", 0, 0, 0ull, 0ull},
|
|
{"TIM" , 11, 1, 515, "RO", 0, 0, 0ull, 0ull},
|
|
{"POW" , 12, 1, 515, "RO", 0, 0, 0ull, 0ull},
|
|
{"USB" , 13, 1, 515, "RO", 0, 0, 0ull, 0ull},
|
|
{"RAD" , 14, 1, 515, "RO", 0, 0, 0ull, 0ull},
|
|
{"USB1" , 15, 1, 515, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"L2C" , 16, 1, 515, "RO", 0, 0, 0ull, 0ull},
|
|
{"LMC0" , 17, 1, 515, "RO", 0, 0, 0ull, 0ull},
|
|
{"SPX0" , 18, 1, 515, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SPX1" , 19, 1, 515, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PIP" , 20, 1, 515, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_21" , 21, 1, 515, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ASXPCS0" , 22, 1, 515, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASXPCS1" , 23, 1, 515, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_27" , 24, 4, 515, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"AGL" , 28, 1, 515, "RO", 0, 0, 0ull, 0ull},
|
|
{"LMC1" , 29, 1, 515, "RO", 0, 0, 0ull, 0ull},
|
|
{"IOB" , 30, 1, 515, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 515, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DATA" , 0, 64, 516, "R/W", 0, 1, 0ull, 0},
|
|
{"CSR" , 0, 39, 517, "RO", 0, 1, 1ull, 0},
|
|
{"ARB" , 39, 1, 517, "RO", 0, 1, 0ull, 0},
|
|
{"CPL0" , 40, 12, 517, "RO", 0, 1, 1ull, 0},
|
|
{"CPL1" , 52, 12, 517, "RO", 0, 1, 1ull, 0},
|
|
{"NND" , 0, 8, 518, "RO", 0, 1, 1ull, 0},
|
|
{"NNP0" , 8, 8, 518, "RO", 0, 1, 1ull, 0},
|
|
{"CSM0" , 16, 15, 518, "RO", 0, 1, 1ull, 0},
|
|
{"CSM1" , 31, 15, 518, "RO", 0, 1, 1ull, 0},
|
|
{"RAC" , 46, 1, 518, "RO", 0, 1, 1ull, 0},
|
|
{"NPEI" , 47, 1, 518, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 518, "RAZ", 1, 1, 0, 0},
|
|
{"NSM0" , 0, 13, 519, "RO", 0, 1, 1ull, 0},
|
|
{"NSM1" , 13, 13, 519, "RO", 0, 1, 1ull, 0},
|
|
{"PSM0" , 26, 15, 519, "RO", 0, 1, 1ull, 0},
|
|
{"PSM1" , 41, 15, 519, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_56_63" , 56, 8, 519, "RAZ", 1, 1, 0, 0},
|
|
{"RD_ADDR" , 0, 48, 520, "R/W", 0, 1, 0ull, 0},
|
|
{"IOBIT" , 48, 1, 520, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LD_CMD" , 49, 2, 520, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_51_63" , 51, 13, 520, "RAZ", 1, 1, 0, 0},
|
|
{"RD_DATA" , 0, 64, 521, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_0_1" , 0, 2, 522, "RAZ", 1, 1, 0, 0},
|
|
{"WR_ADDR" , 2, 46, 522, "R/W", 0, 1, 0ull, 0},
|
|
{"IOBIT" , 48, 1, 522, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 522, "RAZ", 1, 1, 0, 0},
|
|
{"WR_DATA" , 0, 64, 523, "R/W", 0, 1, 0ull, 0},
|
|
{"WR_MASK" , 0, 8, 524, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 524, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 32, 525, "R/W", 0, 0, 0ull, 2097152ull},
|
|
{"RESERVED_32_63" , 32, 32, 525, "RAZ", 1, 1, 0, 0},
|
|
{"VENDID" , 0, 16, 526, "RO/WRSL", 0, 0, 6013ull, 6013ull},
|
|
{"DEVID" , 16, 16, 526, "RO/WRSL", 0, 0, 80ull, 80ull},
|
|
{"ISAE" , 0, 1, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSAE" , 1, 1, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ME" , 2, 1, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SCSE" , 3, 1, 527, "RO", 0, 0, 0ull, 0ull},
|
|
{"MWICE" , 4, 1, 527, "RO", 0, 0, 0ull, 0ull},
|
|
{"VPS" , 5, 1, 527, "RO", 0, 0, 0ull, 0ull},
|
|
{"PER" , 6, 1, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDS_WCC" , 7, 1, 527, "RO", 0, 0, 0ull, 0ull},
|
|
{"SEE" , 8, 1, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FBBE" , 9, 1, 527, "RO", 0, 0, 0ull, 0ull},
|
|
{"I_DIS" , 10, 1, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_18" , 11, 8, 527, "RAZ", 1, 1, 0, 0},
|
|
{"I_STAT" , 19, 1, 527, "RO", 0, 0, 0ull, 0ull},
|
|
{"CL" , 20, 1, 527, "RO", 0, 0, 1ull, 1ull},
|
|
{"M66" , 21, 1, 527, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_22" , 22, 1, 527, "RAZ", 1, 1, 0, 0},
|
|
{"FBB" , 23, 1, 527, "RO", 0, 0, 0ull, 0ull},
|
|
{"MDPE" , 24, 1, 527, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DEVT" , 25, 2, 527, "RO", 0, 0, 0ull, 0ull},
|
|
{"STA" , 27, 1, 527, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTA" , 28, 1, 527, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RMA" , 29, 1, 527, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SSE" , 30, 1, 527, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPE" , 31, 1, 527, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RID" , 0, 8, 528, "RO/WRSL", 0, 0, 8ull, 8ull},
|
|
{"PI" , 8, 8, 528, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"SC" , 16, 8, 528, "RO/WRSL", 0, 0, 48ull, 48ull},
|
|
{"BCC" , 24, 8, 528, "RO/WRSL", 0, 0, 11ull, 11ull},
|
|
{"CLS" , 0, 8, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LT" , 8, 8, 529, "RO", 0, 0, 0ull, 0ull},
|
|
{"CHF" , 16, 7, 529, "RO", 0, 0, 0ull, 0ull},
|
|
{"MFD" , 23, 1, 529, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"BIST" , 24, 8, 529, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSPC" , 0, 1, 530, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 530, "RO/WRSL", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 530, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_13" , 4, 10, 530, "RAZ", 1, 1, 0, 0},
|
|
{"LBAB" , 14, 18, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 0, 1, 531, "WORSL", 0, 0, 1ull, 1ull},
|
|
{"LMASK" , 1, 31, 531, "WORSL", 0, 0, 8191ull, 8191ull},
|
|
{"UBAB" , 0, 32, 532, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMASK" , 0, 32, 533, "WORSL", 0, 0, 0ull, 0ull},
|
|
{"MSPC" , 0, 1, 534, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 534, "RO/WRSL", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 534, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_25" , 4, 22, 534, "RAZ", 1, 1, 0, 0},
|
|
{"LBAB" , 26, 6, 534, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 0, 1, 535, "WORSL", 0, 0, 1ull, 1ull},
|
|
{"LMASK" , 1, 31, 535, "WORSL", 0, 0, 33554431ull, 33554431ull},
|
|
{"UBAB" , 0, 32, 536, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMASK" , 0, 32, 537, "WORSL", 0, 0, 0ull, 0ull},
|
|
{"MSPC" , 0, 1, 538, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 538, "RO/WRSL", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 538, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_31" , 4, 28, 538, "RAZ", 1, 1, 0, 0},
|
|
{"ENB" , 0, 1, 539, "WORSL", 0, 0, 1ull, 1ull},
|
|
{"LMASK" , 1, 31, 539, "WORSL", 0, 0, 2147483647ull, 2147483647ull},
|
|
{"RESERVED_0_6" , 0, 7, 540, "RAZ", 1, 1, 0, 0},
|
|
{"UBAB" , 7, 25, 540, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMASK" , 0, 32, 541, "WORSL", 0, 0, 127ull, 127ull},
|
|
{"CISP" , 0, 32, 542, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"SSVID" , 0, 16, 543, "RO/WRSL", 0, 0, 6013ull, 6013ull},
|
|
{"SSID" , 16, 16, 543, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"ER_EN" , 0, 1, 544, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_15" , 1, 15, 544, "RAZ", 1, 1, 0, 0},
|
|
{"ERADDR" , 16, 16, 544, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 0, 1, 545, "WORSL", 0, 0, 1ull, 1ull},
|
|
{"MASK" , 1, 31, 545, "WORSL", 0, 0, 2147483647ull, 2147483647ull},
|
|
{"CP" , 0, 8, 546, "RO/WRSL", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_8_31" , 8, 24, 546, "RAZ", 1, 1, 0, 0},
|
|
{"IL" , 0, 8, 547, "R/W", 0, 0, 255ull, 255ull},
|
|
{"INTA" , 8, 8, 547, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"MG" , 16, 8, 547, "RO", 0, 0, 0ull, 0ull},
|
|
{"ML" , 24, 8, 547, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMCID" , 0, 8, 548, "RO", 0, 0, 1ull, 0ull},
|
|
{"NCP" , 8, 8, 548, "RO/WRSL", 0, 0, 80ull, 0ull},
|
|
{"PMSV" , 16, 3, 548, "RO/WRSL", 0, 0, 3ull, 0ull},
|
|
{"PME_CLOCK" , 19, 1, 548, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 548, "RAZ", 1, 1, 0, 0},
|
|
{"DSI" , 21, 1, 548, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"AUXC" , 22, 3, 548, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"D1S" , 25, 1, 548, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"D2S" , 26, 1, 548, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PMES" , 27, 5, 548, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PS" , 0, 2, 549, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 549, "RAZ", 1, 1, 0, 0},
|
|
{"NSR" , 3, 1, 549, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 549, "RAZ", 1, 1, 0, 0},
|
|
{"PMEENS" , 8, 1, 549, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMDS" , 9, 4, 549, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMEDSIA" , 13, 2, 549, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMESS" , 15, 1, 549, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_21" , 16, 6, 549, "RAZ", 1, 1, 0, 0},
|
|
{"BD3H" , 22, 1, 549, "RO", 0, 0, 0ull, 0ull},
|
|
{"BPCCEE" , 23, 1, 549, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMDIA" , 24, 8, 549, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSICID" , 0, 8, 550, "RO", 0, 0, 5ull, 5ull},
|
|
{"NCP" , 8, 8, 550, "RO/WRSL", 0, 0, 112ull, 112ull},
|
|
{"MSIEN" , 16, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MMC" , 17, 3, 550, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"MME" , 20, 3, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M64" , 23, 1, 550, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_24_31" , 24, 8, 550, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 551, "RAZ", 1, 1, 0, 0},
|
|
{"LMSI" , 2, 30, 551, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSI" , 0, 32, 552, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSIMD" , 0, 16, 553, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_31" , 16, 16, 553, "RAZ", 1, 1, 0, 0},
|
|
{"PCIEID" , 0, 8, 554, "RO", 0, 0, 16ull, 16ull},
|
|
{"NCP" , 8, 8, 554, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PCIECV" , 16, 4, 554, "RO", 0, 0, 2ull, 2ull},
|
|
{"DPT" , 20, 4, 554, "RO", 0, 0, 0ull, 0ull},
|
|
{"SI" , 24, 1, 554, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"IMN" , 25, 5, 554, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_31" , 30, 2, 554, "RAZ", 1, 1, 0, 0},
|
|
{"MPSS" , 0, 3, 555, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"PFS" , 3, 2, 555, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"ETFS" , 5, 1, 555, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"EL0AL" , 6, 3, 555, "RO/WRSL", 0, 0, 4ull, 4ull},
|
|
{"EL1AL" , 9, 3, 555, "RO/WRSL", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_12_14" , 12, 3, 555, "RAZ", 1, 1, 0, 0},
|
|
{"RBER" , 15, 1, 555, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_16_17" , 16, 2, 555, "RAZ", 1, 1, 0, 0},
|
|
{"CSPLV" , 18, 8, 555, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSPLS" , 26, 2, 555, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_31" , 28, 4, 555, "RAZ", 1, 1, 0, 0},
|
|
{"CE_EN" , 0, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NFE_EN" , 1, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FE_EN" , 2, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UR_EN" , 3, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RO_EN" , 4, 1, 556, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MPS" , 5, 3, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ETF_EN" , 8, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PF_EN" , 9, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AP_EN" , 10, 1, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NS_EN" , 11, 1, 556, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MRRS" , 12, 3, 556, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_15_15" , 15, 1, 556, "RAZ", 1, 1, 0, 0},
|
|
{"CE_D" , 16, 1, 556, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NFE_D" , 17, 1, 556, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FE_D" , 18, 1, 556, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UR_D" , 19, 1, 556, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AP_D" , 20, 1, 556, "RO", 0, 0, 0ull, 0ull},
|
|
{"TP" , 21, 1, 556, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_31" , 22, 10, 556, "RAZ", 1, 1, 0, 0},
|
|
{"MLS" , 0, 4, 557, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"MLW" , 4, 6, 557, "RO/WRSL", 0, 0, 8ull, 8ull},
|
|
{"ASLPMS" , 10, 2, 557, "RO/WRSL", 0, 0, 3ull, 3ull},
|
|
{"L0EL" , 12, 3, 557, "RO/WRSL", 0, 0, 6ull, 6ull},
|
|
{"L1EL" , 15, 3, 557, "RO/WRSL", 0, 0, 6ull, 6ull},
|
|
{"CPM" , 18, 1, 557, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"SDERC" , 19, 1, 557, "RO", 0, 0, 0ull, 0ull},
|
|
{"DLLARC" , 20, 1, 557, "RO", 0, 0, 0ull, 0ull},
|
|
{"LBNC" , 21, 1, 557, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 557, "RAZ", 1, 1, 0, 0},
|
|
{"PNUM" , 24, 8, 557, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"ASLPC" , 0, 2, 558, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 558, "RAZ", 1, 1, 0, 0},
|
|
{"RCB" , 3, 1, 558, "RO", 0, 0, 0ull, 0ull},
|
|
{"LD" , 4, 1, 558, "RO", 0, 0, 0ull, 0ull},
|
|
{"RL" , 5, 1, 558, "RO", 0, 0, 0ull, 0ull},
|
|
{"CCC" , 6, 1, 558, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ES" , 7, 1, 558, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECPM" , 8, 1, 558, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HAWD" , 9, 1, 558, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_15" , 10, 6, 558, "RAZ", 1, 1, 0, 0},
|
|
{"LS" , 16, 4, 558, "RO", 0, 0, 1ull, 1ull},
|
|
{"NLW" , 20, 6, 558, "RO", 0, 0, 0ull, 8ull},
|
|
{"RESERVED_26_26" , 26, 1, 558, "RAZ", 1, 1, 0, 0},
|
|
{"LT" , 27, 1, 558, "RO", 0, 0, 0ull, 0ull},
|
|
{"SCC" , 28, 1, 558, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"DLLA" , 29, 1, 558, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_31" , 30, 2, 558, "RAZ", 1, 1, 0, 0},
|
|
{"ABP" , 0, 1, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PCP" , 1, 1, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"MRLSP" , 2, 1, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"AIP" , 3, 1, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PIP" , 4, 1, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"HP_S" , 5, 1, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"HP_C" , 6, 1, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"SP_LV" , 7, 8, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"SP_LS" , 15, 2, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"EMIP" , 17, 1, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"NCCS" , 18, 1, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PS_NUM" , 19, 13, 559, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"ABP_EN" , 0, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PF_EN" , 1, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRLS_EN" , 2, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PD_EN" , 3, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CCINT_EN" , 4, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HPINT_EN" , 5, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AIC" , 6, 2, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PIC" , 8, 2, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCC" , 10, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EMIC" , 11, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLLS_EN" , 12, 1, 560, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 560, "RAZ", 1, 1, 0, 0},
|
|
{"ABP_D" , 16, 1, 560, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PF_D" , 17, 1, 560, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRLS_C" , 18, 1, 560, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PD_C" , 19, 1, 560, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CCINT_D" , 20, 1, 560, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRLSS" , 21, 1, 560, "RO", 0, 0, 0ull, 0ull},
|
|
{"PDS" , 22, 1, 560, "RO", 0, 0, 0ull, 0ull},
|
|
{"EMIS" , 23, 1, 560, "RO", 0, 0, 0ull, 0ull},
|
|
{"DLLS_C" , 24, 1, 560, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_31" , 25, 7, 560, "RAZ", 1, 1, 0, 0},
|
|
{"CTRS" , 0, 4, 561, "RO", 0, 0, 0ull, 0ull},
|
|
{"CTDS" , 4, 1, 561, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_5_31" , 5, 27, 561, "RAZ", 1, 1, 0, 0},
|
|
{"CTV" , 0, 4, 562, "RO", 0, 0, 0ull, 0ull},
|
|
{"CTD" , 4, 1, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 562, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 563, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 564, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 565, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 566, "RAZ", 1, 1, 0, 0},
|
|
{"PCIEEC" , 0, 16, 567, "RO", 0, 0, 1ull, 0ull},
|
|
{"CV" , 16, 4, 567, "RO", 0, 0, 1ull, 0ull},
|
|
{"NCO" , 20, 12, 567, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_3" , 0, 4, 568, "RAZ", 1, 1, 0, 0},
|
|
{"DLPES" , 4, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SDES" , 5, 1, 568, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_11" , 6, 6, 568, "RAZ", 1, 1, 0, 0},
|
|
{"PTLPS" , 12, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCPES" , 13, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CTS" , 14, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CAS" , 15, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UCS" , 16, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ROS" , 17, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MTLPS" , 18, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ECRCES" , 19, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"URES" , 20, 1, 568, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 568, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_3" , 0, 4, 569, "RAZ", 1, 1, 0, 0},
|
|
{"DLPEM" , 4, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SDEM" , 5, 1, 569, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_11" , 6, 6, 569, "RAZ", 1, 1, 0, 0},
|
|
{"PTLPM" , 12, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCPEM" , 13, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CTM" , 14, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAM" , 15, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UCM" , 16, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROM" , 17, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MTLPM" , 18, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECRCEM" , 19, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UREM" , 20, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 569, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_3" , 0, 4, 570, "RAZ", 1, 1, 0, 0},
|
|
{"DLPES" , 4, 1, 570, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SDES" , 5, 1, 570, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_11" , 6, 6, 570, "RAZ", 1, 1, 0, 0},
|
|
{"PTLPS" , 12, 1, 570, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCPES" , 13, 1, 570, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTS" , 14, 1, 570, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAS" , 15, 1, 570, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UCS" , 16, 1, 570, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROS" , 17, 1, 570, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MTLPS" , 18, 1, 570, "R/W", 0, 0, 1ull, 1ull},
|
|
{"ECRCES" , 19, 1, 570, "R/W", 0, 0, 0ull, 0ull},
|
|
{"URES" , 20, 1, 570, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 570, "RAZ", 1, 1, 0, 0},
|
|
{"RES" , 0, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_5" , 1, 5, 571, "RAZ", 1, 1, 0, 0},
|
|
{"BTLPS" , 6, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BDLLPS" , 7, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RNRS" , 8, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 571, "RAZ", 1, 1, 0, 0},
|
|
{"RTTS" , 12, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ANFES" , 13, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_31" , 14, 18, 571, "RAZ", 1, 1, 0, 0},
|
|
{"REM" , 0, 1, 572, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_5" , 1, 5, 572, "RAZ", 1, 1, 0, 0},
|
|
{"BTLPM" , 6, 1, 572, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BDLLPM" , 7, 1, 572, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNRM" , 8, 1, 572, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 572, "RAZ", 1, 1, 0, 0},
|
|
{"RTTM" , 12, 1, 572, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ANFEM" , 13, 1, 572, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_14_31" , 14, 18, 572, "RAZ", 1, 1, 0, 0},
|
|
{"FEP" , 0, 5, 573, "RO", 0, 0, 0ull, 0ull},
|
|
{"GC" , 5, 1, 573, "RO", 0, 0, 1ull, 1ull},
|
|
{"GE" , 6, 1, 573, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CC" , 7, 1, 573, "RO", 0, 0, 1ull, 1ull},
|
|
{"CE" , 8, 1, 573, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_31" , 9, 23, 573, "RAZ", 1, 1, 0, 0},
|
|
{"DWORD1" , 0, 32, 574, "RO", 0, 0, 0ull, 0ull},
|
|
{"DWORD2" , 0, 32, 575, "RO", 0, 0, 0ull, 0ull},
|
|
{"DWORD3" , 0, 32, 576, "RO", 0, 0, 0ull, 0ull},
|
|
{"DWORD4" , 0, 32, 577, "RO", 0, 0, 0ull, 0ull},
|
|
{"RTLTL" , 0, 16, 578, "R/W", 0, 0, 4143ull, 4143ull},
|
|
{"RTL" , 16, 16, 578, "R/W", 0, 0, 12429ull, 12429ull},
|
|
{"OMR" , 0, 32, 579, "R/W", 0, 1, 4294967295ull, 0},
|
|
{"LINK_NUM" , 0, 8, 580, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_14" , 8, 7, 580, "RAZ", 1, 1, 0, 0},
|
|
{"FORCE_LINK" , 15, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LINK_STATE" , 16, 6, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 580, "RAZ", 1, 1, 0, 0},
|
|
{"LPEC" , 24, 8, 580, "R/W", 0, 0, 7ull, 7ull},
|
|
{"ACK_FREQ" , 0, 8, 581, "R/W", 0, 0, 0ull, 0ull},
|
|
{"N_FTS" , 8, 8, 581, "R/W", 0, 0, 128ull, 128ull},
|
|
{"N_FTS_CC" , 16, 8, 581, "R/W", 0, 0, 128ull, 128ull},
|
|
{"L0EL" , 24, 3, 581, "R/W", 0, 0, 3ull, 3ull},
|
|
{"L1EL" , 27, 3, 581, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_30_31" , 30, 2, 581, "RAZ", 1, 1, 0, 0},
|
|
{"OMR" , 0, 1, 582, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SD" , 1, 1, 582, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LE" , 2, 1, 582, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RA" , 3, 1, 582, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_4" , 4, 1, 582, "RAZ", 1, 1, 0, 0},
|
|
{"DLLLE" , 5, 1, 582, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_6" , 6, 1, 582, "RAZ", 1, 1, 0, 0},
|
|
{"FLM" , 7, 1, 582, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_15" , 8, 8, 582, "RO", 0, 0, 1ull, 1ull},
|
|
{"LME" , 16, 6, 582, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_22_24" , 22, 3, 582, "RAZ", 1, 1, 0, 0},
|
|
{"ECCRC" , 25, 1, 582, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_31" , 26, 6, 582, "RAZ", 1, 1, 0, 0},
|
|
{"ILST" , 0, 24, 583, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCD" , 24, 1, 583, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ACK_NAK" , 25, 1, 583, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_30" , 26, 5, 583, "RAZ", 1, 1, 0, 0},
|
|
{"DLLD" , 31, 1, 583, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NTSS" , 0, 4, 584, "R/W", 0, 0, 10ull, 10ull},
|
|
{"RESERVED_4_7" , 4, 4, 584, "RO", 1, 1, 0, 0},
|
|
{"NSKPS" , 8, 3, 584, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_11_13" , 11, 3, 584, "RAZ", 1, 1, 0, 0},
|
|
{"TMRT" , 14, 5, 584, "R/W", 0, 0, 8ull, 8ull},
|
|
{"TMANLT" , 19, 5, 584, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TMFCWT" , 24, 5, 584, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_31" , 29, 3, 584, "RO", 1, 1, 0, 0},
|
|
{"SKPIV" , 0, 11, 585, "R/W", 0, 0, 1280ull, 1280ull},
|
|
{"RESERVED_11_14" , 11, 4, 585, "RAZ", 1, 1, 0, 0},
|
|
{"DFCWT" , 15, 1, 585, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_FUN" , 16, 1, 585, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_POIS_FILT" , 17, 1, 585, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_BAR_MATCH" , 18, 1, 585, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CFG1_FILT" , 19, 1, 585, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_LK_FILT" , 20, 1, 585, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_TAG_ERR" , 21, 1, 585, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_RID_ERR" , 22, 1, 585, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_FUN_ERR" , 23, 1, 585, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_TC_ERR" , 24, 1, 585, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_ATTR_ERR" , 25, 1, 585, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_LEN_ERR" , 26, 1, 585, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_ECRC_FILT" , 27, 1, 585, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_ECRC_FILT" , 28, 1, 585, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSG_CTRL" , 29, 1, 585, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_IO_FILT" , 30, 1, 585, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CFG0_FILT" , 31, 1, 585, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_VEND0_DRP" , 0, 1, 586, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_VEND1_DRP" , 1, 1, 586, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_31" , 2, 30, 586, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_INFO_L32" , 0, 32, 587, "RO", 0, 0, 0ull, 0ull},
|
|
{"DBG_INFO_U32" , 0, 32, 588, "RO", 0, 0, 0ull, 0ull},
|
|
{"TPDFCC" , 0, 12, 589, "RO", 0, 0, 0ull, 0ull},
|
|
{"TPHFCC" , 12, 8, 589, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 589, "RAZ", 1, 1, 0, 0},
|
|
{"TCDFCC" , 0, 12, 590, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCHFCC" , 12, 8, 590, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 590, "RAZ", 1, 1, 0, 0},
|
|
{"TCDFCC" , 0, 12, 591, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCHFCC" , 12, 8, 591, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 591, "RAZ", 1, 1, 0, 0},
|
|
{"RTLPFCCNR" , 0, 1, 592, "RO", 0, 0, 0ull, 0ull},
|
|
{"TRBNE" , 1, 1, 592, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQNE" , 2, 1, 592, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_31" , 3, 29, 592, "RAZ", 1, 1, 0, 0},
|
|
{"WRR_VC0" , 0, 8, 593, "RO", 0, 0, 15ull, 15ull},
|
|
{"WRR_VC1" , 8, 8, 593, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC2" , 16, 8, 593, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC3" , 24, 8, 593, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC4" , 0, 8, 594, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC5" , 8, 8, 594, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC6" , 16, 8, 594, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC7" , 24, 8, 594, "RO", 0, 0, 0ull, 0ull},
|
|
{"DATA_CREDITS" , 0, 12, 595, "RO/WRSL", 0, 0, 128ull, 128ull},
|
|
{"HEADER_CREDITS" , 12, 8, 595, "RO/WRSL", 0, 0, 35ull, 35ull},
|
|
{"RESERVED_20_20" , 20, 1, 595, "RAZ", 1, 1, 0, 0},
|
|
{"QUEUE_MODE" , 21, 3, 595, "RO/WRSL", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_24_29" , 24, 6, 595, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE_ORDERING" , 30, 1, 595, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"RX_QUEUE_ORDER" , 31, 1, 595, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"DATA_CREDITS" , 0, 12, 596, "RO/WRSL", 0, 0, 4ull, 4ull},
|
|
{"HEADER_CREDITS" , 12, 8, 596, "RO/WRSL", 0, 0, 8ull, 8ull},
|
|
{"RESERVED_20_20" , 20, 1, 596, "RAZ", 1, 1, 0, 0},
|
|
{"QUEUE_MODE" , 21, 3, 596, "RO/WRSL", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_24_31" , 24, 8, 596, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_CREDITS" , 0, 12, 597, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"HEADER_CREDITS" , 12, 8, 597, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 597, "RAZ", 1, 1, 0, 0},
|
|
{"QUEUE_MODE" , 21, 3, 597, "RO/WRSL", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_24_31" , 24, 8, 597, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_DEPTH" , 0, 14, 598, "RO/WRSL", 0, 0, 331ull, 331ull},
|
|
{"RESERVED_14_15" , 14, 2, 598, "RAZ", 1, 1, 0, 0},
|
|
{"HEADER_DEPTH" , 16, 10, 598, "RO/WRSL", 0, 0, 41ull, 41ull},
|
|
{"RESERVED_26_31" , 26, 6, 598, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_DEPTH" , 0, 14, 599, "RO/WRSL", 0, 0, 56ull, 56ull},
|
|
{"RESERVED_14_15" , 14, 2, 599, "RAZ", 1, 1, 0, 0},
|
|
{"HEADER_DEPTH" , 16, 10, 599, "RO/WRSL", 0, 0, 14ull, 14ull},
|
|
{"RESERVED_26_31" , 26, 6, 599, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_DEPTH" , 0, 14, 600, "RO/WRSL", 0, 0, 360ull, 360ull},
|
|
{"RESERVED_14_15" , 14, 2, 600, "RAZ", 1, 1, 0, 0},
|
|
{"HEADER_DEPTH" , 16, 10, 600, "RO/WRSL", 0, 0, 70ull, 70ull},
|
|
{"RESERVED_26_31" , 26, 6, 600, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_STAT" , 0, 32, 601, "RO", 0, 0, 0ull, 0ull},
|
|
{"PHY_CTRL" , 0, 32, 602, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VENDID" , 0, 16, 603, "R/W", 0, 0, 6013ull, 6013ull},
|
|
{"DEVID" , 16, 16, 603, "R/W", 0, 0, 80ull, 80ull},
|
|
{"ISAE" , 0, 1, 604, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSAE" , 1, 1, 604, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ME" , 2, 1, 604, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SCSE" , 3, 1, 604, "RO", 0, 0, 0ull, 0ull},
|
|
{"MWICE" , 4, 1, 604, "RO", 0, 0, 0ull, 0ull},
|
|
{"VPS" , 5, 1, 604, "RO", 0, 0, 0ull, 0ull},
|
|
{"PER" , 6, 1, 604, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDS_WCC" , 7, 1, 604, "RO", 0, 0, 0ull, 0ull},
|
|
{"SEE" , 8, 1, 604, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FBBE" , 9, 1, 604, "RO", 0, 0, 0ull, 0ull},
|
|
{"I_DIS" , 10, 1, 604, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_18" , 11, 8, 604, "RAZ", 1, 1, 0, 0},
|
|
{"I_STAT" , 19, 1, 604, "RO", 0, 0, 0ull, 0ull},
|
|
{"CL" , 20, 1, 604, "RO", 0, 0, 1ull, 1ull},
|
|
{"M66" , 21, 1, 604, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_22" , 22, 1, 604, "RO", 1, 1, 0, 0},
|
|
{"FBB" , 23, 1, 604, "RO", 0, 0, 0ull, 0ull},
|
|
{"MDPE" , 24, 1, 604, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DEVT" , 25, 2, 604, "RO", 0, 0, 0ull, 0ull},
|
|
{"STA" , 27, 1, 604, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTA" , 28, 1, 604, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RMA" , 29, 1, 604, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SSE" , 30, 1, 604, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPE" , 31, 1, 604, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RID" , 0, 8, 605, "R/W", 0, 0, 8ull, 8ull},
|
|
{"PI" , 8, 8, 605, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SC" , 16, 8, 605, "R/W", 0, 0, 48ull, 48ull},
|
|
{"BCC" , 24, 8, 605, "R/W", 0, 0, 11ull, 11ull},
|
|
{"CLS" , 0, 8, 606, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LT" , 8, 8, 606, "RO", 0, 0, 0ull, 0ull},
|
|
{"CHF" , 16, 7, 606, "RO", 0, 0, 1ull, 1ull},
|
|
{"MFD" , 23, 1, 606, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BIST" , 24, 8, 606, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_31" , 0, 32, 607, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 608, "RO", 1, 1, 0, 0},
|
|
{"PBNUM" , 0, 8, 609, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SBNUM" , 8, 8, 609, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SUBBNUM" , 16, 8, 609, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SLT" , 24, 8, 609, "RO", 0, 0, 0ull, 0ull},
|
|
{"IO32A" , 0, 1, 610, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_3" , 1, 3, 610, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LIO_BASE" , 4, 4, 610, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IO32B" , 8, 1, 610, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_9_11" , 9, 3, 610, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LIO_LIMI" , 12, 4, 610, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_20" , 16, 5, 610, "RAZ", 1, 1, 0, 0},
|
|
{"M66" , 21, 1, 610, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_22" , 22, 1, 610, "RO", 1, 1, 0, 0},
|
|
{"FBB" , 23, 1, 610, "RO", 0, 0, 0ull, 0ull},
|
|
{"MDPE" , 24, 1, 610, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DEVT" , 25, 2, 610, "RO", 0, 0, 0ull, 0ull},
|
|
{"STA" , 27, 1, 610, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTA" , 28, 1, 610, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RMA" , 29, 1, 610, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SSE" , 30, 1, 610, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPE" , 31, 1, 610, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_3" , 0, 4, 611, "RO", 1, 1, 0, 0},
|
|
{"MB_ADDR" , 4, 12, 611, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_19" , 16, 4, 611, "RO", 1, 1, 0, 0},
|
|
{"ML_ADDR" , 20, 12, 611, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM64A" , 0, 1, 612, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_3" , 1, 3, 612, "RO", 1, 1, 0, 0},
|
|
{"LMEM_BASE" , 4, 12, 612, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM64B" , 16, 1, 612, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_17_19" , 17, 3, 612, "RO", 1, 1, 0, 0},
|
|
{"LMEM_LIMIT" , 20, 12, 612, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMEM_BASE" , 0, 32, 613, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMEM_LIMIT" , 0, 32, 614, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UIO_BASE" , 0, 16, 615, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UIO_LIMIT" , 16, 16, 615, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP" , 0, 8, 616, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_8_31" , 8, 24, 616, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 617, "RAZ", 1, 1, 0, 0},
|
|
{"IL" , 0, 8, 618, "R/W", 0, 0, 255ull, 255ull},
|
|
{"INTA" , 8, 8, 618, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PERE" , 16, 1, 618, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SEE" , 17, 1, 618, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ISAE" , 18, 1, 618, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VGAE" , 19, 1, 618, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VGA16D" , 20, 1, 618, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAM" , 21, 1, 618, "RO", 0, 0, 0ull, 0ull},
|
|
{"SBRST" , 22, 1, 618, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FBBE" , 23, 1, 618, "RO", 0, 0, 0ull, 0ull},
|
|
{"PDT" , 24, 1, 618, "RO", 0, 0, 0ull, 0ull},
|
|
{"SDT" , 25, 1, 618, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTS" , 26, 1, 618, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTSEES" , 27, 1, 618, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_31" , 28, 4, 618, "RO", 1, 1, 0, 0},
|
|
{"PMCID" , 0, 8, 619, "RO", 0, 0, 1ull, 1ull},
|
|
{"NCP" , 8, 8, 619, "R/W", 0, 0, 80ull, 80ull},
|
|
{"PMSV" , 16, 3, 619, "R/W", 0, 0, 3ull, 3ull},
|
|
{"PME_CLOCK" , 19, 1, 619, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 619, "RAZ", 1, 1, 0, 0},
|
|
{"DSI" , 21, 1, 619, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AUXC" , 22, 3, 619, "R/W", 0, 0, 0ull, 0ull},
|
|
{"D1S" , 25, 1, 619, "R/W", 0, 0, 0ull, 0ull},
|
|
{"D2S" , 26, 1, 619, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMES" , 27, 5, 619, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PS" , 0, 2, 620, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 620, "RAZ", 1, 1, 0, 0},
|
|
{"NSR" , 3, 1, 620, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 620, "RAZ", 1, 1, 0, 0},
|
|
{"PMEENS" , 8, 1, 620, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMDS" , 9, 4, 620, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMEDSIA" , 13, 2, 620, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMESS" , 15, 1, 620, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_21" , 16, 6, 620, "RAZ", 1, 1, 0, 0},
|
|
{"BD3H" , 22, 1, 620, "RO", 0, 0, 0ull, 0ull},
|
|
{"BPCCEE" , 23, 1, 620, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMDIA" , 24, 8, 620, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSICID" , 0, 8, 621, "RO", 0, 0, 5ull, 5ull},
|
|
{"NCP" , 8, 8, 621, "R/W", 0, 0, 112ull, 112ull},
|
|
{"MSIEN" , 16, 1, 621, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MMC" , 17, 3, 621, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MME" , 20, 3, 621, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M64" , 23, 1, 621, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_24_31" , 24, 8, 621, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 622, "RAZ", 1, 1, 0, 0},
|
|
{"LMSI" , 2, 30, 622, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSI" , 0, 32, 623, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSIMD" , 0, 16, 624, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_31" , 16, 16, 624, "RAZ", 1, 1, 0, 0},
|
|
{"PCIEID" , 0, 8, 625, "RO", 0, 0, 16ull, 16ull},
|
|
{"NCP" , 8, 8, 625, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCIECV" , 16, 4, 625, "RO", 0, 0, 2ull, 2ull},
|
|
{"DPT" , 20, 4, 625, "RO", 0, 0, 4ull, 4ull},
|
|
{"SI" , 24, 1, 625, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IMN" , 25, 5, 625, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_31" , 30, 2, 625, "RAZ", 1, 1, 0, 0},
|
|
{"MPSS" , 0, 3, 626, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PFS" , 3, 2, 626, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ETFS" , 5, 1, 626, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EL0AL" , 6, 3, 626, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EL1AL" , 9, 3, 626, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_14" , 12, 3, 626, "RAZ", 1, 1, 0, 0},
|
|
{"RBER" , 15, 1, 626, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_16_17" , 16, 2, 626, "RAZ", 1, 1, 0, 0},
|
|
{"CSPLV" , 18, 8, 626, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSPLS" , 26, 2, 626, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_31" , 28, 4, 626, "RAZ", 1, 1, 0, 0},
|
|
{"CE_EN" , 0, 1, 627, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NFE_EN" , 1, 1, 627, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FE_EN" , 2, 1, 627, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UR_EN" , 3, 1, 627, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RO_EN" , 4, 1, 627, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MPS" , 5, 3, 627, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ETF_EN" , 8, 1, 627, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PF_EN" , 9, 1, 627, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AP_EN" , 10, 1, 627, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NS_EN" , 11, 1, 627, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MRRS" , 12, 3, 627, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_15_15" , 15, 1, 627, "RAZ", 1, 1, 0, 0},
|
|
{"CE_D" , 16, 1, 627, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NFE_D" , 17, 1, 627, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FE_D" , 18, 1, 627, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UR_D" , 19, 1, 627, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AP_D" , 20, 1, 627, "RO", 0, 0, 0ull, 0ull},
|
|
{"TP" , 21, 1, 627, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_31" , 22, 10, 627, "RAZ", 1, 1, 0, 0},
|
|
{"MLS" , 0, 4, 628, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MLW" , 4, 6, 628, "R/W", 0, 0, 8ull, 8ull},
|
|
{"ASLPMS" , 10, 2, 628, "R/W", 0, 0, 3ull, 3ull},
|
|
{"L0EL" , 12, 3, 628, "R/W", 0, 0, 6ull, 6ull},
|
|
{"L1EL" , 15, 3, 628, "R/W", 0, 0, 6ull, 6ull},
|
|
{"CPM" , 18, 1, 628, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SDERC" , 19, 1, 628, "RO", 0, 0, 0ull, 0ull},
|
|
{"DLLARC" , 20, 1, 628, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBNC" , 21, 1, 628, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_22_23" , 22, 2, 628, "RAZ", 1, 1, 0, 0},
|
|
{"PNUM" , 24, 8, 628, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ASLPC" , 0, 2, 629, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 629, "RAZ", 1, 1, 0, 0},
|
|
{"RCB" , 3, 1, 629, "R/W", 0, 0, 1ull, 1ull},
|
|
{"LD" , 4, 1, 629, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RL" , 5, 1, 629, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CCC" , 6, 1, 629, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ES" , 7, 1, 629, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECPM" , 8, 1, 629, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HAWD" , 9, 1, 629, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LBM_INT_ENB" , 10, 1, 629, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LAB_INT_ENB" , 11, 1, 629, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_15" , 12, 4, 629, "RAZ", 1, 1, 0, 0},
|
|
{"LS" , 16, 4, 629, "RO", 0, 0, 1ull, 1ull},
|
|
{"NLW" , 20, 6, 629, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_26" , 26, 1, 629, "RAZ", 1, 1, 0, 0},
|
|
{"LT" , 27, 1, 629, "RO", 0, 0, 0ull, 0ull},
|
|
{"SCC" , 28, 1, 629, "R/W", 0, 0, 1ull, 0ull},
|
|
{"DLLA" , 29, 1, 629, "RO", 0, 0, 0ull, 1ull},
|
|
{"LBM" , 30, 1, 629, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LAB" , 31, 1, 629, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ABP" , 0, 1, 630, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCP" , 1, 1, 630, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRLSP" , 2, 1, 630, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AIP" , 3, 1, 630, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PIP" , 4, 1, 630, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HP_S" , 5, 1, 630, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HP_C" , 6, 1, 630, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SP_LV" , 7, 8, 630, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SP_LS" , 15, 2, 630, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EMIP" , 17, 1, 630, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NCCS" , 18, 1, 630, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PS_NUM" , 19, 13, 630, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ABP_EN" , 0, 1, 631, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PF_EN" , 1, 1, 631, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRLS_EN" , 2, 1, 631, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PD_EN" , 3, 1, 631, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CCINT_EN" , 4, 1, 631, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HPINT_EN" , 5, 1, 631, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AIC" , 6, 2, 631, "R/W", 0, 0, 3ull, 3ull},
|
|
{"PIC" , 8, 2, 631, "R/W", 0, 0, 3ull, 3ull},
|
|
{"PCC" , 10, 1, 631, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EMIC" , 11, 1, 631, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLLS_EN" , 12, 1, 631, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 631, "RAZ", 1, 1, 0, 0},
|
|
{"ABP_D" , 16, 1, 631, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PF_D" , 17, 1, 631, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRLS_C" , 18, 1, 631, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PD_C" , 19, 1, 631, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CCINT_D" , 20, 1, 631, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRLSS" , 21, 1, 631, "RO", 0, 0, 0ull, 0ull},
|
|
{"PDS" , 22, 1, 631, "RO", 0, 0, 1ull, 1ull},
|
|
{"EMIS" , 23, 1, 631, "RO", 0, 0, 0ull, 0ull},
|
|
{"DLLS_C" , 24, 1, 631, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_31" , 25, 7, 631, "RAZ", 1, 1, 0, 0},
|
|
{"SECEE" , 0, 1, 632, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SENFEE" , 1, 1, 632, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SEFEE" , 2, 1, 632, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMEIE" , 3, 1, 632, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CRSSVE" , 4, 1, 632, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_15" , 5, 11, 632, "RAZ", 1, 1, 0, 0},
|
|
{"CRSSV" , 16, 1, 632, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 632, "RAZ", 1, 1, 0, 0},
|
|
{"PME_RID" , 0, 16, 633, "RO", 0, 0, 0ull, 0ull},
|
|
{"PME_STAT" , 16, 1, 633, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PME_PEND" , 17, 1, 633, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_31" , 18, 14, 633, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CTRS" , 0, 4, 634, "RO", 0, 0, 0ull, 0ull},
|
|
{"CTDS" , 4, 1, 634, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_5_31" , 5, 27, 634, "RAZ", 1, 1, 0, 0},
|
|
{"CTV" , 0, 4, 635, "RO", 0, 0, 0ull, 0ull},
|
|
{"CTD" , 4, 1, 635, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 635, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 636, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 637, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 638, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 639, "RAZ", 1, 1, 0, 0},
|
|
{"PCIEEC" , 0, 16, 640, "RO", 0, 0, 1ull, 1ull},
|
|
{"CV" , 16, 4, 640, "RO", 0, 0, 1ull, 1ull},
|
|
{"NCO" , 20, 12, 640, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_3" , 0, 4, 641, "RAZ", 1, 1, 0, 0},
|
|
{"DLPES" , 4, 1, 641, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SDES" , 5, 1, 641, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_11" , 6, 6, 641, "RAZ", 1, 1, 0, 0},
|
|
{"PTLPS" , 12, 1, 641, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCPES" , 13, 1, 641, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CTS" , 14, 1, 641, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CAS" , 15, 1, 641, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UCS" , 16, 1, 641, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ROS" , 17, 1, 641, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MTLPS" , 18, 1, 641, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ECRCES" , 19, 1, 641, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"URES" , 20, 1, 641, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 641, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_3" , 0, 4, 642, "RAZ", 1, 1, 0, 0},
|
|
{"DLPEM" , 4, 1, 642, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SDEM" , 5, 1, 642, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_11" , 6, 6, 642, "RAZ", 1, 1, 0, 0},
|
|
{"PTLPM" , 12, 1, 642, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCPEM" , 13, 1, 642, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CTM" , 14, 1, 642, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAM" , 15, 1, 642, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UCM" , 16, 1, 642, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROM" , 17, 1, 642, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MTLPM" , 18, 1, 642, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECRCEM" , 19, 1, 642, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UREM" , 20, 1, 642, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 642, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_3" , 0, 4, 643, "RAZ", 1, 1, 0, 0},
|
|
{"DLPES" , 4, 1, 643, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SDES" , 5, 1, 643, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_11" , 6, 6, 643, "RAZ", 1, 1, 0, 0},
|
|
{"PTLPS" , 12, 1, 643, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCPES" , 13, 1, 643, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTS" , 14, 1, 643, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAS" , 15, 1, 643, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UCS" , 16, 1, 643, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROS" , 17, 1, 643, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MTLPS" , 18, 1, 643, "R/W", 0, 0, 1ull, 1ull},
|
|
{"ECRCES" , 19, 1, 643, "R/W", 0, 0, 0ull, 0ull},
|
|
{"URES" , 20, 1, 643, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 643, "RAZ", 1, 1, 0, 0},
|
|
{"RES" , 0, 1, 644, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_5" , 1, 5, 644, "RAZ", 1, 1, 0, 0},
|
|
{"BTLPS" , 6, 1, 644, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BDLLPS" , 7, 1, 644, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RNRS" , 8, 1, 644, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 644, "RAZ", 1, 1, 0, 0},
|
|
{"RTTS" , 12, 1, 644, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ANFES" , 13, 1, 644, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_31" , 14, 18, 644, "RAZ", 1, 1, 0, 0},
|
|
{"REM" , 0, 1, 645, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_5" , 1, 5, 645, "RAZ", 1, 1, 0, 0},
|
|
{"BTLPM" , 6, 1, 645, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BDLLPM" , 7, 1, 645, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNRM" , 8, 1, 645, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 645, "RAZ", 1, 1, 0, 0},
|
|
{"RTTM" , 12, 1, 645, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ANFEM" , 13, 1, 645, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_14_31" , 14, 18, 645, "RAZ", 1, 1, 0, 0},
|
|
{"FEP" , 0, 5, 646, "RO", 0, 0, 0ull, 0ull},
|
|
{"GC" , 5, 1, 646, "RO", 0, 0, 1ull, 1ull},
|
|
{"GE" , 6, 1, 646, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CC" , 7, 1, 646, "RO", 0, 0, 1ull, 1ull},
|
|
{"CE" , 8, 1, 646, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_31" , 9, 23, 646, "RAZ", 1, 1, 0, 0},
|
|
{"DWORD1" , 0, 32, 647, "RO", 0, 0, 0ull, 0ull},
|
|
{"DWORD2" , 0, 32, 648, "RO", 0, 0, 0ull, 0ull},
|
|
{"DWORD3" , 0, 32, 649, "RO", 0, 0, 0ull, 0ull},
|
|
{"DWORD4" , 0, 32, 650, "RO", 0, 0, 0ull, 0ull},
|
|
{"CERE" , 0, 1, 651, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NFERE" , 1, 1, 651, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FERE" , 2, 1, 651, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_31" , 3, 29, 651, "RAZ", 1, 1, 0, 0},
|
|
{"ECR" , 0, 1, 652, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MULTI_ECR" , 1, 1, 652, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EFNFR" , 2, 1, 652, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MULTI_EFNFR" , 3, 1, 652, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FUF" , 4, 1, 652, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NFEMR" , 5, 1, 652, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FEMR" , 6, 1, 652, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_26" , 7, 20, 652, "RAZ", 1, 1, 0, 0},
|
|
{"AEIMN" , 27, 5, 652, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECSI" , 0, 16, 653, "RO", 0, 0, 0ull, 0ull},
|
|
{"EFNFSI" , 16, 16, 653, "RO", 0, 0, 0ull, 0ull},
|
|
{"RTLTL" , 0, 16, 654, "R/W", 0, 0, 4143ull, 4143ull},
|
|
{"RTL" , 16, 16, 654, "R/W", 0, 0, 12429ull, 12429ull},
|
|
{"OMR" , 0, 32, 655, "R/W", 0, 1, 4294967295ull, 0},
|
|
{"LINK_NUM" , 0, 8, 656, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_8_14" , 8, 7, 656, "RAZ", 1, 1, 0, 0},
|
|
{"FORCE_LINK" , 15, 1, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LINK_STATE" , 16, 6, 656, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 656, "RAZ", 1, 1, 0, 0},
|
|
{"LPEC" , 24, 8, 656, "RO", 0, 0, 7ull, 7ull},
|
|
{"ACK_FREQ" , 0, 8, 657, "R/W", 0, 0, 0ull, 0ull},
|
|
{"N_FTS" , 8, 8, 657, "R/W", 0, 0, 128ull, 128ull},
|
|
{"N_FTS_CC" , 16, 8, 657, "R/W", 0, 0, 128ull, 128ull},
|
|
{"L0EL" , 24, 3, 657, "R/W", 0, 0, 3ull, 3ull},
|
|
{"L1EL" , 27, 3, 657, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_30_31" , 30, 2, 657, "RAZ", 1, 1, 0, 0},
|
|
{"OMR" , 0, 1, 658, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SD" , 1, 1, 658, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LE" , 2, 1, 658, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RA" , 3, 1, 658, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_4" , 4, 1, 658, "RAZ", 1, 1, 0, 0},
|
|
{"DLLLE" , 5, 1, 658, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_6" , 6, 1, 658, "RAZ", 1, 1, 0, 0},
|
|
{"FLM" , 7, 1, 658, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_15" , 8, 8, 658, "RO", 0, 0, 1ull, 1ull},
|
|
{"LME" , 16, 6, 658, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_22_24" , 22, 3, 658, "RAZ", 1, 1, 0, 0},
|
|
{"ECCRC" , 25, 1, 658, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_31" , 26, 6, 658, "RAZ", 1, 1, 0, 0},
|
|
{"ILST" , 0, 24, 659, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCD" , 24, 1, 659, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ACK_NAK" , 25, 1, 659, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_30" , 26, 5, 659, "RAZ", 1, 1, 0, 0},
|
|
{"DLLD" , 31, 1, 659, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NTSS" , 0, 4, 660, "R/W", 0, 0, 10ull, 10ull},
|
|
{"RESERVED_4_7" , 4, 4, 660, "RO", 1, 1, 0, 0},
|
|
{"NSKPS" , 8, 3, 660, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_11_13" , 11, 3, 660, "RAZ", 1, 1, 0, 0},
|
|
{"TMRT" , 14, 5, 660, "R/W", 0, 0, 8ull, 8ull},
|
|
{"TMANLT" , 19, 5, 660, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TMFCWT" , 24, 5, 660, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_31" , 29, 3, 660, "RO", 1, 1, 0, 0},
|
|
{"SKPIV" , 0, 11, 661, "R/W", 0, 0, 1280ull, 1280ull},
|
|
{"RESERVED_11_14" , 11, 4, 661, "RAZ", 1, 1, 0, 0},
|
|
{"DFCWT" , 15, 1, 661, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_FUN" , 16, 1, 661, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_POIS_FILT" , 17, 1, 661, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_BAR_MATCH" , 18, 1, 661, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CFG1_FILT" , 19, 1, 661, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_LK_FILT" , 20, 1, 661, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_TAG_ERR" , 21, 1, 661, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_RID_ERR" , 22, 1, 661, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_FUN_ERR" , 23, 1, 661, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_TC_ERR" , 24, 1, 661, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_ATTR_ERR" , 25, 1, 661, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_LEN_ERR" , 26, 1, 661, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_ECRC_FILT" , 27, 1, 661, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_ECRC_FILT" , 28, 1, 661, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSG_CTRL" , 29, 1, 661, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_IO_FILT" , 30, 1, 661, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CFG0_FILT" , 31, 1, 661, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_VEND0_DRP" , 0, 1, 662, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_VEND1_DRP" , 1, 1, 662, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_31" , 2, 30, 662, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_INFO_L32" , 0, 32, 663, "RO", 0, 0, 0ull, 0ull},
|
|
{"DBG_INFO_U32" , 0, 32, 664, "RO", 0, 0, 0ull, 0ull},
|
|
{"TPDFCC" , 0, 12, 665, "RO", 0, 0, 0ull, 0ull},
|
|
{"TPHFCC" , 12, 8, 665, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 665, "RAZ", 1, 1, 0, 0},
|
|
{"TCDFCC" , 0, 12, 666, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCHFCC" , 12, 8, 666, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 666, "RAZ", 1, 1, 0, 0},
|
|
{"TCDFCC" , 0, 12, 667, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCHFCC" , 12, 8, 667, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 667, "RAZ", 1, 1, 0, 0},
|
|
{"RTLPFCCNR" , 0, 1, 668, "RO", 0, 0, 0ull, 0ull},
|
|
{"TRBNE" , 1, 1, 668, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQNE" , 2, 1, 668, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_31" , 3, 29, 668, "RAZ", 1, 1, 0, 0},
|
|
{"WRR_VC0" , 0, 8, 669, "RO", 0, 0, 15ull, 15ull},
|
|
{"WRR_VC1" , 8, 8, 669, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC2" , 16, 8, 669, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC3" , 24, 8, 669, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC4" , 0, 8, 670, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC5" , 8, 8, 670, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC6" , 16, 8, 670, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC7" , 24, 8, 670, "RO", 0, 0, 0ull, 0ull},
|
|
{"DATA_CREDITS" , 0, 12, 671, "R/W", 0, 0, 128ull, 128ull},
|
|
{"HEADER_CREDITS" , 12, 8, 671, "R/W", 0, 0, 35ull, 35ull},
|
|
{"RESERVED_20_20" , 20, 1, 671, "RAZ", 1, 1, 0, 0},
|
|
{"QUEUE_MODE" , 21, 3, 671, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_24_29" , 24, 6, 671, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE_ORDERING" , 30, 1, 671, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RX_QUEUE_ORDER" , 31, 1, 671, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DATA_CREDITS" , 0, 12, 672, "R/W", 0, 0, 4ull, 4ull},
|
|
{"HEADER_CREDITS" , 12, 8, 672, "R/W", 0, 0, 8ull, 8ull},
|
|
{"RESERVED_20_20" , 20, 1, 672, "RAZ", 1, 1, 0, 0},
|
|
{"QUEUE_MODE" , 21, 3, 672, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_24_31" , 24, 8, 672, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_CREDITS" , 0, 12, 673, "R/W", 0, 0, 128ull, 128ull},
|
|
{"HEADER_CREDITS" , 12, 8, 673, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_20_20" , 20, 1, 673, "RAZ", 1, 1, 0, 0},
|
|
{"QUEUE_MODE" , 21, 3, 673, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_24_31" , 24, 8, 673, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_DEPTH" , 0, 14, 674, "R/W", 0, 0, 331ull, 331ull},
|
|
{"RESERVED_14_15" , 14, 2, 674, "RAZ", 1, 1, 0, 0},
|
|
{"HEADER_DEPTH" , 16, 10, 674, "R/W", 0, 0, 41ull, 41ull},
|
|
{"RESERVED_26_31" , 26, 6, 674, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_DEPTH" , 0, 14, 675, "R/W", 0, 0, 56ull, 56ull},
|
|
{"RESERVED_14_15" , 14, 2, 675, "RAZ", 1, 1, 0, 0},
|
|
{"HEADER_DEPTH" , 16, 10, 675, "R/W", 0, 0, 14ull, 14ull},
|
|
{"RESERVED_26_31" , 26, 6, 675, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_DEPTH" , 0, 14, 676, "R/W", 0, 0, 360ull, 360ull},
|
|
{"RESERVED_14_15" , 14, 2, 676, "RAZ", 1, 1, 0, 0},
|
|
{"HEADER_DEPTH" , 16, 10, 676, "R/W", 0, 0, 70ull, 70ull},
|
|
{"RESERVED_26_31" , 26, 6, 676, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_STAT" , 0, 32, 677, "RO", 0, 0, 0ull, 0ull},
|
|
{"PHY_CTRL" , 0, 32, 678, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_4" , 0, 5, 679, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FD" , 5, 1, 679, "R/W", 0, 0, 1ull, 1ull},
|
|
{"HFD" , 6, 1, 679, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PAUSE" , 7, 2, 679, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 679, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"REM_FLT" , 12, 2, 679, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_14" , 14, 1, 679, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"NP" , 15, 1, 679, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 679, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_11" , 0, 12, 680, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"THOU_THD" , 12, 1, 680, "RO", 0, 0, 0ull, 0ull},
|
|
{"THOU_TFD" , 13, 1, 680, "RO", 0, 0, 0ull, 0ull},
|
|
{"THOU_XHD" , 14, 1, 680, "RO", 0, 0, 1ull, 1ull},
|
|
{"THOU_XFD" , 15, 1, 680, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_16_63" , 16, 48, 680, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_4" , 0, 5, 681, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FD" , 5, 1, 681, "RO", 0, 0, 0ull, 0ull},
|
|
{"HFD" , 6, 1, 681, "RO", 0, 0, 0ull, 0ull},
|
|
{"PAUSE" , 7, 2, 681, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 681, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"REM_FLT" , 12, 2, 681, "RO", 0, 0, 0ull, 0ull},
|
|
{"ACK" , 14, 1, 681, "RO", 0, 1, 0ull, 0},
|
|
{"NP" , 15, 1, 681, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 681, "RAZ", 1, 1, 0, 0},
|
|
{"LINK_OK" , 0, 1, 682, "RO", 0, 0, 0ull, 0ull},
|
|
{"DUP" , 1, 1, 682, "RO", 0, 0, 0ull, 0ull},
|
|
{"AN_CPT" , 2, 1, 682, "RO", 0, 0, 0ull, 1ull},
|
|
{"SPD" , 3, 2, 682, "RO", 0, 0, 0ull, 0ull},
|
|
{"PAUSE" , 5, 2, 682, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 682, "RAZ", 1, 1, 0, 0},
|
|
{"LNKSPD_EN" , 0, 1, 683, "R/W", 0, 0, 0ull, 1ull},
|
|
{"XMIT_EN" , 1, 1, 683, "R/W", 0, 0, 0ull, 1ull},
|
|
{"AN_ERR_EN" , 2, 1, 683, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXFIFU_EN" , 3, 1, 683, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXFIFO_EN" , 4, 1, 683, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXBAD_EN" , 5, 1, 683, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXERR_EN" , 6, 1, 683, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXBAD_EN" , 7, 1, 683, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXLOCK_EN" , 8, 1, 683, "R/W", 0, 0, 0ull, 1ull},
|
|
{"AN_BAD_EN" , 9, 1, 683, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SYNC_BAD_EN" , 10, 1, 683, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DUP" , 11, 1, 683, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_12_63" , 12, 52, 683, "RAZ", 1, 1, 0, 0},
|
|
{"LNKSPD" , 0, 1, 684, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"XMIT" , 1, 1, 684, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AN_ERR" , 2, 1, 684, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXFIFU" , 3, 1, 684, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXFIFO" , 4, 1, 684, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXBAD" , 5, 1, 684, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXERR" , 6, 1, 684, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXBAD" , 7, 1, 684, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXLOCK" , 8, 1, 684, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AN_BAD" , 9, 1, 684, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SYNC_BAD" , 10, 1, 684, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DUP" , 11, 1, 684, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 684, "RAZ", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 16, 685, "R/W", 0, 1, 1094ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 685, "RAZ", 1, 1, 0, 0},
|
|
{"PKT_SZ" , 0, 2, 686, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LA_EN" , 2, 1, 686, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LAFIFOVFL" , 3, 1, 686, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 686, "RAZ", 1, 1, 0, 0},
|
|
{"SAMP_PT" , 0, 7, 687, "R/W", 0, 1, 1ull, 0},
|
|
{"AN_OVRD" , 7, 1, 687, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MODE" , 8, 1, 687, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAC_PHY" , 9, 1, 687, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LOOPBCK2" , 10, 1, 687, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GMXENO" , 11, 1, 687, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SGMII" , 12, 1, 687, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_13_63" , 13, 51, 687, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_4" , 0, 5, 688, "RAZ", 1, 1, 0, 0},
|
|
{"UNI" , 5, 1, 688, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SPDMSB" , 6, 1, 688, "R/W", 0, 0, 1ull, 1ull},
|
|
{"COLTST" , 7, 1, 688, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DUP" , 8, 1, 688, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RST_AN" , 9, 1, 688, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_10" , 10, 1, 688, "RAZ", 1, 1, 0, 0},
|
|
{"PWR_DN" , 11, 1, 688, "R/W", 0, 0, 1ull, 0ull},
|
|
{"AN_EN" , 12, 1, 688, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SPDLSB" , 13, 1, 688, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LOOPBCK1" , 14, 1, 688, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 15, 1, 688, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 688, "RAZ", 1, 1, 0, 0},
|
|
{"EXTND" , 0, 1, 689, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 689, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LNK_ST" , 2, 1, 689, "RO", 0, 0, 0ull, 1ull},
|
|
{"AN_ABIL" , 3, 1, 689, "RO", 0, 0, 1ull, 1ull},
|
|
{"RM_FLT" , 4, 1, 689, "RO", 0, 0, 0ull, 0ull},
|
|
{"AN_CPT" , 5, 1, 689, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRB_SUP" , 6, 1, 689, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_7_7" , 7, 1, 689, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EXT_ST" , 8, 1, 689, "RO", 0, 0, 1ull, 1ull},
|
|
{"HUN_T2HD" , 9, 1, 689, "RO", 0, 0, 0ull, 0ull},
|
|
{"HUN_T2FD" , 10, 1, 689, "RO", 0, 0, 0ull, 0ull},
|
|
{"TEN_HD" , 11, 1, 689, "RO", 0, 0, 0ull, 0ull},
|
|
{"TEN_FD" , 12, 1, 689, "RO", 0, 0, 0ull, 0ull},
|
|
{"HUN_XHD" , 13, 1, 689, "RO", 0, 0, 0ull, 0ull},
|
|
{"HUN_XFD" , 14, 1, 689, "RO", 0, 0, 0ull, 0ull},
|
|
{"HUN_T4" , 15, 1, 689, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 689, "RAZ", 1, 1, 0, 0},
|
|
{"AN_ST" , 0, 4, 690, "RO", 0, 0, 0ull, 0ull},
|
|
{"AN_BAD" , 4, 1, 690, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYNC" , 5, 4, 690, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYNC_BAD" , 9, 1, 690, "RO", 0, 0, 0ull, 0ull},
|
|
{"RX_ST" , 10, 5, 690, "RO", 0, 0, 0ull, 0ull},
|
|
{"RX_BAD" , 15, 1, 690, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 690, "RAZ", 1, 1, 0, 0},
|
|
{"BIT_LOCK" , 0, 1, 691, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYNC" , 1, 1, 691, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 691, "RAZ", 1, 1, 0, 0},
|
|
{"ONE" , 0, 1, 692, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_9" , 1, 9, 692, "RAZ", 0, 1, 0ull, 0},
|
|
{"SPEED" , 10, 2, 692, "R/W", 0, 0, 2ull, 2ull},
|
|
{"DUP" , 12, 1, 692, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_13_13" , 13, 1, 692, "RAZ", 0, 1, 0ull, 0},
|
|
{"ACK" , 14, 1, 692, "RO", 0, 0, 0ull, 0ull},
|
|
{"LINK" , 15, 1, 692, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_16_63" , 16, 48, 692, "RAZ", 1, 1, 0, 0},
|
|
{"ONE" , 0, 1, 693, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_9" , 1, 9, 693, "RAZ", 0, 1, 0ull, 0},
|
|
{"SPEED" , 10, 2, 693, "RO", 0, 0, 0ull, 2ull},
|
|
{"DUP" , 12, 1, 693, "RO", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_13_14" , 13, 2, 693, "RAZ", 0, 1, 0ull, 0},
|
|
{"LINK" , 15, 1, 693, "RO", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_16_63" , 16, 48, 693, "RAZ", 1, 1, 0, 0},
|
|
{"ORD_ST" , 0, 4, 694, "RO", 0, 0, 0ull, 0ull},
|
|
{"TX_BAD" , 4, 1, 694, "RO", 0, 0, 0ull, 0ull},
|
|
{"XMIT" , 5, 2, 694, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 694, "RAZ", 1, 1, 0, 0},
|
|
{"TXPLRT" , 0, 1, 695, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RXPLRT" , 1, 1, 695, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AUTORXPL" , 2, 1, 695, "RO", 0, 0, 0ull, 0ull},
|
|
{"RXOVRD" , 3, 1, 695, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 695, "RAZ", 1, 1, 0, 0},
|
|
{"L0SYNC" , 0, 1, 696, "RO", 0, 0, 0ull, 1ull},
|
|
{"L1SYNC" , 1, 1, 696, "RO", 0, 0, 0ull, 1ull},
|
|
{"L2SYNC" , 2, 1, 696, "RO", 0, 0, 0ull, 1ull},
|
|
{"L3SYNC" , 3, 1, 696, "RO", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_4_10" , 4, 7, 696, "RAZ", 1, 1, 0, 0},
|
|
{"PATTST" , 11, 1, 696, "RO", 0, 0, 0ull, 0ull},
|
|
{"ALIGND" , 12, 1, 696, "RO", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_13_63" , 13, 51, 696, "RAZ", 1, 1, 0, 0},
|
|
{"BIST_STATUS" , 0, 1, 697, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 697, "RAZ", 1, 1, 0, 0},
|
|
{"BITLCK0" , 0, 1, 698, "RO", 0, 1, 0ull, 0},
|
|
{"BITLCK1" , 1, 1, 698, "RO", 0, 1, 0ull, 0},
|
|
{"BITLCK2" , 2, 1, 698, "RO", 0, 1, 0ull, 0},
|
|
{"BITLCK3" , 3, 1, 698, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 698, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 699, "RAZ", 1, 1, 0, 0},
|
|
{"SPD" , 2, 4, 699, "RO", 0, 0, 0ull, 0ull},
|
|
{"SPDSEL0" , 6, 1, 699, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_7_10" , 7, 4, 699, "RAZ", 1, 1, 0, 0},
|
|
{"LO_PWR" , 11, 1, 699, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_12" , 12, 1, 699, "RAZ", 1, 1, 0, 0},
|
|
{"SPDSEL1" , 13, 1, 699, "RO", 0, 0, 1ull, 1ull},
|
|
{"LOOPBCK1" , 14, 1, 699, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 15, 1, 699, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 699, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 2, 700, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 700, "RAZ", 1, 1, 0, 0},
|
|
{"TXFLT_EN" , 0, 1, 701, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXBAD_EN" , 1, 1, 701, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXSYNBAD_EN" , 2, 1, 701, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BITLCKLS_EN" , 3, 1, 701, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SYNLOS_EN" , 4, 1, 701, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ALGNLOS_EN" , 5, 1, 701, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_6_63" , 6, 58, 701, "RAZ", 1, 1, 0, 0},
|
|
{"TXFLT" , 0, 1, 702, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXBAD" , 1, 1, 702, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXSYNBAD" , 2, 1, 702, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BITLCKLS" , 3, 1, 702, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SYNLOS" , 4, 1, 702, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ALGNLOS" , 5, 1, 702, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 702, "RAZ", 1, 1, 0, 0},
|
|
{"PKT_SZ" , 0, 2, 703, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LA_EN" , 2, 1, 703, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LAFIFOVFL" , 3, 1, 703, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DROP_LN" , 4, 2, 703, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENC_MODE" , 6, 1, 703, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 703, "RAZ", 1, 1, 0, 0},
|
|
{"GMXENO" , 0, 1, 704, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XAUI" , 1, 1, 704, "RO", 1, 1, 0, 0},
|
|
{"RX_SWAP" , 2, 1, 704, "R/W", 0, 1, 0ull, 0},
|
|
{"TX_SWAP" , 3, 1, 704, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 704, "RAZ", 1, 1, 0, 0},
|
|
{"SYNC0ST" , 0, 4, 705, "RO", 0, 1, 0ull, 0},
|
|
{"SYNC1ST" , 4, 4, 705, "RO", 0, 1, 0ull, 0},
|
|
{"SYNC2ST" , 8, 4, 705, "RO", 0, 1, 0ull, 0},
|
|
{"SYNC3ST" , 12, 4, 705, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 705, "RAZ", 1, 1, 0, 0},
|
|
{"TENGB" , 0, 1, 706, "RO", 0, 0, 1ull, 1ull},
|
|
{"TENPASST" , 1, 1, 706, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 706, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 707, "RAZ", 1, 1, 0, 0},
|
|
{"LPABLE" , 1, 1, 707, "RO", 0, 0, 1ull, 1ull},
|
|
{"RCV_LNK" , 2, 1, 707, "RO", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_3_6" , 3, 4, 707, "RAZ", 1, 1, 0, 0},
|
|
{"FLT" , 7, 1, 707, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 707, "RAZ", 1, 1, 0, 0},
|
|
{"TENGB_R" , 0, 1, 708, "RO", 0, 0, 0ull, 0ull},
|
|
{"TENGB_X" , 1, 1, 708, "RO", 0, 0, 1ull, 1ull},
|
|
{"TENGB_W" , 2, 1, 708, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_9" , 3, 7, 708, "RAZ", 1, 1, 0, 0},
|
|
{"RCVFLT" , 10, 1, 708, "RC", 0, 0, 0ull, 0ull},
|
|
{"XMTFLT" , 11, 1, 708, "RC", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_13" , 12, 2, 708, "RAZ", 1, 1, 0, 0},
|
|
{"DEV" , 14, 2, 708, "RO", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_16_63" , 16, 48, 708, "RAZ", 1, 1, 0, 0},
|
|
{"TXPLRT" , 0, 1, 709, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RXPLRT" , 1, 1, 709, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XOR_TXPLRT" , 2, 4, 709, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XOR_RXPLRT" , 6, 4, 709, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 709, "RAZ", 1, 1, 0, 0},
|
|
{"TX_ST" , 0, 3, 710, "RO", 0, 1, 0ull, 0},
|
|
{"RX_ST" , 3, 2, 710, "RO", 0, 1, 0ull, 0},
|
|
{"ALGN_ST" , 5, 3, 710, "RO", 0, 1, 0ull, 0},
|
|
{"RXBAD" , 8, 1, 710, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYN0BAD" , 9, 1, 710, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYN1BAD" , 10, 1, 710, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYN2BAD" , 11, 1, 710, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYN3BAD" , 12, 1, 710, "RO", 0, 0, 0ull, 0ull},
|
|
{"TERM_ERR" , 13, 1, 710, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 710, "RAZ", 1, 1, 0, 0},
|
|
{"SOT" , 0, 1, 711, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQHDR0" , 1, 1, 711, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQHDR1" , 2, 1, 711, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQDATA4" , 3, 1, 711, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQDATA3" , 4, 1, 711, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQDATA2" , 5, 1, 711, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQDATA1" , 6, 1, 711, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQDATA0" , 7, 1, 711, "RO", 0, 0, 0ull, 0ull},
|
|
{"RETRY" , 8, 1, 711, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTLP_OR" , 9, 1, 711, "RO", 0, 0, 0ull, 0ull},
|
|
{"NTLP_OR" , 10, 1, 711, "RO", 0, 0, 0ull, 0ull},
|
|
{"CTLP_OR" , 11, 1, 711, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQDATA5" , 12, 1, 711, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 711, "RAZ", 1, 1, 0, 0},
|
|
{"PPF" , 0, 1, 712, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEF_TC0" , 1, 1, 712, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEF_TCF1" , 2, 1, 712, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEF_TNF" , 3, 1, 712, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEF_TPF0" , 4, 1, 712, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEF_TPF1" , 5, 1, 712, "RO", 0, 0, 0ull, 0ull},
|
|
{"RSL_P2E" , 6, 1, 712, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEAI_P2E" , 7, 1, 712, "RO", 0, 0, 0ull, 0ull},
|
|
{"DBG_P2E" , 8, 1, 712, "RO", 0, 0, 0ull, 0ull},
|
|
{"E2P_RSL" , 9, 1, 712, "RO", 0, 0, 0ull, 0ull},
|
|
{"E2P_P" , 10, 1, 712, "RO", 0, 0, 0ull, 0ull},
|
|
{"E2P_N" , 11, 1, 712, "RO", 0, 0, 0ull, 0ull},
|
|
{"E2P_CPL" , 12, 1, 712, "RO", 0, 0, 0ull, 0ull},
|
|
{"CTO_P2E" , 13, 1, 712, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 712, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 32, 713, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 32, 32, 713, "R/W", 0, 1, 0ull, 0},
|
|
{"ADDR" , 0, 32, 714, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 32, 32, 714, "R/W", 0, 1, 0ull, 0},
|
|
{"TAG" , 0, 32, 715, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 715, "RAZ", 1, 1, 0, 0},
|
|
{"INV_LCRC" , 0, 1, 716, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INV_ECRC" , 1, 1, 716, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 716, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RO_CTLP" , 3, 1, 716, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LNK_ENB" , 4, 1, 716, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLY_ONE" , 5, 1, 716, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NF_ECRC" , 6, 1, 716, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_8" , 7, 2, 716, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OB_P_CMD" , 9, 1, 716, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PM_XPME" , 10, 1, 716, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PM_XTOFF" , 11, 1, 716, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_12" , 12, 1, 716, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"QLM_CFG" , 13, 2, 716, "RO", 1, 1, 0, 0},
|
|
{"PBUS" , 15, 8, 716, "RO", 1, 1, 0, 0},
|
|
{"DNUM" , 23, 5, 716, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_28_63" , 28, 36, 716, "RAZ", 1, 1, 0, 0},
|
|
{"PCIERST" , 0, 1, 717, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCLK_RUN" , 1, 1, 717, "R/W1C", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 717, "RAZ", 1, 1, 0, 0},
|
|
{"SPOISON" , 0, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTLPMAL" , 1, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTLPLLE" , 2, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RECRCE" , 3, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPOISON" , 4, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RCEMRC" , 5, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RNFEMRC" , 6, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RFEMRC" , 7, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPMERC" , 8, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPTAMRC" , 9, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RUMEP" , 10, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RVDM" , 11, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ACTO" , 12, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTE" , 13, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRE" , 14, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RDWDLE" , 15, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTWDLE" , 16, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPEOOSD" , 17, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCPVWT" , 18, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPE" , 19, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCUV" , 20, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQO" , 21, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RAUC" , 22, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RACUR" , 23, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RACCA" , 24, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CAAR" , 25, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RARWDNS" , 26, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RAMTLP" , 27, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RACPP" , 28, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RAWWPP" , 29, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ECRC_E" , 30, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 718, "RAZ", 1, 1, 0, 0},
|
|
{"SPOISON" , 0, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RTLPMAL" , 1, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RTLPLLE" , 2, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RECRCE" , 3, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RPOISON" , 4, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RCEMRC" , 5, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNFEMRC" , 6, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RFEMRC" , 7, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RPMERC" , 8, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RPTAMRC" , 9, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RUMEP" , 10, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RVDM" , 11, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ACTO" , 12, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RTE" , 13, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRE" , 14, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RDWDLE" , 15, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RTWDLE" , 16, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DPEOOSD" , 17, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCPVWT" , 18, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RPE" , 19, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCUV" , 20, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQO" , 21, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RAUC" , 22, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RACUR" , 23, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RACCA" , 24, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAAR" , 25, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RARWDNS" , 26, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RAMTLP" , 27, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RACPP" , 28, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RAWWPP" , 29, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECRC_E" , 30, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 719, "RAZ", 1, 1, 0, 0},
|
|
{"AUX_EN" , 0, 1, 720, "RO", 0, 0, 0ull, 0ull},
|
|
{"PM_EN" , 1, 1, 720, "RO", 0, 0, 0ull, 0ull},
|
|
{"PM_STAT" , 2, 1, 720, "RO", 0, 0, 0ull, 0ull},
|
|
{"PM_DST" , 3, 1, 720, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 720, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_0_13" , 0, 14, 721, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 14, 50, 721, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_25" , 0, 26, 722, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 26, 38, 722, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_38" , 0, 39, 723, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 39, 25, 723, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_11" , 0, 12, 724, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 12, 52, 724, "R/W", 0, 1, 4503599627370495ull, 0},
|
|
{"RESERVED_0_11" , 0, 12, 725, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 12, 52, 725, "R/W", 0, 1, 4503599627370495ull, 0},
|
|
{"NPEI_P" , 0, 8, 726, "R/W", 0, 0, 128ull, 128ull},
|
|
{"NPEI_NP" , 8, 8, 726, "R/W", 0, 0, 16ull, 16ull},
|
|
{"NPEI_CPL" , 16, 8, 726, "R/W", 0, 0, 128ull, 128ull},
|
|
{"PESC_P" , 24, 8, 726, "R/W", 0, 0, 128ull, 128ull},
|
|
{"PESC_NP" , 32, 8, 726, "R/W", 0, 0, 16ull, 16ull},
|
|
{"PESC_CPL" , 40, 8, 726, "R/W", 0, 0, 128ull, 128ull},
|
|
{"PEAI_PPF" , 48, 8, 726, "R/W", 0, 0, 128ull, 128ull},
|
|
{"RESERVED_56_63" , 56, 8, 726, "RAZ", 1, 1, 0, 0},
|
|
{"LOWATER" , 0, 5, 727, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_5_7" , 5, 3, 727, "RAZ", 0, 1, 0ull, 0},
|
|
{"HIWATER" , 8, 5, 727, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_13_62" , 13, 50, 727, "RAZ", 0, 1, 0ull, 0},
|
|
{"BCKPRS" , 63, 1, 727, "RO", 0, 0, 0ull, 0ull},
|
|
{"BIST" , 0, 18, 728, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 728, "RAZ", 1, 1, 0, 0},
|
|
{"DPRT" , 0, 16, 729, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UDP" , 16, 1, 729, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP" , 17, 1, 729, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 729, "RAZ", 1, 1, 0, 0},
|
|
{"MAP0" , 0, 4, 730, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP1" , 4, 4, 730, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP2" , 8, 4, 730, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP3" , 12, 4, 730, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP4" , 16, 4, 730, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP5" , 20, 4, 730, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP6" , 24, 4, 730, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP7" , 28, 4, 730, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP8" , 32, 4, 730, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP9" , 36, 4, 730, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP10" , 40, 4, 730, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP11" , 44, 4, 730, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP12" , 48, 4, 730, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP13" , 52, 4, 730, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP14" , 56, 4, 730, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP15" , 60, 4, 730, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP0" , 0, 4, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP1" , 4, 4, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP2" , 8, 4, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP3" , 12, 4, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP4" , 16, 4, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP5" , 20, 4, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP6" , 24, 4, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP7" , 28, 4, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP8" , 32, 4, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP9" , 36, 4, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP10" , 40, 4, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP11" , 44, 4, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP12" , 48, 4, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP13" , 52, 4, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP14" , 56, 4, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP15" , 60, 4, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MINLEN" , 0, 16, 732, "R/W", 0, 0, 64ull, 64ull},
|
|
{"MAXLEN" , 16, 16, 732, "R/W", 0, 0, 1536ull, 1536ull},
|
|
{"RESERVED_32_63" , 32, 32, 732, "RAZ", 1, 1, 0, 0},
|
|
{"NIP_SHF" , 0, 3, 733, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_7" , 3, 5, 733, "RAZ", 1, 1, 0, 0},
|
|
{"RAW_SHF" , 8, 3, 733, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_15" , 11, 5, 733, "RAZ", 1, 1, 0, 0},
|
|
{"MAX_L2" , 16, 1, 733, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_UDP" , 17, 1, 733, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TAG_SYN" , 18, 1, 733, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 733, "RAZ", 1, 1, 0, 0},
|
|
{"IP_CHK" , 0, 1, 734, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP_MAL" , 1, 1, 734, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP_HOP" , 2, 1, 734, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP4_OPTS" , 3, 1, 734, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP6_EEXT" , 4, 2, 734, "R/W", 0, 0, 1ull, 3ull},
|
|
{"RESERVED_6_7" , 6, 2, 734, "RAZ", 1, 1, 0, 0},
|
|
{"L4_MAL" , 8, 1, 734, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_PRT" , 9, 1, 734, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_CHK" , 10, 1, 734, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_LEN" , 11, 1, 734, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TCP_FLAG" , 12, 1, 734, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L2_MAL" , 13, 1, 734, "R/W", 0, 0, 1ull, 1ull},
|
|
{"VS_QOS" , 14, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VS_WQE" , 15, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IGNRS" , 16, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_19" , 17, 3, 734, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RING_EN" , 20, 1, 734, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_21_23" , 21, 3, 734, "RAZ", 1, 1, 0, 0},
|
|
{"DSA_GRP_SID" , 24, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DSA_GRP_SCMD" , 25, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DSA_GRP_TVID" , 26, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_63" , 27, 37, 734, "RAZ", 1, 1, 0, 0},
|
|
{"PRI" , 0, 6, 735, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_7" , 6, 2, 735, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 8, 3, 735, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_11_11" , 11, 1, 735, "RAZ", 1, 1, 0, 0},
|
|
{"UP_QOS" , 12, 1, 735, "RAZ", 0, 1, 0ull, 0},
|
|
{"RESERVED_13_63" , 13, 51, 735, "RAZ", 1, 1, 0, 0},
|
|
{"PKTDRP" , 0, 1, 736, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CRCERR" , 1, 1, 736, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BCKPRS" , 2, 1, 736, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 3, 1, 736, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BADTAG" , 4, 1, 736, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPRUNT" , 5, 1, 736, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TODOOVR" , 6, 1, 736, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FEPERR" , 7, 1, 736, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BEPERR" , 8, 1, 736, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MINERR" , 9, 1, 736, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 10, 1, 736, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 11, 1, 736, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PUNYERR" , 12, 1, 736, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 736, "RAZ", 1, 1, 0, 0},
|
|
{"PKTDRP" , 0, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CRCERR" , 1, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BCKPRS" , 2, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 3, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BADTAG" , 4, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPRUNT" , 5, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TODOOVR" , 6, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FEPERR" , 7, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BEPERR" , 8, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MINERR" , 9, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 10, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 11, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PUNYERR" , 12, 1, 737, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 737, "RAZ", 1, 1, 0, 0},
|
|
{"OFFSET" , 0, 3, 738, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 738, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP" , 0, 7, 739, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 739, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 8, 2, 739, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DSA_EN" , 10, 1, 739, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HIGIG_EN" , 11, 1, 739, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CRC_EN" , 12, 1, 739, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 739, "RAZ", 1, 1, 0, 0},
|
|
{"QOS_VLAN" , 16, 1, 739, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS_DIFF" , 17, 1, 739, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS_VOD" , 18, 1, 739, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS_VSEL" , 19, 1, 739, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS_WAT" , 20, 4, 739, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS" , 24, 3, 739, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HG_QOS" , 27, 1, 739, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRP_WAT" , 28, 4, 739, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INST_HDR" , 32, 1, 739, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DYN_RS" , 33, 1, 739, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TAG_INC" , 34, 2, 739, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RAWDRP" , 36, 1, 739, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_39" , 37, 3, 739, "RAZ", 1, 1, 0, 0},
|
|
{"QOS_WAT_47" , 40, 4, 739, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRP_WAT_47" , 44, 4, 739, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MINERR_EN" , 48, 1, 739, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MAXERR_EN" , 49, 1, 739, "R/W", 0, 0, 1ull, 1ull},
|
|
{"LENERR_EN" , 50, 1, 739, "R/W", 0, 0, 1ull, 1ull},
|
|
{"VLAN_LEN" , 51, 1, 739, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PAD_LEN" , 52, 1, 739, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_53_63" , 53, 11, 739, "RAZ", 1, 1, 0, 0},
|
|
{"GRP" , 0, 4, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NON_TAG_TYPE" , 4, 2, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_TAG_TYPE" , 6, 2, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_TAG_TYPE" , 8, 2, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP4_TAG_TYPE" , 10, 2, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP6_TAG_TYPE" , 12, 2, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_SRC_FLAG" , 14, 1, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_SRC_FLAG" , 15, 1, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_DST_FLAG" , 16, 1, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_DST_FLAG" , 17, 1, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_PCTL_FLAG" , 18, 1, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_NXTH_FLAG" , 19, 1, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_SPRT_FLAG" , 20, 1, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_SPRT_FLAG" , 21, 1, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_DPRT_FLAG" , 22, 1, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_DPRT_FLAG" , 23, 1, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_PRT_FLAG" , 24, 1, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_VLAN" , 25, 1, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_VS" , 26, 2, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TAG_MODE" , 28, 2, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAG_MSKIP" , 30, 1, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAG" , 31, 1, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAGMASK" , 32, 4, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAGBASE" , 36, 4, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 740, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 0, 3, 741, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 741, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 0, 3, 742, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 742, "RAZ", 1, 1, 0, 0},
|
|
{"QOS1" , 4, 3, 742, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 742, "RAZ", 1, 1, 0, 0},
|
|
{"MATCH_VALUE" , 0, 16, 743, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MATCH_TYPE" , 16, 3, 743, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_19" , 19, 1, 743, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 20, 3, 743, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 743, "RAZ", 1, 1, 0, 0},
|
|
{"GRP" , 24, 4, 743, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_31" , 28, 4, 743, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 32, 16, 743, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 743, "RAZ", 1, 1, 0, 0},
|
|
{"WORD" , 0, 56, 744, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 744, "RAZ", 1, 1, 0, 0},
|
|
{"RST" , 0, 1, 745, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 745, "RAZ", 1, 1, 0, 0},
|
|
{"DRP_OCTS" , 0, 32, 746, "R/W", 0, 1, 0ull, 0},
|
|
{"DRP_PKTS" , 32, 32, 746, "R/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 747, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 747, "RAZ", 1, 1, 0, 0},
|
|
{"RAW" , 0, 32, 748, "R/W", 0, 1, 0ull, 0},
|
|
{"PKTS" , 32, 32, 748, "R/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 0, 32, 749, "R/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 32, 32, 749, "R/W", 0, 1, 0ull, 0},
|
|
{"H64" , 0, 32, 750, "R/W", 0, 1, 0ull, 0},
|
|
{"H65TO127" , 32, 32, 750, "R/W", 0, 1, 0ull, 0},
|
|
{"H128TO255" , 0, 32, 751, "R/W", 0, 1, 0ull, 0},
|
|
{"H256TO511" , 32, 32, 751, "R/W", 0, 1, 0ull, 0},
|
|
{"H512TO1023" , 0, 32, 752, "R/W", 0, 1, 0ull, 0},
|
|
{"H1024TO1518" , 32, 32, 752, "R/W", 0, 1, 0ull, 0},
|
|
{"H1519" , 0, 32, 753, "R/W", 0, 1, 0ull, 0},
|
|
{"FCS" , 32, 32, 753, "R/W", 0, 1, 0ull, 0},
|
|
{"UNDERSZ" , 0, 32, 754, "R/W", 0, 1, 0ull, 0},
|
|
{"FRAG" , 32, 32, 754, "R/W", 0, 1, 0ull, 0},
|
|
{"OVERSZ" , 0, 32, 755, "R/W", 0, 1, 0ull, 0},
|
|
{"JABBER" , 32, 32, 755, "R/W", 0, 1, 0ull, 0},
|
|
{"RDCLR" , 0, 1, 756, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 756, "RAZ", 1, 1, 0, 0},
|
|
{"ERRS" , 0, 16, 757, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 757, "RAZ", 1, 1, 0, 0},
|
|
{"OCTS" , 0, 48, 758, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 758, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 759, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 759, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 8, 760, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 760, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 0, 16, 761, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 761, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 16, 762, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DST" , 16, 16, 762, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 762, "RAZ", 1, 1, 0, 0},
|
|
{"ENTRY" , 0, 62, 763, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_62_62" , 62, 1, 763, "RAZ", 1, 1, 0, 0},
|
|
{"VAL" , 63, 1, 763, "RO", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 32, 764, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 764, "RAZ", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 48, 765, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 765, "RAZ", 1, 1, 0, 0},
|
|
{"SIZE" , 0, 16, 766, "RO", 1, 0, 0, 0ull},
|
|
{"SEGS" , 16, 6, 766, "RO", 1, 0, 0, 0ull},
|
|
{"CMD" , 22, 14, 766, "RO", 1, 0, 0, 0ull},
|
|
{"FAU" , 36, 28, 766, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 767, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 767, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 767, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 767, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 767, "RO", 1, 0, 0, 0ull},
|
|
{"PTRS2" , 0, 17, 768, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 768, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTRS1" , 32, 17, 768, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 768, "RAZ", 1, 0, 0, 0ull},
|
|
{"MOD" , 0, 3, 769, "RO", 1, 0, 0, 0ull},
|
|
{"CNT" , 3, 13, 769, "RO", 1, 0, 0, 0ull},
|
|
{"CHK" , 16, 1, 769, "RO", 1, 0, 0, 0ull},
|
|
{"LEN" , 17, 1, 769, "RO", 1, 0, 0, 0ull},
|
|
{"SOP" , 18, 1, 769, "RO", 1, 0, 0, 0ull},
|
|
{"UID" , 19, 3, 769, "RO", 1, 0, 0, 0ull},
|
|
{"MAJ" , 22, 1, 769, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 769, "RAZ", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 16, 770, "RO", 1, 0, 0, 0ull},
|
|
{"SEGS" , 16, 6, 770, "RO", 1, 0, 0, 0ull},
|
|
{"CMD" , 22, 14, 770, "RO", 1, 0, 0, 0ull},
|
|
{"FAU" , 36, 28, 770, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 771, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 771, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 771, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 771, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 771, "RO", 1, 0, 0, 0ull},
|
|
{"DATA" , 0, 64, 772, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 773, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 773, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 773, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 773, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 773, "RO", 1, 0, 0, 0ull},
|
|
{"DATA" , 0, 64, 774, "RO", 1, 0, 0, 0ull},
|
|
{"MAJOR" , 0, 3, 775, "RO", 1, 0, 0, 0ull},
|
|
{"MINOR" , 3, 2, 775, "RO", 1, 0, 0, 0ull},
|
|
{"WAIT" , 5, 1, 775, "RO", 1, 0, 0, 0ull},
|
|
{"CHK_MODE" , 6, 1, 775, "RO", 1, 0, 0, 0ull},
|
|
{"CHK_ONCE" , 7, 1, 775, "RO", 1, 0, 0, 0ull},
|
|
{"INIT_DWRITE" , 8, 1, 775, "RO", 1, 0, 0, 0ull},
|
|
{"DREAD_SOP" , 9, 1, 775, "RO", 1, 0, 0, 0ull},
|
|
{"UID" , 10, 2, 775, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_OFF" , 12, 6, 775, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_SIZ" , 18, 16, 775, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_SEGS" , 34, 6, 775, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_OFF" , 40, 16, 775, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_SIZ" , 56, 8, 775, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_SIZ" , 0, 8, 776, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_PTR" , 8, 40, 776, "RO", 1, 0, 0, 0ull},
|
|
{"NXT_INFLT" , 48, 6, 776, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_54_63" , 54, 10, 776, "RAZ", 1, 0, 0, 0ull},
|
|
{"QID_BASE" , 0, 8, 777, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFF" , 8, 4, 777, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFFMAX" , 12, 4, 777, "RO", 1, 0, 0, 0ull},
|
|
{"QCB_RIDX" , 16, 5, 777, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 21, 3, 777, "RO", 1, 0, 0, 0ull},
|
|
{"STATC" , 24, 1, 777, "RO", 1, 0, 0, 0ull},
|
|
{"ACTIVE" , 25, 1, 777, "RO", 1, 0, 0, 0ull},
|
|
{"PREEMPTED" , 26, 1, 777, "RO", 1, 0, 0, 0ull},
|
|
{"PREEMPTEE" , 27, 1, 777, "RO", 1, 0, 0, 0ull},
|
|
{"PREEMPTER" , 28, 1, 777, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFFTHS" , 29, 4, 777, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFFRES" , 33, 4, 777, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 777, "RAZ", 1, 0, 0, 0ull},
|
|
{"QCB_RIDX" , 0, 6, 778, "RO", 1, 0, 0, 0ull},
|
|
{"QCB_WIDX" , 6, 6, 778, "RO", 1, 0, 0, 0ull},
|
|
{"BUF_PTR" , 12, 33, 778, "RO", 1, 0, 0, 0ull},
|
|
{"BUF_SIZ" , 45, 13, 778, "RO", 1, 0, 0, 0ull},
|
|
{"TAIL" , 58, 1, 778, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 59, 5, 778, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 0, 3, 779, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_Q" , 3, 1, 779, "RO", 1, 0, 0, 0ull},
|
|
{"S_TAIL" , 4, 1, 779, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 5, 1, 779, "RO", 1, 0, 0, 0ull},
|
|
{"PREEMPTEE" , 6, 1, 779, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 779, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 8, 20, 779, "RO", 1, 0, 0, 0ull},
|
|
{"PREEMPTER" , 28, 1, 779, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 779, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTRS3" , 0, 17, 780, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 780, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTRS0" , 32, 17, 780, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 780, "RAZ", 1, 0, 0, 0ull},
|
|
{"PID" , 0, 6, 781, "R/W", 1, 0, 0, 0ull},
|
|
{"EID" , 6, 4, 781, "R/W", 1, 0, 0, 0ull},
|
|
{"BP_PORT" , 10, 6, 781, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_16_52" , 16, 37, 781, "RAZ", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 781, "R/W", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 61, 1, 781, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_62_63" , 62, 2, 781, "RAZ", 1, 0, 0, 0ull},
|
|
{"PID" , 0, 6, 782, "R/W", 1, 0, 0, 0ull},
|
|
{"EID" , 6, 4, 782, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_10_52" , 10, 43, 782, "RAZ", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 782, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_61_63" , 61, 3, 782, "RAZ", 1, 0, 0, 0ull},
|
|
{"PID" , 0, 6, 783, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 783, "RAZ", 1, 0, 0, 0ull},
|
|
{"RATE_PKT" , 8, 24, 783, "R/W", 1, 0, 0, 0ull},
|
|
{"RATE_WORD" , 32, 19, 783, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_51_63" , 51, 13, 783, "RAZ", 1, 0, 0, 0ull},
|
|
{"PID" , 0, 6, 784, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 784, "RAZ", 1, 0, 0, 0ull},
|
|
{"RATE_LIM" , 8, 24, 784, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 784, "RAZ", 1, 0, 0, 0ull},
|
|
{"QUEUE" , 0, 7, 785, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT" , 7, 6, 785, "WR0", 1, 0, 0, 0ull},
|
|
{"INDEX" , 13, 3, 785, "WR0", 1, 0, 0, 0ull},
|
|
{"TAIL" , 16, 1, 785, "R/W", 1, 0, 0, 0ull},
|
|
{"BUF_PTR" , 17, 36, 785, "R/W", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 785, "R/W", 1, 0, 0, 0ull},
|
|
{"STATIC_Q" , 61, 1, 785, "R/W", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 62, 1, 785, "R/W", 1, 0, 0, 0ull},
|
|
{"S_TAIL" , 63, 1, 785, "R/W", 1, 0, 0, 0ull},
|
|
{"QID" , 0, 7, 786, "R/W", 1, 0, 0, 0ull},
|
|
{"PID" , 7, 6, 786, "WR0", 1, 0, 0, 0ull},
|
|
{"RESERVED_13_52" , 13, 40, 786, "RAZ", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 786, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_61_63" , 61, 3, 786, "RAZ", 1, 0, 0, 0ull},
|
|
{"DAT_PTR" , 0, 4, 787, "RO", 1, 0, 0, 0ull},
|
|
{"DAT_DAT" , 4, 2, 787, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_CTL" , 6, 2, 787, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_QSB" , 8, 3, 787, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_QCB" , 11, 2, 787, "RO", 1, 0, 0, 0ull},
|
|
{"NCB_INB" , 13, 2, 787, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_PSB" , 15, 8, 787, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_NXT" , 23, 1, 787, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_CHK" , 24, 3, 787, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_WIF" , 27, 1, 787, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_STA" , 28, 1, 787, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_CTL" , 29, 3, 787, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_DAT" , 32, 1, 787, "RO", 1, 0, 0, 0ull},
|
|
{"IOB" , 33, 1, 787, "RO", 1, 0, 0, 0ull},
|
|
{"CSR" , 34, 1, 787, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_35_63" , 35, 29, 787, "RAZ", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 13, 788, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_19" , 13, 7, 788, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 20, 3, 788, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 788, "RAZ", 1, 0, 0, 0ull},
|
|
{"ASSERTS" , 0, 64, 789, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 64, 790, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 64, 791, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 64, 792, "RO", 0, 0, 0ull, 0ull},
|
|
{"ENGINE0" , 0, 4, 793, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE1" , 4, 4, 793, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE2" , 8, 4, 793, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE3" , 12, 4, 793, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE4" , 16, 4, 793, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE5" , 20, 4, 793, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE6" , 24, 4, 793, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE7" , 28, 4, 793, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE8" , 32, 4, 793, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE9" , 36, 4, 793, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_40_63" , 40, 24, 793, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 10, 794, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 794, "RAZ", 1, 0, 0, 0ull},
|
|
{"PARITY" , 0, 1, 795, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 1, 1, 795, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CURRZERO" , 2, 1, 795, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 795, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENA_PKO" , 0, 1, 796, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENA_DWB" , 1, 1, 796, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STORE_BE" , 2, 1, 796, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 3, 1, 796, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 796, "RAZ", 1, 0, 0, 0ull},
|
|
{"MODE0" , 0, 3, 797, "R/W", 0, 0, 2ull, 2ull},
|
|
{"MODE1" , 3, 3, 797, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_6_63" , 6, 58, 797, "RAZ", 1, 0, 0, 0ull},
|
|
{"PARITY" , 0, 1, 798, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 1, 1, 798, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CURRZERO" , 2, 1, 798, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 798, "RAZ", 1, 0, 0, 0ull},
|
|
{"MODE" , 0, 2, 799, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 799, "RAZ", 1, 0, 0, 0ull},
|
|
{"QID7" , 0, 1, 800, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDX3" , 1, 1, 800, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 800, "RAZ", 1, 0, 0, 0ull},
|
|
{"INDEX" , 0, 8, 801, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 8, 8, 801, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 801, "RAZ", 1, 0, 0, 0ull},
|
|
{"ADR0" , 0, 1, 802, "RO", 0, 0, 0ull, 0ull},
|
|
{"ADR1" , 1, 1, 802, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEND0" , 2, 1, 802, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEND1" , 3, 1, 802, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBR0" , 4, 1, 802, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBR1" , 5, 1, 802, "RO", 0, 0, 0ull, 0ull},
|
|
{"FIDX" , 6, 1, 802, "RO", 0, 0, 0ull, 0ull},
|
|
{"INDEX" , 7, 1, 802, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBT" , 8, 1, 802, "RO", 0, 0, 0ull, 0ull},
|
|
{"CAM" , 9, 1, 802, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_15" , 10, 6, 802, "RAZ", 1, 1, 0, 0},
|
|
{"PP" , 16, 12, 802, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 802, "RAZ", 1, 1, 0, 0},
|
|
{"DS_PC" , 0, 32, 803, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 803, "RAZ", 1, 1, 0, 0},
|
|
{"SBE" , 0, 1, 804, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DBE" , 1, 1, 804, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SBE_IE" , 2, 1, 804, "R/W", 0, 1, 0ull, 0},
|
|
{"DBE_IE" , 3, 1, 804, "R/W", 0, 1, 0ull, 0},
|
|
{"SYN" , 4, 5, 804, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_9_11" , 9, 3, 804, "RAZ", 1, 1, 0, 0},
|
|
{"RPE" , 12, 1, 804, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPE_IE" , 13, 1, 804, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_15" , 14, 2, 804, "RAZ", 1, 1, 0, 0},
|
|
{"IOP" , 16, 13, 804, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_31" , 29, 3, 804, "RAZ", 1, 1, 0, 0},
|
|
{"IOP_IE" , 32, 13, 804, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_45_63" , 45, 19, 804, "RAZ", 1, 1, 0, 0},
|
|
{"NBR_THR" , 0, 5, 805, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PFR_DIS" , 5, 1, 805, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 805, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 32, 806, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 806, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 32, 807, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 807, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_INT" , 0, 8, 808, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 808, "RAZ", 1, 1, 0, 0},
|
|
{"INT_EN" , 0, 8, 809, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 809, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_THR" , 0, 32, 810, "R/W", 0, 1, 4294967295ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 810, "RAZ", 1, 1, 0, 0},
|
|
{"NOS_CNT" , 0, 12, 811, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_12_63" , 12, 52, 811, "RAZ", 1, 1, 0, 0},
|
|
{"NW_TIM" , 0, 10, 812, "R/W", 0, 0, 0ull, 1023ull},
|
|
{"RESERVED_10_63" , 10, 54, 812, "RAZ", 1, 1, 0, 0},
|
|
{"RST_MSK" , 0, 8, 813, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 813, "RAZ", 1, 1, 0, 0},
|
|
{"GRP_MSK" , 0, 16, 814, "R/W", 0, 0, 65535ull, 65535ull},
|
|
{"QOS0_PRI" , 16, 4, 814, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS1_PRI" , 20, 4, 814, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS2_PRI" , 24, 4, 814, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS3_PRI" , 28, 4, 814, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS4_PRI" , 32, 4, 814, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS5_PRI" , 36, 4, 814, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS6_PRI" , 40, 4, 814, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS7_PRI" , 44, 4, 814, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 814, "RAZ", 1, 1, 0, 0},
|
|
{"RND" , 0, 8, 815, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P1" , 8, 8, 815, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P2" , 16, 8, 815, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P3" , 24, 8, 815, "R/W", 0, 1, 255ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 815, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_THR" , 0, 11, 816, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_11_11" , 11, 1, 816, "RAZ", 1, 1, 0, 0},
|
|
{"MAX_THR" , 12, 11, 816, "R/W", 0, 1, 2047ull, 0},
|
|
{"RESERVED_23_23" , 23, 1, 816, "RAZ", 1, 1, 0, 0},
|
|
{"FREE_CNT" , 24, 12, 816, "RO", 0, 1, 2027ull, 0},
|
|
{"BUF_CNT" , 36, 12, 816, "RO", 0, 1, 0ull, 0},
|
|
{"DES_CNT" , 48, 12, 816, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 816, "RAZ", 1, 1, 0, 0},
|
|
{"TS_PC" , 0, 32, 817, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 817, "RAZ", 1, 1, 0, 0},
|
|
{"WA_PC" , 0, 32, 818, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 818, "RAZ", 1, 1, 0, 0},
|
|
{"WA_PC" , 0, 32, 819, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 819, "RAZ", 1, 1, 0, 0},
|
|
{"WQ_INT" , 0, 16, 820, "R/W1C", 0, 1, 0ull, 0},
|
|
{"IQ_DIS" , 16, 16, 820, "R/W1", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 820, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 12, 821, "RO", 0, 1, 0ull, 0},
|
|
{"DS_CNT" , 12, 12, 821, "RO", 0, 1, 0ull, 0},
|
|
{"TC_CNT" , 24, 4, 821, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_63" , 28, 36, 821, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 822, "RAZ", 1, 1, 0, 0},
|
|
{"PC_THR" , 8, 20, 822, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_31" , 28, 4, 822, "RAZ", 1, 1, 0, 0},
|
|
{"PC" , 32, 28, 822, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 822, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_THR" , 0, 11, 823, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_11_11" , 11, 1, 823, "RAZ", 1, 1, 0, 0},
|
|
{"DS_THR" , 12, 11, 823, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_23_23" , 23, 1, 823, "RAZ", 1, 1, 0, 0},
|
|
{"TC_THR" , 24, 4, 823, "R/W", 0, 1, 0ull, 0},
|
|
{"TC_EN" , 28, 1, 823, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 823, "RAZ", 1, 1, 0, 0},
|
|
{"WS_PC" , 0, 32, 824, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 824, "RAZ", 1, 1, 0, 0},
|
|
{"IWORD" , 0, 64, 825, "RO", 1, 1, 0, 0},
|
|
{"P_DAT" , 0, 64, 826, "RO", 1, 1, 0, 0},
|
|
{"Q_DAT" , 0, 64, 827, "RO", 1, 1, 0, 0},
|
|
{"DAT" , 0, 2, 828, "RO", 1, 0, 0, 0ull},
|
|
{"NCB_INB" , 2, 2, 828, "RO", 1, 0, 0, 0ull},
|
|
{"NCB_OUB" , 4, 1, 828, "RO", 1, 0, 0, 0ull},
|
|
{"STA" , 5, 1, 828, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 828, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PTR" , 0, 33, 829, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 33, 13, 829, "R/W", 0, 1, 0ull, 0},
|
|
{"POOL" , 46, 3, 829, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB" , 49, 9, 829, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_58_63" , 58, 6, 829, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 0, 1, 830, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STORE_LE" , 1, 1, 830, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAX_READ" , 2, 4, 830, "R/W", 0, 0, 8ull, 8ull},
|
|
{"RESERVED_6_63" , 6, 58, 830, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STATE" , 0, 5, 831, "RO", 1, 1, 0, 0},
|
|
{"COMMIT" , 5, 1, 831, "RO", 1, 1, 0, 0},
|
|
{"OWORDPV" , 6, 1, 831, "RO", 1, 1, 0, 0},
|
|
{"OWORDQV" , 7, 1, 831, "RO", 1, 1, 0, 0},
|
|
{"IWIDX" , 8, 6, 831, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_14_15" , 14, 2, 831, "RAZ", 1, 1, 0, 0},
|
|
{"IRIDX" , 16, 6, 831, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_22_31" , 22, 10, 831, "RAZ", 1, 1, 0, 0},
|
|
{"LOOP" , 32, 25, 831, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_57_63" , 57, 7, 831, "RAZ", 1, 1, 0, 0},
|
|
{"CWORD" , 0, 64, 832, "RO", 1, 1, 0, 0},
|
|
{"PTR" , 0, 40, 833, "RO", 1, 1, 0, 0},
|
|
{"SIZE" , 40, 16, 833, "RO", 1, 1, 0, 0},
|
|
{"FLAGS" , 56, 8, 833, "RO", 1, 1, 0, 0},
|
|
{"INDEX" , 0, 8, 834, "RO", 1, 1, 0, 0},
|
|
{"SOD" , 8, 1, 834, "RO", 1, 1, 0, 0},
|
|
{"EOD" , 9, 1, 834, "RO", 1, 1, 0, 0},
|
|
{"WC" , 10, 1, 834, "RO", 1, 1, 0, 0},
|
|
{"P" , 11, 1, 834, "RO", 1, 1, 0, 0},
|
|
{"Q" , 12, 1, 834, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_13_63" , 13, 51, 834, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 15, 835, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_15_63" , 15, 49, 835, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OWORDP" , 0, 64, 836, "RO", 1, 1, 0, 0},
|
|
{"OWORDQ" , 0, 64, 837, "RO", 1, 1, 0, 0},
|
|
{"RWORD" , 0, 64, 838, "RO", 1, 1, 0, 0},
|
|
{"N0CREDS" , 0, 4, 839, "RO", 0, 0, 8ull, 0ull},
|
|
{"N1CREDS" , 4, 4, 839, "RO", 0, 0, 8ull, 0ull},
|
|
{"POWCREDS" , 8, 2, 839, "RO", 0, 0, 2ull, 0ull},
|
|
{"RESERVED_10_11" , 10, 2, 839, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FPACREDS" , 12, 2, 839, "RO", 0, 0, 1ull, 0ull},
|
|
{"WCCREDS" , 14, 2, 839, "RO", 0, 0, 0ull, 0ull},
|
|
{"NIWIDX0" , 16, 4, 839, "RO", 1, 1, 0, 0},
|
|
{"NIRIDX0" , 20, 4, 839, "RO", 1, 1, 0, 0},
|
|
{"NIWIDX1" , 24, 4, 839, "RO", 1, 1, 0, 0},
|
|
{"NIRIDX1" , 28, 4, 839, "RO", 1, 1, 0, 0},
|
|
{"NIRVAL6" , 32, 5, 839, "RO", 1, 1, 0, 0},
|
|
{"NIRARB6" , 37, 1, 839, "RO", 1, 1, 0, 0},
|
|
{"NIRQUE6" , 38, 2, 839, "RO", 1, 1, 0, 0},
|
|
{"NIROPC6" , 40, 3, 839, "RO", 1, 1, 0, 0},
|
|
{"NIRVAL7" , 43, 5, 839, "RO", 1, 1, 0, 0},
|
|
{"NIRQUE7" , 48, 2, 839, "RO", 1, 1, 0, 0},
|
|
{"NIROPC7" , 50, 3, 839, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_53_63" , 53, 11, 839, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PTR" , 0, 40, 840, "RO", 1, 1, 0, 0},
|
|
{"SIZE" , 40, 16, 840, "RO", 1, 1, 0, 0},
|
|
{"CNT" , 56, 8, 840, "RO", 1, 1, 0, 0},
|
|
{"CNT" , 0, 15, 841, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_15_63" , 15, 49, 841, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PTR" , 0, 40, 842, "RO", 1, 1, 0, 0},
|
|
{"SIZE" , 40, 16, 842, "RO", 1, 1, 0, 0},
|
|
{"FLAGS" , 56, 8, 842, "RO", 1, 1, 0, 0},
|
|
{"INDEX" , 0, 8, 843, "RO", 1, 1, 0, 0},
|
|
{"MUL" , 8, 8, 843, "RO", 1, 1, 0, 0},
|
|
{"P" , 16, 1, 843, "RO", 1, 1, 0, 0},
|
|
{"Q" , 17, 1, 843, "RO", 1, 1, 0, 0},
|
|
{"INI" , 18, 1, 843, "RO", 1, 1, 0, 0},
|
|
{"EOD" , 19, 1, 843, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_20_63" , 20, 44, 843, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 0, 1, 844, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 844, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 0, 1, 845, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 845, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"COEFFS" , 0, 8, 846, "R/W", 0, 0, 29ull, 29ull},
|
|
{"RESERVED_8_63" , 8, 56, 846, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"INDEX" , 0, 16, 847, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 16, 16, 847, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 847, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MEM" , 0, 1, 848, "RO", 0, 0, 0ull, 0ull},
|
|
{"RRC" , 1, 1, 848, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 848, "RAZ", 1, 1, 0, 0},
|
|
{"ENT_EN" , 0, 1, 849, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNG_EN" , 1, 1, 849, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNM_RST" , 2, 1, 849, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNG_RST" , 3, 1, 849, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EXP_ENT" , 4, 1, 849, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENT_SEL" , 5, 4, 849, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 849, "RAZ", 1, 1, 0, 0},
|
|
{"PHASE" , 0, 8, 850, "R/W", 0, 0, 100ull, 100ull},
|
|
{"SAMPLE" , 8, 4, 850, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PREAMBLE" , 12, 1, 850, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CLK_IDLE" , 13, 1, 850, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_14" , 14, 1, 850, "RAZ", 1, 1, 0, 0},
|
|
{"SAMPLE_MODE" , 15, 1, 850, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SAMPLE_HI" , 16, 5, 850, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_23" , 21, 3, 850, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 24, 1, 850, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_63" , 25, 39, 850, "RAZ", 1, 1, 0, 0},
|
|
{"REG_ADR" , 0, 5, 851, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 851, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_ADR" , 8, 5, 851, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_13_15" , 13, 3, 851, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_OP" , 16, 2, 851, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 851, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 852, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 852, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 853, "RO", 0, 1, 0ull, 0},
|
|
{"VAL" , 16, 1, 853, "RO", 0, 1, 0ull, 0},
|
|
{"PENDING" , 17, 1, 853, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 853, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 854, "R/W", 0, 1, 0ull, 0},
|
|
{"VAL" , 16, 1, 854, "RO", 0, 1, 0ull, 0},
|
|
{"PENDING" , 17, 1, 854, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 854, "RAZ", 1, 1, 0, 0},
|
|
{"INTERVAL" , 0, 22, 855, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 855, "RAZ", 1, 0, 0, 0ull},
|
|
{"COUNT" , 24, 22, 855, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_46_46" , 46, 1, 855, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENA" , 47, 1, 855, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 855, "RAZ", 1, 0, 0, 0ull},
|
|
{"BSIZE" , 0, 20, 856, "RO", 1, 0, 0, 0ull},
|
|
{"BASE" , 20, 31, 856, "RO", 1, 0, 0, 0ull},
|
|
{"BUCKET" , 51, 13, 856, "RO", 1, 0, 0, 0ull},
|
|
{"BUCKET" , 0, 7, 857, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 857, "RAZ", 1, 0, 0, 0ull},
|
|
{"CSIZE" , 8, 13, 857, "RO", 1, 0, 0, 0ull},
|
|
{"CPOOL" , 21, 3, 857, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 857, "RAZ", 1, 0, 0, 0ull},
|
|
{"RING" , 0, 4, 858, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NUM_BUCKETS" , 4, 20, 858, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIRST_BUCKET" , 24, 31, 858, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_55_63" , 55, 9, 858, "RAZ", 1, 0, 0, 0ull},
|
|
{"RING" , 0, 4, 859, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTERVAL" , 4, 22, 859, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WORDS_PER_CHUNK" , 26, 13, 859, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 39, 3, 859, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENABLE" , 42, 1, 859, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_43_63" , 43, 21, 859, "RAZ", 1, 0, 0, 0ull},
|
|
{"CTL" , 0, 1, 860, "RO", 1, 0, 0, 0ull},
|
|
{"NCB" , 1, 1, 860, "RO", 1, 0, 0, 0ull},
|
|
{"STA" , 2, 2, 860, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 860, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 16, 861, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 861, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENABLE_TIMERS" , 0, 1, 862, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENABLE_DWB" , 1, 1, 862, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 2, 1, 862, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 862, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 16, 863, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 863, "RAZ", 1, 0, 0, 0ull},
|
|
{"INDEX" , 0, 8, 864, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 8, 8, 864, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 864, "RAZ", 1, 0, 0, 0ull},
|
|
{"TDF0" , 0, 1, 865, "RO", 0, 0, 0ull, 0ull},
|
|
{"TDF1" , 1, 1, 865, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCF" , 2, 1, 865, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 865, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ENA" , 0, 1, 866, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WRAP" , 1, 1, 866, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRIG_CTL" , 2, 2, 866, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIME_GRN" , 4, 3, 866, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FULL_THR" , 7, 2, 866, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CIU_TRG" , 9, 1, 866, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CIU_THR" , 10, 1, 866, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_TRG" , 11, 1, 866, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_THR" , 12, 1, 866, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_ENA" , 13, 1, 866, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IGNORE_O" , 14, 1, 866, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 866, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WPTR" , 0, 8, 867, "RO", 0, 0, 0ull, 0ull},
|
|
{"RPTR" , 8, 8, 867, "RO", 0, 0, 0ull, 0ull},
|
|
{"CYCLES" , 16, 48, 867, "RO", 0, 0, 0ull, 0ull},
|
|
{"WPTR" , 0, 10, 868, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_11" , 10, 2, 868, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RPTR" , 12, 10, 868, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 868, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CYCLES" , 24, 40, 868, "RO", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 869, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 869, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 870, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 870, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 871, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 871, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 871, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 871, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 871, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 871, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 871, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 871, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 871, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 871, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 871, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 871, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 871, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 871, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 871, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 871, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SAA" , 16, 1, 871, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_17_63" , 17, 47, 871, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 872, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 872, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 872, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 872, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 872, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 872, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 872, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 872, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 872, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 872, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 872, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 872, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 873, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 873, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 873, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 873, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 873, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 873, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CIU_TRG" , 0, 1, 874, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CIU_THR" , 1, 1, 874, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MCD0_TRG" , 2, 1, 874, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MCD0_THR" , 3, 1, 874, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 874, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DATA" , 0, 64, 875, "RO", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 876, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 876, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 877, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 877, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 878, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 878, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 878, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 878, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 878, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 878, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 878, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 878, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 878, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 878, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 878, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 878, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 878, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 878, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 878, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 878, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SAA" , 16, 1, 878, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_17_63" , 17, 47, 878, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 879, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 879, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 879, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 879, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 879, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 879, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 879, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 879, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 879, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 879, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 879, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 879, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 880, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 880, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 880, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 880, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 880, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 880, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 881, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 881, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 882, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 882, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 883, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 883, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 883, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 883, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 883, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 883, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 883, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 883, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 883, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 883, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 883, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 883, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 883, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 883, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 883, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 883, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SAA" , 16, 1, 883, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_17_63" , 17, 47, 883, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 884, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 884, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 884, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 884, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 884, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 884, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 884, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 884, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 884, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 884, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 884, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 884, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 885, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 885, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 885, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 885, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 885, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 885, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"INEPINT" , 0, 16, 886, "RO", 0, 0, 0ull, 0ull},
|
|
{"OUTEPINT" , 16, 16, 886, "RO", 0, 0, 0ull, 0ull},
|
|
{"INEPMSK" , 0, 16, 887, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OUTEPMSK" , 16, 16, 887, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DEVSPD" , 0, 2, 888, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NZSTSOUTHSHK" , 2, 1, 888, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 888, "RAZ", 1, 1, 0, 0},
|
|
{"DEVADDR" , 4, 7, 888, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PERFRINT" , 11, 2, 888, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_17" , 13, 5, 888, "RAZ", 1, 1, 0, 0},
|
|
{"EPMISCNT" , 18, 5, 888, "R/W", 0, 0, 8ull, 0ull},
|
|
{"RESERVED_23_31" , 23, 9, 888, "RAZ", 1, 1, 0, 0},
|
|
{"RMTWKUPSIG" , 0, 1, 889, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SFTDISCON" , 1, 1, 889, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GNPINNAKSTS" , 2, 1, 889, "RO", 0, 0, 0ull, 0ull},
|
|
{"GOUTNAKSTS" , 3, 1, 889, "RO", 0, 0, 0ull, 0ull},
|
|
{"TSTCTL" , 4, 3, 889, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SGNPINNAK" , 7, 1, 889, "WO", 0, 0, 0ull, 0ull},
|
|
{"CGNPINNAK" , 8, 1, 889, "WO", 0, 0, 0ull, 0ull},
|
|
{"SGOUTNAK" , 9, 1, 889, "WO", 0, 0, 0ull, 0ull},
|
|
{"CGOUTNAK" , 10, 1, 889, "WO", 0, 0, 0ull, 0ull},
|
|
{"PWRONPRGDONE" , 11, 1, 889, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_31" , 12, 20, 889, "RAZ", 1, 1, 0, 0},
|
|
{"MPS" , 0, 11, 890, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NEXTEP" , 11, 4, 890, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBACTEP" , 15, 1, 890, "R/W", 0, 0, 1ull, 0ull},
|
|
{"DPID" , 16, 1, 890, "RO", 0, 0, 0ull, 0ull},
|
|
{"NAKSTS" , 17, 1, 890, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTYPE" , 18, 2, 890, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 890, "RAZ", 1, 1, 0, 0},
|
|
{"STALL" , 21, 1, 890, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFNUM" , 22, 4, 890, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNAK" , 26, 1, 890, "WO", 0, 0, 0ull, 0ull},
|
|
{"SNAK" , 27, 1, 890, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD0PID" , 28, 1, 890, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD1PID" , 29, 1, 890, "WO", 0, 0, 0ull, 0ull},
|
|
{"EPDIS" , 30, 1, 890, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPENA" , 31, 1, 890, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XFERCOMPL" , 0, 1, 891, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLD" , 1, 1, 891, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AHBERR" , 2, 1, 891, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TIMEOUT" , 3, 1, 891, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTKNTXFEMP" , 4, 1, 891, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTKNEPMIS" , 5, 1, 891, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INEPNAKEFF" , 6, 1, 891, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_31" , 7, 25, 891, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPLMSK" , 0, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLDMSK" , 1, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AHBERRMSK" , 2, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMEOUTMSK" , 3, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTKNTXFEMPMSK" , 4, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTKNEPMISMSK" , 5, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INEPNAKEFFMSK" , 6, 1, 892, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_31" , 7, 25, 892, "RAZ", 1, 1, 0, 0},
|
|
{"XFERSIZE" , 0, 19, 893, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKTCNT" , 19, 10, 893, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MC" , 29, 2, 893, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_31" , 31, 1, 893, "RAZ", 1, 1, 0, 0},
|
|
{"MPS" , 0, 11, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_14" , 11, 4, 894, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"USBACTEP" , 15, 1, 894, "R/W", 0, 0, 1ull, 0ull},
|
|
{"DPID" , 16, 1, 894, "RO", 0, 0, 0ull, 0ull},
|
|
{"NAKSTS" , 17, 1, 894, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTYPE" , 18, 2, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SNP" , 20, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STALL" , 21, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_25" , 22, 4, 894, "RAZ", 1, 1, 0, 0},
|
|
{"CNAK" , 26, 1, 894, "WO", 0, 0, 0ull, 0ull},
|
|
{"SNAK" , 27, 1, 894, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD0PID" , 28, 1, 894, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD1PID" , 29, 1, 894, "WO", 0, 0, 0ull, 0ull},
|
|
{"EPDIS" , 30, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPENA" , 31, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XFERCOMPL" , 0, 1, 895, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLD" , 1, 1, 895, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AHBERR" , 2, 1, 895, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SETUP" , 3, 1, 895, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OUTTKNEPDIS" , 4, 1, 895, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 895, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPLMSK" , 0, 1, 896, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLDMSK" , 1, 1, 896, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AHBERRMSK" , 2, 1, 896, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SETUPMSK" , 3, 1, 896, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OUTTKNEPDISMSK" , 4, 1, 896, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 896, "RAZ", 1, 1, 0, 0},
|
|
{"XFERSIZE" , 0, 19, 897, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKTCNT" , 19, 10, 897, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MC" , 29, 2, 897, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_31" , 31, 1, 897, "RAZ", 1, 1, 0, 0},
|
|
{"DPTXFSTADDR" , 0, 16, 898, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPTXFSIZE" , 16, 16, 898, "RO", 0, 0, 1896ull, 1896ull},
|
|
{"SUSPSTS" , 0, 1, 899, "RO", 0, 0, 0ull, 0ull},
|
|
{"ENUMSPD" , 1, 2, 899, "RO", 0, 0, 0ull, 0ull},
|
|
{"ERRTICERR" , 3, 1, 899, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 899, "RAZ", 1, 1, 0, 0},
|
|
{"SOFFN" , 8, 14, 899, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_31" , 22, 10, 899, "RAZ", 1, 1, 0, 0},
|
|
{"INTKNWPTR" , 0, 5, 900, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_6" , 5, 2, 900, "RAZ", 1, 1, 0, 0},
|
|
{"WRAPBIT" , 7, 1, 900, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 8, 24, 900, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 0, 32, 901, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 0, 32, 902, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 0, 32, 903, "RO", 0, 0, 0ull, 0ull},
|
|
{"GLBLINTRMSK" , 0, 1, 904, "R/W", 0, 0, 0ull, 1ull},
|
|
{"HBSTLEN" , 1, 4, 904, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMAEN" , 5, 1, 904, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_6" , 6, 1, 904, "RAZ", 1, 1, 0, 0},
|
|
{"NPTXFEMPLVL" , 7, 1, 904, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PTXFEMPLVL" , 8, 1, 904, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_9_31" , 9, 23, 904, "RAZ", 1, 1, 0, 0},
|
|
{"EPDIR" , 0, 32, 905, "RO", 0, 0, 0ull, 0ull},
|
|
{"OTGMODE" , 0, 3, 906, "RO", 0, 0, 2ull, 2ull},
|
|
{"OTGARCH" , 3, 2, 906, "RO", 0, 0, 1ull, 1ull},
|
|
{"SINGPNT" , 5, 1, 906, "RO", 0, 0, 0ull, 0ull},
|
|
{"HSPHYTYPE" , 6, 2, 906, "RO", 0, 0, 1ull, 1ull},
|
|
{"FSPHYTYPE" , 8, 2, 906, "RO", 0, 0, 0ull, 0ull},
|
|
{"NUMDEVEPS" , 10, 4, 906, "RO", 0, 0, 4ull, 4ull},
|
|
{"NUMHSTCHNL" , 14, 4, 906, "RO", 0, 0, 7ull, 7ull},
|
|
{"PERIOSUPPORT" , 18, 1, 906, "RO", 0, 0, 1ull, 1ull},
|
|
{"DYNFIFOSIZING" , 19, 1, 906, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_20_21" , 20, 2, 906, "RAZ", 1, 1, 0, 0},
|
|
{"NPTXQDEPTH" , 22, 2, 906, "RO", 0, 0, 2ull, 2ull},
|
|
{"PTXQDEPTH" , 24, 2, 906, "RO", 0, 0, 2ull, 2ull},
|
|
{"TKNQDEPTH" , 26, 5, 906, "RO", 0, 0, 30ull, 30ull},
|
|
{"RESERVED_31_31" , 31, 1, 906, "RAZ", 1, 1, 0, 0},
|
|
{"XFERSIZEWIDTH" , 0, 4, 907, "RO", 0, 0, 8ull, 8ull},
|
|
{"PKTSIZEWIDTH" , 4, 3, 907, "RO", 0, 0, 6ull, 6ull},
|
|
{"OTGEN" , 7, 1, 907, "RO", 0, 0, 1ull, 1ull},
|
|
{"I2C_SELECTION" , 8, 1, 907, "RO", 0, 0, 0ull, 0ull},
|
|
{"VENDOR_CONTROL_INTERFACE_SUPPORT", 9, 1, 907, "RO", 0, 0, 0ull, 0ull},
|
|
{"OPTFEATURE" , 10, 1, 907, "RO", 0, 0, 1ull, 1ull},
|
|
{"RSTTYPE" , 11, 1, 907, "RO", 0, 0, 0ull, 0ull},
|
|
{"AHBPHYSYNC" , 12, 1, 907, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 907, "RAZ", 1, 1, 0, 0},
|
|
{"DFIFODEPTH" , 16, 16, 907, "RO", 0, 0, 1824ull, 1824ull},
|
|
{"NUMDEVPERIOEPS" , 0, 4, 908, "RO", 0, 0, 4ull, 4ull},
|
|
{"ENABLEPWROPT" , 4, 1, 908, "RO", 0, 0, 0ull, 0ull},
|
|
{"AHBFREQ" , 5, 1, 908, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_13" , 6, 8, 908, "RAZ", 1, 1, 0, 0},
|
|
{"PHYDATAWIDTH" , 14, 2, 908, "RO", 0, 0, 1ull, 1ull},
|
|
{"NUMCTLEPS" , 16, 4, 908, "RO", 0, 0, 4ull, 4ull},
|
|
{"IDDGFLTR" , 20, 1, 908, "RO", 0, 0, 1ull, 1ull},
|
|
{"VBUSVALIDFLTR" , 21, 1, 908, "RO", 0, 0, 1ull, 1ull},
|
|
{"AVALIDFLTR" , 22, 1, 908, "RO", 0, 0, 0ull, 0ull},
|
|
{"BVALIDFLTR" , 23, 1, 908, "RO", 0, 0, 0ull, 0ull},
|
|
{"SESSENDFLTR" , 24, 1, 908, "RO", 0, 0, 0ull, 0ull},
|
|
{"ENDEDTRFIFO" , 25, 1, 908, "RO", 0, 0, 0ull, 0ull},
|
|
{"NUMDEVMODINEND" , 26, 4, 908, "RO", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_30_31" , 30, 2, 908, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 909, "RAZ", 1, 1, 0, 0},
|
|
{"MODEMISMSK" , 1, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OTGINTMSK" , 2, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SOFMSK" , 3, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RXFLVLMSK" , 4, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NPTXFEMPMSK" , 5, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GINNAKEFFMSK" , 6, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GOUTNAKEFFMSK" , 7, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ULPICKINTMSK" , 8, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"I2CINT" , 9, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ERLYSUSPMSK" , 10, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBSUSPMSK" , 11, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBRSTMSK" , 12, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENUMDONEMSK" , 13, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ISOOUTDROPMSK" , 14, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EOPFMSK" , 15, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 909, "RAZ", 1, 1, 0, 0},
|
|
{"EPMISMSK" , 17, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INEPINTMSK" , 18, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OEPINTMSK" , 19, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INCOMPISOINMSK" , 20, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INCOMPLPMSK" , 21, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FETSUSPMSK" , 22, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 909, "RAZ", 1, 1, 0, 0},
|
|
{"PRTINTMSK" , 24, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HCHINTMSK" , 25, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PTXFEMPMSK" , 26, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 909, "RAZ", 1, 1, 0, 0},
|
|
{"CONIDSTSCHNGMSK" , 28, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DISCONNINTMSK" , 29, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SESSREQINTMSK" , 30, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WKUPINTMSK" , 31, 1, 909, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CURMOD" , 0, 1, 910, "RO", 0, 0, 0ull, 0ull},
|
|
{"MODEMIS" , 1, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OTGINT" , 2, 1, 910, "RO", 0, 0, 0ull, 0ull},
|
|
{"SOF" , 3, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXFLVL" , 4, 1, 910, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPTXFEMP" , 5, 1, 910, "RO", 0, 0, 0ull, 0ull},
|
|
{"GINNAKEFF" , 6, 1, 910, "RO", 0, 0, 0ull, 0ull},
|
|
{"GOUTNAKEFF" , 7, 1, 910, "RO", 0, 0, 0ull, 0ull},
|
|
{"ULPICKINT" , 8, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I2CINT" , 9, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ERLYSUSP" , 10, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USBSUSP" , 11, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USBRST" , 12, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ENUMDONE" , 13, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ISOOUTDROP" , 14, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EOPF" , 15, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 910, "RAZ", 1, 1, 0, 0},
|
|
{"EPMIS" , 17, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IEPINT" , 18, 1, 910, "RO", 0, 0, 0ull, 0ull},
|
|
{"OEPINT" , 19, 1, 910, "RO", 0, 0, 0ull, 0ull},
|
|
{"INCOMPISOIN" , 20, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INCOMPLP" , 21, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FETSUSP" , 22, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 910, "RAZ", 1, 1, 0, 0},
|
|
{"PRTINT" , 24, 1, 910, "RO", 0, 0, 0ull, 0ull},
|
|
{"HCHINT" , 25, 1, 910, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTXFEMP" , 26, 1, 910, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 910, "RAZ", 1, 1, 0, 0},
|
|
{"CONIDSTSCHNG" , 28, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DISCONNINT" , 29, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SESSREQINT" , 30, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WKUPINT" , 31, 1, 910, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NPTXFSTADDR" , 0, 16, 911, "R/W", 0, 0, 1824ull, 456ull},
|
|
{"NPTXFDEP" , 16, 16, 911, "R/W", 0, 0, 1824ull, 912ull},
|
|
{"NPTXFSPCAVAIL" , 0, 16, 912, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPTXQSPCAVAIL" , 16, 8, 912, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPTXQTOP" , 24, 7, 912, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_31" , 31, 1, 912, "RAZ", 1, 1, 0, 0},
|
|
{"SESREQSCS" , 0, 1, 913, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SESREQ" , 1, 1, 913, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_7" , 2, 6, 913, "RAZ", 1, 1, 0, 0},
|
|
{"HSTNEGSCS" , 8, 1, 913, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HNPREQ" , 9, 1, 913, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HSTSETHNPEN" , 10, 1, 913, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DEVHNPEN" , 11, 1, 913, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_15" , 12, 4, 913, "RAZ", 1, 1, 0, 0},
|
|
{"CONIDSTS" , 16, 1, 913, "RO", 1, 1, 0, 0},
|
|
{"DBNCTIME" , 17, 1, 913, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASESVLD" , 18, 1, 913, "RO", 1, 1, 0, 0},
|
|
{"BSESVLD" , 19, 1, 913, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_20_31" , 20, 12, 913, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 914, "RAZ", 1, 1, 0, 0},
|
|
{"SESENDDET" , 2, 1, 914, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_7" , 3, 5, 914, "RAZ", 1, 1, 0, 0},
|
|
{"SESREQSUCSTSCHNG" , 8, 1, 914, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"HSTNEGSUCSTSCHNG" , 9, 1, 914, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_16" , 10, 7, 914, "RAZ", 1, 1, 0, 0},
|
|
{"HSTNEGDET" , 17, 1, 914, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ADEVTOUTCHG" , 18, 1, 914, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DBNCEDONE" , 19, 1, 914, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 914, "RAZ", 1, 1, 0, 0},
|
|
{"CSFTRST" , 0, 1, 915, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HSFTRST" , 1, 1, 915, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMCNTRRST" , 2, 1, 915, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTKNQFLSH" , 3, 1, 915, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RXFFLSH" , 4, 1, 915, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFFLSH" , 5, 1, 915, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFNUM" , 6, 5, 915, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_29" , 11, 19, 915, "RAZ", 1, 1, 0, 0},
|
|
{"DMAREQ" , 30, 1, 915, "RO", 0, 0, 0ull, 0ull},
|
|
{"AHBIDLE" , 31, 1, 915, "RO", 0, 0, 1ull, 1ull},
|
|
{"RXFDEP" , 0, 16, 916, "R/W", 0, 0, 1824ull, 456ull},
|
|
{"RESERVED_16_31" , 16, 16, 916, "RAZ", 1, 1, 0, 0},
|
|
{"EPNUM" , 0, 4, 917, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 917, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 917, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 917, "RO", 0, 0, 0ull, 0ull},
|
|
{"FN" , 21, 4, 917, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_31" , 25, 7, 917, "RAZ", 1, 1, 0, 0},
|
|
{"CHNUM" , 0, 4, 918, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 918, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 918, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 918, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 918, "RAZ", 1, 1, 0, 0},
|
|
{"EPNUM" , 0, 4, 919, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 919, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 919, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 919, "RO", 0, 0, 0ull, 0ull},
|
|
{"FN" , 21, 4, 919, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_31" , 25, 7, 919, "RAZ", 1, 1, 0, 0},
|
|
{"CHNUM" , 0, 4, 920, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 920, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 920, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 920, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 920, "RAZ", 1, 1, 0, 0},
|
|
{"SYNOPSYSID" , 0, 32, 921, "RO", 1, 1, 0, 0},
|
|
{"TOUTCAL" , 0, 3, 922, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHYIF" , 3, 1, 922, "RO", 0, 0, 1ull, 1ull},
|
|
{"ULPI_UTMI_SEL" , 4, 1, 922, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSINTF" , 5, 1, 922, "WO", 0, 0, 0ull, 0ull},
|
|
{"PHYSEL" , 6, 1, 922, "WO", 0, 0, 0ull, 0ull},
|
|
{"DDRSEL" , 7, 1, 922, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SRPCAP" , 8, 1, 922, "RO", 0, 0, 0ull, 0ull},
|
|
{"HNPCAP" , 9, 1, 922, "RO", 0, 0, 0ull, 0ull},
|
|
{"USBTRDTIM" , 10, 4, 922, "R/W", 0, 0, 5ull, 5ull},
|
|
{"RESERVED_14_14" , 14, 1, 922, "RAZ", 1, 1, 0, 0},
|
|
{"PHYLPWRCLKSEL" , 15, 1, 922, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OTGI2CSEL" , 16, 1, 922, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 922, "RAZ", 1, 1, 0, 0},
|
|
{"HAINT" , 0, 16, 923, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_31" , 16, 16, 923, "RAZ", 1, 1, 0, 0},
|
|
{"HAINTMSK" , 0, 16, 924, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_31" , 16, 16, 924, "RAZ", 1, 1, 0, 0},
|
|
{"MPS" , 0, 11, 925, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPNUM" , 11, 4, 925, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPDIR" , 15, 1, 925, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 925, "RAZ", 1, 1, 0, 0},
|
|
{"LSPDDEV" , 17, 1, 925, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPTYPE" , 18, 2, 925, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EC" , 20, 2, 925, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DEVADDR" , 22, 7, 925, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ODDFRM" , 29, 1, 925, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHDIS" , 30, 1, 925, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHENA" , 31, 1, 925, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSLSPCLKSEL" , 0, 2, 926, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSLSSUPP" , 2, 1, 926, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_31" , 3, 29, 926, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPL" , 0, 1, 927, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CHHLTD" , 1, 1, 927, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AHBERR" , 2, 1, 927, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"STALL" , 3, 1, 927, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NAK" , 4, 1, 927, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ACK" , 5, 1, 927, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NYET" , 6, 1, 927, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"XACTERR" , 7, 1, 927, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BBLERR" , 8, 1, 927, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FRMOVRUN" , 9, 1, 927, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DATATGLERR" , 10, 1, 927, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_31" , 11, 21, 927, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPLMSK" , 0, 1, 928, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHHLTDMSK" , 1, 1, 928, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AHBERRMSK" , 2, 1, 928, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STALLMSK" , 3, 1, 928, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NAKMSK" , 4, 1, 928, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ACKMSK" , 5, 1, 928, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NYETMSK" , 6, 1, 928, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XACTERRMSK" , 7, 1, 928, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BBLERRMSK" , 8, 1, 928, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMOVRUNMSK" , 9, 1, 928, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DATATGLERRMSK" , 10, 1, 928, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_31" , 11, 21, 928, "RAZ", 1, 1, 0, 0},
|
|
{"PRTADDR" , 0, 7, 929, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HUBADDR" , 7, 7, 929, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XACTPOS" , 14, 2, 929, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COMPSPLT" , 16, 1, 929, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_30" , 17, 14, 929, "RAZ", 1, 1, 0, 0},
|
|
{"SPLTENA" , 31, 1, 929, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XFERSIZE" , 0, 19, 930, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKTCNT" , 19, 10, 930, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PID" , 29, 2, 930, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DOPNG" , 31, 1, 930, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRINT" , 0, 16, 931, "R/W", 0, 0, 2959ull, 3750ull},
|
|
{"RESERVED_16_31" , 16, 16, 931, "RAZ", 1, 1, 0, 0},
|
|
{"FRNUM" , 0, 16, 932, "RO", 0, 0, 16383ull, 0ull},
|
|
{"FRREM" , 16, 16, 932, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTCONNSTS" , 0, 1, 933, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTCONNDET" , 1, 1, 933, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTENA" , 2, 1, 933, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTENCHNG" , 3, 1, 933, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTOVRCURRACT" , 4, 1, 933, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTOVRCURRCHNG" , 5, 1, 933, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTRES" , 6, 1, 933, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTSUSP" , 7, 1, 933, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTRST" , 8, 1, 933, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 933, "RAZ", 1, 1, 0, 0},
|
|
{"PRTLNSTS" , 10, 2, 933, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTPWR" , 12, 1, 933, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTTSTCTL" , 13, 4, 933, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTSPD" , 17, 2, 933, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_31" , 19, 13, 933, "RAZ", 1, 1, 0, 0},
|
|
{"PTXFSTADDR" , 0, 16, 934, "R/W", 0, 0, 3648ull, 912ull},
|
|
{"PTXFSIZE" , 16, 16, 934, "R/W", 0, 0, 256ull, 456ull},
|
|
{"PTXFSPCAVAIL" , 0, 16, 935, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTXQSPCAVAIL" , 16, 8, 935, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTXQTOP" , 24, 8, 935, "RO", 0, 0, 0ull, 0ull},
|
|
{"DATA" , 0, 32, 936, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STOPPCLK" , 0, 1, 937, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GATEHCLK" , 1, 1, 937, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PWRCLMP" , 2, 1, 937, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSTPDWNMODULE" , 3, 1, 937, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHYSUSPENDED" , 4, 1, 937, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 937, "RAZ", 1, 1, 0, 0},
|
|
{"NOF_BIS" , 0, 1, 938, "RO", 0, 0, 0ull, 0ull},
|
|
{"NIF_BIS" , 1, 1, 938, "RO", 0, 0, 0ull, 0ull},
|
|
{"USBC_BIS" , 2, 1, 938, "RO", 0, 0, 0ull, 0ull},
|
|
{"N2UF_BIS" , 3, 1, 938, "RO", 0, 0, 0ull, 0ull},
|
|
{"E2HC_BIS" , 4, 1, 938, "RO", 0, 0, 0ull, 0ull},
|
|
{"U2NF_BIS" , 5, 1, 938, "RO", 0, 0, 0ull, 0ull},
|
|
{"U2NC_BIS" , 6, 1, 938, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 938, "RAZ", 1, 1, 0, 0},
|
|
{"DIVIDE" , 0, 3, 939, "R/W", 0, 0, 4ull, 0ull},
|
|
{"HRST" , 3, 1, 939, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PRST" , 4, 1, 939, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ENABLE" , 5, 1, 939, "R/W", 0, 0, 1ull, 1ull},
|
|
{"POR" , 6, 1, 939, "R/W", 0, 0, 1ull, 0ull},
|
|
{"S_BIST" , 7, 1, 939, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SD_MODE" , 8, 2, 939, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CDIV_BYP" , 10, 1, 939, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_C_SEL" , 11, 2, 939, "R/W", 0, 0, 2ull, 0ull},
|
|
{"P_COM_ON" , 13, 1, 939, "R/W", 0, 0, 1ull, 1ull},
|
|
{"P_RTYPE" , 14, 2, 939, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 939, "RAZ", 1, 1, 0, 0},
|
|
{"HCLK_RST" , 17, 1, 939, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DIVIDE2" , 18, 2, 939, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_20_63" , 20, 44, 939, "RAZ", 1, 1, 0, 0},
|
|
{"L2C_EMOD" , 0, 2, 940, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INV_A2" , 2, 1, 940, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_TEST" , 3, 1, 940, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_STT" , 4, 1, 940, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_0PAG" , 5, 1, 940, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 940, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 941, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 941, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 942, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 942, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 943, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 943, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 944, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 944, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 945, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 945, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 946, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 946, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 947, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 947, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 948, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 948, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 949, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 949, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 950, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 950, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 951, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 951, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 952, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 952, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 953, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 953, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 954, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 954, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 955, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 955, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 956, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 956, "RAZ", 1, 1, 0, 0},
|
|
{"BURST" , 0, 4, 957, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHANNEL" , 4, 5, 957, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COUNT" , 9, 11, 957, "R/W", 0, 0, 0ull, 0ull},
|
|
{"F_ADDR" , 20, 18, 957, "R/W", 0, 0, 0ull, 0ull},
|
|
{"REQ" , 38, 1, 957, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DONE" , 39, 1, 957, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 957, "RAZ", 1, 1, 0, 0},
|
|
{"PR_PO_E" , 0, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PR_PU_F" , 1, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NR_PO_E" , 2, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NR_PU_F" , 3, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LR_PO_E" , 4, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LR_PU_F" , 5, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PT_PO_E" , 6, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PT_PU_F" , 7, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NT_PO_E" , 8, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NT_PU_F" , 9, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LT_PO_E" , 10, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LT_PU_F" , 11, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DCRED_E" , 12, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DCRED_F" , 13, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2C_S_E" , 14, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2C_A_F" , 15, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2_FI_E" , 16, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2_FI_F" , 17, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_E" , 18, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_F" , 19, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_F" , 20, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_E" , 21, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_F" , 22, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_E" , 23, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UOD_PE" , 24, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UOD_PF" , 25, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_31" , 26, 6, 958, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LTL_F_PE" , 32, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LTL_F_PF" , 33, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_RPE" , 34, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_RPF" , 35, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_DPE" , 36, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_DPF" , 37, 1, 958, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 958, "RAZ", 1, 1, 0, 0},
|
|
{"PR_PO_E" , 0, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PR_PU_F" , 1, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NR_PO_E" , 2, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NR_PU_F" , 3, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LR_PO_E" , 4, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LR_PU_F" , 5, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PT_PO_E" , 6, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PT_PU_F" , 7, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NT_PO_E" , 8, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NT_PU_F" , 9, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LT_PO_E" , 10, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LT_PU_F" , 11, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCRED_E" , 12, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCRED_F" , 13, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"L2C_S_E" , 14, 1, 959, "R/W1C", 1, 0, 0, 0ull},
|
|
{"L2C_A_F" , 15, 1, 959, "R/W1C", 1, 0, 0, 0ull},
|
|
{"LT_FI_E" , 16, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LT_FI_F" , 17, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_E" , 18, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_F" , 19, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_F" , 20, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_E" , 21, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_F" , 22, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_E" , 23, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UOD_PE" , 24, 1, 959, "R/W1C", 1, 0, 0, 0ull},
|
|
{"UOD_PF" , 25, 1, 959, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_26_31" , 26, 6, 959, "RAZ", 1, 0, 0, 0ull},
|
|
{"LTL_F_PE" , 32, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LTL_F_PF" , 33, 1, 959, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ND4O_RPE" , 34, 1, 959, "R/W1C", 1, 0, 0, 0ull},
|
|
{"ND4O_RPF" , 35, 1, 959, "R/W1C", 1, 0, 0, 0ull},
|
|
{"ND4O_DPE" , 36, 1, 959, "R/W1C", 1, 0, 0, 0ull},
|
|
{"ND4O_DPF" , 37, 1, 959, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 959, "RAZ", 1, 1, 0, 0},
|
|
{"ATE_RESET" , 0, 1, 960, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TDATA_IN" , 1, 8, 960, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TADDR_IN" , 9, 4, 960, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TDATA_SEL" , 13, 1, 960, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BIST_ENB" , 14, 1, 960, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VTEST_ENB" , 15, 1, 960, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LOOP_ENB" , 16, 1, 960, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TX_BS_EN" , 17, 1, 960, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TX_BS_ENH" , 18, 1, 960, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_22" , 19, 4, 960, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"HST_MODE" , 23, 1, 960, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DM_PULLD" , 24, 1, 960, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DP_PULLD" , 25, 1, 960, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TCLK" , 26, 1, 960, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBP_BIST" , 27, 1, 960, "R/W", 0, 0, 1ull, 1ull},
|
|
{"USBC_END" , 28, 1, 960, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_BMODE" , 29, 1, 960, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXPREEMPHASISTUNE" , 30, 1, 960, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SIDDQ" , 31, 1, 960, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TDATA_OUT" , 32, 4, 960, "RO", 1, 1, 0, 0},
|
|
{"BIST_ERR" , 36, 1, 960, "RO", 0, 0, 0ull, 0ull},
|
|
{"BIST_DONE" , 37, 1, 960, "RO", 0, 0, 0ull, 0ull},
|
|
{"HSBIST" , 38, 1, 960, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSBIST" , 39, 1, 960, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LSBIST" , 40, 1, 960, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRVVBUS" , 41, 1, 960, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PORTRESET" , 42, 1, 960, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OTGDISABLE" , 43, 1, 960, "R/W", 0, 0, 1ull, 1ull},
|
|
{"OTGTUNE" , 44, 3, 960, "R/W", 0, 0, 2ull, 2ull},
|
|
{"COMPDISTUNE" , 47, 3, 960, "R/W", 0, 0, 2ull, 2ull},
|
|
{"SQRXTUNE" , 50, 3, 960, "R/W", 0, 0, 3ull, 3ull},
|
|
{"TXHSXVTUNE" , 53, 2, 960, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFSLSTUNE" , 55, 4, 960, "R/W", 0, 0, 3ull, 3ull},
|
|
{"TXVREFTUNE" , 59, 4, 960, "R/W", 0, 0, 7ull, 7ull},
|
|
{"TXRISETUNE" , 63, 1, 960, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ZIP_CTL" , 0, 4, 961, "RO", 1, 0, 0, 0ull},
|
|
{"ZIP_CORE" , 4, 27, 961, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 961, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 33, 962, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 33, 13, 962, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 46, 3, 962, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 49, 9, 962, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_58_63" , 58, 6, 962, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 0, 1, 963, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FORCECLK" , 1, 1, 963, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 963, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DISABLED" , 0, 1, 964, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_7" , 1, 7, 964, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CTXSIZE" , 8, 12, 964, "RO", 0, 0, 1536ull, 1536ull},
|
|
{"ONFSIZE" , 20, 12, 964, "RO", 0, 0, 512ull, 512ull},
|
|
{"DEPTH" , 32, 16, 964, "RO", 0, 0, 31744ull, 31744ull},
|
|
{"RESERVED_48_63" , 48, 16, 964, "RAZ", 1, 0, 0, 0ull},
|
|
{"ASSERTS" , 0, 14, 965, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 965, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 0, 1, 966, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 966, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 0, 1, 967, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 967, "RAZ", 1, 0, 0, 0ull},
|
|
{NULL,0,0,0,0,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn50xx[] = {
|
|
/* name , ---------------type, bits, off, #field, fld of */
|
|
{"cvmx_asx#_gmii_rx_clk_set" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 2, 0},
|
|
{"cvmx_asx#_gmii_rx_dat_set" , CVMX_CSR_DB_TYPE_RSL, 64, 1, 2, 2},
|
|
{"cvmx_asx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 6, 4},
|
|
{"cvmx_asx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 3, 6, 10},
|
|
{"cvmx_asx#_mii_rx_dat_set" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 2, 16},
|
|
{"cvmx_asx#_prt_loop" , CVMX_CSR_DB_TYPE_RSL, 64, 5, 4, 18},
|
|
{"cvmx_asx#_rx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 2, 22},
|
|
{"cvmx_asx#_rx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 9, 2, 24},
|
|
{"cvmx_asx#_tx_clk_set#" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 2, 26},
|
|
{"cvmx_asx#_tx_comp_byp" , CVMX_CSR_DB_TYPE_RSL, 64, 13, 6, 28},
|
|
{"cvmx_asx#_tx_hi_water#" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 2, 34},
|
|
{"cvmx_asx#_tx_prt_en" , CVMX_CSR_DB_TYPE_RSL, 64, 17, 2, 36},
|
|
{"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 18, 2, 38},
|
|
{"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 19, 2, 40},
|
|
{"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 20, 2, 42},
|
|
{"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 21, 2, 44},
|
|
{"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 22, 19, 46},
|
|
{"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 27, 2, 65},
|
|
{"cvmx_ciu_int#_en4_0" , CVMX_CSR_DB_TYPE_NCB, 64, 32, 19, 67},
|
|
{"cvmx_ciu_int#_en4_1" , CVMX_CSR_DB_TYPE_NCB, 64, 34, 2, 86},
|
|
{"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 36, 19, 88},
|
|
{"cvmx_ciu_int#_sum4" , CVMX_CSR_DB_TYPE_NCB, 64, 41, 19, 107},
|
|
{"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 43, 2, 126},
|
|
{"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 44, 2, 128},
|
|
{"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 46, 2, 130},
|
|
{"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 48, 2, 132},
|
|
{"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 49, 2, 134},
|
|
{"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 50, 2, 136},
|
|
{"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 51, 1, 138},
|
|
{"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 53, 3, 139},
|
|
{"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 54, 2, 142},
|
|
{"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 55, 4, 144},
|
|
{"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 56, 2, 148},
|
|
{"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 57, 3, 150},
|
|
{"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 61, 7, 153},
|
|
{"cvmx_dbg_data" , CVMX_CSR_DB_TYPE_NCB, 64, 63, 6, 160},
|
|
{"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 64, 6, 166},
|
|
{"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 65, 7, 172},
|
|
{"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 66, 29, 179},
|
|
{"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 67, 29, 208},
|
|
{"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 68, 2, 237},
|
|
{"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 76, 2, 239},
|
|
{"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 84, 3, 241},
|
|
{"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 85, 3, 244},
|
|
{"cvmx_fpa_wart_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 86, 2, 247},
|
|
{"cvmx_fpa_wart_status" , CVMX_CSR_DB_TYPE_RSL, 64, 87, 2, 249},
|
|
{"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 88, 8, 251},
|
|
{"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 89, 2, 259},
|
|
{"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 90, 4, 261},
|
|
{"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 91, 2, 265},
|
|
{"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 92, 5, 267},
|
|
{"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 95, 1, 272},
|
|
{"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 98, 1, 273},
|
|
{"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 101, 1, 274},
|
|
{"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 104, 1, 275},
|
|
{"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 107, 1, 276},
|
|
{"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 110, 1, 277},
|
|
{"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 113, 2, 278},
|
|
{"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 116, 4, 280},
|
|
{"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 119, 2, 284},
|
|
{"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 122, 11, 286},
|
|
{"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 125, 11, 297},
|
|
{"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 128, 2, 308},
|
|
{"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 131, 21, 310},
|
|
{"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 134, 21, 331},
|
|
{"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 137, 2, 352},
|
|
{"cvmx_gmx#_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 140, 2, 354},
|
|
{"cvmx_gmx#_rx#_rx_inbnd" , CVMX_CSR_DB_TYPE_RSL, 64, 143, 4, 356},
|
|
{"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 146, 2, 360},
|
|
{"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 149, 2, 362},
|
|
{"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 152, 2, 364},
|
|
{"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 155, 2, 366},
|
|
{"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 158, 2, 368},
|
|
{"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 161, 2, 370},
|
|
{"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 164, 2, 372},
|
|
{"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 167, 2, 374},
|
|
{"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 170, 2, 376},
|
|
{"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 173, 2, 378},
|
|
{"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 176, 4, 380},
|
|
{"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 179, 2, 384},
|
|
{"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 182, 2, 386},
|
|
{"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 185, 2, 388},
|
|
{"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 188, 4, 390},
|
|
{"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 189, 2, 394},
|
|
{"cvmx_gmx#_rx_tx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 190, 4, 396},
|
|
{"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 191, 2, 400},
|
|
{"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 194, 3, 402},
|
|
{"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 195, 5, 405},
|
|
{"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 198, 2, 410},
|
|
{"cvmx_gmx#_tx#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 201, 2, 412},
|
|
{"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 204, 3, 414},
|
|
{"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 207, 2, 417},
|
|
{"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 210, 2, 419},
|
|
{"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 213, 2, 421},
|
|
{"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 216, 2, 423},
|
|
{"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 219, 2, 425},
|
|
{"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 222, 2, 427},
|
|
{"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 225, 2, 429},
|
|
{"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 228, 2, 431},
|
|
{"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 231, 2, 433},
|
|
{"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 234, 2, 435},
|
|
{"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 237, 2, 437},
|
|
{"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 240, 2, 439},
|
|
{"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 243, 2, 441},
|
|
{"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 246, 2, 443},
|
|
{"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 249, 2, 445},
|
|
{"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 252, 2, 447},
|
|
{"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 255, 2, 449},
|
|
{"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 258, 2, 451},
|
|
{"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 261, 2, 453},
|
|
{"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 264, 2, 455},
|
|
{"cvmx_gmx#_tx_clk_msk#" , CVMX_CSR_DB_TYPE_RSL, 64, 265, 2, 457},
|
|
{"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 267, 2, 459},
|
|
{"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 268, 2, 461},
|
|
{"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 269, 3, 463},
|
|
{"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 270, 10, 466},
|
|
{"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 271, 10, 476},
|
|
{"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 272, 2, 486},
|
|
{"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 273, 2, 488},
|
|
{"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 274, 6, 490},
|
|
{"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 275, 2, 496},
|
|
{"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 276, 2, 498},
|
|
{"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 277, 2, 500},
|
|
{"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 278, 7, 502},
|
|
{"cvmx_gpio_boot_ena" , CVMX_CSR_DB_TYPE_NCB, 64, 294, 3, 509},
|
|
{"cvmx_gpio_dbg_ena" , CVMX_CSR_DB_TYPE_NCB, 64, 295, 2, 512},
|
|
{"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 296, 2, 514},
|
|
{"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 297, 2, 516},
|
|
{"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 298, 2, 518},
|
|
{"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 299, 2, 520},
|
|
{"cvmx_gpio_xbit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 300, 6, 522},
|
|
{"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 308, 19, 528},
|
|
{"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 309, 6, 547},
|
|
{"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 310, 3, 553},
|
|
{"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 311, 5, 556},
|
|
{"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 312, 5, 561},
|
|
{"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 313, 1, 566},
|
|
{"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 314, 1, 567},
|
|
{"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 315, 7, 568},
|
|
{"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 316, 7, 575},
|
|
{"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 317, 5, 582},
|
|
{"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 318, 5, 587},
|
|
{"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 319, 1, 592},
|
|
{"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 320, 1, 593},
|
|
{"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 321, 2, 594},
|
|
{"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 322, 2, 596},
|
|
{"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 323, 2, 598},
|
|
{"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 324, 2, 600},
|
|
{"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 325, 17, 602},
|
|
{"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 326, 2, 619},
|
|
{"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 327, 1, 621},
|
|
{"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 328, 15, 622},
|
|
{"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 329, 11, 637},
|
|
{"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 330, 11, 648},
|
|
{"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 331, 2, 659},
|
|
{"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 332, 2, 661},
|
|
{"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 333, 2, 663},
|
|
{"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 334, 3, 665},
|
|
{"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 339, 2, 668},
|
|
{"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 344, 6, 670},
|
|
{"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 345, 5, 676},
|
|
{"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 346, 6, 681},
|
|
{"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 347, 7, 687},
|
|
{"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 348, 2, 694},
|
|
{"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 356, 2, 696},
|
|
{"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 357, 3, 698},
|
|
{"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 358, 5, 701},
|
|
{"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 366, 3, 706},
|
|
{"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 367, 2, 709},
|
|
{"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 368, 2, 711},
|
|
{"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 369, 2, 713},
|
|
{"cvmx_l2c_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 370, 8, 715},
|
|
{"cvmx_l2c_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 371, 5, 723},
|
|
{"cvmx_l2c_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 372, 8, 728},
|
|
{"cvmx_l2c_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 373, 12, 736},
|
|
{"cvmx_l2c_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 374, 9, 748},
|
|
{"cvmx_l2c_dut" , CVMX_CSR_DB_TYPE_RSL, 64, 375, 5, 757},
|
|
{"cvmx_l2c_lckbase" , CVMX_CSR_DB_TYPE_RSL, 64, 376, 4, 762},
|
|
{"cvmx_l2c_lckoff" , CVMX_CSR_DB_TYPE_RSL, 64, 377, 2, 766},
|
|
{"cvmx_l2c_lfb0" , CVMX_CSR_DB_TYPE_RSL, 64, 378, 16, 768},
|
|
{"cvmx_l2c_lfb1" , CVMX_CSR_DB_TYPE_RSL, 64, 379, 19, 784},
|
|
{"cvmx_l2c_lfb2" , CVMX_CSR_DB_TYPE_RSL, 64, 380, 3, 803},
|
|
{"cvmx_l2c_lfb3" , CVMX_CSR_DB_TYPE_RSL, 64, 381, 4, 806},
|
|
{"cvmx_l2c_pfc#" , CVMX_CSR_DB_TYPE_RSL, 64, 382, 2, 810},
|
|
{"cvmx_l2c_pfctl" , CVMX_CSR_DB_TYPE_RSL, 64, 386, 17, 812},
|
|
{"cvmx_l2c_spar0" , CVMX_CSR_DB_TYPE_RSL, 64, 387, 3, 829},
|
|
{"cvmx_l2c_spar4" , CVMX_CSR_DB_TYPE_RSL, 64, 388, 2, 832},
|
|
{"cvmx_l2d_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 389, 3, 834},
|
|
{"cvmx_l2d_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 390, 2, 837},
|
|
{"cvmx_l2d_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 391, 2, 839},
|
|
{"cvmx_l2d_bst3" , CVMX_CSR_DB_TYPE_RSL, 64, 392, 2, 841},
|
|
{"cvmx_l2d_err" , CVMX_CSR_DB_TYPE_RSL, 64, 393, 7, 843},
|
|
{"cvmx_l2d_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 394, 5, 850},
|
|
{"cvmx_l2d_fsyn0" , CVMX_CSR_DB_TYPE_RSL, 64, 395, 3, 855},
|
|
{"cvmx_l2d_fsyn1" , CVMX_CSR_DB_TYPE_RSL, 64, 396, 3, 858},
|
|
{"cvmx_l2d_fus0" , CVMX_CSR_DB_TYPE_RSL, 64, 397, 2, 861},
|
|
{"cvmx_l2d_fus1" , CVMX_CSR_DB_TYPE_RSL, 64, 398, 2, 863},
|
|
{"cvmx_l2d_fus2" , CVMX_CSR_DB_TYPE_RSL, 64, 399, 2, 865},
|
|
{"cvmx_l2d_fus3" , CVMX_CSR_DB_TYPE_RSL, 64, 400, 6, 867},
|
|
{"cvmx_l2t_err" , CVMX_CSR_DB_TYPE_RSL, 64, 401, 14, 873},
|
|
{"cvmx_lmc#_bist_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 402, 2, 887},
|
|
{"cvmx_lmc#_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 403, 6, 889},
|
|
{"cvmx_lmc#_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 404, 7, 895},
|
|
{"cvmx_lmc#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 405, 20, 902},
|
|
{"cvmx_lmc#_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 406, 5, 922},
|
|
{"cvmx_lmc#_dclk_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 407, 2, 927},
|
|
{"cvmx_lmc#_dclk_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 408, 2, 929},
|
|
{"cvmx_lmc#_ddr2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 409, 18, 931},
|
|
{"cvmx_lmc#_delay_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 410, 6, 949},
|
|
{"cvmx_lmc#_dual_memcfg" , CVMX_CSR_DB_TYPE_RSL, 64, 411, 5, 955},
|
|
{"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 412, 5, 960},
|
|
{"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 413, 6, 965},
|
|
{"cvmx_lmc#_ifb_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 414, 2, 971},
|
|
{"cvmx_lmc#_ifb_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 415, 2, 973},
|
|
{"cvmx_lmc#_mem_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 416, 14, 975},
|
|
{"cvmx_lmc#_mem_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 417, 10, 989},
|
|
{"cvmx_lmc#_ops_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 418, 2, 999},
|
|
{"cvmx_lmc#_ops_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 419, 2, 1001},
|
|
{"cvmx_lmc#_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 420, 13, 1003},
|
|
{"cvmx_lmc#_pll_status" , CVMX_CSR_DB_TYPE_RSL, 64, 421, 6, 1016},
|
|
{"cvmx_lmc#_rodt_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 422, 6, 1022},
|
|
{"cvmx_lmc#_rodt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 423, 9, 1028},
|
|
{"cvmx_lmc#_wodt_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 424, 9, 1037},
|
|
{"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 425, 7, 1046},
|
|
{"cvmx_mio_boot_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 426, 3, 1053},
|
|
{"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 427, 3, 1056},
|
|
{"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 428, 3, 1059},
|
|
{"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 429, 3, 1062},
|
|
{"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 430, 5, 1065},
|
|
{"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 432, 1, 1070},
|
|
{"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 433, 12, 1071},
|
|
{"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 441, 13, 1083},
|
|
{"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 449, 4, 1096},
|
|
{"cvmx_mio_fus_bnk_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 450, 1, 1100},
|
|
{"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 454, 2, 1101},
|
|
{"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 455, 2, 1103},
|
|
{"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 456, 13, 1105},
|
|
{"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 457, 8, 1118},
|
|
{"cvmx_mio_fus_ema" , CVMX_CSR_DB_TYPE_RSL, 64, 458, 4, 1126},
|
|
{"cvmx_mio_fus_pdf" , CVMX_CSR_DB_TYPE_RSL, 64, 459, 1, 1130},
|
|
{"cvmx_mio_fus_pll" , CVMX_CSR_DB_TYPE_RSL, 64, 460, 3, 1131},
|
|
{"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 461, 2, 1134},
|
|
{"cvmx_mio_fus_prog_times" , CVMX_CSR_DB_TYPE_RSL, 64, 462, 6, 1136},
|
|
{"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 463, 8, 1142},
|
|
{"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 464, 4, 1150},
|
|
{"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 465, 2, 1154},
|
|
{"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 466, 2, 1156},
|
|
{"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 467, 13, 1158},
|
|
{"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 468, 12, 1171},
|
|
{"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 469, 3, 1183},
|
|
{"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 470, 3, 1186},
|
|
{"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 471, 2, 1189},
|
|
{"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 473, 2, 1191},
|
|
{"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 475, 2, 1193},
|
|
{"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 477, 7, 1195},
|
|
{"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 479, 2, 1202},
|
|
{"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 481, 7, 1204},
|
|
{"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 483, 4, 1211},
|
|
{"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 485, 8, 1215},
|
|
{"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 487, 9, 1223},
|
|
{"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 489, 7, 1232},
|
|
{"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 491, 9, 1239},
|
|
{"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 493, 2, 1248},
|
|
{"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 495, 2, 1250},
|
|
{"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 497, 4, 1252},
|
|
{"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 499, 2, 1256},
|
|
{"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 501, 2, 1258},
|
|
{"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 503, 2, 1260},
|
|
{"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 505, 4, 1262},
|
|
{"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 507, 2, 1266},
|
|
{"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 509, 2, 1268},
|
|
{"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 511, 2, 1270},
|
|
{"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 513, 2, 1272},
|
|
{"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 515, 2, 1274},
|
|
{"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 517, 2, 1276},
|
|
{"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 519, 6, 1278},
|
|
{"cvmx_mpi_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 521, 14, 1284},
|
|
{"cvmx_mpi_dat#" , CVMX_CSR_DB_TYPE_NCB, 64, 522, 2, 1298},
|
|
{"cvmx_mpi_sts" , CVMX_CSR_DB_TYPE_NCB, 64, 531, 4, 1300},
|
|
{"cvmx_mpi_tx" , CVMX_CSR_DB_TYPE_NCB, 64, 532, 6, 1304},
|
|
{"cvmx_npi_base_addr_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 533, 2, 1310},
|
|
{"cvmx_npi_base_addr_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 535, 2, 1312},
|
|
{"cvmx_npi_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 537, 20, 1314},
|
|
{"cvmx_npi_buff_size_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 538, 3, 1334},
|
|
{"cvmx_npi_comp_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 540, 3, 1337},
|
|
{"cvmx_npi_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 541, 18, 1340},
|
|
{"cvmx_npi_dbg_select" , CVMX_CSR_DB_TYPE_NCB, 64, 542, 2, 1358},
|
|
{"cvmx_npi_dma_control" , CVMX_CSR_DB_TYPE_NCB, 64, 543, 13, 1360},
|
|
{"cvmx_npi_dma_highp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 544, 3, 1373},
|
|
{"cvmx_npi_dma_highp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 545, 3, 1376},
|
|
{"cvmx_npi_dma_lowp_counts" , CVMX_CSR_DB_TYPE_NCB, 64, 546, 3, 1379},
|
|
{"cvmx_npi_dma_lowp_naddr" , CVMX_CSR_DB_TYPE_NCB, 64, 547, 3, 1382},
|
|
{"cvmx_npi_highp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 548, 2, 1385},
|
|
{"cvmx_npi_highp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 549, 2, 1387},
|
|
{"cvmx_npi_input_control" , CVMX_CSR_DB_TYPE_NCB, 64, 550, 10, 1389},
|
|
{"cvmx_npi_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 551, 54, 1399},
|
|
{"cvmx_npi_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 552, 54, 1453},
|
|
{"cvmx_npi_lowp_dbell" , CVMX_CSR_DB_TYPE_NCB, 64, 553, 2, 1507},
|
|
{"cvmx_npi_lowp_ibuff_saddr" , CVMX_CSR_DB_TYPE_NCB, 64, 554, 2, 1509},
|
|
{"cvmx_npi_mem_access_subid#" , CVMX_CSR_DB_TYPE_NCB, 64, 555, 10, 1511},
|
|
{"cvmx_npi_msi_rcv" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 559, 1, 1521},
|
|
{"cvmx_npi_num_desc_output#" , CVMX_CSR_DB_TYPE_NCB, 64, 560, 2, 1522},
|
|
{"cvmx_npi_output_control" , CVMX_CSR_DB_TYPE_NCB, 64, 562, 25, 1524},
|
|
{"cvmx_npi_p#_dbpair_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 563, 3, 1549},
|
|
{"cvmx_npi_p#_instr_addr" , CVMX_CSR_DB_TYPE_NCB, 64, 565, 2, 1552},
|
|
{"cvmx_npi_p#_instr_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 567, 3, 1554},
|
|
{"cvmx_npi_p#_pair_cnts" , CVMX_CSR_DB_TYPE_NCB, 64, 569, 3, 1557},
|
|
{"cvmx_npi_pci_burst_size" , CVMX_CSR_DB_TYPE_NCB, 64, 571, 3, 1560},
|
|
{"cvmx_npi_pci_int_arb_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 572, 7, 1563},
|
|
{"cvmx_npi_pci_read_cmd" , CVMX_CSR_DB_TYPE_NCB, 64, 573, 2, 1570},
|
|
{"cvmx_npi_port32_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 574, 13, 1572},
|
|
{"cvmx_npi_port33_instr_hdr" , CVMX_CSR_DB_TYPE_NCB, 64, 575, 13, 1585},
|
|
{"cvmx_npi_port_bp_control" , CVMX_CSR_DB_TYPE_NCB, 64, 576, 3, 1598},
|
|
{"cvmx_npi_rsl_int_blocks" , CVMX_CSR_DB_TYPE_NCB, 64, 577, 29, 1601},
|
|
{"cvmx_npi_size_input#" , CVMX_CSR_DB_TYPE_NCB, 64, 578, 2, 1630},
|
|
{"cvmx_npi_win_read_to" , CVMX_CSR_DB_TYPE_NCB, 64, 580, 2, 1632},
|
|
{"cvmx_pci_bar1_index#" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 581, 5, 1634},
|
|
{"cvmx_pci_bist_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 613, 11, 1639},
|
|
{"cvmx_pci_cfg00" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 614, 2, 1650},
|
|
{"cvmx_pci_cfg01" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 615, 24, 1652},
|
|
{"cvmx_pci_cfg02" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 616, 2, 1676},
|
|
{"cvmx_pci_cfg03" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 617, 7, 1678},
|
|
{"cvmx_pci_cfg04" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 618, 5, 1685},
|
|
{"cvmx_pci_cfg05" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 619, 1, 1690},
|
|
{"cvmx_pci_cfg06" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 620, 5, 1691},
|
|
{"cvmx_pci_cfg07" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 621, 1, 1696},
|
|
{"cvmx_pci_cfg08" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 622, 4, 1697},
|
|
{"cvmx_pci_cfg09" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 623, 2, 1701},
|
|
{"cvmx_pci_cfg10" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 624, 1, 1703},
|
|
{"cvmx_pci_cfg11" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 625, 2, 1704},
|
|
{"cvmx_pci_cfg12" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 626, 4, 1706},
|
|
{"cvmx_pci_cfg13" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 627, 2, 1710},
|
|
{"cvmx_pci_cfg15" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 628, 4, 1712},
|
|
{"cvmx_pci_cfg16" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 629, 16, 1716},
|
|
{"cvmx_pci_cfg17" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 630, 1, 1732},
|
|
{"cvmx_pci_cfg18" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 631, 1, 1733},
|
|
{"cvmx_pci_cfg19" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 632, 18, 1734},
|
|
{"cvmx_pci_cfg20" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 633, 1, 1752},
|
|
{"cvmx_pci_cfg21" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 634, 1, 1753},
|
|
{"cvmx_pci_cfg22" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 635, 7, 1754},
|
|
{"cvmx_pci_cfg56" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 636, 7, 1761},
|
|
{"cvmx_pci_cfg57" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 637, 13, 1768},
|
|
{"cvmx_pci_cfg58" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 638, 10, 1781},
|
|
{"cvmx_pci_cfg59" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 639, 10, 1791},
|
|
{"cvmx_pci_cfg60" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 640, 7, 1801},
|
|
{"cvmx_pci_cfg61" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 641, 2, 1808},
|
|
{"cvmx_pci_cfg62" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 642, 1, 1810},
|
|
{"cvmx_pci_cfg63" , CVMX_CSR_DB_TYPE_PCICONFIG, 32, 643, 2, 1811},
|
|
{"cvmx_pci_cnt_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 644, 6, 1813},
|
|
{"cvmx_pci_ctl_status_2" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 645, 22, 1819},
|
|
{"cvmx_pci_dbell#" , CVMX_CSR_DB_TYPE_PCI, 32, 646, 2, 1841},
|
|
{"cvmx_pci_dma_cnt#" , CVMX_CSR_DB_TYPE_PCI, 32, 648, 1, 1843},
|
|
{"cvmx_pci_dma_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 650, 1, 1844},
|
|
{"cvmx_pci_dma_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 652, 1, 1845},
|
|
{"cvmx_pci_instr_count#" , CVMX_CSR_DB_TYPE_PCI, 32, 654, 1, 1846},
|
|
{"cvmx_pci_int_enb" , CVMX_CSR_DB_TYPE_PCI, 64, 656, 33, 1847},
|
|
{"cvmx_pci_int_enb2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 657, 33, 1880},
|
|
{"cvmx_pci_int_sum" , CVMX_CSR_DB_TYPE_PCI, 64, 658, 33, 1913},
|
|
{"cvmx_pci_int_sum2" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 659, 33, 1946},
|
|
{"cvmx_pci_msi_rcv" , CVMX_CSR_DB_TYPE_PCI, 32, 660, 2, 1979},
|
|
{"cvmx_pci_pkt_credits#" , CVMX_CSR_DB_TYPE_PCI, 32, 661, 2, 1981},
|
|
{"cvmx_pci_pkts_sent#" , CVMX_CSR_DB_TYPE_PCI, 32, 663, 1, 1983},
|
|
{"cvmx_pci_pkts_sent_int_lev#" , CVMX_CSR_DB_TYPE_PCI, 32, 665, 1, 1984},
|
|
{"cvmx_pci_pkts_sent_time#" , CVMX_CSR_DB_TYPE_PCI, 32, 667, 1, 1985},
|
|
{"cvmx_pci_read_cmd_6" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 669, 3, 1986},
|
|
{"cvmx_pci_read_cmd_c" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 670, 3, 1989},
|
|
{"cvmx_pci_read_cmd_e" , CVMX_CSR_DB_TYPE_PCI_NCB, 32, 671, 3, 1992},
|
|
{"cvmx_pci_read_timeout" , CVMX_CSR_DB_TYPE_NCB, 64, 672, 3, 1995},
|
|
{"cvmx_pci_scm_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 673, 2, 1998},
|
|
{"cvmx_pci_tsr_reg" , CVMX_CSR_DB_TYPE_PCI_NCB, 64, 674, 2, 2000},
|
|
{"cvmx_pci_win_rd_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 675, 4, 2002},
|
|
{"cvmx_pci_win_rd_data" , CVMX_CSR_DB_TYPE_PCI, 64, 676, 1, 2006},
|
|
{"cvmx_pci_win_wr_addr" , CVMX_CSR_DB_TYPE_PCI, 64, 677, 4, 2007},
|
|
{"cvmx_pci_win_wr_data" , CVMX_CSR_DB_TYPE_PCI, 64, 678, 1, 2011},
|
|
{"cvmx_pci_win_wr_mask" , CVMX_CSR_DB_TYPE_PCI, 64, 679, 2, 2012},
|
|
{"cvmx_pcm#_dma_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 680, 12, 2014},
|
|
{"cvmx_pcm#_int_ena" , CVMX_CSR_DB_TYPE_NCB, 64, 684, 9, 2026},
|
|
{"cvmx_pcm#_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 688, 9, 2035},
|
|
{"cvmx_pcm#_rxaddr" , CVMX_CSR_DB_TYPE_NCB, 64, 692, 2, 2044},
|
|
{"cvmx_pcm#_rxcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 696, 2, 2046},
|
|
{"cvmx_pcm#_rxmsk0" , CVMX_CSR_DB_TYPE_NCB, 64, 700, 1, 2048},
|
|
{"cvmx_pcm#_rxmsk1" , CVMX_CSR_DB_TYPE_NCB, 64, 704, 1, 2049},
|
|
{"cvmx_pcm#_rxmsk2" , CVMX_CSR_DB_TYPE_NCB, 64, 708, 1, 2050},
|
|
{"cvmx_pcm#_rxmsk3" , CVMX_CSR_DB_TYPE_NCB, 64, 712, 1, 2051},
|
|
{"cvmx_pcm#_rxmsk4" , CVMX_CSR_DB_TYPE_NCB, 64, 716, 1, 2052},
|
|
{"cvmx_pcm#_rxmsk5" , CVMX_CSR_DB_TYPE_NCB, 64, 720, 1, 2053},
|
|
{"cvmx_pcm#_rxmsk6" , CVMX_CSR_DB_TYPE_NCB, 64, 724, 1, 2054},
|
|
{"cvmx_pcm#_rxmsk7" , CVMX_CSR_DB_TYPE_NCB, 64, 728, 1, 2055},
|
|
{"cvmx_pcm#_rxstart" , CVMX_CSR_DB_TYPE_NCB, 64, 732, 3, 2056},
|
|
{"cvmx_pcm#_tdm_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 736, 6, 2059},
|
|
{"cvmx_pcm#_tdm_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 740, 1, 2065},
|
|
{"cvmx_pcm#_txaddr" , CVMX_CSR_DB_TYPE_NCB, 64, 744, 3, 2066},
|
|
{"cvmx_pcm#_txcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 748, 2, 2069},
|
|
{"cvmx_pcm#_txmsk0" , CVMX_CSR_DB_TYPE_NCB, 64, 752, 1, 2071},
|
|
{"cvmx_pcm#_txmsk1" , CVMX_CSR_DB_TYPE_NCB, 64, 756, 1, 2072},
|
|
{"cvmx_pcm#_txmsk2" , CVMX_CSR_DB_TYPE_NCB, 64, 760, 1, 2073},
|
|
{"cvmx_pcm#_txmsk3" , CVMX_CSR_DB_TYPE_NCB, 64, 764, 1, 2074},
|
|
{"cvmx_pcm#_txmsk4" , CVMX_CSR_DB_TYPE_NCB, 64, 768, 1, 2075},
|
|
{"cvmx_pcm#_txmsk5" , CVMX_CSR_DB_TYPE_NCB, 64, 772, 1, 2076},
|
|
{"cvmx_pcm#_txmsk6" , CVMX_CSR_DB_TYPE_NCB, 64, 776, 1, 2077},
|
|
{"cvmx_pcm#_txmsk7" , CVMX_CSR_DB_TYPE_NCB, 64, 780, 1, 2078},
|
|
{"cvmx_pcm#_txstart" , CVMX_CSR_DB_TYPE_NCB, 64, 784, 3, 2079},
|
|
{"cvmx_pcm_clk#_cfg" , CVMX_CSR_DB_TYPE_NCB, 64, 788, 12, 2082},
|
|
{"cvmx_pcm_clk#_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 790, 1, 2094},
|
|
{"cvmx_pcm_clk#_gen" , CVMX_CSR_DB_TYPE_NCB, 64, 792, 3, 2095},
|
|
{"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 794, 2, 2098},
|
|
{"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 795, 4, 2100},
|
|
{"cvmx_pip_frm_len_chk#" , CVMX_CSR_DB_TYPE_RSL, 64, 799, 3, 2104},
|
|
{"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 801, 8, 2107},
|
|
{"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 802, 16, 2115},
|
|
{"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 803, 13, 2131},
|
|
{"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 804, 13, 2144},
|
|
{"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 805, 2, 2157},
|
|
{"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 806, 27, 2159},
|
|
{"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 811, 25, 2186},
|
|
{"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 816, 2, 2211},
|
|
{"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 880, 2, 2213},
|
|
{"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 888, 9, 2215},
|
|
{"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 896, 2, 2224},
|
|
{"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 897, 2, 2226},
|
|
{"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 898, 2, 2228},
|
|
{"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 903, 2, 2230},
|
|
{"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 908, 2, 2232},
|
|
{"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 913, 2, 2234},
|
|
{"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 918, 2, 2236},
|
|
{"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 923, 2, 2238},
|
|
{"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 928, 2, 2240},
|
|
{"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 933, 2, 2242},
|
|
{"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 938, 2, 2244},
|
|
{"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 943, 2, 2246},
|
|
{"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 948, 2, 2248},
|
|
{"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 949, 2, 2250},
|
|
{"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 954, 2, 2252},
|
|
{"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 959, 2, 2254},
|
|
{"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 964, 2, 2256},
|
|
{"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1028, 2, 2258},
|
|
{"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 1029, 3, 2260},
|
|
{"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 1030, 3, 2263},
|
|
{"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 1031, 2, 2266},
|
|
{"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 1032, 2, 2268},
|
|
{"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1033, 4, 2270},
|
|
{"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 1034, 5, 2274},
|
|
{"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 1035, 4, 2279},
|
|
{"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 1036, 8, 2283},
|
|
{"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 1037, 4, 2291},
|
|
{"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 1038, 5, 2295},
|
|
{"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 1039, 5, 2300},
|
|
{"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 1040, 1, 2305},
|
|
{"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 1041, 18, 2306},
|
|
{"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 1042, 4, 2324},
|
|
{"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 1043, 2, 2328},
|
|
{"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 1044, 6, 2330},
|
|
{"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 1045, 7, 2336},
|
|
{"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 1046, 4, 2343},
|
|
{"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 1047, 9, 2347},
|
|
{"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 1048, 5, 2356},
|
|
{"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1049, 15, 2361},
|
|
{"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 1050, 4, 2376},
|
|
{"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1051, 1, 2380},
|
|
{"cvmx_pko_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 1052, 1, 2381},
|
|
{"cvmx_pko_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 1053, 1, 2382},
|
|
{"cvmx_pko_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 1054, 1, 2383},
|
|
{"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 1055, 4, 2384},
|
|
{"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 1056, 5, 2388},
|
|
{"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 1057, 3, 2393},
|
|
{"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1058, 4, 2396},
|
|
{"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 1059, 2, 2400},
|
|
{"cvmx_pko_reg_queue_ptrs1" , CVMX_CSR_DB_TYPE_RSL, 64, 1060, 3, 2402},
|
|
{"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 1061, 3, 2405},
|
|
{"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 1062, 12, 2408},
|
|
{"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1063, 2, 2420},
|
|
{"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 1064, 13, 2422},
|
|
{"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1065, 3, 2435},
|
|
{"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 1066, 2, 2438},
|
|
{"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1074, 2, 2440},
|
|
{"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1075, 2, 2442},
|
|
{"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 1076, 2, 2444},
|
|
{"cvmx_pow_pf_rst_msk" , CVMX_CSR_DB_TYPE_NCB, 64, 1077, 2, 2446},
|
|
{"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 1078, 10, 2448},
|
|
{"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 1080, 5, 2458},
|
|
{"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 1088, 10, 2463},
|
|
{"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1096, 2, 2473},
|
|
{"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1097, 2, 2475},
|
|
{"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 1098, 2, 2477},
|
|
{"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 1106, 3, 2479},
|
|
{"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 1107, 6, 2482},
|
|
{"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1123, 5, 2488},
|
|
{"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 1124, 7, 2493},
|
|
{"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 1140, 2, 2500},
|
|
{"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1156, 3, 2502},
|
|
{"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1157, 7, 2505},
|
|
{"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 1158, 10, 2512},
|
|
{"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1159, 6, 2522},
|
|
{"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1160, 2, 2528},
|
|
{"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1161, 4, 2530},
|
|
{"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1162, 4, 2534},
|
|
{"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1163, 6, 2538},
|
|
{"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 1164, 3, 2544},
|
|
{"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 1165, 5, 2547},
|
|
{"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 1166, 4, 2552},
|
|
{"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 1167, 6, 2556},
|
|
{"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1168, 4, 2562},
|
|
{"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 1169, 2, 2566},
|
|
{"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 1170, 4, 2568},
|
|
{"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1171, 2, 2572},
|
|
{"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 1172, 3, 2574},
|
|
{"cvmx_usbc#_daint" , CVMX_CSR_DB_TYPE_NCB, 32, 1173, 2, 2577},
|
|
{"cvmx_usbc#_daintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1174, 2, 2579},
|
|
{"cvmx_usbc#_dcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1175, 8, 2581},
|
|
{"cvmx_usbc#_dctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1176, 11, 2589},
|
|
{"cvmx_usbc#_diepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 1177, 15, 2600},
|
|
{"cvmx_usbc#_diepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1182, 8, 2615},
|
|
{"cvmx_usbc#_diepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1187, 8, 2623},
|
|
{"cvmx_usbc#_dieptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1188, 4, 2631},
|
|
{"cvmx_usbc#_doepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 1193, 15, 2635},
|
|
{"cvmx_usbc#_doepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1198, 6, 2650},
|
|
{"cvmx_usbc#_doepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1203, 6, 2656},
|
|
{"cvmx_usbc#_doeptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1204, 4, 2662},
|
|
{"cvmx_usbc#_dptxfsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1209, 2, 2666},
|
|
{"cvmx_usbc#_dsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1213, 6, 2668},
|
|
{"cvmx_usbc#_dtknqr1" , CVMX_CSR_DB_TYPE_NCB, 32, 1214, 4, 2674},
|
|
{"cvmx_usbc#_dtknqr2" , CVMX_CSR_DB_TYPE_NCB, 32, 1215, 1, 2678},
|
|
{"cvmx_usbc#_dtknqr3" , CVMX_CSR_DB_TYPE_NCB, 32, 1216, 1, 2679},
|
|
{"cvmx_usbc#_dtknqr4" , CVMX_CSR_DB_TYPE_NCB, 32, 1217, 1, 2680},
|
|
{"cvmx_usbc#_gahbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1218, 7, 2681},
|
|
{"cvmx_usbc#_ghwcfg1" , CVMX_CSR_DB_TYPE_NCB, 32, 1219, 1, 2688},
|
|
{"cvmx_usbc#_ghwcfg2" , CVMX_CSR_DB_TYPE_NCB, 32, 1220, 14, 2689},
|
|
{"cvmx_usbc#_ghwcfg3" , CVMX_CSR_DB_TYPE_NCB, 32, 1221, 10, 2703},
|
|
{"cvmx_usbc#_ghwcfg4" , CVMX_CSR_DB_TYPE_NCB, 32, 1222, 14, 2713},
|
|
{"cvmx_usbc#_gintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1223, 32, 2727},
|
|
{"cvmx_usbc#_gintsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1224, 32, 2759},
|
|
{"cvmx_usbc#_gnptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1225, 2, 2791},
|
|
{"cvmx_usbc#_gnptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1226, 4, 2793},
|
|
{"cvmx_usbc#_gotgctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1227, 13, 2797},
|
|
{"cvmx_usbc#_gotgint" , CVMX_CSR_DB_TYPE_NCB, 32, 1228, 10, 2810},
|
|
{"cvmx_usbc#_grstctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1229, 10, 2820},
|
|
{"cvmx_usbc#_grxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1230, 2, 2830},
|
|
{"cvmx_usbc#_grxstspd" , CVMX_CSR_DB_TYPE_NCB, 32, 1231, 6, 2832},
|
|
{"cvmx_usbc#_grxstsph" , CVMX_CSR_DB_TYPE_NCB, 32, 1232, 5, 2838},
|
|
{"cvmx_usbc#_grxstsrd" , CVMX_CSR_DB_TYPE_NCB, 32, 1233, 6, 2843},
|
|
{"cvmx_usbc#_grxstsrh" , CVMX_CSR_DB_TYPE_NCB, 32, 1234, 5, 2849},
|
|
{"cvmx_usbc#_gsnpsid" , CVMX_CSR_DB_TYPE_NCB, 32, 1235, 1, 2854},
|
|
{"cvmx_usbc#_gusbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1236, 13, 2855},
|
|
{"cvmx_usbc#_haint" , CVMX_CSR_DB_TYPE_NCB, 32, 1237, 2, 2868},
|
|
{"cvmx_usbc#_haintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1238, 2, 2870},
|
|
{"cvmx_usbc#_hcchar#" , CVMX_CSR_DB_TYPE_NCB, 32, 1239, 11, 2872},
|
|
{"cvmx_usbc#_hcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1247, 3, 2883},
|
|
{"cvmx_usbc#_hcint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1248, 12, 2886},
|
|
{"cvmx_usbc#_hcintmsk#" , CVMX_CSR_DB_TYPE_NCB, 32, 1256, 12, 2898},
|
|
{"cvmx_usbc#_hcsplt#" , CVMX_CSR_DB_TYPE_NCB, 32, 1264, 6, 2910},
|
|
{"cvmx_usbc#_hctsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1272, 4, 2916},
|
|
{"cvmx_usbc#_hfir" , CVMX_CSR_DB_TYPE_NCB, 32, 1280, 2, 2920},
|
|
{"cvmx_usbc#_hfnum" , CVMX_CSR_DB_TYPE_NCB, 32, 1281, 2, 2922},
|
|
{"cvmx_usbc#_hprt" , CVMX_CSR_DB_TYPE_NCB, 32, 1282, 15, 2924},
|
|
{"cvmx_usbc#_hptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1283, 2, 2939},
|
|
{"cvmx_usbc#_hptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1284, 3, 2941},
|
|
{"cvmx_usbc#_nptxdfifo#" , CVMX_CSR_DB_TYPE_NCB, 32, 1285, 1, 2944},
|
|
{"cvmx_usbc#_pcgcctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1293, 6, 2945},
|
|
{"cvmx_usbn#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1294, 8, 2951},
|
|
{"cvmx_usbn#_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1295, 15, 2959},
|
|
{"cvmx_usbn#_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 1296, 6, 2974},
|
|
{"cvmx_usbn#_dma0_inb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 1297, 2, 2980},
|
|
{"cvmx_usbn#_dma0_inb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 1298, 2, 2982},
|
|
{"cvmx_usbn#_dma0_inb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 1299, 2, 2984},
|
|
{"cvmx_usbn#_dma0_inb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 1300, 2, 2986},
|
|
{"cvmx_usbn#_dma0_inb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 1301, 2, 2988},
|
|
{"cvmx_usbn#_dma0_inb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 1302, 2, 2990},
|
|
{"cvmx_usbn#_dma0_inb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 1303, 2, 2992},
|
|
{"cvmx_usbn#_dma0_inb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 1304, 2, 2994},
|
|
{"cvmx_usbn#_dma0_outb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 1305, 2, 2996},
|
|
{"cvmx_usbn#_dma0_outb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 1306, 2, 2998},
|
|
{"cvmx_usbn#_dma0_outb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 1307, 2, 3000},
|
|
{"cvmx_usbn#_dma0_outb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 1308, 2, 3002},
|
|
{"cvmx_usbn#_dma0_outb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 1309, 2, 3004},
|
|
{"cvmx_usbn#_dma0_outb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 1310, 2, 3006},
|
|
{"cvmx_usbn#_dma0_outb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 1311, 2, 3008},
|
|
{"cvmx_usbn#_dma0_outb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 1312, 2, 3010},
|
|
{"cvmx_usbn#_dma_test" , CVMX_CSR_DB_TYPE_NCB, 64, 1313, 7, 3012},
|
|
{"cvmx_usbn#_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 1314, 34, 3019},
|
|
{"cvmx_usbn#_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 1315, 34, 3053},
|
|
{"cvmx_usbn#_usbp_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1316, 35, 3087},
|
|
{NULL,0,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn50xx[] = {
|
|
/* name , --------------address, ---------------type, bits, csr offset */
|
|
{"ASX0_GMII_RX_CLK_SET" , 0x11800B0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
|
|
{"ASX0_GMII_RX_DAT_SET" , 0x11800B0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
|
|
{"ASX0_INT_EN" , 0x11800B0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
|
|
{"ASX0_INT_REG" , 0x11800B0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
|
|
{"ASX0_MII_RX_DAT_SET" , 0x11800B0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
|
|
{"ASX0_PRT_LOOP" , 0x11800B0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
|
|
{"ASX0_RX_CLK_SET000" , 0x11800B0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
|
|
{"ASX0_RX_CLK_SET001" , 0x11800B0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
|
|
{"ASX0_RX_CLK_SET002" , 0x11800B0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
|
|
{"ASX0_RX_PRT_EN" , 0x11800B0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
|
|
{"ASX0_TX_CLK_SET000" , 0x11800B0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
|
|
{"ASX0_TX_CLK_SET001" , 0x11800B0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
|
|
{"ASX0_TX_CLK_SET002" , 0x11800B0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
|
|
{"ASX0_TX_COMP_BYP" , 0x11800B0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
|
|
{"ASX0_TX_HI_WATER000" , 0x11800B0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
|
|
{"ASX0_TX_HI_WATER001" , 0x11800B0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
|
|
{"ASX0_TX_HI_WATER002" , 0x11800B0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
|
|
{"ASX0_TX_PRT_EN" , 0x11800B0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
|
|
{"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 12},
|
|
{"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 13},
|
|
{"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 14},
|
|
{"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 15},
|
|
{"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
|
|
{"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
|
|
{"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
|
|
{"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
|
|
{"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 16},
|
|
{"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
|
|
{"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
|
|
{"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
|
|
{"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
|
|
{"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 17},
|
|
{"CIU_INT0_EN4_0" , 0x1070000000C80ull, CVMX_CSR_DB_TYPE_NCB, 64, 18},
|
|
{"CIU_INT1_EN4_0" , 0x1070000000C90ull, CVMX_CSR_DB_TYPE_NCB, 64, 18},
|
|
{"CIU_INT0_EN4_1" , 0x1070000000C88ull, CVMX_CSR_DB_TYPE_NCB, 64, 19},
|
|
{"CIU_INT1_EN4_1" , 0x1070000000C98ull, CVMX_CSR_DB_TYPE_NCB, 64, 19},
|
|
{"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
|
|
{"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
|
|
{"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
|
|
{"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
|
|
{"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 20},
|
|
{"CIU_INT0_SUM4" , 0x1070000000C00ull, CVMX_CSR_DB_TYPE_NCB, 64, 21},
|
|
{"CIU_INT1_SUM4" , 0x1070000000C08ull, CVMX_CSR_DB_TYPE_NCB, 64, 21},
|
|
{"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 22},
|
|
{"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 23},
|
|
{"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 23},
|
|
{"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 24},
|
|
{"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 25},
|
|
{"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 26},
|
|
{"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 27},
|
|
{"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 28},
|
|
{"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 29},
|
|
{"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 30},
|
|
{"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 31},
|
|
{"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 32},
|
|
{"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 33},
|
|
{"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 34},
|
|
{"DBG_DATA" , 0x11F00000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 35},
|
|
{"FPA_BIST_STATUS" , 0x11800280000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
|
|
{"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
|
|
{"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
|
|
{"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
|
|
{"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
|
|
{"FPA_QUE1_AVAILABLE" , 0x11800280000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
|
|
{"FPA_QUE2_AVAILABLE" , 0x11800280000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
|
|
{"FPA_QUE3_AVAILABLE" , 0x11800280000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
|
|
{"FPA_QUE4_AVAILABLE" , 0x11800280000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
|
|
{"FPA_QUE5_AVAILABLE" , 0x11800280000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
|
|
{"FPA_QUE6_AVAILABLE" , 0x11800280000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
|
|
{"FPA_QUE7_AVAILABLE" , 0x11800280000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
|
|
{"FPA_QUE0_PAGE_INDEX" , 0x11800280000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
|
|
{"FPA_QUE1_PAGE_INDEX" , 0x11800280000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
|
|
{"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
|
|
{"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
|
|
{"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
|
|
{"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
|
|
{"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
|
|
{"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
|
|
{"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
|
|
{"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
|
|
{"FPA_WART_CTL" , 0x11800280000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
|
|
{"FPA_WART_STATUS" , 0x11800280000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
|
|
{"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
|
|
{"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
|
|
{"GMX0_INF_MODE" , 0x11800080007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
|
|
{"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
|
|
{"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
|
|
{"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
|
|
{"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
|
|
{"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
|
|
{"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
|
|
{"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
|
|
{"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
|
|
{"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
|
|
{"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
|
|
{"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
|
|
{"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
|
|
{"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
|
|
{"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
|
|
{"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
|
|
{"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
|
|
{"GMX0_RX000_ADR_CAM4" , 0x11800080001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
|
|
{"GMX0_RX001_ADR_CAM4" , 0x11800080009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
|
|
{"GMX0_RX002_ADR_CAM4" , 0x11800080011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
|
|
{"GMX0_RX000_ADR_CAM5" , 0x11800080001A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
|
|
{"GMX0_RX001_ADR_CAM5" , 0x11800080009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
|
|
{"GMX0_RX002_ADR_CAM5" , 0x11800080011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
|
|
{"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
|
|
{"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
|
|
{"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
|
|
{"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
|
|
{"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
|
|
{"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
|
|
{"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
|
|
{"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
|
|
{"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
|
|
{"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
|
|
{"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
|
|
{"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
|
|
{"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
|
|
{"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
|
|
{"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
|
|
{"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
|
|
{"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
|
|
{"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
|
|
{"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
|
|
{"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
|
|
{"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
|
|
{"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
|
|
{"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
|
|
{"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
|
|
{"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
|
|
{"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
|
|
{"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
|
|
{"GMX0_RX000_PAUSE_DROP_TIME" , 0x1180008000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"GMX0_RX001_PAUSE_DROP_TIME" , 0x1180008000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"GMX0_RX002_PAUSE_DROP_TIME" , 0x1180008001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"GMX0_RX000_RX_INBND" , 0x1180008000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"GMX0_RX001_RX_INBND" , 0x1180008000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"GMX0_RX002_RX_INBND" , 0x1180008001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
|
|
{"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
|
|
{"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
|
|
{"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
|
|
{"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
|
|
{"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
|
|
{"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
|
|
{"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
|
|
{"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
|
|
{"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
|
|
{"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
|
|
{"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 71},
|
|
{"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 72},
|
|
{"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 73},
|
|
{"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
|
|
{"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
|
|
{"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 74},
|
|
{"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
|
|
{"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
|
|
{"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 75},
|
|
{"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
|
|
{"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
|
|
{"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 76},
|
|
{"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
|
|
{"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
|
|
{"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 77},
|
|
{"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
|
|
{"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
|
|
{"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 78},
|
|
{"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
|
|
{"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
|
|
{"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 79},
|
|
{"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
|
|
{"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
|
|
{"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 80},
|
|
{"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
|
|
{"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
|
|
{"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 81},
|
|
{"GMX0_RX_PRT_INFO" , 0x11800080004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 82},
|
|
{"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 83},
|
|
{"GMX0_RX_TX_STATUS" , 0x11800080007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 84},
|
|
{"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX0_SMAC001" , 0x1180008000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 85},
|
|
{"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 86},
|
|
{"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX0_TX001_APPEND" , 0x1180008000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 87},
|
|
{"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX0_TX001_BURST" , 0x1180008000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 88},
|
|
{"GMX0_TX000_CLK" , 0x1180008000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_TX001_CLK" , 0x1180008000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_TX002_CLK" , 0x1180008001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 89},
|
|
{"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_TX001_CTL" , 0x1180008000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 90},
|
|
{"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_TX001_MIN_PKT" , 0x1180008000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 91},
|
|
{"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 92},
|
|
{"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 93},
|
|
{"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_TX001_PAUSE_TOGO" , 0x1180008000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 94},
|
|
{"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_TX001_PAUSE_ZERO" , 0x1180008000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 95},
|
|
{"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_TX001_SLOT" , 0x1180008000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 96},
|
|
{"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_TX001_SOFT_PAUSE" , 0x1180008000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 97},
|
|
{"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_TX001_STAT0" , 0x1180008000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_TX001_STAT1" , 0x1180008000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_TX001_STAT2" , 0x1180008000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX0_TX001_STAT3" , 0x1180008000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"GMX0_TX000_STAT4" , 0x11800080002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX0_TX001_STAT4" , 0x1180008000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX0_TX002_STAT4" , 0x11800080012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"GMX0_TX000_STAT5" , 0x11800080002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX0_TX001_STAT5" , 0x1180008000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX0_TX002_STAT5" , 0x11800080012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"GMX0_TX000_STAT6" , 0x11800080002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_TX001_STAT6" , 0x1180008000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_TX002_STAT6" , 0x11800080012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"GMX0_TX000_STAT7" , 0x11800080002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX0_TX001_STAT7" , 0x1180008000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX0_TX002_STAT7" , 0x11800080012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"GMX0_TX000_STAT8" , 0x11800080002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_TX001_STAT8" , 0x1180008000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_TX002_STAT8" , 0x11800080012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"GMX0_TX000_STAT9" , 0x11800080002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_TX001_STAT9" , 0x1180008000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_TX002_STAT9" , 0x11800080012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX0_TX001_STATS_CTL" , 0x1180008000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_TX001_THRESH" , 0x1180008000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_TX_BP" , 0x11800080004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX0_TX_CLK_MSK000" , 0x1180008000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX0_TX_CLK_MSK001" , 0x1180008000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX0_TX_CORRUPT" , 0x11800080004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX0_TX_LFSR" , 0x11800080004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX0_TX_OVR_BP" , 0x11800080004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
|
|
{"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
|
|
{"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
|
|
{"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
|
|
{"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
|
|
{"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
|
|
{"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
|
|
{"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
|
|
{"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
|
|
{"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
|
|
{"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
|
|
{"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
|
|
{"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
|
|
{"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
|
|
{"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
|
|
{"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 123},
|
|
{"GPIO_BOOT_ENA" , 0x10700000008A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 124},
|
|
{"GPIO_DBG_ENA" , 0x10700000008A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 125},
|
|
{"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 126},
|
|
{"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 127},
|
|
{"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 128},
|
|
{"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 129},
|
|
{"GPIO_XBIT_CFG16" , 0x1070000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
|
|
{"GPIO_XBIT_CFG17" , 0x1070000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
|
|
{"GPIO_XBIT_CFG18" , 0x1070000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
|
|
{"GPIO_XBIT_CFG19" , 0x1070000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
|
|
{"GPIO_XBIT_CFG20" , 0x1070000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
|
|
{"GPIO_XBIT_CFG21" , 0x1070000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
|
|
{"GPIO_XBIT_CFG22" , 0x1070000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
|
|
{"GPIO_XBIT_CFG23" , 0x1070000000938ull, CVMX_CSR_DB_TYPE_NCB, 64, 130},
|
|
{"IOB_BIST_STATUS" , 0x11800F00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"IOB_CTL_STATUS" , 0x11800F0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"IOB_FAU_TIMEOUT" , 0x11800F0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"IOB_INB_CONTROL_MATCH" , 0x11800F0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"IOB_INB_CONTROL_MATCH_ENB" , 0x11800F0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"IOB_INB_DATA_MATCH" , 0x11800F0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"IOB_INB_DATA_MATCH_ENB" , 0x11800F0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"IOB_INT_ENB" , 0x11800F0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"IOB_INT_SUM" , 0x11800F0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"IOB_OUTB_CONTROL_MATCH" , 0x11800F0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800F00000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"IOB_OUTB_DATA_MATCH" , 0x11800F0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"IOB_OUTB_DATA_MATCH_ENB" , 0x11800F00000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"IOB_PKT_ERR" , 0x11800F0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"IPD_1ST_MBUFF_SKIP" , 0x14F0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 145},
|
|
{"IPD_1ST_NEXT_PTR_BACK" , 0x14F0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 146},
|
|
{"IPD_2ND_NEXT_PTR_BACK" , 0x14F0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 147},
|
|
{"IPD_BIST_STATUS" , 0x14F00000007F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 148},
|
|
{"IPD_BP_PRT_RED_END" , 0x14F0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 149},
|
|
{"IPD_CLK_COUNT" , 0x14F0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 150},
|
|
{"IPD_CTL_STATUS" , 0x14F0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 151},
|
|
{"IPD_INT_ENB" , 0x14F0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 152},
|
|
{"IPD_INT_SUM" , 0x14F0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 153},
|
|
{"IPD_NOT_1ST_MBUFF_SKIP" , 0x14F0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 154},
|
|
{"IPD_PACKET_MBUFF_SIZE" , 0x14F0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 155},
|
|
{"IPD_PKT_PTR_VALID" , 0x14F0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 156},
|
|
{"IPD_PORT0_BP_PAGE_CNT" , 0x14F0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
|
|
{"IPD_PORT1_BP_PAGE_CNT" , 0x14F0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
|
|
{"IPD_PORT2_BP_PAGE_CNT" , 0x14F0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
|
|
{"IPD_PORT32_BP_PAGE_CNT" , 0x14F0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
|
|
{"IPD_PORT33_BP_PAGE_CNT" , 0x14F0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 157},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14F00000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14F00000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14F00000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14F00000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR33" , 0x14F00000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 158},
|
|
{"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14F0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 159},
|
|
{"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14F0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 160},
|
|
{"IPD_PTR_COUNT" , 0x14F0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 161},
|
|
{"IPD_PWP_PTR_FIFO_CTL" , 0x14F0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 162},
|
|
{"IPD_QOS0_RED_MARKS" , 0x14F0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
|
|
{"IPD_QOS1_RED_MARKS" , 0x14F0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
|
|
{"IPD_QOS2_RED_MARKS" , 0x14F0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
|
|
{"IPD_QOS3_RED_MARKS" , 0x14F0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
|
|
{"IPD_QOS4_RED_MARKS" , 0x14F0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
|
|
{"IPD_QOS5_RED_MARKS" , 0x14F00000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
|
|
{"IPD_QOS6_RED_MARKS" , 0x14F00000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
|
|
{"IPD_QOS7_RED_MARKS" , 0x14F00000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 163},
|
|
{"IPD_QUE0_FREE_PAGE_CNT" , 0x14F0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 164},
|
|
{"IPD_RED_PORT_ENABLE" , 0x14F00000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 165},
|
|
{"IPD_RED_QUE0_PARAM" , 0x14F00000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
|
|
{"IPD_RED_QUE1_PARAM" , 0x14F00000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
|
|
{"IPD_RED_QUE2_PARAM" , 0x14F00000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
|
|
{"IPD_RED_QUE3_PARAM" , 0x14F00000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
|
|
{"IPD_RED_QUE4_PARAM" , 0x14F0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
|
|
{"IPD_RED_QUE5_PARAM" , 0x14F0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
|
|
{"IPD_RED_QUE6_PARAM" , 0x14F0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
|
|
{"IPD_RED_QUE7_PARAM" , 0x14F0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 166},
|
|
{"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14F0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 167},
|
|
{"IPD_SUB_PORT_FCS" , 0x14F0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 168},
|
|
{"IPD_WQE_FPA_QUEUE" , 0x14F0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 169},
|
|
{"IPD_WQE_PTR_VALID" , 0x14F0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 170},
|
|
{"L2C_BST0" , 0x11800800007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"L2C_BST1" , 0x11800800007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"L2C_BST2" , 0x11800800007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"L2C_CFG" , 0x1180080000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"L2C_DBG" , 0x1180080000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"L2C_DUT" , 0x1180080000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"L2C_LCKBASE" , 0x1180080000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
|
|
{"L2C_LCKOFF" , 0x1180080000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
|
|
{"L2C_LFB0" , 0x1180080000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
|
|
{"L2C_LFB1" , 0x1180080000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
|
|
{"L2C_LFB2" , 0x1180080000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
|
|
{"L2C_LFB3" , 0x11800800000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
|
|
{"L2C_PFC0" , 0x1180080000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
|
|
{"L2C_PFC1" , 0x11800800000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
|
|
{"L2C_PFC2" , 0x11800800000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
|
|
{"L2C_PFC3" , 0x11800800000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
|
|
{"L2C_PFCTL" , 0x1180080000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
|
|
{"L2C_SPAR0" , 0x1180080000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
|
|
{"L2C_SPAR4" , 0x1180080000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
|
|
{"L2D_BST0" , 0x1180080000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
|
|
{"L2D_BST1" , 0x1180080000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
|
|
{"L2D_BST2" , 0x1180080000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
|
|
{"L2D_BST3" , 0x1180080000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
|
|
{"L2D_ERR" , 0x1180080000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 191},
|
|
{"L2D_FADR" , 0x1180080000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 192},
|
|
{"L2D_FSYN0" , 0x1180080000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 193},
|
|
{"L2D_FSYN1" , 0x1180080000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 194},
|
|
{"L2D_FUS0" , 0x11800800007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 195},
|
|
{"L2D_FUS1" , 0x11800800007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
|
|
{"L2D_FUS2" , 0x11800800007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
|
|
{"L2D_FUS3" , 0x11800800007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
|
|
{"L2T_ERR" , 0x1180080000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
|
|
{"LMC0_BIST_CTL" , 0x11800880000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
|
|
{"LMC0_BIST_RESULT" , 0x11800880000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
|
|
{"LMC0_COMP_CTL" , 0x1180088000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
|
|
{"LMC0_CTL" , 0x1180088000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
|
|
{"LMC0_CTL1" , 0x1180088000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
|
|
{"LMC0_DCLK_CNT_HI" , 0x1180088000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 205},
|
|
{"LMC0_DCLK_CNT_LO" , 0x1180088000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 206},
|
|
{"LMC0_DDR2_CTL" , 0x1180088000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 207},
|
|
{"LMC0_DELAY_CFG" , 0x1180088000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 208},
|
|
{"LMC0_DUAL_MEMCFG" , 0x1180088000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 209},
|
|
{"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 210},
|
|
{"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
|
|
{"LMC0_IFB_CNT_HI" , 0x1180088000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
|
|
{"LMC0_IFB_CNT_LO" , 0x1180088000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
|
|
{"LMC0_MEM_CFG0" , 0x1180088000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
|
|
{"LMC0_MEM_CFG1" , 0x1180088000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
|
|
{"LMC0_OPS_CNT_HI" , 0x1180088000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
|
|
{"LMC0_OPS_CNT_LO" , 0x1180088000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
|
|
{"LMC0_PLL_CTL" , 0x11800880000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
|
|
{"LMC0_PLL_STATUS" , 0x11800880000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
|
|
{"LMC0_RODT_COMP_CTL" , 0x11800880000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
|
|
{"LMC0_RODT_CTL" , 0x1180088000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
|
|
{"LMC0_WODT_CTL0" , 0x1180088000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
|
|
{"MIO_BOOT_BIST_STAT" , 0x11800000000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
|
|
{"MIO_BOOT_COMP" , 0x11800000000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
|
|
{"MIO_BOOT_ERR" , 0x11800000000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
|
|
{"MIO_BOOT_INT" , 0x11800000000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
|
|
{"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
|
|
{"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
|
|
{"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
|
|
{"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
|
|
{"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
|
|
{"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
|
|
{"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
|
|
{"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
|
|
{"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
|
|
{"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
|
|
{"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
|
|
{"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
|
|
{"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
|
|
{"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
|
|
{"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
|
|
{"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
|
|
{"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
|
|
{"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
|
|
{"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
|
|
{"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 231},
|
|
{"MIO_BOOT_THR" , 0x11800000000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 232},
|
|
{"MIO_FUS_BNK_DAT0" , 0x1180000001520ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
|
|
{"MIO_FUS_BNK_DAT1" , 0x1180000001528ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
|
|
{"MIO_FUS_BNK_DAT2" , 0x1180000001530ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
|
|
{"MIO_FUS_BNK_DAT3" , 0x1180000001538ull, CVMX_CSR_DB_TYPE_RSL, 64, 233},
|
|
{"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 234},
|
|
{"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 235},
|
|
{"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 236},
|
|
{"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 237},
|
|
{"MIO_FUS_EMA" , 0x1180000001550ull, CVMX_CSR_DB_TYPE_RSL, 64, 238},
|
|
{"MIO_FUS_PDF" , 0x1180000001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 239},
|
|
{"MIO_FUS_PLL" , 0x1180000001580ull, CVMX_CSR_DB_TYPE_RSL, 64, 240},
|
|
{"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 241},
|
|
{"MIO_FUS_PROG_TIMES" , 0x1180000001518ull, CVMX_CSR_DB_TYPE_RSL, 64, 242},
|
|
{"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 243},
|
|
{"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 244},
|
|
{"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 245},
|
|
{"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 246},
|
|
{"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 247},
|
|
{"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 248},
|
|
{"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 249},
|
|
{"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 250},
|
|
{"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
|
|
{"MIO_UART1_DLH" , 0x1180000000C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 251},
|
|
{"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
|
|
{"MIO_UART1_DLL" , 0x1180000000C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
|
|
{"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
|
|
{"MIO_UART1_FAR" , 0x1180000000D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
|
|
{"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
|
|
{"MIO_UART1_FCR" , 0x1180000000C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
|
|
{"MIO_UART0_HTX" , 0x1180000000B08ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
|
|
{"MIO_UART1_HTX" , 0x1180000000F08ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
|
|
{"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
|
|
{"MIO_UART1_IER" , 0x1180000000C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
|
|
{"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
|
|
{"MIO_UART1_IIR" , 0x1180000000C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
|
|
{"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
|
|
{"MIO_UART1_LCR" , 0x1180000000C18ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
|
|
{"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
|
|
{"MIO_UART1_LSR" , 0x1180000000C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
|
|
{"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
|
|
{"MIO_UART1_MCR" , 0x1180000000C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
|
|
{"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
|
|
{"MIO_UART1_MSR" , 0x1180000000C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
|
|
{"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
|
|
{"MIO_UART1_RBR" , 0x1180000000C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
|
|
{"MIO_UART0_RFL" , 0x1180000000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
|
|
{"MIO_UART1_RFL" , 0x1180000000E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
|
|
{"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
|
|
{"MIO_UART1_RFW" , 0x1180000000D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
|
|
{"MIO_UART0_SBCR" , 0x1180000000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
|
|
{"MIO_UART1_SBCR" , 0x1180000000E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
|
|
{"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
|
|
{"MIO_UART1_SCR" , 0x1180000000C38ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
|
|
{"MIO_UART0_SFE" , 0x1180000000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
|
|
{"MIO_UART1_SFE" , 0x1180000000E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
|
|
{"MIO_UART0_SRR" , 0x1180000000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
|
|
{"MIO_UART1_SRR" , 0x1180000000E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
|
|
{"MIO_UART0_SRT" , 0x1180000000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
|
|
{"MIO_UART1_SRT" , 0x1180000000E38ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
|
|
{"MIO_UART0_SRTS" , 0x1180000000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
|
|
{"MIO_UART1_SRTS" , 0x1180000000E18ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
|
|
{"MIO_UART0_STT" , 0x1180000000B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
|
|
{"MIO_UART1_STT" , 0x1180000000F00ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
|
|
{"MIO_UART0_TFL" , 0x1180000000A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
|
|
{"MIO_UART1_TFL" , 0x1180000000E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
|
|
{"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
|
|
{"MIO_UART1_TFR" , 0x1180000000D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
|
|
{"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
|
|
{"MIO_UART1_THR" , 0x1180000000C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
|
|
{"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
|
|
{"MIO_UART1_USR" , 0x1180000000D38ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
|
|
{"MPI_CFG" , 0x1070000001000ull, CVMX_CSR_DB_TYPE_NCB, 64, 276},
|
|
{"MPI_DAT0" , 0x1070000001080ull, CVMX_CSR_DB_TYPE_NCB, 64, 277},
|
|
{"MPI_DAT1" , 0x1070000001088ull, CVMX_CSR_DB_TYPE_NCB, 64, 277},
|
|
{"MPI_DAT2" , 0x1070000001090ull, CVMX_CSR_DB_TYPE_NCB, 64, 277},
|
|
{"MPI_DAT3" , 0x1070000001098ull, CVMX_CSR_DB_TYPE_NCB, 64, 277},
|
|
{"MPI_DAT4" , 0x10700000010A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 277},
|
|
{"MPI_DAT5" , 0x10700000010A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 277},
|
|
{"MPI_DAT6" , 0x10700000010B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 277},
|
|
{"MPI_DAT7" , 0x10700000010B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 277},
|
|
{"MPI_DAT8" , 0x10700000010C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 277},
|
|
{"MPI_STS" , 0x1070000001008ull, CVMX_CSR_DB_TYPE_NCB, 64, 278},
|
|
{"MPI_TX" , 0x1070000001010ull, CVMX_CSR_DB_TYPE_NCB, 64, 279},
|
|
{"NPI_BASE_ADDR_INPUT0" , 0x11F0000000070ull, CVMX_CSR_DB_TYPE_NCB, 64, 280},
|
|
{"NPI_BASE_ADDR_INPUT1" , 0x11F0000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 280},
|
|
{"NPI_BASE_ADDR_OUTPUT0" , 0x11F00000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 281},
|
|
{"NPI_BASE_ADDR_OUTPUT1" , 0x11F00000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 281},
|
|
{"NPI_BIST_STATUS" , 0x11F00000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 282},
|
|
{"NPI_BUFF_SIZE_OUTPUT0" , 0x11F00000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 283},
|
|
{"NPI_BUFF_SIZE_OUTPUT1" , 0x11F00000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 283},
|
|
{"NPI_COMP_CTL" , 0x11F0000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 284},
|
|
{"NPI_CTL_STATUS" , 0x11F0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 285},
|
|
{"NPI_DBG_SELECT" , 0x11F0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 286},
|
|
{"NPI_DMA_CONTROL" , 0x11F0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 287},
|
|
{"NPI_DMA_HIGHP_COUNTS" , 0x11F0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 288},
|
|
{"NPI_DMA_HIGHP_NADDR" , 0x11F0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 289},
|
|
{"NPI_DMA_LOWP_COUNTS" , 0x11F0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 290},
|
|
{"NPI_DMA_LOWP_NADDR" , 0x11F0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 291},
|
|
{"NPI_HIGHP_DBELL" , 0x11F0000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 292},
|
|
{"NPI_HIGHP_IBUFF_SADDR" , 0x11F0000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 293},
|
|
{"NPI_INPUT_CONTROL" , 0x11F0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 294},
|
|
{"NPI_INT_ENB" , 0x11F0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 295},
|
|
{"NPI_INT_SUM" , 0x11F0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 296},
|
|
{"NPI_LOWP_DBELL" , 0x11F0000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 297},
|
|
{"NPI_LOWP_IBUFF_SADDR" , 0x11F0000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 298},
|
|
{"NPI_MEM_ACCESS_SUBID3" , 0x11F0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 299},
|
|
{"NPI_MEM_ACCESS_SUBID4" , 0x11F0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 299},
|
|
{"NPI_MEM_ACCESS_SUBID5" , 0x11F0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 299},
|
|
{"NPI_MEM_ACCESS_SUBID6" , 0x11F0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 299},
|
|
{"NPI_MSI_RCV" , 0x11F0000001190ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 300},
|
|
{"NPI_NUM_DESC_OUTPUT0" , 0x11F0000000050ull, CVMX_CSR_DB_TYPE_NCB, 64, 301},
|
|
{"NPI_NUM_DESC_OUTPUT1" , 0x11F0000000058ull, CVMX_CSR_DB_TYPE_NCB, 64, 301},
|
|
{"NPI_OUTPUT_CONTROL" , 0x11F0000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 302},
|
|
{"NPI_P0_DBPAIR_ADDR" , 0x11F0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 303},
|
|
{"NPI_P1_DBPAIR_ADDR" , 0x11F0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 303},
|
|
{"NPI_P0_INSTR_ADDR" , 0x11F00000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 304},
|
|
{"NPI_P1_INSTR_ADDR" , 0x11F00000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 304},
|
|
{"NPI_P0_INSTR_CNTS" , 0x11F00000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 305},
|
|
{"NPI_P1_INSTR_CNTS" , 0x11F00000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 305},
|
|
{"NPI_P0_PAIR_CNTS" , 0x11F0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 306},
|
|
{"NPI_P1_PAIR_CNTS" , 0x11F0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 306},
|
|
{"NPI_PCI_BURST_SIZE" , 0x11F00000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 307},
|
|
{"NPI_PCI_INT_ARB_CFG" , 0x11F0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 308},
|
|
{"NPI_PCI_READ_CMD" , 0x11F0000000048ull, CVMX_CSR_DB_TYPE_NCB, 64, 309},
|
|
{"NPI_PORT32_INSTR_HDR" , 0x11F00000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 310},
|
|
{"NPI_PORT33_INSTR_HDR" , 0x11F0000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 311},
|
|
{"NPI_PORT_BP_CONTROL" , 0x11F00000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 312},
|
|
{"NPI_RSL_INT_BLOCKS" , 0x11F0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 313},
|
|
{"NPI_SIZE_INPUT0" , 0x11F0000000078ull, CVMX_CSR_DB_TYPE_NCB, 64, 314},
|
|
{"NPI_SIZE_INPUT1" , 0x11F0000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 314},
|
|
{"NPI_WIN_READ_TO" , 0x11F00000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 315},
|
|
{"PCI_BAR1_INDEX0" , 0x11F0000001100ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX1" , 0x11F0000001104ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX2" , 0x11F0000001108ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX3" , 0x11F000000110Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX4" , 0x11F0000001110ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX5" , 0x11F0000001114ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX6" , 0x11F0000001118ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX7" , 0x11F000000111Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX8" , 0x11F0000001120ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX9" , 0x11F0000001124ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX10" , 0x11F0000001128ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX11" , 0x11F000000112Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX12" , 0x11F0000001130ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX13" , 0x11F0000001134ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX14" , 0x11F0000001138ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX15" , 0x11F000000113Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX16" , 0x11F0000001140ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX17" , 0x11F0000001144ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX18" , 0x11F0000001148ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX19" , 0x11F000000114Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX20" , 0x11F0000001150ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX21" , 0x11F0000001154ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX22" , 0x11F0000001158ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX23" , 0x11F000000115Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX24" , 0x11F0000001160ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX25" , 0x11F0000001164ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX26" , 0x11F0000001168ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX27" , 0x11F000000116Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX28" , 0x11F0000001170ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX29" , 0x11F0000001174ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX30" , 0x11F0000001178ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BAR1_INDEX31" , 0x11F000000117Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 316},
|
|
{"PCI_BIST_REG" , 0x11F00000011C0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 317},
|
|
{"PCI_CFG00" , 0x11F0000001800ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 318},
|
|
{"PCI_CFG01" , 0x11F0000001804ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 319},
|
|
{"PCI_CFG02" , 0x11F0000001808ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 320},
|
|
{"PCI_CFG03" , 0x11F000000180Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 321},
|
|
{"PCI_CFG04" , 0x11F0000001810ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 322},
|
|
{"PCI_CFG05" , 0x11F0000001814ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 323},
|
|
{"PCI_CFG06" , 0x11F0000001818ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 324},
|
|
{"PCI_CFG07" , 0x11F000000181Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 325},
|
|
{"PCI_CFG08" , 0x11F0000001820ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 326},
|
|
{"PCI_CFG09" , 0x11F0000001824ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 327},
|
|
{"PCI_CFG10" , 0x11F0000001828ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 328},
|
|
{"PCI_CFG11" , 0x11F000000182Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 329},
|
|
{"PCI_CFG12" , 0x11F0000001830ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 330},
|
|
{"PCI_CFG13" , 0x11F0000001834ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 331},
|
|
{"PCI_CFG15" , 0x11F000000183Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 332},
|
|
{"PCI_CFG16" , 0x11F0000001840ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 333},
|
|
{"PCI_CFG17" , 0x11F0000001844ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 334},
|
|
{"PCI_CFG18" , 0x11F0000001848ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 335},
|
|
{"PCI_CFG19" , 0x11F000000184Cull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 336},
|
|
{"PCI_CFG20" , 0x11F0000001850ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 337},
|
|
{"PCI_CFG21" , 0x11F0000001854ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 338},
|
|
{"PCI_CFG22" , 0x11F0000001858ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 339},
|
|
{"PCI_CFG56" , 0x11F00000018E0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 340},
|
|
{"PCI_CFG57" , 0x11F00000018E4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 341},
|
|
{"PCI_CFG58" , 0x11F00000018E8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 342},
|
|
{"PCI_CFG59" , 0x11F00000018ECull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 343},
|
|
{"PCI_CFG60" , 0x11F00000018F0ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 344},
|
|
{"PCI_CFG61" , 0x11F00000018F4ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 345},
|
|
{"PCI_CFG62" , 0x11F00000018F8ull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 346},
|
|
{"PCI_CFG63" , 0x11F00000018FCull, CVMX_CSR_DB_TYPE_PCICONFIG, 32, 347},
|
|
{"PCI_CNT_REG" , 0x11F00000011B8ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 348},
|
|
{"PCI_CTL_STATUS_2" , 0x11F000000118Cull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 349},
|
|
{"PCI_DBELL0" , 0x80ull, CVMX_CSR_DB_TYPE_PCI, 32, 350},
|
|
{"PCI_DBELL1" , 0x88ull, CVMX_CSR_DB_TYPE_PCI, 32, 350},
|
|
{"PCI_DMA_CNT0" , 0xA0ull, CVMX_CSR_DB_TYPE_PCI, 32, 351},
|
|
{"PCI_DMA_CNT1" , 0xA8ull, CVMX_CSR_DB_TYPE_PCI, 32, 351},
|
|
{"PCI_DMA_INT_LEV0" , 0xA4ull, CVMX_CSR_DB_TYPE_PCI, 32, 352},
|
|
{"PCI_DMA_INT_LEV1" , 0xACull, CVMX_CSR_DB_TYPE_PCI, 32, 352},
|
|
{"PCI_DMA_TIME0" , 0xB0ull, CVMX_CSR_DB_TYPE_PCI, 32, 353},
|
|
{"PCI_DMA_TIME1" , 0xB4ull, CVMX_CSR_DB_TYPE_PCI, 32, 353},
|
|
{"PCI_INSTR_COUNT0" , 0x84ull, CVMX_CSR_DB_TYPE_PCI, 32, 354},
|
|
{"PCI_INSTR_COUNT1" , 0x8Cull, CVMX_CSR_DB_TYPE_PCI, 32, 354},
|
|
{"PCI_INT_ENB" , 0x38ull, CVMX_CSR_DB_TYPE_PCI, 64, 355},
|
|
{"PCI_INT_ENB2" , 0x11F00000011A0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 356},
|
|
{"PCI_INT_SUM" , 0x30ull, CVMX_CSR_DB_TYPE_PCI, 64, 357},
|
|
{"PCI_INT_SUM2" , 0x11F0000001198ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 358},
|
|
{"PCI_MSI_RCV" , 0xF0ull, CVMX_CSR_DB_TYPE_PCI, 32, 359},
|
|
{"PCI_PKT_CREDITS0" , 0x44ull, CVMX_CSR_DB_TYPE_PCI, 32, 360},
|
|
{"PCI_PKT_CREDITS1" , 0x54ull, CVMX_CSR_DB_TYPE_PCI, 32, 360},
|
|
{"PCI_PKTS_SENT0" , 0x40ull, CVMX_CSR_DB_TYPE_PCI, 32, 361},
|
|
{"PCI_PKTS_SENT1" , 0x50ull, CVMX_CSR_DB_TYPE_PCI, 32, 361},
|
|
{"PCI_PKTS_SENT_INT_LEV0" , 0x48ull, CVMX_CSR_DB_TYPE_PCI, 32, 362},
|
|
{"PCI_PKTS_SENT_INT_LEV1" , 0x58ull, CVMX_CSR_DB_TYPE_PCI, 32, 362},
|
|
{"PCI_PKTS_SENT_TIME0" , 0x4Cull, CVMX_CSR_DB_TYPE_PCI, 32, 363},
|
|
{"PCI_PKTS_SENT_TIME1" , 0x5Cull, CVMX_CSR_DB_TYPE_PCI, 32, 363},
|
|
{"PCI_READ_CMD_6" , 0x11F0000001180ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 364},
|
|
{"PCI_READ_CMD_C" , 0x11F0000001184ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 365},
|
|
{"PCI_READ_CMD_E" , 0x11F0000001188ull, CVMX_CSR_DB_TYPE_PCI_NCB, 32, 366},
|
|
{"PCI_READ_TIMEOUT" , 0x11F00000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 367},
|
|
{"PCI_SCM_REG" , 0x11F00000011A8ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 368},
|
|
{"PCI_TSR_REG" , 0x11F00000011B0ull, CVMX_CSR_DB_TYPE_PCI_NCB, 64, 369},
|
|
{"PCI_WIN_RD_ADDR" , 0x8ull, CVMX_CSR_DB_TYPE_PCI, 64, 370},
|
|
{"PCI_WIN_RD_DATA" , 0x20ull, CVMX_CSR_DB_TYPE_PCI, 64, 371},
|
|
{"PCI_WIN_WR_ADDR" , 0x0ull, CVMX_CSR_DB_TYPE_PCI, 64, 372},
|
|
{"PCI_WIN_WR_DATA" , 0x10ull, CVMX_CSR_DB_TYPE_PCI, 64, 373},
|
|
{"PCI_WIN_WR_MASK" , 0x18ull, CVMX_CSR_DB_TYPE_PCI, 64, 374},
|
|
{"PCM0_DMA_CFG" , 0x1070000010018ull, CVMX_CSR_DB_TYPE_NCB, 64, 375},
|
|
{"PCM1_DMA_CFG" , 0x1070000014018ull, CVMX_CSR_DB_TYPE_NCB, 64, 375},
|
|
{"PCM2_DMA_CFG" , 0x1070000018018ull, CVMX_CSR_DB_TYPE_NCB, 64, 375},
|
|
{"PCM3_DMA_CFG" , 0x107000001C018ull, CVMX_CSR_DB_TYPE_NCB, 64, 375},
|
|
{"PCM0_INT_ENA" , 0x1070000010020ull, CVMX_CSR_DB_TYPE_NCB, 64, 376},
|
|
{"PCM1_INT_ENA" , 0x1070000014020ull, CVMX_CSR_DB_TYPE_NCB, 64, 376},
|
|
{"PCM2_INT_ENA" , 0x1070000018020ull, CVMX_CSR_DB_TYPE_NCB, 64, 376},
|
|
{"PCM3_INT_ENA" , 0x107000001C020ull, CVMX_CSR_DB_TYPE_NCB, 64, 376},
|
|
{"PCM0_INT_SUM" , 0x1070000010028ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
|
|
{"PCM1_INT_SUM" , 0x1070000014028ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
|
|
{"PCM2_INT_SUM" , 0x1070000018028ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
|
|
{"PCM3_INT_SUM" , 0x107000001C028ull, CVMX_CSR_DB_TYPE_NCB, 64, 377},
|
|
{"PCM0_RXADDR" , 0x1070000010068ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
|
|
{"PCM1_RXADDR" , 0x1070000014068ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
|
|
{"PCM2_RXADDR" , 0x1070000018068ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
|
|
{"PCM3_RXADDR" , 0x107000001C068ull, CVMX_CSR_DB_TYPE_NCB, 64, 378},
|
|
{"PCM0_RXCNT" , 0x1070000010060ull, CVMX_CSR_DB_TYPE_NCB, 64, 379},
|
|
{"PCM1_RXCNT" , 0x1070000014060ull, CVMX_CSR_DB_TYPE_NCB, 64, 379},
|
|
{"PCM2_RXCNT" , 0x1070000018060ull, CVMX_CSR_DB_TYPE_NCB, 64, 379},
|
|
{"PCM3_RXCNT" , 0x107000001C060ull, CVMX_CSR_DB_TYPE_NCB, 64, 379},
|
|
{"PCM0_RXMSK0" , 0x10700000100C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 380},
|
|
{"PCM1_RXMSK0" , 0x10700000140C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 380},
|
|
{"PCM2_RXMSK0" , 0x10700000180C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 380},
|
|
{"PCM3_RXMSK0" , 0x107000001C0C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 380},
|
|
{"PCM0_RXMSK1" , 0x10700000100C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
|
|
{"PCM1_RXMSK1" , 0x10700000140C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
|
|
{"PCM2_RXMSK1" , 0x10700000180C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
|
|
{"PCM3_RXMSK1" , 0x107000001C0C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 381},
|
|
{"PCM0_RXMSK2" , 0x10700000100D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
|
|
{"PCM1_RXMSK2" , 0x10700000140D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
|
|
{"PCM2_RXMSK2" , 0x10700000180D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
|
|
{"PCM3_RXMSK2" , 0x107000001C0D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 382},
|
|
{"PCM0_RXMSK3" , 0x10700000100D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
|
|
{"PCM1_RXMSK3" , 0x10700000140D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
|
|
{"PCM2_RXMSK3" , 0x10700000180D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
|
|
{"PCM3_RXMSK3" , 0x107000001C0D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 383},
|
|
{"PCM0_RXMSK4" , 0x10700000100E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
|
|
{"PCM1_RXMSK4" , 0x10700000140E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
|
|
{"PCM2_RXMSK4" , 0x10700000180E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
|
|
{"PCM3_RXMSK4" , 0x107000001C0E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 384},
|
|
{"PCM0_RXMSK5" , 0x10700000100E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
|
|
{"PCM1_RXMSK5" , 0x10700000140E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
|
|
{"PCM2_RXMSK5" , 0x10700000180E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
|
|
{"PCM3_RXMSK5" , 0x107000001C0E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 385},
|
|
{"PCM0_RXMSK6" , 0x10700000100F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
|
|
{"PCM1_RXMSK6" , 0x10700000140F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
|
|
{"PCM2_RXMSK6" , 0x10700000180F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
|
|
{"PCM3_RXMSK6" , 0x107000001C0F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 386},
|
|
{"PCM0_RXMSK7" , 0x10700000100F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
|
|
{"PCM1_RXMSK7" , 0x10700000140F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
|
|
{"PCM2_RXMSK7" , 0x10700000180F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
|
|
{"PCM3_RXMSK7" , 0x107000001C0F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 387},
|
|
{"PCM0_RXSTART" , 0x1070000010058ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
|
|
{"PCM1_RXSTART" , 0x1070000014058ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
|
|
{"PCM2_RXSTART" , 0x1070000018058ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
|
|
{"PCM3_RXSTART" , 0x107000001C058ull, CVMX_CSR_DB_TYPE_NCB, 64, 388},
|
|
{"PCM0_TDM_CFG" , 0x1070000010010ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
|
|
{"PCM1_TDM_CFG" , 0x1070000014010ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
|
|
{"PCM2_TDM_CFG" , 0x1070000018010ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
|
|
{"PCM3_TDM_CFG" , 0x107000001C010ull, CVMX_CSR_DB_TYPE_NCB, 64, 389},
|
|
{"PCM0_TDM_DBG" , 0x1070000010030ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
|
|
{"PCM1_TDM_DBG" , 0x1070000014030ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
|
|
{"PCM2_TDM_DBG" , 0x1070000018030ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
|
|
{"PCM3_TDM_DBG" , 0x107000001C030ull, CVMX_CSR_DB_TYPE_NCB, 64, 390},
|
|
{"PCM0_TXADDR" , 0x1070000010050ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
|
|
{"PCM1_TXADDR" , 0x1070000014050ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
|
|
{"PCM2_TXADDR" , 0x1070000018050ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
|
|
{"PCM3_TXADDR" , 0x107000001C050ull, CVMX_CSR_DB_TYPE_NCB, 64, 391},
|
|
{"PCM0_TXCNT" , 0x1070000010048ull, CVMX_CSR_DB_TYPE_NCB, 64, 392},
|
|
{"PCM1_TXCNT" , 0x1070000014048ull, CVMX_CSR_DB_TYPE_NCB, 64, 392},
|
|
{"PCM2_TXCNT" , 0x1070000018048ull, CVMX_CSR_DB_TYPE_NCB, 64, 392},
|
|
{"PCM3_TXCNT" , 0x107000001C048ull, CVMX_CSR_DB_TYPE_NCB, 64, 392},
|
|
{"PCM0_TXMSK0" , 0x1070000010080ull, CVMX_CSR_DB_TYPE_NCB, 64, 393},
|
|
{"PCM1_TXMSK0" , 0x1070000014080ull, CVMX_CSR_DB_TYPE_NCB, 64, 393},
|
|
{"PCM2_TXMSK0" , 0x1070000018080ull, CVMX_CSR_DB_TYPE_NCB, 64, 393},
|
|
{"PCM3_TXMSK0" , 0x107000001C080ull, CVMX_CSR_DB_TYPE_NCB, 64, 393},
|
|
{"PCM0_TXMSK1" , 0x1070000010088ull, CVMX_CSR_DB_TYPE_NCB, 64, 394},
|
|
{"PCM1_TXMSK1" , 0x1070000014088ull, CVMX_CSR_DB_TYPE_NCB, 64, 394},
|
|
{"PCM2_TXMSK1" , 0x1070000018088ull, CVMX_CSR_DB_TYPE_NCB, 64, 394},
|
|
{"PCM3_TXMSK1" , 0x107000001C088ull, CVMX_CSR_DB_TYPE_NCB, 64, 394},
|
|
{"PCM0_TXMSK2" , 0x1070000010090ull, CVMX_CSR_DB_TYPE_NCB, 64, 395},
|
|
{"PCM1_TXMSK2" , 0x1070000014090ull, CVMX_CSR_DB_TYPE_NCB, 64, 395},
|
|
{"PCM2_TXMSK2" , 0x1070000018090ull, CVMX_CSR_DB_TYPE_NCB, 64, 395},
|
|
{"PCM3_TXMSK2" , 0x107000001C090ull, CVMX_CSR_DB_TYPE_NCB, 64, 395},
|
|
{"PCM0_TXMSK3" , 0x1070000010098ull, CVMX_CSR_DB_TYPE_NCB, 64, 396},
|
|
{"PCM1_TXMSK3" , 0x1070000014098ull, CVMX_CSR_DB_TYPE_NCB, 64, 396},
|
|
{"PCM2_TXMSK3" , 0x1070000018098ull, CVMX_CSR_DB_TYPE_NCB, 64, 396},
|
|
{"PCM3_TXMSK3" , 0x107000001C098ull, CVMX_CSR_DB_TYPE_NCB, 64, 396},
|
|
{"PCM0_TXMSK4" , 0x10700000100A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 397},
|
|
{"PCM1_TXMSK4" , 0x10700000140A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 397},
|
|
{"PCM2_TXMSK4" , 0x10700000180A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 397},
|
|
{"PCM3_TXMSK4" , 0x107000001C0A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 397},
|
|
{"PCM0_TXMSK5" , 0x10700000100A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 398},
|
|
{"PCM1_TXMSK5" , 0x10700000140A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 398},
|
|
{"PCM2_TXMSK5" , 0x10700000180A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 398},
|
|
{"PCM3_TXMSK5" , 0x107000001C0A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 398},
|
|
{"PCM0_TXMSK6" , 0x10700000100B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 399},
|
|
{"PCM1_TXMSK6" , 0x10700000140B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 399},
|
|
{"PCM2_TXMSK6" , 0x10700000180B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 399},
|
|
{"PCM3_TXMSK6" , 0x107000001C0B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 399},
|
|
{"PCM0_TXMSK7" , 0x10700000100B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
|
|
{"PCM1_TXMSK7" , 0x10700000140B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
|
|
{"PCM2_TXMSK7" , 0x10700000180B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
|
|
{"PCM3_TXMSK7" , 0x107000001C0B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
|
|
{"PCM0_TXSTART" , 0x1070000010040ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
|
|
{"PCM1_TXSTART" , 0x1070000014040ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
|
|
{"PCM2_TXSTART" , 0x1070000018040ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
|
|
{"PCM3_TXSTART" , 0x107000001C040ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
|
|
{"PCM_CLK0_CFG" , 0x1070000010000ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
|
|
{"PCM_CLK1_CFG" , 0x1070000014000ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
|
|
{"PCM_CLK0_DBG" , 0x1070000010038ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
|
|
{"PCM_CLK1_DBG" , 0x1070000014038ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
|
|
{"PCM_CLK0_GEN" , 0x1070000010008ull, CVMX_CSR_DB_TYPE_NCB, 64, 404},
|
|
{"PCM_CLK1_GEN" , 0x1070000014008ull, CVMX_CSR_DB_TYPE_NCB, 64, 404},
|
|
{"PIP_BIST_STATUS" , 0x11800A0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
|
|
{"PIP_DEC_IPSEC0" , 0x11800A0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
|
|
{"PIP_DEC_IPSEC1" , 0x11800A0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
|
|
{"PIP_DEC_IPSEC2" , 0x11800A0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
|
|
{"PIP_DEC_IPSEC3" , 0x11800A0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
|
|
{"PIP_FRM_LEN_CHK0" , 0x11800A0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
|
|
{"PIP_FRM_LEN_CHK1" , 0x11800A0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
|
|
{"PIP_GBL_CFG" , 0x11800A0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
|
|
{"PIP_GBL_CTL" , 0x11800A0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
|
|
{"PIP_INT_EN" , 0x11800A0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
|
|
{"PIP_INT_REG" , 0x11800A0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
|
|
{"PIP_IP_OFFSET" , 0x11800A0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
|
|
{"PIP_PRT_CFG0" , 0x11800A0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
|
|
{"PIP_PRT_CFG1" , 0x11800A0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
|
|
{"PIP_PRT_CFG2" , 0x11800A0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
|
|
{"PIP_PRT_CFG32" , 0x11800A0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
|
|
{"PIP_PRT_CFG33" , 0x11800A0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
|
|
{"PIP_PRT_TAG0" , 0x11800A0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
|
|
{"PIP_PRT_TAG1" , 0x11800A0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
|
|
{"PIP_PRT_TAG2" , 0x11800A0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
|
|
{"PIP_PRT_TAG32" , 0x11800A0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
|
|
{"PIP_PRT_TAG33" , 0x11800A0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
|
|
{"PIP_QOS_DIFF0" , 0x11800A0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF1" , 0x11800A0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF2" , 0x11800A0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF3" , 0x11800A0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF4" , 0x11800A0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF5" , 0x11800A0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF6" , 0x11800A0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF7" , 0x11800A0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF8" , 0x11800A0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF9" , 0x11800A0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF10" , 0x11800A0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF11" , 0x11800A0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF12" , 0x11800A0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF13" , 0x11800A0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF14" , 0x11800A0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF15" , 0x11800A0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF16" , 0x11800A0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF17" , 0x11800A0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF18" , 0x11800A0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF19" , 0x11800A0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF20" , 0x11800A00006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF21" , 0x11800A00006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF22" , 0x11800A00006B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF23" , 0x11800A00006B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF24" , 0x11800A00006C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF25" , 0x11800A00006C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF26" , 0x11800A00006D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF27" , 0x11800A00006D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF28" , 0x11800A00006E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF29" , 0x11800A00006E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF30" , 0x11800A00006F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF31" , 0x11800A00006F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF32" , 0x11800A0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF33" , 0x11800A0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF34" , 0x11800A0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF35" , 0x11800A0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF36" , 0x11800A0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF37" , 0x11800A0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF38" , 0x11800A0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF39" , 0x11800A0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF40" , 0x11800A0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF41" , 0x11800A0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF42" , 0x11800A0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF43" , 0x11800A0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF44" , 0x11800A0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF45" , 0x11800A0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF46" , 0x11800A0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF47" , 0x11800A0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF48" , 0x11800A0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF49" , 0x11800A0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF50" , 0x11800A0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF51" , 0x11800A0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF52" , 0x11800A00007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF53" , 0x11800A00007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF54" , 0x11800A00007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF55" , 0x11800A00007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF56" , 0x11800A00007C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF57" , 0x11800A00007C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF58" , 0x11800A00007D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF59" , 0x11800A00007D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF60" , 0x11800A00007E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF61" , 0x11800A00007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF62" , 0x11800A00007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_DIFF63" , 0x11800A00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"PIP_QOS_VLAN0" , 0x11800A00000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
|
|
{"PIP_QOS_VLAN1" , 0x11800A00000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
|
|
{"PIP_QOS_VLAN2" , 0x11800A00000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
|
|
{"PIP_QOS_VLAN3" , 0x11800A00000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
|
|
{"PIP_QOS_VLAN4" , 0x11800A00000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
|
|
{"PIP_QOS_VLAN5" , 0x11800A00000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
|
|
{"PIP_QOS_VLAN6" , 0x11800A00000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
|
|
{"PIP_QOS_VLAN7" , 0x11800A00000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
|
|
{"PIP_QOS_WATCH0" , 0x11800A0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
|
|
{"PIP_QOS_WATCH1" , 0x11800A0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
|
|
{"PIP_QOS_WATCH2" , 0x11800A0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
|
|
{"PIP_QOS_WATCH3" , 0x11800A0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
|
|
{"PIP_QOS_WATCH4" , 0x11800A0000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
|
|
{"PIP_QOS_WATCH5" , 0x11800A0000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
|
|
{"PIP_QOS_WATCH6" , 0x11800A0000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
|
|
{"PIP_QOS_WATCH7" , 0x11800A0000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 417},
|
|
{"PIP_RAW_WORD" , 0x11800A00000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 418},
|
|
{"PIP_SFT_RST" , 0x11800A0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 419},
|
|
{"PIP_STAT0_PRT0" , 0x11800A0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_STAT0_PRT1" , 0x11800A0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_STAT0_PRT2" , 0x11800A00008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_STAT0_PRT32" , 0x11800A0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_STAT0_PRT33" , 0x11800A0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 420},
|
|
{"PIP_STAT1_PRT0" , 0x11800A0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_STAT1_PRT1" , 0x11800A0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_STAT1_PRT2" , 0x11800A00008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_STAT1_PRT32" , 0x11800A0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_STAT1_PRT33" , 0x11800A0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 421},
|
|
{"PIP_STAT2_PRT0" , 0x11800A0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_STAT2_PRT1" , 0x11800A0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_STAT2_PRT2" , 0x11800A00008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_STAT2_PRT32" , 0x11800A0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_STAT2_PRT33" , 0x11800A0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 422},
|
|
{"PIP_STAT3_PRT0" , 0x11800A0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
|
|
{"PIP_STAT3_PRT1" , 0x11800A0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
|
|
{"PIP_STAT3_PRT2" , 0x11800A00008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
|
|
{"PIP_STAT3_PRT32" , 0x11800A0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
|
|
{"PIP_STAT3_PRT33" , 0x11800A0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 423},
|
|
{"PIP_STAT4_PRT0" , 0x11800A0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
|
|
{"PIP_STAT4_PRT1" , 0x11800A0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
|
|
{"PIP_STAT4_PRT2" , 0x11800A00008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
|
|
{"PIP_STAT4_PRT32" , 0x11800A0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
|
|
{"PIP_STAT4_PRT33" , 0x11800A0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 424},
|
|
{"PIP_STAT5_PRT0" , 0x11800A0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
|
|
{"PIP_STAT5_PRT1" , 0x11800A0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
|
|
{"PIP_STAT5_PRT2" , 0x11800A00008C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
|
|
{"PIP_STAT5_PRT32" , 0x11800A0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
|
|
{"PIP_STAT5_PRT33" , 0x11800A0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 425},
|
|
{"PIP_STAT6_PRT0" , 0x11800A0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT6_PRT1" , 0x11800A0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT6_PRT2" , 0x11800A00008D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT6_PRT32" , 0x11800A0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT6_PRT33" , 0x11800A0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 426},
|
|
{"PIP_STAT7_PRT0" , 0x11800A0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT7_PRT1" , 0x11800A0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT7_PRT2" , 0x11800A00008D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT7_PRT32" , 0x11800A0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT7_PRT33" , 0x11800A0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 427},
|
|
{"PIP_STAT8_PRT0" , 0x11800A0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT8_PRT1" , 0x11800A0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT8_PRT2" , 0x11800A00008E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT8_PRT32" , 0x11800A0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT8_PRT33" , 0x11800A0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 428},
|
|
{"PIP_STAT9_PRT0" , 0x11800A0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT9_PRT1" , 0x11800A0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT9_PRT2" , 0x11800A00008E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT9_PRT32" , 0x11800A0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT9_PRT33" , 0x11800A0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 429},
|
|
{"PIP_STAT_CTL" , 0x11800A0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 430},
|
|
{"PIP_STAT_INB_ERRS0" , 0x11800A0001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT_INB_ERRS1" , 0x11800A0001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT_INB_ERRS2" , 0x11800A0001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT_INB_ERRS32" , 0x11800A0001E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT_INB_ERRS33" , 0x11800A0001E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 431},
|
|
{"PIP_STAT_INB_OCTS0" , 0x11800A0001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT_INB_OCTS1" , 0x11800A0001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT_INB_OCTS2" , 0x11800A0001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT_INB_OCTS32" , 0x11800A0001E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT_INB_OCTS33" , 0x11800A0001E28ull, CVMX_CSR_DB_TYPE_RSL, 64, 432},
|
|
{"PIP_STAT_INB_PKTS0" , 0x11800A0001A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT_INB_PKTS1" , 0x11800A0001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT_INB_PKTS2" , 0x11800A0001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT_INB_PKTS32" , 0x11800A0001E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_STAT_INB_PKTS33" , 0x11800A0001E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 433},
|
|
{"PIP_TAG_INC0" , 0x11800A0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC1" , 0x11800A0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC2" , 0x11800A0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC3" , 0x11800A0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC4" , 0x11800A0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC5" , 0x11800A0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC6" , 0x11800A0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC7" , 0x11800A0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC8" , 0x11800A0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC9" , 0x11800A0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC10" , 0x11800A0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC11" , 0x11800A0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC12" , 0x11800A0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC13" , 0x11800A0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC14" , 0x11800A0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC15" , 0x11800A0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC16" , 0x11800A0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC17" , 0x11800A0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC18" , 0x11800A0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC19" , 0x11800A0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC20" , 0x11800A00018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC21" , 0x11800A00018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC22" , 0x11800A00018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC23" , 0x11800A00018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC24" , 0x11800A00018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC25" , 0x11800A00018C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC26" , 0x11800A00018D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC27" , 0x11800A00018D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC28" , 0x11800A00018E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC29" , 0x11800A00018E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC30" , 0x11800A00018F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC31" , 0x11800A00018F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC32" , 0x11800A0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC33" , 0x11800A0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC34" , 0x11800A0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC35" , 0x11800A0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC36" , 0x11800A0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC37" , 0x11800A0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC38" , 0x11800A0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC39" , 0x11800A0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC40" , 0x11800A0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC41" , 0x11800A0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC42" , 0x11800A0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC43" , 0x11800A0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC44" , 0x11800A0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC45" , 0x11800A0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC46" , 0x11800A0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC47" , 0x11800A0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC48" , 0x11800A0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC49" , 0x11800A0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC50" , 0x11800A0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC51" , 0x11800A0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC52" , 0x11800A00019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC53" , 0x11800A00019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC54" , 0x11800A00019B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC55" , 0x11800A00019B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC56" , 0x11800A00019C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC57" , 0x11800A00019C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC58" , 0x11800A00019D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC59" , 0x11800A00019D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC60" , 0x11800A00019E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC61" , 0x11800A00019E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC62" , 0x11800A00019F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_INC63" , 0x11800A00019F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 434},
|
|
{"PIP_TAG_MASK" , 0x11800A0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 435},
|
|
{"PIP_TAG_SECRET" , 0x11800A0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 436},
|
|
{"PIP_TODO_ENTRY" , 0x11800A0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 437},
|
|
{"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 438},
|
|
{"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 439},
|
|
{"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 440},
|
|
{"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 441},
|
|
{"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 442},
|
|
{"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 443},
|
|
{"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 444},
|
|
{"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 445},
|
|
{"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 446},
|
|
{"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 447},
|
|
{"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 448},
|
|
{"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 449},
|
|
{"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 450},
|
|
{"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 451},
|
|
{"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 452},
|
|
{"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 453},
|
|
{"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 454},
|
|
{"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 455},
|
|
{"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 456},
|
|
{"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 457},
|
|
{"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 458},
|
|
{"PKO_REG_DEBUG1" , 0x11800500000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 459},
|
|
{"PKO_REG_DEBUG2" , 0x11800500000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 460},
|
|
{"PKO_REG_DEBUG3" , 0x11800500000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 461},
|
|
{"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 462},
|
|
{"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 463},
|
|
{"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 464},
|
|
{"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 465},
|
|
{"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 466},
|
|
{"PKO_REG_QUEUE_PTRS1" , 0x1180050000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 467},
|
|
{"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 468},
|
|
{"POW_BIST_STAT" , 0x16700000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 469},
|
|
{"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 470},
|
|
{"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 471},
|
|
{"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 472},
|
|
{"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 473},
|
|
{"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 473},
|
|
{"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 473},
|
|
{"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 473},
|
|
{"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 473},
|
|
{"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 473},
|
|
{"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 473},
|
|
{"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 473},
|
|
{"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 474},
|
|
{"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 475},
|
|
{"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 476},
|
|
{"POW_PF_RST_MSK" , 0x1670000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 477},
|
|
{"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 478},
|
|
{"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 478},
|
|
{"POW_QOS_RND0" , 0x16700000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
|
|
{"POW_QOS_RND1" , 0x16700000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
|
|
{"POW_QOS_RND2" , 0x16700000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
|
|
{"POW_QOS_RND3" , 0x16700000001D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
|
|
{"POW_QOS_RND4" , 0x16700000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
|
|
{"POW_QOS_RND5" , 0x16700000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
|
|
{"POW_QOS_RND6" , 0x16700000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
|
|
{"POW_QOS_RND7" , 0x16700000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 479},
|
|
{"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
|
|
{"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
|
|
{"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
|
|
{"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
|
|
{"POW_QOS_THR4" , 0x16700000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
|
|
{"POW_QOS_THR5" , 0x16700000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
|
|
{"POW_QOS_THR6" , 0x16700000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
|
|
{"POW_QOS_THR7" , 0x16700000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 480},
|
|
{"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 481},
|
|
{"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 482},
|
|
{"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 483},
|
|
{"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 484},
|
|
{"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 485},
|
|
{"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 486},
|
|
{"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
|
|
{"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
|
|
{"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
|
|
{"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
|
|
{"POW_WQ_INT_THR4" , 0x16700000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
|
|
{"POW_WQ_INT_THR5" , 0x16700000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
|
|
{"POW_WQ_INT_THR6" , 0x16700000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
|
|
{"POW_WQ_INT_THR7" , 0x16700000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
|
|
{"POW_WQ_INT_THR8" , 0x16700000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
|
|
{"POW_WQ_INT_THR9" , 0x16700000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
|
|
{"POW_WQ_INT_THR10" , 0x16700000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
|
|
{"POW_WQ_INT_THR11" , 0x16700000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
|
|
{"POW_WQ_INT_THR12" , 0x16700000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
|
|
{"POW_WQ_INT_THR13" , 0x16700000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
|
|
{"POW_WQ_INT_THR14" , 0x16700000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
|
|
{"POW_WQ_INT_THR15" , 0x16700000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 487},
|
|
{"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WS_PC4" , 0x16700000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WS_PC5" , 0x16700000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WS_PC6" , 0x16700000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WS_PC7" , 0x16700000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WS_PC8" , 0x16700000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WS_PC9" , 0x16700000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WS_PC10" , 0x16700000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WS_PC11" , 0x16700000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WS_PC12" , 0x16700000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WS_PC13" , 0x16700000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WS_PC14" , 0x16700000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"POW_WS_PC15" , 0x16700000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 488},
|
|
{"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 489},
|
|
{"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 490},
|
|
{"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 491},
|
|
{"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 492},
|
|
{"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 493},
|
|
{"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 494},
|
|
{"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 495},
|
|
{"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 496},
|
|
{"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 497},
|
|
{"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 498},
|
|
{"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 499},
|
|
{"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 500},
|
|
{"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 501},
|
|
{"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 502},
|
|
{"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 503},
|
|
{"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 504},
|
|
{"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 505},
|
|
{"USBC0_DAINT" , 0x16F0010000818ull, CVMX_CSR_DB_TYPE_NCB, 32, 506},
|
|
{"USBC0_DAINTMSK" , 0x16F001000081Cull, CVMX_CSR_DB_TYPE_NCB, 32, 507},
|
|
{"USBC0_DCFG" , 0x16F0010000800ull, CVMX_CSR_DB_TYPE_NCB, 32, 508},
|
|
{"USBC0_DCTL" , 0x16F0010000804ull, CVMX_CSR_DB_TYPE_NCB, 32, 509},
|
|
{"USBC0_DIEPCTL000" , 0x16F0010000900ull, CVMX_CSR_DB_TYPE_NCB, 32, 510},
|
|
{"USBC0_DIEPCTL001" , 0x16F0010000920ull, CVMX_CSR_DB_TYPE_NCB, 32, 510},
|
|
{"USBC0_DIEPCTL002" , 0x16F0010000940ull, CVMX_CSR_DB_TYPE_NCB, 32, 510},
|
|
{"USBC0_DIEPCTL003" , 0x16F0010000960ull, CVMX_CSR_DB_TYPE_NCB, 32, 510},
|
|
{"USBC0_DIEPCTL004" , 0x16F0010000980ull, CVMX_CSR_DB_TYPE_NCB, 32, 510},
|
|
{"USBC0_DIEPINT000" , 0x16F0010000908ull, CVMX_CSR_DB_TYPE_NCB, 32, 511},
|
|
{"USBC0_DIEPINT001" , 0x16F0010000928ull, CVMX_CSR_DB_TYPE_NCB, 32, 511},
|
|
{"USBC0_DIEPINT002" , 0x16F0010000948ull, CVMX_CSR_DB_TYPE_NCB, 32, 511},
|
|
{"USBC0_DIEPINT003" , 0x16F0010000968ull, CVMX_CSR_DB_TYPE_NCB, 32, 511},
|
|
{"USBC0_DIEPINT004" , 0x16F0010000988ull, CVMX_CSR_DB_TYPE_NCB, 32, 511},
|
|
{"USBC0_DIEPMSK" , 0x16F0010000810ull, CVMX_CSR_DB_TYPE_NCB, 32, 512},
|
|
{"USBC0_DIEPTSIZ000" , 0x16F0010000910ull, CVMX_CSR_DB_TYPE_NCB, 32, 513},
|
|
{"USBC0_DIEPTSIZ001" , 0x16F0010000930ull, CVMX_CSR_DB_TYPE_NCB, 32, 513},
|
|
{"USBC0_DIEPTSIZ002" , 0x16F0010000950ull, CVMX_CSR_DB_TYPE_NCB, 32, 513},
|
|
{"USBC0_DIEPTSIZ003" , 0x16F0010000970ull, CVMX_CSR_DB_TYPE_NCB, 32, 513},
|
|
{"USBC0_DIEPTSIZ004" , 0x16F0010000990ull, CVMX_CSR_DB_TYPE_NCB, 32, 513},
|
|
{"USBC0_DOEPCTL000" , 0x16F0010000B00ull, CVMX_CSR_DB_TYPE_NCB, 32, 514},
|
|
{"USBC0_DOEPCTL001" , 0x16F0010000B20ull, CVMX_CSR_DB_TYPE_NCB, 32, 514},
|
|
{"USBC0_DOEPCTL002" , 0x16F0010000B40ull, CVMX_CSR_DB_TYPE_NCB, 32, 514},
|
|
{"USBC0_DOEPCTL003" , 0x16F0010000B60ull, CVMX_CSR_DB_TYPE_NCB, 32, 514},
|
|
{"USBC0_DOEPCTL004" , 0x16F0010000B80ull, CVMX_CSR_DB_TYPE_NCB, 32, 514},
|
|
{"USBC0_DOEPINT000" , 0x16F0010000B08ull, CVMX_CSR_DB_TYPE_NCB, 32, 515},
|
|
{"USBC0_DOEPINT001" , 0x16F0010000B28ull, CVMX_CSR_DB_TYPE_NCB, 32, 515},
|
|
{"USBC0_DOEPINT002" , 0x16F0010000B48ull, CVMX_CSR_DB_TYPE_NCB, 32, 515},
|
|
{"USBC0_DOEPINT003" , 0x16F0010000B68ull, CVMX_CSR_DB_TYPE_NCB, 32, 515},
|
|
{"USBC0_DOEPINT004" , 0x16F0010000B88ull, CVMX_CSR_DB_TYPE_NCB, 32, 515},
|
|
{"USBC0_DOEPMSK" , 0x16F0010000814ull, CVMX_CSR_DB_TYPE_NCB, 32, 516},
|
|
{"USBC0_DOEPTSIZ000" , 0x16F0010000B10ull, CVMX_CSR_DB_TYPE_NCB, 32, 517},
|
|
{"USBC0_DOEPTSIZ001" , 0x16F0010000B30ull, CVMX_CSR_DB_TYPE_NCB, 32, 517},
|
|
{"USBC0_DOEPTSIZ002" , 0x16F0010000B50ull, CVMX_CSR_DB_TYPE_NCB, 32, 517},
|
|
{"USBC0_DOEPTSIZ003" , 0x16F0010000B70ull, CVMX_CSR_DB_TYPE_NCB, 32, 517},
|
|
{"USBC0_DOEPTSIZ004" , 0x16F0010000B90ull, CVMX_CSR_DB_TYPE_NCB, 32, 517},
|
|
{"USBC0_DPTXFSIZ001" , 0x16F0010000104ull, CVMX_CSR_DB_TYPE_NCB, 32, 518},
|
|
{"USBC0_DPTXFSIZ002" , 0x16F0010000108ull, CVMX_CSR_DB_TYPE_NCB, 32, 518},
|
|
{"USBC0_DPTXFSIZ003" , 0x16F001000010Cull, CVMX_CSR_DB_TYPE_NCB, 32, 518},
|
|
{"USBC0_DPTXFSIZ004" , 0x16F0010000110ull, CVMX_CSR_DB_TYPE_NCB, 32, 518},
|
|
{"USBC0_DSTS" , 0x16F0010000808ull, CVMX_CSR_DB_TYPE_NCB, 32, 519},
|
|
{"USBC0_DTKNQR1" , 0x16F0010000820ull, CVMX_CSR_DB_TYPE_NCB, 32, 520},
|
|
{"USBC0_DTKNQR2" , 0x16F0010000824ull, CVMX_CSR_DB_TYPE_NCB, 32, 521},
|
|
{"USBC0_DTKNQR3" , 0x16F0010000830ull, CVMX_CSR_DB_TYPE_NCB, 32, 522},
|
|
{"USBC0_DTKNQR4" , 0x16F0010000834ull, CVMX_CSR_DB_TYPE_NCB, 32, 523},
|
|
{"USBC0_GAHBCFG" , 0x16F0010000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 524},
|
|
{"USBC0_GHWCFG1" , 0x16F0010000044ull, CVMX_CSR_DB_TYPE_NCB, 32, 525},
|
|
{"USBC0_GHWCFG2" , 0x16F0010000048ull, CVMX_CSR_DB_TYPE_NCB, 32, 526},
|
|
{"USBC0_GHWCFG3" , 0x16F001000004Cull, CVMX_CSR_DB_TYPE_NCB, 32, 527},
|
|
{"USBC0_GHWCFG4" , 0x16F0010000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 528},
|
|
{"USBC0_GINTMSK" , 0x16F0010000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 529},
|
|
{"USBC0_GINTSTS" , 0x16F0010000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 530},
|
|
{"USBC0_GNPTXFSIZ" , 0x16F0010000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 531},
|
|
{"USBC0_GNPTXSTS" , 0x16F001000002Cull, CVMX_CSR_DB_TYPE_NCB, 32, 532},
|
|
{"USBC0_GOTGCTL" , 0x16F0010000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 533},
|
|
{"USBC0_GOTGINT" , 0x16F0010000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 534},
|
|
{"USBC0_GRSTCTL" , 0x16F0010000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 535},
|
|
{"USBC0_GRXFSIZ" , 0x16F0010000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 536},
|
|
{"USBC0_GRXSTSPD" , 0x16F0010040020ull, CVMX_CSR_DB_TYPE_NCB, 32, 537},
|
|
{"USBC0_GRXSTSPH" , 0x16F0010000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 538},
|
|
{"USBC0_GRXSTSRD" , 0x16F001004001Cull, CVMX_CSR_DB_TYPE_NCB, 32, 539},
|
|
{"USBC0_GRXSTSRH" , 0x16F001000001Cull, CVMX_CSR_DB_TYPE_NCB, 32, 540},
|
|
{"USBC0_GSNPSID" , 0x16F0010000040ull, CVMX_CSR_DB_TYPE_NCB, 32, 541},
|
|
{"USBC0_GUSBCFG" , 0x16F001000000Cull, CVMX_CSR_DB_TYPE_NCB, 32, 542},
|
|
{"USBC0_HAINT" , 0x16F0010000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 543},
|
|
{"USBC0_HAINTMSK" , 0x16F0010000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 544},
|
|
{"USBC0_HCCHAR000" , 0x16F0010000500ull, CVMX_CSR_DB_TYPE_NCB, 32, 545},
|
|
{"USBC0_HCCHAR001" , 0x16F0010000520ull, CVMX_CSR_DB_TYPE_NCB, 32, 545},
|
|
{"USBC0_HCCHAR002" , 0x16F0010000540ull, CVMX_CSR_DB_TYPE_NCB, 32, 545},
|
|
{"USBC0_HCCHAR003" , 0x16F0010000560ull, CVMX_CSR_DB_TYPE_NCB, 32, 545},
|
|
{"USBC0_HCCHAR004" , 0x16F0010000580ull, CVMX_CSR_DB_TYPE_NCB, 32, 545},
|
|
{"USBC0_HCCHAR005" , 0x16F00100005A0ull, CVMX_CSR_DB_TYPE_NCB, 32, 545},
|
|
{"USBC0_HCCHAR006" , 0x16F00100005C0ull, CVMX_CSR_DB_TYPE_NCB, 32, 545},
|
|
{"USBC0_HCCHAR007" , 0x16F00100005E0ull, CVMX_CSR_DB_TYPE_NCB, 32, 545},
|
|
{"USBC0_HCFG" , 0x16F0010000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 546},
|
|
{"USBC0_HCINT000" , 0x16F0010000508ull, CVMX_CSR_DB_TYPE_NCB, 32, 547},
|
|
{"USBC0_HCINT001" , 0x16F0010000528ull, CVMX_CSR_DB_TYPE_NCB, 32, 547},
|
|
{"USBC0_HCINT002" , 0x16F0010000548ull, CVMX_CSR_DB_TYPE_NCB, 32, 547},
|
|
{"USBC0_HCINT003" , 0x16F0010000568ull, CVMX_CSR_DB_TYPE_NCB, 32, 547},
|
|
{"USBC0_HCINT004" , 0x16F0010000588ull, CVMX_CSR_DB_TYPE_NCB, 32, 547},
|
|
{"USBC0_HCINT005" , 0x16F00100005A8ull, CVMX_CSR_DB_TYPE_NCB, 32, 547},
|
|
{"USBC0_HCINT006" , 0x16F00100005C8ull, CVMX_CSR_DB_TYPE_NCB, 32, 547},
|
|
{"USBC0_HCINT007" , 0x16F00100005E8ull, CVMX_CSR_DB_TYPE_NCB, 32, 547},
|
|
{"USBC0_HCINTMSK000" , 0x16F001000050Cull, CVMX_CSR_DB_TYPE_NCB, 32, 548},
|
|
{"USBC0_HCINTMSK001" , 0x16F001000052Cull, CVMX_CSR_DB_TYPE_NCB, 32, 548},
|
|
{"USBC0_HCINTMSK002" , 0x16F001000054Cull, CVMX_CSR_DB_TYPE_NCB, 32, 548},
|
|
{"USBC0_HCINTMSK003" , 0x16F001000056Cull, CVMX_CSR_DB_TYPE_NCB, 32, 548},
|
|
{"USBC0_HCINTMSK004" , 0x16F001000058Cull, CVMX_CSR_DB_TYPE_NCB, 32, 548},
|
|
{"USBC0_HCINTMSK005" , 0x16F00100005ACull, CVMX_CSR_DB_TYPE_NCB, 32, 548},
|
|
{"USBC0_HCINTMSK006" , 0x16F00100005CCull, CVMX_CSR_DB_TYPE_NCB, 32, 548},
|
|
{"USBC0_HCINTMSK007" , 0x16F00100005ECull, CVMX_CSR_DB_TYPE_NCB, 32, 548},
|
|
{"USBC0_HCSPLT000" , 0x16F0010000504ull, CVMX_CSR_DB_TYPE_NCB, 32, 549},
|
|
{"USBC0_HCSPLT001" , 0x16F0010000524ull, CVMX_CSR_DB_TYPE_NCB, 32, 549},
|
|
{"USBC0_HCSPLT002" , 0x16F0010000544ull, CVMX_CSR_DB_TYPE_NCB, 32, 549},
|
|
{"USBC0_HCSPLT003" , 0x16F0010000564ull, CVMX_CSR_DB_TYPE_NCB, 32, 549},
|
|
{"USBC0_HCSPLT004" , 0x16F0010000584ull, CVMX_CSR_DB_TYPE_NCB, 32, 549},
|
|
{"USBC0_HCSPLT005" , 0x16F00100005A4ull, CVMX_CSR_DB_TYPE_NCB, 32, 549},
|
|
{"USBC0_HCSPLT006" , 0x16F00100005C4ull, CVMX_CSR_DB_TYPE_NCB, 32, 549},
|
|
{"USBC0_HCSPLT007" , 0x16F00100005E4ull, CVMX_CSR_DB_TYPE_NCB, 32, 549},
|
|
{"USBC0_HCTSIZ000" , 0x16F0010000510ull, CVMX_CSR_DB_TYPE_NCB, 32, 550},
|
|
{"USBC0_HCTSIZ001" , 0x16F0010000530ull, CVMX_CSR_DB_TYPE_NCB, 32, 550},
|
|
{"USBC0_HCTSIZ002" , 0x16F0010000550ull, CVMX_CSR_DB_TYPE_NCB, 32, 550},
|
|
{"USBC0_HCTSIZ003" , 0x16F0010000570ull, CVMX_CSR_DB_TYPE_NCB, 32, 550},
|
|
{"USBC0_HCTSIZ004" , 0x16F0010000590ull, CVMX_CSR_DB_TYPE_NCB, 32, 550},
|
|
{"USBC0_HCTSIZ005" , 0x16F00100005B0ull, CVMX_CSR_DB_TYPE_NCB, 32, 550},
|
|
{"USBC0_HCTSIZ006" , 0x16F00100005D0ull, CVMX_CSR_DB_TYPE_NCB, 32, 550},
|
|
{"USBC0_HCTSIZ007" , 0x16F00100005F0ull, CVMX_CSR_DB_TYPE_NCB, 32, 550},
|
|
{"USBC0_HFIR" , 0x16F0010000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 551},
|
|
{"USBC0_HFNUM" , 0x16F0010000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 552},
|
|
{"USBC0_HPRT" , 0x16F0010000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 553},
|
|
{"USBC0_HPTXFSIZ" , 0x16F0010000100ull, CVMX_CSR_DB_TYPE_NCB, 32, 554},
|
|
{"USBC0_HPTXSTS" , 0x16F0010000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 555},
|
|
{"USBC0_NPTXDFIFO000" , 0x16F0010001000ull, CVMX_CSR_DB_TYPE_NCB, 32, 556},
|
|
{"USBC0_NPTXDFIFO001" , 0x16F0010002000ull, CVMX_CSR_DB_TYPE_NCB, 32, 556},
|
|
{"USBC0_NPTXDFIFO002" , 0x16F0010003000ull, CVMX_CSR_DB_TYPE_NCB, 32, 556},
|
|
{"USBC0_NPTXDFIFO003" , 0x16F0010004000ull, CVMX_CSR_DB_TYPE_NCB, 32, 556},
|
|
{"USBC0_NPTXDFIFO004" , 0x16F0010005000ull, CVMX_CSR_DB_TYPE_NCB, 32, 556},
|
|
{"USBC0_NPTXDFIFO005" , 0x16F0010006000ull, CVMX_CSR_DB_TYPE_NCB, 32, 556},
|
|
{"USBC0_NPTXDFIFO006" , 0x16F0010007000ull, CVMX_CSR_DB_TYPE_NCB, 32, 556},
|
|
{"USBC0_NPTXDFIFO007" , 0x16F0010008000ull, CVMX_CSR_DB_TYPE_NCB, 32, 556},
|
|
{"USBC0_PCGCCTL" , 0x16F0010000E00ull, CVMX_CSR_DB_TYPE_NCB, 32, 557},
|
|
{"USBN0_BIST_STATUS" , 0x11800680007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 558},
|
|
{"USBN0_CLK_CTL" , 0x1180068000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 559},
|
|
{"USBN0_CTL_STATUS" , 0x16F0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 560},
|
|
{"USBN0_DMA0_INB_CHN0" , 0x16F0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 561},
|
|
{"USBN0_DMA0_INB_CHN1" , 0x16F0000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 562},
|
|
{"USBN0_DMA0_INB_CHN2" , 0x16F0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 563},
|
|
{"USBN0_DMA0_INB_CHN3" , 0x16F0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 564},
|
|
{"USBN0_DMA0_INB_CHN4" , 0x16F0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 565},
|
|
{"USBN0_DMA0_INB_CHN5" , 0x16F0000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 566},
|
|
{"USBN0_DMA0_INB_CHN6" , 0x16F0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 567},
|
|
{"USBN0_DMA0_INB_CHN7" , 0x16F0000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 568},
|
|
{"USBN0_DMA0_OUTB_CHN0" , 0x16F0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 569},
|
|
{"USBN0_DMA0_OUTB_CHN1" , 0x16F0000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 570},
|
|
{"USBN0_DMA0_OUTB_CHN2" , 0x16F0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 571},
|
|
{"USBN0_DMA0_OUTB_CHN3" , 0x16F0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 572},
|
|
{"USBN0_DMA0_OUTB_CHN4" , 0x16F0000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 573},
|
|
{"USBN0_DMA0_OUTB_CHN5" , 0x16F0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 574},
|
|
{"USBN0_DMA0_OUTB_CHN6" , 0x16F0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 575},
|
|
{"USBN0_DMA0_OUTB_CHN7" , 0x16F0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 576},
|
|
{"USBN0_DMA_TEST" , 0x16F0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 577},
|
|
{"USBN0_INT_ENB" , 0x1180068000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 578},
|
|
{"USBN0_INT_SUM" , 0x1180068000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 579},
|
|
{"USBN0_USBP_CTL_STATUS" , 0x1180068000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 580},
|
|
{NULL,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn50xx[] = {
|
|
/* name , bit, width, csr, type, rst un, typ un, reset, typical */
|
|
{"SETTING" , 0, 5, 0, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 0, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 1, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 1, "RAZ", 1, 1, 0, 0},
|
|
{"OVRFLW" , 0, 3, 2, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_3_3" , 3, 1, 2, "RAZ", 1, 1, 0, 0},
|
|
{"TXPOP" , 4, 3, 2, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_7_7" , 7, 1, 2, "RAZ", 1, 1, 0, 0},
|
|
{"TXPSH" , 8, 3, 2, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_11_63" , 11, 53, 2, "RAZ", 1, 1, 0, 0},
|
|
{"OVRFLW" , 0, 3, 3, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 3, "RAZ", 1, 1, 0, 0},
|
|
{"TXPOP" , 4, 3, 3, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 3, "RAZ", 1, 1, 0, 0},
|
|
{"TXPSH" , 8, 3, 3, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 3, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 4, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 4, "RAZ", 1, 1, 0, 0},
|
|
{"INT_LOOP" , 0, 3, 5, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 5, "RAZ", 1, 1, 0, 0},
|
|
{"EXT_LOOP" , 4, 3, 5, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 5, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 6, "R/W", 0, 0, 24ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 6, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_EN" , 0, 3, 7, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_3_63" , 3, 61, 7, "RAZ", 1, 1, 0, 0},
|
|
{"SETTING" , 0, 5, 8, "R/W", 0, 0, 24ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 8, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 5, 9, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 9, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL" , 8, 5, 9, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_13_15" , 13, 3, 9, "RAZ", 1, 1, 0, 0},
|
|
{"BYPASS" , 16, 1, 9, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 9, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 3, 10, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 10, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_EN" , 0, 3, 11, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_3_63" , 3, 61, 11, "RAZ", 1, 1, 0, 0},
|
|
{"BIST" , 0, 2, 12, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 12, "RAZ", 1, 1, 0, 0},
|
|
{"DINT" , 0, 2, 13, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 13, "RAZ", 1, 1, 0, 0},
|
|
{"FUSE" , 0, 2, 14, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_2_63" , 2, 62, 14, "RAZ", 1, 1, 0, 0},
|
|
{"GSTOP" , 0, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 15, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWSI" , 45, 1, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_47_47" , 47, 1, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 1, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_49" , 49, 1, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_51_51" , 51, 1, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCM" , 57, 1, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MPI" , 58, 1, 16, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_59_63" , 59, 5, 16, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 2, 17, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 17, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 18, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 18, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 18, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 18, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 18, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 18, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 18, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 18, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 18, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_47_47" , 47, 1, 18, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 1, 18, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_49" , 49, 1, 18, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 18, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_51_51" , 51, 1, 18, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 18, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 18, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCM" , 57, 1, 18, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MPI" , 58, 1, 18, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_59_63" , 59, 5, 18, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 2, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 19, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 20, "RO", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 20, "RO", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 20, "RO", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 20, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 20, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 20, "RO", 0, 0, 0ull, 0ull},
|
|
{"WDOG_SUM" , 44, 1, 20, "RO", 0, 0, 0ull, 0ull},
|
|
{"TWSI" , 45, 1, 20, "RO", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 20, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_47_47" , 47, 1, 20, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_49" , 49, 1, 20, "RAZ", 1, 1, 0, 0},
|
|
{"IPD_DRP" , 50, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_51_51" , 51, 1, 20, "RAZ", 1, 1, 0, 0},
|
|
{"TIMER" , 52, 4, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 20, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCM" , 57, 1, 20, "RO", 0, 0, 0ull, 0ull},
|
|
{"MPI" , 58, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_59_63" , 59, 5, 20, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 21, "RO", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 21, "RO", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 21, "RO", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 21, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 21, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 21, "RO", 0, 0, 0ull, 0ull},
|
|
{"WDOG_SUM" , 44, 1, 21, "RO", 0, 0, 0ull, 0ull},
|
|
{"TWSI" , 45, 1, 21, "RO", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 21, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_47_47" , 47, 1, 21, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_49" , 49, 1, 21, "RAZ", 1, 1, 0, 0},
|
|
{"IPD_DRP" , 50, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_51_51" , 51, 1, 21, "RAZ", 1, 1, 0, 0},
|
|
{"TIMER" , 52, 4, 21, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 21, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCM" , 57, 1, 21, "RO", 0, 0, 0ull, 0ull},
|
|
{"MPI" , 58, 1, 21, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_59_63" , 59, 5, 21, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 2, 22, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 22, "RAZ", 1, 1, 0, 0},
|
|
{"BITS" , 0, 32, 23, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 23, "RAZ", 1, 1, 0, 0},
|
|
{"BITS" , 0, 32, 24, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 24, "RAZ", 1, 1, 0, 0},
|
|
{"NMI" , 0, 2, 25, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 25, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 0, 2, 26, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 26, "RAZ", 1, 1, 0, 0},
|
|
{"PPDBG" , 0, 2, 27, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 27, "RAZ", 1, 1, 0, 0},
|
|
{"POKE" , 0, 64, 28, "RAZ", 1, 1, 0, 0},
|
|
{"RST0" , 0, 1, 29, "R/W", 1, 1, 0, 0},
|
|
{"RST" , 1, 1, 29, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 29, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_BIST" , 0, 1, 30, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 30, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_PRST" , 0, 1, 31, "R/W", 0, 0, 1ull, 0ull},
|
|
{"NPI" , 1, 1, 31, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HOST64" , 2, 1, 31, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 31, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_RST" , 0, 1, 32, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 32, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 36, 33, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ONE_SHOT" , 36, 1, 33, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 33, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 0, 2, 34, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STATE" , 2, 2, 34, "RO", 0, 0, 0ull, 0ull},
|
|
{"LEN" , 4, 16, 34, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 20, 24, 34, "RO", 0, 0, 0ull, 0ull},
|
|
{"DSTOP" , 44, 1, 34, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GSTOPEN" , 45, 1, 34, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_46_63" , 46, 18, 34, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 17, 35, "RO", 0, 1, 0ull, 0},
|
|
{"DSEL_EXT" , 17, 1, 35, "R/W", 0, 0, 1ull, 0ull},
|
|
{"C_MUL" , 18, 5, 35, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_23_27" , 23, 5, 35, "RAZ", 1, 1, 0, 0},
|
|
{"PLL_MUL" , 28, 3, 35, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_31_63" , 31, 33, 35, "RAZ", 1, 1, 0, 0},
|
|
{"FDR" , 0, 1, 36, "RO", 0, 0, 0ull, 0ull},
|
|
{"FFR" , 1, 1, 36, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPF1" , 2, 1, 36, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPF0" , 3, 1, 36, "RO", 0, 0, 0ull, 0ull},
|
|
{"FRD" , 4, 1, 36, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 36, "RAZ", 1, 1, 0, 0},
|
|
{"MEM0_ERR" , 0, 7, 37, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM1_ERR" , 7, 7, 37, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 14, 1, 37, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USE_STT" , 15, 1, 37, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USE_LDT" , 16, 1, 37, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 17, 1, 37, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 37, "RAZ", 1, 1, 0, 0},
|
|
{"FED0_SBE" , 0, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED0_DBE" , 1, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED1_SBE" , 2, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED1_DBE" , 3, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_UND" , 4, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_COFF" , 5, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_PERR" , 6, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_UND" , 7, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_COFF" , 8, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_PERR" , 9, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_UND" , 10, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_COFF" , 11, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_PERR" , 12, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_UND" , 13, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_COFF" , 14, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_PERR" , 15, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_UND" , 16, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_COFF" , 17, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_PERR" , 18, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_UND" , 19, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_COFF" , 20, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_PERR" , 21, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_UND" , 22, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_COFF" , 23, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_PERR" , 24, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_UND" , 25, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_COFF" , 26, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_PERR" , 27, 1, 38, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 38, "RAZ", 1, 1, 0, 0},
|
|
{"FED0_SBE" , 0, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED0_DBE" , 1, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED1_SBE" , 2, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED1_DBE" , 3, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_UND" , 4, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_COFF" , 5, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_PERR" , 6, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_UND" , 7, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_COFF" , 8, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_PERR" , 9, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_UND" , 10, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_COFF" , 11, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_PERR" , 12, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_UND" , 13, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_COFF" , 14, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_PERR" , 15, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_UND" , 16, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_COFF" , 17, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_PERR" , 18, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_UND" , 19, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_COFF" , 20, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_PERR" , 21, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_UND" , 22, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_COFF" , 23, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_PERR" , 24, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_UND" , 25, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_COFF" , 26, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_PERR" , 27, 1, 39, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 39, "RAZ", 1, 1, 0, 0},
|
|
{"QUE_SIZ" , 0, 29, 40, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 40, "RAZ", 1, 1, 0, 0},
|
|
{"PG_NUM" , 0, 25, 41, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 41, "RAZ", 1, 1, 0, 0},
|
|
{"ACT_INDX" , 0, 26, 42, "RO", 0, 1, 0ull, 0},
|
|
{"ACT_QUE" , 26, 3, 42, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 42, "RAZ", 0, 0, 0ull, 7ull},
|
|
{"EXP_INDX" , 0, 26, 43, "RO", 0, 1, 0ull, 0},
|
|
{"EXP_QUE" , 26, 3, 43, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 43, "RAZ", 0, 0, 0ull, 7ull},
|
|
{"CTL" , 0, 16, 44, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 44, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 32, 45, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 45, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 46, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OUT_OVR" , 2, 3, 46, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_21" , 5, 17, 46, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LOSTSTAT" , 22, 3, 46, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_25" , 25, 1, 46, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STATOVR" , 26, 1, 46, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INB_NXA" , 27, 4, 46, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 46, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 12, 47, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 47, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 1, 48, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 1, 1, 48, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P0MII" , 2, 1, 48, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_63" , 3, 61, 48, "RAZ", 1, 1, 0, 0},
|
|
{"PRT" , 0, 6, 49, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 49, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 50, "R/W", 0, 1, 0ull, 0},
|
|
{"SPEED" , 1, 1, 50, "R/W", 0, 1, 1ull, 0},
|
|
{"DUPLEX" , 2, 1, 50, "R/W", 0, 1, 1ull, 0},
|
|
{"SLOTTIME" , 3, 1, 50, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 50, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 64, 51, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 52, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 53, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 54, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 55, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 56, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 0, 8, 57, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 57, "RAZ", 1, 1, 0, 0},
|
|
{"BCST" , 0, 1, 58, "R/W", 0, 1, 1ull, 0},
|
|
{"MCST" , 1, 2, 58, "R/W", 0, 1, 0ull, 0},
|
|
{"CAM_MODE" , 3, 1, 58, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 58, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 5, 59, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_5_63" , 5, 59, 59, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 60, "RAZ", 1, 1, 0, 0},
|
|
{"CAREXT" , 1, 1, 60, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_2" , 2, 1, 60, "RAZ", 1, 1, 0, 0},
|
|
{"JABBER" , 3, 1, 60, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCSERR" , 4, 1, 60, "R/W", 0, 0, 1ull, 1ull},
|
|
{"ALNERR" , 5, 1, 60, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_6" , 6, 1, 60, "RAZ", 1, 1, 0, 0},
|
|
{"RCVERR" , 7, 1, 60, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SKPERR" , 8, 1, 60, "R/W", 0, 0, 1ull, 1ull},
|
|
{"NIBERR" , 9, 1, 60, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_10_63" , 10, 54, 60, "RAZ", 1, 1, 0, 0},
|
|
{"PRE_CHK" , 0, 1, 61, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PRE_STRP" , 1, 1, 61, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_DRP" , 2, 1, 61, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_BCK" , 3, 1, 61, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_MCST" , 4, 1, 61, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_SMAC" , 5, 1, 61, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRE_FREE" , 6, 1, 61, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_7_8" , 7, 2, 61, "RAZ", 1, 1, 0, 0},
|
|
{"PRE_ALIGN" , 9, 1, 61, "R/W", 0, 0, 1ull, 1ull},
|
|
{"NULL_DIS" , 10, 1, 61, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 61, "RAZ", 1, 1, 0, 0},
|
|
{"IFG" , 0, 4, 62, "R/W", 0, 0, 12ull, 12ull},
|
|
{"RESERVED_4_63" , 4, 60, 62, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 63, "RAZ", 1, 1, 0, 0},
|
|
{"CAREXT" , 1, 1, 63, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 63, "RAZ", 1, 1, 0, 0},
|
|
{"JABBER" , 3, 1, 63, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 63, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ALNERR" , 5, 1, 63, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_6" , 6, 1, 63, "RAZ", 1, 1, 0, 0},
|
|
{"RCVERR" , 7, 1, 63, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 63, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NIBERR" , 9, 1, 63, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OVRERR" , 10, 1, 63, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 63, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 63, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 63, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 63, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 63, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHY_LINK" , 16, 1, 63, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHY_SPD" , 17, 1, 63, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHY_DUPX" , 18, 1, 63, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PAUSE_DRP" , 19, 1, 63, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 63, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 64, "RAZ", 1, 1, 0, 0},
|
|
{"CAREXT" , 1, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 64, "RAZ", 1, 1, 0, 0},
|
|
{"JABBER" , 3, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ALNERR" , 5, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_6" , 6, 1, 64, "RAZ", 1, 1, 0, 0},
|
|
{"RCVERR" , 7, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NIBERR" , 9, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OVRERR" , 10, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PHY_LINK" , 16, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PHY_SPD" , 17, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PHY_DUPX" , 18, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PAUSE_DRP" , 19, 1, 64, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 64, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 65, "R/W", 0, 0, 10240ull, 10240ull},
|
|
{"RESERVED_16_63" , 16, 48, 65, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 16, 66, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 66, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 1, 67, "RO", 0, 1, 0ull, 0},
|
|
{"SPEED" , 1, 2, 67, "RO", 0, 1, 0ull, 0},
|
|
{"DUPLEX" , 3, 1, 67, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 67, "RAZ", 1, 1, 0, 0},
|
|
{"RD_CLR" , 0, 1, 68, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 68, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 69, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 69, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 70, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 70, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 71, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 71, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 72, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 72, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 73, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 73, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 74, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 74, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 75, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 75, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 76, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 76, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 77, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 77, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 7, 78, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 78, "RAZ", 1, 1, 0, 0},
|
|
{"FCSSEL" , 8, 1, 78, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 78, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 79, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_6_63" , 6, 58, 79, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 80, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_6_63" , 6, 58, 80, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 9, 81, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_9_63" , 9, 55, 81, "RAZ", 1, 1, 0, 0},
|
|
{"COMMIT" , 0, 3, 82, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_15" , 3, 13, 82, "RAZ", 1, 1, 0, 0},
|
|
{"DROP" , 16, 3, 82, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 82, "RAZ", 1, 1, 0, 0},
|
|
{"PRTS" , 0, 3, 83, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_3_63" , 3, 61, 83, "RAZ", 1, 1, 0, 0},
|
|
{"RX" , 0, 3, 84, "RC", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 84, "RAZ", 1, 1, 0, 0},
|
|
{"TX" , 4, 3, 84, "RC", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 84, "RAZ", 1, 1, 0, 0},
|
|
{"SMAC" , 0, 48, 85, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 85, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 86, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP" , 16, 1, 86, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 86, "RAZ", 1, 1, 0, 0},
|
|
{"PREAMBLE" , 0, 1, 87, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PAD" , 1, 1, 87, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCS" , 2, 1, 87, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FORCE_FCS" , 3, 1, 87, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 87, "RAZ", 1, 1, 0, 0},
|
|
{"BURST" , 0, 16, 88, "R/W", 0, 0, 8192ull, 8192ull},
|
|
{"RESERVED_16_63" , 16, 48, 88, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_CNT" , 0, 6, 89, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_63" , 6, 58, 89, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL_EN" , 0, 1, 90, "R/W", 0, 0, 1ull, 1ull},
|
|
{"XSDEF_EN" , 1, 1, 90, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 90, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_SIZE" , 0, 8, 91, "R/W", 0, 0, 59ull, 59ull},
|
|
{"RESERVED_8_63" , 8, 56, 91, "RAZ", 1, 1, 0, 0},
|
|
{"INTERVAL" , 0, 16, 92, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 92, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 93, "R/W", 0, 1, 96ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 93, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 94, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_16_63" , 16, 48, 94, "RAZ", 1, 1, 0, 0},
|
|
{"SEND" , 0, 1, 95, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 95, "RAZ", 1, 1, 0, 0},
|
|
{"SLOT" , 0, 10, 96, "R/W", 0, 0, 512ull, 512ull},
|
|
{"RESERVED_10_63" , 10, 54, 96, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 97, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 97, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL" , 0, 32, 98, "RC/W", 0, 1, 0ull, 0},
|
|
{"XSDEF" , 32, 32, 98, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCOL" , 0, 32, 99, "RC/W", 0, 1, 0ull, 0},
|
|
{"SCOL" , 32, 32, 99, "RC/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 100, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 100, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 101, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 101, "RAZ", 1, 1, 0, 0},
|
|
{"HIST0" , 0, 32, 102, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST1" , 32, 32, 102, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST2" , 0, 32, 103, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST3" , 32, 32, 103, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST4" , 0, 32, 104, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST5" , 32, 32, 104, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST6" , 0, 32, 105, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST7" , 32, 32, 105, "RC/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 0, 32, 106, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 32, 32, 106, "RC/W", 0, 1, 0ull, 0},
|
|
{"CTL" , 0, 32, 107, "RC/W", 0, 1, 0ull, 0},
|
|
{"UNDFLW" , 32, 32, 107, "RC/W", 0, 1, 0ull, 0},
|
|
{"RD_CLR" , 0, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 108, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 7, 109, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_7_63" , 7, 57, 109, "RAZ", 1, 1, 0, 0},
|
|
{"BP" , 0, 3, 110, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 110, "RAZ", 1, 1, 0, 0},
|
|
{"MSK" , 0, 1, 111, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 111, "RAZ", 1, 1, 0, 0},
|
|
{"LIMIT" , 0, 5, 112, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_5_63" , 5, 59, 112, "RAZ", 1, 1, 0, 0},
|
|
{"CORRUPT" , 0, 3, 113, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_3_63" , 3, 61, 113, "RAZ", 1, 1, 0, 0},
|
|
{"IFG1" , 0, 4, 114, "R/W", 0, 1, 8ull, 0},
|
|
{"IFG2" , 4, 4, 114, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 114, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 115, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 115, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 3, 115, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_7" , 5, 3, 115, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 3, 115, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_11" , 11, 1, 115, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 3, 115, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_15" , 15, 1, 115, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LATE_COL" , 16, 3, 115, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 115, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PKO_NXA" , 0, 1, 116, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 116, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 3, 116, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_7" , 5, 3, 116, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 3, 116, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_11" , 11, 1, 116, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 3, 116, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_15" , 15, 1, 116, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LATE_COL" , 16, 3, 116, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 116, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"JAM" , 0, 8, 117, "R/W", 0, 1, 238ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 117, "RAZ", 1, 1, 0, 0},
|
|
{"LFSR" , 0, 16, 118, "R/W", 0, 1, 65535ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 118, "RAZ", 1, 1, 0, 0},
|
|
{"IGN_FULL" , 0, 3, 119, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 119, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"BP" , 4, 3, 119, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 119, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EN" , 8, 3, 119, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 119, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DMAC" , 0, 48, 120, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
|
|
{"RESERVED_48_63" , 48, 16, 120, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 121, "R/W", 0, 0, 34824ull, 34824ull},
|
|
{"RESERVED_16_63" , 16, 48, 121, "RAZ", 1, 1, 0, 0},
|
|
{"PRTS" , 0, 5, 122, "R/W", 0, 1, 3ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 122, "RAZ", 1, 1, 0, 0},
|
|
{"TX_OE" , 0, 1, 123, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RX_XOR" , 1, 1, 123, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_EN" , 2, 1, 123, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_TYPE" , 3, 1, 123, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_CNT" , 4, 4, 123, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_SEL" , 8, 4, 123, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 123, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 124, "RAZ", 1, 1, 0, 0},
|
|
{"BOOT_ENA" , 8, 4, 124, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_12_63" , 12, 52, 124, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_ENA" , 0, 21, 125, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_63" , 21, 43, 125, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 126, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 126, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 24, 127, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 127, "RAZ", 1, 1, 0, 0},
|
|
{"CLR" , 0, 24, 128, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 128, "RAZ", 1, 1, 0, 0},
|
|
{"SET" , 0, 24, 129, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 129, "RAZ", 1, 1, 0, 0},
|
|
{"TX_OE" , 0, 1, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RX_XOR" , 1, 1, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_3" , 2, 2, 130, "RAZ", 1, 1, 0, 0},
|
|
{"FIL_CNT" , 4, 4, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_SEL" , 8, 4, 130, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 130, "RAZ", 1, 1, 0, 0},
|
|
{"ICD" , 0, 1, 131, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBD" , 1, 1, 131, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRP1" , 2, 1, 131, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRP0" , 3, 1, 131, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRN1" , 4, 1, 131, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRN0" , 5, 1, 131, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBRQ1" , 6, 1, 131, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBRQ0" , 7, 1, 131, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNRT" , 8, 1, 131, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBR1" , 9, 1, 131, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBR0" , 10, 1, 131, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBDR1" , 11, 1, 131, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBDR0" , 12, 1, 131, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNR0" , 13, 1, 131, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNR1" , 14, 1, 131, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICR1" , 15, 1, 131, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICR0" , 16, 1, 131, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNRCB" , 17, 1, 131, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 131, "RAZ", 1, 1, 0, 0},
|
|
{"FAU_END" , 0, 1, 132, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB_ENB" , 1, 1, 132, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PKO_ENB" , 2, 1, 132, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INB_MAT" , 3, 1, 132, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OUTB_MAT" , 4, 1, 132, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 132, "RAZ", 1, 1, 0, 0},
|
|
{"TOUT_VAL" , 0, 12, 133, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TOUT_ENB" , 12, 1, 133, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 133, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 8, 134, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 8, 9, 134, "R/W", 0, 1, 0ull, 0},
|
|
{"OPC" , 17, 4, 134, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 21, 8, 134, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 134, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 8, 135, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 8, 9, 135, "R/W", 0, 1, 0ull, 0},
|
|
{"OPC" , 17, 4, 135, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 21, 8, 135, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 135, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 136, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 137, "R/W", 0, 1, 0ull, 0},
|
|
{"NP_SOP" , 0, 1, 138, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NP_EOP" , 1, 1, 138, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_SOP" , 2, 1, 138, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_EOP" , 3, 1, 138, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NP_DAT" , 4, 1, 138, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_DAT" , 5, 1, 138, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 138, "RAZ", 1, 1, 0, 0},
|
|
{"NP_SOP" , 0, 1, 139, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NP_EOP" , 1, 1, 139, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_SOP" , 2, 1, 139, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_EOP" , 3, 1, 139, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NP_DAT" , 4, 1, 139, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_DAT" , 5, 1, 139, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 139, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 9, 140, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 9, 8, 140, "R/W", 0, 1, 0ull, 0},
|
|
{"EOT" , 17, 1, 140, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 18, 8, 140, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_26_63" , 26, 38, 140, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 9, 141, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 9, 8, 141, "R/W", 0, 1, 0ull, 0},
|
|
{"EOT" , 17, 1, 141, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 18, 8, 141, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_26_63" , 26, 38, 141, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 142, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 143, "R/W", 0, 1, 0ull, 0},
|
|
{"PORT" , 0, 6, 144, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 144, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP_SZ" , 0, 6, 145, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 145, "RAZ", 1, 1, 0, 0},
|
|
{"BACK" , 0, 4, 146, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 146, "RAZ", 1, 1, 0, 0},
|
|
{"BACK" , 0, 4, 147, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 147, "RAZ", 1, 1, 0, 0},
|
|
{"PWP" , 0, 1, 148, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_NEW" , 1, 1, 148, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_OLD" , 2, 1, 148, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRC_OFF" , 3, 1, 148, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ0" , 4, 1, 148, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ1" , 5, 1, 148, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM_WORD" , 6, 1, 148, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM0" , 7, 1, 148, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM1" , 8, 1, 148, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM2" , 9, 1, 148, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM3" , 10, 1, 148, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPQ_PBE0" , 11, 1, 148, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPQ_PBE1" , 12, 1, 148, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_POW" , 13, 1, 148, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_WP1" , 14, 1, 148, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_WQED" , 15, 1, 148, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 148, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_ENB" , 0, 36, 149, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 149, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_CNT" , 0, 64, 150, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_EN" , 0, 1, 151, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OPC_MODE" , 1, 2, 151, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PBP_EN" , 3, 1, 151, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WQE_LEND" , 4, 1, 151, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKT_LEND" , 5, 1, 151, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NADDBUF" , 6, 1, 151, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDPKT" , 7, 1, 151, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 8, 1, 151, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LEN_M8" , 9, 1, 151, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PKT_OFF" , 10, 1, 151, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPD_FULL" , 11, 1, 151, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PQ_NABUF" , 12, 1, 151, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PQ_APKT" , 13, 1, 151, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NO_WPTR" , 14, 1, 151, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 151, "RAZ", 1, 1, 0, 0},
|
|
{"PRC_PAR0" , 0, 1, 152, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR1" , 1, 1, 152, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR2" , 2, 1, 152, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR3" , 3, 1, 152, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_SUB" , 4, 1, 152, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DC_OVR" , 5, 1, 152, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CC_OVR" , 6, 1, 152, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C_COLL" , 7, 1, 152, "R/W", 0, 0, 0ull, 0ull},
|
|
{"D_COLL" , 8, 1, 152, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BC_OVR" , 9, 1, 152, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 152, "RAZ", 1, 1, 0, 0},
|
|
{"PRC_PAR0" , 0, 1, 153, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR1" , 1, 1, 153, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR2" , 2, 1, 153, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR3" , 3, 1, 153, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP_SUB" , 4, 1, 153, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DC_OVR" , 5, 1, 153, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CC_OVR" , 6, 1, 153, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C_COLL" , 7, 1, 153, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"D_COLL" , 8, 1, 153, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BC_OVR" , 9, 1, 153, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 153, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP_SZ" , 0, 6, 154, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 154, "RAZ", 1, 1, 0, 0},
|
|
{"MB_SIZE" , 0, 12, 155, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_12_63" , 12, 52, 155, "RAZ", 1, 1, 0, 0},
|
|
{"PTR" , 0, 29, 156, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 156, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 17, 157, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_ENB" , 17, 1, 157, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 157, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 25, 158, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 158, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 3, 159, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 3, 1, 159, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 4, 29, 159, "RO", 1, 1, 0, 0},
|
|
{"PRADDR" , 33, 3, 159, "RO", 1, 1, 0, 0},
|
|
{"MAX_PKT" , 36, 3, 159, "RO", 0, 0, 5ull, 5ull},
|
|
{"RESERVED_39_63" , 39, 25, 159, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 7, 160, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 7, 1, 160, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 8, 29, 160, "RO", 1, 1, 0, 0},
|
|
{"MAX_PKT" , 37, 7, 160, "RO", 0, 0, 5ull, 5ull},
|
|
{"RESERVED_44_63" , 44, 20, 160, "RAZ", 1, 1, 0, 0},
|
|
{"WQE_PCNT" , 0, 7, 161, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_PCNT" , 7, 7, 161, "RO", 0, 0, 0ull, 0ull},
|
|
{"PFIF_CNT" , 14, 3, 161, "RO", 0, 0, 0ull, 0ull},
|
|
{"WQEV_CNT" , 17, 1, 161, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTV_CNT" , 18, 1, 161, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 161, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 8, 162, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 8, 1, 162, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 9, 29, 162, "RO", 1, 1, 0, 0},
|
|
{"PRADDR" , 38, 8, 162, "RO", 1, 1, 0, 0},
|
|
{"WRADDR" , 46, 8, 162, "RO", 1, 1, 0, 0},
|
|
{"MAX_CNTS" , 54, 7, 162, "RO", 0, 0, 8ull, 8ull},
|
|
{"RESERVED_61_63" , 61, 3, 162, "RAZ", 1, 1, 0, 0},
|
|
{"PASS" , 0, 32, 163, "R/W", 0, 1, 0ull, 0},
|
|
{"DROP" , 32, 32, 163, "R/W", 0, 1, 0ull, 0},
|
|
{"Q0_PCNT" , 0, 32, 164, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 164, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_ENB" , 0, 36, 165, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AVG_DLY" , 36, 14, 165, "R/W", 0, 1, 0ull, 0},
|
|
{"PRB_DLY" , 50, 14, 165, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRB_CON" , 0, 32, 166, "R/W", 0, 1, 0ull, 0},
|
|
{"AVG_CON" , 32, 8, 166, "R/W", 0, 1, 0ull, 0},
|
|
{"NEW_CON" , 40, 8, 166, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_PCNT" , 48, 1, 166, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 166, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 25, 167, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT" , 25, 6, 167, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 167, "RAZ", 1, 1, 0, 0},
|
|
{"PORT_BIT" , 0, 3, 168, "R/W", 0, 0, 7ull, 7ull},
|
|
{"RESERVED_3_63" , 3, 61, 168, "RAZ", 1, 1, 0, 0},
|
|
{"WQE_POOL" , 0, 3, 169, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_3_63" , 3, 61, 169, "RAZ", 1, 1, 0, 0},
|
|
{"PTR" , 0, 29, 170, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 170, "RAZ", 1, 1, 0, 0},
|
|
{"WLB_DAT" , 0, 4, 171, "RO", 0, 0, 0ull, 0ull},
|
|
{"STIN_MSK" , 4, 1, 171, "RO", 0, 0, 0ull, 0ull},
|
|
{"DT" , 5, 1, 171, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTCNT" , 6, 10, 171, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_18" , 16, 3, 171, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WLB_MSK" , 19, 4, 171, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTBNK" , 23, 1, 171, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 171, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"L2T" , 0, 9, 172, "RO", 0, 0, 0ull, 0ull},
|
|
{"VAB_VWCF" , 9, 1, 172, "RO", 0, 0, 0ull, 0ull},
|
|
{"LRF" , 10, 2, 172, "RO", 0, 0, 0ull, 0ull},
|
|
{"VWDF" , 12, 4, 172, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 172, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XRDDAT" , 0, 1, 173, "RO", 0, 0, 0ull, 0ull},
|
|
{"XRDMSK" , 1, 1, 173, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 173, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IPCBST" , 3, 1, 173, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 173, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RMDF" , 8, 4, 173, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRB" , 12, 4, 173, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 173, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LRF_ARB_MODE" , 0, 1, 174, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RFB_ARB_MODE" , 1, 1, 174, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RSP_ARB_MODE" , 2, 1, 174, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MWF_CRD" , 3, 4, 174, "R/W", 0, 0, 2ull, 2ull},
|
|
{"IDXALIAS" , 7, 1, 174, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPEN" , 8, 1, 174, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FPEMPTY" , 9, 1, 174, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FPEXP" , 10, 4, 174, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_17" , 14, 4, 174, "RAZ", 1, 1, 0, 0},
|
|
{"LBIST" , 18, 1, 174, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BSTRUN" , 19, 1, 174, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 174, "RAZ", 1, 1, 0, 0},
|
|
{"L2T" , 0, 1, 175, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2D" , 1, 1, 175, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FINV" , 2, 1, 175, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SET" , 3, 3, 175, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PPNUM" , 6, 1, 175, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_9" , 7, 3, 175, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_DMP" , 10, 1, 175, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LFB_ENUM" , 11, 3, 175, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 175, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DT_TAG" , 0, 29, 176, "RO", 0, 0, 0ull, 0ull},
|
|
{"DT_VLD" , 29, 1, 176, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_30" , 30, 1, 176, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DTENA" , 31, 1, 176, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 176, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_ENA" , 0, 1, 177, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_3" , 1, 3, 177, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_BASE" , 4, 27, 177, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 177, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_OFFSET" , 0, 10, 178, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 178, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VLD" , 0, 1, 179, "RO", 0, 0, 0ull, 0ull},
|
|
{"CMD" , 1, 4, 179, "RO", 0, 0, 0ull, 0ull},
|
|
{"SID" , 5, 9, 179, "RO", 0, 0, 0ull, 0ull},
|
|
{"VABNUM" , 14, 3, 179, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_17" , 17, 1, 179, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SET" , 18, 3, 179, "RO", 0, 0, 0ull, 0ull},
|
|
{"IHD" , 21, 1, 179, "RO", 0, 0, 0ull, 0ull},
|
|
{"ITL" , 22, 1, 179, "RO", 0, 0, 0ull, 0ull},
|
|
{"INXT" , 23, 3, 179, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_26" , 26, 1, 179, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VAM" , 27, 1, 179, "RO", 0, 0, 0ull, 0ull},
|
|
{"STCFL" , 28, 1, 179, "RO", 0, 0, 0ull, 0ull},
|
|
{"STINV" , 29, 1, 179, "RO", 0, 0, 0ull, 0ull},
|
|
{"STPND" , 30, 1, 179, "RO", 0, 0, 0ull, 0ull},
|
|
{"STCPND" , 31, 1, 179, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 179, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VLD" , 0, 1, 180, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTPRB" , 1, 1, 180, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRBRTY" , 2, 1, 180, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTMFL" , 3, 1, 180, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTVTM" , 4, 1, 180, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTRSC" , 5, 1, 180, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTRSP" , 6, 1, 180, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTDT" , 7, 1, 180, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTRDA" , 8, 1, 180, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTM" , 9, 1, 180, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWRM" , 10, 1, 180, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWHF" , 11, 1, 180, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWHP" , 12, 1, 180, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTDQ" , 13, 1, 180, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTDW" , 14, 1, 180, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTRSP" , 15, 1, 180, "RO", 0, 0, 0ull, 0ull},
|
|
{"BID" , 16, 2, 180, "RO", 0, 0, 0ull, 0ull},
|
|
{"DSGOING" , 18, 1, 180, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 180, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_IDX" , 0, 7, 181, "RO", 0, 0, 0ull, 0ull},
|
|
{"LFB_TAG" , 7, 20, 181, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_63" , 27, 37, 181, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_HWM" , 0, 3, 182, "R/W", 0, 0, 7ull, 7ull},
|
|
{"RESERVED_3_3" , 3, 1, 182, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STPARTDIS" , 4, 1, 182, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 182, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PFCNT0" , 0, 36, 183, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 183, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT0SEL" , 0, 6, 184, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0CLR" , 6, 1, 184, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0ENA" , 7, 1, 184, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1SEL" , 8, 6, 184, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1CLR" , 14, 1, 184, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1ENA" , 15, 1, 184, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2SEL" , 16, 6, 184, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2CLR" , 22, 1, 184, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2ENA" , 23, 1, 184, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3SEL" , 24, 6, 184, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3CLR" , 30, 1, 184, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3ENA" , 31, 1, 184, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0RDCLR" , 32, 1, 184, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1RDCLR" , 33, 1, 184, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2RDCLR" , 34, 1, 184, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3RDCLR" , 35, 1, 184, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 184, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK0" , 0, 8, 185, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK1" , 8, 8, 185, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 185, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSKIOB" , 0, 8, 186, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 186, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q0STAT" , 0, 34, 187, "RO", 0, 0, 0ull, 0ull},
|
|
{"FTL" , 34, 1, 187, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_35_63" , 35, 29, 187, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q1STAT" , 0, 34, 188, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 188, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q2STAT" , 0, 34, 189, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 189, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q3STAT" , 0, 34, 190, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 190, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 0, 1, 191, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_INTENA" , 1, 1, 191, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DED_INTENA" , 2, 1, 191, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 3, 1, 191, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 4, 1, 191, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BMHCLSEL" , 5, 1, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 191, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 0, 8, 192, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_10" , 8, 3, 192, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSET" , 11, 3, 192, "RO", 0, 0, 0ull, 0ull},
|
|
{"FOWMSK" , 14, 4, 192, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 192, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW0" , 0, 10, 193, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW1" , 10, 10, 193, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 193, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW2" , 0, 10, 194, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW3" , 10, 10, 194, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 194, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q0FUS" , 0, 34, 195, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 195, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q1FUS" , 0, 34, 196, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 196, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q2FUS" , 0, 34, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 197, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q3FUS" , 0, 34, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRIP_64K" , 34, 1, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRIP_32K" , 35, 1, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_36" , 36, 1, 198, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EMA_CTL" , 37, 3, 198, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 198, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 0, 1, 199, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_INTENA" , 1, 1, 199, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DED_INTENA" , 2, 1, 199, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 3, 1, 199, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 4, 1, 199, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FSYN" , 5, 6, 199, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 11, 7, 199, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_20" , 18, 3, 199, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSET" , 21, 3, 199, "RO", 0, 0, 0ull, 0ull},
|
|
{"LCKERR" , 24, 1, 199, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK_INTENA" , 25, 1, 199, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LCKERR2" , 26, 1, 199, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK_INTENA2" , 27, 1, 199, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_28_63" , 28, 36, 199, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"START" , 0, 1, 200, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 200, "RAZ", 1, 0, 0, 0ull},
|
|
{"MRD" , 0, 3, 201, "RO", 1, 0, 0, 0ull},
|
|
{"MRF" , 3, 1, 201, "RO", 1, 0, 0, 0ull},
|
|
{"MWC" , 4, 1, 201, "RO", 1, 0, 0, 0ull},
|
|
{"MWD" , 5, 3, 201, "RO", 1, 0, 0, 0ull},
|
|
{"MWF" , 8, 1, 201, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 201, "RAZ", 1, 0, 0, 0ull},
|
|
{"PCTL_DAT" , 0, 5, 202, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_11" , 5, 7, 202, "RAZ", 0, 1, 0ull, 0},
|
|
{"PCTL_CSR" , 12, 4, 202, "R/W", 0, 1, 15ull, 0},
|
|
{"NCTL_DAT" , 16, 4, 202, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_27" , 20, 8, 202, "RAZ", 0, 1, 0ull, 0},
|
|
{"NCTL_CSR" , 28, 4, 202, "R/W", 0, 1, 15ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 202, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DIC" , 0, 2, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QS_DIC" , 2, 2, 203, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TSKW" , 4, 2, 203, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SIL_LAT" , 6, 2, 203, "R/W", 0, 0, 1ull, 1ull},
|
|
{"BPRCH" , 8, 1, 203, "R/W", 0, 1, 0ull, 0},
|
|
{"FPRCH2" , 9, 1, 203, "R/W", 0, 0, 0ull, 1ull},
|
|
{"MODE32B" , 10, 1, 203, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DRESET" , 11, 1, 203, "R/W", 0, 0, 1ull, 0ull},
|
|
{"INORDER_MRF" , 12, 1, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INORDER_MWF" , 13, 1, 203, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"R2R_SLOT" , 14, 1, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RDIMM_ENA" , 15, 1, 203, "R/W", 0, 1, 0ull, 0},
|
|
{"PLL_BYPASS" , 16, 1, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_17" , 17, 1, 203, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX_WRITE_BATCH" , 18, 4, 203, "R/W", 0, 0, 8ull, 8ull},
|
|
{"XOR_BANK" , 22, 1, 203, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SLOW_SCF" , 23, 1, 203, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DDR__PCTL" , 24, 4, 203, "RO", 1, 1, 0, 0},
|
|
{"DDR__NCTL" , 28, 4, 203, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 203, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_LAYOUT" , 0, 2, 204, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_7" , 2, 6, 204, "RAZ", 0, 1, 0ull, 0},
|
|
{"DCC_ENABLE" , 8, 1, 204, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SIL_MODE" , 9, 1, 204, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_10_63" , 10, 54, 204, "RAZ", 1, 1, 0, 0},
|
|
{"DCLKCNT_HI" , 0, 32, 205, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 205, "RAZ", 1, 1, 0, 0},
|
|
{"DCLKCNT_LO" , 0, 32, 206, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 206, "RAZ", 1, 1, 0, 0},
|
|
{"DDR2" , 0, 1, 207, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RDQS" , 1, 1, 207, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLL90_BYP" , 2, 1, 207, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLL90_VLU" , 3, 5, 207, "R/W", 0, 1, 0ull, 0},
|
|
{"QDLL_ENA" , 8, 1, 207, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ODT_ENA" , 9, 1, 207, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DDR2T" , 10, 1, 207, "R/W", 0, 1, 0ull, 0},
|
|
{"CRIP_MODE" , 11, 1, 207, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TFAW" , 12, 5, 207, "R/W", 0, 0, 0ull, 9ull},
|
|
{"DDR_EOF" , 17, 4, 207, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SILO_HC" , 21, 1, 207, "R/W", 0, 1, 1ull, 0},
|
|
{"TWR" , 22, 3, 207, "R/W", 0, 0, 3ull, 1ull},
|
|
{"BWCNT" , 25, 1, 207, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POCAS" , 26, 1, 207, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDLAT" , 27, 3, 207, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BURST8" , 30, 1, 207, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BANK8" , 31, 1, 207, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 207, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CLK" , 0, 4, 208, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_4" , 4, 1, 208, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CMD" , 5, 4, 208, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 208, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DQ" , 10, 4, 208, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 208, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CS_MASK" , 0, 8, 209, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_15" , 8, 8, 209, "RAZ", 0, 1, 0ull, 0},
|
|
{"ROW_LSB" , 16, 3, 209, "R/W", 0, 1, 3ull, 0},
|
|
{"BANK8" , 19, 1, 209, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_63" , 20, 44, 209, "RAZ", 0, 1, 0ull, 0},
|
|
{"MRDSYN0" , 0, 8, 210, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN1" , 8, 8, 210, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN2" , 16, 8, 210, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN3" , 24, 8, 210, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 210, "RAZ", 1, 1, 0, 0},
|
|
{"FCOL" , 0, 12, 211, "RO", 0, 0, 0ull, 0ull},
|
|
{"FROW" , 12, 14, 211, "RO", 0, 0, 0ull, 0ull},
|
|
{"FBANK" , 26, 3, 211, "RO", 0, 0, 0ull, 0ull},
|
|
{"FBUNK" , 29, 1, 211, "RO", 0, 0, 0ull, 0ull},
|
|
{"FDIMM" , 30, 2, 211, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 211, "RAZ", 1, 1, 0, 0},
|
|
{"IFBCNT_HI" , 0, 32, 212, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 212, "RAZ", 1, 1, 0, 0},
|
|
{"IFBCNT_LO" , 0, 32, 213, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 213, "RAZ", 1, 1, 0, 0},
|
|
{"INIT_START" , 0, 1, 214, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 1, 1, 214, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ROW_LSB" , 2, 3, 214, "R/W", 0, 1, 3ull, 0},
|
|
{"PBANK_LSB" , 5, 4, 214, "R/W", 0, 1, 5ull, 0},
|
|
{"REF_INT" , 9, 6, 214, "R/W", 0, 0, 1ull, 2ull},
|
|
{"TCL" , 15, 4, 214, "R/W", 0, 1, 3ull, 0},
|
|
{"INTR_SEC_ENA" , 19, 1, 214, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INTR_DED_ENA" , 20, 1, 214, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 21, 4, 214, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 25, 4, 214, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BUNK_ENA" , 29, 1, 214, "R/W", 0, 1, 0ull, 0},
|
|
{"SILO_QC" , 30, 1, 214, "R/W", 0, 1, 0ull, 0},
|
|
{"RESET" , 31, 1, 214, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 214, "RAZ", 1, 1, 0, 0},
|
|
{"TRAS" , 0, 5, 215, "R/W", 0, 0, 12ull, 12ull},
|
|
{"TRCD" , 5, 4, 215, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TWTR" , 9, 4, 215, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TRP" , 13, 4, 215, "R/W", 0, 0, 5ull, 4ull},
|
|
{"TRFC" , 17, 5, 215, "R/W", 0, 0, 6ull, 7ull},
|
|
{"TMRD" , 22, 3, 215, "R/W", 0, 0, 2ull, 2ull},
|
|
{"CASLAT" , 25, 3, 215, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TRRD" , 28, 3, 215, "R/W", 0, 0, 2ull, 2ull},
|
|
{"COMP_BYPASS" , 31, 1, 215, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 215, "RAZ", 1, 1, 0, 0},
|
|
{"OPSCNT_HI" , 0, 32, 216, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 216, "RAZ", 1, 1, 0, 0},
|
|
{"OPSCNT_LO" , 0, 32, 217, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 217, "RAZ", 1, 1, 0, 0},
|
|
{"EN2" , 0, 1, 218, "R/W", 0, 1, 0ull, 0},
|
|
{"EN4" , 1, 1, 218, "R/W", 0, 1, 0ull, 0},
|
|
{"EN6" , 2, 1, 218, "R/W", 0, 1, 0ull, 0},
|
|
{"EN8" , 3, 1, 218, "R/W", 0, 1, 1ull, 0},
|
|
{"EN12" , 4, 1, 218, "R/W", 0, 1, 0ull, 0},
|
|
{"EN16" , 5, 1, 218, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_7" , 6, 2, 218, "RAZ", 0, 1, 0ull, 0},
|
|
{"CLKR" , 8, 6, 218, "R/W", 0, 1, 0ull, 0},
|
|
{"CLKF" , 14, 12, 218, "R/W", 0, 1, 31ull, 0},
|
|
{"RESET_N" , 26, 1, 218, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DIV_RESET" , 27, 1, 218, "R/W", 0, 0, 1ull, 0ull},
|
|
{"FASTEN_N" , 28, 1, 218, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 218, "RAZ", 0, 1, 0ull, 0},
|
|
{"FBSLIP" , 0, 1, 219, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RFSLIP" , 1, 1, 219, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_21" , 2, 20, 219, "RAZ", 1, 1, 0, 0},
|
|
{"DDR__PCTL" , 22, 5, 219, "RO", 1, 1, 0, 0},
|
|
{"DDR__NCTL" , 27, 5, 219, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 219, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL" , 0, 5, 220, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 220, "RAZ", 0, 1, 0ull, 0},
|
|
{"NCTL" , 8, 4, 220, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_12_15" , 12, 4, 220, "RAZ", 0, 1, 0ull, 0},
|
|
{"ENABLE" , 16, 1, 220, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_17_63" , 17, 47, 220, "RAZ", 0, 1, 0ull, 0},
|
|
{"RODT_LO0" , 0, 4, 221, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_LO1" , 4, 4, 221, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_LO2" , 8, 4, 221, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_LO3" , 12, 4, 221, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI0" , 16, 4, 221, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI1" , 20, 4, 221, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI2" , 24, 4, 221, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI3" , 28, 4, 221, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_32_63" , 32, 32, 221, "RAZ", 1, 1, 0, 0},
|
|
{"WODT_LO0" , 0, 4, 222, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_LO1" , 4, 4, 222, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_LO2" , 8, 4, 222, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_LO3" , 12, 4, 222, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_HI0" , 16, 4, 222, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_HI1" , 20, 4, 222, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_HI2" , 24, 4, 222, "R/W", 0, 0, 15ull, 15ull},
|
|
{"WODT_HI3" , 28, 4, 222, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_32_63" , 32, 32, 222, "RAZ", 1, 1, 0, 0},
|
|
{"NCBI" , 0, 1, 223, "RO", 0, 0, 0ull, 0ull},
|
|
{"LOC" , 1, 1, 223, "RO", 0, 0, 0ull, 0ull},
|
|
{"NCBO_0" , 2, 1, 223, "RO", 0, 0, 0ull, 0ull},
|
|
{"NCBO_1" , 3, 1, 223, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCM_0" , 4, 1, 223, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCM_1" , 5, 1, 223, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 223, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 5, 224, "R/W", 0, 1, 31ull, 0},
|
|
{"PCTL" , 5, 5, 224, "R/W", 0, 1, 31ull, 0},
|
|
{"RESERVED_10_63" , 10, 54, 224, "RAZ", 1, 1, 0, 0},
|
|
{"ADR_ERR" , 0, 1, 225, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WAIT_ERR" , 1, 1, 225, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 225, "RAZ", 1, 1, 0, 0},
|
|
{"ADR_INT" , 0, 1, 226, "R/W", 0, 1, 0ull, 0},
|
|
{"WAIT_INT" , 1, 1, 226, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 226, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 227, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 3, 5, 227, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 227, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 228, "RAZ", 1, 1, 0, 0},
|
|
{"BASE" , 3, 25, 228, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_30" , 28, 3, 228, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 31, 1, 228, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 228, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 229, "R/W", 1, 1, 0, 0},
|
|
{"BASE" , 0, 16, 230, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 16, 12, 230, "R/W", 0, 1, 0ull, 0},
|
|
{"WIDTH" , 28, 1, 230, "R/W", 0, 1, 0ull, 0},
|
|
{"ALE" , 29, 1, 230, "R/W", 0, 1, 0ull, 0},
|
|
{"ORBIT" , 30, 1, 230, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 31, 1, 230, "R/W", 0, 1, 0ull, 0},
|
|
{"OE_EXT" , 32, 2, 230, "R/W", 0, 1, 0ull, 0},
|
|
{"WE_EXT" , 34, 2, 230, "R/W", 0, 1, 0ull, 0},
|
|
{"SAM" , 36, 1, 230, "R/W", 0, 1, 0ull, 0},
|
|
{"RD_DLY" , 37, 3, 230, "R/W", 0, 1, 0ull, 0},
|
|
{"TIM_MULT" , 40, 2, 230, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_42_63" , 42, 22, 230, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 6, 231, "R/W", 0, 1, 63ull, 0},
|
|
{"CE" , 6, 6, 231, "R/W", 0, 1, 63ull, 0},
|
|
{"OE" , 12, 6, 231, "R/W", 0, 1, 63ull, 0},
|
|
{"WE" , 18, 6, 231, "R/W", 0, 1, 63ull, 0},
|
|
{"RD_HLD" , 24, 6, 231, "R/W", 0, 1, 63ull, 0},
|
|
{"WR_HLD" , 30, 6, 231, "R/W", 0, 1, 63ull, 0},
|
|
{"PAUSE" , 36, 6, 231, "R/W", 0, 1, 63ull, 0},
|
|
{"WAIT" , 42, 6, 231, "R/W", 0, 1, 63ull, 0},
|
|
{"PAGE" , 48, 6, 231, "R/W", 0, 1, 63ull, 0},
|
|
{"ALE" , 54, 6, 231, "R/W", 0, 1, 63ull, 0},
|
|
{"PAGES" , 60, 2, 231, "R/W", 0, 1, 0ull, 0},
|
|
{"WAITM" , 62, 1, 231, "R/W", 0, 1, 0ull, 0},
|
|
{"PAGEM" , 63, 1, 231, "R/W", 0, 1, 0ull, 0},
|
|
{"FIF_THR" , 0, 6, 232, "R/W", 0, 0, 26ull, 26ull},
|
|
{"RESERVED_6_7" , 6, 2, 232, "RAZ", 1, 1, 0, 0},
|
|
{"FIF_CNT" , 8, 6, 232, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_63" , 14, 50, 232, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 64, 233, "R/W", 1, 1, 0, 0},
|
|
{"MAN_INFO" , 0, 32, 234, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 234, "RAZ", 1, 1, 0, 0},
|
|
{"MAN_INFO" , 0, 32, 235, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 235, "RAZ", 1, 1, 0, 0},
|
|
{"PP_DIS" , 0, 2, 236, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_2_15" , 2, 14, 236, "RAZ", 1, 1, 0, 0},
|
|
{"CHIP_ID" , 16, 8, 236, "RO", 1, 1, 0, 0},
|
|
{"BIST_DIS" , 24, 1, 236, "RO", 1, 1, 0, 0},
|
|
{"RST_SHT" , 25, 1, 236, "RO", 1, 1, 0, 0},
|
|
{"NOCRYPTO" , 26, 1, 236, "RO", 1, 1, 0, 0},
|
|
{"NOMUL" , 27, 1, 236, "RO", 1, 1, 0, 0},
|
|
{"NODFA_CP2" , 28, 1, 236, "RO", 0, 0, 1ull, 1ull},
|
|
{"NOKASU" , 29, 1, 236, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_30_31" , 30, 2, 236, "RAZ", 1, 1, 0, 0},
|
|
{"RAID_EN" , 32, 1, 236, "RO", 0, 0, 0ull, 0ull},
|
|
{"FUS318" , 33, 1, 236, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_34_63" , 34, 30, 236, "RAZ", 1, 1, 0, 0},
|
|
{"ICACHE" , 0, 24, 237, "RO", 1, 1, 0, 0},
|
|
{"NODFA_DTE" , 24, 1, 237, "RO", 0, 0, 1ull, 1ull},
|
|
{"NOZIP" , 25, 1, 237, "RO", 0, 0, 1ull, 1ull},
|
|
{"EFUS_IGN" , 26, 1, 237, "RO", 1, 1, 0, 0},
|
|
{"EFUS_LCK" , 27, 1, 237, "RO", 1, 1, 0, 0},
|
|
{"BAR2_EN" , 28, 1, 237, "RO", 1, 1, 0, 0},
|
|
{"ZIP_CRIP" , 29, 2, 237, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_31_63" , 31, 33, 237, "RAZ", 1, 1, 0, 0},
|
|
{"EMA" , 0, 3, 238, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 238, "RAZ", 1, 1, 0, 0},
|
|
{"EFF_EMA" , 4, 3, 238, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 238, "RAZ", 1, 1, 0, 0},
|
|
{"PDF" , 0, 64, 239, "RO", 1, 1, 0, 0},
|
|
{"FBSLIP" , 0, 1, 240, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RFSLIP" , 1, 1, 240, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 240, "RAZ", 1, 1, 0, 0},
|
|
{"PROG" , 0, 1, 241, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_1_63" , 1, 63, 241, "RAZ", 1, 1, 0, 0},
|
|
{"SETUP" , 0, 8, 242, "R/W", 0, 1, 3ull, 0},
|
|
{"SCLK_HI" , 8, 12, 242, "R/W", 0, 1, 100ull, 0},
|
|
{"SCLK_LO" , 20, 4, 242, "R/W", 0, 1, 2ull, 0},
|
|
{"OUT" , 24, 8, 242, "R/W", 0, 1, 3ull, 0},
|
|
{"PROG_PIN" , 32, 1, 242, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_33_63" , 33, 31, 242, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 7, 243, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 243, "RAZ", 1, 1, 0, 0},
|
|
{"EFUSE" , 8, 1, 243, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 243, "RAZ", 1, 1, 0, 0},
|
|
{"PEND" , 12, 1, 243, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 243, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 16, 8, 243, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_24_63" , 24, 40, 243, "RAZ", 1, 1, 0, 0},
|
|
{"REPAIR0" , 0, 14, 244, "RO", 0, 0, 0ull, 0ull},
|
|
{"REPAIR1" , 14, 14, 244, "RO", 0, 0, 0ull, 0ull},
|
|
{"REPAIR2" , 28, 14, 244, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_42_63" , 42, 22, 244, "RAZ", 1, 1, 0, 0},
|
|
{"TOO_MANY" , 0, 1, 245, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 245, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 2, 246, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_2_63" , 2, 62, 246, "RAZ", 1, 1, 0, 0},
|
|
{"ST_INT" , 0, 1, 247, "R/W1C", 0, 1, 0ull, 0},
|
|
{"TS_INT" , 1, 1, 247, "R/W1C", 0, 1, 0ull, 0},
|
|
{"CORE_INT" , 2, 1, 247, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_3" , 3, 1, 247, "RAZ", 1, 1, 0, 0},
|
|
{"ST_EN" , 4, 1, 247, "R/W", 0, 1, 0ull, 0},
|
|
{"TS_EN" , 5, 1, 247, "R/W", 0, 1, 0ull, 0},
|
|
{"CORE_EN" , 6, 1, 247, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_7" , 7, 1, 247, "RAZ", 1, 1, 0, 0},
|
|
{"SDA_OVR" , 8, 1, 247, "R/W", 0, 1, 0ull, 0},
|
|
{"SCL_OVR" , 9, 1, 247, "R/W", 0, 1, 0ull, 0},
|
|
{"SDA" , 10, 1, 247, "RO", 1, 1, 0, 0},
|
|
{"SCL" , 11, 1, 247, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_12_63" , 12, 52, 247, "RAZ", 1, 1, 0, 0},
|
|
{"D" , 0, 32, 248, "R/W", 0, 1, 0ull, 0},
|
|
{"EOP_IA" , 32, 3, 248, "R/W", 0, 1, 0ull, 0},
|
|
{"IA" , 35, 5, 248, "R/W", 0, 1, 0ull, 0},
|
|
{"A" , 40, 10, 248, "R/W", 0, 1, 0ull, 0},
|
|
{"SCR" , 50, 2, 248, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 52, 3, 248, "R/W", 0, 1, 0ull, 0},
|
|
{"SOVR" , 55, 1, 248, "R/W", 0, 1, 0ull, 0},
|
|
{"R" , 56, 1, 248, "R/W", 0, 1, 0ull, 0},
|
|
{"OP" , 57, 4, 248, "R/W", 0, 1, 0ull, 0},
|
|
{"EIA" , 61, 1, 248, "R/W", 0, 1, 0ull, 0},
|
|
{"SLONLY" , 62, 1, 248, "R/W", 0, 1, 0ull, 0},
|
|
{"V" , 63, 1, 248, "RC/W", 0, 1, 0ull, 0},
|
|
{"D" , 0, 32, 249, "R/W", 0, 1, 0ull, 0},
|
|
{"IA" , 32, 8, 249, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_40_63" , 40, 24, 249, "RAZ", 1, 1, 0, 0},
|
|
{"D" , 0, 32, 250, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_32_61" , 32, 30, 250, "RAZ", 1, 1, 0, 0},
|
|
{"V" , 62, 2, 250, "RC/W", 0, 1, 0ull, 0},
|
|
{"DLH" , 0, 8, 251, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 251, "RAZ", 1, 1, 0, 0},
|
|
{"DLL" , 0, 8, 252, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 252, "RAZ", 1, 1, 0, 0},
|
|
{"FAR" , 0, 1, 253, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 253, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 254, "WO", 0, 1, 0ull, 0},
|
|
{"RXFR" , 1, 1, 254, "WO", 0, 1, 0ull, 0},
|
|
{"TXFR" , 2, 1, 254, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_3" , 3, 1, 254, "RAZ", 0, 1, 0ull, 0},
|
|
{"TXTRIG" , 4, 2, 254, "WO", 0, 1, 0ull, 0},
|
|
{"RXTRIG" , 6, 2, 254, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 254, "RAZ", 1, 1, 0, 0},
|
|
{"HTX" , 0, 1, 255, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 255, "RAZ", 1, 1, 0, 0},
|
|
{"ERBFI" , 0, 1, 256, "R/W", 0, 1, 0ull, 0},
|
|
{"ETBEI" , 1, 1, 256, "R/W", 0, 1, 0ull, 0},
|
|
{"ELSI" , 2, 1, 256, "R/W", 0, 1, 0ull, 0},
|
|
{"EDSSI" , 3, 1, 256, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_6" , 4, 3, 256, "RAZ", 0, 1, 0ull, 0},
|
|
{"PTIME" , 7, 1, 256, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 256, "RAZ", 1, 1, 0, 0},
|
|
{"IID" , 0, 4, 257, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_4_5" , 4, 2, 257, "RAZ", 0, 1, 0ull, 0},
|
|
{"FEN" , 6, 2, 257, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 257, "RAZ", 1, 1, 0, 0},
|
|
{"CLS" , 0, 2, 258, "R/W", 0, 1, 0ull, 0},
|
|
{"STOP" , 2, 1, 258, "R/W", 0, 1, 0ull, 0},
|
|
{"PEN" , 3, 1, 258, "R/W", 0, 1, 0ull, 0},
|
|
{"EPS" , 4, 1, 258, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_5" , 5, 1, 258, "RAZ", 0, 1, 0ull, 0},
|
|
{"BRK" , 6, 1, 258, "R/W", 0, 1, 0ull, 0},
|
|
{"DLAB" , 7, 1, 258, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 258, "RAZ", 1, 1, 0, 0},
|
|
{"DR" , 0, 1, 259, "RO", 0, 1, 0ull, 0},
|
|
{"OE" , 1, 1, 259, "RC", 0, 1, 0ull, 0},
|
|
{"PE" , 2, 1, 259, "RC", 0, 1, 0ull, 0},
|
|
{"FE" , 3, 1, 259, "RC", 0, 1, 0ull, 0},
|
|
{"BI" , 4, 1, 259, "RC", 0, 1, 0ull, 0},
|
|
{"THRE" , 5, 1, 259, "RO", 0, 1, 1ull, 0},
|
|
{"TEMT" , 6, 1, 259, "RO", 0, 1, 1ull, 0},
|
|
{"FERR" , 7, 1, 259, "RC", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 259, "RAZ", 1, 1, 0, 0},
|
|
{"DTR" , 0, 1, 260, "R/W", 0, 1, 0ull, 0},
|
|
{"RTS" , 1, 1, 260, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT1" , 2, 1, 260, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT2" , 3, 1, 260, "R/W", 0, 1, 0ull, 0},
|
|
{"LOOP" , 4, 1, 260, "R/W", 0, 1, 0ull, 0},
|
|
{"AFCE" , 5, 1, 260, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 260, "RAZ", 0, 1, 0ull, 0},
|
|
{"DCTS" , 0, 1, 261, "RC", 0, 1, 0ull, 0},
|
|
{"DDSR" , 1, 1, 261, "RC", 0, 1, 0ull, 0},
|
|
{"TERI" , 2, 1, 261, "RC", 0, 1, 0ull, 0},
|
|
{"DDCD" , 3, 1, 261, "RC", 0, 1, 0ull, 0},
|
|
{"CTS" , 4, 1, 261, "RO", 1, 1, 0, 0},
|
|
{"DSR" , 5, 1, 261, "RO", 0, 1, 0ull, 0},
|
|
{"RI" , 6, 1, 261, "RO", 0, 1, 0ull, 0},
|
|
{"DCD" , 7, 1, 261, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 261, "RAZ", 1, 1, 0, 0},
|
|
{"RBR" , 0, 8, 262, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 262, "RAZ", 1, 1, 0, 0},
|
|
{"RFL" , 0, 7, 263, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 263, "RAZ", 1, 1, 0, 0},
|
|
{"RFWD" , 0, 8, 264, "WO", 0, 1, 0ull, 0},
|
|
{"RFPE" , 8, 1, 264, "WO", 0, 1, 0ull, 0},
|
|
{"RFFE" , 9, 1, 264, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_10_63" , 10, 54, 264, "RAZ", 1, 1, 0, 0},
|
|
{"SBCR" , 0, 1, 265, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 265, "RAZ", 1, 1, 0, 0},
|
|
{"SCR" , 0, 8, 266, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 266, "RAZ", 1, 1, 0, 0},
|
|
{"SFE" , 0, 1, 267, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 267, "RAZ", 1, 1, 0, 0},
|
|
{"USR" , 0, 1, 268, "WO", 0, 1, 0ull, 0},
|
|
{"SRFR" , 1, 1, 268, "WO", 0, 1, 0ull, 0},
|
|
{"STFR" , 2, 1, 268, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_63" , 3, 61, 268, "RAZ", 1, 1, 0, 0},
|
|
{"SRT" , 0, 2, 269, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 269, "RAZ", 1, 1, 0, 0},
|
|
{"SRTS" , 0, 1, 270, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 270, "RAZ", 1, 1, 0, 0},
|
|
{"STT" , 0, 2, 271, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 271, "RAZ", 1, 1, 0, 0},
|
|
{"TFL" , 0, 7, 272, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 272, "RAZ", 1, 1, 0, 0},
|
|
{"TFR" , 0, 8, 273, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 273, "RAZ", 1, 1, 0, 0},
|
|
{"THR" , 0, 8, 274, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 274, "RAZ", 1, 1, 0, 0},
|
|
{"BUSY" , 0, 1, 275, "RO", 0, 1, 0ull, 0},
|
|
{"TFNF" , 1, 1, 275, "RO", 0, 1, 1ull, 0},
|
|
{"TFE" , 2, 1, 275, "RO", 0, 1, 1ull, 0},
|
|
{"RFNE" , 3, 1, 275, "RO", 0, 1, 0ull, 0},
|
|
{"RFF" , 4, 1, 275, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 275, "RAZ", 1, 1, 0, 0},
|
|
{"ENABLE" , 0, 1, 276, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDLELO" , 1, 1, 276, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLK_CONT" , 2, 1, 276, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WIREOR" , 3, 1, 276, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LSBFIRST" , 4, 1, 276, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_ENA" , 5, 1, 276, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CSENA" , 6, 1, 276, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CSHI" , 7, 1, 276, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDLECLKS" , 8, 2, 276, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRITX" , 10, 1, 276, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CSLATE" , 11, 1, 276, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_15" , 12, 4, 276, "RAZ", 1, 1, 0, 0},
|
|
{"CLKDIV" , 16, 13, 276, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 276, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 8, 277, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_8_63" , 8, 56, 277, "RAZ", 1, 1, 0, 0},
|
|
{"BUSY" , 0, 1, 278, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_7" , 1, 7, 278, "RAZ", 1, 1, 0, 0},
|
|
{"RXNUM" , 8, 5, 278, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 278, "RAZ", 1, 1, 0, 0},
|
|
{"TOTNUM" , 0, 5, 279, "WO", 1, 0, 0, 2ull},
|
|
{"RESERVED_5_7" , 5, 3, 279, "RAZ", 1, 1, 0, 0},
|
|
{"TXNUM" , 8, 5, 279, "WO", 1, 0, 0, 1ull},
|
|
{"RESERVED_13_15" , 13, 3, 279, "RAZ", 1, 1, 0, 0},
|
|
{"LEAVECS" , 16, 1, 279, "WO", 1, 0, 0, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 279, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 280, "RAZ", 1, 1, 0, 0},
|
|
{"BADDR" , 3, 61, 280, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_0_2" , 0, 3, 281, "RAZ", 1, 1, 0, 0},
|
|
{"BADDR" , 3, 61, 281, "R/W", 0, 1, 0ull, 0},
|
|
{"DPI_BS" , 0, 1, 282, "RO", 0, 0, 0ull, 0ull},
|
|
{"PDF_BS" , 1, 1, 282, "RO", 0, 0, 0ull, 0ull},
|
|
{"DOB_BS" , 2, 1, 282, "RO", 0, 0, 0ull, 0ull},
|
|
{"NUS_BS" , 3, 1, 282, "RO", 0, 0, 0ull, 0ull},
|
|
{"POS_BS" , 4, 1, 282, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_6" , 5, 2, 282, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"POF1_BS" , 7, 1, 282, "RO", 0, 0, 0ull, 0ull},
|
|
{"POF0_BS" , 8, 1, 282, "RO", 0, 0, 0ull, 0ull},
|
|
{"PIG_BS" , 9, 1, 282, "RO", 0, 0, 0ull, 0ull},
|
|
{"PGF_BS" , 10, 1, 282, "RO", 0, 0, 0ull, 0ull},
|
|
{"RDNL_BS" , 11, 1, 282, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCAD_BS" , 12, 1, 282, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCAC_BS" , 13, 1, 282, "RO", 0, 0, 0ull, 0ull},
|
|
{"RDN_BS" , 14, 1, 282, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCN_BS" , 15, 1, 282, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCNC_BS" , 16, 1, 282, "RO", 0, 0, 0ull, 0ull},
|
|
{"RDP_BS" , 17, 1, 282, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF_BS" , 18, 1, 282, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSR_BS" , 19, 1, 282, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 282, "RAZ", 1, 1, 0, 0},
|
|
{"BSIZE" , 0, 16, 283, "R/W", 0, 1, 1024ull, 0},
|
|
{"ISIZE" , 16, 7, 283, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_23_63" , 23, 41, 283, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 5, 284, "R/W", 0, 1, 16ull, 0},
|
|
{"PCTL" , 5, 5, 284, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_10_63" , 10, 54, 284, "RAZ", 1, 1, 0, 0},
|
|
{"TIMER" , 0, 10, 285, "R/W", 0, 0, 0ull, 50ull},
|
|
{"RESERVED_10_31" , 10, 22, 285, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX_WORD" , 32, 5, 285, "R/W", 0, 0, 2ull, 0ull},
|
|
{"RESERVED_37_39" , 37, 3, 285, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WAIT_COM" , 40, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCI_WDIS" , 41, 1, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INS0_64B" , 42, 1, 285, "R/W", 0, 1, 0ull, 0},
|
|
{"INS1_64B" , 43, 1, 285, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_45" , 44, 2, 285, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"INS0_ENB" , 46, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INS1_ENB" , 47, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_48_49" , 48, 2, 285, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OUT0_ENB" , 50, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OUT1_ENB" , 51, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_52_53" , 52, 2, 285, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DIS_PNIW" , 54, 1, 285, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CHIP_REV" , 55, 8, 285, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_63_63" , 63, 1, 285, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_SEL" , 0, 16, 286, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 286, "RAZ", 1, 1, 0, 0},
|
|
{"CSIZE" , 0, 14, 287, "R/W", 0, 1, 0ull, 0},
|
|
{"LP_ENB" , 14, 1, 287, "R/W", 0, 0, 0ull, 1ull},
|
|
{"HP_ENB" , 15, 1, 287, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O_MODE" , 16, 1, 287, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O_ES" , 17, 2, 287, "R/W", 0, 1, 0ull, 0},
|
|
{"O_NS" , 19, 1, 287, "R/W", 0, 1, 0ull, 0},
|
|
{"O_RO" , 20, 1, 287, "R/W", 0, 1, 0ull, 0},
|
|
{"O_ADD1" , 21, 1, 287, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA_QUE" , 22, 3, 287, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB_ICHK" , 25, 9, 287, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB_DENB" , 34, 1, 287, "R/W", 0, 0, 0ull, 1ull},
|
|
{"B0_LEND" , 35, 1, 287, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 287, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 32, 288, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 7, 288, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_39_63" , 39, 25, 288, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 289, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 36, 4, 289, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 289, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 32, 290, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 7, 290, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_39_63" , 39, 25, 290, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 291, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 36, 4, 291, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 291, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 16, 292, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 292, "RAZ", 1, 1, 0, 0},
|
|
{"SADDR" , 0, 36, 293, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 293, "RAZ", 1, 1, 0, 0},
|
|
{"ROR" , 0, 1, 294, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR" , 1, 2, 294, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR" , 3, 1, 294, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_CSR" , 4, 1, 294, "R/W", 0, 0, 0ull, 1ull},
|
|
{"D_ROR" , 5, 1, 294, "R/W", 0, 1, 0ull, 0},
|
|
{"D_ESR" , 6, 2, 294, "R/W", 0, 1, 0ull, 0},
|
|
{"D_NSR" , 8, 1, 294, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP_DHI" , 9, 13, 294, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_RR" , 22, 1, 294, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 294, "RAZ", 1, 1, 0, 0},
|
|
{"RML_RTO" , 0, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RML_WTO" , 1, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCI_RSL" , 2, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PO0_2SML" , 3, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PO1_2SML" , 4, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_5_6" , 5, 2, 295, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"I0_RTOUT" , 7, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I1_RTOUT" , 8, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_9_10" , 9, 2, 295, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"I0_OVERF" , 11, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I1_OVERF" , 12, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_13_14" , 13, 2, 295, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"P0_RTOUT" , 15, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_RTOUT" , 16, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_17_18" , 17, 2, 295, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"P0_PERR" , 19, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_PERR" , 20, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_21_22" , 21, 2, 295, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"G0_RTOUT" , 23, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"G1_RTOUT" , 24, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_25_26" , 25, 2, 295, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"P0_PPERR" , 27, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_PPERR" , 28, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_29_30" , 29, 2, 295, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"P0_PTOUT" , 31, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_PTOUT" , 32, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_33_34" , 33, 2, 295, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"I0_PPERR" , 35, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I1_PPERR" , 36, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_37_38" , 37, 2, 295, "RAZ", 0, 0, 0ull, 1ull},
|
|
{"WIN_RTO" , 39, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P_DPERR" , 40, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 41, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FCR_S_E" , 42, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FCR_A_F" , 43, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCR_S_E" , 44, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCR_A_F" , 45, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q2_S_E" , 46, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q2_A_F" , 47, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q3_S_E" , 48, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q3_A_F" , 49, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"COM_S_E" , 50, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"COM_A_F" , 51, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PNC_S_E" , 52, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PNC_A_F" , 53, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RWX_S_E" , 54, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RDX_S_E" , 55, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCF_P_E" , 56, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCF_P_F" , 57, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PDF_P_E" , 58, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PDF_P_F" , 59, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q1_S_E" , 60, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"Q1_A_F" , 61, 1, 295, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_62_63" , 62, 2, 295, "RAZ", 1, 1, 0, 0},
|
|
{"RML_RTO" , 0, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RML_WTO" , 1, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCI_RSL" , 2, 1, 296, "RO", 0, 0, 0ull, 0ull},
|
|
{"PO0_2SML" , 3, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PO1_2SML" , 4, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_6" , 5, 2, 296, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"I0_RTOUT" , 7, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I1_RTOUT" , 8, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_10" , 9, 2, 296, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"I0_OVERF" , 11, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I1_OVERF" , 12, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_14" , 13, 2, 296, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"P0_RTOUT" , 15, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_RTOUT" , 16, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_18" , 17, 2, 296, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"P0_PERR" , 19, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_PERR" , 20, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_22" , 21, 2, 296, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"G0_RTOUT" , 23, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"G1_RTOUT" , 24, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_26" , 25, 2, 296, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"P0_PPERR" , 27, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_PPERR" , 28, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_30" , 29, 2, 296, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"P0_PTOUT" , 31, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_PTOUT" , 32, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_33_34" , 33, 2, 296, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"I0_PPERR" , 35, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I1_PPERR" , 36, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_38" , 37, 2, 296, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WIN_RTO" , 39, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_DPERR" , 40, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IOBDMA" , 41, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCR_S_E" , 42, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCR_A_F" , 43, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCR_S_E" , 44, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCR_A_F" , 45, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_S_E" , 46, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_A_F" , 47, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_S_E" , 48, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_A_F" , 49, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COM_S_E" , 50, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COM_A_F" , 51, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PNC_S_E" , 52, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PNC_A_F" , 53, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RWX_S_E" , 54, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RDX_S_E" , 55, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCF_P_E" , 56, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCF_P_F" , 57, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PDF_P_E" , 58, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PDF_P_F" , 59, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_S_E" , 60, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_A_F" , 61, 1, 296, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_62_63" , 62, 2, 296, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 16, 297, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 297, "RAZ", 1, 1, 0, 0},
|
|
{"SADDR" , 0, 36, 298, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 298, "RAZ", 1, 1, 0, 0},
|
|
{"BA" , 0, 28, 299, "R/W", 0, 1, 0ull, 0},
|
|
{"ROW" , 28, 1, 299, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR" , 29, 1, 299, "R/W", 0, 1, 0ull, 0},
|
|
{"NSW" , 30, 1, 299, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR" , 31, 1, 299, "R/W", 0, 1, 0ull, 0},
|
|
{"ESW" , 32, 2, 299, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR" , 34, 2, 299, "R/W", 0, 1, 0ull, 0},
|
|
{"NMERGE" , 36, 1, 299, "R/W", 0, 1, 0ull, 0},
|
|
{"SHORTL" , 37, 1, 299, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_38_63" , 38, 26, 299, "RAZ", 1, 1, 0, 0},
|
|
{"INT_VEC" , 0, 64, 300, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 0, 32, 301, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 301, "RAZ", 1, 1, 0, 0},
|
|
{"ROR_SL0" , 0, 1, 302, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR_SL0" , 1, 1, 302, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR_SL0" , 2, 2, 302, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR_SL1" , 4, 1, 302, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR_SL1" , 5, 1, 302, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR_SL1" , 6, 2, 302, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_15" , 8, 8, 302, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IPTR_O0" , 16, 1, 302, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IPTR_O1" , 17, 1, 302, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_18_23" , 18, 6, 302, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"O0_CSRM" , 24, 1, 302, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O1_CSRM" , 25, 1, 302, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_26_27" , 26, 2, 302, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"O0_RO" , 28, 1, 302, "R/W", 0, 1, 0ull, 0},
|
|
{"O0_NS" , 29, 1, 302, "R/W", 0, 1, 0ull, 0},
|
|
{"O0_ES" , 30, 2, 302, "R/W", 0, 1, 0ull, 0},
|
|
{"O1_RO" , 32, 1, 302, "R/W", 0, 1, 0ull, 0},
|
|
{"O1_NS" , 33, 1, 302, "R/W", 0, 1, 0ull, 0},
|
|
{"O1_ES" , 34, 2, 302, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_43" , 36, 8, 302, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"P0_BMODE" , 44, 1, 302, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P1_BMODE" , 45, 1, 302, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_46_47" , 46, 2, 302, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PKT_RR" , 48, 1, 302, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 302, "RAZ", 1, 1, 0, 0},
|
|
{"NADDR" , 0, 61, 303, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 61, 2, 303, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_63_63" , 63, 1, 303, "RAZ", 1, 1, 0, 0},
|
|
{"NADDR" , 0, 61, 304, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 61, 3, 304, "RO", 0, 0, 0ull, 0ull},
|
|
{"AVAIL" , 0, 32, 305, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 6, 305, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 305, "RAZ", 1, 1, 0, 0},
|
|
{"AVAIL" , 0, 32, 306, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 5, 306, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 306, "RAZ", 1, 1, 0, 0},
|
|
{"RD_BRST" , 0, 7, 307, "R/W", 0, 0, 17ull, 64ull},
|
|
{"WR_BRST" , 7, 7, 307, "R/W", 0, 0, 16ull, 64ull},
|
|
{"RESERVED_14_63" , 14, 50, 307, "RAZ", 1, 1, 0, 0},
|
|
{"PARK_DEV" , 0, 3, 308, "R/W", 0, 1, 0ull, 0},
|
|
{"PARK_MOD" , 3, 1, 308, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 4, 1, 308, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 308, "RAZ", 1, 1, 0, 0},
|
|
{"PCI_OVR" , 8, 4, 308, "R/W", 0, 1, 0ull, 0},
|
|
{"HOSTMODE" , 12, 1, 308, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_13_63" , 13, 51, 308, "RAZ", 1, 1, 0, 0},
|
|
{"CMD_SIZE" , 0, 11, 309, "R/W", 0, 0, 9ull, 9ull},
|
|
{"RESERVED_11_63" , 11, 53, 309, "RAZ", 1, 1, 0, 0},
|
|
{"RSV_A" , 0, 6, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"SKP_LEN" , 6, 7, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_B" , 13, 1, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"PAR_MODE" , 14, 2, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_C" , 16, 5, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_IHDR" , 21, 1, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_D" , 22, 6, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"RSKP_LEN" , 28, 7, 310, "R/W", 0, 1, 8ull, 0},
|
|
{"RSV_E" , 35, 1, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"RPARMODE" , 36, 2, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_F" , 38, 5, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP" , 43, 1, 310, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 310, "RAZ", 1, 1, 0, 0},
|
|
{"RSV_A" , 0, 6, 311, "R/W", 0, 1, 0ull, 0},
|
|
{"SKP_LEN" , 6, 7, 311, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_B" , 13, 1, 311, "R/W", 0, 1, 0ull, 0},
|
|
{"PAR_MODE" , 14, 2, 311, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_C" , 16, 5, 311, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_IHDR" , 21, 1, 311, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_D" , 22, 6, 311, "R/W", 0, 1, 0ull, 0},
|
|
{"RSKP_LEN" , 28, 7, 311, "R/W", 0, 1, 8ull, 0},
|
|
{"RSV_E" , 35, 1, 311, "R/W", 0, 1, 0ull, 0},
|
|
{"RPARMODE" , 36, 2, 311, "R/W", 0, 1, 0ull, 0},
|
|
{"RSV_F" , 38, 5, 311, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP" , 43, 1, 311, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 311, "RAZ", 1, 1, 0, 0},
|
|
{"ENB" , 0, 4, 312, "R/W", 0, 0, 15ull, 15ull},
|
|
{"BP_ON" , 4, 4, 312, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 312, "RAZ", 1, 1, 0, 0},
|
|
{"MIO" , 0, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX0" , 1, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX1" , 2, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPI" , 3, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"KEY" , 4, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPA" , 5, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"DFA" , 6, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"ZIP" , 7, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_8" , 8, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD" , 9, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 10, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"TIM" , 11, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"POW" , 12, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"USB" , 13, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"RAD" , 14, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_15" , 15, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"L2C" , 16, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"LMC" , 17, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"SPX0" , 18, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"SPX1" , 19, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"PIP" , 20, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_21" , 21, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASX0" , 22, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASX1" , 23, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_27" , 24, 4, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"AGL" , 28, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"LMC1" , 29, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"IOB" , 30, 1, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 0, 32, 314, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 314, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 32, 315, "R/W", 0, 0, 0ull, 131072ull},
|
|
{"RESERVED_32_63" , 32, 32, 315, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR_V" , 0, 1, 316, "R/W", 0, 1, 0ull, 0},
|
|
{"END_SWP" , 1, 2, 316, "R/W", 0, 1, 0ull, 0},
|
|
{"CA" , 3, 1, 316, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDR_IDX" , 4, 14, 316, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_31" , 18, 14, 316, "RAZ", 1, 1, 0, 0},
|
|
{"DBG2N_BS" , 0, 1, 317, "RO", 0, 0, 0ull, 0ull},
|
|
{"DAT2N_BS" , 1, 1, 317, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSR2N_BS" , 2, 1, 317, "RO", 0, 0, 0ull, 0ull},
|
|
{"RSP2P_BS" , 3, 1, 317, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSRR_BS" , 4, 1, 317, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSR2P_BS" , 5, 1, 317, "RO", 0, 0, 0ull, 0ull},
|
|
{"CMD_BS" , 6, 1, 317, "RO", 0, 0, 0ull, 0ull},
|
|
{"CMD0_BS" , 7, 1, 317, "RO", 0, 0, 0ull, 0ull},
|
|
{"DMA0_BS" , 8, 1, 317, "RO", 0, 0, 0ull, 0ull},
|
|
{"RSP_BS" , 9, 1, 317, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 317, "RAZ", 1, 1, 0, 0},
|
|
{"VENDID" , 0, 16, 318, "RO", 0, 0, 6013ull, 6013ull},
|
|
{"DEVID" , 16, 16, 318, "RO", 0, 0, 112ull, 32ull},
|
|
{"ISAE" , 0, 1, 319, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSAE" , 1, 1, 319, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ME" , 2, 1, 319, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SCSE" , 3, 1, 319, "RO", 0, 0, 0ull, 0ull},
|
|
{"MWICE" , 4, 1, 319, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VPS" , 5, 1, 319, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEE" , 6, 1, 319, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ADS" , 7, 1, 319, "RO", 0, 0, 0ull, 0ull},
|
|
{"SEE" , 8, 1, 319, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FBBE" , 9, 1, 319, "R/W", 0, 0, 0ull, 1ull},
|
|
{"I_DIS" , 10, 1, 319, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_18" , 11, 8, 319, "RAZ", 1, 1, 0, 0},
|
|
{"I_STAT" , 19, 1, 319, "RO", 0, 0, 0ull, 0ull},
|
|
{"CLE" , 20, 1, 319, "RO", 0, 0, 1ull, 1ull},
|
|
{"M66" , 21, 1, 319, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_22_22" , 22, 1, 319, "RAZ", 1, 1, 0, 0},
|
|
{"FBB" , 23, 1, 319, "RO", 0, 1, 1ull, 0},
|
|
{"MDPE" , 24, 1, 319, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DEVT" , 25, 2, 319, "RO", 0, 0, 1ull, 1ull},
|
|
{"STA" , 27, 1, 319, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTA" , 28, 1, 319, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RMA" , 29, 1, 319, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SSE" , 30, 1, 319, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPE" , 31, 1, 319, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RID" , 0, 8, 320, "RO", 0, 0, 0ull, 0ull},
|
|
{"CC" , 8, 24, 320, "RO", 0, 0, 733184ull, 733184ull},
|
|
{"CLS" , 0, 8, 321, "R/W", 0, 1, 0ull, 0},
|
|
{"LT" , 8, 8, 321, "R/W", 0, 0, 0ull, 64ull},
|
|
{"HT" , 16, 8, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCOD" , 24, 4, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_29" , 28, 2, 321, "RAZ", 1, 1, 0, 0},
|
|
{"BRB" , 30, 1, 321, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BCAP" , 31, 1, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSPC" , 0, 1, 322, "RO", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 322, "RO", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 322, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBASEZ" , 4, 8, 322, "RO", 0, 0, 0ull, 0ull},
|
|
{"LBASE" , 12, 20, 322, "R/W", 0, 1, 0ull, 0},
|
|
{"HBASE" , 0, 32, 323, "R/W", 0, 1, 0ull, 0},
|
|
{"MSPC" , 0, 1, 324, "RO", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 324, "RO", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 324, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBASEZ" , 4, 23, 324, "RO", 0, 0, 0ull, 0ull},
|
|
{"LBASE" , 27, 5, 324, "R/W", 0, 1, 0ull, 0},
|
|
{"HBASE" , 0, 32, 325, "R/W", 0, 1, 0ull, 0},
|
|
{"MSPC" , 0, 1, 326, "RO", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 326, "RO", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 326, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBASEZ" , 4, 28, 326, "RO", 0, 0, 0ull, 0ull},
|
|
{"HBASEZ" , 0, 7, 327, "RO", 0, 0, 0ull, 0ull},
|
|
{"HBASE" , 7, 25, 327, "R/W", 0, 1, 0ull, 0},
|
|
{"CISP" , 0, 32, 328, "RO", 0, 0, 0ull, 0ull},
|
|
{"SSVID" , 0, 16, 329, "RO", 0, 0, 6013ull, 6013ull},
|
|
{"SSID" , 16, 16, 329, "RO", 0, 0, 1ull, 1ull},
|
|
{"ERBAR_EN" , 0, 1, 330, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_10" , 1, 10, 330, "RAZ", 1, 1, 0, 0},
|
|
{"ERBARZ" , 11, 5, 330, "RO", 0, 0, 0ull, 0ull},
|
|
{"ERBAR" , 16, 16, 330, "R/W", 0, 1, 0ull, 0},
|
|
{"CP" , 0, 8, 331, "RO", 0, 0, 224ull, 224ull},
|
|
{"RESERVED_8_31" , 8, 24, 331, "RAZ", 1, 1, 0, 0},
|
|
{"IL" , 0, 8, 332, "R/W", 0, 1, 0ull, 0},
|
|
{"INTA" , 8, 8, 332, "RO", 0, 0, 1ull, 1ull},
|
|
{"MG" , 16, 8, 332, "RO", 0, 0, 64ull, 64ull},
|
|
{"ML" , 24, 8, 332, "RO", 0, 0, 64ull, 64ull},
|
|
{"MLTD" , 0, 1, 333, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TSWC" , 1, 1, 333, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 333, "RAZ", 1, 1, 0, 0},
|
|
{"DPPMR" , 3, 1, 333, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PBE" , 4, 12, 333, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TILT" , 16, 4, 333, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TSLTE" , 20, 3, 333, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TMAE" , 23, 1, 333, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWTAE" , 24, 1, 333, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWSEN" , 25, 1, 333, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWSEI" , 26, 1, 333, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRTAE" , 27, 1, 333, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRDRS" , 28, 1, 333, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RDSATI" , 29, 1, 333, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRDARD" , 30, 1, 333, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TRDNPR" , 31, 1, 333, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TSCME" , 0, 32, 334, "R/W1C", 0, 1, 0ull, 0},
|
|
{"TDSRPS" , 0, 32, 335, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TDOMC" , 0, 5, 336, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TIDOMC" , 5, 1, 336, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_6" , 6, 1, 336, "RAZ", 1, 1, 0, 0},
|
|
{"TIBDE" , 7, 1, 336, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIBCD" , 8, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_10" , 9, 2, 336, "RAZ", 1, 1, 0, 0},
|
|
{"TMAPES" , 11, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TMDPES" , 12, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TMSE" , 13, 1, 336, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TMEI" , 14, 1, 336, "RO", 0, 0, 0ull, 0ull},
|
|
{"TECI" , 15, 1, 336, "RO", 0, 0, 0ull, 0ull},
|
|
{"TMES" , 16, 8, 336, "RO", 0, 0, 0ull, 0ull},
|
|
{"MDRRMC" , 24, 3, 336, "R/W", 0, 0, 2ull, 2ull},
|
|
{"MDRIMC" , 27, 1, 336, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MDRE" , 28, 1, 336, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MDWE" , 29, 1, 336, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRBCI" , 30, 1, 336, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRBCM" , 31, 1, 336, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MDSP" , 0, 32, 337, "R/W1C", 0, 1, 0ull, 0},
|
|
{"SCMRE" , 0, 32, 338, "R/W1C", 0, 1, 0ull, 0},
|
|
{"MTTV" , 0, 8, 339, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRV" , 8, 8, 339, "R/W", 0, 0, 0ull, 255ull},
|
|
{"MTTA" , 16, 1, 339, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRA" , 17, 1, 339, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FLUSH" , 18, 1, 339, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_19_24" , 19, 6, 339, "RAZ", 1, 1, 0, 0},
|
|
{"MAC" , 25, 7, 339, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PXCID" , 0, 8, 340, "RO", 0, 0, 7ull, 7ull},
|
|
{"NCP" , 8, 8, 340, "RO", 0, 0, 232ull, 232ull},
|
|
{"DPERE" , 16, 1, 340, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROE" , 17, 1, 340, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MMBC" , 18, 2, 340, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MOST" , 20, 3, 340, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_23_31" , 23, 9, 340, "RAZ", 1, 1, 0, 0},
|
|
{"FN" , 0, 3, 341, "RO", 0, 0, 0ull, 0ull},
|
|
{"DN" , 3, 5, 341, "RO", 0, 0, 31ull, 31ull},
|
|
{"BN" , 8, 8, 341, "RO", 0, 1, 17ull, 0},
|
|
{"W64" , 16, 1, 341, "RO", 0, 0, 1ull, 1ull},
|
|
{"M133" , 17, 1, 341, "RO", 0, 0, 1ull, 1ull},
|
|
{"SCD" , 18, 1, 341, "R/W1C", 0, 1, 0ull, 0},
|
|
{"USC" , 19, 1, 341, "R/W1C", 0, 1, 0ull, 0},
|
|
{"DC" , 20, 1, 341, "RO", 0, 0, 0ull, 0ull},
|
|
{"MMRBCD" , 21, 2, 341, "RO", 0, 0, 2ull, 2ull},
|
|
{"MOSTD" , 23, 3, 341, "RO", 0, 0, 3ull, 3ull},
|
|
{"MCRSD" , 26, 3, 341, "RO", 0, 0, 7ull, 7ull},
|
|
{"SCEMR" , 29, 1, 341, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_30_31" , 30, 2, 341, "RAZ", 1, 1, 0, 0},
|
|
{"PMCID" , 0, 8, 342, "RO", 0, 0, 1ull, 1ull},
|
|
{"NCP" , 8, 8, 342, "RO", 0, 0, 240ull, 240ull},
|
|
{"PCIMIV" , 16, 3, 342, "RO", 0, 0, 2ull, 2ull},
|
|
{"PMEC" , 19, 1, 342, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 342, "RAZ", 1, 1, 0, 0},
|
|
{"DSI" , 21, 1, 342, "RO", 0, 0, 0ull, 0ull},
|
|
{"AUXC" , 22, 3, 342, "RO", 0, 0, 0ull, 0ull},
|
|
{"D1S" , 25, 1, 342, "RO", 0, 0, 0ull, 0ull},
|
|
{"D2S" , 26, 1, 342, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMES" , 27, 5, 342, "RO", 0, 0, 0ull, 0ull},
|
|
{"PS" , 0, 2, 343, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_7" , 2, 6, 343, "RAZ", 1, 1, 0, 0},
|
|
{"PMEENS" , 8, 1, 343, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMDS" , 9, 4, 343, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMEDSIA" , 13, 2, 343, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMESS" , 15, 1, 343, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_21" , 16, 6, 343, "RAZ", 1, 1, 0, 0},
|
|
{"BD3H" , 22, 1, 343, "RO", 0, 0, 0ull, 0ull},
|
|
{"BPCCEN" , 23, 1, 343, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMDIA" , 24, 8, 343, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSICID" , 0, 8, 344, "RO", 0, 0, 5ull, 5ull},
|
|
{"NCP" , 8, 8, 344, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSIEN" , 16, 1, 344, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MMC" , 17, 3, 344, "RO", 0, 0, 0ull, 0ull},
|
|
{"MME" , 20, 3, 344, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M64" , 23, 1, 344, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_24_31" , 24, 8, 344, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 345, "RAZ", 1, 1, 0, 0},
|
|
{"MSI31T2" , 2, 30, 345, "R/W", 0, 1, 0ull, 0},
|
|
{"MSI" , 0, 32, 346, "R/W", 0, 1, 0ull, 0},
|
|
{"MSIMD" , 0, 16, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_31" , 16, 16, 347, "RAZ", 1, 1, 0, 0},
|
|
{"PCICNT" , 0, 32, 348, "R/W", 0, 1, 0ull, 0},
|
|
{"AP_SPEED" , 32, 2, 348, "RO", 1, 1, 0, 0},
|
|
{"AP_PCIX" , 34, 1, 348, "RO", 1, 1, 0, 0},
|
|
{"HM_SPEED" , 35, 2, 348, "RO", 0, 1, 0ull, 0},
|
|
{"HM_PCIX" , 37, 1, 348, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_38_63" , 38, 26, 348, "RAZ", 1, 1, 0, 0},
|
|
{"BAR2_CAX" , 0, 1, 349, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAR2_ESX" , 1, 2, 349, "R/W", 0, 1, 0ull, 0},
|
|
{"BAR2_ENB" , 3, 1, 349, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TSR_HWM" , 4, 3, 349, "R/W", 0, 1, 1ull, 0},
|
|
{"PMO_FPC" , 7, 3, 349, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMO_AMOD" , 10, 1, 349, "R/W", 0, 0, 0ull, 0ull},
|
|
{"B12_BIST" , 11, 1, 349, "RO", 0, 0, 0ull, 0ull},
|
|
{"AP_64AD" , 12, 1, 349, "RO", 0, 1, 0ull, 0},
|
|
{"AP_PCIX" , 13, 1, 349, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_14" , 14, 1, 349, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EN_WFILT" , 15, 1, 349, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SCM" , 16, 1, 349, "RO", 0, 1, 0ull, 0},
|
|
{"SCMTYP" , 17, 1, 349, "RO", 0, 1, 0ull, 0},
|
|
{"BAR2PRES" , 18, 1, 349, "R/W", 1, 1, 0, 0},
|
|
{"ERST_N" , 19, 1, 349, "RO", 0, 0, 1ull, 1ull},
|
|
{"BB0" , 20, 1, 349, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB1" , 21, 1, 349, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB_ES" , 22, 2, 349, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB_CA" , 24, 1, 349, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB1_SIZ" , 25, 1, 349, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BB1_HOLE" , 26, 3, 349, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_31" , 29, 3, 349, "RAZ", 1, 1, 0, 0},
|
|
{"INC_VAL" , 0, 16, 350, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_31" , 16, 16, 350, "RAZ", 1, 1, 0, 0},
|
|
{"DMA_CNT" , 0, 32, 351, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKT_CNT" , 0, 32, 352, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA_TIME" , 0, 32, 353, "R/W", 0, 1, 0ull, 0},
|
|
{"ICNT" , 0, 32, 354, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ITR_WABT" , 0, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_WABT" , 1, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_WTTO" , 2, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"ITR_ABT" , 3, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_ABT" , 4, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"IMR_TTO" , 5, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSI_PER" , 6, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSI_TABT" , 7, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSI_MABT" , 8, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"IMSC_MSG" , 9, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"ITSR_ABT" , 10, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"ISERR" , 11, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"IAPERR" , 12, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"IDPERR" , 13, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RWR" , 14, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RRD" , 15, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"IRSL_INT" , 16, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"IPCNT0" , 17, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"IPCNT1" , 18, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_19_20" , 19, 2, 355, "RAZ", 0, 1, 0ull, 0},
|
|
{"IPTIME0" , 21, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"IPTIME1" , 22, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_23_24" , 23, 2, 355, "RAZ", 0, 1, 0ull, 0},
|
|
{"IDCNT0" , 25, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"IDCNT1" , 26, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"IDTIME0" , 27, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"IDTIME1" , 28, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA0_FI" , 29, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA1_FI" , 30, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"WIN_WR" , 31, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_WR" , 32, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RD" , 33, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_34_63" , 34, 30, 355, "RAZ", 1, 1, 0, 0},
|
|
{"RTR_WABT" , 0, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_WABT" , 1, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_WTTO" , 2, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RTR_ABT" , 3, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_ABT" , 4, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RMR_TTO" , 5, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSI_PER" , 6, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSI_TABT" , 7, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSI_MABT" , 8, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RMSC_MSG" , 9, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RTSR_ABT" , 10, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RSERR" , 11, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RAPERR" , 12, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RDPERR" , 13, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RWR" , 14, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RRD" , 15, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RRSL_INT" , 16, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RPCNT0" , 17, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RPCNT1" , 18, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_19_20" , 19, 2, 356, "RAZ", 0, 1, 0ull, 0},
|
|
{"RPTIME0" , 21, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RPTIME1" , 22, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_23_24" , 23, 2, 356, "RAZ", 0, 1, 0ull, 0},
|
|
{"RDCNT0" , 25, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RDCNT1" , 26, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RDTIME0" , 27, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RDTIME1" , 28, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA0_FI" , 29, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA1_FI" , 30, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"WIN_WR" , 31, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_WR" , 32, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"ILL_RD" , 33, 1, 356, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_34_63" , 34, 30, 356, "RAZ", 1, 1, 0, 0},
|
|
{"TR_WABT" , 0, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WABT" , 1, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WTTO" , 2, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TR_ABT" , 3, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_ABT" , 4, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_TTO" , 5, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_PER" , 6, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_TABT" , 7, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_MABT" , 8, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSC_MSG" , 9, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TSR_ABT" , 10, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SERR" , 11, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"APERR" , 12, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPERR" , 13, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RWR" , 14, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RRD" , 15, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSL_INT" , 16, 1, 357, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCNT0" , 17, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT1" , 18, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_20" , 19, 2, 357, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PTIME0" , 21, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME1" , 22, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_24" , 23, 2, 357, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DCNT0" , 25, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT1" , 26, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME0" , 27, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME1" , 28, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA0_FI" , 29, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1_FI" , 30, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WIN_WR" , 31, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_WR" , 32, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RD" , 33, 1, 357, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 357, "RAZ", 1, 1, 0, 0},
|
|
{"TR_WABT" , 0, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WABT" , 1, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_WTTO" , 2, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TR_ABT" , 3, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_ABT" , 4, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MR_TTO" , 5, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_PER" , 6, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_TABT" , 7, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_MABT" , 8, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSC_MSG" , 9, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TSR_ABT" , 10, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SERR" , 11, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"APERR" , 12, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPERR" , 13, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RWR" , 14, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RRD" , 15, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSL_INT" , 16, 1, 358, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCNT0" , 17, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT1" , 18, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_20" , 19, 2, 358, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PTIME0" , 21, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PTIME1" , 22, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_24" , 23, 2, 358, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DCNT0" , 25, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT1" , 26, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME0" , 27, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME1" , 28, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA0_FI" , 29, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1_FI" , 30, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WIN_WR" , 31, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_WR" , 32, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ILL_RD" , 33, 1, 358, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 358, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 0, 6, 359, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_31" , 6, 26, 359, "R/W", 1, 1, 0, 0},
|
|
{"PTR_CNT" , 0, 16, 360, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_CNT" , 16, 16, 360, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_CNT" , 0, 32, 361, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_CNT" , 0, 32, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"PKT_TIME" , 0, 32, 363, "R/W", 0, 1, 0ull, 0},
|
|
{"PREFETCH" , 0, 3, 364, "R/W", 0, 0, 0ull, 2ull},
|
|
{"MIN_DATA" , 3, 6, 364, "R/W", 0, 0, 0ull, 4ull},
|
|
{"RESERVED_9_31" , 9, 23, 364, "RAZ", 1, 1, 0, 0},
|
|
{"PREFETCH" , 0, 3, 365, "R/W", 0, 0, 0ull, 3ull},
|
|
{"MIN_DATA" , 3, 6, 365, "R/W", 0, 0, 0ull, 6ull},
|
|
{"RESERVED_9_31" , 9, 23, 365, "RAZ", 1, 1, 0, 0},
|
|
{"PREFETCH" , 0, 3, 366, "R/W", 0, 0, 0ull, 3ull},
|
|
{"MIN_DATA" , 3, 6, 366, "R/W", 0, 0, 0ull, 6ull},
|
|
{"RESERVED_9_31" , 9, 23, 366, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 31, 367, "R/W", 0, 0, 10000ull, 10000ull},
|
|
{"ENB" , 31, 1, 367, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_32_63" , 32, 32, 367, "RAZ", 1, 1, 0, 0},
|
|
{"SCM" , 0, 32, 368, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 368, "RAZ", 1, 1, 0, 0},
|
|
{"TSR" , 0, 36, 369, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 369, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 370, "RAZ", 1, 1, 0, 0},
|
|
{"RD_ADDR" , 2, 46, 370, "R/W", 0, 1, 0ull, 0},
|
|
{"IOBIT" , 48, 1, 370, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 370, "RAZ", 1, 1, 0, 0},
|
|
{"RD_DATA" , 0, 64, 371, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_0_2" , 0, 3, 372, "RAZ", 1, 1, 0, 0},
|
|
{"WR_ADDR" , 3, 45, 372, "R/W", 0, 1, 0ull, 0},
|
|
{"IOBIT" , 48, 1, 372, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 372, "RAZ", 1, 1, 0, 0},
|
|
{"WR_DATA" , 0, 64, 373, "R/W", 0, 1, 0ull, 0},
|
|
{"WR_MASK" , 0, 8, 374, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 374, "RAZ", 1, 1, 0, 0},
|
|
{"THRESH" , 0, 4, 375, "R/W", 0, 0, 0ull, 8ull},
|
|
{"FETCHSIZ" , 4, 4, 375, "R/W", 0, 0, 0ull, 7ull},
|
|
{"TXRD" , 8, 10, 375, "R/W", 0, 0, 0ull, 1ull},
|
|
{"USELDT" , 18, 1, 375, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_19" , 19, 1, 375, "RAZ", 1, 1, 0, 0},
|
|
{"RXST" , 20, 10, 375, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_30_31" , 30, 2, 375, "RAZ", 1, 1, 0, 0},
|
|
{"TXSLOTS" , 32, 10, 375, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_42_43" , 42, 2, 375, "RAZ", 1, 1, 0, 0},
|
|
{"RXSLOTS" , 44, 10, 375, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_54_62" , 54, 9, 375, "RAZ", 1, 1, 0, 0},
|
|
{"RDPEND" , 63, 1, 375, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYNCMISSED" , 0, 1, 376, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FSYNCEXTRA" , 1, 1, 376, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXWRAP" , 2, 1, 376, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXST" , 3, 1, 376, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXWRAP" , 4, 1, 376, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXRD" , 5, 1, 376, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXEMPTY" , 6, 1, 376, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXOVF" , 7, 1, 376, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_8_63" , 8, 56, 376, "RAZ", 1, 1, 0, 0},
|
|
{"FSYNCMISSED" , 0, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FSYNCEXTRA" , 1, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXWRAP" , 2, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXST" , 3, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXWRAP" , 4, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXRD" , 5, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXEMPTY" , 6, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXOVF" , 7, 1, 377, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 377, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 378, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_36_63" , 36, 28, 378, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 379, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_16_63" , 16, 48, 379, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 380, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 381, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 382, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 383, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 384, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 385, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 386, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 387, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 388, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 3, 33, 388, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_36_63" , 36, 28, 388, "RAZ", 1, 1, 0, 0},
|
|
{"ENABLE" , 0, 1, 389, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USECLK1" , 1, 1, 389, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LSBFIRST" , 2, 1, 389, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_31" , 3, 29, 389, "RAZ", 1, 1, 0, 0},
|
|
{"SAMPPT" , 32, 16, 389, "R/W", 0, 1, 0ull, 0},
|
|
{"DRVTIM" , 48, 16, 389, "R/W", 0, 1, 0ull, 0},
|
|
{"DEBUGINFO" , 0, 64, 390, "RO", 1, 1, 0, 0},
|
|
{"FRAM" , 0, 3, 391, "R/W", 1, 1, 0, 0},
|
|
{"ADDR" , 3, 33, 391, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_36_63" , 36, 28, 391, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 392, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_16_63" , 16, 48, 392, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 393, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 394, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 395, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 396, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 397, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 398, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 399, "R/W", 1, 1, 0, 0},
|
|
{"MASK" , 0, 64, 400, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 401, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 3, 33, 401, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_36_63" , 36, 28, 401, "RAZ", 1, 1, 0, 0},
|
|
{"ENA" , 0, 1, 402, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSYNCPOL" , 1, 1, 402, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BCLKPOL" , 2, 1, 402, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BITLEN" , 3, 2, 402, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EXTRABIT" , 5, 1, 402, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NUMSLOTS" , 6, 10, 402, "R/W", 0, 1, 0ull, 0},
|
|
{"FSYNCLOC" , 16, 5, 402, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSYNCLEN" , 21, 5, 402, "R/W", 0, 0, 0ull, 2ull},
|
|
{"RESERVED_26_31" , 26, 6, 402, "RAZ", 1, 1, 0, 0},
|
|
{"FSYNCSAMP" , 32, 16, 402, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_62" , 48, 15, 402, "RAZ", 1, 1, 0, 0},
|
|
{"FSYNCGOOD" , 63, 1, 402, "RO", 0, 0, 0ull, 1ull},
|
|
{"DEBUGINFO" , 0, 64, 403, "RO", 1, 1, 0, 0},
|
|
{"N" , 0, 32, 404, "R/W", 0, 1, 0ull, 0},
|
|
{"NUMSAMP" , 32, 16, 404, "R/W", 0, 1, 0ull, 0},
|
|
{"DELTASAMP" , 48, 16, 404, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BIST" , 0, 17, 405, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 405, "RAZ", 1, 1, 0, 0},
|
|
{"DPRT" , 0, 16, 406, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UDP" , 16, 1, 406, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP" , 17, 1, 406, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 406, "RAZ", 1, 1, 0, 0},
|
|
{"MINLEN" , 0, 16, 407, "R/W", 0, 0, 64ull, 64ull},
|
|
{"MAXLEN" , 16, 16, 407, "R/W", 0, 0, 1536ull, 1536ull},
|
|
{"RESERVED_32_63" , 32, 32, 407, "RAZ", 1, 1, 0, 0},
|
|
{"NIP_SHF" , 0, 3, 408, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_7" , 3, 5, 408, "RAZ", 1, 1, 0, 0},
|
|
{"RAW_SHF" , 8, 3, 408, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_15" , 11, 5, 408, "RAZ", 1, 1, 0, 0},
|
|
{"MAX_L2" , 16, 1, 408, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_UDP" , 17, 1, 408, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TAG_SYN" , 18, 1, 408, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 408, "RAZ", 1, 1, 0, 0},
|
|
{"IP_CHK" , 0, 1, 409, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP_MAL" , 1, 1, 409, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP_HOP" , 2, 1, 409, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP4_OPTS" , 3, 1, 409, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP6_EEXT" , 4, 2, 409, "R/W", 0, 0, 1ull, 3ull},
|
|
{"RESERVED_6_7" , 6, 2, 409, "RAZ", 0, 1, 0ull, 0},
|
|
{"L4_MAL" , 8, 1, 409, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_PRT" , 9, 1, 409, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_CHK" , 10, 1, 409, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_LEN" , 11, 1, 409, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TCP_FLAG" , 12, 1, 409, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L2_MAL" , 13, 1, 409, "R/W", 0, 0, 1ull, 1ull},
|
|
{"VS_QOS" , 14, 1, 409, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VS_WQE" , 15, 1, 409, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IGNRS" , 16, 1, 409, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 409, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PKTDRP" , 0, 1, 410, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 410, "RAZ", 1, 1, 0, 0},
|
|
{"BCKPRS" , 2, 1, 410, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 3, 1, 410, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BADTAG" , 4, 1, 410, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPRUNT" , 5, 1, 410, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TODOOVR" , 6, 1, 410, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FEPERR" , 7, 1, 410, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BEPERR" , 8, 1, 410, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MINERR" , 9, 1, 410, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 10, 1, 410, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 11, 1, 410, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 410, "RAZ", 1, 1, 0, 0},
|
|
{"PKTDRP" , 0, 1, 411, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 411, "RAZ", 1, 1, 0, 0},
|
|
{"BCKPRS" , 2, 1, 411, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 3, 1, 411, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BADTAG" , 4, 1, 411, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPRUNT" , 5, 1, 411, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TODOOVR" , 6, 1, 411, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FEPERR" , 7, 1, 411, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BEPERR" , 8, 1, 411, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MINERR" , 9, 1, 411, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 10, 1, 411, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 11, 1, 411, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 411, "RAZ", 1, 1, 0, 0},
|
|
{"OFFSET" , 0, 3, 412, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 412, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP" , 0, 7, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 413, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 8, 2, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_11" , 10, 2, 413, "RAZ", 1, 1, 0, 0},
|
|
{"CRC_EN" , 12, 1, 413, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 413, "RAZ", 1, 1, 0, 0},
|
|
{"QOS_VLAN" , 16, 1, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS_DIFF" , 17, 1, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS_VOD" , 18, 1, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_19" , 19, 1, 413, "RAZ", 1, 1, 0, 0},
|
|
{"QOS_WAT" , 20, 4, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS" , 24, 3, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 413, "RAZ", 1, 1, 0, 0},
|
|
{"GRP_WAT" , 28, 4, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INST_HDR" , 32, 1, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DYN_RS" , 33, 1, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TAG_INC" , 34, 2, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RAWDRP" , 36, 1, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_39" , 37, 3, 413, "RAZ", 1, 1, 0, 0},
|
|
{"QOS_WAT_47" , 40, 4, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRP_WAT_47" , 44, 4, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MINERR_EN" , 48, 1, 413, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MAXERR_EN" , 49, 1, 413, "R/W", 0, 0, 1ull, 1ull},
|
|
{"LENERR_EN" , 50, 1, 413, "R/W", 0, 0, 1ull, 1ull},
|
|
{"VLAN_LEN" , 51, 1, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PAD_LEN" , 52, 1, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_53_63" , 53, 11, 413, "RAZ", 1, 1, 0, 0},
|
|
{"GRP" , 0, 4, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NON_TAG_TYPE" , 4, 2, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_TAG_TYPE" , 6, 2, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_TAG_TYPE" , 8, 2, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP4_TAG_TYPE" , 10, 2, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP6_TAG_TYPE" , 12, 2, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_SRC_FLAG" , 14, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_SRC_FLAG" , 15, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_DST_FLAG" , 16, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_DST_FLAG" , 17, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_PCTL_FLAG" , 18, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_NXTH_FLAG" , 19, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_SPRT_FLAG" , 20, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_SPRT_FLAG" , 21, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_DPRT_FLAG" , 22, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_DPRT_FLAG" , 23, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_PRT_FLAG" , 24, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_VLAN" , 25, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_VS" , 26, 2, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TAG_MODE" , 28, 2, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAG_MSKIP" , 30, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAG" , 31, 1, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAGMASK" , 32, 4, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAGBASE" , 36, 4, 414, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 414, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 0, 3, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 415, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 0, 3, 416, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 416, "RAZ", 1, 1, 0, 0},
|
|
{"MATCH_VALUE" , 0, 16, 417, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MATCH_TYPE" , 16, 3, 417, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_19" , 19, 1, 417, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 20, 3, 417, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 417, "RAZ", 1, 1, 0, 0},
|
|
{"GRP" , 24, 4, 417, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_31" , 28, 4, 417, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 32, 16, 417, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 417, "RAZ", 1, 1, 0, 0},
|
|
{"WORD" , 0, 56, 418, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 418, "RAZ", 1, 1, 0, 0},
|
|
{"RST" , 0, 1, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 419, "RAZ", 1, 1, 0, 0},
|
|
{"DRP_OCTS" , 0, 32, 420, "R/W", 0, 1, 0ull, 0},
|
|
{"DRP_PKTS" , 32, 32, 420, "R/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 421, "RAZ", 1, 1, 0, 0},
|
|
{"RAW" , 0, 32, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"PKTS" , 32, 32, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 0, 32, 423, "R/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 32, 32, 423, "R/W", 0, 1, 0ull, 0},
|
|
{"H64" , 0, 32, 424, "R/W", 0, 1, 0ull, 0},
|
|
{"H65TO127" , 32, 32, 424, "R/W", 0, 1, 0ull, 0},
|
|
{"H128TO255" , 0, 32, 425, "R/W", 0, 1, 0ull, 0},
|
|
{"H256TO511" , 32, 32, 425, "R/W", 0, 1, 0ull, 0},
|
|
{"H512TO1023" , 0, 32, 426, "R/W", 0, 1, 0ull, 0},
|
|
{"H1024TO1518" , 32, 32, 426, "R/W", 0, 1, 0ull, 0},
|
|
{"H1519" , 0, 32, 427, "R/W", 0, 1, 0ull, 0},
|
|
{"FCS" , 32, 32, 427, "R/W", 0, 1, 0ull, 0},
|
|
{"UNDERSZ" , 0, 32, 428, "R/W", 0, 1, 0ull, 0},
|
|
{"FRAG" , 32, 32, 428, "R/W", 0, 1, 0ull, 0},
|
|
{"OVERSZ" , 0, 32, 429, "R/W", 0, 1, 0ull, 0},
|
|
{"JABBER" , 32, 32, 429, "R/W", 0, 1, 0ull, 0},
|
|
{"RDCLR" , 0, 1, 430, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 430, "RAZ", 1, 1, 0, 0},
|
|
{"ERRS" , 0, 16, 431, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 431, "RAZ", 1, 1, 0, 0},
|
|
{"OCTS" , 0, 48, 432, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 432, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 433, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 433, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 8, 434, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 434, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 0, 16, 435, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 435, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 16, 436, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DST" , 16, 16, 436, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 436, "RAZ", 1, 1, 0, 0},
|
|
{"ENTRY" , 0, 62, 437, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_62_62" , 62, 1, 437, "RAZ", 1, 1, 0, 0},
|
|
{"VAL" , 63, 1, 437, "RO", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 32, 438, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 438, "RAZ", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 48, 439, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 439, "RAZ", 1, 1, 0, 0},
|
|
{"SIZE" , 0, 16, 440, "RO", 1, 0, 0, 0ull},
|
|
{"SEGS" , 16, 6, 440, "RO", 1, 0, 0, 0ull},
|
|
{"CMD" , 22, 14, 440, "RO", 1, 0, 0, 0ull},
|
|
{"FAU" , 36, 28, 440, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 441, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 441, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 441, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 441, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 441, "RO", 1, 0, 0, 0ull},
|
|
{"PTRS2" , 0, 17, 442, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 442, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTRS1" , 32, 17, 442, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 442, "RAZ", 1, 0, 0, 0ull},
|
|
{"MOD" , 0, 3, 443, "RO", 1, 0, 0, 0ull},
|
|
{"CNT" , 3, 13, 443, "RO", 1, 0, 0, 0ull},
|
|
{"CHK" , 16, 1, 443, "RO", 1, 0, 0, 0ull},
|
|
{"LEN" , 17, 1, 443, "RO", 1, 0, 0, 0ull},
|
|
{"SOP" , 18, 1, 443, "RO", 1, 0, 0, 0ull},
|
|
{"UID" , 19, 3, 443, "RO", 1, 0, 0, 0ull},
|
|
{"MAJ" , 22, 1, 443, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 443, "RAZ", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 16, 444, "RO", 1, 0, 0, 0ull},
|
|
{"SEGS" , 16, 6, 444, "RO", 1, 0, 0, 0ull},
|
|
{"CMD" , 22, 14, 444, "RO", 1, 0, 0, 0ull},
|
|
{"FAU" , 36, 28, 444, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 445, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 445, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 445, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 445, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 445, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 446, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 446, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 446, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 446, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 446, "RO", 1, 0, 0, 0ull},
|
|
{"DATA" , 0, 64, 447, "RO", 1, 0, 0, 0ull},
|
|
{"MAJOR" , 0, 3, 448, "RO", 1, 0, 0, 0ull},
|
|
{"MINOR" , 3, 2, 448, "RO", 1, 0, 0, 0ull},
|
|
{"WAIT" , 5, 1, 448, "RO", 1, 0, 0, 0ull},
|
|
{"QID_BASE" , 6, 8, 448, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFF" , 14, 4, 448, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFF_MAX" , 18, 4, 448, "RO", 1, 0, 0, 0ull},
|
|
{"QCB_RIDX" , 22, 5, 448, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 27, 3, 448, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 30, 1, 448, "RO", 1, 0, 0, 0ull},
|
|
{"ACTIVE" , 31, 1, 448, "RO", 1, 0, 0, 0ull},
|
|
{"CHK_MODE" , 32, 1, 448, "RO", 1, 0, 0, 0ull},
|
|
{"CHK_ONCE" , 33, 1, 448, "RO", 1, 0, 0, 0ull},
|
|
{"INIT_DWRITE" , 34, 1, 448, "RO", 1, 0, 0, 0ull},
|
|
{"DREAD_SOP" , 35, 1, 448, "RO", 1, 0, 0, 0ull},
|
|
{"UID" , 36, 3, 448, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_OFF" , 39, 6, 448, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_SIZ" , 45, 16, 448, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_SEGS" , 61, 3, 448, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_SEGS" , 0, 3, 449, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_OFF" , 3, 16, 449, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_SIZ" , 19, 16, 449, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_PTR" , 35, 29, 449, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_PTR" , 0, 11, 450, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 450, "RAZ", 1, 0, 0, 0ull},
|
|
{"QCB_RIDX" , 0, 6, 451, "RO", 1, 0, 0, 0ull},
|
|
{"QCB_WIDX" , 6, 6, 451, "RO", 1, 0, 0, 0ull},
|
|
{"BUF_PTR" , 12, 33, 451, "RO", 1, 0, 0, 0ull},
|
|
{"BUF_SIZ" , 45, 13, 451, "RO", 1, 0, 0, 0ull},
|
|
{"TAIL" , 58, 1, 451, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 59, 5, 451, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 0, 3, 452, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_Q" , 3, 1, 452, "RO", 1, 0, 0, 0ull},
|
|
{"S_TAIL" , 4, 1, 452, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 5, 1, 452, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 452, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 8, 20, 452, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 452, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTRS3" , 0, 17, 453, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 453, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTRS0" , 32, 17, 453, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 453, "RAZ", 1, 0, 0, 0ull},
|
|
{"QUEUE" , 0, 7, 454, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT" , 7, 6, 454, "WR0", 1, 0, 0, 0ull},
|
|
{"INDEX" , 13, 3, 454, "WR0", 1, 0, 0, 0ull},
|
|
{"TAIL" , 16, 1, 454, "R/W", 1, 0, 0, 0ull},
|
|
{"BUF_PTR" , 17, 36, 454, "R/W", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 454, "R/W", 1, 0, 0, 0ull},
|
|
{"STATIC_Q" , 61, 1, 454, "R/W", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 62, 1, 454, "R/W", 1, 0, 0, 0ull},
|
|
{"S_TAIL" , 63, 1, 454, "R/W", 1, 0, 0, 0ull},
|
|
{"QID" , 0, 7, 455, "R/W", 1, 0, 0, 0ull},
|
|
{"PID" , 7, 6, 455, "WR0", 1, 0, 0, 0ull},
|
|
{"RESERVED_13_52" , 13, 40, 455, "RAZ", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 455, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_61_63" , 61, 3, 455, "RAZ", 1, 0, 0, 0ull},
|
|
{"DAT_PTR" , 0, 4, 456, "RO", 1, 0, 0, 0ull},
|
|
{"DAT_DAT" , 4, 4, 456, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_QSB" , 8, 3, 456, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_QCB" , 11, 2, 456, "RO", 1, 0, 0, 0ull},
|
|
{"NCB_INB" , 13, 2, 456, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_PSB" , 15, 6, 456, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_NXT" , 21, 1, 456, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_CHK" , 22, 3, 456, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_WIF" , 25, 1, 456, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_STA" , 26, 1, 456, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_CTL" , 27, 3, 456, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_CRC" , 30, 1, 456, "RO", 1, 0, 0, 0ull},
|
|
{"IOB" , 31, 1, 456, "RO", 1, 0, 0, 0ull},
|
|
{"CSR" , 32, 1, 456, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_33_63" , 33, 31, 456, "RAZ", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 13, 457, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_19" , 13, 7, 457, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 20, 3, 457, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 457, "RAZ", 1, 0, 0, 0ull},
|
|
{"ASSERTS" , 0, 64, 458, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 64, 459, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 64, 460, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 64, 461, "RO", 0, 0, 0ull, 0ull},
|
|
{"PARITY" , 0, 1, 462, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 1, 1, 462, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CURRZERO" , 2, 1, 462, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 462, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENA_PKO" , 0, 1, 463, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENA_DWB" , 1, 1, 463, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STORE_BE" , 2, 1, 463, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 3, 1, 463, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 463, "RAZ", 1, 0, 0, 0ull},
|
|
{"MODE0" , 0, 3, 464, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MODE1" , 3, 3, 464, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 464, "RAZ", 1, 0, 0, 0ull},
|
|
{"PARITY" , 0, 1, 465, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 1, 1, 465, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CURRZERO" , 2, 1, 465, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 465, "RAZ", 1, 0, 0, 0ull},
|
|
{"MODE" , 0, 2, 466, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 466, "RAZ", 1, 0, 0, 0ull},
|
|
{"QID7" , 0, 1, 467, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDX3" , 1, 1, 467, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 467, "RAZ", 1, 0, 0, 0ull},
|
|
{"INDEX" , 0, 8, 468, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 8, 8, 468, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 468, "RAZ", 1, 0, 0, 0ull},
|
|
{"ADR" , 0, 1, 469, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEND" , 1, 1, 469, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBR0" , 2, 1, 469, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBR1" , 3, 1, 469, "RO", 0, 0, 0ull, 0ull},
|
|
{"FIDX" , 4, 1, 469, "RO", 0, 0, 0ull, 0ull},
|
|
{"INDEX" , 5, 1, 469, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBT0" , 6, 1, 469, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBT1" , 7, 1, 469, "RO", 0, 0, 0ull, 0ull},
|
|
{"CAM" , 8, 1, 469, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_15" , 9, 7, 469, "RAZ", 1, 1, 0, 0},
|
|
{"PP" , 16, 2, 469, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 469, "RAZ", 1, 1, 0, 0},
|
|
{"DS_PC" , 0, 32, 470, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 470, "RAZ", 1, 1, 0, 0},
|
|
{"SBE" , 0, 1, 471, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DBE" , 1, 1, 471, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SBE_IE" , 2, 1, 471, "R/W", 0, 1, 0ull, 0},
|
|
{"DBE_IE" , 3, 1, 471, "R/W", 0, 1, 0ull, 0},
|
|
{"SYN" , 4, 5, 471, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_9_11" , 9, 3, 471, "RAZ", 1, 1, 0, 0},
|
|
{"RPE" , 12, 1, 471, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPE_IE" , 13, 1, 471, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_15" , 14, 2, 471, "RAZ", 1, 1, 0, 0},
|
|
{"IOP" , 16, 13, 471, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_31" , 29, 3, 471, "RAZ", 1, 1, 0, 0},
|
|
{"IOP_IE" , 32, 13, 471, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_45_63" , 45, 19, 471, "RAZ", 1, 1, 0, 0},
|
|
{"NBR_THR" , 0, 5, 472, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PFR_DIS" , 5, 1, 472, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 472, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 32, 473, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 473, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 32, 474, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 474, "RAZ", 1, 1, 0, 0},
|
|
{"NOS_CNT" , 0, 9, 475, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_9_63" , 9, 55, 475, "RAZ", 1, 1, 0, 0},
|
|
{"NW_TIM" , 0, 10, 476, "R/W", 0, 0, 0ull, 1023ull},
|
|
{"RESERVED_10_63" , 10, 54, 476, "RAZ", 1, 1, 0, 0},
|
|
{"RST_MSK" , 0, 8, 477, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 477, "RAZ", 1, 1, 0, 0},
|
|
{"GRP_MSK" , 0, 16, 478, "R/W", 0, 0, 65535ull, 65535ull},
|
|
{"QOS0_PRI" , 16, 4, 478, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS1_PRI" , 20, 4, 478, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS2_PRI" , 24, 4, 478, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS3_PRI" , 28, 4, 478, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS4_PRI" , 32, 4, 478, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS5_PRI" , 36, 4, 478, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS6_PRI" , 40, 4, 478, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS7_PRI" , 44, 4, 478, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 478, "RAZ", 1, 1, 0, 0},
|
|
{"RND" , 0, 8, 479, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P1" , 8, 8, 479, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P2" , 16, 8, 479, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P3" , 24, 8, 479, "R/W", 0, 1, 255ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 479, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_THR" , 0, 8, 480, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_11" , 8, 4, 480, "RAZ", 1, 1, 0, 0},
|
|
{"MAX_THR" , 12, 8, 480, "R/W", 0, 1, 255ull, 0},
|
|
{"RESERVED_20_23" , 20, 4, 480, "RAZ", 1, 1, 0, 0},
|
|
{"FREE_CNT" , 24, 9, 480, "RO", 0, 1, 249ull, 0},
|
|
{"RESERVED_33_35" , 33, 3, 480, "RAZ", 1, 1, 0, 0},
|
|
{"BUF_CNT" , 36, 9, 480, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_45_47" , 45, 3, 480, "RAZ", 1, 1, 0, 0},
|
|
{"DES_CNT" , 48, 9, 480, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_57_63" , 57, 7, 480, "RAZ", 1, 1, 0, 0},
|
|
{"TS_PC" , 0, 32, 481, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 481, "RAZ", 1, 1, 0, 0},
|
|
{"WA_PC" , 0, 32, 482, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 482, "RAZ", 1, 1, 0, 0},
|
|
{"WA_PC" , 0, 32, 483, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 483, "RAZ", 1, 1, 0, 0},
|
|
{"WQ_INT" , 0, 16, 484, "R/W1C", 0, 1, 0ull, 0},
|
|
{"IQ_DIS" , 16, 16, 484, "R/W1", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 484, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 9, 485, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_9_11" , 9, 3, 485, "RAZ", 1, 1, 0, 0},
|
|
{"DS_CNT" , 12, 9, 485, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_21_23" , 21, 3, 485, "RAZ", 1, 1, 0, 0},
|
|
{"TC_CNT" , 24, 4, 485, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_63" , 28, 36, 485, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 486, "RAZ", 1, 1, 0, 0},
|
|
{"PC_THR" , 8, 20, 486, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_31" , 28, 4, 486, "RAZ", 1, 1, 0, 0},
|
|
{"PC" , 32, 28, 486, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 486, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_THR" , 0, 8, 487, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_11" , 8, 4, 487, "RAZ", 1, 1, 0, 0},
|
|
{"DS_THR" , 12, 8, 487, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_23" , 20, 4, 487, "RAZ", 1, 1, 0, 0},
|
|
{"TC_THR" , 24, 4, 487, "R/W", 0, 1, 0ull, 0},
|
|
{"TC_EN" , 28, 1, 487, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 487, "RAZ", 1, 1, 0, 0},
|
|
{"WS_PC" , 0, 32, 488, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 488, "RAZ", 1, 1, 0, 0},
|
|
{"MEM" , 0, 1, 489, "RO", 0, 0, 0ull, 0ull},
|
|
{"RRC" , 1, 1, 489, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 489, "RAZ", 1, 1, 0, 0},
|
|
{"ENT_EN" , 0, 1, 490, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNG_EN" , 1, 1, 490, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNM_RST" , 2, 1, 490, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNG_RST" , 3, 1, 490, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EXP_ENT" , 4, 1, 490, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENT_SEL" , 5, 4, 490, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 490, "RAZ", 1, 1, 0, 0},
|
|
{"PHASE" , 0, 8, 491, "R/W", 0, 0, 100ull, 100ull},
|
|
{"SAMPLE" , 8, 4, 491, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PREAMBLE" , 12, 1, 491, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CLK_IDLE" , 13, 1, 491, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_14" , 14, 1, 491, "RAZ", 1, 1, 0, 0},
|
|
{"SAMPLE_MODE" , 15, 1, 491, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SAMPLE_HI" , 16, 5, 491, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_23" , 21, 3, 491, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 24, 1, 491, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_63" , 25, 39, 491, "RAZ", 1, 1, 0, 0},
|
|
{"REG_ADR" , 0, 5, 492, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 492, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_ADR" , 8, 5, 492, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_13_15" , 13, 3, 492, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_OP" , 16, 2, 492, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 492, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 493, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 493, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 494, "RO", 0, 1, 0ull, 0},
|
|
{"VAL" , 16, 1, 494, "RO", 0, 1, 0ull, 0},
|
|
{"PENDING" , 17, 1, 494, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 494, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 495, "R/W", 0, 1, 0ull, 0},
|
|
{"VAL" , 16, 1, 495, "RO", 0, 1, 0ull, 0},
|
|
{"PENDING" , 17, 1, 495, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 495, "RAZ", 1, 1, 0, 0},
|
|
{"INTERVAL" , 0, 22, 496, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 496, "RAZ", 1, 0, 0, 0ull},
|
|
{"COUNT" , 24, 22, 496, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_46_46" , 46, 1, 496, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENA" , 47, 1, 496, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 496, "RAZ", 1, 0, 0, 0ull},
|
|
{"BSIZE" , 0, 20, 497, "RO", 1, 0, 0, 0ull},
|
|
{"BASE" , 20, 31, 497, "RO", 1, 0, 0, 0ull},
|
|
{"BUCKET" , 51, 13, 497, "RO", 1, 0, 0, 0ull},
|
|
{"BUCKET" , 0, 7, 498, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 498, "RAZ", 1, 0, 0, 0ull},
|
|
{"CSIZE" , 8, 13, 498, "RO", 1, 0, 0, 0ull},
|
|
{"CPOOL" , 21, 3, 498, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 498, "RAZ", 1, 0, 0, 0ull},
|
|
{"RING" , 0, 4, 499, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NUM_BUCKETS" , 4, 20, 499, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIRST_BUCKET" , 24, 31, 499, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_55_63" , 55, 9, 499, "RAZ", 1, 0, 0, 0ull},
|
|
{"RING" , 0, 4, 500, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTERVAL" , 4, 22, 500, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WORDS_PER_CHUNK" , 26, 13, 500, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 39, 3, 500, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENABLE" , 42, 1, 500, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_43_63" , 43, 21, 500, "RAZ", 1, 0, 0, 0ull},
|
|
{"CTL" , 0, 1, 501, "RO", 1, 0, 0, 0ull},
|
|
{"NCB" , 1, 1, 501, "RO", 1, 0, 0, 0ull},
|
|
{"STA" , 2, 2, 501, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 501, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 16, 502, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 502, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENABLE_TIMERS" , 0, 1, 503, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENABLE_DWB" , 1, 1, 503, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 2, 1, 503, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 503, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 16, 504, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 504, "RAZ", 1, 0, 0, 0ull},
|
|
{"INDEX" , 0, 8, 505, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 8, 8, 505, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 505, "RAZ", 1, 0, 0, 0ull},
|
|
{"INEPINT" , 0, 16, 506, "RO", 0, 0, 0ull, 0ull},
|
|
{"OUTEPINT" , 16, 16, 506, "RO", 0, 0, 0ull, 0ull},
|
|
{"INEPMSK" , 0, 16, 507, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OUTEPMSK" , 16, 16, 507, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DEVSPD" , 0, 2, 508, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NZSTSOUTHSHK" , 2, 1, 508, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 508, "RAZ", 1, 1, 0, 0},
|
|
{"DEVADDR" , 4, 7, 508, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PERFRINT" , 11, 2, 508, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_17" , 13, 5, 508, "RAZ", 1, 1, 0, 0},
|
|
{"EPMISCNT" , 18, 5, 508, "R/W", 0, 0, 8ull, 0ull},
|
|
{"RESERVED_23_31" , 23, 9, 508, "RAZ", 1, 1, 0, 0},
|
|
{"RMTWKUPSIG" , 0, 1, 509, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SFTDISCON" , 1, 1, 509, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GNPINNAKSTS" , 2, 1, 509, "RO", 0, 0, 0ull, 0ull},
|
|
{"GOUTNAKSTS" , 3, 1, 509, "RO", 0, 0, 0ull, 0ull},
|
|
{"TSTCTL" , 4, 3, 509, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SGNPINNAK" , 7, 1, 509, "WO", 0, 0, 0ull, 0ull},
|
|
{"CGNPINNAK" , 8, 1, 509, "WO", 0, 0, 0ull, 0ull},
|
|
{"SGOUTNAK" , 9, 1, 509, "WO", 0, 0, 0ull, 0ull},
|
|
{"CGOUTNAK" , 10, 1, 509, "WO", 0, 0, 0ull, 0ull},
|
|
{"PWRONPRGDONE" , 11, 1, 509, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_31" , 12, 20, 509, "RAZ", 1, 1, 0, 0},
|
|
{"MPS" , 0, 11, 510, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NEXTEP" , 11, 4, 510, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBACTEP" , 15, 1, 510, "R/W", 0, 0, 1ull, 0ull},
|
|
{"DPID" , 16, 1, 510, "RO", 0, 0, 0ull, 0ull},
|
|
{"NAKSTS" , 17, 1, 510, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTYPE" , 18, 2, 510, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 510, "RAZ", 1, 1, 0, 0},
|
|
{"STALL" , 21, 1, 510, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFNUM" , 22, 4, 510, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNAK" , 26, 1, 510, "WO", 0, 0, 0ull, 0ull},
|
|
{"SNAK" , 27, 1, 510, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD0PID" , 28, 1, 510, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD1PID" , 29, 1, 510, "WO", 0, 0, 0ull, 0ull},
|
|
{"EPDIS" , 30, 1, 510, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPENA" , 31, 1, 510, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XFERCOMPL" , 0, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLD" , 1, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AHBERR" , 2, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TIMEOUT" , 3, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTKNTXFEMP" , 4, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTKNEPMIS" , 5, 1, 511, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INEPNAKEFF" , 6, 1, 511, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_31" , 7, 25, 511, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPLMSK" , 0, 1, 512, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLDMSK" , 1, 1, 512, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AHBERRMSK" , 2, 1, 512, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMEOUTMSK" , 3, 1, 512, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTKNTXFEMPMSK" , 4, 1, 512, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTKNEPMISMSK" , 5, 1, 512, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INEPNAKEFFMSK" , 6, 1, 512, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_31" , 7, 25, 512, "RAZ", 1, 1, 0, 0},
|
|
{"XFERSIZE" , 0, 19, 513, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKTCNT" , 19, 10, 513, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MC" , 29, 2, 513, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_31" , 31, 1, 513, "RAZ", 1, 1, 0, 0},
|
|
{"MPS" , 0, 11, 514, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_14" , 11, 4, 514, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"USBACTEP" , 15, 1, 514, "R/W", 0, 0, 1ull, 0ull},
|
|
{"DPID" , 16, 1, 514, "RO", 0, 0, 0ull, 0ull},
|
|
{"NAKSTS" , 17, 1, 514, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTYPE" , 18, 2, 514, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SNP" , 20, 1, 514, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STALL" , 21, 1, 514, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_25" , 22, 4, 514, "RAZ", 1, 1, 0, 0},
|
|
{"CNAK" , 26, 1, 514, "WO", 0, 0, 0ull, 0ull},
|
|
{"SNAK" , 27, 1, 514, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD0PID" , 28, 1, 514, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD1PID" , 29, 1, 514, "WO", 0, 0, 0ull, 0ull},
|
|
{"EPDIS" , 30, 1, 514, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPENA" , 31, 1, 514, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XFERCOMPL" , 0, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLD" , 1, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AHBERR" , 2, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SETUP" , 3, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OUTTKNEPDIS" , 4, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 515, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPLMSK" , 0, 1, 516, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLDMSK" , 1, 1, 516, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AHBERRMSK" , 2, 1, 516, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SETUPMSK" , 3, 1, 516, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OUTTKNEPDISMSK" , 4, 1, 516, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 516, "RAZ", 1, 1, 0, 0},
|
|
{"XFERSIZE" , 0, 19, 517, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKTCNT" , 19, 10, 517, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MC" , 29, 2, 517, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_31" , 31, 1, 517, "RAZ", 1, 1, 0, 0},
|
|
{"DPTXFSTADDR" , 0, 16, 518, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPTXFSIZE" , 16, 16, 518, "RO", 0, 0, 1896ull, 1896ull},
|
|
{"SUSPSTS" , 0, 1, 519, "RO", 0, 0, 0ull, 0ull},
|
|
{"ENUMSPD" , 1, 2, 519, "RO", 0, 0, 0ull, 0ull},
|
|
{"ERRTICERR" , 3, 1, 519, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 519, "RAZ", 1, 1, 0, 0},
|
|
{"SOFFN" , 8, 14, 519, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_31" , 22, 10, 519, "RAZ", 1, 1, 0, 0},
|
|
{"INTKNWPTR" , 0, 5, 520, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_6" , 5, 2, 520, "RAZ", 1, 1, 0, 0},
|
|
{"WRAPBIT" , 7, 1, 520, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 8, 24, 520, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 0, 32, 521, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 0, 32, 522, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 0, 32, 523, "RO", 0, 0, 0ull, 0ull},
|
|
{"GLBLINTRMSK" , 0, 1, 524, "R/W", 0, 0, 0ull, 1ull},
|
|
{"HBSTLEN" , 1, 4, 524, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMAEN" , 5, 1, 524, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_6" , 6, 1, 524, "RAZ", 1, 1, 0, 0},
|
|
{"NPTXFEMPLVL" , 7, 1, 524, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PTXFEMPLVL" , 8, 1, 524, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_9_31" , 9, 23, 524, "RAZ", 1, 1, 0, 0},
|
|
{"EPDIR" , 0, 32, 525, "RO", 0, 0, 0ull, 0ull},
|
|
{"OTGMODE" , 0, 3, 526, "RO", 0, 0, 2ull, 2ull},
|
|
{"OTGARCH" , 3, 2, 526, "RO", 0, 0, 1ull, 1ull},
|
|
{"SINGPNT" , 5, 1, 526, "RO", 0, 0, 0ull, 0ull},
|
|
{"HSPHYTYPE" , 6, 2, 526, "RO", 0, 0, 1ull, 1ull},
|
|
{"FSPHYTYPE" , 8, 2, 526, "RO", 0, 0, 0ull, 0ull},
|
|
{"NUMDEVEPS" , 10, 4, 526, "RO", 0, 0, 4ull, 4ull},
|
|
{"NUMHSTCHNL" , 14, 4, 526, "RO", 0, 0, 7ull, 7ull},
|
|
{"PERIOSUPPORT" , 18, 1, 526, "RO", 0, 0, 1ull, 1ull},
|
|
{"DYNFIFOSIZING" , 19, 1, 526, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_20_21" , 20, 2, 526, "RAZ", 1, 1, 0, 0},
|
|
{"NPTXQDEPTH" , 22, 2, 526, "RO", 0, 0, 2ull, 2ull},
|
|
{"PTXQDEPTH" , 24, 2, 526, "RO", 0, 0, 2ull, 2ull},
|
|
{"TKNQDEPTH" , 26, 5, 526, "RO", 0, 0, 30ull, 30ull},
|
|
{"RESERVED_31_31" , 31, 1, 526, "RAZ", 1, 1, 0, 0},
|
|
{"XFERSIZEWIDTH" , 0, 4, 527, "RO", 0, 0, 8ull, 8ull},
|
|
{"PKTSIZEWIDTH" , 4, 3, 527, "RO", 0, 0, 6ull, 6ull},
|
|
{"OTGEN" , 7, 1, 527, "RO", 0, 0, 1ull, 1ull},
|
|
{"I2C_SELECTION" , 8, 1, 527, "RO", 0, 0, 0ull, 0ull},
|
|
{"VENDOR_CONTROL_INTERFACE_SUPPORT", 9, 1, 527, "RO", 0, 0, 0ull, 0ull},
|
|
{"OPTFEATURE" , 10, 1, 527, "RO", 0, 0, 1ull, 1ull},
|
|
{"RSTTYPE" , 11, 1, 527, "RO", 0, 0, 1ull, 1ull},
|
|
{"AHBPHYSYNC" , 12, 1, 527, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 527, "RAZ", 1, 1, 0, 0},
|
|
{"DFIFODEPTH" , 16, 16, 527, "RO", 0, 0, 1824ull, 1824ull},
|
|
{"NUMDEVPERIOEPS" , 0, 4, 528, "RO", 0, 0, 4ull, 4ull},
|
|
{"ENABLEPWROPT" , 4, 1, 528, "RO", 0, 0, 0ull, 0ull},
|
|
{"AHBFREQ" , 5, 1, 528, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_13" , 6, 8, 528, "RAZ", 1, 1, 0, 0},
|
|
{"PHYDATAWIDTH" , 14, 2, 528, "RO", 0, 0, 1ull, 1ull},
|
|
{"NUMCTLEPS" , 16, 4, 528, "RO", 0, 0, 4ull, 4ull},
|
|
{"IDDGFLTR" , 20, 1, 528, "RO", 0, 0, 1ull, 1ull},
|
|
{"VBUSVALIDFLTR" , 21, 1, 528, "RO", 0, 0, 1ull, 1ull},
|
|
{"AVALIDFLTR" , 22, 1, 528, "RO", 0, 0, 0ull, 0ull},
|
|
{"BVALIDFLTR" , 23, 1, 528, "RO", 0, 0, 0ull, 0ull},
|
|
{"SESSENDFLTR" , 24, 1, 528, "RO", 0, 0, 0ull, 0ull},
|
|
{"ENDEDTRFIFO" , 25, 1, 528, "RO", 0, 0, 0ull, 0ull},
|
|
{"NUMDEVMODINEND" , 26, 4, 528, "RO", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_30_31" , 30, 2, 528, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 529, "RAZ", 1, 1, 0, 0},
|
|
{"MODEMISMSK" , 1, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OTGINTMSK" , 2, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SOFMSK" , 3, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RXFLVLMSK" , 4, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NPTXFEMPMSK" , 5, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GINNAKEFFMSK" , 6, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GOUTNAKEFFMSK" , 7, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ULPICKINTMSK" , 8, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"I2CINT" , 9, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ERLYSUSPMSK" , 10, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBSUSPMSK" , 11, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBRSTMSK" , 12, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENUMDONEMSK" , 13, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ISOOUTDROPMSK" , 14, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EOPFMSK" , 15, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 529, "RAZ", 1, 1, 0, 0},
|
|
{"EPMISMSK" , 17, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INEPINTMSK" , 18, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OEPINTMSK" , 19, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INCOMPISOINMSK" , 20, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INCOMPLPMSK" , 21, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FETSUSPMSK" , 22, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 529, "RAZ", 1, 1, 0, 0},
|
|
{"PRTINTMSK" , 24, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HCHINTMSK" , 25, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PTXFEMPMSK" , 26, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 529, "RAZ", 1, 1, 0, 0},
|
|
{"CONIDSTSCHNGMSK" , 28, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DISCONNINTMSK" , 29, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SESSREQINTMSK" , 30, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WKUPINTMSK" , 31, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CURMOD" , 0, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"MODEMIS" , 1, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OTGINT" , 2, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"SOF" , 3, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXFLVL" , 4, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPTXFEMP" , 5, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"GINNAKEFF" , 6, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"GOUTNAKEFF" , 7, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"ULPICKINT" , 8, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I2CINT" , 9, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ERLYSUSP" , 10, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USBSUSP" , 11, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USBRST" , 12, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ENUMDONE" , 13, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ISOOUTDROP" , 14, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EOPF" , 15, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 530, "RAZ", 1, 1, 0, 0},
|
|
{"EPMIS" , 17, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IEPINT" , 18, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"OEPINT" , 19, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"INCOMPISOIN" , 20, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INCOMPLP" , 21, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FETSUSP" , 22, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 530, "RAZ", 1, 1, 0, 0},
|
|
{"PRTINT" , 24, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"HCHINT" , 25, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTXFEMP" , 26, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 530, "RAZ", 1, 1, 0, 0},
|
|
{"CONIDSTSCHNG" , 28, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DISCONNINT" , 29, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SESSREQINT" , 30, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WKUPINT" , 31, 1, 530, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NPTXFSTADDR" , 0, 16, 531, "R/W", 0, 0, 1824ull, 456ull},
|
|
{"NPTXFDEP" , 16, 16, 531, "R/W", 0, 0, 1824ull, 912ull},
|
|
{"NPTXFSPCAVAIL" , 0, 16, 532, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPTXQSPCAVAIL" , 16, 8, 532, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPTXQTOP" , 24, 7, 532, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_31" , 31, 1, 532, "RAZ", 1, 1, 0, 0},
|
|
{"SESREQSCS" , 0, 1, 533, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SESREQ" , 1, 1, 533, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_7" , 2, 6, 533, "RAZ", 1, 1, 0, 0},
|
|
{"HSTNEGSCS" , 8, 1, 533, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HNPREQ" , 9, 1, 533, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HSTSETHNPEN" , 10, 1, 533, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DEVHNPEN" , 11, 1, 533, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_15" , 12, 4, 533, "RAZ", 1, 1, 0, 0},
|
|
{"CONIDSTS" , 16, 1, 533, "RO", 1, 1, 0, 0},
|
|
{"DBNCTIME" , 17, 1, 533, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASESVLD" , 18, 1, 533, "RO", 1, 1, 0, 0},
|
|
{"BSESVLD" , 19, 1, 533, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_20_31" , 20, 12, 533, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 534, "RAZ", 1, 1, 0, 0},
|
|
{"SESENDDET" , 2, 1, 534, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_7" , 3, 5, 534, "RAZ", 1, 1, 0, 0},
|
|
{"SESREQSUCSTSCHNG" , 8, 1, 534, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"HSTNEGSUCSTSCHNG" , 9, 1, 534, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_16" , 10, 7, 534, "RAZ", 1, 1, 0, 0},
|
|
{"HSTNEGDET" , 17, 1, 534, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ADEVTOUTCHG" , 18, 1, 534, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DBNCEDONE" , 19, 1, 534, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 534, "RAZ", 1, 1, 0, 0},
|
|
{"CSFTRST" , 0, 1, 535, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HSFTRST" , 1, 1, 535, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMCNTRRST" , 2, 1, 535, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTKNQFLSH" , 3, 1, 535, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RXFFLSH" , 4, 1, 535, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFFLSH" , 5, 1, 535, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFNUM" , 6, 5, 535, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_29" , 11, 19, 535, "RAZ", 1, 1, 0, 0},
|
|
{"DMAREQ" , 30, 1, 535, "RO", 0, 0, 0ull, 0ull},
|
|
{"AHBIDLE" , 31, 1, 535, "RO", 0, 0, 1ull, 1ull},
|
|
{"RXFDEP" , 0, 16, 536, "R/W", 0, 0, 1824ull, 456ull},
|
|
{"RESERVED_16_31" , 16, 16, 536, "RAZ", 1, 1, 0, 0},
|
|
{"EPNUM" , 0, 4, 537, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 537, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 537, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 537, "RO", 0, 0, 0ull, 0ull},
|
|
{"FN" , 21, 4, 537, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_31" , 25, 7, 537, "RAZ", 1, 1, 0, 0},
|
|
{"CHNUM" , 0, 4, 538, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 538, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 538, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 538, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 538, "RAZ", 1, 1, 0, 0},
|
|
{"EPNUM" , 0, 4, 539, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 539, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 539, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 539, "RO", 0, 0, 0ull, 0ull},
|
|
{"FN" , 21, 4, 539, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_31" , 25, 7, 539, "RAZ", 1, 1, 0, 0},
|
|
{"CHNUM" , 0, 4, 540, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 540, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 540, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 540, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 540, "RAZ", 1, 1, 0, 0},
|
|
{"SYNOPSYSID" , 0, 32, 541, "RO", 1, 1, 0, 0},
|
|
{"TOUTCAL" , 0, 3, 542, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHYIF" , 3, 1, 542, "RO", 0, 0, 1ull, 1ull},
|
|
{"ULPI_UTMI_SEL" , 4, 1, 542, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSINTF" , 5, 1, 542, "WO", 0, 0, 0ull, 0ull},
|
|
{"PHYSEL" , 6, 1, 542, "WO", 0, 0, 0ull, 0ull},
|
|
{"DDRSEL" , 7, 1, 542, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SRPCAP" , 8, 1, 542, "RO", 0, 0, 0ull, 0ull},
|
|
{"HNPCAP" , 9, 1, 542, "RO", 0, 0, 0ull, 0ull},
|
|
{"USBTRDTIM" , 10, 4, 542, "R/W", 0, 0, 5ull, 5ull},
|
|
{"RESERVED_14_14" , 14, 1, 542, "RAZ", 1, 1, 0, 0},
|
|
{"PHYLPWRCLKSEL" , 15, 1, 542, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OTGI2CSEL" , 16, 1, 542, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 542, "RAZ", 1, 1, 0, 0},
|
|
{"HAINT" , 0, 16, 543, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_31" , 16, 16, 543, "RAZ", 1, 1, 0, 0},
|
|
{"HAINTMSK" , 0, 16, 544, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_31" , 16, 16, 544, "RAZ", 1, 1, 0, 0},
|
|
{"MPS" , 0, 11, 545, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPNUM" , 11, 4, 545, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPDIR" , 15, 1, 545, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 545, "RAZ", 1, 1, 0, 0},
|
|
{"LSPDDEV" , 17, 1, 545, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPTYPE" , 18, 2, 545, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EC" , 20, 2, 545, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DEVADDR" , 22, 7, 545, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ODDFRM" , 29, 1, 545, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHDIS" , 30, 1, 545, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHENA" , 31, 1, 545, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSLSPCLKSEL" , 0, 2, 546, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSLSSUPP" , 2, 1, 546, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_31" , 3, 29, 546, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPL" , 0, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CHHLTD" , 1, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AHBERR" , 2, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"STALL" , 3, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NAK" , 4, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ACK" , 5, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NYET" , 6, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"XACTERR" , 7, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BBLERR" , 8, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FRMOVRUN" , 9, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DATATGLERR" , 10, 1, 547, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_31" , 11, 21, 547, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPLMSK" , 0, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHHLTDMSK" , 1, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AHBERRMSK" , 2, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STALLMSK" , 3, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NAKMSK" , 4, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ACKMSK" , 5, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NYETMSK" , 6, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XACTERRMSK" , 7, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BBLERRMSK" , 8, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMOVRUNMSK" , 9, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DATATGLERRMSK" , 10, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_31" , 11, 21, 548, "RAZ", 1, 1, 0, 0},
|
|
{"PRTADDR" , 0, 7, 549, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HUBADDR" , 7, 7, 549, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XACTPOS" , 14, 2, 549, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COMPSPLT" , 16, 1, 549, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_30" , 17, 14, 549, "RAZ", 1, 1, 0, 0},
|
|
{"SPLTENA" , 31, 1, 549, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XFERSIZE" , 0, 19, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKTCNT" , 19, 10, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PID" , 29, 2, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DOPNG" , 31, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRINT" , 0, 16, 551, "R/W", 0, 0, 2959ull, 3750ull},
|
|
{"RESERVED_16_31" , 16, 16, 551, "RAZ", 1, 1, 0, 0},
|
|
{"FRNUM" , 0, 16, 552, "RO", 0, 0, 16383ull, 0ull},
|
|
{"FRREM" , 16, 16, 552, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTCONNSTS" , 0, 1, 553, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTCONNDET" , 1, 1, 553, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTENA" , 2, 1, 553, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTENCHNG" , 3, 1, 553, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTOVRCURRACT" , 4, 1, 553, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTOVRCURRCHNG" , 5, 1, 553, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTRES" , 6, 1, 553, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTSUSP" , 7, 1, 553, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTRST" , 8, 1, 553, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 553, "RAZ", 1, 1, 0, 0},
|
|
{"PRTLNSTS" , 10, 2, 553, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTPWR" , 12, 1, 553, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTTSTCTL" , 13, 4, 553, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTSPD" , 17, 2, 553, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_31" , 19, 13, 553, "RAZ", 1, 1, 0, 0},
|
|
{"PTXFSTADDR" , 0, 16, 554, "R/W", 0, 0, 3648ull, 912ull},
|
|
{"PTXFSIZE" , 16, 16, 554, "R/W", 0, 0, 256ull, 456ull},
|
|
{"PTXFSPCAVAIL" , 0, 16, 555, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTXQSPCAVAIL" , 16, 8, 555, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTXQTOP" , 24, 8, 555, "RO", 0, 0, 0ull, 0ull},
|
|
{"DATA" , 0, 32, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STOPPCLK" , 0, 1, 557, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GATEHCLK" , 1, 1, 557, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PWRCLMP" , 2, 1, 557, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSTPDWNMODULE" , 3, 1, 557, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHYSUSPENDED" , 4, 1, 557, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 557, "RAZ", 1, 1, 0, 0},
|
|
{"NOF_BIS" , 0, 1, 558, "RO", 0, 0, 0ull, 0ull},
|
|
{"NIF_BIS" , 1, 1, 558, "RO", 0, 0, 0ull, 0ull},
|
|
{"USBC_BIS" , 2, 1, 558, "RO", 0, 0, 0ull, 0ull},
|
|
{"N2UF_BIS" , 3, 1, 558, "RO", 0, 0, 0ull, 0ull},
|
|
{"E2HC_BIS" , 4, 1, 558, "RO", 0, 0, 0ull, 0ull},
|
|
{"U2NF_BIS" , 5, 1, 558, "RO", 0, 0, 0ull, 0ull},
|
|
{"U2NC_BIS" , 6, 1, 558, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 558, "RAZ", 1, 1, 0, 0},
|
|
{"DIVIDE" , 0, 3, 559, "R/W", 0, 0, 4ull, 0ull},
|
|
{"HRST" , 3, 1, 559, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PRST" , 4, 1, 559, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ENABLE" , 5, 1, 559, "R/W", 0, 0, 1ull, 1ull},
|
|
{"POR" , 6, 1, 559, "R/W", 0, 0, 1ull, 0ull},
|
|
{"S_BIST" , 7, 1, 559, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SD_MODE" , 8, 2, 559, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CDIV_BYP" , 10, 1, 559, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_C_SEL" , 11, 2, 559, "R/W", 0, 0, 2ull, 0ull},
|
|
{"P_COM_ON" , 13, 1, 559, "R/W", 0, 0, 1ull, 1ull},
|
|
{"P_RTYPE" , 14, 2, 559, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 559, "RAZ", 1, 1, 0, 0},
|
|
{"HCLK_RST" , 17, 1, 559, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DIVIDE2" , 18, 2, 559, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_20_63" , 20, 44, 559, "RAZ", 1, 1, 0, 0},
|
|
{"L2C_EMOD" , 0, 2, 560, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INV_A2" , 2, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_TEST" , 3, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_STT" , 4, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_0PAG" , 5, 1, 560, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 560, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 561, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 561, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 562, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 562, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 563, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 563, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 564, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 564, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 565, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 565, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 566, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 566, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 567, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 567, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 568, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 568, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 569, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 569, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 570, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 570, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 571, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 571, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 572, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 572, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 573, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 573, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 574, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 574, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 575, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 575, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 576, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 576, "RAZ", 1, 1, 0, 0},
|
|
{"BURST" , 0, 4, 577, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHANNEL" , 4, 5, 577, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COUNT" , 9, 11, 577, "R/W", 0, 0, 0ull, 0ull},
|
|
{"F_ADDR" , 20, 18, 577, "R/W", 0, 0, 0ull, 0ull},
|
|
{"REQ" , 38, 1, 577, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DONE" , 39, 1, 577, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 577, "RAZ", 1, 1, 0, 0},
|
|
{"PR_PO_E" , 0, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PR_PU_F" , 1, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NR_PO_E" , 2, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NR_PU_F" , 3, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LR_PO_E" , 4, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LR_PU_F" , 5, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PT_PO_E" , 6, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PT_PU_F" , 7, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NT_PO_E" , 8, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NT_PU_F" , 9, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LT_PO_E" , 10, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LT_PU_F" , 11, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DCRED_E" , 12, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DCRED_F" , 13, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2C_S_E" , 14, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2C_A_F" , 15, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2_FI_E" , 16, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2_FI_F" , 17, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_E" , 18, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_F" , 19, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_F" , 20, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_E" , 21, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_F" , 22, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_E" , 23, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UOD_PE" , 24, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UOD_PF" , 25, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_31" , 26, 6, 578, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LTL_F_PE" , 32, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LTL_F_PF" , 33, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_RPE" , 34, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_RPF" , 35, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_DPE" , 36, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_DPF" , 37, 1, 578, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 578, "RAZ", 1, 1, 0, 0},
|
|
{"PR_PO_E" , 0, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PR_PU_F" , 1, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NR_PO_E" , 2, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NR_PU_F" , 3, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LR_PO_E" , 4, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LR_PU_F" , 5, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PT_PO_E" , 6, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PT_PU_F" , 7, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NT_PO_E" , 8, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NT_PU_F" , 9, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LT_PO_E" , 10, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LT_PU_F" , 11, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCRED_E" , 12, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCRED_F" , 13, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"L2C_S_E" , 14, 1, 579, "R/W1C", 1, 0, 0, 0ull},
|
|
{"L2C_A_F" , 15, 1, 579, "R/W1C", 1, 0, 0, 0ull},
|
|
{"LT_FI_E" , 16, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LT_FI_F" , 17, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_E" , 18, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_F" , 19, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_F" , 20, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_E" , 21, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_F" , 22, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_E" , 23, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UOD_PE" , 24, 1, 579, "R/W1C", 1, 0, 0, 0ull},
|
|
{"UOD_PF" , 25, 1, 579, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_26_31" , 26, 6, 579, "RAZ", 1, 0, 0, 0ull},
|
|
{"LTL_F_PE" , 32, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LTL_F_PF" , 33, 1, 579, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ND4O_RPE" , 34, 1, 579, "R/W1C", 1, 0, 0, 0ull},
|
|
{"ND4O_RPF" , 35, 1, 579, "R/W1C", 1, 0, 0, 0ull},
|
|
{"ND4O_DPE" , 36, 1, 579, "R/W1C", 1, 0, 0, 0ull},
|
|
{"ND4O_DPF" , 37, 1, 579, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 579, "RAZ", 1, 1, 0, 0},
|
|
{"ATE_RESET" , 0, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TDATA_IN" , 1, 8, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TADDR_IN" , 9, 4, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TDATA_SEL" , 13, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BIST_ENB" , 14, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VTEST_ENB" , 15, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LOOP_ENB" , 16, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TX_BS_EN" , 17, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TX_BS_ENH" , 18, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_22" , 19, 4, 580, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"HST_MODE" , 23, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DM_PULLD" , 24, 1, 580, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DP_PULLD" , 25, 1, 580, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TCLK" , 26, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBP_BIST" , 27, 1, 580, "R/W", 0, 0, 1ull, 1ull},
|
|
{"USBC_END" , 28, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_BMODE" , 29, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXPREEMPHASISTUNE" , 30, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_31" , 31, 1, 580, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TDATA_OUT" , 32, 4, 580, "RO", 1, 1, 0, 0},
|
|
{"BIST_ERR" , 36, 1, 580, "RO", 0, 0, 0ull, 0ull},
|
|
{"BIST_DONE" , 37, 1, 580, "RO", 0, 0, 0ull, 0ull},
|
|
{"HSBIST" , 38, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSBIST" , 39, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LSBIST" , 40, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRVVBUS" , 41, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PORTRESET" , 42, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OTGDISABLE" , 43, 1, 580, "R/W", 0, 0, 1ull, 1ull},
|
|
{"OTGTUNE" , 44, 3, 580, "R/W", 0, 0, 2ull, 2ull},
|
|
{"COMPDISTUNE" , 47, 3, 580, "R/W", 0, 0, 2ull, 2ull},
|
|
{"SQRXTUNE" , 50, 3, 580, "R/W", 0, 0, 3ull, 3ull},
|
|
{"TXHSXVTUNE" , 53, 2, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFSLSTUNE" , 55, 4, 580, "R/W", 0, 0, 3ull, 3ull},
|
|
{"TXVREFTUNE" , 59, 4, 580, "R/W", 0, 0, 7ull, 7ull},
|
|
{"TXRISETUNE" , 63, 1, 580, "R/W", 0, 0, 0ull, 0ull},
|
|
{NULL,0,0,0,0,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn52xxp1[] = {
|
|
/* name , ---------------type, bits, off, #field, fld of */
|
|
{"cvmx_agl_gmx_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 14, 0},
|
|
{"cvmx_agl_gmx_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 1, 2, 14},
|
|
{"cvmx_agl_gmx_drv_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 12, 16},
|
|
{"cvmx_agl_gmx_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 3, 3, 28},
|
|
{"cvmx_agl_gmx_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 7, 31},
|
|
{"cvmx_agl_gmx_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 1, 38},
|
|
{"cvmx_agl_gmx_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 8, 1, 39},
|
|
{"cvmx_agl_gmx_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 1, 40},
|
|
{"cvmx_agl_gmx_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 1, 41},
|
|
{"cvmx_agl_gmx_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 1, 42},
|
|
{"cvmx_agl_gmx_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 1, 43},
|
|
{"cvmx_agl_gmx_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 18, 2, 44},
|
|
{"cvmx_agl_gmx_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 20, 4, 46},
|
|
{"cvmx_agl_gmx_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 22, 2, 50},
|
|
{"cvmx_agl_gmx_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 24, 10, 52},
|
|
{"cvmx_agl_gmx_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 26, 11, 62},
|
|
{"cvmx_agl_gmx_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 28, 2, 73},
|
|
{"cvmx_agl_gmx_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 30, 2, 75},
|
|
{"cvmx_agl_gmx_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 32, 2, 77},
|
|
{"cvmx_agl_gmx_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 34, 19, 79},
|
|
{"cvmx_agl_gmx_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 36, 19, 98},
|
|
{"cvmx_agl_gmx_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 38, 2, 117},
|
|
{"cvmx_agl_gmx_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 40, 2, 119},
|
|
{"cvmx_agl_gmx_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 42, 2, 121},
|
|
{"cvmx_agl_gmx_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 44, 2, 123},
|
|
{"cvmx_agl_gmx_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 46, 2, 125},
|
|
{"cvmx_agl_gmx_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 48, 2, 127},
|
|
{"cvmx_agl_gmx_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 50, 2, 129},
|
|
{"cvmx_agl_gmx_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 2, 131},
|
|
{"cvmx_agl_gmx_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 54, 2, 133},
|
|
{"cvmx_agl_gmx_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 56, 2, 135},
|
|
{"cvmx_agl_gmx_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 58, 2, 137},
|
|
{"cvmx_agl_gmx_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 60, 2, 139},
|
|
{"cvmx_agl_gmx_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 62, 4, 141},
|
|
{"cvmx_agl_gmx_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 64, 2, 145},
|
|
{"cvmx_agl_gmx_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 66, 2, 147},
|
|
{"cvmx_agl_gmx_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 68, 2, 149},
|
|
{"cvmx_agl_gmx_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 70, 4, 151},
|
|
{"cvmx_agl_gmx_rx_tx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 71, 4, 155},
|
|
{"cvmx_agl_gmx_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 72, 2, 159},
|
|
{"cvmx_agl_gmx_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 74, 3, 161},
|
|
{"cvmx_agl_gmx_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 75, 5, 164},
|
|
{"cvmx_agl_gmx_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 77, 3, 169},
|
|
{"cvmx_agl_gmx_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 79, 2, 172},
|
|
{"cvmx_agl_gmx_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 81, 2, 174},
|
|
{"cvmx_agl_gmx_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 83, 2, 176},
|
|
{"cvmx_agl_gmx_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 85, 2, 178},
|
|
{"cvmx_agl_gmx_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 87, 2, 180},
|
|
{"cvmx_agl_gmx_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 89, 2, 182},
|
|
{"cvmx_agl_gmx_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 91, 2, 184},
|
|
{"cvmx_agl_gmx_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 93, 2, 186},
|
|
{"cvmx_agl_gmx_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 95, 2, 188},
|
|
{"cvmx_agl_gmx_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 97, 2, 190},
|
|
{"cvmx_agl_gmx_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 99, 2, 192},
|
|
{"cvmx_agl_gmx_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 101, 2, 194},
|
|
{"cvmx_agl_gmx_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 103, 2, 196},
|
|
{"cvmx_agl_gmx_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 105, 2, 198},
|
|
{"cvmx_agl_gmx_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 107, 2, 200},
|
|
{"cvmx_agl_gmx_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 109, 2, 202},
|
|
{"cvmx_agl_gmx_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 111, 2, 204},
|
|
{"cvmx_agl_gmx_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 113, 2, 206},
|
|
{"cvmx_agl_gmx_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 115, 2, 208},
|
|
{"cvmx_agl_gmx_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 116, 2, 210},
|
|
{"cvmx_agl_gmx_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 117, 3, 212},
|
|
{"cvmx_agl_gmx_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 118, 10, 215},
|
|
{"cvmx_agl_gmx_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 119, 10, 225},
|
|
{"cvmx_agl_gmx_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 120, 2, 235},
|
|
{"cvmx_agl_gmx_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 121, 2, 237},
|
|
{"cvmx_agl_gmx_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 122, 6, 239},
|
|
{"cvmx_agl_gmx_tx_pause_pkt_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 123, 2, 245},
|
|
{"cvmx_agl_gmx_tx_pause_pkt_type", CVMX_CSR_DB_TYPE_RSL, 64, 124, 2, 247},
|
|
{"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 125, 2, 249},
|
|
{"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 126, 2, 251},
|
|
{"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 127, 2, 253},
|
|
{"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 128, 2, 255},
|
|
{"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 129, 22, 257},
|
|
{"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 138, 6, 279},
|
|
{"cvmx_ciu_int#_en4_0" , CVMX_CSR_DB_TYPE_NCB, 64, 147, 22, 285},
|
|
{"cvmx_ciu_int#_en4_1" , CVMX_CSR_DB_TYPE_NCB, 64, 151, 6, 307},
|
|
{"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 155, 22, 313},
|
|
{"cvmx_ciu_int#_sum4" , CVMX_CSR_DB_TYPE_NCB, 64, 164, 22, 335},
|
|
{"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 168, 6, 357},
|
|
{"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 169, 2, 363},
|
|
{"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 173, 2, 365},
|
|
{"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 177, 2, 367},
|
|
{"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 178, 2, 369},
|
|
{"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 179, 2, 371},
|
|
{"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 180, 1, 373},
|
|
{"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 184, 3, 374},
|
|
{"cvmx_ciu_qlm_dcok" , CVMX_CSR_DB_TYPE_NCB, 64, 185, 2, 377},
|
|
{"cvmx_ciu_qlm_jtgc" , CVMX_CSR_DB_TYPE_NCB, 64, 186, 6, 379},
|
|
{"cvmx_ciu_qlm_jtgd" , CVMX_CSR_DB_TYPE_NCB, 64, 187, 8, 385},
|
|
{"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 188, 2, 393},
|
|
{"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 189, 2, 395},
|
|
{"cvmx_ciu_soft_prst1" , CVMX_CSR_DB_TYPE_NCB, 64, 190, 2, 397},
|
|
{"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 191, 2, 399},
|
|
{"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 192, 3, 401},
|
|
{"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 196, 7, 404},
|
|
{"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 200, 6, 411},
|
|
{"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 201, 7, 417},
|
|
{"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 202, 29, 424},
|
|
{"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 203, 29, 453},
|
|
{"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 204, 2, 482},
|
|
{"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 212, 2, 484},
|
|
{"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 220, 3, 486},
|
|
{"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 221, 3, 489},
|
|
{"cvmx_fpa_wart_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 222, 2, 492},
|
|
{"cvmx_fpa_wart_status" , CVMX_CSR_DB_TYPE_RSL, 64, 223, 2, 494},
|
|
{"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 224, 7, 496},
|
|
{"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 225, 2, 503},
|
|
{"cvmx_gmx#_clk_en" , CVMX_CSR_DB_TYPE_RSL, 64, 226, 2, 505},
|
|
{"cvmx_gmx#_hg2_control" , CVMX_CSR_DB_TYPE_RSL, 64, 227, 5, 507},
|
|
{"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 228, 7, 512},
|
|
{"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 229, 2, 519},
|
|
{"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 230, 10, 521},
|
|
{"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 234, 1, 531},
|
|
{"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 238, 1, 532},
|
|
{"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 242, 1, 533},
|
|
{"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 246, 1, 534},
|
|
{"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 250, 1, 535},
|
|
{"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 254, 1, 536},
|
|
{"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 258, 2, 537},
|
|
{"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 262, 4, 539},
|
|
{"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 266, 2, 543},
|
|
{"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 270, 9, 545},
|
|
{"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 274, 11, 554},
|
|
{"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 278, 2, 565},
|
|
{"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 282, 27, 567},
|
|
{"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 286, 27, 594},
|
|
{"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 290, 2, 621},
|
|
{"cvmx_gmx#_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 294, 2, 623},
|
|
{"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 298, 2, 625},
|
|
{"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 302, 2, 627},
|
|
{"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 306, 2, 629},
|
|
{"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 310, 2, 631},
|
|
{"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 314, 2, 633},
|
|
{"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 318, 2, 635},
|
|
{"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 322, 2, 637},
|
|
{"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 326, 2, 639},
|
|
{"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 330, 2, 641},
|
|
{"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 334, 2, 643},
|
|
{"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 338, 4, 645},
|
|
{"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 342, 2, 649},
|
|
{"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 346, 2, 651},
|
|
{"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 350, 2, 653},
|
|
{"cvmx_gmx#_rx_hg2_status" , CVMX_CSR_DB_TYPE_RSL, 64, 354, 4, 655},
|
|
{"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 355, 4, 659},
|
|
{"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 356, 2, 663},
|
|
{"cvmx_gmx#_rx_xaui_bad_col" , CVMX_CSR_DB_TYPE_RSL, 64, 357, 5, 665},
|
|
{"cvmx_gmx#_rx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 358, 2, 670},
|
|
{"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 359, 2, 672},
|
|
{"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 363, 3, 674},
|
|
{"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 364, 5, 677},
|
|
{"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 368, 2, 682},
|
|
{"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 372, 3, 684},
|
|
{"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 376, 2, 687},
|
|
{"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 380, 2, 689},
|
|
{"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 384, 2, 691},
|
|
{"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 388, 3, 693},
|
|
{"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 392, 2, 696},
|
|
{"cvmx_gmx#_tx#_sgmii_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 396, 2, 698},
|
|
{"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 400, 2, 700},
|
|
{"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 404, 2, 702},
|
|
{"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 408, 2, 704},
|
|
{"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 412, 2, 706},
|
|
{"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 416, 2, 708},
|
|
{"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 420, 2, 710},
|
|
{"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 424, 2, 712},
|
|
{"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 428, 2, 714},
|
|
{"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 432, 2, 716},
|
|
{"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 436, 2, 718},
|
|
{"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 440, 2, 720},
|
|
{"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 444, 2, 722},
|
|
{"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 448, 2, 724},
|
|
{"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 452, 2, 726},
|
|
{"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 456, 2, 728},
|
|
{"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 457, 2, 730},
|
|
{"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 458, 2, 732},
|
|
{"cvmx_gmx#_tx_hg2_reg1" , CVMX_CSR_DB_TYPE_RSL, 64, 459, 2, 734},
|
|
{"cvmx_gmx#_tx_hg2_reg2" , CVMX_CSR_DB_TYPE_RSL, 64, 460, 2, 736},
|
|
{"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 461, 3, 738},
|
|
{"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 462, 8, 741},
|
|
{"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 463, 8, 749},
|
|
{"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 464, 2, 757},
|
|
{"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 465, 2, 759},
|
|
{"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 466, 6, 761},
|
|
{"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 467, 2, 767},
|
|
{"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 468, 2, 769},
|
|
{"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 469, 2, 771},
|
|
{"cvmx_gmx#_tx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 470, 9, 773},
|
|
{"cvmx_gmx#_xaui_ext_loopback" , CVMX_CSR_DB_TYPE_RSL, 64, 471, 3, 782},
|
|
{"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 472, 9, 785},
|
|
{"cvmx_gpio_clk_gen#" , CVMX_CSR_DB_TYPE_NCB, 64, 488, 2, 794},
|
|
{"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 492, 2, 796},
|
|
{"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 493, 2, 798},
|
|
{"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 494, 2, 800},
|
|
{"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 495, 2, 802},
|
|
{"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 496, 19, 804},
|
|
{"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 497, 6, 823},
|
|
{"cvmx_iob_dwb_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 498, 3, 829},
|
|
{"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 499, 3, 832},
|
|
{"cvmx_iob_i2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 500, 3, 835},
|
|
{"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 501, 5, 838},
|
|
{"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 502, 5, 843},
|
|
{"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 503, 1, 848},
|
|
{"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 504, 1, 849},
|
|
{"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 505, 7, 850},
|
|
{"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 506, 7, 857},
|
|
{"cvmx_iob_n2c_l2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 507, 3, 864},
|
|
{"cvmx_iob_n2c_rsp_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 508, 3, 867},
|
|
{"cvmx_iob_outb_com_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 509, 3, 870},
|
|
{"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 510, 5, 873},
|
|
{"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 511, 5, 878},
|
|
{"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 512, 1, 883},
|
|
{"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 513, 1, 884},
|
|
{"cvmx_iob_outb_fpa_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 514, 3, 885},
|
|
{"cvmx_iob_outb_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 515, 3, 888},
|
|
{"cvmx_iob_p2c_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 516, 3, 891},
|
|
{"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 517, 2, 894},
|
|
{"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 518, 2, 896},
|
|
{"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 519, 2, 898},
|
|
{"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 520, 2, 900},
|
|
{"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 521, 19, 902},
|
|
{"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 522, 2, 921},
|
|
{"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 523, 1, 923},
|
|
{"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 524, 15, 924},
|
|
{"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 525, 13, 939},
|
|
{"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 526, 13, 952},
|
|
{"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 527, 2, 965},
|
|
{"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 528, 2, 967},
|
|
{"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 529, 2, 969},
|
|
{"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 530, 3, 971},
|
|
{"cvmx_ipd_port#_bp_page_cnt2" , CVMX_CSR_DB_TYPE_NCB, 64, 534, 3, 974},
|
|
{"cvmx_ipd_port_bp_counters2_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 538, 2, 977},
|
|
{"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 542, 2, 979},
|
|
{"cvmx_ipd_port_qos_#_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 546, 2, 981},
|
|
{"cvmx_ipd_port_qos_int#" , CVMX_CSR_DB_TYPE_NCB, 64, 610, 1, 983},
|
|
{"cvmx_ipd_port_qos_int_enb#" , CVMX_CSR_DB_TYPE_NCB, 64, 612, 1, 984},
|
|
{"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 614, 6, 985},
|
|
{"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 615, 5, 991},
|
|
{"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 616, 6, 996},
|
|
{"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 617, 7, 1002},
|
|
{"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 618, 2, 1009},
|
|
{"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 626, 2, 1011},
|
|
{"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 627, 3, 1013},
|
|
{"cvmx_ipd_red_port_enable2" , CVMX_CSR_DB_TYPE_NCB, 64, 628, 2, 1016},
|
|
{"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 629, 5, 1018},
|
|
{"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 637, 3, 1023},
|
|
{"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 638, 4, 1026},
|
|
{"cvmx_ipd_sub_port_qos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 639, 3, 1030},
|
|
{"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 640, 2, 1033},
|
|
{"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 641, 2, 1035},
|
|
{"cvmx_l2c_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 642, 8, 1037},
|
|
{"cvmx_l2c_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 643, 9, 1045},
|
|
{"cvmx_l2c_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 644, 8, 1054},
|
|
{"cvmx_l2c_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 645, 12, 1062},
|
|
{"cvmx_l2c_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 646, 9, 1074},
|
|
{"cvmx_l2c_dut" , CVMX_CSR_DB_TYPE_RSL, 64, 647, 5, 1083},
|
|
{"cvmx_l2c_grpwrr0" , CVMX_CSR_DB_TYPE_RSL, 64, 648, 2, 1088},
|
|
{"cvmx_l2c_grpwrr1" , CVMX_CSR_DB_TYPE_RSL, 64, 649, 2, 1090},
|
|
{"cvmx_l2c_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 650, 10, 1092},
|
|
{"cvmx_l2c_int_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 651, 10, 1102},
|
|
{"cvmx_l2c_lckbase" , CVMX_CSR_DB_TYPE_RSL, 64, 652, 4, 1112},
|
|
{"cvmx_l2c_lckoff" , CVMX_CSR_DB_TYPE_RSL, 64, 653, 2, 1116},
|
|
{"cvmx_l2c_lfb0" , CVMX_CSR_DB_TYPE_RSL, 64, 654, 16, 1118},
|
|
{"cvmx_l2c_lfb1" , CVMX_CSR_DB_TYPE_RSL, 64, 655, 19, 1134},
|
|
{"cvmx_l2c_lfb2" , CVMX_CSR_DB_TYPE_RSL, 64, 656, 3, 1153},
|
|
{"cvmx_l2c_lfb3" , CVMX_CSR_DB_TYPE_RSL, 64, 657, 4, 1156},
|
|
{"cvmx_l2c_oob" , CVMX_CSR_DB_TYPE_RSL, 64, 658, 3, 1160},
|
|
{"cvmx_l2c_oob1" , CVMX_CSR_DB_TYPE_RSL, 64, 659, 6, 1163},
|
|
{"cvmx_l2c_oob2" , CVMX_CSR_DB_TYPE_RSL, 64, 660, 6, 1169},
|
|
{"cvmx_l2c_oob3" , CVMX_CSR_DB_TYPE_RSL, 64, 661, 6, 1175},
|
|
{"cvmx_l2c_pfc#" , CVMX_CSR_DB_TYPE_RSL, 64, 662, 2, 1181},
|
|
{"cvmx_l2c_pfctl" , CVMX_CSR_DB_TYPE_RSL, 64, 666, 17, 1183},
|
|
{"cvmx_l2c_ppgrp" , CVMX_CSR_DB_TYPE_RSL, 64, 667, 5, 1200},
|
|
{"cvmx_l2c_spar0" , CVMX_CSR_DB_TYPE_RSL, 64, 668, 5, 1205},
|
|
{"cvmx_l2c_spar4" , CVMX_CSR_DB_TYPE_RSL, 64, 669, 2, 1210},
|
|
{"cvmx_l2d_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 670, 3, 1212},
|
|
{"cvmx_l2d_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 671, 2, 1215},
|
|
{"cvmx_l2d_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 672, 2, 1217},
|
|
{"cvmx_l2d_bst3" , CVMX_CSR_DB_TYPE_RSL, 64, 673, 2, 1219},
|
|
{"cvmx_l2d_err" , CVMX_CSR_DB_TYPE_RSL, 64, 674, 7, 1221},
|
|
{"cvmx_l2d_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 675, 5, 1228},
|
|
{"cvmx_l2d_fsyn0" , CVMX_CSR_DB_TYPE_RSL, 64, 676, 3, 1233},
|
|
{"cvmx_l2d_fsyn1" , CVMX_CSR_DB_TYPE_RSL, 64, 677, 3, 1236},
|
|
{"cvmx_l2d_fus0" , CVMX_CSR_DB_TYPE_RSL, 64, 678, 2, 1239},
|
|
{"cvmx_l2d_fus1" , CVMX_CSR_DB_TYPE_RSL, 64, 679, 2, 1241},
|
|
{"cvmx_l2d_fus2" , CVMX_CSR_DB_TYPE_RSL, 64, 680, 2, 1243},
|
|
{"cvmx_l2d_fus3" , CVMX_CSR_DB_TYPE_RSL, 64, 681, 6, 1245},
|
|
{"cvmx_l2t_err" , CVMX_CSR_DB_TYPE_RSL, 64, 682, 14, 1251},
|
|
{"cvmx_lmc#_bist_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 683, 2, 1265},
|
|
{"cvmx_lmc#_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 684, 8, 1267},
|
|
{"cvmx_lmc#_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 685, 7, 1275},
|
|
{"cvmx_lmc#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 686, 19, 1282},
|
|
{"cvmx_lmc#_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 687, 8, 1301},
|
|
{"cvmx_lmc#_dclk_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 688, 2, 1309},
|
|
{"cvmx_lmc#_dclk_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 689, 2, 1311},
|
|
{"cvmx_lmc#_ddr2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 690, 18, 1313},
|
|
{"cvmx_lmc#_delay_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 691, 6, 1331},
|
|
{"cvmx_lmc#_dll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 692, 5, 1337},
|
|
{"cvmx_lmc#_dual_memcfg" , CVMX_CSR_DB_TYPE_RSL, 64, 693, 5, 1342},
|
|
{"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 694, 5, 1347},
|
|
{"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 695, 6, 1352},
|
|
{"cvmx_lmc#_ifb_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 696, 2, 1358},
|
|
{"cvmx_lmc#_ifb_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 697, 2, 1360},
|
|
{"cvmx_lmc#_mem_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 698, 14, 1362},
|
|
{"cvmx_lmc#_mem_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 699, 9, 1376},
|
|
{"cvmx_lmc#_ops_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 700, 2, 1385},
|
|
{"cvmx_lmc#_ops_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 701, 2, 1387},
|
|
{"cvmx_lmc#_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 702, 14, 1389},
|
|
{"cvmx_lmc#_pll_status" , CVMX_CSR_DB_TYPE_RSL, 64, 703, 6, 1403},
|
|
{"cvmx_lmc#_read_level_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 704, 7, 1409},
|
|
{"cvmx_lmc#_read_level_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 705, 4, 1416},
|
|
{"cvmx_lmc#_read_level_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 706, 11, 1420},
|
|
{"cvmx_lmc#_rodt_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 710, 6, 1431},
|
|
{"cvmx_lmc#_rodt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 711, 9, 1437},
|
|
{"cvmx_lmc#_wodt_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 712, 5, 1446},
|
|
{"cvmx_lmc#_wodt_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 713, 5, 1451},
|
|
{"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 714, 5, 1456},
|
|
{"cvmx_mio_boot_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 715, 3, 1461},
|
|
{"cvmx_mio_boot_dma_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 716, 10, 1464},
|
|
{"cvmx_mio_boot_dma_int#" , CVMX_CSR_DB_TYPE_RSL, 64, 718, 3, 1474},
|
|
{"cvmx_mio_boot_dma_int_en#" , CVMX_CSR_DB_TYPE_RSL, 64, 720, 3, 1477},
|
|
{"cvmx_mio_boot_dma_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 722, 15, 1480},
|
|
{"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 724, 3, 1495},
|
|
{"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 725, 3, 1498},
|
|
{"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 726, 3, 1501},
|
|
{"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 727, 5, 1504},
|
|
{"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 729, 1, 1509},
|
|
{"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 730, 13, 1510},
|
|
{"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 738, 13, 1523},
|
|
{"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 746, 6, 1536},
|
|
{"cvmx_mio_fus_bnk_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 747, 1, 1542},
|
|
{"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 751, 2, 1543},
|
|
{"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 752, 2, 1545},
|
|
{"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 753, 13, 1547},
|
|
{"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 754, 8, 1560},
|
|
{"cvmx_mio_fus_ema" , CVMX_CSR_DB_TYPE_RSL, 64, 755, 4, 1568},
|
|
{"cvmx_mio_fus_pdf" , CVMX_CSR_DB_TYPE_RSL, 64, 756, 1, 1572},
|
|
{"cvmx_mio_fus_pll" , CVMX_CSR_DB_TYPE_RSL, 64, 757, 3, 1573},
|
|
{"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 758, 2, 1576},
|
|
{"cvmx_mio_fus_prog_times" , CVMX_CSR_DB_TYPE_RSL, 64, 759, 6, 1578},
|
|
{"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 760, 7, 1584},
|
|
{"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 761, 4, 1591},
|
|
{"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 762, 2, 1595},
|
|
{"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 763, 2, 1597},
|
|
{"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 764, 13, 1599},
|
|
{"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 766, 12, 1612},
|
|
{"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 768, 3, 1624},
|
|
{"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 770, 3, 1627},
|
|
{"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 772, 2, 1630},
|
|
{"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 774, 2, 1632},
|
|
{"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 776, 2, 1634},
|
|
{"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 778, 7, 1636},
|
|
{"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 780, 2, 1643},
|
|
{"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 782, 7, 1645},
|
|
{"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 784, 4, 1652},
|
|
{"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 786, 8, 1656},
|
|
{"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 788, 9, 1664},
|
|
{"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 790, 7, 1673},
|
|
{"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 792, 9, 1680},
|
|
{"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 794, 2, 1689},
|
|
{"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 796, 2, 1691},
|
|
{"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 798, 4, 1693},
|
|
{"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 800, 2, 1697},
|
|
{"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 802, 2, 1699},
|
|
{"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 804, 2, 1701},
|
|
{"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 806, 4, 1703},
|
|
{"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 808, 2, 1707},
|
|
{"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 810, 2, 1709},
|
|
{"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 812, 2, 1711},
|
|
{"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 814, 2, 1713},
|
|
{"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 816, 2, 1715},
|
|
{"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 818, 2, 1717},
|
|
{"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 820, 6, 1719},
|
|
{"cvmx_mio_uart2_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 822, 2, 1725},
|
|
{"cvmx_mio_uart2_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 823, 2, 1727},
|
|
{"cvmx_mio_uart2_far" , CVMX_CSR_DB_TYPE_RSL, 64, 824, 2, 1729},
|
|
{"cvmx_mio_uart2_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 825, 7, 1731},
|
|
{"cvmx_mio_uart2_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 826, 2, 1738},
|
|
{"cvmx_mio_uart2_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 827, 7, 1740},
|
|
{"cvmx_mio_uart2_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 828, 4, 1747},
|
|
{"cvmx_mio_uart2_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 829, 8, 1751},
|
|
{"cvmx_mio_uart2_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 830, 9, 1759},
|
|
{"cvmx_mio_uart2_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 831, 7, 1768},
|
|
{"cvmx_mio_uart2_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 832, 9, 1775},
|
|
{"cvmx_mio_uart2_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 833, 2, 1784},
|
|
{"cvmx_mio_uart2_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 834, 2, 1786},
|
|
{"cvmx_mio_uart2_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 835, 4, 1788},
|
|
{"cvmx_mio_uart2_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 836, 2, 1792},
|
|
{"cvmx_mio_uart2_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 837, 2, 1794},
|
|
{"cvmx_mio_uart2_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 838, 2, 1796},
|
|
{"cvmx_mio_uart2_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 839, 4, 1798},
|
|
{"cvmx_mio_uart2_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 840, 2, 1802},
|
|
{"cvmx_mio_uart2_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 841, 2, 1804},
|
|
{"cvmx_mio_uart2_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 842, 2, 1806},
|
|
{"cvmx_mio_uart2_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 843, 2, 1808},
|
|
{"cvmx_mio_uart2_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 844, 2, 1810},
|
|
{"cvmx_mio_uart2_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 845, 2, 1812},
|
|
{"cvmx_mio_uart2_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 846, 6, 1814},
|
|
{"cvmx_mix#_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 847, 5, 1820},
|
|
{"cvmx_mix#_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 849, 8, 1825},
|
|
{"cvmx_mix#_intena" , CVMX_CSR_DB_TYPE_NCB, 64, 851, 8, 1833},
|
|
{"cvmx_mix#_ircnt" , CVMX_CSR_DB_TYPE_NCB, 64, 853, 2, 1841},
|
|
{"cvmx_mix#_irhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 855, 3, 1843},
|
|
{"cvmx_mix#_iring1" , CVMX_CSR_DB_TYPE_NCB, 64, 857, 5, 1846},
|
|
{"cvmx_mix#_iring2" , CVMX_CSR_DB_TYPE_NCB, 64, 859, 4, 1851},
|
|
{"cvmx_mix#_isr" , CVMX_CSR_DB_TYPE_NCB, 64, 861, 8, 1855},
|
|
{"cvmx_mix#_orcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 863, 2, 1863},
|
|
{"cvmx_mix#_orhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 865, 2, 1865},
|
|
{"cvmx_mix#_oring1" , CVMX_CSR_DB_TYPE_NCB, 64, 867, 5, 1867},
|
|
{"cvmx_mix#_oring2" , CVMX_CSR_DB_TYPE_NCB, 64, 869, 4, 1872},
|
|
{"cvmx_mix#_remcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 871, 4, 1876},
|
|
{"cvmx_npei_bar1_index#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 873, 5, 1880},
|
|
{"cvmx_npei_bist_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 905, 47, 1885},
|
|
{"cvmx_npei_ctl_port0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 906, 17, 1932},
|
|
{"cvmx_npei_ctl_port1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 907, 17, 1949},
|
|
{"cvmx_npei_ctl_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 908, 10, 1966},
|
|
{"cvmx_npei_ctl_status2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 909, 11, 1976},
|
|
{"cvmx_npei_data_out_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 910, 5, 1987},
|
|
{"cvmx_npei_dbg_data" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 911, 8, 1992},
|
|
{"cvmx_npei_dbg_select" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 912, 2, 2000},
|
|
{"cvmx_npei_dma#_counts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 913, 3, 2002},
|
|
{"cvmx_npei_dma#_dbell" , CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 917, 2, 2005},
|
|
{"cvmx_npei_dma#_ibuff_saddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 921, 3, 2007},
|
|
{"cvmx_npei_dma#_naddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 925, 2, 2010},
|
|
{"cvmx_npei_dma0_int_level" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 929, 2, 2012},
|
|
{"cvmx_npei_dma1_int_level" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 930, 2, 2014},
|
|
{"cvmx_npei_dma_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 931, 2, 2016},
|
|
{"cvmx_npei_dma_control" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 932, 15, 2018},
|
|
{"cvmx_npei_dma_state1_p1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 933, 11, 2033},
|
|
{"cvmx_npei_dma_state2_p1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 934, 6, 2044},
|
|
{"cvmx_npei_dma_state3_p1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 935, 5, 2050},
|
|
{"cvmx_npei_dma_state4_p1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 936, 5, 2055},
|
|
{"cvmx_npei_int_a_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 937, 3, 2060},
|
|
{"cvmx_npei_int_a_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 938, 3, 2063},
|
|
{"cvmx_npei_int_a_sum" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 939, 3, 2066},
|
|
{"cvmx_npei_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 940, 64, 2069},
|
|
{"cvmx_npei_int_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 941, 63, 2133},
|
|
{"cvmx_npei_int_sum" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 942, 61, 2196},
|
|
{"cvmx_npei_int_sum2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 943, 61, 2257},
|
|
{"cvmx_npei_last_win_rdata0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 944, 1, 2318},
|
|
{"cvmx_npei_last_win_rdata1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 945, 1, 2319},
|
|
{"cvmx_npei_mem_access_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 946, 3, 2320},
|
|
{"cvmx_npei_mem_access_subid#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 947, 11, 2323},
|
|
{"cvmx_npei_msi_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 963, 1, 2334},
|
|
{"cvmx_npei_msi_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 964, 1, 2335},
|
|
{"cvmx_npei_msi_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 965, 1, 2336},
|
|
{"cvmx_npei_msi_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 966, 1, 2337},
|
|
{"cvmx_npei_msi_rcv0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 967, 1, 2338},
|
|
{"cvmx_npei_msi_rcv1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 968, 1, 2339},
|
|
{"cvmx_npei_msi_rcv2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 969, 1, 2340},
|
|
{"cvmx_npei_msi_rcv3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 970, 1, 2341},
|
|
{"cvmx_npei_msi_rd_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 971, 3, 2342},
|
|
{"cvmx_npei_msi_wr_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 972, 3, 2345},
|
|
{"cvmx_npei_pcie_msi_rcv" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 973, 2, 2348},
|
|
{"cvmx_npei_pcie_msi_rcv_b1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 974, 3, 2350},
|
|
{"cvmx_npei_pcie_msi_rcv_b2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 975, 3, 2353},
|
|
{"cvmx_npei_pcie_msi_rcv_b3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 976, 3, 2356},
|
|
{"cvmx_npei_rsl_int_blocks" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 977, 29, 2359},
|
|
{"cvmx_npei_scratch_1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 978, 1, 2388},
|
|
{"cvmx_npei_state1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 979, 4, 2389},
|
|
{"cvmx_npei_state2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 980, 7, 2393},
|
|
{"cvmx_npei_state3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 981, 5, 2400},
|
|
{"cvmx_npei_win_rd_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 982, 4, 2405},
|
|
{"cvmx_npei_win_rd_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 983, 1, 2409},
|
|
{"cvmx_npei_win_wr_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 984, 4, 2410},
|
|
{"cvmx_npei_win_wr_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 985, 1, 2414},
|
|
{"cvmx_npei_win_wr_mask" , CVMX_CSR_DB_TYPE_PEXP, 64, 986, 2, 2415},
|
|
{"cvmx_npei_window_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 987, 2, 2417},
|
|
{"cvmx_pcieep_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 988, 2, 2419},
|
|
{"cvmx_pcieep_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 989, 24, 2421},
|
|
{"cvmx_pcieep_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 990, 4, 2445},
|
|
{"cvmx_pcieep_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 991, 5, 2449},
|
|
{"cvmx_pcieep_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 992, 5, 2454},
|
|
{"cvmx_pcieep_cfg004_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 993, 2, 2459},
|
|
{"cvmx_pcieep_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 994, 1, 2461},
|
|
{"cvmx_pcieep_cfg005_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 995, 1, 2462},
|
|
{"cvmx_pcieep_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 996, 5, 2463},
|
|
{"cvmx_pcieep_cfg006_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 997, 2, 2468},
|
|
{"cvmx_pcieep_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 998, 1, 2470},
|
|
{"cvmx_pcieep_cfg007_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 999, 1, 2471},
|
|
{"cvmx_pcieep_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1000, 4, 2472},
|
|
{"cvmx_pcieep_cfg008_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1001, 2, 2476},
|
|
{"cvmx_pcieep_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1002, 2, 2478},
|
|
{"cvmx_pcieep_cfg009_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1003, 1, 2480},
|
|
{"cvmx_pcieep_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1004, 1, 2481},
|
|
{"cvmx_pcieep_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1005, 2, 2482},
|
|
{"cvmx_pcieep_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1006, 3, 2484},
|
|
{"cvmx_pcieep_cfg012_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1007, 2, 2487},
|
|
{"cvmx_pcieep_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1008, 2, 2489},
|
|
{"cvmx_pcieep_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1009, 4, 2491},
|
|
{"cvmx_pcieep_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1010, 10, 2495},
|
|
{"cvmx_pcieep_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1011, 12, 2505},
|
|
{"cvmx_pcieep_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1012, 7, 2517},
|
|
{"cvmx_pcieep_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1013, 2, 2524},
|
|
{"cvmx_pcieep_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1014, 1, 2526},
|
|
{"cvmx_pcieep_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1015, 2, 2527},
|
|
{"cvmx_pcieep_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1016, 7, 2529},
|
|
{"cvmx_pcieep_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1017, 11, 2536},
|
|
{"cvmx_pcieep_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1018, 19, 2547},
|
|
{"cvmx_pcieep_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1019, 11, 2566},
|
|
{"cvmx_pcieep_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1020, 17, 2577},
|
|
{"cvmx_pcieep_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1021, 12, 2594},
|
|
{"cvmx_pcieep_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1022, 22, 2606},
|
|
{"cvmx_pcieep_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1023, 3, 2628},
|
|
{"cvmx_pcieep_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1024, 3, 2631},
|
|
{"cvmx_pcieep_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1025, 1, 2634},
|
|
{"cvmx_pcieep_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1026, 1, 2635},
|
|
{"cvmx_pcieep_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1027, 1, 2636},
|
|
{"cvmx_pcieep_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1028, 1, 2637},
|
|
{"cvmx_pcieep_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1029, 3, 2638},
|
|
{"cvmx_pcieep_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1030, 14, 2641},
|
|
{"cvmx_pcieep_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1031, 14, 2655},
|
|
{"cvmx_pcieep_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1032, 14, 2669},
|
|
{"cvmx_pcieep_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1033, 9, 2683},
|
|
{"cvmx_pcieep_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1034, 9, 2692},
|
|
{"cvmx_pcieep_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1035, 6, 2701},
|
|
{"cvmx_pcieep_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1036, 1, 2707},
|
|
{"cvmx_pcieep_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1037, 1, 2708},
|
|
{"cvmx_pcieep_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1038, 1, 2709},
|
|
{"cvmx_pcieep_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1039, 1, 2710},
|
|
{"cvmx_pcieep_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1040, 2, 2711},
|
|
{"cvmx_pcieep_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1041, 1, 2713},
|
|
{"cvmx_pcieep_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1042, 6, 2714},
|
|
{"cvmx_pcieep_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1043, 6, 2720},
|
|
{"cvmx_pcieep_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1044, 13, 2726},
|
|
{"cvmx_pcieep_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1045, 5, 2739},
|
|
{"cvmx_pcieep_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1046, 8, 2744},
|
|
{"cvmx_pcieep_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1047, 19, 2752},
|
|
{"cvmx_pcieep_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1048, 3, 2771},
|
|
{"cvmx_pcieep_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1049, 1, 2774},
|
|
{"cvmx_pcieep_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1050, 1, 2775},
|
|
{"cvmx_pcieep_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1051, 3, 2776},
|
|
{"cvmx_pcieep_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1052, 3, 2779},
|
|
{"cvmx_pcieep_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1053, 3, 2782},
|
|
{"cvmx_pcieep_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1054, 4, 2785},
|
|
{"cvmx_pcieep_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1055, 4, 2789},
|
|
{"cvmx_pcieep_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1056, 4, 2793},
|
|
{"cvmx_pcieep_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1057, 7, 2797},
|
|
{"cvmx_pcieep_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1058, 5, 2804},
|
|
{"cvmx_pcieep_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1059, 5, 2809},
|
|
{"cvmx_pcieep_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1060, 4, 2814},
|
|
{"cvmx_pcieep_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1061, 4, 2818},
|
|
{"cvmx_pcieep_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1062, 4, 2822},
|
|
{"cvmx_pcieep_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1063, 1, 2826},
|
|
{"cvmx_pcieep_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1064, 1, 2827},
|
|
{"cvmx_pcierc#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1065, 2, 2828},
|
|
{"cvmx_pcierc#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1067, 24, 2830},
|
|
{"cvmx_pcierc#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1069, 4, 2854},
|
|
{"cvmx_pcierc#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1071, 5, 2858},
|
|
{"cvmx_pcierc#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1073, 1, 2863},
|
|
{"cvmx_pcierc#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1075, 1, 2864},
|
|
{"cvmx_pcierc#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1077, 4, 2865},
|
|
{"cvmx_pcierc#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1079, 17, 2869},
|
|
{"cvmx_pcierc#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1081, 4, 2886},
|
|
{"cvmx_pcierc#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1083, 6, 2890},
|
|
{"cvmx_pcierc#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1085, 1, 2896},
|
|
{"cvmx_pcierc#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1087, 1, 2897},
|
|
{"cvmx_pcierc#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1089, 2, 2898},
|
|
{"cvmx_pcierc#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1091, 2, 2900},
|
|
{"cvmx_pcierc#_cfg014" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1093, 1, 2902},
|
|
{"cvmx_pcierc#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1095, 15, 2903},
|
|
{"cvmx_pcierc#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1097, 10, 2918},
|
|
{"cvmx_pcierc#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1099, 12, 2928},
|
|
{"cvmx_pcierc#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1101, 7, 2940},
|
|
{"cvmx_pcierc#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1103, 2, 2947},
|
|
{"cvmx_pcierc#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1105, 1, 2949},
|
|
{"cvmx_pcierc#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1107, 2, 2950},
|
|
{"cvmx_pcierc#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1109, 7, 2952},
|
|
{"cvmx_pcierc#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1111, 11, 2959},
|
|
{"cvmx_pcierc#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1113, 19, 2970},
|
|
{"cvmx_pcierc#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1115, 11, 2989},
|
|
{"cvmx_pcierc#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1117, 20, 3000},
|
|
{"cvmx_pcierc#_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1119, 12, 3020},
|
|
{"cvmx_pcierc#_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1121, 22, 3032},
|
|
{"cvmx_pcierc#_cfg035" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1123, 8, 3054},
|
|
{"cvmx_pcierc#_cfg036" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1125, 4, 3062},
|
|
{"cvmx_pcierc#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1127, 3, 3066},
|
|
{"cvmx_pcierc#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1129, 3, 3069},
|
|
{"cvmx_pcierc#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1131, 1, 3072},
|
|
{"cvmx_pcierc#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1133, 1, 3073},
|
|
{"cvmx_pcierc#_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1135, 1, 3074},
|
|
{"cvmx_pcierc#_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1137, 1, 3075},
|
|
{"cvmx_pcierc#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1139, 3, 3076},
|
|
{"cvmx_pcierc#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1141, 14, 3079},
|
|
{"cvmx_pcierc#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1143, 14, 3093},
|
|
{"cvmx_pcierc#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1145, 14, 3107},
|
|
{"cvmx_pcierc#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1147, 9, 3121},
|
|
{"cvmx_pcierc#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1149, 9, 3130},
|
|
{"cvmx_pcierc#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1151, 6, 3139},
|
|
{"cvmx_pcierc#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1153, 1, 3145},
|
|
{"cvmx_pcierc#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1155, 1, 3146},
|
|
{"cvmx_pcierc#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1157, 1, 3147},
|
|
{"cvmx_pcierc#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1159, 1, 3148},
|
|
{"cvmx_pcierc#_cfg075" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1161, 4, 3149},
|
|
{"cvmx_pcierc#_cfg076" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1163, 9, 3153},
|
|
{"cvmx_pcierc#_cfg077" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1165, 2, 3162},
|
|
{"cvmx_pcierc#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1167, 2, 3164},
|
|
{"cvmx_pcierc#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1169, 1, 3166},
|
|
{"cvmx_pcierc#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1171, 6, 3167},
|
|
{"cvmx_pcierc#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1173, 6, 3173},
|
|
{"cvmx_pcierc#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1175, 13, 3179},
|
|
{"cvmx_pcierc#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1177, 5, 3192},
|
|
{"cvmx_pcierc#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1179, 8, 3197},
|
|
{"cvmx_pcierc#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1181, 19, 3205},
|
|
{"cvmx_pcierc#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1183, 3, 3224},
|
|
{"cvmx_pcierc#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1185, 1, 3227},
|
|
{"cvmx_pcierc#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1187, 1, 3228},
|
|
{"cvmx_pcierc#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1189, 3, 3229},
|
|
{"cvmx_pcierc#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1191, 3, 3232},
|
|
{"cvmx_pcierc#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1193, 3, 3235},
|
|
{"cvmx_pcierc#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1195, 4, 3238},
|
|
{"cvmx_pcierc#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1197, 4, 3242},
|
|
{"cvmx_pcierc#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1199, 4, 3246},
|
|
{"cvmx_pcierc#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1201, 7, 3250},
|
|
{"cvmx_pcierc#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1203, 5, 3257},
|
|
{"cvmx_pcierc#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1205, 5, 3262},
|
|
{"cvmx_pcierc#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1207, 4, 3267},
|
|
{"cvmx_pcierc#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1209, 4, 3271},
|
|
{"cvmx_pcierc#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1211, 4, 3275},
|
|
{"cvmx_pcierc#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1213, 1, 3279},
|
|
{"cvmx_pcierc#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1215, 1, 3280},
|
|
{"cvmx_pcs#_an#_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1217, 9, 3281},
|
|
{"cvmx_pcs#_an#_ext_st_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1221, 6, 3290},
|
|
{"cvmx_pcs#_an#_lp_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1225, 9, 3296},
|
|
{"cvmx_pcs#_an#_results_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1229, 6, 3305},
|
|
{"cvmx_pcs#_int#_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1233, 13, 3311},
|
|
{"cvmx_pcs#_int#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1237, 13, 3324},
|
|
{"cvmx_pcs#_link#_timer_count_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1241, 2, 3337},
|
|
{"cvmx_pcs#_log_anl#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1245, 4, 3339},
|
|
{"cvmx_pcs#_misc#_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1249, 8, 3343},
|
|
{"cvmx_pcs#_mr#_control_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1253, 13, 3351},
|
|
{"cvmx_pcs#_mr#_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1257, 17, 3364},
|
|
{"cvmx_pcs#_rx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1261, 7, 3381},
|
|
{"cvmx_pcs#_rx#_sync_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1265, 3, 3388},
|
|
{"cvmx_pcs#_sgm#_an_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1269, 8, 3391},
|
|
{"cvmx_pcs#_sgm#_lp_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1273, 7, 3399},
|
|
{"cvmx_pcs#_tx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1277, 4, 3406},
|
|
{"cvmx_pcs#_tx_rx#_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1281, 5, 3410},
|
|
{"cvmx_pcsx#_10gbx_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1285, 8, 3415},
|
|
{"cvmx_pcsx#_bist_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1287, 2, 3423},
|
|
{"cvmx_pcsx#_bit_lock_status_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1289, 5, 3425},
|
|
{"cvmx_pcsx#_control1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1291, 10, 3430},
|
|
{"cvmx_pcsx#_control2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1293, 2, 3440},
|
|
{"cvmx_pcsx#_int_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1295, 7, 3442},
|
|
{"cvmx_pcsx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1297, 7, 3449},
|
|
{"cvmx_pcsx#_log_anl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1299, 6, 3456},
|
|
{"cvmx_pcsx#_misc_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1301, 5, 3462},
|
|
{"cvmx_pcsx#_rx_sync_states_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1303, 5, 3467},
|
|
{"cvmx_pcsx#_spd_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1305, 3, 3472},
|
|
{"cvmx_pcsx#_status1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1307, 6, 3475},
|
|
{"cvmx_pcsx#_status2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1309, 9, 3481},
|
|
{"cvmx_pcsx#_tx_rx_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1311, 3, 3490},
|
|
{"cvmx_pcsx#_tx_rx_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1313, 9, 3493},
|
|
{"cvmx_pesc#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1315, 13, 3502},
|
|
{"cvmx_pesc#_bist_status2" , CVMX_CSR_DB_TYPE_RSL, 64, 1317, 15, 3515},
|
|
{"cvmx_pesc#_cfg_rd" , CVMX_CSR_DB_TYPE_RSL, 64, 1319, 2, 3530},
|
|
{"cvmx_pesc#_cfg_wr" , CVMX_CSR_DB_TYPE_RSL, 64, 1321, 2, 3532},
|
|
{"cvmx_pesc#_cpl_lut_valid" , CVMX_CSR_DB_TYPE_RSL, 64, 1323, 2, 3534},
|
|
{"cvmx_pesc#_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1325, 16, 3536},
|
|
{"cvmx_pesc#_ctl_status2" , CVMX_CSR_DB_TYPE_RSL, 64, 1327, 2, 3552},
|
|
{"cvmx_pesc#_dbg_info" , CVMX_CSR_DB_TYPE_RSL, 64, 1329, 32, 3554},
|
|
{"cvmx_pesc#_dbg_info_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1331, 32, 3586},
|
|
{"cvmx_pesc#_diag_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1333, 5, 3618},
|
|
{"cvmx_pesc#_p2n_bar0_start" , CVMX_CSR_DB_TYPE_RSL, 64, 1335, 2, 3623},
|
|
{"cvmx_pesc#_p2n_bar1_start" , CVMX_CSR_DB_TYPE_RSL, 64, 1337, 2, 3625},
|
|
{"cvmx_pesc#_p2n_bar2_start" , CVMX_CSR_DB_TYPE_RSL, 64, 1339, 2, 3627},
|
|
{"cvmx_pesc#_p2p_bar#_end" , CVMX_CSR_DB_TYPE_RSL, 64, 1341, 2, 3629},
|
|
{"cvmx_pesc#_p2p_bar#_start" , CVMX_CSR_DB_TYPE_RSL, 64, 1349, 2, 3631},
|
|
{"cvmx_pesc#_tlp_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 1357, 8, 3633},
|
|
{"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1359, 2, 3641},
|
|
{"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 1360, 4, 3643},
|
|
{"cvmx_pip_dsa_src_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 1364, 16, 3647},
|
|
{"cvmx_pip_dsa_vid_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 1365, 16, 3663},
|
|
{"cvmx_pip_frm_len_chk#" , CVMX_CSR_DB_TYPE_RSL, 64, 1366, 3, 3679},
|
|
{"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1368, 8, 3682},
|
|
{"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1369, 22, 3690},
|
|
{"cvmx_pip_hg_pri_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 1370, 6, 3712},
|
|
{"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1371, 14, 3718},
|
|
{"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1372, 14, 3732},
|
|
{"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 1373, 2, 3746},
|
|
{"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1374, 28, 3748},
|
|
{"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 1382, 25, 3776},
|
|
{"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 1390, 2, 3801},
|
|
{"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 1454, 4, 3803},
|
|
{"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 1462, 9, 3807},
|
|
{"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 1470, 2, 3816},
|
|
{"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 1471, 2, 3818},
|
|
{"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1472, 2, 3820},
|
|
{"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1480, 2, 3822},
|
|
{"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1488, 2, 3824},
|
|
{"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1496, 2, 3826},
|
|
{"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1504, 2, 3828},
|
|
{"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1512, 2, 3830},
|
|
{"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1520, 2, 3832},
|
|
{"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1528, 2, 3834},
|
|
{"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1536, 2, 3836},
|
|
{"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1544, 2, 3838},
|
|
{"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1552, 2, 3840},
|
|
{"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 1553, 2, 3842},
|
|
{"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 1561, 2, 3844},
|
|
{"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 1569, 2, 3846},
|
|
{"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 1577, 2, 3848},
|
|
{"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1641, 2, 3850},
|
|
{"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 1642, 3, 3852},
|
|
{"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 1643, 3, 3855},
|
|
{"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 1644, 2, 3858},
|
|
{"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 1645, 2, 3860},
|
|
{"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1646, 4, 3862},
|
|
{"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 1647, 5, 3866},
|
|
{"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 1648, 4, 3871},
|
|
{"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 1649, 8, 3875},
|
|
{"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 1650, 4, 3883},
|
|
{"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 1651, 5, 3887},
|
|
{"cvmx_pko_mem_debug14" , CVMX_CSR_DB_TYPE_RSL, 64, 1652, 1, 3892},
|
|
{"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 1653, 5, 3893},
|
|
{"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 1654, 1, 3898},
|
|
{"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 1655, 13, 3899},
|
|
{"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 1656, 4, 3912},
|
|
{"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 1657, 13, 3916},
|
|
{"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 1658, 6, 3929},
|
|
{"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 1659, 9, 3935},
|
|
{"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 1660, 4, 3944},
|
|
{"cvmx_pko_mem_port_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 1661, 7, 3948},
|
|
{"cvmx_pko_mem_port_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 1662, 5, 3955},
|
|
{"cvmx_pko_mem_port_rate0" , CVMX_CSR_DB_TYPE_RSL, 64, 1663, 5, 3960},
|
|
{"cvmx_pko_mem_port_rate1" , CVMX_CSR_DB_TYPE_RSL, 64, 1664, 4, 3965},
|
|
{"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 1665, 9, 3969},
|
|
{"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 1666, 5, 3978},
|
|
{"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1667, 16, 3983},
|
|
{"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 1668, 4, 3999},
|
|
{"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1669, 1, 4003},
|
|
{"cvmx_pko_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 1670, 1, 4004},
|
|
{"cvmx_pko_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 1671, 1, 4005},
|
|
{"cvmx_pko_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 1672, 1, 4006},
|
|
{"cvmx_pko_reg_engine_inflight", CVMX_CSR_DB_TYPE_RSL, 64, 1673, 11, 4007},
|
|
{"cvmx_pko_reg_engine_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 1674, 2, 4018},
|
|
{"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 1675, 4, 4020},
|
|
{"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 1676, 5, 4024},
|
|
{"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 1677, 3, 4029},
|
|
{"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1678, 4, 4032},
|
|
{"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 1679, 2, 4036},
|
|
{"cvmx_pko_reg_queue_ptrs1" , CVMX_CSR_DB_TYPE_RSL, 64, 1680, 3, 4038},
|
|
{"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 1681, 3, 4041},
|
|
{"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 1682, 12, 4044},
|
|
{"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1683, 2, 4056},
|
|
{"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 1684, 13, 4058},
|
|
{"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 1685, 3, 4071},
|
|
{"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 1686, 2, 4074},
|
|
{"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1694, 2, 4076},
|
|
{"cvmx_pow_iq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 1695, 2, 4078},
|
|
{"cvmx_pow_iq_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 1696, 2, 4080},
|
|
{"cvmx_pow_iq_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 1697, 2, 4082},
|
|
{"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 1705, 2, 4084},
|
|
{"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 1706, 2, 4086},
|
|
{"cvmx_pow_pf_rst_msk" , CVMX_CSR_DB_TYPE_NCB, 64, 1707, 2, 4088},
|
|
{"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 1708, 10, 4090},
|
|
{"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 1712, 5, 4100},
|
|
{"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 1720, 10, 4105},
|
|
{"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1728, 2, 4115},
|
|
{"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1729, 2, 4117},
|
|
{"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 1730, 2, 4119},
|
|
{"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 1738, 3, 4121},
|
|
{"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 1739, 6, 4124},
|
|
{"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 1755, 5, 4130},
|
|
{"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 1756, 7, 4135},
|
|
{"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 1772, 2, 4142},
|
|
{"cvmx_rad_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1788, 1, 4144},
|
|
{"cvmx_rad_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 1789, 1, 4145},
|
|
{"cvmx_rad_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 1790, 1, 4146},
|
|
{"cvmx_rad_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1791, 5, 4147},
|
|
{"cvmx_rad_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 1792, 5, 4152},
|
|
{"cvmx_rad_reg_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1793, 4, 4157},
|
|
{"cvmx_rad_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1794, 10, 4161},
|
|
{"cvmx_rad_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 1795, 1, 4171},
|
|
{"cvmx_rad_reg_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 1796, 3, 4172},
|
|
{"cvmx_rad_reg_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 1797, 7, 4175},
|
|
{"cvmx_rad_reg_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 1798, 2, 4182},
|
|
{"cvmx_rad_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 1799, 1, 4184},
|
|
{"cvmx_rad_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 1800, 1, 4185},
|
|
{"cvmx_rad_reg_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 1801, 1, 4186},
|
|
{"cvmx_rad_reg_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 1802, 18, 4187},
|
|
{"cvmx_rad_reg_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 1803, 3, 4205},
|
|
{"cvmx_rad_reg_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 1804, 2, 4208},
|
|
{"cvmx_rad_reg_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 1805, 3, 4210},
|
|
{"cvmx_rad_reg_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 1806, 7, 4213},
|
|
{"cvmx_rad_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 1807, 2, 4220},
|
|
{"cvmx_rad_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1808, 2, 4222},
|
|
{"cvmx_rad_reg_polynomial" , CVMX_CSR_DB_TYPE_RSL, 64, 1809, 2, 4224},
|
|
{"cvmx_rad_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 1810, 3, 4226},
|
|
{"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1811, 3, 4229},
|
|
{"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1812, 7, 4232},
|
|
{"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 1813, 10, 4239},
|
|
{"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1815, 6, 4249},
|
|
{"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1817, 2, 4255},
|
|
{"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1819, 4, 4257},
|
|
{"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1821, 4, 4261},
|
|
{"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 1823, 6, 4265},
|
|
{"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 1824, 3, 4271},
|
|
{"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 1825, 5, 4274},
|
|
{"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 1826, 4, 4279},
|
|
{"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 1827, 6, 4283},
|
|
{"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 1828, 4, 4289},
|
|
{"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 1829, 2, 4293},
|
|
{"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 1830, 4, 4295},
|
|
{"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 1831, 2, 4299},
|
|
{"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 1832, 3, 4301},
|
|
{"cvmx_tra_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1833, 4, 4304},
|
|
{"cvmx_tra_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1834, 12, 4308},
|
|
{"cvmx_tra_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 1835, 3, 4320},
|
|
{"cvmx_tra_cycles_since1" , CVMX_CSR_DB_TYPE_RSL, 64, 1836, 5, 4323},
|
|
{"cvmx_tra_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1837, 2, 4328},
|
|
{"cvmx_tra_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 1838, 2, 4330},
|
|
{"cvmx_tra_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1839, 18, 4332},
|
|
{"cvmx_tra_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 1840, 12, 4350},
|
|
{"cvmx_tra_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 1841, 6, 4362},
|
|
{"cvmx_tra_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1842, 5, 4368},
|
|
{"cvmx_tra_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 1843, 1, 4373},
|
|
{"cvmx_tra_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1844, 2, 4374},
|
|
{"cvmx_tra_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 1845, 2, 4376},
|
|
{"cvmx_tra_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1846, 18, 4378},
|
|
{"cvmx_tra_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 1847, 12, 4396},
|
|
{"cvmx_tra_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 1848, 6, 4408},
|
|
{"cvmx_tra_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 1849, 2, 4414},
|
|
{"cvmx_tra_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 1850, 2, 4416},
|
|
{"cvmx_tra_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 1851, 18, 4418},
|
|
{"cvmx_tra_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 1852, 12, 4436},
|
|
{"cvmx_tra_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 1853, 6, 4448},
|
|
{"cvmx_usbc#_daint" , CVMX_CSR_DB_TYPE_NCB, 32, 1854, 2, 4454},
|
|
{"cvmx_usbc#_daintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1856, 2, 4456},
|
|
{"cvmx_usbc#_dcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1858, 8, 4458},
|
|
{"cvmx_usbc#_dctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1860, 11, 4466},
|
|
{"cvmx_usbc#_diepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 1862, 15, 4477},
|
|
{"cvmx_usbc#_diepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1872, 8, 4492},
|
|
{"cvmx_usbc#_diepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1882, 8, 4500},
|
|
{"cvmx_usbc#_dieptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1884, 4, 4508},
|
|
{"cvmx_usbc#_doepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 1894, 15, 4512},
|
|
{"cvmx_usbc#_doepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 1904, 6, 4527},
|
|
{"cvmx_usbc#_doepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1914, 6, 4533},
|
|
{"cvmx_usbc#_doeptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1916, 4, 4539},
|
|
{"cvmx_usbc#_dptxfsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 1926, 2, 4543},
|
|
{"cvmx_usbc#_dsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1934, 6, 4545},
|
|
{"cvmx_usbc#_dtknqr1" , CVMX_CSR_DB_TYPE_NCB, 32, 1936, 4, 4551},
|
|
{"cvmx_usbc#_dtknqr2" , CVMX_CSR_DB_TYPE_NCB, 32, 1938, 1, 4555},
|
|
{"cvmx_usbc#_dtknqr3" , CVMX_CSR_DB_TYPE_NCB, 32, 1940, 1, 4556},
|
|
{"cvmx_usbc#_dtknqr4" , CVMX_CSR_DB_TYPE_NCB, 32, 1942, 1, 4557},
|
|
{"cvmx_usbc#_gahbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1944, 7, 4558},
|
|
{"cvmx_usbc#_ghwcfg1" , CVMX_CSR_DB_TYPE_NCB, 32, 1946, 1, 4565},
|
|
{"cvmx_usbc#_ghwcfg2" , CVMX_CSR_DB_TYPE_NCB, 32, 1948, 14, 4566},
|
|
{"cvmx_usbc#_ghwcfg3" , CVMX_CSR_DB_TYPE_NCB, 32, 1950, 10, 4580},
|
|
{"cvmx_usbc#_ghwcfg4" , CVMX_CSR_DB_TYPE_NCB, 32, 1952, 14, 4590},
|
|
{"cvmx_usbc#_gintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1954, 32, 4604},
|
|
{"cvmx_usbc#_gintsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1956, 32, 4636},
|
|
{"cvmx_usbc#_gnptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1958, 2, 4668},
|
|
{"cvmx_usbc#_gnptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 1960, 4, 4670},
|
|
{"cvmx_usbc#_gotgctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1962, 13, 4674},
|
|
{"cvmx_usbc#_gotgint" , CVMX_CSR_DB_TYPE_NCB, 32, 1964, 10, 4687},
|
|
{"cvmx_usbc#_grstctl" , CVMX_CSR_DB_TYPE_NCB, 32, 1966, 10, 4697},
|
|
{"cvmx_usbc#_grxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 1968, 2, 4707},
|
|
{"cvmx_usbc#_grxstspd" , CVMX_CSR_DB_TYPE_NCB, 32, 1970, 6, 4709},
|
|
{"cvmx_usbc#_grxstsph" , CVMX_CSR_DB_TYPE_NCB, 32, 1972, 5, 4715},
|
|
{"cvmx_usbc#_grxstsrd" , CVMX_CSR_DB_TYPE_NCB, 32, 1974, 6, 4720},
|
|
{"cvmx_usbc#_grxstsrh" , CVMX_CSR_DB_TYPE_NCB, 32, 1976, 5, 4726},
|
|
{"cvmx_usbc#_gsnpsid" , CVMX_CSR_DB_TYPE_NCB, 32, 1978, 1, 4731},
|
|
{"cvmx_usbc#_gusbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 1980, 13, 4732},
|
|
{"cvmx_usbc#_haint" , CVMX_CSR_DB_TYPE_NCB, 32, 1982, 2, 4745},
|
|
{"cvmx_usbc#_haintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 1984, 2, 4747},
|
|
{"cvmx_usbc#_hcchar#" , CVMX_CSR_DB_TYPE_NCB, 32, 1986, 11, 4749},
|
|
{"cvmx_usbc#_hcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 2002, 3, 4760},
|
|
{"cvmx_usbc#_hcint#" , CVMX_CSR_DB_TYPE_NCB, 32, 2004, 12, 4763},
|
|
{"cvmx_usbc#_hcintmsk#" , CVMX_CSR_DB_TYPE_NCB, 32, 2020, 12, 4775},
|
|
{"cvmx_usbc#_hcsplt#" , CVMX_CSR_DB_TYPE_NCB, 32, 2036, 6, 4787},
|
|
{"cvmx_usbc#_hctsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 2052, 4, 4793},
|
|
{"cvmx_usbc#_hfir" , CVMX_CSR_DB_TYPE_NCB, 32, 2068, 2, 4797},
|
|
{"cvmx_usbc#_hfnum" , CVMX_CSR_DB_TYPE_NCB, 32, 2070, 2, 4799},
|
|
{"cvmx_usbc#_hprt" , CVMX_CSR_DB_TYPE_NCB, 32, 2072, 15, 4801},
|
|
{"cvmx_usbc#_hptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 2074, 2, 4816},
|
|
{"cvmx_usbc#_hptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 2076, 3, 4818},
|
|
{"cvmx_usbc#_nptxdfifo#" , CVMX_CSR_DB_TYPE_NCB, 32, 2078, 1, 4821},
|
|
{"cvmx_usbc#_pcgcctl" , CVMX_CSR_DB_TYPE_NCB, 32, 2094, 6, 4822},
|
|
{"cvmx_usbn#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2096, 8, 4828},
|
|
{"cvmx_usbn#_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2098, 15, 4836},
|
|
{"cvmx_usbn#_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 2100, 6, 4851},
|
|
{"cvmx_usbn#_dma0_inb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 2102, 2, 4857},
|
|
{"cvmx_usbn#_dma0_inb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 2104, 2, 4859},
|
|
{"cvmx_usbn#_dma0_inb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 2106, 2, 4861},
|
|
{"cvmx_usbn#_dma0_inb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 2108, 2, 4863},
|
|
{"cvmx_usbn#_dma0_inb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 2110, 2, 4865},
|
|
{"cvmx_usbn#_dma0_inb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 2112, 2, 4867},
|
|
{"cvmx_usbn#_dma0_inb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 2114, 2, 4869},
|
|
{"cvmx_usbn#_dma0_inb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 2116, 2, 4871},
|
|
{"cvmx_usbn#_dma0_outb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 2118, 2, 4873},
|
|
{"cvmx_usbn#_dma0_outb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 2120, 2, 4875},
|
|
{"cvmx_usbn#_dma0_outb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 2122, 2, 4877},
|
|
{"cvmx_usbn#_dma0_outb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 2124, 2, 4879},
|
|
{"cvmx_usbn#_dma0_outb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 2126, 2, 4881},
|
|
{"cvmx_usbn#_dma0_outb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 2128, 2, 4883},
|
|
{"cvmx_usbn#_dma0_outb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 2130, 2, 4885},
|
|
{"cvmx_usbn#_dma0_outb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 2132, 2, 4887},
|
|
{"cvmx_usbn#_dma_test" , CVMX_CSR_DB_TYPE_NCB, 64, 2134, 7, 4889},
|
|
{"cvmx_usbn#_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 2136, 34, 4896},
|
|
{"cvmx_usbn#_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 2138, 34, 4930},
|
|
{"cvmx_usbn#_usbp_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2140, 35, 4964},
|
|
{NULL,0,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
|
|
/* name , --------------address, ---------------type, bits, csr offset */
|
|
{"AGL_GMX_BAD_REG" , 0x11800E0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
|
|
{"AGL_GMX_BIST" , 0x11800E0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
|
|
{"AGL_GMX_DRV_CTL" , 0x11800E00007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
|
|
{"AGL_GMX_INF_MODE" , 0x11800E00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
|
|
{"AGL_GMX_PRT0_CFG" , 0x11800E0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
|
|
{"AGL_GMX_PRT1_CFG" , 0x11800E0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
|
|
{"AGL_GMX_RX0_ADR_CAM0" , 0x11800E0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
|
|
{"AGL_GMX_RX1_ADR_CAM0" , 0x11800E0000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
|
|
{"AGL_GMX_RX0_ADR_CAM1" , 0x11800E0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
|
|
{"AGL_GMX_RX1_ADR_CAM1" , 0x11800E0000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
|
|
{"AGL_GMX_RX0_ADR_CAM2" , 0x11800E0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
|
|
{"AGL_GMX_RX1_ADR_CAM2" , 0x11800E0000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
|
|
{"AGL_GMX_RX0_ADR_CAM3" , 0x11800E0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
|
|
{"AGL_GMX_RX1_ADR_CAM3" , 0x11800E0000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
|
|
{"AGL_GMX_RX0_ADR_CAM4" , 0x11800E00001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
|
|
{"AGL_GMX_RX1_ADR_CAM4" , 0x11800E00009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
|
|
{"AGL_GMX_RX0_ADR_CAM5" , 0x11800E00001A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
|
|
{"AGL_GMX_RX1_ADR_CAM5" , 0x11800E00009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
|
|
{"AGL_GMX_RX0_ADR_CAM_EN" , 0x11800E0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
|
|
{"AGL_GMX_RX1_ADR_CAM_EN" , 0x11800E0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
|
|
{"AGL_GMX_RX0_ADR_CTL" , 0x11800E0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"AGL_GMX_RX1_ADR_CTL" , 0x11800E0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"AGL_GMX_RX0_DECISION" , 0x11800E0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"AGL_GMX_RX1_DECISION" , 0x11800E0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"AGL_GMX_RX0_FRM_CHK" , 0x11800E0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"AGL_GMX_RX1_FRM_CHK" , 0x11800E0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"AGL_GMX_RX0_FRM_CTL" , 0x11800E0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
|
|
{"AGL_GMX_RX1_FRM_CTL" , 0x11800E0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
|
|
{"AGL_GMX_RX0_FRM_MAX" , 0x11800E0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"AGL_GMX_RX1_FRM_MAX" , 0x11800E0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"AGL_GMX_RX0_FRM_MIN" , 0x11800E0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
|
|
{"AGL_GMX_RX1_FRM_MIN" , 0x11800E0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
|
|
{"AGL_GMX_RX0_IFG" , 0x11800E0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
|
|
{"AGL_GMX_RX1_IFG" , 0x11800E0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
|
|
{"AGL_GMX_RX0_INT_EN" , 0x11800E0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
|
|
{"AGL_GMX_RX1_INT_EN" , 0x11800E0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
|
|
{"AGL_GMX_RX0_INT_REG" , 0x11800E0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
|
|
{"AGL_GMX_RX1_INT_REG" , 0x11800E0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
|
|
{"AGL_GMX_RX0_JABBER" , 0x11800E0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
|
|
{"AGL_GMX_RX1_JABBER" , 0x11800E0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
|
|
{"AGL_GMX_RX0_PAUSE_DROP_TIME" , 0x11800E0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
|
|
{"AGL_GMX_RX1_PAUSE_DROP_TIME" , 0x11800E0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
|
|
{"AGL_GMX_RX0_STATS_CTL" , 0x11800E0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
|
|
{"AGL_GMX_RX1_STATS_CTL" , 0x11800E0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
|
|
{"AGL_GMX_RX0_STATS_OCTS" , 0x11800E0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
|
|
{"AGL_GMX_RX1_STATS_OCTS" , 0x11800E0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
|
|
{"AGL_GMX_RX0_STATS_OCTS_CTL" , 0x11800E0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 25},
|
|
{"AGL_GMX_RX1_STATS_OCTS_CTL" , 0x11800E0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 25},
|
|
{"AGL_GMX_RX0_STATS_OCTS_DMAC" , 0x11800E00000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 26},
|
|
{"AGL_GMX_RX1_STATS_OCTS_DMAC" , 0x11800E00008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 26},
|
|
{"AGL_GMX_RX0_STATS_OCTS_DRP" , 0x11800E00000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 27},
|
|
{"AGL_GMX_RX1_STATS_OCTS_DRP" , 0x11800E00008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 27},
|
|
{"AGL_GMX_RX0_STATS_PKTS" , 0x11800E0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 28},
|
|
{"AGL_GMX_RX1_STATS_PKTS" , 0x11800E0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 28},
|
|
{"AGL_GMX_RX0_STATS_PKTS_BAD" , 0x11800E00000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 29},
|
|
{"AGL_GMX_RX1_STATS_PKTS_BAD" , 0x11800E00008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 29},
|
|
{"AGL_GMX_RX0_STATS_PKTS_CTL" , 0x11800E0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 30},
|
|
{"AGL_GMX_RX1_STATS_PKTS_CTL" , 0x11800E0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 30},
|
|
{"AGL_GMX_RX0_STATS_PKTS_DMAC" , 0x11800E00000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 31},
|
|
{"AGL_GMX_RX1_STATS_PKTS_DMAC" , 0x11800E00008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 31},
|
|
{"AGL_GMX_RX0_STATS_PKTS_DRP" , 0x11800E00000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
|
|
{"AGL_GMX_RX1_STATS_PKTS_DRP" , 0x11800E00008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
|
|
{"AGL_GMX_RX0_UDD_SKP" , 0x11800E0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
|
|
{"AGL_GMX_RX1_UDD_SKP" , 0x11800E0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
|
|
{"AGL_GMX_RX_BP_DROP0" , 0x11800E0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 34},
|
|
{"AGL_GMX_RX_BP_DROP1" , 0x11800E0000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 34},
|
|
{"AGL_GMX_RX_BP_OFF0" , 0x11800E0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
|
|
{"AGL_GMX_RX_BP_OFF1" , 0x11800E0000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
|
|
{"AGL_GMX_RX_BP_ON0" , 0x11800E0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
|
|
{"AGL_GMX_RX_BP_ON1" , 0x11800E0000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
|
|
{"AGL_GMX_RX_PRT_INFO" , 0x11800E00004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
|
|
{"AGL_GMX_RX_TX_STATUS" , 0x11800E00007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
|
|
{"AGL_GMX_SMAC0" , 0x11800E0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
|
|
{"AGL_GMX_SMAC1" , 0x11800E0000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
|
|
{"AGL_GMX_STAT_BP" , 0x11800E0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
|
|
{"AGL_GMX_TX0_APPEND" , 0x11800E0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
|
|
{"AGL_GMX_TX1_APPEND" , 0x11800E0000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
|
|
{"AGL_GMX_TX0_CTL" , 0x11800E0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
|
|
{"AGL_GMX_TX1_CTL" , 0x11800E0000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
|
|
{"AGL_GMX_TX0_MIN_PKT" , 0x11800E0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
|
|
{"AGL_GMX_TX1_MIN_PKT" , 0x11800E0000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
|
|
{"AGL_GMX_TX0_PAUSE_PKT_INTERVAL", 0x11800E0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
|
|
{"AGL_GMX_TX1_PAUSE_PKT_INTERVAL", 0x11800E0000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
|
|
{"AGL_GMX_TX0_PAUSE_PKT_TIME" , 0x11800E0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
|
|
{"AGL_GMX_TX1_PAUSE_PKT_TIME" , 0x11800E0000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
|
|
{"AGL_GMX_TX0_PAUSE_TOGO" , 0x11800E0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
|
|
{"AGL_GMX_TX1_PAUSE_TOGO" , 0x11800E0000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
|
|
{"AGL_GMX_TX0_PAUSE_ZERO" , 0x11800E0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
|
|
{"AGL_GMX_TX1_PAUSE_ZERO" , 0x11800E0000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
|
|
{"AGL_GMX_TX0_SOFT_PAUSE" , 0x11800E0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
|
|
{"AGL_GMX_TX1_SOFT_PAUSE" , 0x11800E0000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
|
|
{"AGL_GMX_TX0_STAT0" , 0x11800E0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
|
|
{"AGL_GMX_TX1_STAT0" , 0x11800E0000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
|
|
{"AGL_GMX_TX0_STAT1" , 0x11800E0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
|
|
{"AGL_GMX_TX1_STAT1" , 0x11800E0000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
|
|
{"AGL_GMX_TX0_STAT2" , 0x11800E0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
|
|
{"AGL_GMX_TX1_STAT2" , 0x11800E0000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
|
|
{"AGL_GMX_TX0_STAT3" , 0x11800E0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
|
|
{"AGL_GMX_TX1_STAT3" , 0x11800E0000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
|
|
{"AGL_GMX_TX0_STAT4" , 0x11800E00002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
|
|
{"AGL_GMX_TX1_STAT4" , 0x11800E0000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
|
|
{"AGL_GMX_TX0_STAT5" , 0x11800E00002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
|
|
{"AGL_GMX_TX1_STAT5" , 0x11800E0000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
|
|
{"AGL_GMX_TX0_STAT6" , 0x11800E00002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
|
|
{"AGL_GMX_TX1_STAT6" , 0x11800E0000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
|
|
{"AGL_GMX_TX0_STAT7" , 0x11800E00002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
|
|
{"AGL_GMX_TX1_STAT7" , 0x11800E0000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
|
|
{"AGL_GMX_TX0_STAT8" , 0x11800E00002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
|
|
{"AGL_GMX_TX1_STAT8" , 0x11800E0000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
|
|
{"AGL_GMX_TX0_STAT9" , 0x11800E00002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
|
|
{"AGL_GMX_TX1_STAT9" , 0x11800E0000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
|
|
{"AGL_GMX_TX0_STATS_CTL" , 0x11800E0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
|
|
{"AGL_GMX_TX1_STATS_CTL" , 0x11800E0000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
|
|
{"AGL_GMX_TX0_THRESH" , 0x11800E0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
|
|
{"AGL_GMX_TX1_THRESH" , 0x11800E0000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
|
|
{"AGL_GMX_TX_BP" , 0x11800E00004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
|
|
{"AGL_GMX_TX_COL_ATTEMPT" , 0x11800E0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
|
|
{"AGL_GMX_TX_IFG" , 0x11800E0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
|
|
{"AGL_GMX_TX_INT_EN" , 0x11800E0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
|
|
{"AGL_GMX_TX_INT_REG" , 0x11800E0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
|
|
{"AGL_GMX_TX_JAM" , 0x11800E0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"AGL_GMX_TX_LFSR" , 0x11800E00004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"AGL_GMX_TX_OVR_BP" , 0x11800E00004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
|
|
{"AGL_GMX_TX_PAUSE_PKT_DMAC" , 0x11800E00004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
|
|
{"AGL_GMX_TX_PAUSE_PKT_TYPE" , 0x11800E00004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
|
|
{"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 71},
|
|
{"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 72},
|
|
{"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
|
|
{"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
|
|
{"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT4_EN0" , 0x1070000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT5_EN0" , 0x1070000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT6_EN0" , 0x1070000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT7_EN0" , 0x1070000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT4_EN1" , 0x1070000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT5_EN1" , 0x1070000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT6_EN1" , 0x1070000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT7_EN1" , 0x1070000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT0_EN4_0" , 0x1070000000C80ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT1_EN4_0" , 0x1070000000C90ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT2_EN4_0" , 0x1070000000CA0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT3_EN4_0" , 0x1070000000CB0ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT0_EN4_1" , 0x1070000000C88ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT1_EN4_1" , 0x1070000000C98ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT2_EN4_1" , 0x1070000000CA8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT3_EN4_1" , 0x1070000000CB8ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT4_SUM0" , 0x1070000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT5_SUM0" , 0x1070000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT6_SUM0" , 0x1070000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT7_SUM0" , 0x1070000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT0_SUM4" , 0x1070000000C00ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT1_SUM4" , 0x1070000000C08ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT2_SUM4" , 0x1070000000C10ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT3_SUM4" , 0x1070000000C18ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
|
|
{"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_MBOX_CLR2" , 0x1070000000690ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_MBOX_CLR3" , 0x1070000000698ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_MBOX_SET2" , 0x1070000000610ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_MBOX_SET3" , 0x1070000000618ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
|
|
{"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
|
|
{"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
|
|
{"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_PP_POKE2" , 0x1070000000590ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_PP_POKE3" , 0x1070000000598ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
|
|
{"CIU_QLM_DCOK" , 0x1070000000760ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
|
|
{"CIU_QLM_JTGC" , 0x1070000000768ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
|
|
{"CIU_QLM_JTGD" , 0x1070000000770ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
|
|
{"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
|
|
{"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
|
|
{"CIU_SOFT_PRST1" , 0x1070000000758ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
|
|
{"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
|
|
{"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
|
|
{"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
|
|
{"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
|
|
{"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
|
|
{"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
|
|
{"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
|
|
{"CIU_WDOG2" , 0x1070000000510ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
|
|
{"CIU_WDOG3" , 0x1070000000518ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
|
|
{"FPA_BIST_STATUS" , 0x11800280000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 98},
|
|
{"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 99},
|
|
{"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 100},
|
|
{"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 101},
|
|
{"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"FPA_QUE1_AVAILABLE" , 0x11800280000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"FPA_QUE2_AVAILABLE" , 0x11800280000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"FPA_QUE3_AVAILABLE" , 0x11800280000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"FPA_QUE4_AVAILABLE" , 0x11800280000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"FPA_QUE5_AVAILABLE" , 0x11800280000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"FPA_QUE6_AVAILABLE" , 0x11800280000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"FPA_QUE7_AVAILABLE" , 0x11800280000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 102},
|
|
{"FPA_QUE0_PAGE_INDEX" , 0x11800280000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"FPA_QUE1_PAGE_INDEX" , 0x11800280000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 103},
|
|
{"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 104},
|
|
{"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 105},
|
|
{"FPA_WART_CTL" , 0x11800280000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"FPA_WART_STATUS" , 0x11800280000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"GMX0_CLK_EN" , 0x11800080007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"GMX0_HG2_CONTROL" , 0x1180008000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"GMX0_INF_MODE" , 0x11800080007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_PRT003_CFG" , 0x1180008001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX0_RX003_ADR_CAM0" , 0x1180008001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX003_ADR_CAM1" , 0x1180008001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX0_RX003_ADR_CAM2" , 0x1180008001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX0_RX003_ADR_CAM3" , 0x1180008001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX0_RX000_ADR_CAM4" , 0x11800080001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_RX001_ADR_CAM4" , 0x11800080009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_RX002_ADR_CAM4" , 0x11800080011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_RX003_ADR_CAM4" , 0x11800080019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_RX000_ADR_CAM5" , 0x11800080001A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX0_RX001_ADR_CAM5" , 0x11800080009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX0_RX002_ADR_CAM5" , 0x11800080011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX0_RX003_ADR_CAM5" , 0x11800080019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_RX003_ADR_CAM_EN" , 0x1180008001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_RX003_ADR_CTL" , 0x1180008001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_RX003_DECISION" , 0x1180008001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX003_FRM_CHK" , 0x1180008001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_RX003_FRM_CTL" , 0x1180008001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_RX003_IFG" , 0x1180008001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_RX003_INT_EN" , 0x1180008001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_RX003_INT_REG" , 0x1180008001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_RX003_JABBER" , 0x1180008001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_RX000_PAUSE_DROP_TIME" , 0x1180008000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_RX001_PAUSE_DROP_TIME" , 0x1180008000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_RX002_PAUSE_DROP_TIME" , 0x1180008001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_RX003_PAUSE_DROP_TIME" , 0x1180008001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_RX003_STATS_CTL" , 0x1180008001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_RX003_STATS_OCTS" , 0x1180008001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_RX003_STATS_OCTS_CTL" , 0x1180008001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_RX003_STATS_OCTS_DMAC" , 0x11800080018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_RX003_STATS_OCTS_DRP" , 0x11800080018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_RX003_STATS_PKTS" , 0x1180008001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_RX003_STATS_PKTS_BAD" , 0x11800080018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_RX003_STATS_PKTS_CTL" , 0x1180008001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_RX003_STATS_PKTS_DMAC" , 0x11800080018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_RX003_STATS_PKTS_DRP" , 0x11800080018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_RX003_UDD_SKP" , 0x1180008001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_RX_BP_DROP003" , 0x1180008000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_RX_BP_OFF003" , 0x1180008000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX0_RX_BP_ON003" , 0x1180008000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX0_RX_HG2_STATUS" , 0x1180008000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX0_RX_PRT_INFO" , 0x11800080004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX0_RX_XAUI_BAD_COL" , 0x1180008000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX0_RX_XAUI_CTL" , 0x1180008000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX0_SMAC001" , 0x1180008000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX0_SMAC003" , 0x1180008001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX0_TX001_APPEND" , 0x1180008000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX0_TX003_APPEND" , 0x1180008001A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX0_TX001_BURST" , 0x1180008000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX0_TX003_BURST" , 0x1180008001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX0_TX001_CTL" , 0x1180008000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX0_TX003_CTL" , 0x1180008001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX0_TX001_MIN_PKT" , 0x1180008000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX0_TX003_MIN_PKT" , 0x1180008001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX0_TX003_PAUSE_PKT_INTERVAL", 0x1180008001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX0_TX003_PAUSE_PKT_TIME" , 0x1180008001A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
|
|
{"GMX0_TX001_PAUSE_TOGO" , 0x1180008000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
|
|
{"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
|
|
{"GMX0_TX003_PAUSE_TOGO" , 0x1180008001A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
|
|
{"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX001_PAUSE_ZERO" , 0x1180008000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX003_PAUSE_ZERO" , 0x1180008001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_TX000_SGMII_CTL" , 0x1180008000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
|
|
{"GMX0_TX001_SGMII_CTL" , 0x1180008000B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
|
|
{"GMX0_TX002_SGMII_CTL" , 0x1180008001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
|
|
{"GMX0_TX003_SGMII_CTL" , 0x1180008001B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
|
|
{"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
|
|
{"GMX0_TX001_SLOT" , 0x1180008000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
|
|
{"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
|
|
{"GMX0_TX003_SLOT" , 0x1180008001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
|
|
{"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
|
|
{"GMX0_TX001_SOFT_PAUSE" , 0x1180008000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
|
|
{"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
|
|
{"GMX0_TX003_SOFT_PAUSE" , 0x1180008001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
|
|
{"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
|
|
{"GMX0_TX001_STAT0" , 0x1180008000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
|
|
{"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
|
|
{"GMX0_TX003_STAT0" , 0x1180008001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
|
|
{"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
|
|
{"GMX0_TX001_STAT1" , 0x1180008000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
|
|
{"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
|
|
{"GMX0_TX003_STAT1" , 0x1180008001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
|
|
{"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX0_TX001_STAT2" , 0x1180008000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX0_TX003_STAT2" , 0x1180008001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX0_TX001_STAT3" , 0x1180008000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX0_TX003_STAT3" , 0x1180008001A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX0_TX000_STAT4" , 0x11800080002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX001_STAT4" , 0x1180008000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX002_STAT4" , 0x11800080012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX003_STAT4" , 0x1180008001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX000_STAT5" , 0x11800080002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
|
|
{"GMX0_TX001_STAT5" , 0x1180008000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
|
|
{"GMX0_TX002_STAT5" , 0x11800080012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
|
|
{"GMX0_TX003_STAT5" , 0x1180008001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
|
|
{"GMX0_TX000_STAT6" , 0x11800080002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"GMX0_TX001_STAT6" , 0x1180008000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"GMX0_TX002_STAT6" , 0x11800080012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"GMX0_TX003_STAT6" , 0x1180008001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"GMX0_TX000_STAT7" , 0x11800080002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"GMX0_TX001_STAT7" , 0x1180008000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"GMX0_TX002_STAT7" , 0x11800080012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"GMX0_TX003_STAT7" , 0x1180008001AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"GMX0_TX000_STAT8" , 0x11800080002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"GMX0_TX001_STAT8" , 0x1180008000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"GMX0_TX002_STAT8" , 0x11800080012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"GMX0_TX003_STAT8" , 0x1180008001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"GMX0_TX000_STAT9" , 0x11800080002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"GMX0_TX001_STAT9" , 0x1180008000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"GMX0_TX002_STAT9" , 0x11800080012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"GMX0_TX003_STAT9" , 0x1180008001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"GMX0_TX001_STATS_CTL" , 0x1180008000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"GMX0_TX003_STATS_CTL" , 0x1180008001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"GMX0_TX001_THRESH" , 0x1180008000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"GMX0_TX003_THRESH" , 0x1180008001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"GMX0_TX_BP" , 0x11800080004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"GMX0_TX_CORRUPT" , 0x11800080004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
|
|
{"GMX0_TX_HG2_REG1" , 0x1180008000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
|
|
{"GMX0_TX_HG2_REG2" , 0x1180008000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
|
|
{"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
|
|
{"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
|
|
{"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
|
|
{"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
|
|
{"GMX0_TX_LFSR" , 0x11800080004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
|
|
{"GMX0_TX_OVR_BP" , 0x11800080004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
|
|
{"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
|
|
{"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
|
|
{"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
|
|
{"GMX0_TX_XAUI_CTL" , 0x1180008000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
|
|
{"GMX0_XAUI_EXT_LOOPBACK" , 0x1180008000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
|
|
{"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 191},
|
|
{"GPIO_CLK_GEN0" , 0x10700000008C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
|
|
{"GPIO_CLK_GEN1" , 0x10700000008C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
|
|
{"GPIO_CLK_GEN2" , 0x10700000008D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
|
|
{"GPIO_CLK_GEN3" , 0x10700000008D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 192},
|
|
{"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 193},
|
|
{"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 194},
|
|
{"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 195},
|
|
{"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 196},
|
|
{"IOB_BIST_STATUS" , 0x11800F00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
|
|
{"IOB_CTL_STATUS" , 0x11800F0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
|
|
{"IOB_DWB_PRI_CNT" , 0x11800F0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
|
|
{"IOB_FAU_TIMEOUT" , 0x11800F0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
|
|
{"IOB_I2C_PRI_CNT" , 0x11800F0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
|
|
{"IOB_INB_CONTROL_MATCH" , 0x11800F0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 202},
|
|
{"IOB_INB_CONTROL_MATCH_ENB" , 0x11800F0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 203},
|
|
{"IOB_INB_DATA_MATCH" , 0x11800F0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 204},
|
|
{"IOB_INB_DATA_MATCH_ENB" , 0x11800F0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 205},
|
|
{"IOB_INT_ENB" , 0x11800F0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 206},
|
|
{"IOB_INT_SUM" , 0x11800F0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 207},
|
|
{"IOB_N2C_L2C_PRI_CNT" , 0x11800F0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 208},
|
|
{"IOB_N2C_RSP_PRI_CNT" , 0x11800F0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 209},
|
|
{"IOB_OUTB_COM_PRI_CNT" , 0x11800F0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 210},
|
|
{"IOB_OUTB_CONTROL_MATCH" , 0x11800F0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
|
|
{"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800F00000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
|
|
{"IOB_OUTB_DATA_MATCH" , 0x11800F0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
|
|
{"IOB_OUTB_DATA_MATCH_ENB" , 0x11800F00000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
|
|
{"IOB_OUTB_FPA_PRI_CNT" , 0x11800F0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
|
|
{"IOB_OUTB_REQ_PRI_CNT" , 0x11800F0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
|
|
{"IOB_P2C_REQ_PRI_CNT" , 0x11800F0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
|
|
{"IOB_PKT_ERR" , 0x11800F0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
|
|
{"IPD_1ST_MBUFF_SKIP" , 0x14F0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 219},
|
|
{"IPD_1ST_NEXT_PTR_BACK" , 0x14F0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 220},
|
|
{"IPD_2ND_NEXT_PTR_BACK" , 0x14F0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 221},
|
|
{"IPD_BIST_STATUS" , 0x14F00000007F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 222},
|
|
{"IPD_BP_PRT_RED_END" , 0x14F0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 223},
|
|
{"IPD_CLK_COUNT" , 0x14F0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 224},
|
|
{"IPD_CTL_STATUS" , 0x14F0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 225},
|
|
{"IPD_INT_ENB" , 0x14F0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 226},
|
|
{"IPD_INT_SUM" , 0x14F0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 227},
|
|
{"IPD_NOT_1ST_MBUFF_SKIP" , 0x14F0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 228},
|
|
{"IPD_PACKET_MBUFF_SIZE" , 0x14F0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 229},
|
|
{"IPD_PKT_PTR_VALID" , 0x14F0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 230},
|
|
{"IPD_PORT0_BP_PAGE_CNT" , 0x14F0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
|
|
{"IPD_PORT1_BP_PAGE_CNT" , 0x14F0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
|
|
{"IPD_PORT2_BP_PAGE_CNT" , 0x14F0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
|
|
{"IPD_PORT3_BP_PAGE_CNT" , 0x14F0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
|
|
{"IPD_PORT36_BP_PAGE_CNT2" , 0x14F0000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 232},
|
|
{"IPD_PORT37_BP_PAGE_CNT2" , 0x14F0000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 232},
|
|
{"IPD_PORT38_BP_PAGE_CNT2" , 0x14F0000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 232},
|
|
{"IPD_PORT39_BP_PAGE_CNT2" , 0x14F0000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 232},
|
|
{"IPD_PORT_BP_COUNTERS2_PAIR36", 0x14F0000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 233},
|
|
{"IPD_PORT_BP_COUNTERS2_PAIR37", 0x14F0000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 233},
|
|
{"IPD_PORT_BP_COUNTERS2_PAIR38", 0x14F0000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 233},
|
|
{"IPD_PORT_BP_COUNTERS2_PAIR39", 0x14F00000003A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 233},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14F00000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14F00000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14F00000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR3" , 0x14F00000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
|
|
{"IPD_PORT_QOS_0_CNT" , 0x14F0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_1_CNT" , 0x14F0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_2_CNT" , 0x14F0000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_3_CNT" , 0x14F00000008A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_4_CNT" , 0x14F00000008A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_5_CNT" , 0x14F00000008B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_6_CNT" , 0x14F00000008B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_7_CNT" , 0x14F00000008C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_8_CNT" , 0x14F00000008C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_9_CNT" , 0x14F00000008D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_10_CNT" , 0x14F00000008D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_11_CNT" , 0x14F00000008E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_12_CNT" , 0x14F00000008E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_13_CNT" , 0x14F00000008F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_14_CNT" , 0x14F00000008F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_15_CNT" , 0x14F0000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_16_CNT" , 0x14F0000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_17_CNT" , 0x14F0000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_18_CNT" , 0x14F0000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_19_CNT" , 0x14F0000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_20_CNT" , 0x14F0000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_21_CNT" , 0x14F0000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_22_CNT" , 0x14F0000000938ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_23_CNT" , 0x14F0000000940ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_24_CNT" , 0x14F0000000948ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_25_CNT" , 0x14F0000000950ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_26_CNT" , 0x14F0000000958ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_27_CNT" , 0x14F0000000960ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_28_CNT" , 0x14F0000000968ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_29_CNT" , 0x14F0000000970ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_30_CNT" , 0x14F0000000978ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_31_CNT" , 0x14F0000000980ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_288_CNT" , 0x14F0000001188ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_289_CNT" , 0x14F0000001190ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_290_CNT" , 0x14F0000001198ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_291_CNT" , 0x14F00000011A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_292_CNT" , 0x14F00000011A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_293_CNT" , 0x14F00000011B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_294_CNT" , 0x14F00000011B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_295_CNT" , 0x14F00000011C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_296_CNT" , 0x14F00000011C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_297_CNT" , 0x14F00000011D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_298_CNT" , 0x14F00000011D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_299_CNT" , 0x14F00000011E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_300_CNT" , 0x14F00000011E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_301_CNT" , 0x14F00000011F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_302_CNT" , 0x14F00000011F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_303_CNT" , 0x14F0000001200ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_304_CNT" , 0x14F0000001208ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_305_CNT" , 0x14F0000001210ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_306_CNT" , 0x14F0000001218ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_307_CNT" , 0x14F0000001220ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_308_CNT" , 0x14F0000001228ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_309_CNT" , 0x14F0000001230ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_310_CNT" , 0x14F0000001238ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_311_CNT" , 0x14F0000001240ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_312_CNT" , 0x14F0000001248ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_313_CNT" , 0x14F0000001250ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_314_CNT" , 0x14F0000001258ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_315_CNT" , 0x14F0000001260ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_316_CNT" , 0x14F0000001268ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_317_CNT" , 0x14F0000001270ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_318_CNT" , 0x14F0000001278ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_319_CNT" , 0x14F0000001280ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_PORT_QOS_INT0" , 0x14F0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
|
|
{"IPD_PORT_QOS_INT4" , 0x14F0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
|
|
{"IPD_PORT_QOS_INT_ENB0" , 0x14F0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
|
|
{"IPD_PORT_QOS_INT_ENB4" , 0x14F0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
|
|
{"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14F0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
|
|
{"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14F0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
|
|
{"IPD_PTR_COUNT" , 0x14F0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
|
|
{"IPD_PWP_PTR_FIFO_CTL" , 0x14F0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
|
|
{"IPD_QOS0_RED_MARKS" , 0x14F0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
|
|
{"IPD_QOS1_RED_MARKS" , 0x14F0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
|
|
{"IPD_QOS2_RED_MARKS" , 0x14F0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
|
|
{"IPD_QOS3_RED_MARKS" , 0x14F0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
|
|
{"IPD_QOS4_RED_MARKS" , 0x14F0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
|
|
{"IPD_QOS5_RED_MARKS" , 0x14F00000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
|
|
{"IPD_QOS6_RED_MARKS" , 0x14F00000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
|
|
{"IPD_QOS7_RED_MARKS" , 0x14F00000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
|
|
{"IPD_QUE0_FREE_PAGE_CNT" , 0x14F0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
|
|
{"IPD_RED_PORT_ENABLE" , 0x14F00000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
|
|
{"IPD_RED_PORT_ENABLE2" , 0x14F00000003A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
|
|
{"IPD_RED_QUE0_PARAM" , 0x14F00000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_RED_QUE1_PARAM" , 0x14F00000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_RED_QUE2_PARAM" , 0x14F00000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_RED_QUE3_PARAM" , 0x14F00000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_RED_QUE4_PARAM" , 0x14F0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_RED_QUE5_PARAM" , 0x14F0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_RED_QUE6_PARAM" , 0x14F0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_RED_QUE7_PARAM" , 0x14F0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14F0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_SUB_PORT_FCS" , 0x14F0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
|
|
{"IPD_SUB_PORT_QOS_CNT" , 0x14F0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
|
|
{"IPD_WQE_FPA_QUEUE" , 0x14F0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_WQE_PTR_VALID" , 0x14F0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
|
|
{"L2C_BST0" , 0x11800800007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 252},
|
|
{"L2C_BST1" , 0x11800800007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 253},
|
|
{"L2C_BST2" , 0x11800800007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 254},
|
|
{"L2C_CFG" , 0x1180080000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 255},
|
|
{"L2C_DBG" , 0x1180080000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 256},
|
|
{"L2C_DUT" , 0x1180080000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 257},
|
|
{"L2C_GRPWRR0" , 0x11800800000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 258},
|
|
{"L2C_GRPWRR1" , 0x11800800000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 259},
|
|
{"L2C_INT_EN" , 0x1180080000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 260},
|
|
{"L2C_INT_STAT" , 0x11800800000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 261},
|
|
{"L2C_LCKBASE" , 0x1180080000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 262},
|
|
{"L2C_LCKOFF" , 0x1180080000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 263},
|
|
{"L2C_LFB0" , 0x1180080000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
|
|
{"L2C_LFB1" , 0x1180080000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
|
|
{"L2C_LFB2" , 0x1180080000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
|
|
{"L2C_LFB3" , 0x11800800000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
|
|
{"L2C_OOB" , 0x11800800000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
|
|
{"L2C_OOB1" , 0x11800800000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
|
|
{"L2C_OOB2" , 0x11800800000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
|
|
{"L2C_OOB3" , 0x11800800000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
|
|
{"L2C_PFC0" , 0x1180080000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
|
|
{"L2C_PFC1" , 0x11800800000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
|
|
{"L2C_PFC2" , 0x11800800000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
|
|
{"L2C_PFC3" , 0x11800800000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
|
|
{"L2C_PFCTL" , 0x1180080000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
|
|
{"L2C_PPGRP" , 0x11800800000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
|
|
{"L2C_SPAR0" , 0x1180080000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
|
|
{"L2C_SPAR4" , 0x1180080000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
|
|
{"L2D_BST0" , 0x1180080000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
|
|
{"L2D_BST1" , 0x1180080000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
|
|
{"L2D_BST2" , 0x1180080000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
|
|
{"L2D_BST3" , 0x1180080000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
|
|
{"L2D_ERR" , 0x1180080000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
|
|
{"L2D_FADR" , 0x1180080000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
|
|
{"L2D_FSYN0" , 0x1180080000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
|
|
{"L2D_FSYN1" , 0x1180080000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
|
|
{"L2D_FUS0" , 0x11800800007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
|
|
{"L2D_FUS1" , 0x11800800007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
|
|
{"L2D_FUS2" , 0x11800800007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
|
|
{"L2D_FUS3" , 0x11800800007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
|
|
{"L2T_ERR" , 0x1180080000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 289},
|
|
{"LMC0_BIST_CTL" , 0x11800880000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
|
|
{"LMC0_BIST_RESULT" , 0x11800880000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
|
|
{"LMC0_COMP_CTL" , 0x1180088000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
|
|
{"LMC0_CTL" , 0x1180088000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
|
|
{"LMC0_CTL1" , 0x1180088000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
|
|
{"LMC0_DCLK_CNT_HI" , 0x1180088000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
|
|
{"LMC0_DCLK_CNT_LO" , 0x1180088000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
|
|
{"LMC0_DDR2_CTL" , 0x1180088000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
|
|
{"LMC0_DELAY_CFG" , 0x1180088000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
|
|
{"LMC0_DLL_CTL" , 0x11800880000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
|
|
{"LMC0_DUAL_MEMCFG" , 0x1180088000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
|
|
{"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
|
|
{"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
|
|
{"LMC0_IFB_CNT_HI" , 0x1180088000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
|
|
{"LMC0_IFB_CNT_LO" , 0x1180088000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
|
|
{"LMC0_MEM_CFG0" , 0x1180088000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
|
|
{"LMC0_MEM_CFG1" , 0x1180088000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
|
|
{"LMC0_OPS_CNT_HI" , 0x1180088000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
|
|
{"LMC0_OPS_CNT_LO" , 0x1180088000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
|
|
{"LMC0_PLL_CTL" , 0x11800880000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
|
|
{"LMC0_PLL_STATUS" , 0x11800880000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
|
|
{"LMC0_READ_LEVEL_CTL" , 0x1180088000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
|
|
{"LMC0_READ_LEVEL_DBG" , 0x1180088000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
|
|
{"LMC0_READ_LEVEL_RANK000" , 0x1180088000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
|
|
{"LMC0_READ_LEVEL_RANK001" , 0x1180088000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
|
|
{"LMC0_READ_LEVEL_RANK002" , 0x1180088000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
|
|
{"LMC0_READ_LEVEL_RANK003" , 0x1180088000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
|
|
{"LMC0_RODT_COMP_CTL" , 0x11800880000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
|
|
{"LMC0_RODT_CTL" , 0x1180088000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
|
|
{"LMC0_WODT_CTL0" , 0x1180088000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
|
|
{"LMC0_WODT_CTL1" , 0x1180088000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
|
|
{"MIO_BOOT_BIST_STAT" , 0x11800000000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
|
|
{"MIO_BOOT_COMP" , 0x11800000000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
|
|
{"MIO_BOOT_DMA_CFG0" , 0x1180000000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
|
|
{"MIO_BOOT_DMA_CFG1" , 0x1180000000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
|
|
{"MIO_BOOT_DMA_INT0" , 0x1180000000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
|
|
{"MIO_BOOT_DMA_INT1" , 0x1180000000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
|
|
{"MIO_BOOT_DMA_INT_EN0" , 0x1180000000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
|
|
{"MIO_BOOT_DMA_INT_EN1" , 0x1180000000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
|
|
{"MIO_BOOT_DMA_TIM0" , 0x1180000000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
|
|
{"MIO_BOOT_DMA_TIM1" , 0x1180000000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
|
|
{"MIO_BOOT_ERR" , 0x11800000000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
|
|
{"MIO_BOOT_INT" , 0x11800000000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
|
|
{"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
|
|
{"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
|
|
{"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
|
|
{"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 328},
|
|
{"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
|
|
{"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
|
|
{"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
|
|
{"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
|
|
{"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
|
|
{"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
|
|
{"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
|
|
{"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
|
|
{"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
|
|
{"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
|
|
{"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
|
|
{"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
|
|
{"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
|
|
{"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
|
|
{"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
|
|
{"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
|
|
{"MIO_BOOT_THR" , 0x11800000000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 331},
|
|
{"MIO_FUS_BNK_DAT0" , 0x1180000001520ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
|
|
{"MIO_FUS_BNK_DAT1" , 0x1180000001528ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
|
|
{"MIO_FUS_BNK_DAT2" , 0x1180000001530ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
|
|
{"MIO_FUS_BNK_DAT3" , 0x1180000001538ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
|
|
{"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
|
|
{"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 334},
|
|
{"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 335},
|
|
{"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 336},
|
|
{"MIO_FUS_EMA" , 0x1180000001550ull, CVMX_CSR_DB_TYPE_RSL, 64, 337},
|
|
{"MIO_FUS_PDF" , 0x1180000001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 338},
|
|
{"MIO_FUS_PLL" , 0x1180000001580ull, CVMX_CSR_DB_TYPE_RSL, 64, 339},
|
|
{"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 340},
|
|
{"MIO_FUS_PROG_TIMES" , 0x1180000001518ull, CVMX_CSR_DB_TYPE_RSL, 64, 341},
|
|
{"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 342},
|
|
{"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
|
|
{"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
|
|
{"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 345},
|
|
{"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
|
|
{"MIO_TWS1_INT" , 0x1180000001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
|
|
{"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
|
|
{"MIO_TWS1_SW_TWSI" , 0x1180000001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
|
|
{"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 348},
|
|
{"MIO_TWS1_SW_TWSI_EXT" , 0x1180000001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 348},
|
|
{"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
|
|
{"MIO_TWS1_TWSI_SW" , 0x1180000001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
|
|
{"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
|
|
{"MIO_UART1_DLH" , 0x1180000000C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
|
|
{"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 351},
|
|
{"MIO_UART1_DLL" , 0x1180000000C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 351},
|
|
{"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 352},
|
|
{"MIO_UART1_FAR" , 0x1180000000D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 352},
|
|
{"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 353},
|
|
{"MIO_UART1_FCR" , 0x1180000000C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 353},
|
|
{"MIO_UART0_HTX" , 0x1180000000B08ull, CVMX_CSR_DB_TYPE_RSL, 64, 354},
|
|
{"MIO_UART1_HTX" , 0x1180000000F08ull, CVMX_CSR_DB_TYPE_RSL, 64, 354},
|
|
{"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 355},
|
|
{"MIO_UART1_IER" , 0x1180000000C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 355},
|
|
{"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
|
|
{"MIO_UART1_IIR" , 0x1180000000C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
|
|
{"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
|
|
{"MIO_UART1_LCR" , 0x1180000000C18ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
|
|
{"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
|
|
{"MIO_UART1_LSR" , 0x1180000000C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
|
|
{"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
|
|
{"MIO_UART1_MCR" , 0x1180000000C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
|
|
{"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 360},
|
|
{"MIO_UART1_MSR" , 0x1180000000C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 360},
|
|
{"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 361},
|
|
{"MIO_UART1_RBR" , 0x1180000000C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 361},
|
|
{"MIO_UART0_RFL" , 0x1180000000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 362},
|
|
{"MIO_UART1_RFL" , 0x1180000000E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 362},
|
|
{"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
|
|
{"MIO_UART1_RFW" , 0x1180000000D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
|
|
{"MIO_UART0_SBCR" , 0x1180000000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 364},
|
|
{"MIO_UART1_SBCR" , 0x1180000000E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 364},
|
|
{"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
|
|
{"MIO_UART1_SCR" , 0x1180000000C38ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
|
|
{"MIO_UART0_SFE" , 0x1180000000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
|
|
{"MIO_UART1_SFE" , 0x1180000000E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
|
|
{"MIO_UART0_SRR" , 0x1180000000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
|
|
{"MIO_UART1_SRR" , 0x1180000000E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
|
|
{"MIO_UART0_SRT" , 0x1180000000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
|
|
{"MIO_UART1_SRT" , 0x1180000000E38ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
|
|
{"MIO_UART0_SRTS" , 0x1180000000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
|
|
{"MIO_UART1_SRTS" , 0x1180000000E18ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
|
|
{"MIO_UART0_STT" , 0x1180000000B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
|
|
{"MIO_UART1_STT" , 0x1180000000F00ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
|
|
{"MIO_UART0_TFL" , 0x1180000000A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
|
|
{"MIO_UART1_TFL" , 0x1180000000E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
|
|
{"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
|
|
{"MIO_UART1_TFR" , 0x1180000000D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
|
|
{"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
|
|
{"MIO_UART1_THR" , 0x1180000000C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
|
|
{"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
|
|
{"MIO_UART1_USR" , 0x1180000000D38ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
|
|
{"MIO_UART2_DLH" , 0x1180000000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
|
|
{"MIO_UART2_DLL" , 0x1180000000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
|
|
{"MIO_UART2_FAR" , 0x1180000000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
|
|
{"MIO_UART2_FCR" , 0x1180000000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
|
|
{"MIO_UART2_HTX" , 0x1180000000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
|
|
{"MIO_UART2_IER" , 0x1180000000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
|
|
{"MIO_UART2_IIR" , 0x1180000000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
|
|
{"MIO_UART2_LCR" , 0x1180000000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
|
|
{"MIO_UART2_LSR" , 0x1180000000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
|
|
{"MIO_UART2_MCR" , 0x1180000000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
|
|
{"MIO_UART2_MSR" , 0x1180000000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
|
|
{"MIO_UART2_RBR" , 0x1180000000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
|
|
{"MIO_UART2_RFL" , 0x1180000000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
|
|
{"MIO_UART2_RFW" , 0x1180000000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
|
|
{"MIO_UART2_SBCR" , 0x1180000000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
|
|
{"MIO_UART2_SCR" , 0x1180000000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
|
|
{"MIO_UART2_SFE" , 0x1180000000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
|
|
{"MIO_UART2_SRR" , 0x1180000000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
|
|
{"MIO_UART2_SRT" , 0x1180000000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
|
|
{"MIO_UART2_SRTS" , 0x1180000000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
|
|
{"MIO_UART2_STT" , 0x1180000000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
|
|
{"MIO_UART2_TFL" , 0x1180000000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
|
|
{"MIO_UART2_TFR" , 0x1180000000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
|
|
{"MIO_UART2_THR" , 0x1180000000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
|
|
{"MIO_UART2_USR" , 0x1180000000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
|
|
{"MIX0_BIST" , 0x1070000100078ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
|
|
{"MIX1_BIST" , 0x1070000100878ull, CVMX_CSR_DB_TYPE_NCB, 64, 400},
|
|
{"MIX0_CTL" , 0x1070000100020ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
|
|
{"MIX1_CTL" , 0x1070000100820ull, CVMX_CSR_DB_TYPE_NCB, 64, 401},
|
|
{"MIX0_INTENA" , 0x1070000100050ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
|
|
{"MIX1_INTENA" , 0x1070000100850ull, CVMX_CSR_DB_TYPE_NCB, 64, 402},
|
|
{"MIX0_IRCNT" , 0x1070000100030ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
|
|
{"MIX1_IRCNT" , 0x1070000100830ull, CVMX_CSR_DB_TYPE_NCB, 64, 403},
|
|
{"MIX0_IRHWM" , 0x1070000100028ull, CVMX_CSR_DB_TYPE_NCB, 64, 404},
|
|
{"MIX1_IRHWM" , 0x1070000100828ull, CVMX_CSR_DB_TYPE_NCB, 64, 404},
|
|
{"MIX0_IRING1" , 0x1070000100010ull, CVMX_CSR_DB_TYPE_NCB, 64, 405},
|
|
{"MIX1_IRING1" , 0x1070000100810ull, CVMX_CSR_DB_TYPE_NCB, 64, 405},
|
|
{"MIX0_IRING2" , 0x1070000100018ull, CVMX_CSR_DB_TYPE_NCB, 64, 406},
|
|
{"MIX1_IRING2" , 0x1070000100818ull, CVMX_CSR_DB_TYPE_NCB, 64, 406},
|
|
{"MIX0_ISR" , 0x1070000100048ull, CVMX_CSR_DB_TYPE_NCB, 64, 407},
|
|
{"MIX1_ISR" , 0x1070000100848ull, CVMX_CSR_DB_TYPE_NCB, 64, 407},
|
|
{"MIX0_ORCNT" , 0x1070000100040ull, CVMX_CSR_DB_TYPE_NCB, 64, 408},
|
|
{"MIX1_ORCNT" , 0x1070000100840ull, CVMX_CSR_DB_TYPE_NCB, 64, 408},
|
|
{"MIX0_ORHWM" , 0x1070000100038ull, CVMX_CSR_DB_TYPE_NCB, 64, 409},
|
|
{"MIX1_ORHWM" , 0x1070000100838ull, CVMX_CSR_DB_TYPE_NCB, 64, 409},
|
|
{"MIX0_ORING1" , 0x1070000100000ull, CVMX_CSR_DB_TYPE_NCB, 64, 410},
|
|
{"MIX1_ORING1" , 0x1070000100800ull, CVMX_CSR_DB_TYPE_NCB, 64, 410},
|
|
{"MIX0_ORING2" , 0x1070000100008ull, CVMX_CSR_DB_TYPE_NCB, 64, 411},
|
|
{"MIX1_ORING2" , 0x1070000100808ull, CVMX_CSR_DB_TYPE_NCB, 64, 411},
|
|
{"MIX0_REMCNT" , 0x1070000100058ull, CVMX_CSR_DB_TYPE_NCB, 64, 412},
|
|
{"MIX1_REMCNT" , 0x1070000100858ull, CVMX_CSR_DB_TYPE_NCB, 64, 412},
|
|
{"NPEI_BAR1_INDEX0" , 0x11F0000008000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX1" , 0x11F0000008010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX2" , 0x11F0000008020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX3" , 0x11F0000008030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX4" , 0x11F0000008040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX5" , 0x11F0000008050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX6" , 0x11F0000008060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX7" , 0x11F0000008070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX8" , 0x11F0000008080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX9" , 0x11F0000008090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX10" , 0x11F00000080A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX11" , 0x11F00000080B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX12" , 0x11F00000080C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX13" , 0x11F00000080D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX14" , 0x11F00000080E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX15" , 0x11F00000080F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX16" , 0x11F0000008100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX17" , 0x11F0000008110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX18" , 0x11F0000008120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX19" , 0x11F0000008130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX20" , 0x11F0000008140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX21" , 0x11F0000008150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX22" , 0x11F0000008160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX23" , 0x11F0000008170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX24" , 0x11F0000008180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX25" , 0x11F0000008190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX26" , 0x11F00000081A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX27" , 0x11F00000081B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX28" , 0x11F00000081C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX29" , 0x11F00000081D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX30" , 0x11F00000081E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BAR1_INDEX31" , 0x11F00000081F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 413},
|
|
{"NPEI_BIST_STATUS" , 0x11F0000008580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 414},
|
|
{"NPEI_CTL_PORT0" , 0x11F0000008250ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 415},
|
|
{"NPEI_CTL_PORT1" , 0x11F0000008260ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 416},
|
|
{"NPEI_CTL_STATUS" , 0x11F0000008570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 417},
|
|
{"NPEI_CTL_STATUS2" , 0x11F000000BC00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 418},
|
|
{"NPEI_DATA_OUT_CNT" , 0x11F00000085F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 419},
|
|
{"NPEI_DBG_DATA" , 0x11F0000008510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 420},
|
|
{"NPEI_DBG_SELECT" , 0x11F0000008500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 421},
|
|
{"NPEI_DMA0_COUNTS" , 0x11F0000008450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 422},
|
|
{"NPEI_DMA1_COUNTS" , 0x11F0000008460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 422},
|
|
{"NPEI_DMA2_COUNTS" , 0x11F0000008470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 422},
|
|
{"NPEI_DMA3_COUNTS" , 0x11F0000008480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 422},
|
|
{"NPEI_DMA0_DBELL" , 0x11F00000083B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 423},
|
|
{"NPEI_DMA1_DBELL" , 0x11F00000083C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 423},
|
|
{"NPEI_DMA2_DBELL" , 0x11F00000083D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 423},
|
|
{"NPEI_DMA3_DBELL" , 0x11F00000083E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 423},
|
|
{"NPEI_DMA0_IBUFF_SADDR" , 0x11F0000008400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 424},
|
|
{"NPEI_DMA1_IBUFF_SADDR" , 0x11F0000008410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 424},
|
|
{"NPEI_DMA2_IBUFF_SADDR" , 0x11F0000008420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 424},
|
|
{"NPEI_DMA3_IBUFF_SADDR" , 0x11F0000008430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 424},
|
|
{"NPEI_DMA0_NADDR" , 0x11F00000084A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 425},
|
|
{"NPEI_DMA1_NADDR" , 0x11F00000084B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 425},
|
|
{"NPEI_DMA2_NADDR" , 0x11F00000084C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 425},
|
|
{"NPEI_DMA3_NADDR" , 0x11F00000084D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 425},
|
|
{"NPEI_DMA0_INT_LEVEL" , 0x11F00000085C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 426},
|
|
{"NPEI_DMA1_INT_LEVEL" , 0x11F00000085D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 427},
|
|
{"NPEI_DMA_CNTS" , 0x11F00000085E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 428},
|
|
{"NPEI_DMA_CONTROL" , 0x11F00000083A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 429},
|
|
{"NPEI_DMA_STATE1_P1" , 0x11F0000008680ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 430},
|
|
{"NPEI_DMA_STATE2_P1" , 0x11F0000008690ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 431},
|
|
{"NPEI_DMA_STATE3_P1" , 0x11F00000086A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 432},
|
|
{"NPEI_DMA_STATE4_P1" , 0x11F00000086B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 433},
|
|
{"NPEI_INT_A_ENB" , 0x11F0000008560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 434},
|
|
{"NPEI_INT_A_ENB2" , 0x11F000000BCE0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 435},
|
|
{"NPEI_INT_A_SUM" , 0x11F0000008550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 436},
|
|
{"NPEI_INT_ENB" , 0x11F0000008540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 437},
|
|
{"NPEI_INT_ENB2" , 0x11F000000BCD0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 438},
|
|
{"NPEI_INT_SUM" , 0x11F0000008530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 439},
|
|
{"NPEI_INT_SUM2" , 0x11F000000BCC0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 440},
|
|
{"NPEI_LAST_WIN_RDATA0" , 0x11F0000008600ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 441},
|
|
{"NPEI_LAST_WIN_RDATA1" , 0x11F0000008610ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 442},
|
|
{"NPEI_MEM_ACCESS_CTL" , 0x11F00000084F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 443},
|
|
{"NPEI_MEM_ACCESS_SUBID12" , 0x11F0000008280ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
|
|
{"NPEI_MEM_ACCESS_SUBID13" , 0x11F0000008290ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
|
|
{"NPEI_MEM_ACCESS_SUBID14" , 0x11F00000082A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
|
|
{"NPEI_MEM_ACCESS_SUBID15" , 0x11F00000082B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
|
|
{"NPEI_MEM_ACCESS_SUBID16" , 0x11F00000082C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
|
|
{"NPEI_MEM_ACCESS_SUBID17" , 0x11F00000082D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
|
|
{"NPEI_MEM_ACCESS_SUBID18" , 0x11F00000082E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
|
|
{"NPEI_MEM_ACCESS_SUBID19" , 0x11F00000082F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
|
|
{"NPEI_MEM_ACCESS_SUBID20" , 0x11F0000008300ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
|
|
{"NPEI_MEM_ACCESS_SUBID21" , 0x11F0000008310ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
|
|
{"NPEI_MEM_ACCESS_SUBID22" , 0x11F0000008320ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
|
|
{"NPEI_MEM_ACCESS_SUBID23" , 0x11F0000008330ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
|
|
{"NPEI_MEM_ACCESS_SUBID24" , 0x11F0000008340ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
|
|
{"NPEI_MEM_ACCESS_SUBID25" , 0x11F0000008350ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
|
|
{"NPEI_MEM_ACCESS_SUBID26" , 0x11F0000008360ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
|
|
{"NPEI_MEM_ACCESS_SUBID27" , 0x11F0000008370ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
|
|
{"NPEI_MSI_ENB0" , 0x11F000000BC50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 445},
|
|
{"NPEI_MSI_ENB1" , 0x11F000000BC60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 446},
|
|
{"NPEI_MSI_ENB2" , 0x11F000000BC70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 447},
|
|
{"NPEI_MSI_ENB3" , 0x11F000000BC80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 448},
|
|
{"NPEI_MSI_RCV0" , 0x11F000000BC10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 449},
|
|
{"NPEI_MSI_RCV1" , 0x11F000000BC20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 450},
|
|
{"NPEI_MSI_RCV2" , 0x11F000000BC30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 451},
|
|
{"NPEI_MSI_RCV3" , 0x11F000000BC40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 452},
|
|
{"NPEI_MSI_RD_MAP" , 0x11F000000BCA0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 453},
|
|
{"NPEI_MSI_WR_MAP" , 0x11F000000BC90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 454},
|
|
{"NPEI_PCIE_MSI_RCV" , 0x11F000000BCB0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
|
|
{"NPEI_PCIE_MSI_RCV_B1" , 0x11F0000008650ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 456},
|
|
{"NPEI_PCIE_MSI_RCV_B2" , 0x11F0000008660ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 457},
|
|
{"NPEI_PCIE_MSI_RCV_B3" , 0x11F0000008670ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 458},
|
|
{"NPEI_RSL_INT_BLOCKS" , 0x11F0000008520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 459},
|
|
{"NPEI_SCRATCH_1" , 0x11F0000008270ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 460},
|
|
{"NPEI_STATE1" , 0x11F0000008620ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 461},
|
|
{"NPEI_STATE2" , 0x11F0000008630ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 462},
|
|
{"NPEI_STATE3" , 0x11F0000008640ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 463},
|
|
{"NPEI_WIN_RD_ADDR" , 0x210ull, CVMX_CSR_DB_TYPE_PEXP, 64, 464},
|
|
{"NPEI_WIN_RD_DATA" , 0x240ull, CVMX_CSR_DB_TYPE_PEXP, 64, 465},
|
|
{"NPEI_WIN_WR_ADDR" , 0x200ull, CVMX_CSR_DB_TYPE_PEXP, 64, 466},
|
|
{"NPEI_WIN_WR_DATA" , 0x220ull, CVMX_CSR_DB_TYPE_PEXP, 64, 467},
|
|
{"NPEI_WIN_WR_MASK" , 0x230ull, CVMX_CSR_DB_TYPE_PEXP, 64, 468},
|
|
{"NPEI_WINDOW_CTL" , 0x11F0000008380ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 469},
|
|
{"PCIEEP_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 470},
|
|
{"PCIEEP_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 471},
|
|
{"PCIEEP_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 472},
|
|
{"PCIEEP_CFG003" , 0xCull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 473},
|
|
{"PCIEEP_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 474},
|
|
{"PCIEEP_CFG004_MASK" , 0x80000010ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 475},
|
|
{"PCIEEP_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 476},
|
|
{"PCIEEP_CFG005_MASK" , 0x80000014ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 477},
|
|
{"PCIEEP_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 478},
|
|
{"PCIEEP_CFG006_MASK" , 0x80000018ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 479},
|
|
{"PCIEEP_CFG007" , 0x1Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 480},
|
|
{"PCIEEP_CFG007_MASK" , 0x8000001Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 481},
|
|
{"PCIEEP_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 482},
|
|
{"PCIEEP_CFG008_MASK" , 0x80000020ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 483},
|
|
{"PCIEEP_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 484},
|
|
{"PCIEEP_CFG009_MASK" , 0x80000024ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 485},
|
|
{"PCIEEP_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 486},
|
|
{"PCIEEP_CFG011" , 0x2Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 487},
|
|
{"PCIEEP_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 488},
|
|
{"PCIEEP_CFG012_MASK" , 0x80000030ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 489},
|
|
{"PCIEEP_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 490},
|
|
{"PCIEEP_CFG015" , 0x3Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 491},
|
|
{"PCIEEP_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 492},
|
|
{"PCIEEP_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 493},
|
|
{"PCIEEP_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 494},
|
|
{"PCIEEP_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 495},
|
|
{"PCIEEP_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 496},
|
|
{"PCIEEP_CFG023" , 0x5Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 497},
|
|
{"PCIEEP_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 498},
|
|
{"PCIEEP_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 499},
|
|
{"PCIEEP_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 500},
|
|
{"PCIEEP_CFG031" , 0x7Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 501},
|
|
{"PCIEEP_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 502},
|
|
{"PCIEEP_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 503},
|
|
{"PCIEEP_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 504},
|
|
{"PCIEEP_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 505},
|
|
{"PCIEEP_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 506},
|
|
{"PCIEEP_CFG039" , 0x9Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 507},
|
|
{"PCIEEP_CFG040" , 0xA0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 508},
|
|
{"PCIEEP_CFG041" , 0xA4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 509},
|
|
{"PCIEEP_CFG042" , 0xA8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 510},
|
|
{"PCIEEP_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 511},
|
|
{"PCIEEP_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 512},
|
|
{"PCIEEP_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 513},
|
|
{"PCIEEP_CFG067" , 0x10Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 514},
|
|
{"PCIEEP_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 515},
|
|
{"PCIEEP_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 516},
|
|
{"PCIEEP_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 517},
|
|
{"PCIEEP_CFG071" , 0x11Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 518},
|
|
{"PCIEEP_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 519},
|
|
{"PCIEEP_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 520},
|
|
{"PCIEEP_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 521},
|
|
{"PCIEEP_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 522},
|
|
{"PCIEEP_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 523},
|
|
{"PCIEEP_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 524},
|
|
{"PCIEEP_CFG451" , 0x70Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 525},
|
|
{"PCIEEP_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 526},
|
|
{"PCIEEP_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 527},
|
|
{"PCIEEP_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 528},
|
|
{"PCIEEP_CFG455" , 0x71Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 529},
|
|
{"PCIEEP_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 530},
|
|
{"PCIEEP_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 531},
|
|
{"PCIEEP_CFG459" , 0x72Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 532},
|
|
{"PCIEEP_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 533},
|
|
{"PCIEEP_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 534},
|
|
{"PCIEEP_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 535},
|
|
{"PCIEEP_CFG463" , 0x73Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 536},
|
|
{"PCIEEP_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 537},
|
|
{"PCIEEP_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 538},
|
|
{"PCIEEP_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 539},
|
|
{"PCIEEP_CFG467" , 0x74Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 540},
|
|
{"PCIEEP_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 541},
|
|
{"PCIEEP_CFG490" , 0x7A8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 542},
|
|
{"PCIEEP_CFG491" , 0x7ACull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 543},
|
|
{"PCIEEP_CFG492" , 0x7B0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 544},
|
|
{"PCIEEP_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 545},
|
|
{"PCIEEP_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 546},
|
|
{"PCIERC0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 547},
|
|
{"PCIERC1_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 547},
|
|
{"PCIERC0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 548},
|
|
{"PCIERC1_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 548},
|
|
{"PCIERC0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 549},
|
|
{"PCIERC1_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 549},
|
|
{"PCIERC0_CFG003" , 0xCull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 550},
|
|
{"PCIERC1_CFG003" , 0xCull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 550},
|
|
{"PCIERC0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 551},
|
|
{"PCIERC1_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 551},
|
|
{"PCIERC0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 552},
|
|
{"PCIERC1_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 552},
|
|
{"PCIERC0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 553},
|
|
{"PCIERC1_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 553},
|
|
{"PCIERC0_CFG007" , 0x1Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 554},
|
|
{"PCIERC1_CFG007" , 0x1Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 554},
|
|
{"PCIERC0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 555},
|
|
{"PCIERC1_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 555},
|
|
{"PCIERC0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 556},
|
|
{"PCIERC1_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 556},
|
|
{"PCIERC0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 557},
|
|
{"PCIERC1_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 557},
|
|
{"PCIERC0_CFG011" , 0x2Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 558},
|
|
{"PCIERC1_CFG011" , 0x2Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 558},
|
|
{"PCIERC0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 559},
|
|
{"PCIERC1_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 559},
|
|
{"PCIERC0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 560},
|
|
{"PCIERC1_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 560},
|
|
{"PCIERC0_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 561},
|
|
{"PCIERC1_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 561},
|
|
{"PCIERC0_CFG015" , 0x3Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 562},
|
|
{"PCIERC1_CFG015" , 0x3Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 562},
|
|
{"PCIERC0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 563},
|
|
{"PCIERC1_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 563},
|
|
{"PCIERC0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 564},
|
|
{"PCIERC1_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 564},
|
|
{"PCIERC0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 565},
|
|
{"PCIERC1_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 565},
|
|
{"PCIERC0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 566},
|
|
{"PCIERC1_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 566},
|
|
{"PCIERC0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 567},
|
|
{"PCIERC1_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 567},
|
|
{"PCIERC0_CFG023" , 0x5Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 568},
|
|
{"PCIERC1_CFG023" , 0x5Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 568},
|
|
{"PCIERC0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 569},
|
|
{"PCIERC1_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 569},
|
|
{"PCIERC0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 570},
|
|
{"PCIERC1_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 570},
|
|
{"PCIERC0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 571},
|
|
{"PCIERC1_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 571},
|
|
{"PCIERC0_CFG031" , 0x7Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 572},
|
|
{"PCIERC1_CFG031" , 0x7Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 572},
|
|
{"PCIERC0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 573},
|
|
{"PCIERC1_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 573},
|
|
{"PCIERC0_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 574},
|
|
{"PCIERC1_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 574},
|
|
{"PCIERC0_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 575},
|
|
{"PCIERC1_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 575},
|
|
{"PCIERC0_CFG035" , 0x8Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 576},
|
|
{"PCIERC1_CFG035" , 0x8Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 576},
|
|
{"PCIERC0_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 577},
|
|
{"PCIERC1_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 577},
|
|
{"PCIERC0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 578},
|
|
{"PCIERC1_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 578},
|
|
{"PCIERC0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 579},
|
|
{"PCIERC1_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 579},
|
|
{"PCIERC0_CFG039" , 0x9Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 580},
|
|
{"PCIERC1_CFG039" , 0x9Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 580},
|
|
{"PCIERC0_CFG040" , 0xA0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 581},
|
|
{"PCIERC1_CFG040" , 0xA0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 581},
|
|
{"PCIERC0_CFG041" , 0xA4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 582},
|
|
{"PCIERC1_CFG041" , 0xA4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 582},
|
|
{"PCIERC0_CFG042" , 0xA8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 583},
|
|
{"PCIERC1_CFG042" , 0xA8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 583},
|
|
{"PCIERC0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 584},
|
|
{"PCIERC1_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 584},
|
|
{"PCIERC0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 585},
|
|
{"PCIERC1_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 585},
|
|
{"PCIERC0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 586},
|
|
{"PCIERC1_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 586},
|
|
{"PCIERC0_CFG067" , 0x10Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 587},
|
|
{"PCIERC1_CFG067" , 0x10Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 587},
|
|
{"PCIERC0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 588},
|
|
{"PCIERC1_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 588},
|
|
{"PCIERC0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 589},
|
|
{"PCIERC1_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 589},
|
|
{"PCIERC0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 590},
|
|
{"PCIERC1_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 590},
|
|
{"PCIERC0_CFG071" , 0x11Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 591},
|
|
{"PCIERC1_CFG071" , 0x11Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 591},
|
|
{"PCIERC0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 592},
|
|
{"PCIERC1_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 592},
|
|
{"PCIERC0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 593},
|
|
{"PCIERC1_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 593},
|
|
{"PCIERC0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 594},
|
|
{"PCIERC1_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 594},
|
|
{"PCIERC0_CFG075" , 0x12Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 595},
|
|
{"PCIERC1_CFG075" , 0x12Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 595},
|
|
{"PCIERC0_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 596},
|
|
{"PCIERC1_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 596},
|
|
{"PCIERC0_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 597},
|
|
{"PCIERC1_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 597},
|
|
{"PCIERC0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 598},
|
|
{"PCIERC1_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 598},
|
|
{"PCIERC0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 599},
|
|
{"PCIERC1_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 599},
|
|
{"PCIERC0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 600},
|
|
{"PCIERC1_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 600},
|
|
{"PCIERC0_CFG451" , 0x70Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 601},
|
|
{"PCIERC1_CFG451" , 0x70Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 601},
|
|
{"PCIERC0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 602},
|
|
{"PCIERC1_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 602},
|
|
{"PCIERC0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 603},
|
|
{"PCIERC1_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 603},
|
|
{"PCIERC0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 604},
|
|
{"PCIERC1_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 604},
|
|
{"PCIERC0_CFG455" , 0x71Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 605},
|
|
{"PCIERC1_CFG455" , 0x71Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 605},
|
|
{"PCIERC0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 606},
|
|
{"PCIERC1_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 606},
|
|
{"PCIERC0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 607},
|
|
{"PCIERC1_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 607},
|
|
{"PCIERC0_CFG459" , 0x72Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 608},
|
|
{"PCIERC1_CFG459" , 0x72Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 608},
|
|
{"PCIERC0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 609},
|
|
{"PCIERC1_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 609},
|
|
{"PCIERC0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 610},
|
|
{"PCIERC1_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 610},
|
|
{"PCIERC0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 611},
|
|
{"PCIERC1_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 611},
|
|
{"PCIERC0_CFG463" , 0x73Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 612},
|
|
{"PCIERC1_CFG463" , 0x73Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 612},
|
|
{"PCIERC0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 613},
|
|
{"PCIERC1_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 613},
|
|
{"PCIERC0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 614},
|
|
{"PCIERC1_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 614},
|
|
{"PCIERC0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 615},
|
|
{"PCIERC1_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 615},
|
|
{"PCIERC0_CFG467" , 0x74Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 616},
|
|
{"PCIERC1_CFG467" , 0x74Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 616},
|
|
{"PCIERC0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 617},
|
|
{"PCIERC1_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 617},
|
|
{"PCIERC0_CFG490" , 0x7A8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 618},
|
|
{"PCIERC1_CFG490" , 0x7A8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 618},
|
|
{"PCIERC0_CFG491" , 0x7ACull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 619},
|
|
{"PCIERC1_CFG491" , 0x7ACull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 619},
|
|
{"PCIERC0_CFG492" , 0x7B0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 620},
|
|
{"PCIERC1_CFG492" , 0x7B0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 620},
|
|
{"PCIERC0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 621},
|
|
{"PCIERC1_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 621},
|
|
{"PCIERC0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 622},
|
|
{"PCIERC1_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 622},
|
|
{"PCS0_AN000_ADV_REG" , 0x11800B0001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
|
|
{"PCS0_AN001_ADV_REG" , 0x11800B0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
|
|
{"PCS0_AN002_ADV_REG" , 0x11800B0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
|
|
{"PCS0_AN003_ADV_REG" , 0x11800B0001C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 623},
|
|
{"PCS0_AN000_EXT_ST_REG" , 0x11800B0001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
|
|
{"PCS0_AN001_EXT_ST_REG" , 0x11800B0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
|
|
{"PCS0_AN002_EXT_ST_REG" , 0x11800B0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
|
|
{"PCS0_AN003_EXT_ST_REG" , 0x11800B0001C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 624},
|
|
{"PCS0_AN000_LP_ABIL_REG" , 0x11800B0001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
|
|
{"PCS0_AN001_LP_ABIL_REG" , 0x11800B0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
|
|
{"PCS0_AN002_LP_ABIL_REG" , 0x11800B0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
|
|
{"PCS0_AN003_LP_ABIL_REG" , 0x11800B0001C18ull, CVMX_CSR_DB_TYPE_RSL, 64, 625},
|
|
{"PCS0_AN000_RESULTS_REG" , 0x11800B0001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
|
|
{"PCS0_AN001_RESULTS_REG" , 0x11800B0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
|
|
{"PCS0_AN002_RESULTS_REG" , 0x11800B0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
|
|
{"PCS0_AN003_RESULTS_REG" , 0x11800B0001C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 626},
|
|
{"PCS0_INT000_EN_REG" , 0x11800B0001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
|
|
{"PCS0_INT001_EN_REG" , 0x11800B0001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
|
|
{"PCS0_INT002_EN_REG" , 0x11800B0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
|
|
{"PCS0_INT003_EN_REG" , 0x11800B0001C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 627},
|
|
{"PCS0_INT000_REG" , 0x11800B0001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
|
|
{"PCS0_INT001_REG" , 0x11800B0001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
|
|
{"PCS0_INT002_REG" , 0x11800B0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
|
|
{"PCS0_INT003_REG" , 0x11800B0001C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 628},
|
|
{"PCS0_LINK000_TIMER_COUNT_REG", 0x11800B0001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
|
|
{"PCS0_LINK001_TIMER_COUNT_REG", 0x11800B0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
|
|
{"PCS0_LINK002_TIMER_COUNT_REG", 0x11800B0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
|
|
{"PCS0_LINK003_TIMER_COUNT_REG", 0x11800B0001C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 629},
|
|
{"PCS0_LOG_ANL000_REG" , 0x11800B0001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
|
|
{"PCS0_LOG_ANL001_REG" , 0x11800B0001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
|
|
{"PCS0_LOG_ANL002_REG" , 0x11800B0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
|
|
{"PCS0_LOG_ANL003_REG" , 0x11800B0001C90ull, CVMX_CSR_DB_TYPE_RSL, 64, 630},
|
|
{"PCS0_MISC000_CTL_REG" , 0x11800B0001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
|
|
{"PCS0_MISC001_CTL_REG" , 0x11800B0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
|
|
{"PCS0_MISC002_CTL_REG" , 0x11800B0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
|
|
{"PCS0_MISC003_CTL_REG" , 0x11800B0001C78ull, CVMX_CSR_DB_TYPE_RSL, 64, 631},
|
|
{"PCS0_MR000_CONTROL_REG" , 0x11800B0001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
|
|
{"PCS0_MR001_CONTROL_REG" , 0x11800B0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
|
|
{"PCS0_MR002_CONTROL_REG" , 0x11800B0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
|
|
{"PCS0_MR003_CONTROL_REG" , 0x11800B0001C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 632},
|
|
{"PCS0_MR000_STATUS_REG" , 0x11800B0001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 633},
|
|
{"PCS0_MR001_STATUS_REG" , 0x11800B0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 633},
|
|
{"PCS0_MR002_STATUS_REG" , 0x11800B0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 633},
|
|
{"PCS0_MR003_STATUS_REG" , 0x11800B0001C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 633},
|
|
{"PCS0_RX000_STATES_REG" , 0x11800B0001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 634},
|
|
{"PCS0_RX001_STATES_REG" , 0x11800B0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 634},
|
|
{"PCS0_RX002_STATES_REG" , 0x11800B0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 634},
|
|
{"PCS0_RX003_STATES_REG" , 0x11800B0001C58ull, CVMX_CSR_DB_TYPE_RSL, 64, 634},
|
|
{"PCS0_RX000_SYNC_REG" , 0x11800B0001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 635},
|
|
{"PCS0_RX001_SYNC_REG" , 0x11800B0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 635},
|
|
{"PCS0_RX002_SYNC_REG" , 0x11800B0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 635},
|
|
{"PCS0_RX003_SYNC_REG" , 0x11800B0001C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 635},
|
|
{"PCS0_SGM000_AN_ADV_REG" , 0x11800B0001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
|
|
{"PCS0_SGM001_AN_ADV_REG" , 0x11800B0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
|
|
{"PCS0_SGM002_AN_ADV_REG" , 0x11800B0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
|
|
{"PCS0_SGM003_AN_ADV_REG" , 0x11800B0001C68ull, CVMX_CSR_DB_TYPE_RSL, 64, 636},
|
|
{"PCS0_SGM000_LP_ADV_REG" , 0x11800B0001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 637},
|
|
{"PCS0_SGM001_LP_ADV_REG" , 0x11800B0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 637},
|
|
{"PCS0_SGM002_LP_ADV_REG" , 0x11800B0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 637},
|
|
{"PCS0_SGM003_LP_ADV_REG" , 0x11800B0001C70ull, CVMX_CSR_DB_TYPE_RSL, 64, 637},
|
|
{"PCS0_TX000_STATES_REG" , 0x11800B0001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
|
|
{"PCS0_TX001_STATES_REG" , 0x11800B0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
|
|
{"PCS0_TX002_STATES_REG" , 0x11800B0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
|
|
{"PCS0_TX003_STATES_REG" , 0x11800B0001C60ull, CVMX_CSR_DB_TYPE_RSL, 64, 638},
|
|
{"PCS0_TX_RX000_POLARITY_REG" , 0x11800B0001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 639},
|
|
{"PCS0_TX_RX001_POLARITY_REG" , 0x11800B0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 639},
|
|
{"PCS0_TX_RX002_POLARITY_REG" , 0x11800B0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 639},
|
|
{"PCS0_TX_RX003_POLARITY_REG" , 0x11800B0001C48ull, CVMX_CSR_DB_TYPE_RSL, 64, 639},
|
|
{"PCSX0_10GBX_STATUS_REG" , 0x11800B0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
|
|
{"PCSX1_10GBX_STATUS_REG" , 0x11800B8000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 640},
|
|
{"PCSX0_BIST_STATUS_REG" , 0x11800B0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 641},
|
|
{"PCSX1_BIST_STATUS_REG" , 0x11800B8000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 641},
|
|
{"PCSX0_BIT_LOCK_STATUS_REG" , 0x11800B0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
|
|
{"PCSX1_BIT_LOCK_STATUS_REG" , 0x11800B8000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 642},
|
|
{"PCSX0_CONTROL1_REG" , 0x11800B0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 643},
|
|
{"PCSX1_CONTROL1_REG" , 0x11800B8000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 643},
|
|
{"PCSX0_CONTROL2_REG" , 0x11800B0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
|
|
{"PCSX1_CONTROL2_REG" , 0x11800B8000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 644},
|
|
{"PCSX0_INT_EN_REG" , 0x11800B0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 645},
|
|
{"PCSX1_INT_EN_REG" , 0x11800B8000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 645},
|
|
{"PCSX0_INT_REG" , 0x11800B0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
|
|
{"PCSX1_INT_REG" , 0x11800B8000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 646},
|
|
{"PCSX0_LOG_ANL_REG" , 0x11800B0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 647},
|
|
{"PCSX1_LOG_ANL_REG" , 0x11800B8000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 647},
|
|
{"PCSX0_MISC_CTL_REG" , 0x11800B0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 648},
|
|
{"PCSX1_MISC_CTL_REG" , 0x11800B8000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 648},
|
|
{"PCSX0_RX_SYNC_STATES_REG" , 0x11800B0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 649},
|
|
{"PCSX1_RX_SYNC_STATES_REG" , 0x11800B8000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 649},
|
|
{"PCSX0_SPD_ABIL_REG" , 0x11800B0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 650},
|
|
{"PCSX1_SPD_ABIL_REG" , 0x11800B8000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 650},
|
|
{"PCSX0_STATUS1_REG" , 0x11800B0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 651},
|
|
{"PCSX1_STATUS1_REG" , 0x11800B8000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 651},
|
|
{"PCSX0_STATUS2_REG" , 0x11800B0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 652},
|
|
{"PCSX1_STATUS2_REG" , 0x11800B8000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 652},
|
|
{"PCSX0_TX_RX_POLARITY_REG" , 0x11800B0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 653},
|
|
{"PCSX1_TX_RX_POLARITY_REG" , 0x11800B8000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 653},
|
|
{"PCSX0_TX_RX_STATES_REG" , 0x11800B0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 654},
|
|
{"PCSX1_TX_RX_STATES_REG" , 0x11800B8000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 654},
|
|
{"PESC0_BIST_STATUS" , 0x11800C8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 655},
|
|
{"PESC1_BIST_STATUS" , 0x11800D0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 655},
|
|
{"PESC0_BIST_STATUS2" , 0x11800C8000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 656},
|
|
{"PESC1_BIST_STATUS2" , 0x11800D0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 656},
|
|
{"PESC0_CFG_RD" , 0x11800C8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 657},
|
|
{"PESC1_CFG_RD" , 0x11800D0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 657},
|
|
{"PESC0_CFG_WR" , 0x11800C8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 658},
|
|
{"PESC1_CFG_WR" , 0x11800D0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 658},
|
|
{"PESC0_CPL_LUT_VALID" , 0x11800C8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 659},
|
|
{"PESC1_CPL_LUT_VALID" , 0x11800D0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 659},
|
|
{"PESC0_CTL_STATUS" , 0x11800C8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 660},
|
|
{"PESC1_CTL_STATUS" , 0x11800D0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 660},
|
|
{"PESC0_CTL_STATUS2" , 0x11800C8000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
|
|
{"PESC1_CTL_STATUS2" , 0x11800D0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 661},
|
|
{"PESC0_DBG_INFO" , 0x11800C8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
|
|
{"PESC1_DBG_INFO" , 0x11800D0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 662},
|
|
{"PESC0_DBG_INFO_EN" , 0x11800C80000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 663},
|
|
{"PESC1_DBG_INFO_EN" , 0x11800D00000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 663},
|
|
{"PESC0_DIAG_STATUS" , 0x11800C8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 664},
|
|
{"PESC1_DIAG_STATUS" , 0x11800D0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 664},
|
|
{"PESC0_P2N_BAR0_START" , 0x11800C8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 665},
|
|
{"PESC1_P2N_BAR0_START" , 0x11800D0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 665},
|
|
{"PESC0_P2N_BAR1_START" , 0x11800C8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 666},
|
|
{"PESC1_P2N_BAR1_START" , 0x11800D0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 666},
|
|
{"PESC0_P2N_BAR2_START" , 0x11800C8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 667},
|
|
{"PESC1_P2N_BAR2_START" , 0x11800D0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 667},
|
|
{"PESC0_P2P_BAR000_END" , 0x11800C8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
|
|
{"PESC0_P2P_BAR001_END" , 0x11800C8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
|
|
{"PESC0_P2P_BAR002_END" , 0x11800C8000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
|
|
{"PESC0_P2P_BAR003_END" , 0x11800C8000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
|
|
{"PESC1_P2P_BAR000_END" , 0x11800D0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
|
|
{"PESC1_P2P_BAR001_END" , 0x11800D0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
|
|
{"PESC1_P2P_BAR002_END" , 0x11800D0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
|
|
{"PESC1_P2P_BAR003_END" , 0x11800D0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 668},
|
|
{"PESC0_P2P_BAR000_START" , 0x11800C8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
|
|
{"PESC0_P2P_BAR001_START" , 0x11800C8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
|
|
{"PESC0_P2P_BAR002_START" , 0x11800C8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
|
|
{"PESC0_P2P_BAR003_START" , 0x11800C8000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
|
|
{"PESC1_P2P_BAR000_START" , 0x11800D0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
|
|
{"PESC1_P2P_BAR001_START" , 0x11800D0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
|
|
{"PESC1_P2P_BAR002_START" , 0x11800D0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
|
|
{"PESC1_P2P_BAR003_START" , 0x11800D0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 669},
|
|
{"PESC0_TLP_CREDITS" , 0x11800C8000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 670},
|
|
{"PESC1_TLP_CREDITS" , 0x11800D0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 670},
|
|
{"PIP_BIST_STATUS" , 0x11800A0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 671},
|
|
{"PIP_DEC_IPSEC0" , 0x11800A0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 672},
|
|
{"PIP_DEC_IPSEC1" , 0x11800A0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 672},
|
|
{"PIP_DEC_IPSEC2" , 0x11800A0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 672},
|
|
{"PIP_DEC_IPSEC3" , 0x11800A0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 672},
|
|
{"PIP_DSA_SRC_GRP" , 0x11800A0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 673},
|
|
{"PIP_DSA_VID_GRP" , 0x11800A0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 674},
|
|
{"PIP_FRM_LEN_CHK0" , 0x11800A0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_FRM_LEN_CHK1" , 0x11800A0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 675},
|
|
{"PIP_GBL_CFG" , 0x11800A0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 676},
|
|
{"PIP_GBL_CTL" , 0x11800A0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 677},
|
|
{"PIP_HG_PRI_QOS" , 0x11800A00001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 678},
|
|
{"PIP_INT_EN" , 0x11800A0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 679},
|
|
{"PIP_INT_REG" , 0x11800A0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 680},
|
|
{"PIP_IP_OFFSET" , 0x11800A0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 681},
|
|
{"PIP_PRT_CFG0" , 0x11800A0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PIP_PRT_CFG1" , 0x11800A0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PIP_PRT_CFG2" , 0x11800A0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PIP_PRT_CFG3" , 0x11800A0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PIP_PRT_CFG36" , 0x11800A0000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PIP_PRT_CFG37" , 0x11800A0000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PIP_PRT_CFG38" , 0x11800A0000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PIP_PRT_CFG39" , 0x11800A0000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 682},
|
|
{"PIP_PRT_TAG0" , 0x11800A0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PIP_PRT_TAG1" , 0x11800A0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PIP_PRT_TAG2" , 0x11800A0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PIP_PRT_TAG3" , 0x11800A0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PIP_PRT_TAG36" , 0x11800A0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PIP_PRT_TAG37" , 0x11800A0000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PIP_PRT_TAG38" , 0x11800A0000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PIP_PRT_TAG39" , 0x11800A0000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 683},
|
|
{"PIP_QOS_DIFF0" , 0x11800A0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF1" , 0x11800A0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF2" , 0x11800A0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF3" , 0x11800A0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF4" , 0x11800A0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF5" , 0x11800A0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF6" , 0x11800A0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF7" , 0x11800A0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF8" , 0x11800A0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF9" , 0x11800A0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF10" , 0x11800A0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF11" , 0x11800A0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF12" , 0x11800A0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF13" , 0x11800A0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF14" , 0x11800A0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF15" , 0x11800A0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF16" , 0x11800A0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF17" , 0x11800A0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF18" , 0x11800A0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF19" , 0x11800A0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF20" , 0x11800A00006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF21" , 0x11800A00006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF22" , 0x11800A00006B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF23" , 0x11800A00006B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF24" , 0x11800A00006C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF25" , 0x11800A00006C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF26" , 0x11800A00006D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF27" , 0x11800A00006D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF28" , 0x11800A00006E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF29" , 0x11800A00006E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF30" , 0x11800A00006F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF31" , 0x11800A00006F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF32" , 0x11800A0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF33" , 0x11800A0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF34" , 0x11800A0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF35" , 0x11800A0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF36" , 0x11800A0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF37" , 0x11800A0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF38" , 0x11800A0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF39" , 0x11800A0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF40" , 0x11800A0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF41" , 0x11800A0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF42" , 0x11800A0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF43" , 0x11800A0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF44" , 0x11800A0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF45" , 0x11800A0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF46" , 0x11800A0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF47" , 0x11800A0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF48" , 0x11800A0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF49" , 0x11800A0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF50" , 0x11800A0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF51" , 0x11800A0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF52" , 0x11800A00007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF53" , 0x11800A00007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF54" , 0x11800A00007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF55" , 0x11800A00007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF56" , 0x11800A00007C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF57" , 0x11800A00007C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF58" , 0x11800A00007D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF59" , 0x11800A00007D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF60" , 0x11800A00007E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF61" , 0x11800A00007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF62" , 0x11800A00007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_DIFF63" , 0x11800A00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 684},
|
|
{"PIP_QOS_VLAN0" , 0x11800A00000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PIP_QOS_VLAN1" , 0x11800A00000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PIP_QOS_VLAN2" , 0x11800A00000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PIP_QOS_VLAN3" , 0x11800A00000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PIP_QOS_VLAN4" , 0x11800A00000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PIP_QOS_VLAN5" , 0x11800A00000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PIP_QOS_VLAN6" , 0x11800A00000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PIP_QOS_VLAN7" , 0x11800A00000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 685},
|
|
{"PIP_QOS_WATCH0" , 0x11800A0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PIP_QOS_WATCH1" , 0x11800A0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PIP_QOS_WATCH2" , 0x11800A0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PIP_QOS_WATCH3" , 0x11800A0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PIP_QOS_WATCH4" , 0x11800A0000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PIP_QOS_WATCH5" , 0x11800A0000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PIP_QOS_WATCH6" , 0x11800A0000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PIP_QOS_WATCH7" , 0x11800A0000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 686},
|
|
{"PIP_RAW_WORD" , 0x11800A00000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 687},
|
|
{"PIP_SFT_RST" , 0x11800A0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 688},
|
|
{"PIP_STAT0_PRT0" , 0x11800A0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PIP_STAT0_PRT1" , 0x11800A0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PIP_STAT0_PRT2" , 0x11800A00008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PIP_STAT0_PRT3" , 0x11800A00008F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PIP_STAT0_PRT36" , 0x11800A0001340ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PIP_STAT0_PRT37" , 0x11800A0001390ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PIP_STAT0_PRT38" , 0x11800A00013E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PIP_STAT0_PRT39" , 0x11800A0001430ull, CVMX_CSR_DB_TYPE_RSL, 64, 689},
|
|
{"PIP_STAT1_PRT0" , 0x11800A0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
|
|
{"PIP_STAT1_PRT1" , 0x11800A0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
|
|
{"PIP_STAT1_PRT2" , 0x11800A00008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
|
|
{"PIP_STAT1_PRT3" , 0x11800A00008F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
|
|
{"PIP_STAT1_PRT36" , 0x11800A0001348ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
|
|
{"PIP_STAT1_PRT37" , 0x11800A0001398ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
|
|
{"PIP_STAT1_PRT38" , 0x11800A00013E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
|
|
{"PIP_STAT1_PRT39" , 0x11800A0001438ull, CVMX_CSR_DB_TYPE_RSL, 64, 690},
|
|
{"PIP_STAT2_PRT0" , 0x11800A0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PIP_STAT2_PRT1" , 0x11800A0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PIP_STAT2_PRT2" , 0x11800A00008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PIP_STAT2_PRT3" , 0x11800A0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PIP_STAT2_PRT36" , 0x11800A0001350ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PIP_STAT2_PRT37" , 0x11800A00013A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PIP_STAT2_PRT38" , 0x11800A00013F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PIP_STAT2_PRT39" , 0x11800A0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 691},
|
|
{"PIP_STAT3_PRT0" , 0x11800A0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PIP_STAT3_PRT1" , 0x11800A0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PIP_STAT3_PRT2" , 0x11800A00008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PIP_STAT3_PRT3" , 0x11800A0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PIP_STAT3_PRT36" , 0x11800A0001358ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PIP_STAT3_PRT37" , 0x11800A00013A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PIP_STAT3_PRT38" , 0x11800A00013F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PIP_STAT3_PRT39" , 0x11800A0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 692},
|
|
{"PIP_STAT4_PRT0" , 0x11800A0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PIP_STAT4_PRT1" , 0x11800A0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PIP_STAT4_PRT2" , 0x11800A00008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PIP_STAT4_PRT3" , 0x11800A0000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PIP_STAT4_PRT36" , 0x11800A0001360ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PIP_STAT4_PRT37" , 0x11800A00013B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PIP_STAT4_PRT38" , 0x11800A0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PIP_STAT4_PRT39" , 0x11800A0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 693},
|
|
{"PIP_STAT5_PRT0" , 0x11800A0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_STAT5_PRT1" , 0x11800A0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_STAT5_PRT2" , 0x11800A00008C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_STAT5_PRT3" , 0x11800A0000918ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_STAT5_PRT36" , 0x11800A0001368ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_STAT5_PRT37" , 0x11800A00013B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_STAT5_PRT38" , 0x11800A0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_STAT5_PRT39" , 0x11800A0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PIP_STAT6_PRT0" , 0x11800A0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
|
|
{"PIP_STAT6_PRT1" , 0x11800A0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
|
|
{"PIP_STAT6_PRT2" , 0x11800A00008D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
|
|
{"PIP_STAT6_PRT3" , 0x11800A0000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
|
|
{"PIP_STAT6_PRT36" , 0x11800A0001370ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
|
|
{"PIP_STAT6_PRT37" , 0x11800A00013C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
|
|
{"PIP_STAT6_PRT38" , 0x11800A0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
|
|
{"PIP_STAT6_PRT39" , 0x11800A0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
|
|
{"PIP_STAT7_PRT0" , 0x11800A0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
|
|
{"PIP_STAT7_PRT1" , 0x11800A0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
|
|
{"PIP_STAT7_PRT2" , 0x11800A00008D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
|
|
{"PIP_STAT7_PRT3" , 0x11800A0000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
|
|
{"PIP_STAT7_PRT36" , 0x11800A0001378ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
|
|
{"PIP_STAT7_PRT37" , 0x11800A00013C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
|
|
{"PIP_STAT7_PRT38" , 0x11800A0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
|
|
{"PIP_STAT7_PRT39" , 0x11800A0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
|
|
{"PIP_STAT8_PRT0" , 0x11800A0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
|
|
{"PIP_STAT8_PRT1" , 0x11800A0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
|
|
{"PIP_STAT8_PRT2" , 0x11800A00008E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
|
|
{"PIP_STAT8_PRT3" , 0x11800A0000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
|
|
{"PIP_STAT8_PRT36" , 0x11800A0001380ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
|
|
{"PIP_STAT8_PRT37" , 0x11800A00013D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
|
|
{"PIP_STAT8_PRT38" , 0x11800A0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
|
|
{"PIP_STAT8_PRT39" , 0x11800A0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
|
|
{"PIP_STAT9_PRT0" , 0x11800A0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
|
|
{"PIP_STAT9_PRT1" , 0x11800A0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
|
|
{"PIP_STAT9_PRT2" , 0x11800A00008E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
|
|
{"PIP_STAT9_PRT3" , 0x11800A0000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
|
|
{"PIP_STAT9_PRT36" , 0x11800A0001388ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
|
|
{"PIP_STAT9_PRT37" , 0x11800A00013D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
|
|
{"PIP_STAT9_PRT38" , 0x11800A0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
|
|
{"PIP_STAT9_PRT39" , 0x11800A0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
|
|
{"PIP_STAT_CTL" , 0x11800A0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
|
|
{"PIP_STAT_INB_ERRS0" , 0x11800A0001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
|
|
{"PIP_STAT_INB_ERRS1" , 0x11800A0001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
|
|
{"PIP_STAT_INB_ERRS2" , 0x11800A0001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
|
|
{"PIP_STAT_INB_ERRS3" , 0x11800A0001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
|
|
{"PIP_STAT_INB_ERRS36" , 0x11800A0001E90ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
|
|
{"PIP_STAT_INB_ERRS37" , 0x11800A0001EB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
|
|
{"PIP_STAT_INB_ERRS38" , 0x11800A0001ED0ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
|
|
{"PIP_STAT_INB_ERRS39" , 0x11800A0001EF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
|
|
{"PIP_STAT_INB_OCTS0" , 0x11800A0001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
|
|
{"PIP_STAT_INB_OCTS1" , 0x11800A0001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
|
|
{"PIP_STAT_INB_OCTS2" , 0x11800A0001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
|
|
{"PIP_STAT_INB_OCTS3" , 0x11800A0001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
|
|
{"PIP_STAT_INB_OCTS36" , 0x11800A0001E88ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
|
|
{"PIP_STAT_INB_OCTS37" , 0x11800A0001EA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
|
|
{"PIP_STAT_INB_OCTS38" , 0x11800A0001EC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
|
|
{"PIP_STAT_INB_OCTS39" , 0x11800A0001EE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
|
|
{"PIP_STAT_INB_PKTS0" , 0x11800A0001A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
|
|
{"PIP_STAT_INB_PKTS1" , 0x11800A0001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
|
|
{"PIP_STAT_INB_PKTS2" , 0x11800A0001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
|
|
{"PIP_STAT_INB_PKTS3" , 0x11800A0001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
|
|
{"PIP_STAT_INB_PKTS36" , 0x11800A0001E80ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
|
|
{"PIP_STAT_INB_PKTS37" , 0x11800A0001EA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
|
|
{"PIP_STAT_INB_PKTS38" , 0x11800A0001EC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
|
|
{"PIP_STAT_INB_PKTS39" , 0x11800A0001EE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
|
|
{"PIP_TAG_INC0" , 0x11800A0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC1" , 0x11800A0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC2" , 0x11800A0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC3" , 0x11800A0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC4" , 0x11800A0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC5" , 0x11800A0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC6" , 0x11800A0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC7" , 0x11800A0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC8" , 0x11800A0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC9" , 0x11800A0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC10" , 0x11800A0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC11" , 0x11800A0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC12" , 0x11800A0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC13" , 0x11800A0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC14" , 0x11800A0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC15" , 0x11800A0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC16" , 0x11800A0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC17" , 0x11800A0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC18" , 0x11800A0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC19" , 0x11800A0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC20" , 0x11800A00018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC21" , 0x11800A00018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC22" , 0x11800A00018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC23" , 0x11800A00018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC24" , 0x11800A00018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC25" , 0x11800A00018C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC26" , 0x11800A00018D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC27" , 0x11800A00018D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC28" , 0x11800A00018E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC29" , 0x11800A00018E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC30" , 0x11800A00018F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC31" , 0x11800A00018F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC32" , 0x11800A0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC33" , 0x11800A0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC34" , 0x11800A0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC35" , 0x11800A0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC36" , 0x11800A0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC37" , 0x11800A0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC38" , 0x11800A0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC39" , 0x11800A0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC40" , 0x11800A0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC41" , 0x11800A0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC42" , 0x11800A0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC43" , 0x11800A0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC44" , 0x11800A0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC45" , 0x11800A0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC46" , 0x11800A0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC47" , 0x11800A0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC48" , 0x11800A0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC49" , 0x11800A0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC50" , 0x11800A0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC51" , 0x11800A0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC52" , 0x11800A00019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC53" , 0x11800A00019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC54" , 0x11800A00019B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC55" , 0x11800A00019B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC56" , 0x11800A00019C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC57" , 0x11800A00019C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC58" , 0x11800A00019D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC59" , 0x11800A00019D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC60" , 0x11800A00019E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC61" , 0x11800A00019E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC62" , 0x11800A00019F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_INC63" , 0x11800A00019F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PIP_TAG_MASK" , 0x11800A0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
|
|
{"PIP_TAG_SECRET" , 0x11800A0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
|
|
{"PIP_TODO_ENTRY" , 0x11800A0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
|
|
{"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
|
|
{"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
|
|
{"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
|
|
{"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
|
|
{"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 711},
|
|
{"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 712},
|
|
{"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 713},
|
|
{"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 714},
|
|
{"PKO_MEM_DEBUG14" , 0x1180050001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 715},
|
|
{"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 716},
|
|
{"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 717},
|
|
{"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 718},
|
|
{"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 719},
|
|
{"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 720},
|
|
{"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 721},
|
|
{"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 722},
|
|
{"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 723},
|
|
{"PKO_MEM_PORT_PTRS" , 0x1180050001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
|
|
{"PKO_MEM_PORT_QOS" , 0x1180050001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
|
|
{"PKO_MEM_PORT_RATE0" , 0x1180050001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 726},
|
|
{"PKO_MEM_PORT_RATE1" , 0x1180050001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 727},
|
|
{"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 728},
|
|
{"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 729},
|
|
{"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
|
|
{"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 731},
|
|
{"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 732},
|
|
{"PKO_REG_DEBUG1" , 0x11800500000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 733},
|
|
{"PKO_REG_DEBUG2" , 0x11800500000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 734},
|
|
{"PKO_REG_DEBUG3" , 0x11800500000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 735},
|
|
{"PKO_REG_ENGINE_INFLIGHT" , 0x1180050000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 736},
|
|
{"PKO_REG_ENGINE_THRESH" , 0x1180050000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 737},
|
|
{"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
|
|
{"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
|
|
{"PKO_REG_QUEUE_PTRS1" , 0x1180050000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
|
|
{"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 744},
|
|
{"POW_BIST_STAT" , 0x16700000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 745},
|
|
{"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 746},
|
|
{"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 747},
|
|
{"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 748},
|
|
{"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
|
|
{"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
|
|
{"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
|
|
{"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
|
|
{"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
|
|
{"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
|
|
{"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
|
|
{"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 749},
|
|
{"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 750},
|
|
{"POW_IQ_INT" , 0x1670000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 751},
|
|
{"POW_IQ_INT_EN" , 0x1670000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 752},
|
|
{"POW_IQ_THR0" , 0x16700000003A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
|
|
{"POW_IQ_THR1" , 0x16700000003A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
|
|
{"POW_IQ_THR2" , 0x16700000003B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
|
|
{"POW_IQ_THR3" , 0x16700000003B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
|
|
{"POW_IQ_THR4" , 0x16700000003C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
|
|
{"POW_IQ_THR5" , 0x16700000003C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
|
|
{"POW_IQ_THR6" , 0x16700000003D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
|
|
{"POW_IQ_THR7" , 0x16700000003D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 753},
|
|
{"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 754},
|
|
{"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 755},
|
|
{"POW_PF_RST_MSK" , 0x1670000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 756},
|
|
{"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
|
|
{"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
|
|
{"POW_PP_GRP_MSK2" , 0x1670000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
|
|
{"POW_PP_GRP_MSK3" , 0x1670000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 757},
|
|
{"POW_QOS_RND0" , 0x16700000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
|
|
{"POW_QOS_RND1" , 0x16700000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
|
|
{"POW_QOS_RND2" , 0x16700000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
|
|
{"POW_QOS_RND3" , 0x16700000001D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
|
|
{"POW_QOS_RND4" , 0x16700000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
|
|
{"POW_QOS_RND5" , 0x16700000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
|
|
{"POW_QOS_RND6" , 0x16700000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
|
|
{"POW_QOS_RND7" , 0x16700000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 758},
|
|
{"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 759},
|
|
{"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 759},
|
|
{"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 759},
|
|
{"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 759},
|
|
{"POW_QOS_THR4" , 0x16700000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 759},
|
|
{"POW_QOS_THR5" , 0x16700000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 759},
|
|
{"POW_QOS_THR6" , 0x16700000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 759},
|
|
{"POW_QOS_THR7" , 0x16700000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 759},
|
|
{"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 760},
|
|
{"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 761},
|
|
{"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 762},
|
|
{"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 762},
|
|
{"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 762},
|
|
{"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 762},
|
|
{"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 762},
|
|
{"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 762},
|
|
{"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 762},
|
|
{"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 762},
|
|
{"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 763},
|
|
{"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
|
|
{"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
|
|
{"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
|
|
{"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
|
|
{"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
|
|
{"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
|
|
{"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
|
|
{"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
|
|
{"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
|
|
{"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
|
|
{"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
|
|
{"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
|
|
{"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
|
|
{"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
|
|
{"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
|
|
{"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 764},
|
|
{"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 765},
|
|
{"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
|
|
{"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
|
|
{"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
|
|
{"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
|
|
{"POW_WQ_INT_THR4" , 0x16700000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
|
|
{"POW_WQ_INT_THR5" , 0x16700000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
|
|
{"POW_WQ_INT_THR6" , 0x16700000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
|
|
{"POW_WQ_INT_THR7" , 0x16700000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
|
|
{"POW_WQ_INT_THR8" , 0x16700000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
|
|
{"POW_WQ_INT_THR9" , 0x16700000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
|
|
{"POW_WQ_INT_THR10" , 0x16700000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
|
|
{"POW_WQ_INT_THR11" , 0x16700000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
|
|
{"POW_WQ_INT_THR12" , 0x16700000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
|
|
{"POW_WQ_INT_THR13" , 0x16700000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
|
|
{"POW_WQ_INT_THR14" , 0x16700000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
|
|
{"POW_WQ_INT_THR15" , 0x16700000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 766},
|
|
{"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
|
|
{"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
|
|
{"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
|
|
{"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
|
|
{"POW_WS_PC4" , 0x16700000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
|
|
{"POW_WS_PC5" , 0x16700000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
|
|
{"POW_WS_PC6" , 0x16700000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
|
|
{"POW_WS_PC7" , 0x16700000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
|
|
{"POW_WS_PC8" , 0x16700000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
|
|
{"POW_WS_PC9" , 0x16700000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
|
|
{"POW_WS_PC10" , 0x16700000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
|
|
{"POW_WS_PC11" , 0x16700000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
|
|
{"POW_WS_PC12" , 0x16700000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
|
|
{"POW_WS_PC13" , 0x16700000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
|
|
{"POW_WS_PC14" , 0x16700000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
|
|
{"POW_WS_PC15" , 0x16700000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 767},
|
|
{"RAD_MEM_DEBUG0" , 0x1180070001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
|
|
{"RAD_MEM_DEBUG1" , 0x1180070001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
|
|
{"RAD_MEM_DEBUG2" , 0x1180070001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
|
|
{"RAD_REG_BIST_RESULT" , 0x1180070000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
|
|
{"RAD_REG_CMD_BUF" , 0x1180070000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
|
|
{"RAD_REG_CTL" , 0x1180070000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
|
|
{"RAD_REG_DEBUG0" , 0x1180070000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"RAD_REG_DEBUG1" , 0x1180070000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
|
|
{"RAD_REG_DEBUG10" , 0x1180070000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
|
|
{"RAD_REG_DEBUG11" , 0x1180070000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
|
|
{"RAD_REG_DEBUG12" , 0x1180070000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
|
|
{"RAD_REG_DEBUG2" , 0x1180070000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
|
|
{"RAD_REG_DEBUG3" , 0x1180070000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
|
|
{"RAD_REG_DEBUG4" , 0x1180070000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
|
|
{"RAD_REG_DEBUG5" , 0x1180070000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
|
|
{"RAD_REG_DEBUG6" , 0x1180070000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
|
|
{"RAD_REG_DEBUG7" , 0x1180070000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
|
|
{"RAD_REG_DEBUG8" , 0x1180070000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
|
|
{"RAD_REG_DEBUG9" , 0x1180070000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
|
|
{"RAD_REG_ERROR" , 0x1180070000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
|
|
{"RAD_REG_INT_MASK" , 0x1180070000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
|
|
{"RAD_REG_POLYNOMIAL" , 0x1180070000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
|
|
{"RAD_REG_READ_IDX" , 0x1180070000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 790},
|
|
{"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
|
|
{"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
|
|
{"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
|
|
{"SMI1_CLK" , 0x1180000001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
|
|
{"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
|
|
{"SMI1_CMD" , 0x1180000001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
|
|
{"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 795},
|
|
{"SMI1_EN" , 0x1180000001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 795},
|
|
{"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 796},
|
|
{"SMI1_RD_DAT" , 0x1180000001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 796},
|
|
{"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 797},
|
|
{"SMI1_WR_DAT" , 0x1180000001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 797},
|
|
{"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 798},
|
|
{"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 799},
|
|
{"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 800},
|
|
{"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 801},
|
|
{"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 802},
|
|
{"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 803},
|
|
{"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 804},
|
|
{"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 805},
|
|
{"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 806},
|
|
{"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 807},
|
|
{"TRA_BIST_STATUS" , 0x11800A8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 808},
|
|
{"TRA_CTL" , 0x11800A8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 809},
|
|
{"TRA_CYCLES_SINCE" , 0x11800A8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 810},
|
|
{"TRA_CYCLES_SINCE1" , 0x11800A8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 811},
|
|
{"TRA_FILT_ADR_ADR" , 0x11800A8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 812},
|
|
{"TRA_FILT_ADR_MSK" , 0x11800A8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 813},
|
|
{"TRA_FILT_CMD" , 0x11800A8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 814},
|
|
{"TRA_FILT_DID" , 0x11800A8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 815},
|
|
{"TRA_FILT_SID" , 0x11800A8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 816},
|
|
{"TRA_INT_STATUS" , 0x11800A8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 817},
|
|
{"TRA_READ_DAT" , 0x11800A8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 818},
|
|
{"TRA_TRIG0_ADR_ADR" , 0x11800A8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 819},
|
|
{"TRA_TRIG0_ADR_MSK" , 0x11800A80000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 820},
|
|
{"TRA_TRIG0_CMD" , 0x11800A8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 821},
|
|
{"TRA_TRIG0_DID" , 0x11800A8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 822},
|
|
{"TRA_TRIG0_SID" , 0x11800A8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 823},
|
|
{"TRA_TRIG1_ADR_ADR" , 0x11800A80000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 824},
|
|
{"TRA_TRIG1_ADR_MSK" , 0x11800A80000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 825},
|
|
{"TRA_TRIG1_CMD" , 0x11800A80000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 826},
|
|
{"TRA_TRIG1_DID" , 0x11800A80000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 827},
|
|
{"TRA_TRIG1_SID" , 0x11800A80000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 828},
|
|
{"USBC0_DAINT" , 0x16F0010000818ull, CVMX_CSR_DB_TYPE_NCB, 32, 829},
|
|
{"USBC1_DAINT" , 0x17F0010000818ull, CVMX_CSR_DB_TYPE_NCB, 32, 829},
|
|
{"USBC0_DAINTMSK" , 0x16F001000081Cull, CVMX_CSR_DB_TYPE_NCB, 32, 830},
|
|
{"USBC1_DAINTMSK" , 0x17F001000081Cull, CVMX_CSR_DB_TYPE_NCB, 32, 830},
|
|
{"USBC0_DCFG" , 0x16F0010000800ull, CVMX_CSR_DB_TYPE_NCB, 32, 831},
|
|
{"USBC1_DCFG" , 0x17F0010000800ull, CVMX_CSR_DB_TYPE_NCB, 32, 831},
|
|
{"USBC0_DCTL" , 0x16F0010000804ull, CVMX_CSR_DB_TYPE_NCB, 32, 832},
|
|
{"USBC1_DCTL" , 0x17F0010000804ull, CVMX_CSR_DB_TYPE_NCB, 32, 832},
|
|
{"USBC0_DIEPCTL000" , 0x16F0010000900ull, CVMX_CSR_DB_TYPE_NCB, 32, 833},
|
|
{"USBC0_DIEPCTL001" , 0x16F0010000920ull, CVMX_CSR_DB_TYPE_NCB, 32, 833},
|
|
{"USBC0_DIEPCTL002" , 0x16F0010000940ull, CVMX_CSR_DB_TYPE_NCB, 32, 833},
|
|
{"USBC0_DIEPCTL003" , 0x16F0010000960ull, CVMX_CSR_DB_TYPE_NCB, 32, 833},
|
|
{"USBC0_DIEPCTL004" , 0x16F0010000980ull, CVMX_CSR_DB_TYPE_NCB, 32, 833},
|
|
{"USBC1_DIEPCTL000" , 0x17F0010000900ull, CVMX_CSR_DB_TYPE_NCB, 32, 833},
|
|
{"USBC1_DIEPCTL001" , 0x17F0010000920ull, CVMX_CSR_DB_TYPE_NCB, 32, 833},
|
|
{"USBC1_DIEPCTL002" , 0x17F0010000940ull, CVMX_CSR_DB_TYPE_NCB, 32, 833},
|
|
{"USBC1_DIEPCTL003" , 0x17F0010000960ull, CVMX_CSR_DB_TYPE_NCB, 32, 833},
|
|
{"USBC1_DIEPCTL004" , 0x17F0010000980ull, CVMX_CSR_DB_TYPE_NCB, 32, 833},
|
|
{"USBC0_DIEPINT000" , 0x16F0010000908ull, CVMX_CSR_DB_TYPE_NCB, 32, 834},
|
|
{"USBC0_DIEPINT001" , 0x16F0010000928ull, CVMX_CSR_DB_TYPE_NCB, 32, 834},
|
|
{"USBC0_DIEPINT002" , 0x16F0010000948ull, CVMX_CSR_DB_TYPE_NCB, 32, 834},
|
|
{"USBC0_DIEPINT003" , 0x16F0010000968ull, CVMX_CSR_DB_TYPE_NCB, 32, 834},
|
|
{"USBC0_DIEPINT004" , 0x16F0010000988ull, CVMX_CSR_DB_TYPE_NCB, 32, 834},
|
|
{"USBC1_DIEPINT000" , 0x17F0010000908ull, CVMX_CSR_DB_TYPE_NCB, 32, 834},
|
|
{"USBC1_DIEPINT001" , 0x17F0010000928ull, CVMX_CSR_DB_TYPE_NCB, 32, 834},
|
|
{"USBC1_DIEPINT002" , 0x17F0010000948ull, CVMX_CSR_DB_TYPE_NCB, 32, 834},
|
|
{"USBC1_DIEPINT003" , 0x17F0010000968ull, CVMX_CSR_DB_TYPE_NCB, 32, 834},
|
|
{"USBC1_DIEPINT004" , 0x17F0010000988ull, CVMX_CSR_DB_TYPE_NCB, 32, 834},
|
|
{"USBC0_DIEPMSK" , 0x16F0010000810ull, CVMX_CSR_DB_TYPE_NCB, 32, 835},
|
|
{"USBC1_DIEPMSK" , 0x17F0010000810ull, CVMX_CSR_DB_TYPE_NCB, 32, 835},
|
|
{"USBC0_DIEPTSIZ000" , 0x16F0010000910ull, CVMX_CSR_DB_TYPE_NCB, 32, 836},
|
|
{"USBC0_DIEPTSIZ001" , 0x16F0010000930ull, CVMX_CSR_DB_TYPE_NCB, 32, 836},
|
|
{"USBC0_DIEPTSIZ002" , 0x16F0010000950ull, CVMX_CSR_DB_TYPE_NCB, 32, 836},
|
|
{"USBC0_DIEPTSIZ003" , 0x16F0010000970ull, CVMX_CSR_DB_TYPE_NCB, 32, 836},
|
|
{"USBC0_DIEPTSIZ004" , 0x16F0010000990ull, CVMX_CSR_DB_TYPE_NCB, 32, 836},
|
|
{"USBC1_DIEPTSIZ000" , 0x17F0010000910ull, CVMX_CSR_DB_TYPE_NCB, 32, 836},
|
|
{"USBC1_DIEPTSIZ001" , 0x17F0010000930ull, CVMX_CSR_DB_TYPE_NCB, 32, 836},
|
|
{"USBC1_DIEPTSIZ002" , 0x17F0010000950ull, CVMX_CSR_DB_TYPE_NCB, 32, 836},
|
|
{"USBC1_DIEPTSIZ003" , 0x17F0010000970ull, CVMX_CSR_DB_TYPE_NCB, 32, 836},
|
|
{"USBC1_DIEPTSIZ004" , 0x17F0010000990ull, CVMX_CSR_DB_TYPE_NCB, 32, 836},
|
|
{"USBC0_DOEPCTL000" , 0x16F0010000B00ull, CVMX_CSR_DB_TYPE_NCB, 32, 837},
|
|
{"USBC0_DOEPCTL001" , 0x16F0010000B20ull, CVMX_CSR_DB_TYPE_NCB, 32, 837},
|
|
{"USBC0_DOEPCTL002" , 0x16F0010000B40ull, CVMX_CSR_DB_TYPE_NCB, 32, 837},
|
|
{"USBC0_DOEPCTL003" , 0x16F0010000B60ull, CVMX_CSR_DB_TYPE_NCB, 32, 837},
|
|
{"USBC0_DOEPCTL004" , 0x16F0010000B80ull, CVMX_CSR_DB_TYPE_NCB, 32, 837},
|
|
{"USBC1_DOEPCTL000" , 0x17F0010000B00ull, CVMX_CSR_DB_TYPE_NCB, 32, 837},
|
|
{"USBC1_DOEPCTL001" , 0x17F0010000B20ull, CVMX_CSR_DB_TYPE_NCB, 32, 837},
|
|
{"USBC1_DOEPCTL002" , 0x17F0010000B40ull, CVMX_CSR_DB_TYPE_NCB, 32, 837},
|
|
{"USBC1_DOEPCTL003" , 0x17F0010000B60ull, CVMX_CSR_DB_TYPE_NCB, 32, 837},
|
|
{"USBC1_DOEPCTL004" , 0x17F0010000B80ull, CVMX_CSR_DB_TYPE_NCB, 32, 837},
|
|
{"USBC0_DOEPINT000" , 0x16F0010000B08ull, CVMX_CSR_DB_TYPE_NCB, 32, 838},
|
|
{"USBC0_DOEPINT001" , 0x16F0010000B28ull, CVMX_CSR_DB_TYPE_NCB, 32, 838},
|
|
{"USBC0_DOEPINT002" , 0x16F0010000B48ull, CVMX_CSR_DB_TYPE_NCB, 32, 838},
|
|
{"USBC0_DOEPINT003" , 0x16F0010000B68ull, CVMX_CSR_DB_TYPE_NCB, 32, 838},
|
|
{"USBC0_DOEPINT004" , 0x16F0010000B88ull, CVMX_CSR_DB_TYPE_NCB, 32, 838},
|
|
{"USBC1_DOEPINT000" , 0x17F0010000B08ull, CVMX_CSR_DB_TYPE_NCB, 32, 838},
|
|
{"USBC1_DOEPINT001" , 0x17F0010000B28ull, CVMX_CSR_DB_TYPE_NCB, 32, 838},
|
|
{"USBC1_DOEPINT002" , 0x17F0010000B48ull, CVMX_CSR_DB_TYPE_NCB, 32, 838},
|
|
{"USBC1_DOEPINT003" , 0x17F0010000B68ull, CVMX_CSR_DB_TYPE_NCB, 32, 838},
|
|
{"USBC1_DOEPINT004" , 0x17F0010000B88ull, CVMX_CSR_DB_TYPE_NCB, 32, 838},
|
|
{"USBC0_DOEPMSK" , 0x16F0010000814ull, CVMX_CSR_DB_TYPE_NCB, 32, 839},
|
|
{"USBC1_DOEPMSK" , 0x17F0010000814ull, CVMX_CSR_DB_TYPE_NCB, 32, 839},
|
|
{"USBC0_DOEPTSIZ000" , 0x16F0010000B10ull, CVMX_CSR_DB_TYPE_NCB, 32, 840},
|
|
{"USBC0_DOEPTSIZ001" , 0x16F0010000B30ull, CVMX_CSR_DB_TYPE_NCB, 32, 840},
|
|
{"USBC0_DOEPTSIZ002" , 0x16F0010000B50ull, CVMX_CSR_DB_TYPE_NCB, 32, 840},
|
|
{"USBC0_DOEPTSIZ003" , 0x16F0010000B70ull, CVMX_CSR_DB_TYPE_NCB, 32, 840},
|
|
{"USBC0_DOEPTSIZ004" , 0x16F0010000B90ull, CVMX_CSR_DB_TYPE_NCB, 32, 840},
|
|
{"USBC1_DOEPTSIZ000" , 0x17F0010000B10ull, CVMX_CSR_DB_TYPE_NCB, 32, 840},
|
|
{"USBC1_DOEPTSIZ001" , 0x17F0010000B30ull, CVMX_CSR_DB_TYPE_NCB, 32, 840},
|
|
{"USBC1_DOEPTSIZ002" , 0x17F0010000B50ull, CVMX_CSR_DB_TYPE_NCB, 32, 840},
|
|
{"USBC1_DOEPTSIZ003" , 0x17F0010000B70ull, CVMX_CSR_DB_TYPE_NCB, 32, 840},
|
|
{"USBC1_DOEPTSIZ004" , 0x17F0010000B90ull, CVMX_CSR_DB_TYPE_NCB, 32, 840},
|
|
{"USBC0_DPTXFSIZ001" , 0x16F0010000104ull, CVMX_CSR_DB_TYPE_NCB, 32, 841},
|
|
{"USBC0_DPTXFSIZ002" , 0x16F0010000108ull, CVMX_CSR_DB_TYPE_NCB, 32, 841},
|
|
{"USBC0_DPTXFSIZ003" , 0x16F001000010Cull, CVMX_CSR_DB_TYPE_NCB, 32, 841},
|
|
{"USBC0_DPTXFSIZ004" , 0x16F0010000110ull, CVMX_CSR_DB_TYPE_NCB, 32, 841},
|
|
{"USBC1_DPTXFSIZ001" , 0x17F0010000104ull, CVMX_CSR_DB_TYPE_NCB, 32, 841},
|
|
{"USBC1_DPTXFSIZ002" , 0x17F0010000108ull, CVMX_CSR_DB_TYPE_NCB, 32, 841},
|
|
{"USBC1_DPTXFSIZ003" , 0x17F001000010Cull, CVMX_CSR_DB_TYPE_NCB, 32, 841},
|
|
{"USBC1_DPTXFSIZ004" , 0x17F0010000110ull, CVMX_CSR_DB_TYPE_NCB, 32, 841},
|
|
{"USBC0_DSTS" , 0x16F0010000808ull, CVMX_CSR_DB_TYPE_NCB, 32, 842},
|
|
{"USBC1_DSTS" , 0x17F0010000808ull, CVMX_CSR_DB_TYPE_NCB, 32, 842},
|
|
{"USBC0_DTKNQR1" , 0x16F0010000820ull, CVMX_CSR_DB_TYPE_NCB, 32, 843},
|
|
{"USBC1_DTKNQR1" , 0x17F0010000820ull, CVMX_CSR_DB_TYPE_NCB, 32, 843},
|
|
{"USBC0_DTKNQR2" , 0x16F0010000824ull, CVMX_CSR_DB_TYPE_NCB, 32, 844},
|
|
{"USBC1_DTKNQR2" , 0x17F0010000824ull, CVMX_CSR_DB_TYPE_NCB, 32, 844},
|
|
{"USBC0_DTKNQR3" , 0x16F0010000830ull, CVMX_CSR_DB_TYPE_NCB, 32, 845},
|
|
{"USBC1_DTKNQR3" , 0x17F0010000830ull, CVMX_CSR_DB_TYPE_NCB, 32, 845},
|
|
{"USBC0_DTKNQR4" , 0x16F0010000834ull, CVMX_CSR_DB_TYPE_NCB, 32, 846},
|
|
{"USBC1_DTKNQR4" , 0x17F0010000834ull, CVMX_CSR_DB_TYPE_NCB, 32, 846},
|
|
{"USBC0_GAHBCFG" , 0x16F0010000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 847},
|
|
{"USBC1_GAHBCFG" , 0x17F0010000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 847},
|
|
{"USBC0_GHWCFG1" , 0x16F0010000044ull, CVMX_CSR_DB_TYPE_NCB, 32, 848},
|
|
{"USBC1_GHWCFG1" , 0x17F0010000044ull, CVMX_CSR_DB_TYPE_NCB, 32, 848},
|
|
{"USBC0_GHWCFG2" , 0x16F0010000048ull, CVMX_CSR_DB_TYPE_NCB, 32, 849},
|
|
{"USBC1_GHWCFG2" , 0x17F0010000048ull, CVMX_CSR_DB_TYPE_NCB, 32, 849},
|
|
{"USBC0_GHWCFG3" , 0x16F001000004Cull, CVMX_CSR_DB_TYPE_NCB, 32, 850},
|
|
{"USBC1_GHWCFG3" , 0x17F001000004Cull, CVMX_CSR_DB_TYPE_NCB, 32, 850},
|
|
{"USBC0_GHWCFG4" , 0x16F0010000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 851},
|
|
{"USBC1_GHWCFG4" , 0x17F0010000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 851},
|
|
{"USBC0_GINTMSK" , 0x16F0010000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 852},
|
|
{"USBC1_GINTMSK" , 0x17F0010000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 852},
|
|
{"USBC0_GINTSTS" , 0x16F0010000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 853},
|
|
{"USBC1_GINTSTS" , 0x17F0010000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 853},
|
|
{"USBC0_GNPTXFSIZ" , 0x16F0010000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 854},
|
|
{"USBC1_GNPTXFSIZ" , 0x17F0010000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 854},
|
|
{"USBC0_GNPTXSTS" , 0x16F001000002Cull, CVMX_CSR_DB_TYPE_NCB, 32, 855},
|
|
{"USBC1_GNPTXSTS" , 0x17F001000002Cull, CVMX_CSR_DB_TYPE_NCB, 32, 855},
|
|
{"USBC0_GOTGCTL" , 0x16F0010000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 856},
|
|
{"USBC1_GOTGCTL" , 0x17F0010000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 856},
|
|
{"USBC0_GOTGINT" , 0x16F0010000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 857},
|
|
{"USBC1_GOTGINT" , 0x17F0010000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 857},
|
|
{"USBC0_GRSTCTL" , 0x16F0010000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 858},
|
|
{"USBC1_GRSTCTL" , 0x17F0010000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 858},
|
|
{"USBC0_GRXFSIZ" , 0x16F0010000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 859},
|
|
{"USBC1_GRXFSIZ" , 0x17F0010000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 859},
|
|
{"USBC0_GRXSTSPD" , 0x16F0010040020ull, CVMX_CSR_DB_TYPE_NCB, 32, 860},
|
|
{"USBC1_GRXSTSPD" , 0x17F0010040020ull, CVMX_CSR_DB_TYPE_NCB, 32, 860},
|
|
{"USBC0_GRXSTSPH" , 0x16F0010000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 861},
|
|
{"USBC1_GRXSTSPH" , 0x17F0010000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 861},
|
|
{"USBC0_GRXSTSRD" , 0x16F001004001Cull, CVMX_CSR_DB_TYPE_NCB, 32, 862},
|
|
{"USBC1_GRXSTSRD" , 0x17F001004001Cull, CVMX_CSR_DB_TYPE_NCB, 32, 862},
|
|
{"USBC0_GRXSTSRH" , 0x16F001000001Cull, CVMX_CSR_DB_TYPE_NCB, 32, 863},
|
|
{"USBC1_GRXSTSRH" , 0x17F001000001Cull, CVMX_CSR_DB_TYPE_NCB, 32, 863},
|
|
{"USBC0_GSNPSID" , 0x16F0010000040ull, CVMX_CSR_DB_TYPE_NCB, 32, 864},
|
|
{"USBC1_GSNPSID" , 0x17F0010000040ull, CVMX_CSR_DB_TYPE_NCB, 32, 864},
|
|
{"USBC0_GUSBCFG" , 0x16F001000000Cull, CVMX_CSR_DB_TYPE_NCB, 32, 865},
|
|
{"USBC1_GUSBCFG" , 0x17F001000000Cull, CVMX_CSR_DB_TYPE_NCB, 32, 865},
|
|
{"USBC0_HAINT" , 0x16F0010000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 866},
|
|
{"USBC1_HAINT" , 0x17F0010000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 866},
|
|
{"USBC0_HAINTMSK" , 0x16F0010000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 867},
|
|
{"USBC1_HAINTMSK" , 0x17F0010000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 867},
|
|
{"USBC0_HCCHAR000" , 0x16F0010000500ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
|
|
{"USBC0_HCCHAR001" , 0x16F0010000520ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
|
|
{"USBC0_HCCHAR002" , 0x16F0010000540ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
|
|
{"USBC0_HCCHAR003" , 0x16F0010000560ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
|
|
{"USBC0_HCCHAR004" , 0x16F0010000580ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
|
|
{"USBC0_HCCHAR005" , 0x16F00100005A0ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
|
|
{"USBC0_HCCHAR006" , 0x16F00100005C0ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
|
|
{"USBC0_HCCHAR007" , 0x16F00100005E0ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
|
|
{"USBC1_HCCHAR000" , 0x17F0010000500ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
|
|
{"USBC1_HCCHAR001" , 0x17F0010000520ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
|
|
{"USBC1_HCCHAR002" , 0x17F0010000540ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
|
|
{"USBC1_HCCHAR003" , 0x17F0010000560ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
|
|
{"USBC1_HCCHAR004" , 0x17F0010000580ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
|
|
{"USBC1_HCCHAR005" , 0x17F00100005A0ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
|
|
{"USBC1_HCCHAR006" , 0x17F00100005C0ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
|
|
{"USBC1_HCCHAR007" , 0x17F00100005E0ull, CVMX_CSR_DB_TYPE_NCB, 32, 868},
|
|
{"USBC0_HCFG" , 0x16F0010000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 869},
|
|
{"USBC1_HCFG" , 0x17F0010000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 869},
|
|
{"USBC0_HCINT000" , 0x16F0010000508ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
|
|
{"USBC0_HCINT001" , 0x16F0010000528ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
|
|
{"USBC0_HCINT002" , 0x16F0010000548ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
|
|
{"USBC0_HCINT003" , 0x16F0010000568ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
|
|
{"USBC0_HCINT004" , 0x16F0010000588ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
|
|
{"USBC0_HCINT005" , 0x16F00100005A8ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
|
|
{"USBC0_HCINT006" , 0x16F00100005C8ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
|
|
{"USBC0_HCINT007" , 0x16F00100005E8ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
|
|
{"USBC1_HCINT000" , 0x17F0010000508ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
|
|
{"USBC1_HCINT001" , 0x17F0010000528ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
|
|
{"USBC1_HCINT002" , 0x17F0010000548ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
|
|
{"USBC1_HCINT003" , 0x17F0010000568ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
|
|
{"USBC1_HCINT004" , 0x17F0010000588ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
|
|
{"USBC1_HCINT005" , 0x17F00100005A8ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
|
|
{"USBC1_HCINT006" , 0x17F00100005C8ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
|
|
{"USBC1_HCINT007" , 0x17F00100005E8ull, CVMX_CSR_DB_TYPE_NCB, 32, 870},
|
|
{"USBC0_HCINTMSK000" , 0x16F001000050Cull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
|
|
{"USBC0_HCINTMSK001" , 0x16F001000052Cull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
|
|
{"USBC0_HCINTMSK002" , 0x16F001000054Cull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
|
|
{"USBC0_HCINTMSK003" , 0x16F001000056Cull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
|
|
{"USBC0_HCINTMSK004" , 0x16F001000058Cull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
|
|
{"USBC0_HCINTMSK005" , 0x16F00100005ACull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
|
|
{"USBC0_HCINTMSK006" , 0x16F00100005CCull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
|
|
{"USBC0_HCINTMSK007" , 0x16F00100005ECull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
|
|
{"USBC1_HCINTMSK000" , 0x17F001000050Cull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
|
|
{"USBC1_HCINTMSK001" , 0x17F001000052Cull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
|
|
{"USBC1_HCINTMSK002" , 0x17F001000054Cull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
|
|
{"USBC1_HCINTMSK003" , 0x17F001000056Cull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
|
|
{"USBC1_HCINTMSK004" , 0x17F001000058Cull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
|
|
{"USBC1_HCINTMSK005" , 0x17F00100005ACull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
|
|
{"USBC1_HCINTMSK006" , 0x17F00100005CCull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
|
|
{"USBC1_HCINTMSK007" , 0x17F00100005ECull, CVMX_CSR_DB_TYPE_NCB, 32, 871},
|
|
{"USBC0_HCSPLT000" , 0x16F0010000504ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
|
|
{"USBC0_HCSPLT001" , 0x16F0010000524ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
|
|
{"USBC0_HCSPLT002" , 0x16F0010000544ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
|
|
{"USBC0_HCSPLT003" , 0x16F0010000564ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
|
|
{"USBC0_HCSPLT004" , 0x16F0010000584ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
|
|
{"USBC0_HCSPLT005" , 0x16F00100005A4ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
|
|
{"USBC0_HCSPLT006" , 0x16F00100005C4ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
|
|
{"USBC0_HCSPLT007" , 0x16F00100005E4ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
|
|
{"USBC1_HCSPLT000" , 0x17F0010000504ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
|
|
{"USBC1_HCSPLT001" , 0x17F0010000524ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
|
|
{"USBC1_HCSPLT002" , 0x17F0010000544ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
|
|
{"USBC1_HCSPLT003" , 0x17F0010000564ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
|
|
{"USBC1_HCSPLT004" , 0x17F0010000584ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
|
|
{"USBC1_HCSPLT005" , 0x17F00100005A4ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
|
|
{"USBC1_HCSPLT006" , 0x17F00100005C4ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
|
|
{"USBC1_HCSPLT007" , 0x17F00100005E4ull, CVMX_CSR_DB_TYPE_NCB, 32, 872},
|
|
{"USBC0_HCTSIZ000" , 0x16F0010000510ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
|
|
{"USBC0_HCTSIZ001" , 0x16F0010000530ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
|
|
{"USBC0_HCTSIZ002" , 0x16F0010000550ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
|
|
{"USBC0_HCTSIZ003" , 0x16F0010000570ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
|
|
{"USBC0_HCTSIZ004" , 0x16F0010000590ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
|
|
{"USBC0_HCTSIZ005" , 0x16F00100005B0ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
|
|
{"USBC0_HCTSIZ006" , 0x16F00100005D0ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
|
|
{"USBC0_HCTSIZ007" , 0x16F00100005F0ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
|
|
{"USBC1_HCTSIZ000" , 0x17F0010000510ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
|
|
{"USBC1_HCTSIZ001" , 0x17F0010000530ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
|
|
{"USBC1_HCTSIZ002" , 0x17F0010000550ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
|
|
{"USBC1_HCTSIZ003" , 0x17F0010000570ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
|
|
{"USBC1_HCTSIZ004" , 0x17F0010000590ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
|
|
{"USBC1_HCTSIZ005" , 0x17F00100005B0ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
|
|
{"USBC1_HCTSIZ006" , 0x17F00100005D0ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
|
|
{"USBC1_HCTSIZ007" , 0x17F00100005F0ull, CVMX_CSR_DB_TYPE_NCB, 32, 873},
|
|
{"USBC0_HFIR" , 0x16F0010000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 874},
|
|
{"USBC1_HFIR" , 0x17F0010000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 874},
|
|
{"USBC0_HFNUM" , 0x16F0010000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 875},
|
|
{"USBC1_HFNUM" , 0x17F0010000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 875},
|
|
{"USBC0_HPRT" , 0x16F0010000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 876},
|
|
{"USBC1_HPRT" , 0x17F0010000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 876},
|
|
{"USBC0_HPTXFSIZ" , 0x16F0010000100ull, CVMX_CSR_DB_TYPE_NCB, 32, 877},
|
|
{"USBC1_HPTXFSIZ" , 0x17F0010000100ull, CVMX_CSR_DB_TYPE_NCB, 32, 877},
|
|
{"USBC0_HPTXSTS" , 0x16F0010000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 878},
|
|
{"USBC1_HPTXSTS" , 0x17F0010000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 878},
|
|
{"USBC0_NPTXDFIFO000" , 0x16F0010001000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
|
|
{"USBC0_NPTXDFIFO001" , 0x16F0010002000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
|
|
{"USBC0_NPTXDFIFO002" , 0x16F0010003000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
|
|
{"USBC0_NPTXDFIFO003" , 0x16F0010004000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
|
|
{"USBC0_NPTXDFIFO004" , 0x16F0010005000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
|
|
{"USBC0_NPTXDFIFO005" , 0x16F0010006000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
|
|
{"USBC0_NPTXDFIFO006" , 0x16F0010007000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
|
|
{"USBC0_NPTXDFIFO007" , 0x16F0010008000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
|
|
{"USBC1_NPTXDFIFO000" , 0x17F0010001000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
|
|
{"USBC1_NPTXDFIFO001" , 0x17F0010002000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
|
|
{"USBC1_NPTXDFIFO002" , 0x17F0010003000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
|
|
{"USBC1_NPTXDFIFO003" , 0x17F0010004000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
|
|
{"USBC1_NPTXDFIFO004" , 0x17F0010005000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
|
|
{"USBC1_NPTXDFIFO005" , 0x17F0010006000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
|
|
{"USBC1_NPTXDFIFO006" , 0x17F0010007000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
|
|
{"USBC1_NPTXDFIFO007" , 0x17F0010008000ull, CVMX_CSR_DB_TYPE_NCB, 32, 879},
|
|
{"USBC0_PCGCCTL" , 0x16F0010000E00ull, CVMX_CSR_DB_TYPE_NCB, 32, 880},
|
|
{"USBC1_PCGCCTL" , 0x17F0010000E00ull, CVMX_CSR_DB_TYPE_NCB, 32, 880},
|
|
{"USBN0_BIST_STATUS" , 0x11800680007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 881},
|
|
{"USBN1_BIST_STATUS" , 0x11800780007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 881},
|
|
{"USBN0_CLK_CTL" , 0x1180068000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 882},
|
|
{"USBN1_CLK_CTL" , 0x1180078000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 882},
|
|
{"USBN0_CTL_STATUS" , 0x16F0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 883},
|
|
{"USBN1_CTL_STATUS" , 0x17F0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 883},
|
|
{"USBN0_DMA0_INB_CHN0" , 0x16F0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 884},
|
|
{"USBN1_DMA0_INB_CHN0" , 0x17F0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 884},
|
|
{"USBN0_DMA0_INB_CHN1" , 0x16F0000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 885},
|
|
{"USBN1_DMA0_INB_CHN1" , 0x17F0000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 885},
|
|
{"USBN0_DMA0_INB_CHN2" , 0x16F0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 886},
|
|
{"USBN1_DMA0_INB_CHN2" , 0x17F0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 886},
|
|
{"USBN0_DMA0_INB_CHN3" , 0x16F0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 887},
|
|
{"USBN1_DMA0_INB_CHN3" , 0x17F0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 887},
|
|
{"USBN0_DMA0_INB_CHN4" , 0x16F0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 888},
|
|
{"USBN1_DMA0_INB_CHN4" , 0x17F0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 888},
|
|
{"USBN0_DMA0_INB_CHN5" , 0x16F0000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 889},
|
|
{"USBN1_DMA0_INB_CHN5" , 0x17F0000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 889},
|
|
{"USBN0_DMA0_INB_CHN6" , 0x16F0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 890},
|
|
{"USBN1_DMA0_INB_CHN6" , 0x17F0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 890},
|
|
{"USBN0_DMA0_INB_CHN7" , 0x16F0000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 891},
|
|
{"USBN1_DMA0_INB_CHN7" , 0x17F0000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 891},
|
|
{"USBN0_DMA0_OUTB_CHN0" , 0x16F0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 892},
|
|
{"USBN1_DMA0_OUTB_CHN0" , 0x17F0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 892},
|
|
{"USBN0_DMA0_OUTB_CHN1" , 0x16F0000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 893},
|
|
{"USBN1_DMA0_OUTB_CHN1" , 0x17F0000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 893},
|
|
{"USBN0_DMA0_OUTB_CHN2" , 0x16F0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 894},
|
|
{"USBN1_DMA0_OUTB_CHN2" , 0x17F0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 894},
|
|
{"USBN0_DMA0_OUTB_CHN3" , 0x16F0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 895},
|
|
{"USBN1_DMA0_OUTB_CHN3" , 0x17F0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 895},
|
|
{"USBN0_DMA0_OUTB_CHN4" , 0x16F0000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 896},
|
|
{"USBN1_DMA0_OUTB_CHN4" , 0x17F0000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 896},
|
|
{"USBN0_DMA0_OUTB_CHN5" , 0x16F0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 897},
|
|
{"USBN1_DMA0_OUTB_CHN5" , 0x17F0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 897},
|
|
{"USBN0_DMA0_OUTB_CHN6" , 0x16F0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 898},
|
|
{"USBN1_DMA0_OUTB_CHN6" , 0x17F0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 898},
|
|
{"USBN0_DMA0_OUTB_CHN7" , 0x16F0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 899},
|
|
{"USBN1_DMA0_OUTB_CHN7" , 0x17F0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 899},
|
|
{"USBN0_DMA_TEST" , 0x16F0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 900},
|
|
{"USBN1_DMA_TEST" , 0x17F0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 900},
|
|
{"USBN0_INT_ENB" , 0x1180068000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 901},
|
|
{"USBN1_INT_ENB" , 0x1180078000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 901},
|
|
{"USBN0_INT_SUM" , 0x1180068000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 902},
|
|
{"USBN1_INT_SUM" , 0x1180078000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 902},
|
|
{"USBN0_USBP_CTL_STATUS" , 0x1180068000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 903},
|
|
{"USBN1_USBP_CTL_STATUS" , 0x1180078000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 903},
|
|
{NULL,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
|
|
/* name , bit, width, csr, type, rst un, typ un, reset, typical */
|
|
{"RESERVED_0_1" , 0, 2, 0, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OUT_OVR" , 2, 2, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_21" , 4, 18, 0, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LOSTSTAT" , 22, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_25" , 23, 3, 0, "RAZ", 1, 1, 0, 0},
|
|
{"STATOVR" , 26, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_31" , 27, 5, 0, "RAZ", 1, 1, 0, 0},
|
|
{"OVRFLW" , 32, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXPOP" , 33, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXPSH" , 34, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OVRFLW1" , 35, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXPOP1" , 36, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXPSH1" , 37, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 0, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 10, 1, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 1, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 5, 2, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 2, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL" , 8, 5, 2, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_13_15" , 13, 3, 2, "RAZ", 1, 1, 0, 0},
|
|
{"BYP_EN" , 16, 1, 2, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 2, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL1" , 32, 5, 2, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_37_39" , 37, 3, 2, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL1" , 40, 5, 2, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_45_47" , 45, 3, 2, "RAZ", 1, 1, 0, 0},
|
|
{"BYP_EN1" , 48, 1, 2, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 2, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 3, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 1, 1, 3, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 3, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 4, "R/W", 0, 1, 0ull, 0},
|
|
{"SPEED" , 1, 1, 4, "RO", 0, 0, 0ull, 0ull},
|
|
{"DUPLEX" , 2, 1, 4, "R/W", 0, 1, 1ull, 0},
|
|
{"SLOTTIME" , 3, 1, 4, "RO", 0, 0, 0ull, 0ull},
|
|
{"RX_EN" , 4, 1, 4, "R/W", 0, 1, 0ull, 0},
|
|
{"TX_EN" , 5, 1, 4, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 4, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 64, 5, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 6, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 7, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 8, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 9, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 10, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 0, 8, 11, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 11, "RAZ", 1, 1, 0, 0},
|
|
{"BCST" , 0, 1, 12, "R/W", 0, 1, 1ull, 0},
|
|
{"MCST" , 1, 2, 12, "R/W", 0, 1, 0ull, 0},
|
|
{"CAM_MODE" , 3, 1, 12, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 12, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 5, 13, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_5_63" , 5, 59, 13, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_1" , 1, 1, 14, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 2, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"JABBER" , 3, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCSERR" , 4, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"ALNERR" , 5, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"LENERR" , 6, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RCVERR" , 7, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SKPERR" , 8, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_9_63" , 9, 55, 14, "RAZ", 1, 1, 0, 0},
|
|
{"PRE_CHK" , 0, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PRE_STRP" , 1, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_DRP" , 2, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_BCK" , 3, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_MCST" , 4, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_SMAC" , 5, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRE_FREE" , 6, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"VLAN_LEN" , 7, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PAD_LEN" , 8, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRE_ALIGN" , 9, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_10_63" , 10, 54, 15, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 16, 16, "R/W", 0, 0, 1536ull, 1536ull},
|
|
{"RESERVED_16_63" , 16, 48, 16, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 16, 17, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_16_63" , 16, 48, 17, "RAZ", 1, 1, 0, 0},
|
|
{"IFG" , 0, 4, 18, "R/W", 0, 0, 12ull, 12ull},
|
|
{"RESERVED_4_63" , 4, 60, 18, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 19, "RAZ", 1, 1, 0, 0},
|
|
{"MAXERR" , 2, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"JABBER" , 3, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ALNERR" , 5, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 6, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RCVERR" , 7, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 19, "RAZ", 1, 1, 0, 0},
|
|
{"OVRERR" , 10, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_18" , 16, 3, 19, "RAZ", 1, 1, 0, 0},
|
|
{"PAUSE_DRP" , 19, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 19, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 20, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 2, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"JABBER" , 3, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ALNERR" , 5, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 6, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RCVERR" , 7, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 20, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OVRERR" , 10, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_18" , 16, 3, 20, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PAUSE_DRP" , 19, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 20, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 21, "R/W", 0, 0, 10240ull, 10240ull},
|
|
{"RESERVED_16_63" , 16, 48, 21, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 16, 22, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 22, "RAZ", 1, 1, 0, 0},
|
|
{"RD_CLR" , 0, 1, 23, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 23, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 24, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 24, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 25, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 25, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 26, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 26, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 27, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 27, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 28, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 28, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 29, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 29, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 30, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 30, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 31, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 31, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 32, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 32, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 7, 33, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 33, "RAZ", 1, 1, 0, 0},
|
|
{"FCSSEL" , 8, 1, 33, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 33, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 34, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_6_63" , 6, 58, 34, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 35, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_6_63" , 6, 58, 35, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 9, 36, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_9_63" , 9, 55, 36, "RAZ", 1, 1, 0, 0},
|
|
{"COMMIT" , 0, 2, 37, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_15" , 2, 14, 37, "RAZ", 1, 1, 0, 0},
|
|
{"DROP" , 16, 2, 37, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 37, "RAZ", 1, 1, 0, 0},
|
|
{"RX" , 0, 2, 38, "RC", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_3" , 2, 2, 38, "RAZ", 1, 1, 0, 0},
|
|
{"TX" , 4, 2, 38, "RC", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 38, "RAZ", 1, 1, 0, 0},
|
|
{"SMAC" , 0, 48, 39, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 39, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 40, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP" , 16, 1, 40, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 40, "RAZ", 1, 1, 0, 0},
|
|
{"PREAMBLE" , 0, 1, 41, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PAD" , 1, 1, 41, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCS" , 2, 1, 41, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FORCE_FCS" , 3, 1, 41, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 41, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL_EN" , 0, 1, 42, "R/W", 0, 0, 1ull, 1ull},
|
|
{"XSDEF_EN" , 1, 1, 42, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 42, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_SIZE" , 0, 8, 43, "R/W", 0, 0, 59ull, 59ull},
|
|
{"RESERVED_8_63" , 8, 56, 43, "RAZ", 1, 1, 0, 0},
|
|
{"INTERVAL" , 0, 16, 44, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 44, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 45, "R/W", 0, 1, 96ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 45, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 46, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_16_63" , 16, 48, 46, "RAZ", 1, 1, 0, 0},
|
|
{"SEND" , 0, 1, 47, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 47, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 48, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 48, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL" , 0, 32, 49, "RC/W", 0, 1, 0ull, 0},
|
|
{"XSDEF" , 32, 32, 49, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCOL" , 0, 32, 50, "RC/W", 0, 1, 0ull, 0},
|
|
{"SCOL" , 32, 32, 50, "RC/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 51, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 51, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 52, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 52, "RAZ", 1, 1, 0, 0},
|
|
{"HIST0" , 0, 32, 53, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST1" , 32, 32, 53, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST2" , 0, 32, 54, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST3" , 32, 32, 54, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST4" , 0, 32, 55, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST5" , 32, 32, 55, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST6" , 0, 32, 56, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST7" , 32, 32, 56, "RC/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 0, 32, 57, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 32, 32, 57, "RC/W", 0, 1, 0ull, 0},
|
|
{"CTL" , 0, 32, 58, "RC/W", 0, 1, 0ull, 0},
|
|
{"UNDFLW" , 32, 32, 58, "RC/W", 0, 1, 0ull, 0},
|
|
{"RD_CLR" , 0, 1, 59, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 59, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 6, 60, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_6_63" , 6, 58, 60, "RAZ", 1, 1, 0, 0},
|
|
{"BP" , 0, 2, 61, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 61, "RAZ", 1, 1, 0, 0},
|
|
{"LIMIT" , 0, 5, 62, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_5_63" , 5, 59, 62, "RAZ", 1, 1, 0, 0},
|
|
{"IFG1" , 0, 4, 63, "R/W", 0, 1, 8ull, 0},
|
|
{"IFG2" , 4, 4, 63, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 63, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 64, "RAZ", 1, 1, 0, 0},
|
|
{"UNDFLW" , 2, 2, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 64, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL" , 8, 2, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_11" , 10, 2, 64, "RAZ", 1, 1, 0, 0},
|
|
{"XSDEF" , 12, 2, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_15" , 14, 2, 64, "RAZ", 1, 1, 0, 0},
|
|
{"LATE_COL" , 16, 2, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 64, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 65, "RAZ", 1, 1, 0, 0},
|
|
{"UNDFLW" , 2, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 65, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL" , 8, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_11" , 10, 2, 65, "RAZ", 1, 1, 0, 0},
|
|
{"XSDEF" , 12, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_15" , 14, 2, 65, "RAZ", 1, 1, 0, 0},
|
|
{"LATE_COL" , 16, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 65, "RAZ", 1, 1, 0, 0},
|
|
{"JAM" , 0, 8, 66, "R/W", 0, 1, 238ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 66, "RAZ", 1, 1, 0, 0},
|
|
{"LFSR" , 0, 16, 67, "R/W", 0, 1, 65535ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 67, "RAZ", 1, 1, 0, 0},
|
|
{"IGN_FULL" , 0, 2, 68, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_3" , 2, 2, 68, "RAZ", 1, 1, 0, 0},
|
|
{"BP" , 4, 2, 68, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 68, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 8, 2, 68, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 68, "RAZ", 1, 1, 0, 0},
|
|
{"DMAC" , 0, 48, 69, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
|
|
{"RESERVED_48_63" , 48, 16, 69, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 70, "R/W", 0, 0, 34824ull, 34824ull},
|
|
{"RESERVED_16_63" , 16, 48, 70, "RAZ", 1, 1, 0, 0},
|
|
{"BIST" , 0, 3, 71, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 71, "RAZ", 1, 1, 0, 0},
|
|
{"DINT" , 0, 4, 72, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 72, "RAZ", 1, 1, 0, 0},
|
|
{"FUSE" , 0, 4, 73, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_4_63" , 4, 60, 73, "RAZ", 1, 1, 0, 0},
|
|
{"GSTOP" , 0, 1, 74, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 74, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 75, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_49" , 49, 1, 75, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_51_51" , 51, 1, 75, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_57_58" , 57, 2, 75, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TWSI2" , 59, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POWIQ" , 60, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPDPPTHR" , 61, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MII" , 62, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BOOTDMA" , 63, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WDOG" , 0, 4, 76, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_15" , 4, 12, 76, "RAZ", 1, 1, 0, 0},
|
|
{"UART2" , 16, 1, 76, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USB1" , 17, 1, 76, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MII1" , 18, 1, 76, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 76, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 77, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_49" , 49, 1, 77, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_51_51" , 51, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_57_58" , 57, 2, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWSI2" , 59, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POWIQ" , 60, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPDPPTHR" , 61, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MII" , 62, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BOOTDMA" , 63, 1, 77, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WDOG" , 0, 4, 78, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_15" , 4, 12, 78, "RAZ", 1, 1, 0, 0},
|
|
{"UART2" , 16, 1, 78, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USB1" , 17, 1, 78, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MII1" , 18, 1, 78, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 78, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"WDOG_SUM" , 44, 1, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"TWSI" , 45, 1, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 1, 79, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_49" , 49, 1, 79, "RAZ", 1, 1, 0, 0},
|
|
{"IPD_DRP" , 50, 1, 79, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_51_51" , 51, 1, 79, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 79, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_57_58" , 57, 2, 79, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TWSI2" , 59, 1, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"POWIQ" , 60, 1, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPDPPTHR" , 61, 1, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"MII" , 62, 1, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"BOOTDMA" , 63, 1, 79, "RO", 0, 0, 0ull, 0ull},
|
|
{"WORKQ" , 0, 16, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"WDOG_SUM" , 44, 1, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"TWSI" , 45, 1, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 1, 80, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_49" , 49, 1, 80, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 80, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_51_51" , 51, 1, 80, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 80, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_57_58" , 57, 2, 80, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TWSI2" , 59, 1, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"POWIQ" , 60, 1, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPDPPTHR" , 61, 1, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"MII" , 62, 1, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"BOOTDMA" , 63, 1, 80, "RO", 0, 0, 0ull, 0ull},
|
|
{"WDOG" , 0, 4, 81, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_15" , 4, 12, 81, "RAZ", 1, 1, 0, 0},
|
|
{"UART2" , 16, 1, 81, "RO", 0, 0, 0ull, 0ull},
|
|
{"USB1" , 17, 1, 81, "RO", 0, 0, 0ull, 0ull},
|
|
{"MII1" , 18, 1, 81, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 81, "RAZ", 1, 1, 0, 0},
|
|
{"BITS" , 0, 32, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 82, "RAZ", 1, 1, 0, 0},
|
|
{"BITS" , 0, 32, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 83, "RAZ", 1, 1, 0, 0},
|
|
{"NMI" , 0, 4, 84, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 84, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 0, 2, 85, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 85, "RAZ", 1, 1, 0, 0},
|
|
{"PPDBG" , 0, 4, 86, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 86, "RAZ", 1, 1, 0, 0},
|
|
{"POKE" , 0, 64, 87, "RAZ", 1, 1, 0, 0},
|
|
{"RST0" , 0, 1, 88, "R/W", 1, 1, 0, 0},
|
|
{"RST" , 1, 3, 88, "R/W", 0, 0, 32767ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 88, "RAZ", 1, 1, 0, 0},
|
|
{"QLM_DCOK" , 0, 2, 89, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 89, "RAZ", 1, 1, 0, 0},
|
|
{"BYPASS" , 0, 2, 90, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_3" , 2, 2, 90, "RAZ", 1, 1, 0, 0},
|
|
{"MUX_SEL" , 4, 1, 90, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 90, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_DIV" , 8, 3, 90, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_11_63" , 11, 53, 90, "RAZ", 1, 1, 0, 0},
|
|
{"SHFT_REG" , 0, 32, 91, "R/W", 0, 1, 0ull, 0},
|
|
{"SHFT_CNT" , 32, 5, 91, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_37_39" , 37, 3, 91, "RAZ", 1, 1, 0, 0},
|
|
{"SELECT" , 40, 2, 91, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_42_60" , 42, 19, 91, "RAZ", 1, 1, 0, 0},
|
|
{"UPDATE" , 61, 1, 91, "R/W", 0, 1, 0ull, 0},
|
|
{"SHIFT" , 62, 1, 91, "R/W", 0, 1, 0ull, 0},
|
|
{"CAPTURE" , 63, 1, 91, "R/W", 0, 1, 0ull, 0},
|
|
{"SOFT_BIST" , 0, 1, 92, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 92, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_PRST" , 0, 1, 93, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 93, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_PRST" , 0, 1, 94, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 94, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_RST" , 0, 1, 95, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 95, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 36, 96, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ONE_SHOT" , 36, 1, 96, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 96, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 0, 2, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STATE" , 2, 2, 97, "RO", 0, 0, 0ull, 0ull},
|
|
{"LEN" , 4, 16, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 20, 24, 97, "RO", 0, 0, 0ull, 0ull},
|
|
{"DSTOP" , 44, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GSTOPEN" , 45, 1, 97, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_46_63" , 46, 18, 97, "RAZ", 1, 1, 0, 0},
|
|
{"FDR" , 0, 1, 98, "RO", 0, 0, 0ull, 0ull},
|
|
{"FFR" , 1, 1, 98, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPF1" , 2, 1, 98, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPF0" , 3, 1, 98, "RO", 0, 0, 0ull, 0ull},
|
|
{"FRD" , 4, 1, 98, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 98, "RAZ", 1, 1, 0, 0},
|
|
{"MEM0_ERR" , 0, 7, 99, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM1_ERR" , 7, 7, 99, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 14, 1, 99, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USE_STT" , 15, 1, 99, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USE_LDT" , 16, 1, 99, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 17, 1, 99, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 99, "RAZ", 1, 1, 0, 0},
|
|
{"FED0_SBE" , 0, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED0_DBE" , 1, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED1_SBE" , 2, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED1_DBE" , 3, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_UND" , 4, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_COFF" , 5, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_PERR" , 6, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_UND" , 7, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_COFF" , 8, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_PERR" , 9, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_UND" , 10, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_COFF" , 11, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_PERR" , 12, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_UND" , 13, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_COFF" , 14, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_PERR" , 15, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_UND" , 16, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_COFF" , 17, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_PERR" , 18, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_UND" , 19, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_COFF" , 20, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_PERR" , 21, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_UND" , 22, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_COFF" , 23, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_PERR" , 24, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_UND" , 25, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_COFF" , 26, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_PERR" , 27, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 100, "RAZ", 1, 1, 0, 0},
|
|
{"FED0_SBE" , 0, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED0_DBE" , 1, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED1_SBE" , 2, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED1_DBE" , 3, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_UND" , 4, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_COFF" , 5, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_PERR" , 6, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_UND" , 7, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_COFF" , 8, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_PERR" , 9, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_UND" , 10, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_COFF" , 11, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_PERR" , 12, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_UND" , 13, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_COFF" , 14, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_PERR" , 15, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_UND" , 16, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_COFF" , 17, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_PERR" , 18, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_UND" , 19, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_COFF" , 20, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_PERR" , 21, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_UND" , 22, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_COFF" , 23, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_PERR" , 24, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_UND" , 25, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_COFF" , 26, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_PERR" , 27, 1, 101, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 101, "RAZ", 1, 1, 0, 0},
|
|
{"QUE_SIZ" , 0, 29, 102, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 102, "RAZ", 1, 1, 0, 0},
|
|
{"PG_NUM" , 0, 25, 103, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 103, "RAZ", 1, 1, 0, 0},
|
|
{"ACT_INDX" , 0, 26, 104, "RO", 0, 1, 0ull, 0},
|
|
{"ACT_QUE" , 26, 3, 104, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 104, "RAZ", 0, 0, 0ull, 7ull},
|
|
{"EXP_INDX" , 0, 26, 105, "RO", 0, 1, 0ull, 0},
|
|
{"EXP_QUE" , 26, 3, 105, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 105, "RAZ", 0, 0, 0ull, 7ull},
|
|
{"CTL" , 0, 16, 106, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 106, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 32, 107, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 107, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 108, "RAZ", 1, 1, 0, 0},
|
|
{"OUT_OVR" , 2, 4, 108, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_21" , 6, 16, 108, "RAZ", 1, 1, 0, 0},
|
|
{"LOSTSTAT" , 22, 4, 108, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"STATOVR" , 26, 1, 108, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INB_NXA" , 27, 4, 108, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 108, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 16, 109, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 109, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_EN" , 0, 1, 110, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 110, "RAZ", 1, 1, 0, 0},
|
|
{"LOGL_EN" , 0, 16, 111, "R/W", 0, 1, 65535ull, 0},
|
|
{"PHYS_EN" , 16, 1, 111, "R/W", 0, 1, 1ull, 0},
|
|
{"HG2RX_EN" , 17, 1, 111, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HG2TX_EN" , 18, 1, 111, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 111, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 1, 112, "RO", 0, 1, 0ull, 0},
|
|
{"EN" , 1, 1, 112, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_3" , 2, 2, 112, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 4, 2, 112, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_7" , 6, 2, 112, "RAZ", 1, 1, 0, 0},
|
|
{"SPEED" , 8, 2, 112, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_10_63" , 10, 54, 112, "RAZ", 1, 1, 0, 0},
|
|
{"PRT" , 0, 6, 113, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 113, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 114, "R/W", 0, 1, 0ull, 0},
|
|
{"SPEED" , 1, 1, 114, "R/W", 0, 1, 1ull, 0},
|
|
{"DUPLEX" , 2, 1, 114, "R/W", 0, 1, 1ull, 0},
|
|
{"SLOTTIME" , 3, 1, 114, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_4_7" , 4, 4, 114, "RAZ", 1, 1, 0, 0},
|
|
{"SPEED_MSB" , 8, 1, 114, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_9_11" , 9, 3, 114, "RAZ", 1, 1, 0, 0},
|
|
{"RX_IDLE" , 12, 1, 114, "RO", 0, 1, 1ull, 0},
|
|
{"TX_IDLE" , 13, 1, 114, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_14_63" , 14, 50, 114, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 64, 115, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 116, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 117, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 118, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 119, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 120, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 0, 8, 121, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 121, "RAZ", 1, 1, 0, 0},
|
|
{"BCST" , 0, 1, 122, "R/W", 0, 1, 1ull, 0},
|
|
{"MCST" , 1, 2, 122, "R/W", 0, 1, 0ull, 0},
|
|
{"CAM_MODE" , 3, 1, 122, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 122, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 5, 123, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_5_63" , 5, 59, 123, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 124, "RAZ", 1, 1, 0, 0},
|
|
{"CAREXT" , 1, 1, 124, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_2" , 2, 1, 124, "RAZ", 1, 1, 0, 0},
|
|
{"JABBER" , 3, 1, 124, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCSERR" , 4, 1, 124, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_5_6" , 5, 2, 124, "RAZ", 1, 1, 0, 0},
|
|
{"RCVERR" , 7, 1, 124, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SKPERR" , 8, 1, 124, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_9_63" , 9, 55, 124, "RAZ", 1, 1, 0, 0},
|
|
{"PRE_CHK" , 0, 1, 125, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PRE_STRP" , 1, 1, 125, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_DRP" , 2, 1, 125, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_BCK" , 3, 1, 125, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_MCST" , 4, 1, 125, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_SMAC" , 5, 1, 125, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRE_FREE" , 6, 1, 125, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_7_8" , 7, 2, 125, "RAZ", 1, 1, 0, 0},
|
|
{"PRE_ALIGN" , 9, 1, 125, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NULL_DIS" , 10, 1, 125, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 125, "RAZ", 1, 1, 0, 0},
|
|
{"IFG" , 0, 4, 126, "R/W", 0, 0, 8ull, 8ull},
|
|
{"RESERVED_4_63" , 4, 60, 126, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 127, "RAZ", 1, 1, 0, 0},
|
|
{"CAREXT" , 1, 1, 127, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 127, "RAZ", 1, 1, 0, 0},
|
|
{"JABBER" , 3, 1, 127, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 127, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_6" , 5, 2, 127, "RAZ", 1, 1, 0, 0},
|
|
{"RCVERR" , 7, 1, 127, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 127, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 127, "RAZ", 1, 1, 0, 0},
|
|
{"OVRERR" , 10, 1, 127, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 127, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 127, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 127, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 127, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 127, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_18" , 16, 3, 127, "RAZ", 1, 1, 0, 0},
|
|
{"PAUSE_DRP" , 19, 1, 127, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LOC_FAULT" , 20, 1, 127, "R/W", 0, 0, 0ull, 0ull},
|
|
{"REM_FAULT" , 21, 1, 127, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAD_SEQ" , 22, 1, 127, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAD_TERM" , 23, 1, 127, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UNSOP" , 24, 1, 127, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UNEOP" , 25, 1, 127, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UNDAT" , 26, 1, 127, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HG2FLD" , 27, 1, 127, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HG2CC" , 28, 1, 127, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 127, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 128, "RAZ", 1, 1, 0, 0},
|
|
{"CAREXT" , 1, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 128, "RAZ", 1, 1, 0, 0},
|
|
{"JABBER" , 3, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_6" , 5, 2, 128, "RAZ", 1, 1, 0, 0},
|
|
{"RCVERR" , 7, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 128, "RAZ", 1, 1, 0, 0},
|
|
{"OVRERR" , 10, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_18" , 16, 3, 128, "RAZ", 1, 1, 0, 0},
|
|
{"PAUSE_DRP" , 19, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LOC_FAULT" , 20, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"REM_FAULT" , 21, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BAD_SEQ" , 22, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BAD_TERM" , 23, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UNSOP" , 24, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UNEOP" , 25, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UNDAT" , 26, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"HG2FLD" , 27, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"HG2CC" , 28, 1, 128, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 128, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 129, "R/W", 0, 0, 10240ull, 10240ull},
|
|
{"RESERVED_16_63" , 16, 48, 129, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 16, 130, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 130, "RAZ", 1, 1, 0, 0},
|
|
{"RD_CLR" , 0, 1, 131, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 131, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 132, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 132, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 133, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 133, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 134, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 134, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 135, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 135, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 136, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 136, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 137, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 137, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 138, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 138, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 139, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 139, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 140, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 140, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 7, 141, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 141, "RAZ", 1, 1, 0, 0},
|
|
{"FCSSEL" , 8, 1, 141, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 141, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 142, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_6_63" , 6, 58, 142, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 143, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_6_63" , 6, 58, 143, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 9, 144, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_9_63" , 9, 55, 144, "RAZ", 1, 1, 0, 0},
|
|
{"LGTIM2GO" , 0, 16, 145, "RO", 0, 1, 0ull, 0},
|
|
{"XOF" , 16, 16, 145, "RO", 0, 0, 0ull, 0ull},
|
|
{"PHTIM2GO" , 32, 16, 145, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 145, "RAZ", 1, 1, 0, 0},
|
|
{"COMMIT" , 0, 4, 146, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_15" , 4, 12, 146, "RAZ", 1, 1, 0, 0},
|
|
{"DROP" , 16, 4, 146, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 146, "RAZ", 1, 1, 0, 0},
|
|
{"PRTS" , 0, 3, 147, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_3_63" , 3, 61, 147, "RAZ", 1, 1, 0, 0},
|
|
{"LANE_RXD" , 0, 32, 148, "RO", 0, 1, 0ull, 0},
|
|
{"LANE_RXC" , 32, 4, 148, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 36, 3, 148, "RO", 0, 1, 0ull, 0},
|
|
{"VAL" , 39, 1, 148, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_40_63" , 40, 24, 148, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 2, 149, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 149, "RAZ", 1, 1, 0, 0},
|
|
{"SMAC" , 0, 48, 150, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 150, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 151, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP" , 16, 1, 151, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 151, "RAZ", 1, 1, 0, 0},
|
|
{"PREAMBLE" , 0, 1, 152, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PAD" , 1, 1, 152, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCS" , 2, 1, 152, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FORCE_FCS" , 3, 1, 152, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 152, "RAZ", 1, 1, 0, 0},
|
|
{"BURST" , 0, 16, 153, "R/W", 0, 0, 8192ull, 8192ull},
|
|
{"RESERVED_16_63" , 16, 48, 153, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL_EN" , 0, 1, 154, "R/W", 0, 0, 1ull, 1ull},
|
|
{"XSDEF_EN" , 1, 1, 154, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 154, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_SIZE" , 0, 8, 155, "R/W", 0, 0, 59ull, 59ull},
|
|
{"RESERVED_8_63" , 8, 56, 155, "RAZ", 1, 1, 0, 0},
|
|
{"INTERVAL" , 0, 16, 156, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 156, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 157, "R/W", 0, 1, 96ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 157, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 158, "RO", 1, 1, 0, 0},
|
|
{"MSG_TIME" , 16, 16, 158, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 158, "RAZ", 1, 1, 0, 0},
|
|
{"SEND" , 0, 1, 159, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 159, "RAZ", 1, 1, 0, 0},
|
|
{"ALIGN" , 0, 1, 160, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 160, "RAZ", 1, 1, 0, 0},
|
|
{"SLOT" , 0, 10, 161, "R/W", 0, 0, 512ull, 512ull},
|
|
{"RESERVED_10_63" , 10, 54, 161, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 162, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 162, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL" , 0, 32, 163, "RC/W", 0, 1, 0ull, 0},
|
|
{"XSDEF" , 32, 32, 163, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCOL" , 0, 32, 164, "RC/W", 0, 1, 0ull, 0},
|
|
{"SCOL" , 32, 32, 164, "RC/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 165, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 165, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 166, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 166, "RAZ", 1, 1, 0, 0},
|
|
{"HIST0" , 0, 32, 167, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST1" , 32, 32, 167, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST2" , 0, 32, 168, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST3" , 32, 32, 168, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST4" , 0, 32, 169, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST5" , 32, 32, 169, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST6" , 0, 32, 170, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST7" , 32, 32, 170, "RC/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 0, 32, 171, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 32, 32, 171, "RC/W", 0, 1, 0ull, 0},
|
|
{"CTL" , 0, 32, 172, "RC/W", 0, 1, 0ull, 0},
|
|
{"UNDFLW" , 32, 32, 172, "RC/W", 0, 1, 0ull, 0},
|
|
{"RD_CLR" , 0, 1, 173, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 173, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 9, 174, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_9_63" , 9, 55, 174, "RAZ", 1, 1, 0, 0},
|
|
{"BP" , 0, 4, 175, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 175, "RAZ", 1, 1, 0, 0},
|
|
{"LIMIT" , 0, 5, 176, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_5_63" , 5, 59, 176, "RAZ", 1, 1, 0, 0},
|
|
{"CORRUPT" , 0, 4, 177, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_4_63" , 4, 60, 177, "RAZ", 1, 1, 0, 0},
|
|
{"TX_XOF" , 0, 16, 178, "R/W1", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 178, "RAZ", 1, 1, 0, 0},
|
|
{"TX_XON" , 0, 16, 179, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 179, "RAZ", 1, 1, 0, 0},
|
|
{"IFG1" , 0, 4, 180, "R/W", 0, 1, 8ull, 0},
|
|
{"IFG2" , 4, 4, 180, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 180, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 181, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 181, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 4, 181, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 181, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 4, 181, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 4, 181, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LATE_COL" , 16, 4, 181, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 181, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 182, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 182, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 4, 182, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 182, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 4, 182, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 4, 182, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LATE_COL" , 16, 4, 182, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 182, "RAZ", 1, 1, 0, 0},
|
|
{"JAM" , 0, 8, 183, "R/W", 0, 1, 238ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 183, "RAZ", 1, 1, 0, 0},
|
|
{"LFSR" , 0, 16, 184, "R/W", 0, 1, 65535ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 184, "RAZ", 1, 1, 0, 0},
|
|
{"IGN_FULL" , 0, 4, 185, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP" , 4, 4, 185, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EN" , 8, 4, 185, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_31" , 12, 20, 185, "RAZ", 1, 1, 0, 0},
|
|
{"TX_PRT_BP" , 32, 16, 185, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 185, "RAZ", 1, 1, 0, 0},
|
|
{"DMAC" , 0, 48, 186, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
|
|
{"RESERVED_48_63" , 48, 16, 186, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 187, "R/W", 0, 0, 34824ull, 34824ull},
|
|
{"RESERVED_16_63" , 16, 48, 187, "RAZ", 1, 1, 0, 0},
|
|
{"PRTS" , 0, 5, 188, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 188, "RAZ", 1, 1, 0, 0},
|
|
{"DIC_EN" , 0, 1, 189, "R/W", 0, 0, 0ull, 1ull},
|
|
{"UNI_EN" , 1, 1, 189, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_3" , 2, 2, 189, "RAZ", 1, 1, 0, 0},
|
|
{"LS" , 4, 2, 189, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LS_BYP" , 6, 1, 189, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 189, "RAZ", 1, 1, 0, 0},
|
|
{"HG_EN" , 8, 1, 189, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HG_PAUSE_HGI" , 9, 2, 189, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_11_63" , 11, 53, 189, "RAZ", 1, 1, 0, 0},
|
|
{"THRESH" , 0, 4, 190, "R/W", 0, 0, 8ull, 8ull},
|
|
{"EN" , 4, 1, 190, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 190, "RAZ", 1, 1, 0, 0},
|
|
{"TX_OE" , 0, 1, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RX_XOR" , 1, 1, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_EN" , 2, 1, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_TYPE" , 3, 1, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_CNT" , 4, 4, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_SEL" , 8, 4, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLK_SEL" , 12, 2, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLK_GEN" , 14, 1, 191, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 191, "RAZ", 1, 1, 0, 0},
|
|
{"N" , 0, 32, 192, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 192, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 193, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 193, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 194, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 194, "RAZ", 1, 1, 0, 0},
|
|
{"CLR" , 0, 16, 195, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 195, "RAZ", 1, 1, 0, 0},
|
|
{"SET" , 0, 16, 196, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 196, "RAZ", 1, 1, 0, 0},
|
|
{"ICD" , 0, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBD" , 1, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRP1" , 2, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRP0" , 3, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRN1" , 4, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRN0" , 5, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBRQ1" , 6, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBRQ0" , 7, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNRT" , 8, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBR1" , 9, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBR0" , 10, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBDR1" , 11, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBDR0" , 12, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNR0" , 13, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNR1" , 14, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICR1" , 15, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICR0" , 16, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNRCB" , 17, 1, 197, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 197, "RAZ", 1, 1, 0, 0},
|
|
{"FAU_END" , 0, 1, 198, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB_ENB" , 1, 1, 198, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PKO_ENB" , 2, 1, 198, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INB_MAT" , 3, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OUTB_MAT" , 4, 1, 198, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 198, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 199, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 199, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 199, "RAZ", 1, 1, 0, 0},
|
|
{"TOUT_VAL" , 0, 12, 200, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TOUT_ENB" , 12, 1, 200, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 200, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 201, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 201, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 201, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 8, 202, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 8, 9, 202, "R/W", 0, 1, 0ull, 0},
|
|
{"OPC" , 17, 4, 202, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 21, 8, 202, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 202, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 8, 203, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 8, 9, 203, "R/W", 0, 1, 0ull, 0},
|
|
{"OPC" , 17, 4, 203, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 21, 8, 203, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 203, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 204, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 205, "R/W", 0, 1, 0ull, 0},
|
|
{"NP_SOP" , 0, 1, 206, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NP_EOP" , 1, 1, 206, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_SOP" , 2, 1, 206, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_EOP" , 3, 1, 206, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NP_DAT" , 4, 1, 206, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_DAT" , 5, 1, 206, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 206, "RAZ", 1, 1, 0, 0},
|
|
{"NP_SOP" , 0, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NP_EOP" , 1, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_SOP" , 2, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_EOP" , 3, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NP_DAT" , 4, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_DAT" , 5, 1, 207, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 207, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 208, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 208, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 208, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 209, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 209, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 209, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 210, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 210, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 210, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 9, 211, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 9, 8, 211, "R/W", 0, 1, 0ull, 0},
|
|
{"EOT" , 17, 1, 211, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 18, 8, 211, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_26_63" , 26, 38, 211, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 9, 212, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 9, 8, 212, "R/W", 0, 1, 0ull, 0},
|
|
{"EOT" , 17, 1, 212, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 18, 8, 212, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_26_63" , 26, 38, 212, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 213, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 214, "R/W", 0, 1, 0ull, 0},
|
|
{"CNT_VAL" , 0, 15, 215, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 215, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 215, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 216, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 216, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 216, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 217, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 217, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 217, "RAZ", 1, 1, 0, 0},
|
|
{"PORT" , 0, 6, 218, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 218, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP_SZ" , 0, 6, 219, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 219, "RAZ", 1, 1, 0, 0},
|
|
{"BACK" , 0, 4, 220, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 220, "RAZ", 1, 1, 0, 0},
|
|
{"BACK" , 0, 4, 221, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 221, "RAZ", 1, 1, 0, 0},
|
|
{"PWP" , 0, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_NEW" , 1, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_OLD" , 2, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRC_OFF" , 3, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ0" , 4, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ1" , 5, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM_WORD" , 6, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM0" , 7, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM1" , 8, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM2" , 9, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM3" , 10, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPQ_PBE0" , 11, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPQ_PBE1" , 12, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_POW" , 13, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_WP1" , 14, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_WQED" , 15, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSR_NCMD" , 16, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSR_MEM" , 17, 1, 222, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 222, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_ENB" , 0, 40, 223, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 223, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_CNT" , 0, 64, 224, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_EN" , 0, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OPC_MODE" , 1, 2, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PBP_EN" , 3, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WQE_LEND" , 4, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKT_LEND" , 5, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NADDBUF" , 6, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDPKT" , 7, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 8, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LEN_M8" , 9, 1, 225, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PKT_OFF" , 10, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPD_FULL" , 11, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PQ_NABUF" , 12, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PQ_APKT" , 13, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NO_WPTR" , 14, 1, 225, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 225, "RAZ", 1, 1, 0, 0},
|
|
{"PRC_PAR0" , 0, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR1" , 1, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR2" , 2, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR3" , 3, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_SUB" , 4, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DC_OVR" , 5, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CC_OVR" , 6, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C_COLL" , 7, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"D_COLL" , 8, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BC_OVR" , 9, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PQ_ADD" , 10, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PQ_SUB" , 11, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 226, "RAZ", 1, 1, 0, 0},
|
|
{"PRC_PAR0" , 0, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR1" , 1, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR2" , 2, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR3" , 3, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP_SUB" , 4, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DC_OVR" , 5, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CC_OVR" , 6, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C_COLL" , 7, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"D_COLL" , 8, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BC_OVR" , 9, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PQ_ADD" , 10, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PQ_SUB" , 11, 1, 227, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 227, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP_SZ" , 0, 6, 228, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 228, "RAZ", 1, 1, 0, 0},
|
|
{"MB_SIZE" , 0, 12, 229, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_12_63" , 12, 52, 229, "RAZ", 1, 1, 0, 0},
|
|
{"PTR" , 0, 29, 230, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 230, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 17, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_ENB" , 17, 1, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 231, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 17, 232, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_ENB" , 17, 1, 232, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 232, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 25, 233, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 233, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 25, 234, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 234, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 235, "RO", 0, 1, 0ull, 0},
|
|
{"WMARK" , 32, 32, 235, "R/W", 0, 1, 4294967295ull, 0},
|
|
{"INTR" , 0, 64, 236, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 0, 64, 237, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RADDR" , 0, 3, 238, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 3, 1, 238, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 4, 29, 238, "RO", 1, 1, 0, 0},
|
|
{"PRADDR" , 33, 3, 238, "RO", 1, 1, 0, 0},
|
|
{"MAX_PKT" , 36, 3, 238, "RO", 0, 0, 5ull, 5ull},
|
|
{"RESERVED_39_63" , 39, 25, 238, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 7, 239, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 7, 1, 239, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 8, 29, 239, "RO", 1, 1, 0, 0},
|
|
{"MAX_PKT" , 37, 7, 239, "RO", 0, 0, 8ull, 8ull},
|
|
{"RESERVED_44_63" , 44, 20, 239, "RAZ", 1, 1, 0, 0},
|
|
{"WQE_PCNT" , 0, 7, 240, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_PCNT" , 7, 7, 240, "RO", 0, 0, 0ull, 0ull},
|
|
{"PFIF_CNT" , 14, 3, 240, "RO", 0, 0, 0ull, 0ull},
|
|
{"WQEV_CNT" , 17, 1, 240, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTV_CNT" , 18, 1, 240, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 240, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 8, 241, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 8, 1, 241, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 9, 29, 241, "RO", 1, 1, 0, 0},
|
|
{"PRADDR" , 38, 8, 241, "RO", 1, 1, 0, 0},
|
|
{"WRADDR" , 46, 8, 241, "RO", 1, 1, 0, 0},
|
|
{"MAX_CNTS" , 54, 7, 241, "RO", 0, 0, 8ull, 8ull},
|
|
{"RESERVED_61_63" , 61, 3, 241, "RAZ", 1, 1, 0, 0},
|
|
{"PASS" , 0, 32, 242, "R/W", 0, 1, 0ull, 0},
|
|
{"DROP" , 32, 32, 242, "R/W", 0, 1, 0ull, 0},
|
|
{"Q0_PCNT" , 0, 32, 243, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 243, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_ENB" , 0, 36, 244, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AVG_DLY" , 36, 14, 244, "R/W", 0, 1, 0ull, 0},
|
|
{"PRB_DLY" , 50, 14, 244, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRT_ENB" , 0, 4, 245, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 245, "RAZ", 1, 1, 0, 0},
|
|
{"PRB_CON" , 0, 32, 246, "R/W", 0, 1, 0ull, 0},
|
|
{"AVG_CON" , 32, 8, 246, "R/W", 0, 1, 0ull, 0},
|
|
{"NEW_CON" , 40, 8, 246, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_PCNT" , 48, 1, 246, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 246, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 25, 247, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT" , 25, 6, 247, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 247, "RAZ", 1, 1, 0, 0},
|
|
{"PORT_BIT" , 0, 32, 248, "R/W", 0, 0, 4294967295ull, 4294967295ull},
|
|
{"RESERVED_32_35" , 32, 4, 248, "RAZ", 1, 1, 0, 0},
|
|
{"PORT_BIT2" , 36, 4, 248, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_40_63" , 40, 24, 248, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 249, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT_QOS" , 32, 9, 249, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_41_63" , 41, 23, 249, "RAZ", 1, 1, 0, 0},
|
|
{"WQE_POOL" , 0, 3, 250, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_3_63" , 3, 61, 250, "RAZ", 1, 1, 0, 0},
|
|
{"PTR" , 0, 29, 251, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 251, "RAZ", 1, 1, 0, 0},
|
|
{"WLB_DAT" , 0, 4, 252, "RO", 0, 0, 0ull, 0ull},
|
|
{"STIN_MSK" , 4, 1, 252, "RO", 0, 0, 0ull, 0ull},
|
|
{"DT" , 5, 1, 252, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTCNT" , 6, 10, 252, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_18" , 16, 3, 252, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WLB_MSK" , 19, 4, 252, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTBNK" , 23, 1, 252, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 252, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"L2T" , 0, 9, 253, "RO", 0, 0, 0ull, 0ull},
|
|
{"VAB_VWCF" , 9, 1, 253, "RO", 0, 0, 0ull, 0ull},
|
|
{"ILC" , 10, 1, 253, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_11" , 11, 1, 253, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VWDF" , 12, 4, 253, "RO", 0, 0, 0ull, 0ull},
|
|
{"PLC0" , 16, 1, 253, "RO", 0, 0, 0ull, 0ull},
|
|
{"PLC1" , 17, 1, 253, "RO", 0, 0, 0ull, 0ull},
|
|
{"PLC2" , 18, 1, 253, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 253, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XRDDAT" , 0, 1, 254, "RO", 0, 0, 0ull, 0ull},
|
|
{"XRDMSK" , 1, 1, 254, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 254, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IPCBST" , 3, 1, 254, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 254, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RMDF" , 8, 4, 254, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRB" , 12, 4, 254, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 254, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LRF_ARB_MODE" , 0, 1, 255, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RFB_ARB_MODE" , 1, 1, 255, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RSP_ARB_MODE" , 2, 1, 255, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MWF_CRD" , 3, 4, 255, "R/W", 0, 0, 2ull, 2ull},
|
|
{"IDXALIAS" , 7, 1, 255, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPEN" , 8, 1, 255, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FPEMPTY" , 9, 1, 255, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FPEXP" , 10, 4, 255, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_17" , 14, 4, 255, "RAZ", 1, 1, 0, 0},
|
|
{"LBIST" , 18, 1, 255, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BSTRUN" , 19, 1, 255, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 255, "RAZ", 1, 1, 0, 0},
|
|
{"L2T" , 0, 1, 256, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2D" , 1, 1, 256, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FINV" , 2, 1, 256, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SET" , 3, 3, 256, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PPNUM" , 6, 2, 256, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_9" , 8, 2, 256, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_DMP" , 10, 1, 256, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LFB_ENUM" , 11, 3, 256, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 256, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DT_TAG" , 0, 29, 257, "RO", 0, 0, 0ull, 0ull},
|
|
{"DT_VLD" , 29, 1, 257, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_30" , 30, 1, 257, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DTENA" , 31, 1, 257, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 257, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PLC0RMSK" , 0, 32, 258, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PLC1RMSK" , 32, 32, 258, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PLC2RMSK" , 0, 32, 259, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ILCRMSK" , 32, 32, 259, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OOB1EN" , 0, 1, 260, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OOB2EN" , 1, 1, 260, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OOB3EN" , 2, 1, 260, "R/W", 0, 0, 0ull, 1ull},
|
|
{"L2TSECEN" , 3, 1, 260, "R/W", 0, 0, 0ull, 1ull},
|
|
{"L2TDEDEN" , 4, 1, 260, "R/W", 0, 0, 0ull, 1ull},
|
|
{"L2DSECEN" , 5, 1, 260, "R/W", 0, 0, 0ull, 1ull},
|
|
{"L2DDEDEN" , 6, 1, 260, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LCKENA" , 7, 1, 260, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LCK2ENA" , 8, 1, 260, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_9_63" , 9, 55, 260, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OOB1" , 0, 1, 261, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OOB2" , 1, 1, 261, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OOB3" , 2, 1, 261, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"L2TSEC" , 3, 1, 261, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"L2TDED" , 4, 1, 261, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"L2DSEC" , 5, 1, 261, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"L2DDED" , 6, 1, 261, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK" , 7, 1, 261, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK2" , 8, 1, 261, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 261, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_ENA" , 0, 1, 262, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_3" , 1, 3, 262, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_BASE" , 4, 27, 262, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 262, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_OFFSET" , 0, 10, 263, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 263, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VLD" , 0, 1, 264, "RO", 0, 0, 0ull, 0ull},
|
|
{"CMD" , 1, 4, 264, "RO", 0, 0, 0ull, 0ull},
|
|
{"SID" , 5, 9, 264, "RO", 0, 0, 0ull, 0ull},
|
|
{"VABNUM" , 14, 3, 264, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_17" , 17, 1, 264, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SET" , 18, 3, 264, "RO", 0, 0, 0ull, 0ull},
|
|
{"IHD" , 21, 1, 264, "RO", 0, 0, 0ull, 0ull},
|
|
{"ITL" , 22, 1, 264, "RO", 0, 0, 0ull, 0ull},
|
|
{"INXT" , 23, 3, 264, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_26" , 26, 1, 264, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VAM" , 27, 1, 264, "RO", 0, 0, 0ull, 0ull},
|
|
{"STCFL" , 28, 1, 264, "RO", 0, 0, 0ull, 0ull},
|
|
{"STINV" , 29, 1, 264, "RO", 0, 0, 0ull, 0ull},
|
|
{"STPND" , 30, 1, 264, "RO", 0, 0, 0ull, 0ull},
|
|
{"STCPND" , 31, 1, 264, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 264, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VLD" , 0, 1, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTPRB" , 1, 1, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRBRTY" , 2, 1, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTMFL" , 3, 1, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTVTM" , 4, 1, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTRSC" , 5, 1, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTRSP" , 6, 1, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTDT" , 7, 1, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTRDA" , 8, 1, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTM" , 9, 1, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWRM" , 10, 1, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWHF" , 11, 1, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWHP" , 12, 1, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTDQ" , 13, 1, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTDW" , 14, 1, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTRSP" , 15, 1, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"BID" , 16, 2, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"DSGOING" , 18, 1, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 265, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_IDX" , 0, 9, 266, "RO", 0, 0, 0ull, 0ull},
|
|
{"LFB_TAG" , 9, 18, 266, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_63" , 27, 37, 266, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_HWM" , 0, 3, 267, "R/W", 0, 0, 7ull, 7ull},
|
|
{"RESERVED_3_3" , 3, 1, 267, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STPARTDIS" , 4, 1, 267, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 267, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STENA" , 0, 1, 268, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWBENA" , 1, 1, 268, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 268, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 0, 14, 269, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_19" , 14, 6, 269, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SADR" , 20, 14, 269, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_35" , 34, 2, 269, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSRC" , 36, 1, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 37, 27, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 0, 14, 270, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_19" , 14, 6, 270, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SADR" , 20, 14, 270, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_35" , 34, 2, 270, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSRC" , 36, 1, 270, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 37, 27, 270, "RO", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 0, 14, 271, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_19" , 14, 6, 271, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SADR" , 20, 14, 271, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_35" , 34, 2, 271, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSRC" , 36, 1, 271, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 37, 27, 271, "RO", 0, 0, 0ull, 0ull},
|
|
{"PFCNT0" , 0, 36, 272, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 272, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT0SEL" , 0, 6, 273, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0CLR" , 6, 1, 273, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0ENA" , 7, 1, 273, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1SEL" , 8, 6, 273, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1CLR" , 14, 1, 273, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1ENA" , 15, 1, 273, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2SEL" , 16, 6, 273, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2CLR" , 22, 1, 273, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2ENA" , 23, 1, 273, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3SEL" , 24, 6, 273, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3CLR" , 30, 1, 273, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3ENA" , 31, 1, 273, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0RDCLR" , 32, 1, 273, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1RDCLR" , 33, 1, 273, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2RDCLR" , 34, 1, 273, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3RDCLR" , 35, 1, 273, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 273, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP0GRP" , 0, 2, 274, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP1GRP" , 2, 2, 274, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP2GRP" , 4, 2, 274, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP3GRP" , 6, 2, 274, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 274, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK0" , 0, 8, 275, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK1" , 8, 8, 275, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK2" , 16, 8, 275, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK3" , 24, 8, 275, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 275, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSKIOB" , 0, 8, 276, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 276, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q0STAT" , 0, 34, 277, "RO", 0, 0, 0ull, 0ull},
|
|
{"FTL" , 34, 1, 277, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_35_63" , 35, 29, 277, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q1STAT" , 0, 34, 278, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 278, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q2STAT" , 0, 34, 279, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 279, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q3STAT" , 0, 34, 280, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 280, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 0, 1, 281, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_INTENA" , 1, 1, 281, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DED_INTENA" , 2, 1, 281, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 3, 1, 281, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 4, 1, 281, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BMHCLSEL" , 5, 1, 281, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 281, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 0, 10, 282, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_10" , 10, 1, 282, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSET" , 11, 3, 282, "RO", 0, 0, 0ull, 0ull},
|
|
{"FOWMSK" , 14, 4, 282, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 282, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW0" , 0, 10, 283, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW1" , 10, 10, 283, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 283, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW2" , 0, 10, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW3" , 10, 10, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 284, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q0FUS" , 0, 34, 285, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 285, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q1FUS" , 0, 34, 286, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 286, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q2FUS" , 0, 34, 287, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 287, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q3FUS" , 0, 34, 288, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRIP_256K" , 34, 1, 288, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRIP_128K" , 35, 1, 288, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_36" , 36, 1, 288, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EMA_CTL" , 37, 3, 288, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 288, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 0, 1, 289, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_INTENA" , 1, 1, 289, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DED_INTENA" , 2, 1, 289, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 3, 1, 289, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 4, 1, 289, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FSYN" , 5, 6, 289, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 11, 9, 289, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 289, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSET" , 21, 3, 289, "RO", 0, 0, 0ull, 0ull},
|
|
{"LCKERR" , 24, 1, 289, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK_INTENA" , 25, 1, 289, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LCKERR2" , 26, 1, 289, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK_INTENA2" , 27, 1, 289, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_28_63" , 28, 36, 289, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"START" , 0, 1, 290, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 290, "RAZ", 1, 0, 0, 0ull},
|
|
{"MRD" , 0, 3, 291, "RO", 1, 0, 0, 0ull},
|
|
{"MRF" , 3, 1, 291, "RO", 1, 0, 0, 0ull},
|
|
{"MWC" , 4, 1, 291, "RO", 1, 0, 0, 0ull},
|
|
{"MWD" , 5, 3, 291, "RO", 1, 0, 0, 0ull},
|
|
{"MWF" , 8, 1, 291, "RO", 1, 0, 0, 0ull},
|
|
{"CSRE2D" , 9, 1, 291, "RO", 1, 0, 0, 0ull},
|
|
{"CSRD2E" , 10, 1, 291, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 291, "RAZ", 1, 0, 0, 0ull},
|
|
{"PCTL_DAT" , 0, 5, 292, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_11" , 5, 7, 292, "RAZ", 0, 1, 0ull, 0},
|
|
{"PCTL_CSR" , 12, 4, 292, "R/W", 0, 1, 15ull, 0},
|
|
{"NCTL_DAT" , 16, 4, 292, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_27" , 20, 8, 292, "RAZ", 0, 1, 0ull, 0},
|
|
{"NCTL_CSR" , 28, 4, 292, "R/W", 0, 1, 15ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 292, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DIC" , 0, 2, 293, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QS_DIC" , 2, 2, 293, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TSKW" , 4, 2, 293, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SIL_LAT" , 6, 2, 293, "R/W", 0, 0, 1ull, 1ull},
|
|
{"BPRCH" , 8, 1, 293, "R/W", 0, 1, 0ull, 0},
|
|
{"FPRCH2" , 9, 1, 293, "R/W", 0, 0, 0ull, 1ull},
|
|
{"MODE32B" , 10, 1, 293, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRESET" , 11, 1, 293, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INORDER_MRF" , 12, 1, 293, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INORDER_MWF" , 13, 1, 293, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"R2R_SLOT" , 14, 1, 293, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RDIMM_ENA" , 15, 1, 293, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_17" , 16, 2, 293, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX_WRITE_BATCH" , 18, 4, 293, "R/W", 0, 0, 8ull, 8ull},
|
|
{"XOR_BANK" , 22, 1, 293, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SLOW_SCF" , 23, 1, 293, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DDR__PCTL" , 24, 4, 293, "RO", 1, 1, 0, 0},
|
|
{"DDR__NCTL" , 28, 4, 293, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 293, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 294, "RAZ", 0, 1, 0ull, 0},
|
|
{"DCC_ENABLE" , 8, 1, 294, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SIL_MODE" , 9, 1, 294, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEQUENCE" , 10, 3, 294, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDLEPOWER" , 13, 3, 294, "R/W", 0, 0, 0ull, 6ull},
|
|
{"FORCEWRITE" , 16, 4, 294, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECC_ADR" , 20, 1, 294, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_21_63" , 21, 43, 294, "RAZ", 1, 1, 0, 0},
|
|
{"DCLKCNT_HI" , 0, 32, 295, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 295, "RAZ", 1, 1, 0, 0},
|
|
{"DCLKCNT_LO" , 0, 32, 296, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 296, "RAZ", 1, 1, 0, 0},
|
|
{"DDR2" , 0, 1, 297, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RDQS" , 1, 1, 297, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLL90_BYP" , 2, 1, 297, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLL90_VLU" , 3, 5, 297, "R/W", 0, 1, 0ull, 0},
|
|
{"QDLL_ENA" , 8, 1, 297, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ODT_ENA" , 9, 1, 297, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DDR2T" , 10, 1, 297, "R/W", 0, 1, 0ull, 0},
|
|
{"CRIP_MODE" , 11, 1, 297, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TFAW" , 12, 5, 297, "R/W", 0, 0, 0ull, 9ull},
|
|
{"DDR_EOF" , 17, 4, 297, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SILO_HC" , 21, 1, 297, "R/W", 0, 1, 1ull, 0},
|
|
{"TWR" , 22, 3, 297, "R/W", 0, 0, 3ull, 1ull},
|
|
{"BWCNT" , 25, 1, 297, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POCAS" , 26, 1, 297, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDLAT" , 27, 3, 297, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BURST8" , 30, 1, 297, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BANK8" , 31, 1, 297, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 297, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CLK" , 0, 4, 298, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_4" , 4, 1, 298, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CMD" , 5, 4, 298, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 298, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DQ" , 10, 4, 298, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 298, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DLL90_VLU" , 0, 5, 299, "R/W", 0, 1, 0ull, 0},
|
|
{"DLL90_ENA" , 5, 1, 299, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLL90_BYP" , 6, 1, 299, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRESET" , 7, 1, 299, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 299, "RAZ", 1, 1, 0, 0},
|
|
{"CS_MASK" , 0, 8, 300, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_15" , 8, 8, 300, "RAZ", 0, 1, 0ull, 0},
|
|
{"ROW_LSB" , 16, 3, 300, "R/W", 0, 1, 3ull, 0},
|
|
{"BANK8" , 19, 1, 300, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_63" , 20, 44, 300, "RAZ", 0, 1, 0ull, 0},
|
|
{"MRDSYN0" , 0, 8, 301, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN1" , 8, 8, 301, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN2" , 16, 8, 301, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN3" , 24, 8, 301, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 301, "RAZ", 1, 1, 0, 0},
|
|
{"FCOL" , 0, 12, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"FROW" , 12, 14, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"FBANK" , 26, 3, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"FBUNK" , 29, 1, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"FDIMM" , 30, 2, 302, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 302, "RAZ", 1, 1, 0, 0},
|
|
{"IFBCNT_HI" , 0, 32, 303, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 303, "RAZ", 1, 1, 0, 0},
|
|
{"IFBCNT_LO" , 0, 32, 304, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 304, "RAZ", 1, 1, 0, 0},
|
|
{"INIT_START" , 0, 1, 305, "WR0", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 1, 1, 305, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ROW_LSB" , 2, 3, 305, "R/W", 0, 1, 3ull, 0},
|
|
{"PBANK_LSB" , 5, 4, 305, "R/W", 0, 1, 5ull, 0},
|
|
{"REF_INT" , 9, 6, 305, "R/W", 0, 0, 1ull, 2ull},
|
|
{"TCL" , 15, 4, 305, "R/W", 0, 1, 3ull, 0},
|
|
{"INTR_SEC_ENA" , 19, 1, 305, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INTR_DED_ENA" , 20, 1, 305, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 21, 4, 305, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 25, 4, 305, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BUNK_ENA" , 29, 1, 305, "R/W", 0, 1, 0ull, 0},
|
|
{"SILO_QC" , 30, 1, 305, "R/W", 0, 1, 0ull, 0},
|
|
{"RESET" , 31, 1, 305, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 305, "RAZ", 1, 1, 0, 0},
|
|
{"TRAS" , 0, 5, 306, "R/W", 0, 0, 12ull, 12ull},
|
|
{"TRCD" , 5, 4, 306, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TWTR" , 9, 4, 306, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TRP" , 13, 4, 306, "R/W", 0, 0, 5ull, 4ull},
|
|
{"TRFC" , 17, 5, 306, "R/W", 0, 0, 6ull, 7ull},
|
|
{"TMRD" , 22, 3, 306, "R/W", 0, 0, 2ull, 2ull},
|
|
{"CASLAT" , 25, 3, 306, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TRRD" , 28, 3, 306, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_31_63" , 31, 33, 306, "RAZ", 1, 1, 0, 0},
|
|
{"OPSCNT_HI" , 0, 32, 307, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 307, "RAZ", 1, 1, 0, 0},
|
|
{"OPSCNT_LO" , 0, 32, 308, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 308, "RAZ", 1, 1, 0, 0},
|
|
{"EN2" , 0, 1, 309, "R/W", 0, 1, 0ull, 0},
|
|
{"EN4" , 1, 1, 309, "R/W", 0, 1, 0ull, 0},
|
|
{"EN6" , 2, 1, 309, "R/W", 0, 1, 0ull, 0},
|
|
{"EN8" , 3, 1, 309, "R/W", 0, 1, 1ull, 0},
|
|
{"EN12" , 4, 1, 309, "R/W", 0, 1, 0ull, 0},
|
|
{"EN16" , 5, 1, 309, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_7" , 6, 2, 309, "RAZ", 0, 1, 0ull, 0},
|
|
{"CLKR" , 8, 6, 309, "R/W", 0, 1, 0ull, 0},
|
|
{"CLKF" , 14, 12, 309, "R/W", 0, 1, 31ull, 0},
|
|
{"RESET_N" , 26, 1, 309, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DIV_RESET" , 27, 1, 309, "R/W", 0, 0, 1ull, 0ull},
|
|
{"FASTEN_N" , 28, 1, 309, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BYPASS" , 29, 1, 309, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_63" , 30, 34, 309, "RAZ", 0, 1, 0ull, 0},
|
|
{"FBSLIP" , 0, 1, 310, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RFSLIP" , 1, 1, 310, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_21" , 2, 20, 310, "RAZ", 1, 1, 0, 0},
|
|
{"DDR__PCTL" , 22, 5, 310, "RO", 1, 1, 0, 0},
|
|
{"DDR__NCTL" , 27, 5, 310, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 310, "RAZ", 1, 1, 0, 0},
|
|
{"BNK" , 0, 3, 311, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 311, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"COL" , 4, 12, 311, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROW" , 16, 16, 311, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PATTERN" , 32, 8, 311, "R/W", 0, 0, 170ull, 170ull},
|
|
{"RANKMASK" , 40, 4, 311, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_63" , 44, 20, 311, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"BYTE" , 0, 4, 312, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_15" , 4, 12, 312, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"BITMASK" , 16, 16, 312, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 312, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"BYTE0" , 0, 4, 313, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE1" , 4, 4, 313, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE2" , 8, 4, 313, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE3" , 12, 4, 313, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE4" , 16, 4, 313, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE5" , 20, 4, 313, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE6" , 24, 4, 313, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE7" , 28, 4, 313, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE8" , 32, 4, 313, "R/W", 0, 1, 0ull, 0},
|
|
{"STATUS" , 36, 2, 313, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_38_63" , 38, 26, 313, "RAZ", 1, 0, 0, 0ull},
|
|
{"PCTL" , 0, 5, 314, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 314, "RAZ", 0, 1, 0ull, 0},
|
|
{"NCTL" , 8, 4, 314, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_12_15" , 12, 4, 314, "RAZ", 0, 1, 0ull, 0},
|
|
{"ENABLE" , 16, 1, 314, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_17_63" , 17, 47, 314, "RAZ", 0, 1, 0ull, 0},
|
|
{"RODT_LO0" , 0, 4, 315, "R/W", 0, 0, 15ull, 0ull},
|
|
{"RODT_LO1" , 4, 4, 315, "R/W", 0, 0, 15ull, 0ull},
|
|
{"RODT_LO2" , 8, 4, 315, "R/W", 0, 0, 15ull, 0ull},
|
|
{"RODT_LO3" , 12, 4, 315, "R/W", 0, 0, 15ull, 0ull},
|
|
{"RODT_HI0" , 16, 4, 315, "R/W", 0, 0, 15ull, 0ull},
|
|
{"RODT_HI1" , 20, 4, 315, "R/W", 0, 0, 15ull, 0ull},
|
|
{"RODT_HI2" , 24, 4, 315, "R/W", 0, 0, 15ull, 0ull},
|
|
{"RODT_HI3" , 28, 4, 315, "R/W", 0, 0, 15ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 315, "RAZ", 1, 1, 0, 0},
|
|
{"WODT_D0_R0" , 0, 8, 316, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D0_R1" , 8, 8, 316, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D1_R0" , 16, 8, 316, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D1_R1" , 24, 8, 316, "R/W", 0, 0, 255ull, 255ull},
|
|
{"RESERVED_32_63" , 32, 32, 316, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WODT_D2_R0" , 0, 8, 317, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D2_R1" , 8, 8, 317, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D3_R0" , 16, 8, 317, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D3_R1" , 24, 8, 317, "R/W", 0, 0, 255ull, 255ull},
|
|
{"RESERVED_32_63" , 32, 32, 317, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"NCBI" , 0, 1, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"LOC" , 1, 1, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"DMA" , 2, 1, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"NCBO_0" , 3, 1, 318, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 318, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 5, 319, "R/W", 0, 1, 31ull, 0},
|
|
{"PCTL" , 5, 5, 319, "R/W", 0, 1, 31ull, 0},
|
|
{"RESERVED_10_63" , 10, 54, 319, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 36, 320, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 36, 20, 320, "R/W", 0, 1, 0ull, 0},
|
|
{"ENDIAN" , 56, 1, 320, "R/W", 0, 1, 0ull, 0},
|
|
{"SWAP8" , 57, 1, 320, "R/W", 0, 1, 0ull, 0},
|
|
{"SWAP16" , 58, 1, 320, "R/W", 0, 1, 0ull, 0},
|
|
{"SWAP32" , 59, 1, 320, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_60" , 60, 1, 320, "RAZ", 1, 1, 0, 0},
|
|
{"CLR" , 61, 1, 320, "R/W", 0, 1, 0ull, 0},
|
|
{"RW" , 62, 1, 320, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 63, 1, 320, "R/W", 0, 1, 0ull, 0},
|
|
{"DONE" , 0, 1, 321, "R/W1C", 0, 1, 0ull, 0},
|
|
{"DMARQ" , 1, 1, 321, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_2_63" , 2, 62, 321, "RAZ", 1, 1, 0, 0},
|
|
{"DONE" , 0, 1, 322, "R/W", 0, 1, 0ull, 0},
|
|
{"DMARQ" , 1, 1, 322, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 322, "RAZ", 1, 1, 0, 0},
|
|
{"DMARQ" , 0, 6, 323, "R/W", 0, 1, 63ull, 0},
|
|
{"DMACK_S" , 6, 6, 323, "R/W", 0, 1, 63ull, 0},
|
|
{"OE_A" , 12, 6, 323, "R/W", 0, 1, 63ull, 0},
|
|
{"OE_N" , 18, 6, 323, "R/W", 0, 1, 63ull, 0},
|
|
{"WE_A" , 24, 6, 323, "R/W", 0, 1, 63ull, 0},
|
|
{"WE_N" , 30, 6, 323, "R/W", 0, 1, 63ull, 0},
|
|
{"DMACK_H" , 36, 6, 323, "R/W", 0, 1, 63ull, 0},
|
|
{"PAUSE" , 42, 6, 323, "R/W", 0, 1, 63ull, 0},
|
|
{"RESERVED_48_54" , 48, 7, 323, "RAZ", 1, 1, 0, 0},
|
|
{"WIDTH" , 55, 1, 323, "R/W", 0, 1, 0ull, 0},
|
|
{"DDR" , 56, 1, 323, "R/W", 0, 1, 0ull, 0},
|
|
{"RD_DLY" , 57, 3, 323, "R/W", 0, 1, 0ull, 0},
|
|
{"TIM_MULT" , 60, 2, 323, "R/W", 0, 1, 0ull, 0},
|
|
{"DMARQ_PI" , 62, 1, 323, "R/W", 0, 1, 0ull, 0},
|
|
{"DMACK_PI" , 63, 1, 323, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR_ERR" , 0, 1, 324, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WAIT_ERR" , 1, 1, 324, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 324, "RAZ", 1, 1, 0, 0},
|
|
{"ADR_INT" , 0, 1, 325, "R/W", 0, 1, 0ull, 0},
|
|
{"WAIT_INT" , 1, 1, 325, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 325, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 326, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 3, 5, 326, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 326, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 327, "RAZ", 1, 1, 0, 0},
|
|
{"BASE" , 3, 25, 327, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_30" , 28, 3, 327, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 31, 1, 327, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 327, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 328, "R/W", 1, 1, 0, 0},
|
|
{"BASE" , 0, 16, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 16, 12, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"WIDTH" , 28, 1, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"ALE" , 29, 1, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"ORBIT" , 30, 1, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 31, 1, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"OE_EXT" , 32, 2, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"WE_EXT" , 34, 2, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"SAM" , 36, 1, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"RD_DLY" , 37, 3, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"TIM_MULT" , 40, 2, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"DMACK" , 42, 2, 329, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 329, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 6, 330, "R/W", 0, 1, 63ull, 0},
|
|
{"CE" , 6, 6, 330, "R/W", 0, 1, 63ull, 0},
|
|
{"OE" , 12, 6, 330, "R/W", 0, 1, 63ull, 0},
|
|
{"WE" , 18, 6, 330, "R/W", 0, 1, 63ull, 0},
|
|
{"RD_HLD" , 24, 6, 330, "R/W", 0, 1, 63ull, 0},
|
|
{"WR_HLD" , 30, 6, 330, "R/W", 0, 1, 63ull, 0},
|
|
{"PAUSE" , 36, 6, 330, "R/W", 0, 1, 63ull, 0},
|
|
{"WAIT" , 42, 6, 330, "R/W", 0, 1, 63ull, 0},
|
|
{"PAGE" , 48, 6, 330, "R/W", 0, 1, 63ull, 0},
|
|
{"ALE" , 54, 6, 330, "R/W", 0, 1, 63ull, 0},
|
|
{"PAGES" , 60, 2, 330, "R/W", 0, 1, 0ull, 0},
|
|
{"WAITM" , 62, 1, 330, "R/W", 0, 1, 0ull, 0},
|
|
{"PAGEM" , 63, 1, 330, "R/W", 0, 1, 0ull, 0},
|
|
{"FIF_THR" , 0, 6, 331, "R/W", 0, 0, 26ull, 26ull},
|
|
{"RESERVED_6_7" , 6, 2, 331, "RAZ", 1, 1, 0, 0},
|
|
{"FIF_CNT" , 8, 6, 331, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_15" , 14, 2, 331, "RAZ", 1, 1, 0, 0},
|
|
{"DMA_THR" , 16, 6, 331, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_22_63" , 22, 42, 331, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 64, 332, "R/W", 1, 1, 0, 0},
|
|
{"MAN_INFO" , 0, 32, 333, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 333, "RAZ", 1, 1, 0, 0},
|
|
{"MAN_INFO" , 0, 32, 334, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 334, "RAZ", 1, 1, 0, 0},
|
|
{"PP_DIS" , 0, 4, 335, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_4_15" , 4, 12, 335, "RO", 1, 1, 0, 0},
|
|
{"CHIP_ID" , 16, 8, 335, "RO", 1, 1, 0, 0},
|
|
{"BIST_DIS" , 24, 1, 335, "RO", 1, 1, 0, 0},
|
|
{"RST_SHT" , 25, 1, 335, "RO", 1, 1, 0, 0},
|
|
{"NOCRYPTO" , 26, 1, 335, "RO", 1, 1, 0, 0},
|
|
{"NOMUL" , 27, 1, 335, "RO", 1, 1, 0, 0},
|
|
{"NODFA_CP2" , 28, 1, 335, "RO", 1, 1, 0, 0},
|
|
{"NOKASU" , 29, 1, 335, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_30_31" , 30, 2, 335, "RAZ", 1, 1, 0, 0},
|
|
{"RAID_EN" , 32, 1, 335, "RO", 1, 1, 0, 0},
|
|
{"FUS318" , 33, 1, 335, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_34_63" , 34, 30, 335, "RAZ", 1, 1, 0, 0},
|
|
{"ICACHE" , 0, 24, 336, "RO", 1, 1, 0, 0},
|
|
{"NODFA_DTE" , 24, 1, 336, "RO", 1, 1, 0, 0},
|
|
{"NOZIP" , 25, 1, 336, "RO", 1, 1, 0, 0},
|
|
{"EFUS_IGN" , 26, 1, 336, "RO", 1, 1, 0, 0},
|
|
{"EFUS_LCK" , 27, 1, 336, "RO", 1, 1, 0, 0},
|
|
{"BAR2_EN" , 28, 1, 336, "RO", 1, 1, 0, 0},
|
|
{"ZIP_CRIP" , 29, 2, 336, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_31_63" , 31, 33, 336, "RAZ", 1, 1, 0, 0},
|
|
{"EMA" , 0, 3, 337, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 337, "RAZ", 1, 1, 0, 0},
|
|
{"EFF_EMA" , 4, 3, 337, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 337, "RAZ", 1, 1, 0, 0},
|
|
{"PDF" , 0, 64, 338, "RO", 1, 1, 0, 0},
|
|
{"FBSLIP" , 0, 1, 339, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RFSLIP" , 1, 1, 339, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 339, "RAZ", 1, 1, 0, 0},
|
|
{"PROG" , 0, 1, 340, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_1_63" , 1, 63, 340, "RAZ", 1, 1, 0, 0},
|
|
{"SETUP" , 0, 8, 341, "R/W", 0, 1, 3ull, 0},
|
|
{"SCLK_HI" , 8, 12, 341, "R/W", 0, 1, 100ull, 0},
|
|
{"SCLK_LO" , 20, 4, 341, "R/W", 0, 1, 2ull, 0},
|
|
{"OUT" , 24, 8, 341, "R/W", 0, 1, 3ull, 0},
|
|
{"PROG_PIN" , 32, 1, 341, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_33_63" , 33, 31, 341, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 8, 342, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EFUSE" , 8, 1, 342, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 342, "RAZ", 1, 1, 0, 0},
|
|
{"PEND" , 12, 1, 342, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 342, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 16, 8, 342, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_24_63" , 24, 40, 342, "RAZ", 1, 1, 0, 0},
|
|
{"REPAIR0" , 0, 14, 343, "RO", 0, 0, 0ull, 0ull},
|
|
{"REPAIR1" , 14, 14, 343, "RO", 0, 0, 0ull, 0ull},
|
|
{"REPAIR2" , 28, 14, 343, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_42_63" , 42, 22, 343, "RAZ", 1, 1, 0, 0},
|
|
{"TOO_MANY" , 0, 1, 344, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 344, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 3, 345, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_3_63" , 3, 61, 345, "RAZ", 1, 1, 0, 0},
|
|
{"ST_INT" , 0, 1, 346, "R/W1C", 0, 1, 0ull, 0},
|
|
{"TS_INT" , 1, 1, 346, "R/W1C", 0, 1, 0ull, 0},
|
|
{"CORE_INT" , 2, 1, 346, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_3" , 3, 1, 346, "RAZ", 1, 1, 0, 0},
|
|
{"ST_EN" , 4, 1, 346, "R/W", 0, 1, 0ull, 0},
|
|
{"TS_EN" , 5, 1, 346, "R/W", 0, 1, 0ull, 0},
|
|
{"CORE_EN" , 6, 1, 346, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_7" , 7, 1, 346, "RAZ", 1, 1, 0, 0},
|
|
{"SDA_OVR" , 8, 1, 346, "R/W", 0, 1, 0ull, 0},
|
|
{"SCL_OVR" , 9, 1, 346, "R/W", 0, 1, 0ull, 0},
|
|
{"SDA" , 10, 1, 346, "RO", 1, 1, 0, 0},
|
|
{"SCL" , 11, 1, 346, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_12_63" , 12, 52, 346, "RAZ", 1, 1, 0, 0},
|
|
{"D" , 0, 32, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"EOP_IA" , 32, 3, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"IA" , 35, 5, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"A" , 40, 10, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"SCR" , 50, 2, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 52, 3, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"SOVR" , 55, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"R" , 56, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"OP" , 57, 4, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"EIA" , 61, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"SLONLY" , 62, 1, 347, "R/W", 0, 1, 0ull, 0},
|
|
{"V" , 63, 1, 347, "RC/W", 0, 1, 0ull, 0},
|
|
{"D" , 0, 32, 348, "R/W", 0, 1, 0ull, 0},
|
|
{"IA" , 32, 8, 348, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_40_63" , 40, 24, 348, "RAZ", 1, 1, 0, 0},
|
|
{"D" , 0, 32, 349, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_32_61" , 32, 30, 349, "RAZ", 1, 1, 0, 0},
|
|
{"V" , 62, 2, 349, "RC/W", 0, 1, 0ull, 0},
|
|
{"DLH" , 0, 8, 350, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 350, "RAZ", 1, 1, 0, 0},
|
|
{"DLL" , 0, 8, 351, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 351, "RAZ", 1, 1, 0, 0},
|
|
{"FAR" , 0, 1, 352, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 352, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 353, "WO", 0, 1, 0ull, 0},
|
|
{"RXFR" , 1, 1, 353, "WO", 0, 1, 0ull, 0},
|
|
{"TXFR" , 2, 1, 353, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_3" , 3, 1, 353, "RAZ", 0, 1, 0ull, 0},
|
|
{"TXTRIG" , 4, 2, 353, "WO", 0, 1, 0ull, 0},
|
|
{"RXTRIG" , 6, 2, 353, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 353, "RAZ", 1, 1, 0, 0},
|
|
{"HTX" , 0, 1, 354, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 354, "RAZ", 1, 1, 0, 0},
|
|
{"ERBFI" , 0, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"ETBEI" , 1, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"ELSI" , 2, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"EDSSI" , 3, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_6" , 4, 3, 355, "RAZ", 0, 1, 0ull, 0},
|
|
{"PTIME" , 7, 1, 355, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 355, "RAZ", 1, 1, 0, 0},
|
|
{"IID" , 0, 4, 356, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_4_5" , 4, 2, 356, "RAZ", 0, 1, 0ull, 0},
|
|
{"FEN" , 6, 2, 356, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 356, "RAZ", 1, 1, 0, 0},
|
|
{"CLS" , 0, 2, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"STOP" , 2, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"PEN" , 3, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"EPS" , 4, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_5" , 5, 1, 357, "RAZ", 0, 1, 0ull, 0},
|
|
{"BRK" , 6, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"DLAB" , 7, 1, 357, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 357, "RAZ", 1, 1, 0, 0},
|
|
{"DR" , 0, 1, 358, "RO", 0, 1, 0ull, 0},
|
|
{"OE" , 1, 1, 358, "RC", 0, 1, 0ull, 0},
|
|
{"PE" , 2, 1, 358, "RC", 0, 1, 0ull, 0},
|
|
{"FE" , 3, 1, 358, "RC", 0, 1, 0ull, 0},
|
|
{"BI" , 4, 1, 358, "RC", 0, 1, 0ull, 0},
|
|
{"THRE" , 5, 1, 358, "RO", 0, 1, 1ull, 0},
|
|
{"TEMT" , 6, 1, 358, "RO", 0, 1, 1ull, 0},
|
|
{"FERR" , 7, 1, 358, "RC", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 358, "RAZ", 1, 1, 0, 0},
|
|
{"DTR" , 0, 1, 359, "R/W", 0, 1, 0ull, 0},
|
|
{"RTS" , 1, 1, 359, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT1" , 2, 1, 359, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT2" , 3, 1, 359, "R/W", 0, 1, 0ull, 0},
|
|
{"LOOP" , 4, 1, 359, "R/W", 0, 1, 0ull, 0},
|
|
{"AFCE" , 5, 1, 359, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 359, "RAZ", 0, 1, 0ull, 0},
|
|
{"DCTS" , 0, 1, 360, "RC", 0, 1, 0ull, 0},
|
|
{"DDSR" , 1, 1, 360, "RC", 0, 1, 0ull, 0},
|
|
{"TERI" , 2, 1, 360, "RC", 0, 1, 0ull, 0},
|
|
{"DDCD" , 3, 1, 360, "RC", 0, 1, 0ull, 0},
|
|
{"CTS" , 4, 1, 360, "RO", 1, 1, 0, 0},
|
|
{"DSR" , 5, 1, 360, "RO", 0, 1, 0ull, 0},
|
|
{"RI" , 6, 1, 360, "RO", 0, 1, 0ull, 0},
|
|
{"DCD" , 7, 1, 360, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 360, "RAZ", 1, 1, 0, 0},
|
|
{"RBR" , 0, 8, 361, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 361, "RAZ", 1, 1, 0, 0},
|
|
{"RFL" , 0, 7, 362, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 362, "RAZ", 1, 1, 0, 0},
|
|
{"RFWD" , 0, 8, 363, "WO", 0, 1, 0ull, 0},
|
|
{"RFPE" , 8, 1, 363, "WO", 0, 1, 0ull, 0},
|
|
{"RFFE" , 9, 1, 363, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_10_63" , 10, 54, 363, "RAZ", 1, 1, 0, 0},
|
|
{"SBCR" , 0, 1, 364, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 364, "RAZ", 1, 1, 0, 0},
|
|
{"SCR" , 0, 8, 365, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 365, "RAZ", 1, 1, 0, 0},
|
|
{"SFE" , 0, 1, 366, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 366, "RAZ", 1, 1, 0, 0},
|
|
{"USR" , 0, 1, 367, "WO", 0, 1, 0ull, 0},
|
|
{"SRFR" , 1, 1, 367, "WO", 0, 1, 0ull, 0},
|
|
{"STFR" , 2, 1, 367, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_63" , 3, 61, 367, "RAZ", 1, 1, 0, 0},
|
|
{"SRT" , 0, 2, 368, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 368, "RAZ", 1, 1, 0, 0},
|
|
{"SRTS" , 0, 1, 369, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 369, "RAZ", 1, 1, 0, 0},
|
|
{"STT" , 0, 2, 370, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 370, "RAZ", 1, 1, 0, 0},
|
|
{"TFL" , 0, 7, 371, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 371, "RAZ", 1, 1, 0, 0},
|
|
{"TFR" , 0, 8, 372, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 372, "RAZ", 1, 1, 0, 0},
|
|
{"THR" , 0, 8, 373, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 373, "RAZ", 1, 1, 0, 0},
|
|
{"BUSY" , 0, 1, 374, "RO", 0, 1, 0ull, 0},
|
|
{"TFNF" , 1, 1, 374, "RO", 0, 1, 1ull, 0},
|
|
{"TFE" , 2, 1, 374, "RO", 0, 1, 1ull, 0},
|
|
{"RFNE" , 3, 1, 374, "RO", 0, 1, 0ull, 0},
|
|
{"RFF" , 4, 1, 374, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 374, "RAZ", 1, 1, 0, 0},
|
|
{"DLH" , 0, 8, 375, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 375, "RAZ", 1, 1, 0, 0},
|
|
{"DLL" , 0, 8, 376, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 376, "RAZ", 1, 1, 0, 0},
|
|
{"FAR" , 0, 1, 377, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 377, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 378, "WO", 0, 1, 0ull, 0},
|
|
{"RXFR" , 1, 1, 378, "WO", 0, 1, 0ull, 0},
|
|
{"TXFR" , 2, 1, 378, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_3" , 3, 1, 378, "RAZ", 0, 1, 0ull, 0},
|
|
{"TXTRIG" , 4, 2, 378, "WO", 0, 1, 0ull, 0},
|
|
{"RXTRIG" , 6, 2, 378, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 378, "RAZ", 1, 1, 0, 0},
|
|
{"HTX" , 0, 1, 379, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 379, "RAZ", 1, 1, 0, 0},
|
|
{"ERBFI" , 0, 1, 380, "R/W", 0, 1, 0ull, 0},
|
|
{"ETBEI" , 1, 1, 380, "R/W", 0, 1, 0ull, 0},
|
|
{"ELSI" , 2, 1, 380, "R/W", 0, 1, 0ull, 0},
|
|
{"EDSSI" , 3, 1, 380, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_6" , 4, 3, 380, "RAZ", 0, 1, 0ull, 0},
|
|
{"PTIME" , 7, 1, 380, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 380, "RAZ", 1, 1, 0, 0},
|
|
{"IID" , 0, 4, 381, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_4_5" , 4, 2, 381, "RAZ", 0, 1, 0ull, 0},
|
|
{"FEN" , 6, 2, 381, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 381, "RAZ", 1, 1, 0, 0},
|
|
{"CLS" , 0, 2, 382, "R/W", 0, 1, 0ull, 0},
|
|
{"STOP" , 2, 1, 382, "R/W", 0, 1, 0ull, 0},
|
|
{"PEN" , 3, 1, 382, "R/W", 0, 1, 0ull, 0},
|
|
{"EPS" , 4, 1, 382, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_5" , 5, 1, 382, "RAZ", 0, 1, 0ull, 0},
|
|
{"BRK" , 6, 1, 382, "R/W", 0, 1, 0ull, 0},
|
|
{"DLAB" , 7, 1, 382, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 382, "RAZ", 1, 1, 0, 0},
|
|
{"DR" , 0, 1, 383, "RO", 0, 1, 0ull, 0},
|
|
{"OE" , 1, 1, 383, "RC", 0, 1, 0ull, 0},
|
|
{"PE" , 2, 1, 383, "RC", 0, 1, 0ull, 0},
|
|
{"FE" , 3, 1, 383, "RC", 0, 1, 0ull, 0},
|
|
{"BI" , 4, 1, 383, "RC", 0, 1, 0ull, 0},
|
|
{"THRE" , 5, 1, 383, "RO", 0, 1, 1ull, 0},
|
|
{"TEMT" , 6, 1, 383, "RO", 0, 1, 1ull, 0},
|
|
{"FERR" , 7, 1, 383, "RC", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 383, "RAZ", 1, 1, 0, 0},
|
|
{"DTR" , 0, 1, 384, "R/W", 0, 1, 0ull, 0},
|
|
{"RTS" , 1, 1, 384, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT1" , 2, 1, 384, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT2" , 3, 1, 384, "R/W", 0, 1, 0ull, 0},
|
|
{"LOOP" , 4, 1, 384, "R/W", 0, 1, 0ull, 0},
|
|
{"AFCE" , 5, 1, 384, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 384, "RAZ", 0, 1, 0ull, 0},
|
|
{"DCTS" , 0, 1, 385, "RC", 0, 1, 0ull, 0},
|
|
{"DDSR" , 1, 1, 385, "RC", 0, 1, 0ull, 0},
|
|
{"TERI" , 2, 1, 385, "RC", 0, 1, 0ull, 0},
|
|
{"DDCD" , 3, 1, 385, "RC", 0, 1, 0ull, 0},
|
|
{"CTS" , 4, 1, 385, "RO", 1, 1, 0, 0},
|
|
{"DSR" , 5, 1, 385, "RO", 0, 1, 0ull, 0},
|
|
{"RI" , 6, 1, 385, "RO", 0, 1, 0ull, 0},
|
|
{"DCD" , 7, 1, 385, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 385, "RAZ", 1, 1, 0, 0},
|
|
{"RBR" , 0, 8, 386, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 386, "RAZ", 1, 1, 0, 0},
|
|
{"RFL" , 0, 7, 387, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 387, "RAZ", 1, 1, 0, 0},
|
|
{"RFWD" , 0, 8, 388, "WO", 0, 1, 0ull, 0},
|
|
{"RFPE" , 8, 1, 388, "WO", 0, 1, 0ull, 0},
|
|
{"RFFE" , 9, 1, 388, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_10_63" , 10, 54, 388, "RAZ", 1, 1, 0, 0},
|
|
{"SBCR" , 0, 1, 389, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 389, "RAZ", 1, 1, 0, 0},
|
|
{"SCR" , 0, 8, 390, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 390, "RAZ", 1, 1, 0, 0},
|
|
{"SFE" , 0, 1, 391, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 391, "RAZ", 1, 1, 0, 0},
|
|
{"USR" , 0, 1, 392, "WO", 0, 1, 0ull, 0},
|
|
{"SRFR" , 1, 1, 392, "WO", 0, 1, 0ull, 0},
|
|
{"STFR" , 2, 1, 392, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_63" , 3, 61, 392, "RAZ", 1, 1, 0, 0},
|
|
{"SRT" , 0, 2, 393, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 393, "RAZ", 1, 1, 0, 0},
|
|
{"SRTS" , 0, 1, 394, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 394, "RAZ", 1, 1, 0, 0},
|
|
{"STT" , 0, 2, 395, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 395, "RAZ", 1, 1, 0, 0},
|
|
{"TFL" , 0, 7, 396, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 396, "RAZ", 1, 1, 0, 0},
|
|
{"TFR" , 0, 8, 397, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 397, "RAZ", 1, 1, 0, 0},
|
|
{"THR" , 0, 8, 398, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 398, "RAZ", 1, 1, 0, 0},
|
|
{"BUSY" , 0, 1, 399, "RO", 0, 1, 0ull, 0},
|
|
{"TFNF" , 1, 1, 399, "RO", 0, 1, 1ull, 0},
|
|
{"TFE" , 2, 1, 399, "RO", 0, 1, 1ull, 0},
|
|
{"RFNE" , 3, 1, 399, "RO", 0, 1, 0ull, 0},
|
|
{"RFF" , 4, 1, 399, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 399, "RAZ", 1, 1, 0, 0},
|
|
{"ORFDAT" , 0, 1, 400, "RO", 0, 0, 0ull, 0ull},
|
|
{"IRFDAT" , 1, 1, 400, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPFDAT" , 2, 1, 400, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRQDAT" , 3, 1, 400, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 400, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MRQ_HWM" , 0, 2, 401, "R/W", 0, 0, 1ull, 1ull},
|
|
{"NBTARB" , 2, 1, 401, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LENDIAN" , 3, 1, 401, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 4, 1, 401, "R/W", 0, 0, 1ull, 0ull},
|
|
{"EN" , 5, 1, 401, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BUSY" , 6, 1, 401, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRC_STRIP" , 7, 1, 401, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 401, "RAZ", 1, 1, 0, 0},
|
|
{"OVFENA" , 0, 1, 402, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IVFENA" , 1, 1, 402, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OTHENA" , 2, 1, 402, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ITHENA" , 3, 1, 402, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DATA_DRPENA" , 4, 1, 402, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IRUNENA" , 5, 1, 402, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ORUNENA" , 6, 1, 402, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 402, "RAZ", 1, 1, 0, 0},
|
|
{"IRCNT" , 0, 20, 403, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 403, "RAZ", 1, 1, 0, 0},
|
|
{"IRHWM" , 0, 20, 404, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IBPLWM" , 20, 20, 404, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 404, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 405, "RAZ", 1, 1, 0, 0},
|
|
{"IBASE" , 3, 33, 405, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_39" , 36, 4, 405, "RAZ", 1, 1, 0, 0},
|
|
{"ISIZE" , 40, 20, 405, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 405, "RAZ", 1, 1, 0, 0},
|
|
{"IDBELL" , 0, 20, 406, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_31" , 20, 12, 406, "RAZ", 1, 1, 0, 0},
|
|
{"ITLPTR" , 32, 20, 406, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_52_63" , 52, 12, 406, "RAZ", 1, 1, 0, 0},
|
|
{"ODBLOVF" , 0, 1, 407, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IDBLOVF" , 1, 1, 407, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ORTHRESH" , 2, 1, 407, "RO", 0, 0, 0ull, 0ull},
|
|
{"IRTHRESH" , 3, 1, 407, "RO", 0, 0, 0ull, 0ull},
|
|
{"DATA_DRP" , 4, 1, 407, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IRUN" , 5, 1, 407, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ORUN" , 6, 1, 407, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 407, "RAZ", 1, 1, 0, 0},
|
|
{"ORCNT" , 0, 20, 408, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 408, "RAZ", 1, 1, 0, 0},
|
|
{"ORHWM" , 0, 20, 409, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 409, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 410, "RAZ", 1, 1, 0, 0},
|
|
{"OBASE" , 3, 33, 410, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_39" , 36, 4, 410, "RAZ", 1, 1, 0, 0},
|
|
{"OSIZE" , 40, 20, 410, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 410, "RAZ", 1, 1, 0, 0},
|
|
{"ODBELL" , 0, 20, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_31" , 20, 12, 411, "RAZ", 1, 1, 0, 0},
|
|
{"OTLPTR" , 32, 20, 411, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_52_63" , 52, 12, 411, "RAZ", 1, 1, 0, 0},
|
|
{"OREMCNT" , 0, 20, 412, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 412, "RAZ", 1, 1, 0, 0},
|
|
{"IREMCNT" , 32, 20, 412, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_52_63" , 52, 12, 412, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR_V" , 0, 1, 413, "R/W", 0, 1, 0ull, 0},
|
|
{"END_SWP" , 1, 2, 413, "R/W", 0, 1, 0ull, 0},
|
|
{"CA" , 3, 1, 413, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDR_IDX" , 4, 14, 413, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_31" , 18, 14, 413, "RAZ", 1, 1, 0, 0},
|
|
{"NCB_CMD" , 0, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSI" , 1, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"DR3_MEM" , 2, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF3" , 3, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF2" , 4, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF1" , 5, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF0" , 6, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSM1" , 7, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSM0" , 8, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_P1" , 9, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_P0" , 10, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_N" , 11, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_C1" , 12, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_C0" , 13, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_P1" , 14, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_P0" , 15, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_N" , 16, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_C1" , 17, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_C0" , 18, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_CO" , 19, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_NO" , 20, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_PO" , 21, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_CO" , 22, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_NO" , 23, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_PO" , 24, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"CPL_P1" , 25, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"CPL_P0" , 26, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"N2P1_O" , 27, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"N2P1_C" , 28, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"N2P0_O" , 29, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"N2P0_C" , 30, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"DR2_MEM" , 31, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"D3_PST" , 32, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"D2_PST" , 33, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"D1_PST" , 34, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"D0_PST" , 35, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"DR1_MEM" , 36, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"D3_MEM" , 37, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"D2_MEM" , 38, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"D1_MEM" , 39, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"D0_MEM" , 40, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"DR0_MEM" , 41, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"D3_MEM3" , 42, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"D2_MEM2" , 43, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"D1_MEM1" , 44, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"D0_MEM0" , 45, 1, 414, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_46_63" , 46, 18, 414, "RAZ", 1, 1, 0, 0},
|
|
{"WAIT_COM" , 0, 1, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAR2_CAX" , 1, 1, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAR2_ESX" , 2, 2, 415, "R/W", 0, 1, 0ull, 0},
|
|
{"BAR2_ENB" , 4, 1, 415, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PTLP_RO" , 5, 1, 415, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_6_6" , 6, 1, 415, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CTLP_RO" , 7, 1, 415, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INTA_MAP" , 8, 2, 415, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTB_MAP" , 10, 2, 415, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INTC_MAP" , 12, 2, 415, "R/W", 0, 0, 2ull, 2ull},
|
|
{"INTD_MAP" , 14, 2, 415, "R/W", 0, 0, 3ull, 3ull},
|
|
{"INTA" , 16, 1, 415, "RO", 0, 0, 1ull, 1ull},
|
|
{"INTB" , 17, 1, 415, "RO", 0, 0, 1ull, 1ull},
|
|
{"INTC" , 18, 1, 415, "RO", 0, 0, 1ull, 1ull},
|
|
{"INTD" , 19, 1, 415, "RO", 0, 0, 1ull, 1ull},
|
|
{"WAITL_COM" , 20, 1, 415, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_21_63" , 21, 43, 415, "RAZ", 1, 1, 0, 0},
|
|
{"WAIT_COM" , 0, 1, 416, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAR2_CAX" , 1, 1, 416, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAR2_ESX" , 2, 2, 416, "R/W", 0, 1, 0ull, 0},
|
|
{"BAR2_ENB" , 4, 1, 416, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PTLP_RO" , 5, 1, 416, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_6_6" , 6, 1, 416, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CTLP_RO" , 7, 1, 416, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INTA_MAP" , 8, 2, 416, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTB_MAP" , 10, 2, 416, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INTC_MAP" , 12, 2, 416, "R/W", 0, 0, 2ull, 2ull},
|
|
{"INTD_MAP" , 14, 2, 416, "R/W", 0, 0, 3ull, 3ull},
|
|
{"INTA" , 16, 1, 416, "RO", 0, 0, 1ull, 1ull},
|
|
{"INTB" , 17, 1, 416, "RO", 0, 0, 1ull, 1ull},
|
|
{"INTC" , 18, 1, 416, "RO", 0, 0, 1ull, 1ull},
|
|
{"INTD" , 19, 1, 416, "RO", 0, 0, 1ull, 1ull},
|
|
{"WAITL_COM" , 20, 1, 416, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_21_63" , 21, 43, 416, "RAZ", 1, 1, 0, 0},
|
|
{"CHIP_REV" , 0, 8, 417, "RO", 1, 1, 0, 0},
|
|
{"HOST_MODE" , 8, 1, 417, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_9_12" , 9, 4, 417, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ARB" , 13, 1, 417, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LNK_RST" , 14, 1, 417, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_15" , 15, 1, 417, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CFG_RTRY" , 16, 16, 417, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P0_NTAGS" , 32, 6, 417, "R/W", 0, 0, 32ull, 32ull},
|
|
{"P1_NTAGS" , 38, 6, 417, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_44_63" , 44, 20, 417, "RAZ", 1, 1, 0, 0},
|
|
{"C0_B0_D" , 0, 1, 418, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C0_WI_D" , 1, 1, 418, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C1_B0_D" , 2, 1, 418, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C1_WI_D" , 3, 1, 418, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C0_B1_S" , 4, 3, 418, "R/W", 0, 0, 1ull, 1ull},
|
|
{"C1_B1_S" , 7, 3, 418, "R/W", 0, 0, 1ull, 1ull},
|
|
{"C0_W_FLT" , 10, 1, 418, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C1_W_FLT" , 11, 1, 418, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRRS" , 12, 3, 418, "R/W", 0, 0, 2ull, 2ull},
|
|
{"MPS" , 15, 1, 418, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 418, "RAZ", 1, 1, 0, 0},
|
|
{"P0_FCNT" , 0, 6, 419, "RO", 0, 1, 0ull, 0},
|
|
{"P0_UCNT" , 6, 16, 419, "RO", 0, 1, 0ull, 0},
|
|
{"P1_FCNT" , 22, 6, 419, "RO", 0, 1, 0ull, 0},
|
|
{"P1_UCNT" , 28, 16, 419, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 419, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 17, 420, "RO", 0, 1, 0ull, 0},
|
|
{"DSEL_EXT" , 17, 1, 420, "R/W", 0, 0, 1ull, 0ull},
|
|
{"C_MUL" , 18, 5, 420, "RO", 1, 1, 0, 0},
|
|
{"QLM1_SPD" , 23, 2, 420, "RO", 1, 1, 0, 0},
|
|
{"QLM1_MODE" , 25, 2, 420, "RO", 1, 1, 0, 0},
|
|
{"QLM0_REV_LANES" , 27, 1, 420, "RO", 1, 1, 0, 0},
|
|
{"QLM0_LINK_WIDTH" , 28, 1, 420, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 420, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_SEL" , 0, 16, 421, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 421, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 32, 422, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 7, 422, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_39_63" , 39, 25, 422, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 16, 423, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_31" , 16, 16, 423, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_6" , 0, 7, 424, "RAZ", 1, 1, 0, 0},
|
|
{"SADDR" , 7, 29, 424, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 424, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 425, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 425, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 426, "R/W", 0, 1, 0ull, 0},
|
|
{"TIME" , 32, 32, 426, "R/W", 0, 1, 0ull, 0},
|
|
{"CNT" , 0, 32, 427, "R/W", 0, 1, 0ull, 0},
|
|
{"TIME" , 32, 32, 427, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA0" , 0, 32, 428, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA1" , 32, 32, 428, "R/W", 0, 1, 0ull, 0},
|
|
{"CSIZE" , 0, 14, 429, "R/W", 0, 1, 0ull, 0},
|
|
{"O_MODE" , 14, 1, 429, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O_ES" , 15, 2, 429, "R/W", 0, 1, 0ull, 0},
|
|
{"O_NS" , 17, 1, 429, "R/W", 0, 1, 0ull, 0},
|
|
{"O_RO" , 18, 1, 429, "R/W", 0, 1, 0ull, 0},
|
|
{"O_ADD1" , 19, 1, 429, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA_QUE" , 20, 3, 429, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB_ICHK" , 23, 9, 429, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB_DENB" , 32, 1, 429, "R/W", 0, 0, 0ull, 1ull},
|
|
{"B0_LEND" , 33, 1, 429, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA0_ENB" , 34, 1, 429, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1_ENB" , 35, 1, 429, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA2_ENB" , 36, 1, 429, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA3_ENB" , 37, 1, 429, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_38_63" , 38, 26, 429, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_4" , 0, 5, 430, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"D3_REQST" , 5, 5, 430, "RO", 0, 1, 0ull, 0},
|
|
{"D2_REQST" , 10, 5, 430, "RO", 0, 1, 0ull, 0},
|
|
{"D1_REQST" , 15, 5, 430, "RO", 0, 1, 0ull, 0},
|
|
{"D0_REQST" , 20, 5, 430, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_31" , 25, 7, 430, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"D3_DIFST" , 32, 7, 430, "RO", 0, 1, 0ull, 0},
|
|
{"D2_DIFST" , 39, 7, 430, "RO", 0, 1, 0ull, 0},
|
|
{"D1_DIFST" , 46, 7, 430, "RO", 0, 1, 0ull, 0},
|
|
{"D0_DIFST" , 53, 7, 430, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 430, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_8" , 0, 9, 431, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"D3_DFFST" , 9, 9, 431, "RO", 0, 1, 0ull, 0},
|
|
{"D2_DFFST" , 18, 9, 431, "RO", 0, 1, 0ull, 0},
|
|
{"D1_DFFST" , 27, 9, 431, "RO", 0, 1, 0ull, 0},
|
|
{"D0_DFFST" , 36, 9, 431, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_45_63" , 45, 19, 431, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"D3_DREST" , 0, 15, 432, "RO", 0, 1, 0ull, 0},
|
|
{"D2_DREST" , 15, 15, 432, "RO", 0, 1, 0ull, 0},
|
|
{"D1_DREST" , 30, 15, 432, "RO", 0, 1, 0ull, 0},
|
|
{"D0_DREST" , 45, 15, 432, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 432, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"D3_DWEST" , 0, 13, 433, "RO", 0, 1, 0ull, 0},
|
|
{"D2_DWEST" , 13, 13, 433, "RO", 0, 1, 0ull, 0},
|
|
{"D1_DWEST" , 26, 13, 433, "RO", 0, 1, 0ull, 0},
|
|
{"D0_DWEST" , 39, 13, 433, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_52_63" , 52, 12, 433, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DMA0_CPL" , 0, 1, 434, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1_CPL" , 1, 1, 434, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 434, "RAZ", 0, 1, 0ull, 0},
|
|
{"DMA0_CPL" , 0, 1, 435, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1_CPL" , 1, 1, 435, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 435, "RAZ", 0, 1, 0ull, 0},
|
|
{"DMA0_CPL" , 0, 1, 436, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1_CPL" , 1, 1, 436, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 436, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RML_RTO" , 0, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RML_WTO" , 1, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BAR0_TO" , 2, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOB2BIG" , 3, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA0DBO" , 4, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1DBO" , 5, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA2DBO" , 6, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA3DBO" , 7, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_8_8" , 8, 1, 437, "RAZ", 1, 1, 0, 0},
|
|
{"DMA0FI" , 9, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1FI" , 10, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DCNT0" , 11, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DCNT1" , 12, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DTIME0" , 13, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DTIME1" , 14, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSLDBOF" , 15, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PIDBOF" , 16, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCNT" , 17, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PTIME" , 18, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_AERI" , 19, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CRS0_ER" , 20, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_SE" , 21, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CRS0_DR" , 22, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_WAKE" , 23, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_PMEI" , 24, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_HPINT" , 25, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_AERI" , 26, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CRS1_ER" , 27, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_SE" , 28, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CRS1_DR" , 29, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_WAKE" , 30, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_PMEI" , 31, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_HPINT" , 32, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_B0" , 33, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_B1" , 34, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_B2" , 35, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_WI" , 36, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_BX" , 37, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_B0" , 38, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_B1" , 39, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_B2" , 40, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_WI" , 41, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_BX" , 42, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_B0" , 43, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_B1" , 44, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_B2" , 45, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_WI" , 46, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_BX" , 47, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_B0" , 48, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_B1" , 49, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_B2" , 50, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_WI" , 51, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_BX" , 52, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_WF" , 53, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_WF" , 54, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_WF" , 55, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_WF" , 56, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_EXC" , 57, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_EXC" , 58, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_LDWN" , 59, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_LDWN" , 60, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INT_A" , 61, 1, 437, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_62_62" , 62, 1, 437, "RAZ", 0, 1, 0ull, 0},
|
|
{"MIO_INTA" , 63, 1, 437, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RML_RTO" , 0, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RML_WTO" , 1, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BAR0_TO" , 2, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOB2BIG" , 3, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA0DBO" , 4, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1DBO" , 5, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA2DBO" , 6, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA3DBO" , 7, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_8_8" , 8, 1, 438, "RAZ", 1, 1, 0, 0},
|
|
{"DMA0FI" , 9, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1FI" , 10, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DCNT0" , 11, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DCNT1" , 12, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DTIME0" , 13, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DTIME1" , 14, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSLDBOF" , 15, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PIDBOF" , 16, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCNT" , 17, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PTIME" , 18, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_AERI" , 19, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CRS0_ER" , 20, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_SE" , 21, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CRS0_DR" , 22, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_WAKE" , 23, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_PMEI" , 24, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_HPINT" , 25, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_AERI" , 26, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CRS1_ER" , 27, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_SE" , 28, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CRS1_DR" , 29, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_WAKE" , 30, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_PMEI" , 31, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_HPINT" , 32, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_B0" , 33, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_B1" , 34, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_B2" , 35, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_WI" , 36, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_BX" , 37, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_B0" , 38, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_B1" , 39, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_B2" , 40, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_WI" , 41, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_BX" , 42, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_B0" , 43, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_B1" , 44, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_B2" , 45, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_WI" , 46, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_BX" , 47, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_B0" , 48, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_B1" , 49, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_B2" , 50, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_WI" , 51, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_BX" , 52, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_WF" , 53, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_WF" , 54, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_WF" , 55, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_WF" , 56, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_EXC" , 57, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_EXC" , 58, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_LDWN" , 59, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_LDWN" , 60, 1, 438, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INT_A" , 61, 1, 438, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_62_63" , 62, 2, 438, "RAZ", 0, 1, 0ull, 0},
|
|
{"RML_RTO" , 0, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RML_WTO" , 1, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BAR0_TO" , 2, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IOB2BIG" , 3, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA0DBO" , 4, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1DBO" , 5, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA2DBO" , 6, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA3DBO" , 7, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_8" , 8, 1, 439, "RAZ", 1, 1, 0, 0},
|
|
{"DMA0FI" , 9, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1FI" , 10, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT0" , 11, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT1" , 12, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME0" , 13, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME1" , 14, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_18" , 15, 4, 439, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"C0_AERI" , 19, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRS0_ER" , 20, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_SE" , 21, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CRS0_DR" , 22, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_WAKE" , 23, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_PMEI" , 24, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_HPINT" , 25, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_AERI" , 26, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRS1_ER" , 27, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_SE" , 28, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CRS1_DR" , 29, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_WAKE" , 30, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_PMEI" , 31, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_HPINT" , 32, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_B0" , 33, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_B1" , 34, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_B2" , 35, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_WI" , 36, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_BX" , 37, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_B0" , 38, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_B1" , 39, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_B2" , 40, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_WI" , 41, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_BX" , 42, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_B0" , 43, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_B1" , 44, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_B2" , 45, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_WI" , 46, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_BX" , 47, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_B0" , 48, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_B1" , 49, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_B2" , 50, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_WI" , 51, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_BX" , 52, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_WF" , 53, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_WF" , 54, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_WF" , 55, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_WF" , 56, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_EXC" , 57, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_EXC" , 58, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_LDWN" , 59, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_LDWN" , 60, 1, 439, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INT_A" , 61, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_62_62" , 62, 1, 439, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO_INTA" , 63, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"RML_RTO" , 0, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"RML_WTO" , 1, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"BAR0_TO" , 2, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"IOB2BIG" , 3, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"DMA0DBO" , 4, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"DMA1DBO" , 5, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"DMA2DBO" , 6, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"DMA3DBO" , 7, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_8" , 8, 1, 440, "RAZ", 1, 1, 0, 0},
|
|
{"DMA0FI" , 9, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"DMA1FI" , 10, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"DCNT0" , 11, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"DCNT1" , 12, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTIME0" , 13, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTIME1" , 14, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_18" , 15, 4, 440, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"C0_AERI" , 19, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRS0_ER" , 20, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_SE" , 21, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRS0_DR" , 22, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_WAKE" , 23, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_PMEI" , 24, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_HPINT" , 25, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_AERI" , 26, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRS1_ER" , 27, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_SE" , 28, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRS1_DR" , 29, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_WAKE" , 30, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_PMEI" , 31, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_HPINT" , 32, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_B0" , 33, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_B1" , 34, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_B2" , 35, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_WI" , 36, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_BX" , 37, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_B0" , 38, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_B1" , 39, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_B2" , 40, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_WI" , 41, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_BX" , 42, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_B0" , 43, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_B1" , 44, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_B2" , 45, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_WI" , 46, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_BX" , 47, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_B0" , 48, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_B1" , 49, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_B2" , 50, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_WI" , 51, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_BX" , 52, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_WF" , 53, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_WF" , 54, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_WF" , 55, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_WF" , 56, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_EXC" , 57, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_EXC" , 58, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_LDWN" , 59, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_LDWN" , 60, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"INT_A" , 61, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_62_62" , 62, 1, 440, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO_INTA" , 63, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"DATA" , 0, 64, 441, "RO", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 442, "RO", 0, 1, 0ull, 0},
|
|
{"TIMER" , 0, 10, 443, "R/W", 0, 0, 0ull, 50ull},
|
|
{"MAX_WORD" , 10, 4, 443, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 443, "RAZ", 1, 1, 0, 0},
|
|
{"BA" , 0, 30, 444, "R/W", 0, 1, 0ull, 0},
|
|
{"ROW" , 30, 1, 444, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR" , 31, 1, 444, "R/W", 0, 1, 0ull, 0},
|
|
{"NSW" , 32, 1, 444, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR" , 33, 1, 444, "R/W", 0, 1, 0ull, 0},
|
|
{"ESW" , 34, 2, 444, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR" , 36, 2, 444, "R/W", 0, 1, 0ull, 0},
|
|
{"NMERGE" , 38, 1, 444, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PORT" , 39, 2, 444, "R/W", 0, 1, 0ull, 0},
|
|
{"ZERO" , 41, 1, 444, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_42_63" , 42, 22, 444, "RAZ", 1, 1, 0, 0},
|
|
{"ENB" , 0, 64, 445, "R/W", 0, 0, 0ull, 18446744073709551615ull},
|
|
{"ENB" , 0, 64, 446, "R/W", 0, 0, 0ull, 18446744073709551615ull},
|
|
{"ENB" , 0, 64, 447, "R/W", 0, 0, 0ull, 18446744073709551615ull},
|
|
{"ENB" , 0, 64, 448, "R/W", 0, 0, 0ull, 18446744073709551615ull},
|
|
{"INTR" , 0, 64, 449, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTR" , 0, 64, 450, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTR" , 0, 64, 451, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTR" , 0, 64, 452, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_INT" , 0, 8, 453, "R/W", 0, 1, 0ull, 0},
|
|
{"RD_INT" , 8, 8, 453, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 453, "RAZ", 1, 1, 0, 0},
|
|
{"MSI_INT" , 0, 8, 454, "R/W", 0, 1, 0ull, 0},
|
|
{"CIU_INT" , 8, 8, 454, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 454, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 0, 8, 455, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 455, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 456, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 8, 8, 456, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 456, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_15" , 0, 16, 457, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 16, 8, 457, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_24_63" , 24, 40, 457, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_23" , 0, 24, 458, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 24, 8, 458, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 458, "RAZ", 1, 1, 0, 0},
|
|
{"MIO" , 0, 1, 459, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX0" , 1, 1, 459, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX1" , 2, 1, 459, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPEI" , 3, 1, 459, "RO", 0, 0, 0ull, 0ull},
|
|
{"KEY" , 4, 1, 459, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPA" , 5, 1, 459, "RO", 0, 0, 0ull, 0ull},
|
|
{"DFA" , 6, 1, 459, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ZIP" , 7, 1, 459, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_8" , 8, 1, 459, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IPD" , 9, 1, 459, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 10, 1, 459, "RO", 0, 0, 0ull, 0ull},
|
|
{"TIM" , 11, 1, 459, "RO", 0, 0, 0ull, 0ull},
|
|
{"POW" , 12, 1, 459, "RO", 0, 0, 0ull, 0ull},
|
|
{"USB" , 13, 1, 459, "RO", 0, 0, 0ull, 0ull},
|
|
{"RAD" , 14, 1, 459, "RO", 0, 0, 0ull, 0ull},
|
|
{"USB1" , 15, 1, 459, "RO", 0, 0, 0ull, 0ull},
|
|
{"L2C" , 16, 1, 459, "RO", 0, 0, 0ull, 0ull},
|
|
{"LMC0" , 17, 1, 459, "RO", 0, 0, 0ull, 0ull},
|
|
{"SPX0" , 18, 1, 459, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SPX1" , 19, 1, 459, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PIP" , 20, 1, 459, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_21" , 21, 1, 459, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ASXPCS0" , 22, 1, 459, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASXPCS1" , 23, 1, 459, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_27" , 24, 4, 459, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"AGL" , 28, 1, 459, "RO", 0, 0, 0ull, 0ull},
|
|
{"LMC1" , 29, 1, 459, "RO", 0, 0, 0ull, 0ull},
|
|
{"IOB" , 30, 1, 459, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 459, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DATA" , 0, 64, 460, "R/W", 0, 1, 0ull, 0},
|
|
{"CSR" , 0, 39, 461, "RO", 0, 1, 1ull, 0},
|
|
{"ARB" , 39, 1, 461, "RO", 0, 1, 0ull, 0},
|
|
{"CPL0" , 40, 12, 461, "RO", 0, 1, 1ull, 0},
|
|
{"CPL1" , 52, 12, 461, "RO", 0, 1, 1ull, 0},
|
|
{"NND" , 0, 8, 462, "RO", 0, 1, 1ull, 0},
|
|
{"NNP0" , 8, 8, 462, "RO", 0, 1, 1ull, 0},
|
|
{"CSM0" , 16, 15, 462, "RO", 0, 1, 1ull, 0},
|
|
{"CSM1" , 31, 15, 462, "RO", 0, 1, 1ull, 0},
|
|
{"RAC" , 46, 1, 462, "RO", 0, 1, 1ull, 0},
|
|
{"NPEI" , 47, 1, 462, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 462, "RAZ", 1, 1, 0, 0},
|
|
{"NSM0" , 0, 13, 463, "RO", 0, 1, 1ull, 0},
|
|
{"NSM1" , 13, 13, 463, "RO", 0, 1, 1ull, 0},
|
|
{"PSM0" , 26, 15, 463, "RO", 0, 1, 1ull, 0},
|
|
{"PSM1" , 41, 15, 463, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_56_63" , 56, 8, 463, "RAZ", 1, 1, 0, 0},
|
|
{"RD_ADDR" , 0, 48, 464, "R/W", 0, 1, 0ull, 0},
|
|
{"IOBIT" , 48, 1, 464, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LD_CMD" , 49, 2, 464, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_51_63" , 51, 13, 464, "RAZ", 1, 1, 0, 0},
|
|
{"RD_DATA" , 0, 64, 465, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_0_1" , 0, 2, 466, "RAZ", 1, 1, 0, 0},
|
|
{"WR_ADDR" , 2, 46, 466, "R/W", 0, 1, 0ull, 0},
|
|
{"IOBIT" , 48, 1, 466, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 466, "RAZ", 1, 1, 0, 0},
|
|
{"WR_DATA" , 0, 64, 467, "R/W", 0, 1, 0ull, 0},
|
|
{"WR_MASK" , 0, 8, 468, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 468, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 32, 469, "R/W", 0, 0, 0ull, 2097152ull},
|
|
{"RESERVED_32_63" , 32, 32, 469, "RAZ", 1, 1, 0, 0},
|
|
{"VENDID" , 0, 16, 470, "RO/WRSL", 0, 0, 6013ull, 6013ull},
|
|
{"DEVID" , 16, 16, 470, "RO/WRSL", 0, 0, 128ull, 128ull},
|
|
{"ISAE" , 0, 1, 471, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSAE" , 1, 1, 471, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ME" , 2, 1, 471, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SCSE" , 3, 1, 471, "RO", 0, 0, 0ull, 0ull},
|
|
{"MWICE" , 4, 1, 471, "RO", 0, 0, 0ull, 0ull},
|
|
{"VPS" , 5, 1, 471, "RO", 0, 0, 0ull, 0ull},
|
|
{"PER" , 6, 1, 471, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDS_WCC" , 7, 1, 471, "RO", 0, 0, 0ull, 0ull},
|
|
{"SEE" , 8, 1, 471, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FBBE" , 9, 1, 471, "RO", 0, 0, 0ull, 0ull},
|
|
{"I_DIS" , 10, 1, 471, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_18" , 11, 8, 471, "RAZ", 1, 1, 0, 0},
|
|
{"I_STAT" , 19, 1, 471, "RO", 0, 0, 0ull, 0ull},
|
|
{"CL" , 20, 1, 471, "RO", 0, 0, 1ull, 1ull},
|
|
{"M66" , 21, 1, 471, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_22" , 22, 1, 471, "RAZ", 1, 1, 0, 0},
|
|
{"FBB" , 23, 1, 471, "RO", 0, 0, 0ull, 0ull},
|
|
{"MDPE" , 24, 1, 471, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DEVT" , 25, 2, 471, "RO", 0, 0, 0ull, 0ull},
|
|
{"STA" , 27, 1, 471, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTA" , 28, 1, 471, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RMA" , 29, 1, 471, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SSE" , 30, 1, 471, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPE" , 31, 1, 471, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RID" , 0, 8, 472, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PI" , 8, 8, 472, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"SC" , 16, 8, 472, "RO/WRSL", 0, 0, 48ull, 48ull},
|
|
{"BCC" , 24, 8, 472, "RO/WRSL", 0, 0, 11ull, 11ull},
|
|
{"CLS" , 0, 8, 473, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LT" , 8, 8, 473, "RO", 0, 0, 0ull, 0ull},
|
|
{"CHF" , 16, 7, 473, "RO", 0, 0, 0ull, 0ull},
|
|
{"MFD" , 23, 1, 473, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"BIST" , 24, 8, 473, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSPC" , 0, 1, 474, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 474, "RO/WRSL", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 474, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_13" , 4, 10, 474, "RAZ", 1, 1, 0, 0},
|
|
{"LBAB" , 14, 18, 474, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 0, 1, 475, "WORSL", 0, 0, 1ull, 1ull},
|
|
{"LMASK" , 1, 31, 475, "WORSL", 0, 0, 8191ull, 8191ull},
|
|
{"UBAB" , 0, 32, 476, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMASK" , 0, 32, 477, "WORSL", 0, 0, 0ull, 0ull},
|
|
{"MSPC" , 0, 1, 478, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 478, "RO/WRSL", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 478, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_25" , 4, 22, 478, "RAZ", 1, 1, 0, 0},
|
|
{"LBAB" , 26, 6, 478, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 0, 1, 479, "WORSL", 0, 0, 1ull, 1ull},
|
|
{"LMASK" , 1, 31, 479, "WORSL", 0, 0, 33554431ull, 33554431ull},
|
|
{"UBAB" , 0, 32, 480, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMASK" , 0, 32, 481, "WORSL", 0, 0, 0ull, 0ull},
|
|
{"MSPC" , 0, 1, 482, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 482, "RO/WRSL", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 482, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_31" , 4, 28, 482, "RAZ", 1, 1, 0, 0},
|
|
{"ENB" , 0, 1, 483, "WORSL", 0, 0, 1ull, 1ull},
|
|
{"LMASK" , 1, 31, 483, "WORSL", 0, 0, 2147483647ull, 2147483647ull},
|
|
{"RESERVED_0_6" , 0, 7, 484, "RAZ", 1, 1, 0, 0},
|
|
{"UBAB" , 7, 25, 484, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMASK" , 0, 32, 485, "WORSL", 0, 0, 127ull, 127ull},
|
|
{"CISP" , 0, 32, 486, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"SSVID" , 0, 16, 487, "RO/WRSL", 0, 0, 6013ull, 6013ull},
|
|
{"SSID" , 16, 16, 487, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"ER_EN" , 0, 1, 488, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_15" , 1, 15, 488, "RAZ", 1, 1, 0, 0},
|
|
{"ERADDR" , 16, 16, 488, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 0, 1, 489, "WORSL", 0, 0, 1ull, 1ull},
|
|
{"MASK" , 1, 31, 489, "WORSL", 0, 0, 2147483647ull, 2147483647ull},
|
|
{"CP" , 0, 8, 490, "RO/WRSL", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_8_31" , 8, 24, 490, "RAZ", 1, 1, 0, 0},
|
|
{"IL" , 0, 8, 491, "R/W", 0, 0, 255ull, 255ull},
|
|
{"INTA" , 8, 8, 491, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"MG" , 16, 8, 491, "RO", 0, 0, 0ull, 0ull},
|
|
{"ML" , 24, 8, 491, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMCID" , 0, 8, 492, "RO", 0, 0, 1ull, 0ull},
|
|
{"NCP" , 8, 8, 492, "RO/WRSL", 0, 0, 80ull, 0ull},
|
|
{"PMSV" , 16, 3, 492, "RO/WRSL", 0, 0, 3ull, 0ull},
|
|
{"PME_CLOCK" , 19, 1, 492, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 492, "RAZ", 1, 1, 0, 0},
|
|
{"DSI" , 21, 1, 492, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"AUXC" , 22, 3, 492, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"D1S" , 25, 1, 492, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"D2S" , 26, 1, 492, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PMES" , 27, 5, 492, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PS" , 0, 2, 493, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 493, "RAZ", 1, 1, 0, 0},
|
|
{"NSR" , 3, 1, 493, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 493, "RAZ", 1, 1, 0, 0},
|
|
{"PMEENS" , 8, 1, 493, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMDS" , 9, 4, 493, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMEDSIA" , 13, 2, 493, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMESS" , 15, 1, 493, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_21" , 16, 6, 493, "RAZ", 1, 1, 0, 0},
|
|
{"BD3H" , 22, 1, 493, "RO", 0, 0, 0ull, 0ull},
|
|
{"BPCCEE" , 23, 1, 493, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMDIA" , 24, 8, 493, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSICID" , 0, 8, 494, "RO", 0, 0, 5ull, 5ull},
|
|
{"NCP" , 8, 8, 494, "RO/WRSL", 0, 0, 112ull, 112ull},
|
|
{"MSIEN" , 16, 1, 494, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MMC" , 17, 3, 494, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"MME" , 20, 3, 494, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M64" , 23, 1, 494, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_24_31" , 24, 8, 494, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 495, "RAZ", 1, 1, 0, 0},
|
|
{"LMSI" , 2, 30, 495, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSI" , 0, 32, 496, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSIMD" , 0, 16, 497, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_31" , 16, 16, 497, "RAZ", 1, 1, 0, 0},
|
|
{"PCIEID" , 0, 8, 498, "RO", 0, 0, 16ull, 16ull},
|
|
{"NCP" , 8, 8, 498, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PCIECV" , 16, 4, 498, "RO", 0, 0, 2ull, 2ull},
|
|
{"DPT" , 20, 4, 498, "RO", 0, 0, 0ull, 0ull},
|
|
{"SI" , 24, 1, 498, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"IMN" , 25, 5, 498, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_31" , 30, 2, 498, "RAZ", 1, 1, 0, 0},
|
|
{"MPSS" , 0, 3, 499, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"PFS" , 3, 2, 499, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"ETFS" , 5, 1, 499, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"EL0AL" , 6, 3, 499, "RO/WRSL", 0, 0, 4ull, 4ull},
|
|
{"EL1AL" , 9, 3, 499, "RO/WRSL", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_12_14" , 12, 3, 499, "RAZ", 1, 1, 0, 0},
|
|
{"RBER" , 15, 1, 499, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_16_17" , 16, 2, 499, "RAZ", 1, 1, 0, 0},
|
|
{"CSPLV" , 18, 8, 499, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSPLS" , 26, 2, 499, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_31" , 28, 4, 499, "RAZ", 1, 1, 0, 0},
|
|
{"CE_EN" , 0, 1, 500, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NFE_EN" , 1, 1, 500, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FE_EN" , 2, 1, 500, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UR_EN" , 3, 1, 500, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RO_EN" , 4, 1, 500, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MPS" , 5, 3, 500, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ETF_EN" , 8, 1, 500, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PF_EN" , 9, 1, 500, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AP_EN" , 10, 1, 500, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NS_EN" , 11, 1, 500, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MRRS" , 12, 3, 500, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_15_15" , 15, 1, 500, "RAZ", 1, 1, 0, 0},
|
|
{"CE_D" , 16, 1, 500, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NFE_D" , 17, 1, 500, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FE_D" , 18, 1, 500, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UR_D" , 19, 1, 500, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AP_D" , 20, 1, 500, "RO", 0, 0, 0ull, 0ull},
|
|
{"TP" , 21, 1, 500, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_31" , 22, 10, 500, "RAZ", 1, 1, 0, 0},
|
|
{"MLS" , 0, 4, 501, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"MLW" , 4, 6, 501, "RO/WRSL", 0, 0, 8ull, 8ull},
|
|
{"ASLPMS" , 10, 2, 501, "RO/WRSL", 0, 0, 3ull, 3ull},
|
|
{"L0EL" , 12, 3, 501, "RO/WRSL", 0, 0, 6ull, 6ull},
|
|
{"L1EL" , 15, 3, 501, "RO/WRSL", 0, 0, 6ull, 6ull},
|
|
{"CPM" , 18, 1, 501, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"SDERC" , 19, 1, 501, "RO", 0, 0, 0ull, 0ull},
|
|
{"DLLARC" , 20, 1, 501, "RO", 0, 0, 0ull, 0ull},
|
|
{"LBNC" , 21, 1, 501, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 501, "RAZ", 1, 1, 0, 0},
|
|
{"PNUM" , 24, 8, 501, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"ASLPC" , 0, 2, 502, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 502, "RAZ", 1, 1, 0, 0},
|
|
{"RCB" , 3, 1, 502, "RO", 0, 0, 0ull, 0ull},
|
|
{"LD" , 4, 1, 502, "RO", 0, 0, 0ull, 0ull},
|
|
{"RL" , 5, 1, 502, "RO", 0, 0, 0ull, 0ull},
|
|
{"CCC" , 6, 1, 502, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ES" , 7, 1, 502, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECPM" , 8, 1, 502, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HAWD" , 9, 1, 502, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_15" , 10, 6, 502, "RAZ", 1, 1, 0, 0},
|
|
{"LS" , 16, 4, 502, "RO", 0, 0, 1ull, 1ull},
|
|
{"NLW" , 20, 6, 502, "RO", 0, 0, 0ull, 8ull},
|
|
{"RESERVED_26_26" , 26, 1, 502, "RAZ", 1, 1, 0, 0},
|
|
{"LT" , 27, 1, 502, "RO", 0, 0, 0ull, 0ull},
|
|
{"SCC" , 28, 1, 502, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"DLLA" , 29, 1, 502, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_31" , 30, 2, 502, "RAZ", 1, 1, 0, 0},
|
|
{"ABP" , 0, 1, 503, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PCP" , 1, 1, 503, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"MRLSP" , 2, 1, 503, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"AIP" , 3, 1, 503, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PIP" , 4, 1, 503, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"HP_S" , 5, 1, 503, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"HP_C" , 6, 1, 503, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"SP_LV" , 7, 8, 503, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"SP_LS" , 15, 2, 503, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"EMIP" , 17, 1, 503, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"NCCS" , 18, 1, 503, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PS_NUM" , 19, 13, 503, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"ABP_EN" , 0, 1, 504, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PF_EN" , 1, 1, 504, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRLS_EN" , 2, 1, 504, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PD_EN" , 3, 1, 504, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CCINT_EN" , 4, 1, 504, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HPINT_EN" , 5, 1, 504, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AIC" , 6, 2, 504, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PIC" , 8, 2, 504, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCC" , 10, 1, 504, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EMIC" , 11, 1, 504, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLLS_EN" , 12, 1, 504, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 504, "RAZ", 1, 1, 0, 0},
|
|
{"ABP_D" , 16, 1, 504, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PF_D" , 17, 1, 504, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRLS_C" , 18, 1, 504, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PD_C" , 19, 1, 504, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CCINT_D" , 20, 1, 504, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRLSS" , 21, 1, 504, "RO", 0, 0, 0ull, 0ull},
|
|
{"PDS" , 22, 1, 504, "RO", 0, 0, 0ull, 0ull},
|
|
{"EMIS" , 23, 1, 504, "RO", 0, 0, 0ull, 0ull},
|
|
{"DLLS_C" , 24, 1, 504, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_31" , 25, 7, 504, "RAZ", 1, 1, 0, 0},
|
|
{"CTRS" , 0, 4, 505, "RO", 0, 0, 0ull, 0ull},
|
|
{"CTDS" , 4, 1, 505, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_5_31" , 5, 27, 505, "RAZ", 1, 1, 0, 0},
|
|
{"CTV" , 0, 4, 506, "RO", 0, 0, 0ull, 0ull},
|
|
{"CTD" , 4, 1, 506, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 506, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 507, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 508, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 509, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 510, "RAZ", 1, 1, 0, 0},
|
|
{"PCIEEC" , 0, 16, 511, "RO", 0, 0, 1ull, 0ull},
|
|
{"CV" , 16, 4, 511, "RO", 0, 0, 1ull, 0ull},
|
|
{"NCO" , 20, 12, 511, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_3" , 0, 4, 512, "RAZ", 1, 1, 0, 0},
|
|
{"DLPES" , 4, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SDES" , 5, 1, 512, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_11" , 6, 6, 512, "RAZ", 1, 1, 0, 0},
|
|
{"PTLPS" , 12, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCPES" , 13, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CTS" , 14, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CAS" , 15, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UCS" , 16, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ROS" , 17, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MTLPS" , 18, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ECRCES" , 19, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"URES" , 20, 1, 512, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 512, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_3" , 0, 4, 513, "RAZ", 1, 1, 0, 0},
|
|
{"DLPEM" , 4, 1, 513, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SDEM" , 5, 1, 513, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_11" , 6, 6, 513, "RAZ", 1, 1, 0, 0},
|
|
{"PTLPM" , 12, 1, 513, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCPEM" , 13, 1, 513, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CTM" , 14, 1, 513, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAM" , 15, 1, 513, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UCM" , 16, 1, 513, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROM" , 17, 1, 513, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MTLPM" , 18, 1, 513, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECRCEM" , 19, 1, 513, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UREM" , 20, 1, 513, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 513, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_3" , 0, 4, 514, "RAZ", 1, 1, 0, 0},
|
|
{"DLPES" , 4, 1, 514, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SDES" , 5, 1, 514, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_11" , 6, 6, 514, "RAZ", 1, 1, 0, 0},
|
|
{"PTLPS" , 12, 1, 514, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCPES" , 13, 1, 514, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTS" , 14, 1, 514, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAS" , 15, 1, 514, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UCS" , 16, 1, 514, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROS" , 17, 1, 514, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MTLPS" , 18, 1, 514, "R/W", 0, 0, 1ull, 1ull},
|
|
{"ECRCES" , 19, 1, 514, "R/W", 0, 0, 0ull, 0ull},
|
|
{"URES" , 20, 1, 514, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 514, "RAZ", 1, 1, 0, 0},
|
|
{"RES" , 0, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_5" , 1, 5, 515, "RAZ", 1, 1, 0, 0},
|
|
{"BTLPS" , 6, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BDLLPS" , 7, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RNRS" , 8, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 515, "RAZ", 1, 1, 0, 0},
|
|
{"RTTS" , 12, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ANFES" , 13, 1, 515, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_31" , 14, 18, 515, "RAZ", 1, 1, 0, 0},
|
|
{"REM" , 0, 1, 516, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_5" , 1, 5, 516, "RAZ", 1, 1, 0, 0},
|
|
{"BTLPM" , 6, 1, 516, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BDLLPM" , 7, 1, 516, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNRM" , 8, 1, 516, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 516, "RAZ", 1, 1, 0, 0},
|
|
{"RTTM" , 12, 1, 516, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ANFEM" , 13, 1, 516, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_14_31" , 14, 18, 516, "RAZ", 1, 1, 0, 0},
|
|
{"FEP" , 0, 5, 517, "RO", 0, 0, 0ull, 0ull},
|
|
{"GC" , 5, 1, 517, "RO", 0, 0, 1ull, 1ull},
|
|
{"GE" , 6, 1, 517, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CC" , 7, 1, 517, "RO", 0, 0, 1ull, 1ull},
|
|
{"CE" , 8, 1, 517, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_31" , 9, 23, 517, "RAZ", 1, 1, 0, 0},
|
|
{"DWORD1" , 0, 32, 518, "RO", 0, 0, 0ull, 0ull},
|
|
{"DWORD2" , 0, 32, 519, "RO", 0, 0, 0ull, 0ull},
|
|
{"DWORD3" , 0, 32, 520, "RO", 0, 0, 0ull, 0ull},
|
|
{"DWORD4" , 0, 32, 521, "RO", 0, 0, 0ull, 0ull},
|
|
{"RTLTL" , 0, 16, 522, "R/W", 0, 0, 4143ull, 4143ull},
|
|
{"RTL" , 16, 16, 522, "R/W", 0, 0, 12429ull, 12429ull},
|
|
{"OMR" , 0, 32, 523, "R/W", 0, 1, 4294967295ull, 0},
|
|
{"LINK_NUM" , 0, 8, 524, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_14" , 8, 7, 524, "RAZ", 1, 1, 0, 0},
|
|
{"FORCE_LINK" , 15, 1, 524, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LINK_STATE" , 16, 6, 524, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 524, "RAZ", 1, 1, 0, 0},
|
|
{"LPEC" , 24, 8, 524, "R/W", 0, 0, 7ull, 7ull},
|
|
{"ACK_FREQ" , 0, 8, 525, "R/W", 0, 0, 0ull, 0ull},
|
|
{"N_FTS" , 8, 8, 525, "R/W", 0, 0, 128ull, 128ull},
|
|
{"N_FTS_CC" , 16, 8, 525, "R/W", 0, 0, 128ull, 128ull},
|
|
{"L0EL" , 24, 3, 525, "R/W", 0, 0, 3ull, 3ull},
|
|
{"L1EL" , 27, 3, 525, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_30_31" , 30, 2, 525, "RAZ", 1, 1, 0, 0},
|
|
{"OMR" , 0, 1, 526, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SD" , 1, 1, 526, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LE" , 2, 1, 526, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RA" , 3, 1, 526, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_4" , 4, 1, 526, "RAZ", 1, 1, 0, 0},
|
|
{"DLLLE" , 5, 1, 526, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_6" , 6, 1, 526, "RAZ", 1, 1, 0, 0},
|
|
{"FLM" , 7, 1, 526, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_15" , 8, 8, 526, "RO", 0, 0, 1ull, 1ull},
|
|
{"LME" , 16, 6, 526, "R/W", 0, 0, 7ull, 7ull},
|
|
{"RESERVED_22_24" , 22, 3, 526, "RAZ", 1, 1, 0, 0},
|
|
{"ECCRC" , 25, 1, 526, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_31" , 26, 6, 526, "RAZ", 1, 1, 0, 0},
|
|
{"ILST" , 0, 24, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCD" , 24, 1, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ACK_NAK" , 25, 1, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_30" , 26, 5, 527, "RAZ", 1, 1, 0, 0},
|
|
{"DLLD" , 31, 1, 527, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NTSS" , 0, 4, 528, "R/W", 0, 0, 10ull, 10ull},
|
|
{"RESERVED_4_7" , 4, 4, 528, "RO", 1, 1, 0, 0},
|
|
{"NSKPS" , 8, 3, 528, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_11_13" , 11, 3, 528, "RAZ", 1, 1, 0, 0},
|
|
{"TMRT" , 14, 5, 528, "R/W", 0, 0, 8ull, 8ull},
|
|
{"TMANLT" , 19, 5, 528, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TMFCWT" , 24, 5, 528, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_31" , 29, 3, 528, "RO", 1, 1, 0, 0},
|
|
{"SKPIV" , 0, 11, 529, "R/W", 0, 0, 1280ull, 1280ull},
|
|
{"RESERVED_11_14" , 11, 4, 529, "RAZ", 1, 1, 0, 0},
|
|
{"DFCWT" , 15, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_FUN" , 16, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_POIS_FILT" , 17, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_BAR_MATCH" , 18, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CFG1_FILT" , 19, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_LK_FILT" , 20, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_TAG_ERR" , 21, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_RID_ERR" , 22, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_FUN_ERR" , 23, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_TC_ERR" , 24, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_ATTR_ERR" , 25, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_LEN_ERR" , 26, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_ECRC_FILT" , 27, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_ECRC_FILT" , 28, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSG_CTRL" , 29, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_IO_FILT" , 30, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CFG0_FILT" , 31, 1, 529, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_VEND0_DRP" , 0, 1, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_VEND1_DRP" , 1, 1, 530, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_31" , 2, 30, 530, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_INFO_L32" , 0, 32, 531, "RO", 0, 0, 0ull, 0ull},
|
|
{"DBG_INFO_U32" , 0, 32, 532, "RO", 0, 0, 0ull, 0ull},
|
|
{"TPDFCC" , 0, 12, 533, "RO", 0, 0, 0ull, 0ull},
|
|
{"TPHFCC" , 12, 8, 533, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 533, "RAZ", 1, 1, 0, 0},
|
|
{"TCDFCC" , 0, 12, 534, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCHFCC" , 12, 8, 534, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 534, "RAZ", 1, 1, 0, 0},
|
|
{"TCDFCC" , 0, 12, 535, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCHFCC" , 12, 8, 535, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 535, "RAZ", 1, 1, 0, 0},
|
|
{"RTLPFCCNR" , 0, 1, 536, "RO", 0, 0, 0ull, 0ull},
|
|
{"TRBNE" , 1, 1, 536, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQNE" , 2, 1, 536, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_31" , 3, 29, 536, "RAZ", 1, 1, 0, 0},
|
|
{"WRR_VC0" , 0, 8, 537, "RO", 0, 0, 15ull, 15ull},
|
|
{"WRR_VC1" , 8, 8, 537, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC2" , 16, 8, 537, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC3" , 24, 8, 537, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC4" , 0, 8, 538, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC5" , 8, 8, 538, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC6" , 16, 8, 538, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC7" , 24, 8, 538, "RO", 0, 0, 0ull, 0ull},
|
|
{"DATA_CREDITS" , 0, 12, 539, "RO/WRSL", 0, 0, 72ull, 72ull},
|
|
{"HEADER_CREDITS" , 12, 8, 539, "RO/WRSL", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_20_20" , 20, 1, 539, "RAZ", 1, 1, 0, 0},
|
|
{"QUEUE_MODE" , 21, 3, 539, "RO/WRSL", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_24_29" , 24, 6, 539, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE_ORDERING" , 30, 1, 539, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"RX_QUEUE_ORDER" , 31, 1, 539, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"DATA_CREDITS" , 0, 12, 540, "RO/WRSL", 0, 0, 4ull, 4ull},
|
|
{"HEADER_CREDITS" , 12, 8, 540, "RO/WRSL", 0, 0, 8ull, 8ull},
|
|
{"RESERVED_20_20" , 20, 1, 540, "RAZ", 1, 1, 0, 0},
|
|
{"QUEUE_MODE" , 21, 3, 540, "RO/WRSL", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_24_31" , 24, 8, 540, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_CREDITS" , 0, 12, 541, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"HEADER_CREDITS" , 12, 8, 541, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 541, "RAZ", 1, 1, 0, 0},
|
|
{"QUEUE_MODE" , 21, 3, 541, "RO/WRSL", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_24_31" , 24, 8, 541, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_DEPTH" , 0, 14, 542, "RO/WRSL", 0, 0, 216ull, 216ull},
|
|
{"RESERVED_14_15" , 14, 2, 542, "RAZ", 1, 1, 0, 0},
|
|
{"HEADER_DEPTH" , 16, 10, 542, "RO/WRSL", 0, 0, 38ull, 38ull},
|
|
{"RESERVED_26_31" , 26, 6, 542, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_DEPTH" , 0, 14, 543, "RO/WRSL", 0, 0, 56ull, 56ull},
|
|
{"RESERVED_14_15" , 14, 2, 543, "RAZ", 1, 1, 0, 0},
|
|
{"HEADER_DEPTH" , 16, 10, 543, "RO/WRSL", 0, 0, 14ull, 14ull},
|
|
{"RESERVED_26_31" , 26, 6, 543, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_DEPTH" , 0, 14, 544, "RO/WRSL", 0, 0, 360ull, 360ull},
|
|
{"RESERVED_14_15" , 14, 2, 544, "RAZ", 1, 1, 0, 0},
|
|
{"HEADER_DEPTH" , 16, 10, 544, "RO/WRSL", 0, 0, 70ull, 70ull},
|
|
{"RESERVED_26_31" , 26, 6, 544, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_STAT" , 0, 32, 545, "RO", 0, 0, 0ull, 0ull},
|
|
{"PHY_CTRL" , 0, 32, 546, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VENDID" , 0, 16, 547, "R/W", 0, 0, 6013ull, 6013ull},
|
|
{"DEVID" , 16, 16, 547, "R/W", 0, 0, 128ull, 128ull},
|
|
{"ISAE" , 0, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSAE" , 1, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ME" , 2, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SCSE" , 3, 1, 548, "RO", 0, 0, 0ull, 0ull},
|
|
{"MWICE" , 4, 1, 548, "RO", 0, 0, 0ull, 0ull},
|
|
{"VPS" , 5, 1, 548, "RO", 0, 0, 0ull, 0ull},
|
|
{"PER" , 6, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDS_WCC" , 7, 1, 548, "RO", 0, 0, 0ull, 0ull},
|
|
{"SEE" , 8, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FBBE" , 9, 1, 548, "RO", 0, 0, 0ull, 0ull},
|
|
{"I_DIS" , 10, 1, 548, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_18" , 11, 8, 548, "RAZ", 1, 1, 0, 0},
|
|
{"I_STAT" , 19, 1, 548, "RO", 0, 0, 0ull, 0ull},
|
|
{"CL" , 20, 1, 548, "RO", 0, 0, 1ull, 1ull},
|
|
{"M66" , 21, 1, 548, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_22" , 22, 1, 548, "RO", 1, 1, 0, 0},
|
|
{"FBB" , 23, 1, 548, "RO", 0, 0, 0ull, 0ull},
|
|
{"MDPE" , 24, 1, 548, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DEVT" , 25, 2, 548, "RO", 0, 0, 0ull, 0ull},
|
|
{"STA" , 27, 1, 548, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTA" , 28, 1, 548, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RMA" , 29, 1, 548, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SSE" , 30, 1, 548, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPE" , 31, 1, 548, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RID" , 0, 8, 549, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PI" , 8, 8, 549, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SC" , 16, 8, 549, "R/W", 0, 0, 48ull, 48ull},
|
|
{"BCC" , 24, 8, 549, "R/W", 0, 0, 11ull, 11ull},
|
|
{"CLS" , 0, 8, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LT" , 8, 8, 550, "RO", 0, 0, 0ull, 0ull},
|
|
{"CHF" , 16, 7, 550, "RO", 0, 0, 1ull, 1ull},
|
|
{"MFD" , 23, 1, 550, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BIST" , 24, 8, 550, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_31" , 0, 32, 551, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 552, "RO", 1, 1, 0, 0},
|
|
{"PBNUM" , 0, 8, 553, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SBNUM" , 8, 8, 553, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SUBBNUM" , 16, 8, 553, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SLT" , 24, 8, 553, "RO", 0, 0, 0ull, 0ull},
|
|
{"IO32A" , 0, 1, 554, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_3" , 1, 3, 554, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LIO_BASE" , 4, 4, 554, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IO32B" , 8, 1, 554, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_9_11" , 9, 3, 554, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LIO_LIMI" , 12, 4, 554, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_20" , 16, 5, 554, "RAZ", 1, 1, 0, 0},
|
|
{"M66" , 21, 1, 554, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_22" , 22, 1, 554, "RO", 1, 1, 0, 0},
|
|
{"FBB" , 23, 1, 554, "RO", 0, 0, 0ull, 0ull},
|
|
{"MDPE" , 24, 1, 554, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DEVT" , 25, 2, 554, "RO", 0, 0, 0ull, 0ull},
|
|
{"STA" , 27, 1, 554, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTA" , 28, 1, 554, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RMA" , 29, 1, 554, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SSE" , 30, 1, 554, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPE" , 31, 1, 554, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_3" , 0, 4, 555, "RO", 1, 1, 0, 0},
|
|
{"MB_ADDR" , 4, 12, 555, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_19" , 16, 4, 555, "RO", 1, 1, 0, 0},
|
|
{"ML_ADDR" , 20, 12, 555, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM64A" , 0, 1, 556, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_3" , 1, 3, 556, "RO", 1, 1, 0, 0},
|
|
{"LMEM_BASE" , 4, 12, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM64B" , 16, 1, 556, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_17_19" , 17, 3, 556, "RO", 1, 1, 0, 0},
|
|
{"LMEM_LIMIT" , 20, 12, 556, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMEM_BASE" , 0, 32, 557, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMEM_LIMIT" , 0, 32, 558, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UIO_BASE" , 0, 16, 559, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UIO_LIMIT" , 16, 16, 559, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP" , 0, 8, 560, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_8_31" , 8, 24, 560, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 561, "RAZ", 1, 1, 0, 0},
|
|
{"IL" , 0, 8, 562, "R/W", 0, 0, 255ull, 255ull},
|
|
{"INTA" , 8, 8, 562, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PERE" , 16, 1, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SEE" , 17, 1, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ISAE" , 18, 1, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VGAE" , 19, 1, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VGA16D" , 20, 1, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAM" , 21, 1, 562, "RO", 0, 0, 0ull, 0ull},
|
|
{"SBRST" , 22, 1, 562, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FBBE" , 23, 1, 562, "RO", 0, 0, 0ull, 0ull},
|
|
{"PDT" , 24, 1, 562, "RO", 0, 0, 0ull, 0ull},
|
|
{"SDT" , 25, 1, 562, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTS" , 26, 1, 562, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTSEES" , 27, 1, 562, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_31" , 28, 4, 562, "RO", 1, 1, 0, 0},
|
|
{"PMCID" , 0, 8, 563, "RO", 0, 0, 1ull, 1ull},
|
|
{"NCP" , 8, 8, 563, "R/W", 0, 0, 80ull, 80ull},
|
|
{"PMSV" , 16, 3, 563, "R/W", 0, 0, 3ull, 3ull},
|
|
{"PME_CLOCK" , 19, 1, 563, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 563, "RAZ", 1, 1, 0, 0},
|
|
{"DSI" , 21, 1, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AUXC" , 22, 3, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"D1S" , 25, 1, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"D2S" , 26, 1, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMES" , 27, 5, 563, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PS" , 0, 2, 564, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 564, "RAZ", 1, 1, 0, 0},
|
|
{"NSR" , 3, 1, 564, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 564, "RAZ", 1, 1, 0, 0},
|
|
{"PMEENS" , 8, 1, 564, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMDS" , 9, 4, 564, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMEDSIA" , 13, 2, 564, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMESS" , 15, 1, 564, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_21" , 16, 6, 564, "RAZ", 1, 1, 0, 0},
|
|
{"BD3H" , 22, 1, 564, "RO", 0, 0, 0ull, 0ull},
|
|
{"BPCCEE" , 23, 1, 564, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMDIA" , 24, 8, 564, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSICID" , 0, 8, 565, "RO", 0, 0, 5ull, 5ull},
|
|
{"NCP" , 8, 8, 565, "R/W", 0, 0, 112ull, 112ull},
|
|
{"MSIEN" , 16, 1, 565, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MMC" , 17, 3, 565, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MME" , 20, 3, 565, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M64" , 23, 1, 565, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_24_31" , 24, 8, 565, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 566, "RAZ", 1, 1, 0, 0},
|
|
{"LMSI" , 2, 30, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSI" , 0, 32, 567, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSIMD" , 0, 16, 568, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_31" , 16, 16, 568, "RAZ", 1, 1, 0, 0},
|
|
{"PCIEID" , 0, 8, 569, "RO", 0, 0, 16ull, 16ull},
|
|
{"NCP" , 8, 8, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCIECV" , 16, 4, 569, "RO", 0, 0, 2ull, 2ull},
|
|
{"DPT" , 20, 4, 569, "RO", 0, 0, 4ull, 4ull},
|
|
{"SI" , 24, 1, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IMN" , 25, 5, 569, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_31" , 30, 2, 569, "RAZ", 1, 1, 0, 0},
|
|
{"MPSS" , 0, 3, 570, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PFS" , 3, 2, 570, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ETFS" , 5, 1, 570, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EL0AL" , 6, 3, 570, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EL1AL" , 9, 3, 570, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_14" , 12, 3, 570, "RAZ", 1, 1, 0, 0},
|
|
{"RBER" , 15, 1, 570, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_16_17" , 16, 2, 570, "RAZ", 1, 1, 0, 0},
|
|
{"CSPLV" , 18, 8, 570, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSPLS" , 26, 2, 570, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_31" , 28, 4, 570, "RAZ", 1, 1, 0, 0},
|
|
{"CE_EN" , 0, 1, 571, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NFE_EN" , 1, 1, 571, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FE_EN" , 2, 1, 571, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UR_EN" , 3, 1, 571, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RO_EN" , 4, 1, 571, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MPS" , 5, 3, 571, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ETF_EN" , 8, 1, 571, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PF_EN" , 9, 1, 571, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AP_EN" , 10, 1, 571, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NS_EN" , 11, 1, 571, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MRRS" , 12, 3, 571, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_15_15" , 15, 1, 571, "RAZ", 1, 1, 0, 0},
|
|
{"CE_D" , 16, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NFE_D" , 17, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FE_D" , 18, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UR_D" , 19, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AP_D" , 20, 1, 571, "RO", 0, 0, 0ull, 0ull},
|
|
{"TP" , 21, 1, 571, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_31" , 22, 10, 571, "RAZ", 1, 1, 0, 0},
|
|
{"MLS" , 0, 4, 572, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MLW" , 4, 6, 572, "R/W", 0, 0, 8ull, 8ull},
|
|
{"ASLPMS" , 10, 2, 572, "R/W", 0, 0, 3ull, 3ull},
|
|
{"L0EL" , 12, 3, 572, "R/W", 0, 0, 6ull, 6ull},
|
|
{"L1EL" , 15, 3, 572, "R/W", 0, 0, 6ull, 6ull},
|
|
{"CPM" , 18, 1, 572, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SDERC" , 19, 1, 572, "RO", 0, 0, 0ull, 0ull},
|
|
{"DLLARC" , 20, 1, 572, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBNC" , 21, 1, 572, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_22_23" , 22, 2, 572, "RAZ", 1, 1, 0, 0},
|
|
{"PNUM" , 24, 8, 572, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ASLPC" , 0, 2, 573, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 573, "RAZ", 1, 1, 0, 0},
|
|
{"RCB" , 3, 1, 573, "R/W", 0, 0, 1ull, 1ull},
|
|
{"LD" , 4, 1, 573, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RL" , 5, 1, 573, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CCC" , 6, 1, 573, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ES" , 7, 1, 573, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECPM" , 8, 1, 573, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HAWD" , 9, 1, 573, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LBM_INT_ENB" , 10, 1, 573, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LAB_INT_ENB" , 11, 1, 573, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_15" , 12, 4, 573, "RAZ", 1, 1, 0, 0},
|
|
{"LS" , 16, 4, 573, "RO", 0, 0, 1ull, 1ull},
|
|
{"NLW" , 20, 6, 573, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_26" , 26, 1, 573, "RAZ", 1, 1, 0, 0},
|
|
{"LT" , 27, 1, 573, "RO", 0, 0, 0ull, 0ull},
|
|
{"SCC" , 28, 1, 573, "R/W", 0, 0, 1ull, 0ull},
|
|
{"DLLA" , 29, 1, 573, "RO", 0, 0, 0ull, 1ull},
|
|
{"LBM" , 30, 1, 573, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LAB" , 31, 1, 573, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ABP" , 0, 1, 574, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCP" , 1, 1, 574, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRLSP" , 2, 1, 574, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AIP" , 3, 1, 574, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PIP" , 4, 1, 574, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HP_S" , 5, 1, 574, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HP_C" , 6, 1, 574, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SP_LV" , 7, 8, 574, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SP_LS" , 15, 2, 574, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EMIP" , 17, 1, 574, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NCCS" , 18, 1, 574, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PS_NUM" , 19, 13, 574, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ABP_EN" , 0, 1, 575, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PF_EN" , 1, 1, 575, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRLS_EN" , 2, 1, 575, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PD_EN" , 3, 1, 575, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CCINT_EN" , 4, 1, 575, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HPINT_EN" , 5, 1, 575, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AIC" , 6, 2, 575, "R/W", 0, 0, 3ull, 3ull},
|
|
{"PIC" , 8, 2, 575, "R/W", 0, 0, 3ull, 3ull},
|
|
{"PCC" , 10, 1, 575, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EMIC" , 11, 1, 575, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLLS_EN" , 12, 1, 575, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 575, "RAZ", 1, 1, 0, 0},
|
|
{"ABP_D" , 16, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PF_D" , 17, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRLS_C" , 18, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PD_C" , 19, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CCINT_D" , 20, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRLSS" , 21, 1, 575, "RO", 0, 0, 0ull, 0ull},
|
|
{"PDS" , 22, 1, 575, "RO", 0, 0, 1ull, 1ull},
|
|
{"EMIS" , 23, 1, 575, "RO", 0, 0, 0ull, 0ull},
|
|
{"DLLS_C" , 24, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_31" , 25, 7, 575, "RAZ", 1, 1, 0, 0},
|
|
{"SECEE" , 0, 1, 576, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SENFEE" , 1, 1, 576, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SEFEE" , 2, 1, 576, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMEIE" , 3, 1, 576, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CRSSVE" , 4, 1, 576, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_15" , 5, 11, 576, "RAZ", 1, 1, 0, 0},
|
|
{"CRSSV" , 16, 1, 576, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 576, "RAZ", 1, 1, 0, 0},
|
|
{"PME_RID" , 0, 16, 577, "RO", 0, 0, 0ull, 0ull},
|
|
{"PME_STAT" , 16, 1, 577, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PME_PEND" , 17, 1, 577, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_31" , 18, 14, 577, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CTRS" , 0, 4, 578, "RO", 0, 0, 0ull, 0ull},
|
|
{"CTDS" , 4, 1, 578, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_5_31" , 5, 27, 578, "RAZ", 1, 1, 0, 0},
|
|
{"CTV" , 0, 4, 579, "RO", 0, 0, 0ull, 0ull},
|
|
{"CTD" , 4, 1, 579, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 579, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 580, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 581, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 582, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 583, "RAZ", 1, 1, 0, 0},
|
|
{"PCIEEC" , 0, 16, 584, "RO", 0, 0, 1ull, 1ull},
|
|
{"CV" , 16, 4, 584, "RO", 0, 0, 1ull, 1ull},
|
|
{"NCO" , 20, 12, 584, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_3" , 0, 4, 585, "RAZ", 1, 1, 0, 0},
|
|
{"DLPES" , 4, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SDES" , 5, 1, 585, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_11" , 6, 6, 585, "RAZ", 1, 1, 0, 0},
|
|
{"PTLPS" , 12, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCPES" , 13, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CTS" , 14, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CAS" , 15, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UCS" , 16, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ROS" , 17, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MTLPS" , 18, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ECRCES" , 19, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"URES" , 20, 1, 585, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 585, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_3" , 0, 4, 586, "RAZ", 1, 1, 0, 0},
|
|
{"DLPEM" , 4, 1, 586, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SDEM" , 5, 1, 586, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_11" , 6, 6, 586, "RAZ", 1, 1, 0, 0},
|
|
{"PTLPM" , 12, 1, 586, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCPEM" , 13, 1, 586, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CTM" , 14, 1, 586, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAM" , 15, 1, 586, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UCM" , 16, 1, 586, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROM" , 17, 1, 586, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MTLPM" , 18, 1, 586, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECRCEM" , 19, 1, 586, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UREM" , 20, 1, 586, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 586, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_3" , 0, 4, 587, "RAZ", 1, 1, 0, 0},
|
|
{"DLPES" , 4, 1, 587, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SDES" , 5, 1, 587, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_11" , 6, 6, 587, "RAZ", 1, 1, 0, 0},
|
|
{"PTLPS" , 12, 1, 587, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCPES" , 13, 1, 587, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTS" , 14, 1, 587, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAS" , 15, 1, 587, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UCS" , 16, 1, 587, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROS" , 17, 1, 587, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MTLPS" , 18, 1, 587, "R/W", 0, 0, 1ull, 1ull},
|
|
{"ECRCES" , 19, 1, 587, "R/W", 0, 0, 0ull, 0ull},
|
|
{"URES" , 20, 1, 587, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 587, "RAZ", 1, 1, 0, 0},
|
|
{"RES" , 0, 1, 588, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_5" , 1, 5, 588, "RAZ", 1, 1, 0, 0},
|
|
{"BTLPS" , 6, 1, 588, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BDLLPS" , 7, 1, 588, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RNRS" , 8, 1, 588, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 588, "RAZ", 1, 1, 0, 0},
|
|
{"RTTS" , 12, 1, 588, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ANFES" , 13, 1, 588, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_31" , 14, 18, 588, "RAZ", 1, 1, 0, 0},
|
|
{"REM" , 0, 1, 589, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_5" , 1, 5, 589, "RAZ", 1, 1, 0, 0},
|
|
{"BTLPM" , 6, 1, 589, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BDLLPM" , 7, 1, 589, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNRM" , 8, 1, 589, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 589, "RAZ", 1, 1, 0, 0},
|
|
{"RTTM" , 12, 1, 589, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ANFEM" , 13, 1, 589, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_14_31" , 14, 18, 589, "RAZ", 1, 1, 0, 0},
|
|
{"FEP" , 0, 5, 590, "RO", 0, 0, 0ull, 0ull},
|
|
{"GC" , 5, 1, 590, "RO", 0, 0, 1ull, 1ull},
|
|
{"GE" , 6, 1, 590, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CC" , 7, 1, 590, "RO", 0, 0, 1ull, 1ull},
|
|
{"CE" , 8, 1, 590, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_31" , 9, 23, 590, "RAZ", 1, 1, 0, 0},
|
|
{"DWORD1" , 0, 32, 591, "RO", 0, 0, 0ull, 0ull},
|
|
{"DWORD2" , 0, 32, 592, "RO", 0, 0, 0ull, 0ull},
|
|
{"DWORD3" , 0, 32, 593, "RO", 0, 0, 0ull, 0ull},
|
|
{"DWORD4" , 0, 32, 594, "RO", 0, 0, 0ull, 0ull},
|
|
{"CERE" , 0, 1, 595, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NFERE" , 1, 1, 595, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FERE" , 2, 1, 595, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_31" , 3, 29, 595, "RAZ", 1, 1, 0, 0},
|
|
{"ECR" , 0, 1, 596, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MULTI_ECR" , 1, 1, 596, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EFNFR" , 2, 1, 596, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MULTI_EFNFR" , 3, 1, 596, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FUF" , 4, 1, 596, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NFEMR" , 5, 1, 596, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FEMR" , 6, 1, 596, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_26" , 7, 20, 596, "RAZ", 1, 1, 0, 0},
|
|
{"AEIMN" , 27, 5, 596, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECSI" , 0, 16, 597, "RO", 0, 0, 0ull, 0ull},
|
|
{"EFNFSI" , 16, 16, 597, "RO", 0, 0, 0ull, 0ull},
|
|
{"RTLTL" , 0, 16, 598, "R/W", 0, 0, 4143ull, 4143ull},
|
|
{"RTL" , 16, 16, 598, "R/W", 0, 0, 12429ull, 12429ull},
|
|
{"OMR" , 0, 32, 599, "R/W", 0, 1, 4294967295ull, 0},
|
|
{"LINK_NUM" , 0, 8, 600, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_8_14" , 8, 7, 600, "RAZ", 1, 1, 0, 0},
|
|
{"FORCE_LINK" , 15, 1, 600, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LINK_STATE" , 16, 6, 600, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 600, "RAZ", 1, 1, 0, 0},
|
|
{"LPEC" , 24, 8, 600, "RO", 0, 0, 7ull, 7ull},
|
|
{"ACK_FREQ" , 0, 8, 601, "R/W", 0, 0, 0ull, 0ull},
|
|
{"N_FTS" , 8, 8, 601, "R/W", 0, 0, 128ull, 128ull},
|
|
{"N_FTS_CC" , 16, 8, 601, "R/W", 0, 0, 128ull, 128ull},
|
|
{"L0EL" , 24, 3, 601, "R/W", 0, 0, 3ull, 3ull},
|
|
{"L1EL" , 27, 3, 601, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_30_31" , 30, 2, 601, "RAZ", 1, 1, 0, 0},
|
|
{"OMR" , 0, 1, 602, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SD" , 1, 1, 602, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LE" , 2, 1, 602, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RA" , 3, 1, 602, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_4" , 4, 1, 602, "RAZ", 1, 1, 0, 0},
|
|
{"DLLLE" , 5, 1, 602, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_6" , 6, 1, 602, "RAZ", 1, 1, 0, 0},
|
|
{"FLM" , 7, 1, 602, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_15" , 8, 8, 602, "RO", 0, 0, 1ull, 1ull},
|
|
{"LME" , 16, 6, 602, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_22_24" , 22, 3, 602, "RAZ", 1, 1, 0, 0},
|
|
{"ECCRC" , 25, 1, 602, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_31" , 26, 6, 602, "RAZ", 1, 1, 0, 0},
|
|
{"ILST" , 0, 24, 603, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCD" , 24, 1, 603, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ACK_NAK" , 25, 1, 603, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_30" , 26, 5, 603, "RAZ", 1, 1, 0, 0},
|
|
{"DLLD" , 31, 1, 603, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NTSS" , 0, 4, 604, "R/W", 0, 0, 10ull, 10ull},
|
|
{"RESERVED_4_7" , 4, 4, 604, "RO", 1, 1, 0, 0},
|
|
{"NSKPS" , 8, 3, 604, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_11_13" , 11, 3, 604, "RAZ", 1, 1, 0, 0},
|
|
{"TMRT" , 14, 5, 604, "R/W", 0, 0, 8ull, 8ull},
|
|
{"TMANLT" , 19, 5, 604, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TMFCWT" , 24, 5, 604, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_31" , 29, 3, 604, "RO", 1, 1, 0, 0},
|
|
{"SKPIV" , 0, 11, 605, "R/W", 0, 0, 1280ull, 1280ull},
|
|
{"RESERVED_11_14" , 11, 4, 605, "RAZ", 1, 1, 0, 0},
|
|
{"DFCWT" , 15, 1, 605, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_FUN" , 16, 1, 605, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_POIS_FILT" , 17, 1, 605, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_BAR_MATCH" , 18, 1, 605, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CFG1_FILT" , 19, 1, 605, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_LK_FILT" , 20, 1, 605, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_TAG_ERR" , 21, 1, 605, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_RID_ERR" , 22, 1, 605, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_FUN_ERR" , 23, 1, 605, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_TC_ERR" , 24, 1, 605, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_ATTR_ERR" , 25, 1, 605, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_LEN_ERR" , 26, 1, 605, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_ECRC_FILT" , 27, 1, 605, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_ECRC_FILT" , 28, 1, 605, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSG_CTRL" , 29, 1, 605, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_IO_FILT" , 30, 1, 605, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CFG0_FILT" , 31, 1, 605, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_VEND0_DRP" , 0, 1, 606, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_VEND1_DRP" , 1, 1, 606, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_31" , 2, 30, 606, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_INFO_L32" , 0, 32, 607, "RO", 0, 0, 0ull, 0ull},
|
|
{"DBG_INFO_U32" , 0, 32, 608, "RO", 0, 0, 0ull, 0ull},
|
|
{"TPDFCC" , 0, 12, 609, "RO", 0, 0, 0ull, 0ull},
|
|
{"TPHFCC" , 12, 8, 609, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 609, "RAZ", 1, 1, 0, 0},
|
|
{"TCDFCC" , 0, 12, 610, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCHFCC" , 12, 8, 610, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 610, "RAZ", 1, 1, 0, 0},
|
|
{"TCDFCC" , 0, 12, 611, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCHFCC" , 12, 8, 611, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 611, "RAZ", 1, 1, 0, 0},
|
|
{"RTLPFCCNR" , 0, 1, 612, "RO", 0, 0, 0ull, 0ull},
|
|
{"TRBNE" , 1, 1, 612, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQNE" , 2, 1, 612, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_31" , 3, 29, 612, "RAZ", 1, 1, 0, 0},
|
|
{"WRR_VC0" , 0, 8, 613, "RO", 0, 0, 15ull, 15ull},
|
|
{"WRR_VC1" , 8, 8, 613, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC2" , 16, 8, 613, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC3" , 24, 8, 613, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC4" , 0, 8, 614, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC5" , 8, 8, 614, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC6" , 16, 8, 614, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC7" , 24, 8, 614, "RO", 0, 0, 0ull, 0ull},
|
|
{"DATA_CREDITS" , 0, 12, 615, "R/W", 0, 0, 72ull, 72ull},
|
|
{"HEADER_CREDITS" , 12, 8, 615, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_20_20" , 20, 1, 615, "RAZ", 1, 1, 0, 0},
|
|
{"QUEUE_MODE" , 21, 3, 615, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_24_29" , 24, 6, 615, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE_ORDERING" , 30, 1, 615, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RX_QUEUE_ORDER" , 31, 1, 615, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DATA_CREDITS" , 0, 12, 616, "R/W", 0, 0, 4ull, 4ull},
|
|
{"HEADER_CREDITS" , 12, 8, 616, "R/W", 0, 0, 8ull, 8ull},
|
|
{"RESERVED_20_20" , 20, 1, 616, "RAZ", 1, 1, 0, 0},
|
|
{"QUEUE_MODE" , 21, 3, 616, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_24_31" , 24, 8, 616, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_CREDITS" , 0, 12, 617, "R/W", 0, 0, 128ull, 128ull},
|
|
{"HEADER_CREDITS" , 12, 8, 617, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_20_20" , 20, 1, 617, "RAZ", 1, 1, 0, 0},
|
|
{"QUEUE_MODE" , 21, 3, 617, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_24_31" , 24, 8, 617, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_DEPTH" , 0, 14, 618, "R/W", 0, 0, 216ull, 216ull},
|
|
{"RESERVED_14_15" , 14, 2, 618, "RAZ", 1, 1, 0, 0},
|
|
{"HEADER_DEPTH" , 16, 10, 618, "R/W", 0, 0, 38ull, 38ull},
|
|
{"RESERVED_26_31" , 26, 6, 618, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_DEPTH" , 0, 14, 619, "R/W", 0, 0, 56ull, 56ull},
|
|
{"RESERVED_14_15" , 14, 2, 619, "RAZ", 1, 1, 0, 0},
|
|
{"HEADER_DEPTH" , 16, 10, 619, "R/W", 0, 0, 14ull, 14ull},
|
|
{"RESERVED_26_31" , 26, 6, 619, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_DEPTH" , 0, 14, 620, "R/W", 0, 0, 360ull, 360ull},
|
|
{"RESERVED_14_15" , 14, 2, 620, "RAZ", 1, 1, 0, 0},
|
|
{"HEADER_DEPTH" , 16, 10, 620, "R/W", 0, 0, 70ull, 70ull},
|
|
{"RESERVED_26_31" , 26, 6, 620, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_STAT" , 0, 32, 621, "RO", 0, 0, 0ull, 0ull},
|
|
{"PHY_CTRL" , 0, 32, 622, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_4" , 0, 5, 623, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FD" , 5, 1, 623, "R/W", 0, 0, 1ull, 1ull},
|
|
{"HFD" , 6, 1, 623, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PAUSE" , 7, 2, 623, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 623, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"REM_FLT" , 12, 2, 623, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_14" , 14, 1, 623, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"NP" , 15, 1, 623, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 623, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_11" , 0, 12, 624, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"THOU_THD" , 12, 1, 624, "RO", 0, 0, 0ull, 0ull},
|
|
{"THOU_TFD" , 13, 1, 624, "RO", 0, 0, 0ull, 0ull},
|
|
{"THOU_XHD" , 14, 1, 624, "RO", 0, 0, 1ull, 1ull},
|
|
{"THOU_XFD" , 15, 1, 624, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_16_63" , 16, 48, 624, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_4" , 0, 5, 625, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FD" , 5, 1, 625, "RO", 0, 0, 0ull, 0ull},
|
|
{"HFD" , 6, 1, 625, "RO", 0, 0, 0ull, 0ull},
|
|
{"PAUSE" , 7, 2, 625, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 625, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"REM_FLT" , 12, 2, 625, "RO", 0, 0, 0ull, 0ull},
|
|
{"ACK" , 14, 1, 625, "RO", 0, 1, 0ull, 0},
|
|
{"NP" , 15, 1, 625, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 625, "RAZ", 1, 1, 0, 0},
|
|
{"LINK_OK" , 0, 1, 626, "RO", 0, 0, 0ull, 0ull},
|
|
{"DUP" , 1, 1, 626, "RO", 0, 0, 0ull, 0ull},
|
|
{"AN_CPT" , 2, 1, 626, "RO", 0, 0, 0ull, 1ull},
|
|
{"SPD" , 3, 2, 626, "RO", 0, 0, 0ull, 0ull},
|
|
{"PAUSE" , 5, 2, 626, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 626, "RAZ", 1, 1, 0, 0},
|
|
{"LNKSPD_EN" , 0, 1, 627, "R/W", 0, 0, 0ull, 1ull},
|
|
{"XMIT_EN" , 1, 1, 627, "R/W", 0, 0, 0ull, 1ull},
|
|
{"AN_ERR_EN" , 2, 1, 627, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXFIFU_EN" , 3, 1, 627, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXFIFO_EN" , 4, 1, 627, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXBAD_EN" , 5, 1, 627, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXERR_EN" , 6, 1, 627, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXBAD_EN" , 7, 1, 627, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXLOCK_EN" , 8, 1, 627, "R/W", 0, 0, 0ull, 1ull},
|
|
{"AN_BAD_EN" , 9, 1, 627, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SYNC_BAD_EN" , 10, 1, 627, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DUP" , 11, 1, 627, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_12_63" , 12, 52, 627, "RAZ", 1, 1, 0, 0},
|
|
{"LNKSPD" , 0, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"XMIT" , 1, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AN_ERR" , 2, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXFIFU" , 3, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXFIFO" , 4, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXBAD" , 5, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXERR" , 6, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXBAD" , 7, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXLOCK" , 8, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AN_BAD" , 9, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SYNC_BAD" , 10, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DUP" , 11, 1, 628, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 628, "RAZ", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 16, 629, "R/W", 0, 1, 1094ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 629, "RAZ", 1, 1, 0, 0},
|
|
{"PKT_SZ" , 0, 2, 630, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LA_EN" , 2, 1, 630, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LAFIFOVFL" , 3, 1, 630, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 630, "RAZ", 1, 1, 0, 0},
|
|
{"SAMP_PT" , 0, 7, 631, "R/W", 0, 1, 1ull, 0},
|
|
{"AN_OVRD" , 7, 1, 631, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MODE" , 8, 1, 631, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAC_PHY" , 9, 1, 631, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LOOPBCK2" , 10, 1, 631, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GMXENO" , 11, 1, 631, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SGMII" , 12, 1, 631, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_13_63" , 13, 51, 631, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_4" , 0, 5, 632, "RAZ", 1, 1, 0, 0},
|
|
{"UNI" , 5, 1, 632, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SPDMSB" , 6, 1, 632, "R/W", 0, 0, 1ull, 1ull},
|
|
{"COLTST" , 7, 1, 632, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DUP" , 8, 1, 632, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RST_AN" , 9, 1, 632, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_10" , 10, 1, 632, "RAZ", 1, 1, 0, 0},
|
|
{"PWR_DN" , 11, 1, 632, "R/W", 0, 0, 1ull, 0ull},
|
|
{"AN_EN" , 12, 1, 632, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SPDLSB" , 13, 1, 632, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LOOPBCK1" , 14, 1, 632, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 15, 1, 632, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 632, "RAZ", 1, 1, 0, 0},
|
|
{"EXTND" , 0, 1, 633, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 633, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LNK_ST" , 2, 1, 633, "RO", 0, 0, 0ull, 1ull},
|
|
{"AN_ABIL" , 3, 1, 633, "RO", 0, 0, 1ull, 1ull},
|
|
{"RM_FLT" , 4, 1, 633, "RO", 0, 0, 0ull, 0ull},
|
|
{"AN_CPT" , 5, 1, 633, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRB_SUP" , 6, 1, 633, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_7_7" , 7, 1, 633, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EXT_ST" , 8, 1, 633, "RO", 0, 0, 1ull, 1ull},
|
|
{"HUN_T2HD" , 9, 1, 633, "RO", 0, 0, 0ull, 0ull},
|
|
{"HUN_T2FD" , 10, 1, 633, "RO", 0, 0, 0ull, 0ull},
|
|
{"TEN_HD" , 11, 1, 633, "RO", 0, 0, 0ull, 0ull},
|
|
{"TEN_FD" , 12, 1, 633, "RO", 0, 0, 0ull, 0ull},
|
|
{"HUN_XHD" , 13, 1, 633, "RO", 0, 0, 0ull, 0ull},
|
|
{"HUN_XFD" , 14, 1, 633, "RO", 0, 0, 0ull, 0ull},
|
|
{"HUN_T4" , 15, 1, 633, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 633, "RAZ", 1, 1, 0, 0},
|
|
{"AN_ST" , 0, 4, 634, "RO", 0, 0, 0ull, 0ull},
|
|
{"AN_BAD" , 4, 1, 634, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYNC" , 5, 4, 634, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYNC_BAD" , 9, 1, 634, "RO", 0, 0, 0ull, 0ull},
|
|
{"RX_ST" , 10, 5, 634, "RO", 0, 0, 0ull, 0ull},
|
|
{"RX_BAD" , 15, 1, 634, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 634, "RAZ", 1, 1, 0, 0},
|
|
{"BIT_LOCK" , 0, 1, 635, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYNC" , 1, 1, 635, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 635, "RAZ", 1, 1, 0, 0},
|
|
{"ONE" , 0, 1, 636, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_9" , 1, 9, 636, "RAZ", 0, 1, 0ull, 0},
|
|
{"SPEED" , 10, 2, 636, "R/W", 0, 0, 2ull, 2ull},
|
|
{"DUP" , 12, 1, 636, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_13_13" , 13, 1, 636, "RAZ", 0, 1, 0ull, 0},
|
|
{"ACK" , 14, 1, 636, "RO", 0, 0, 0ull, 0ull},
|
|
{"LINK" , 15, 1, 636, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_16_63" , 16, 48, 636, "RAZ", 1, 1, 0, 0},
|
|
{"ONE" , 0, 1, 637, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_9" , 1, 9, 637, "RAZ", 0, 1, 0ull, 0},
|
|
{"SPEED" , 10, 2, 637, "RO", 0, 0, 0ull, 2ull},
|
|
{"DUP" , 12, 1, 637, "RO", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_13_14" , 13, 2, 637, "RAZ", 0, 1, 0ull, 0},
|
|
{"LINK" , 15, 1, 637, "RO", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_16_63" , 16, 48, 637, "RAZ", 1, 1, 0, 0},
|
|
{"ORD_ST" , 0, 4, 638, "RO", 0, 0, 0ull, 0ull},
|
|
{"TX_BAD" , 4, 1, 638, "RO", 0, 0, 0ull, 0ull},
|
|
{"XMIT" , 5, 2, 638, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 638, "RAZ", 1, 1, 0, 0},
|
|
{"TXPLRT" , 0, 1, 639, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RXPLRT" , 1, 1, 639, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AUTORXPL" , 2, 1, 639, "RO", 0, 0, 0ull, 0ull},
|
|
{"RXOVRD" , 3, 1, 639, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 639, "RAZ", 1, 1, 0, 0},
|
|
{"L0SYNC" , 0, 1, 640, "RO", 0, 0, 0ull, 1ull},
|
|
{"L1SYNC" , 1, 1, 640, "RO", 0, 0, 0ull, 1ull},
|
|
{"L2SYNC" , 2, 1, 640, "RO", 0, 0, 0ull, 1ull},
|
|
{"L3SYNC" , 3, 1, 640, "RO", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_4_10" , 4, 7, 640, "RAZ", 1, 1, 0, 0},
|
|
{"PATTST" , 11, 1, 640, "RO", 0, 0, 0ull, 0ull},
|
|
{"ALIGND" , 12, 1, 640, "RO", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_13_63" , 13, 51, 640, "RAZ", 1, 1, 0, 0},
|
|
{"BIST_STATUS" , 0, 1, 641, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 641, "RAZ", 1, 1, 0, 0},
|
|
{"BITLCK0" , 0, 1, 642, "RO", 0, 1, 0ull, 0},
|
|
{"BITLCK1" , 1, 1, 642, "RO", 0, 1, 0ull, 0},
|
|
{"BITLCK2" , 2, 1, 642, "RO", 0, 1, 0ull, 0},
|
|
{"BITLCK3" , 3, 1, 642, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 642, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 643, "RAZ", 1, 1, 0, 0},
|
|
{"SPD" , 2, 4, 643, "RO", 0, 0, 0ull, 0ull},
|
|
{"SPDSEL0" , 6, 1, 643, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_7_10" , 7, 4, 643, "RAZ", 1, 1, 0, 0},
|
|
{"LO_PWR" , 11, 1, 643, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_12" , 12, 1, 643, "RAZ", 1, 1, 0, 0},
|
|
{"SPDSEL1" , 13, 1, 643, "RO", 0, 0, 1ull, 1ull},
|
|
{"LOOPBCK1" , 14, 1, 643, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 15, 1, 643, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 643, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 2, 644, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 644, "RAZ", 1, 1, 0, 0},
|
|
{"TXFLT_EN" , 0, 1, 645, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXBAD_EN" , 1, 1, 645, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXSYNBAD_EN" , 2, 1, 645, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BITLCKLS_EN" , 3, 1, 645, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SYNLOS_EN" , 4, 1, 645, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ALGNLOS_EN" , 5, 1, 645, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_6_63" , 6, 58, 645, "RAZ", 1, 1, 0, 0},
|
|
{"TXFLT" , 0, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXBAD" , 1, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXSYNBAD" , 2, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BITLCKLS" , 3, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SYNLOS" , 4, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ALGNLOS" , 5, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 646, "RAZ", 1, 1, 0, 0},
|
|
{"PKT_SZ" , 0, 2, 647, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LA_EN" , 2, 1, 647, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LAFIFOVFL" , 3, 1, 647, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DROP_LN" , 4, 2, 647, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENC_MODE" , 6, 1, 647, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 647, "RAZ", 1, 1, 0, 0},
|
|
{"GMXENO" , 0, 1, 648, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XAUI" , 1, 1, 648, "RO", 1, 1, 0, 0},
|
|
{"RX_SWAP" , 2, 1, 648, "R/W", 0, 1, 0ull, 0},
|
|
{"TX_SWAP" , 3, 1, 648, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 648, "RAZ", 1, 1, 0, 0},
|
|
{"SYNC0ST" , 0, 4, 649, "RO", 0, 1, 0ull, 0},
|
|
{"SYNC1ST" , 4, 4, 649, "RO", 0, 1, 0ull, 0},
|
|
{"SYNC2ST" , 8, 4, 649, "RO", 0, 1, 0ull, 0},
|
|
{"SYNC3ST" , 12, 4, 649, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 649, "RAZ", 1, 1, 0, 0},
|
|
{"TENGB" , 0, 1, 650, "RO", 0, 0, 1ull, 1ull},
|
|
{"TENPASST" , 1, 1, 650, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 650, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 651, "RAZ", 1, 1, 0, 0},
|
|
{"LPABLE" , 1, 1, 651, "RO", 0, 0, 1ull, 1ull},
|
|
{"RCV_LNK" , 2, 1, 651, "RO", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_3_6" , 3, 4, 651, "RAZ", 1, 1, 0, 0},
|
|
{"FLT" , 7, 1, 651, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 651, "RAZ", 1, 1, 0, 0},
|
|
{"TENGB_R" , 0, 1, 652, "RO", 0, 0, 0ull, 0ull},
|
|
{"TENGB_X" , 1, 1, 652, "RO", 0, 0, 1ull, 1ull},
|
|
{"TENGB_W" , 2, 1, 652, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_9" , 3, 7, 652, "RAZ", 1, 1, 0, 0},
|
|
{"RCVFLT" , 10, 1, 652, "RC", 0, 0, 0ull, 0ull},
|
|
{"XMTFLT" , 11, 1, 652, "RC", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_13" , 12, 2, 652, "RAZ", 1, 1, 0, 0},
|
|
{"DEV" , 14, 2, 652, "RO", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_16_63" , 16, 48, 652, "RAZ", 1, 1, 0, 0},
|
|
{"TXPLRT" , 0, 1, 653, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RXPLRT" , 1, 1, 653, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 653, "RAZ", 1, 1, 0, 0},
|
|
{"TX_ST" , 0, 3, 654, "RO", 0, 1, 0ull, 0},
|
|
{"RX_ST" , 3, 2, 654, "RO", 0, 1, 0ull, 0},
|
|
{"ALGN_ST" , 5, 3, 654, "RO", 0, 1, 0ull, 0},
|
|
{"RXBAD" , 8, 1, 654, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYN0BAD" , 9, 1, 654, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYN1BAD" , 10, 1, 654, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYN2BAD" , 11, 1, 654, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYN3BAD" , 12, 1, 654, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 654, "RAZ", 1, 1, 0, 0},
|
|
{"SOT" , 0, 1, 655, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQHDR0" , 1, 1, 655, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQHDR1" , 2, 1, 655, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQDATA4" , 3, 1, 655, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQDATA3" , 4, 1, 655, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQDATA2" , 5, 1, 655, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQDATA1" , 6, 1, 655, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQDATA0" , 7, 1, 655, "RO", 0, 0, 0ull, 0ull},
|
|
{"RETRY" , 8, 1, 655, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTLP_OR" , 9, 1, 655, "RO", 0, 0, 0ull, 0ull},
|
|
{"NTLP_OR" , 10, 1, 655, "RO", 0, 0, 0ull, 0ull},
|
|
{"CTLP_OR" , 11, 1, 655, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 655, "RAZ", 1, 1, 0, 0},
|
|
{"PPF" , 0, 1, 656, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEF_TC0" , 1, 1, 656, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEF_TCF1" , 2, 1, 656, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEF_TNF" , 3, 1, 656, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEF_TPF0" , 4, 1, 656, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEF_TPF1" , 5, 1, 656, "RO", 0, 0, 0ull, 0ull},
|
|
{"RSL_P2E" , 6, 1, 656, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEAI_P2E" , 7, 1, 656, "RO", 0, 0, 0ull, 0ull},
|
|
{"DBG_P2E" , 8, 1, 656, "RO", 0, 0, 0ull, 0ull},
|
|
{"E2P_RSL" , 9, 1, 656, "RO", 0, 0, 0ull, 0ull},
|
|
{"E2P_P" , 10, 1, 656, "RO", 0, 0, 0ull, 0ull},
|
|
{"E2P_N" , 11, 1, 656, "RO", 0, 0, 0ull, 0ull},
|
|
{"E2P_CPL" , 12, 1, 656, "RO", 0, 0, 0ull, 0ull},
|
|
{"CTO_P2E" , 13, 1, 656, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 656, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 32, 657, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 32, 32, 657, "R/W", 0, 1, 0ull, 0},
|
|
{"ADDR" , 0, 32, 658, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 32, 32, 658, "R/W", 0, 1, 0ull, 0},
|
|
{"TAG" , 0, 32, 659, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 659, "RAZ", 1, 1, 0, 0},
|
|
{"INV_LCRC" , 0, 1, 660, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INV_ECRC" , 1, 1, 660, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 660, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RO_CTLP" , 3, 1, 660, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LNK_ENB" , 4, 1, 660, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLY_ONE" , 5, 1, 660, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NF_ECRC" , 6, 1, 660, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_8" , 7, 2, 660, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OB_P_CMD" , 9, 1, 660, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PM_XPME" , 10, 1, 660, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PM_XTOFF" , 11, 1, 660, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LANE_SWP" , 12, 1, 660, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QLM_CFG" , 13, 2, 660, "RO", 1, 1, 0, 0},
|
|
{"PBUS" , 15, 8, 660, "RO", 1, 1, 0, 0},
|
|
{"DNUM" , 23, 5, 660, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_28_63" , 28, 36, 660, "RAZ", 1, 1, 0, 0},
|
|
{"PCIERST" , 0, 1, 661, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 661, "RAZ", 1, 1, 0, 0},
|
|
{"SPOISON" , 0, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTLPMAL" , 1, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTLPLLE" , 2, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RECRCE" , 3, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPOISON" , 4, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RCEMRC" , 5, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RNFEMRC" , 6, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RFEMRC" , 7, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPMERC" , 8, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPTAMRC" , 9, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RUMEP" , 10, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RVDM" , 11, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ACTO" , 12, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTE" , 13, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRE" , 14, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RDWDLE" , 15, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTWDLE" , 16, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPEOOSD" , 17, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCPVWT" , 18, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPE" , 19, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCUV" , 20, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQO" , 21, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RAUC" , 22, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RACUR" , 23, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RACCA" , 24, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CAAR" , 25, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RARWDNS" , 26, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RAMTLP" , 27, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RACPP" , 28, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RAWWPP" , 29, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ECRC_E" , 30, 1, 662, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 662, "RAZ", 1, 1, 0, 0},
|
|
{"SPOISON" , 0, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RTLPMAL" , 1, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RTLPLLE" , 2, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RECRCE" , 3, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RPOISON" , 4, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RCEMRC" , 5, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNFEMRC" , 6, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RFEMRC" , 7, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RPMERC" , 8, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RPTAMRC" , 9, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RUMEP" , 10, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RVDM" , 11, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ACTO" , 12, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RTE" , 13, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRE" , 14, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RDWDLE" , 15, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RTWDLE" , 16, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DPEOOSD" , 17, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCPVWT" , 18, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RPE" , 19, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCUV" , 20, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQO" , 21, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RAUC" , 22, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RACUR" , 23, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RACCA" , 24, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAAR" , 25, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RARWDNS" , 26, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RAMTLP" , 27, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RACPP" , 28, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RAWWPP" , 29, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECRC_E" , 30, 1, 663, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 663, "RAZ", 1, 1, 0, 0},
|
|
{"AUX_EN" , 0, 1, 664, "RO", 0, 0, 0ull, 0ull},
|
|
{"PM_EN" , 1, 1, 664, "RO", 0, 0, 0ull, 0ull},
|
|
{"PM_STAT" , 2, 1, 664, "RO", 0, 0, 0ull, 0ull},
|
|
{"PM_DST" , 3, 1, 664, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 664, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_0_13" , 0, 14, 665, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 14, 50, 665, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_25" , 0, 26, 666, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 26, 38, 666, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_38" , 0, 39, 667, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 39, 25, 667, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_11" , 0, 12, 668, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 12, 52, 668, "R/W", 0, 1, 4503599627370495ull, 0},
|
|
{"RESERVED_0_11" , 0, 12, 669, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 12, 52, 669, "R/W", 0, 1, 4503599627370495ull, 0},
|
|
{"NPEI_P" , 0, 5, 670, "R/W", 0, 0, 2ull, 2ull},
|
|
{"NPEI_NP" , 5, 5, 670, "R/W", 0, 0, 2ull, 2ull},
|
|
{"NPEI_CPL" , 10, 5, 670, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PESC_P" , 15, 5, 670, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PESC_NP" , 20, 5, 670, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PESC_CPL" , 25, 5, 670, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PEAI_PPF" , 30, 8, 670, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_38_63" , 38, 26, 670, "RAZ", 1, 1, 0, 0},
|
|
{"BIST" , 0, 18, 671, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 671, "RAZ", 1, 1, 0, 0},
|
|
{"DPRT" , 0, 16, 672, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UDP" , 16, 1, 672, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP" , 17, 1, 672, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 672, "RAZ", 1, 1, 0, 0},
|
|
{"MAP0" , 0, 4, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP1" , 4, 4, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP2" , 8, 4, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP3" , 12, 4, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP4" , 16, 4, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP5" , 20, 4, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP6" , 24, 4, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP7" , 28, 4, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP8" , 32, 4, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP9" , 36, 4, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP10" , 40, 4, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP11" , 44, 4, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP12" , 48, 4, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP13" , 52, 4, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP14" , 56, 4, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP15" , 60, 4, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP0" , 0, 4, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP1" , 4, 4, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP2" , 8, 4, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP3" , 12, 4, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP4" , 16, 4, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP5" , 20, 4, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP6" , 24, 4, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP7" , 28, 4, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP8" , 32, 4, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP9" , 36, 4, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP10" , 40, 4, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP11" , 44, 4, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP12" , 48, 4, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP13" , 52, 4, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP14" , 56, 4, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP15" , 60, 4, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MINLEN" , 0, 16, 675, "R/W", 0, 0, 64ull, 64ull},
|
|
{"MAXLEN" , 16, 16, 675, "R/W", 0, 0, 1536ull, 1536ull},
|
|
{"RESERVED_32_63" , 32, 32, 675, "RAZ", 1, 1, 0, 0},
|
|
{"NIP_SHF" , 0, 3, 676, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_7" , 3, 5, 676, "RAZ", 1, 1, 0, 0},
|
|
{"RAW_SHF" , 8, 3, 676, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_15" , 11, 5, 676, "RAZ", 1, 1, 0, 0},
|
|
{"MAX_L2" , 16, 1, 676, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_UDP" , 17, 1, 676, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TAG_SYN" , 18, 1, 676, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 676, "RAZ", 1, 1, 0, 0},
|
|
{"IP_CHK" , 0, 1, 677, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP_MAL" , 1, 1, 677, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP_HOP" , 2, 1, 677, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP4_OPTS" , 3, 1, 677, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP6_EEXT" , 4, 2, 677, "R/W", 0, 0, 1ull, 3ull},
|
|
{"RESERVED_6_7" , 6, 2, 677, "RAZ", 1, 1, 0, 0},
|
|
{"L4_MAL" , 8, 1, 677, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_PRT" , 9, 1, 677, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_CHK" , 10, 1, 677, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_LEN" , 11, 1, 677, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TCP_FLAG" , 12, 1, 677, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L2_MAL" , 13, 1, 677, "R/W", 0, 0, 1ull, 1ull},
|
|
{"VS_QOS" , 14, 1, 677, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VS_WQE" , 15, 1, 677, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IGNRS" , 16, 1, 677, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_19" , 17, 3, 677, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RING_EN" , 20, 1, 677, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_23" , 21, 3, 677, "RAZ", 1, 1, 0, 0},
|
|
{"DSA_GRP_SID" , 24, 1, 677, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DSA_GRP_SCMD" , 25, 1, 677, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DSA_GRP_TVID" , 26, 1, 677, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_63" , 27, 37, 677, "RAZ", 1, 1, 0, 0},
|
|
{"PRI" , 0, 6, 678, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_7" , 6, 2, 678, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 8, 3, 678, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_11_11" , 11, 1, 678, "RAZ", 1, 1, 0, 0},
|
|
{"UP_QOS" , 12, 1, 678, "RAZ", 0, 1, 0ull, 0},
|
|
{"RESERVED_13_63" , 13, 51, 678, "RAZ", 1, 1, 0, 0},
|
|
{"PKTDRP" , 0, 1, 679, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 679, "RAZ", 1, 1, 0, 0},
|
|
{"BCKPRS" , 2, 1, 679, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 3, 1, 679, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BADTAG" , 4, 1, 679, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPRUNT" , 5, 1, 679, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TODOOVR" , 6, 1, 679, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FEPERR" , 7, 1, 679, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BEPERR" , 8, 1, 679, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MINERR" , 9, 1, 679, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 10, 1, 679, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 11, 1, 679, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PUNYERR" , 12, 1, 679, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 679, "RAZ", 1, 1, 0, 0},
|
|
{"PKTDRP" , 0, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 680, "RAZ", 1, 1, 0, 0},
|
|
{"BCKPRS" , 2, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 3, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BADTAG" , 4, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPRUNT" , 5, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TODOOVR" , 6, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FEPERR" , 7, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BEPERR" , 8, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MINERR" , 9, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 10, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 11, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PUNYERR" , 12, 1, 680, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 680, "RAZ", 1, 1, 0, 0},
|
|
{"OFFSET" , 0, 3, 681, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 681, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP" , 0, 7, 682, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 682, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 8, 2, 682, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DSA_EN" , 10, 1, 682, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HIGIG_EN" , 11, 1, 682, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CRC_EN" , 12, 1, 682, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 682, "RAZ", 1, 1, 0, 0},
|
|
{"QOS_VLAN" , 16, 1, 682, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS_DIFF" , 17, 1, 682, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS_VOD" , 18, 1, 682, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS_VSEL" , 19, 1, 682, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS_WAT" , 20, 4, 682, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS" , 24, 3, 682, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HG_QOS" , 27, 1, 682, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRP_WAT" , 28, 4, 682, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INST_HDR" , 32, 1, 682, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DYN_RS" , 33, 1, 682, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TAG_INC" , 34, 2, 682, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RAWDRP" , 36, 1, 682, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_39" , 37, 3, 682, "RAZ", 1, 1, 0, 0},
|
|
{"QOS_WAT_47" , 40, 4, 682, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRP_WAT_47" , 44, 4, 682, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MINERR_EN" , 48, 1, 682, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MAXERR_EN" , 49, 1, 682, "R/W", 0, 0, 1ull, 1ull},
|
|
{"LENERR_EN" , 50, 1, 682, "R/W", 0, 0, 1ull, 1ull},
|
|
{"VLAN_LEN" , 51, 1, 682, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PAD_LEN" , 52, 1, 682, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_53_63" , 53, 11, 682, "RAZ", 1, 1, 0, 0},
|
|
{"GRP" , 0, 4, 683, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NON_TAG_TYPE" , 4, 2, 683, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_TAG_TYPE" , 6, 2, 683, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_TAG_TYPE" , 8, 2, 683, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP4_TAG_TYPE" , 10, 2, 683, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP6_TAG_TYPE" , 12, 2, 683, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_SRC_FLAG" , 14, 1, 683, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_SRC_FLAG" , 15, 1, 683, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_DST_FLAG" , 16, 1, 683, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_DST_FLAG" , 17, 1, 683, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_PCTL_FLAG" , 18, 1, 683, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_NXTH_FLAG" , 19, 1, 683, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_SPRT_FLAG" , 20, 1, 683, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_SPRT_FLAG" , 21, 1, 683, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_DPRT_FLAG" , 22, 1, 683, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_DPRT_FLAG" , 23, 1, 683, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_PRT_FLAG" , 24, 1, 683, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_VLAN" , 25, 1, 683, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_VS" , 26, 2, 683, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TAG_MODE" , 28, 2, 683, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAG_MSKIP" , 30, 1, 683, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAG" , 31, 1, 683, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAGMASK" , 32, 4, 683, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAGBASE" , 36, 4, 683, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 683, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 0, 3, 684, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 684, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 0, 3, 685, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 685, "RAZ", 1, 1, 0, 0},
|
|
{"QOS1" , 4, 3, 685, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 685, "RAZ", 1, 1, 0, 0},
|
|
{"MATCH_VALUE" , 0, 16, 686, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MATCH_TYPE" , 16, 3, 686, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_19" , 19, 1, 686, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 20, 3, 686, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 686, "RAZ", 1, 1, 0, 0},
|
|
{"GRP" , 24, 4, 686, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_31" , 28, 4, 686, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 32, 16, 686, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 686, "RAZ", 1, 1, 0, 0},
|
|
{"WORD" , 0, 56, 687, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 687, "RAZ", 1, 1, 0, 0},
|
|
{"RST" , 0, 1, 688, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 688, "RAZ", 1, 1, 0, 0},
|
|
{"DRP_OCTS" , 0, 32, 689, "R/W", 0, 1, 0ull, 0},
|
|
{"DRP_PKTS" , 32, 32, 689, "R/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 690, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 690, "RAZ", 1, 1, 0, 0},
|
|
{"RAW" , 0, 32, 691, "R/W", 0, 1, 0ull, 0},
|
|
{"PKTS" , 32, 32, 691, "R/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 0, 32, 692, "R/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 32, 32, 692, "R/W", 0, 1, 0ull, 0},
|
|
{"H64" , 0, 32, 693, "R/W", 0, 1, 0ull, 0},
|
|
{"H65TO127" , 32, 32, 693, "R/W", 0, 1, 0ull, 0},
|
|
{"H128TO255" , 0, 32, 694, "R/W", 0, 1, 0ull, 0},
|
|
{"H256TO511" , 32, 32, 694, "R/W", 0, 1, 0ull, 0},
|
|
{"H512TO1023" , 0, 32, 695, "R/W", 0, 1, 0ull, 0},
|
|
{"H1024TO1518" , 32, 32, 695, "R/W", 0, 1, 0ull, 0},
|
|
{"H1519" , 0, 32, 696, "R/W", 0, 1, 0ull, 0},
|
|
{"FCS" , 32, 32, 696, "R/W", 0, 1, 0ull, 0},
|
|
{"UNDERSZ" , 0, 32, 697, "R/W", 0, 1, 0ull, 0},
|
|
{"FRAG" , 32, 32, 697, "R/W", 0, 1, 0ull, 0},
|
|
{"OVERSZ" , 0, 32, 698, "R/W", 0, 1, 0ull, 0},
|
|
{"JABBER" , 32, 32, 698, "R/W", 0, 1, 0ull, 0},
|
|
{"RDCLR" , 0, 1, 699, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 699, "RAZ", 1, 1, 0, 0},
|
|
{"ERRS" , 0, 16, 700, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 700, "RAZ", 1, 1, 0, 0},
|
|
{"OCTS" , 0, 48, 701, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 701, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 702, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 702, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 8, 703, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 703, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 0, 16, 704, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 704, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 16, 705, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DST" , 16, 16, 705, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 705, "RAZ", 1, 1, 0, 0},
|
|
{"ENTRY" , 0, 62, 706, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_62_62" , 62, 1, 706, "RAZ", 1, 1, 0, 0},
|
|
{"VAL" , 63, 1, 706, "RO", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 32, 707, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 707, "RAZ", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 48, 708, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 708, "RAZ", 1, 1, 0, 0},
|
|
{"SIZE" , 0, 16, 709, "RO", 1, 0, 0, 0ull},
|
|
{"SEGS" , 16, 6, 709, "RO", 1, 0, 0, 0ull},
|
|
{"CMD" , 22, 14, 709, "RO", 1, 0, 0, 0ull},
|
|
{"FAU" , 36, 28, 709, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 710, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 710, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 710, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 710, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 710, "RO", 1, 0, 0, 0ull},
|
|
{"PTRS2" , 0, 17, 711, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 711, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTRS1" , 32, 17, 711, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 711, "RAZ", 1, 0, 0, 0ull},
|
|
{"MOD" , 0, 3, 712, "RO", 1, 0, 0, 0ull},
|
|
{"CNT" , 3, 13, 712, "RO", 1, 0, 0, 0ull},
|
|
{"CHK" , 16, 1, 712, "RO", 1, 0, 0, 0ull},
|
|
{"LEN" , 17, 1, 712, "RO", 1, 0, 0, 0ull},
|
|
{"SOP" , 18, 1, 712, "RO", 1, 0, 0, 0ull},
|
|
{"UID" , 19, 3, 712, "RO", 1, 0, 0, 0ull},
|
|
{"MAJ" , 22, 1, 712, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 712, "RAZ", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 16, 713, "RO", 1, 0, 0, 0ull},
|
|
{"SEGS" , 16, 6, 713, "RO", 1, 0, 0, 0ull},
|
|
{"CMD" , 22, 14, 713, "RO", 1, 0, 0, 0ull},
|
|
{"FAU" , 36, 28, 713, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 714, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 714, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 714, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 714, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 714, "RO", 1, 0, 0, 0ull},
|
|
{"DATA" , 0, 64, 715, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 716, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 716, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 716, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 716, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 716, "RO", 1, 0, 0, 0ull},
|
|
{"DATA" , 0, 64, 717, "RO", 1, 0, 0, 0ull},
|
|
{"MAJOR" , 0, 3, 718, "RO", 1, 0, 0, 0ull},
|
|
{"MINOR" , 3, 2, 718, "RO", 1, 0, 0, 0ull},
|
|
{"WAIT" , 5, 1, 718, "RO", 1, 0, 0, 0ull},
|
|
{"CHK_MODE" , 6, 1, 718, "RO", 1, 0, 0, 0ull},
|
|
{"CHK_ONCE" , 7, 1, 718, "RO", 1, 0, 0, 0ull},
|
|
{"INIT_DWRITE" , 8, 1, 718, "RO", 1, 0, 0, 0ull},
|
|
{"DREAD_SOP" , 9, 1, 718, "RO", 1, 0, 0, 0ull},
|
|
{"UID" , 10, 2, 718, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_OFF" , 12, 6, 718, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_SIZ" , 18, 16, 718, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_SEGS" , 34, 6, 718, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_OFF" , 40, 16, 718, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_SIZ" , 56, 8, 718, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_SIZ" , 0, 8, 719, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_PTR" , 8, 40, 719, "RO", 1, 0, 0, 0ull},
|
|
{"NXT_INFLT" , 48, 6, 719, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_54_63" , 54, 10, 719, "RAZ", 1, 0, 0, 0ull},
|
|
{"QID_BASE" , 0, 8, 720, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFF" , 8, 4, 720, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFFMAX" , 12, 4, 720, "RO", 1, 0, 0, 0ull},
|
|
{"QCB_RIDX" , 16, 5, 720, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 21, 3, 720, "RO", 1, 0, 0, 0ull},
|
|
{"STATC" , 24, 1, 720, "RO", 1, 0, 0, 0ull},
|
|
{"ACTIVE" , 25, 1, 720, "RO", 1, 0, 0, 0ull},
|
|
{"PREEMPTED" , 26, 1, 720, "RO", 1, 0, 0, 0ull},
|
|
{"PREEMPTEE" , 27, 1, 720, "RO", 1, 0, 0, 0ull},
|
|
{"PREEMPTER" , 28, 1, 720, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFFTHS" , 29, 4, 720, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFFRES" , 33, 4, 720, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 720, "RAZ", 1, 0, 0, 0ull},
|
|
{"QCB_RIDX" , 0, 6, 721, "RO", 1, 0, 0, 0ull},
|
|
{"QCB_WIDX" , 6, 6, 721, "RO", 1, 0, 0, 0ull},
|
|
{"BUF_PTR" , 12, 33, 721, "RO", 1, 0, 0, 0ull},
|
|
{"BUF_SIZ" , 45, 13, 721, "RO", 1, 0, 0, 0ull},
|
|
{"TAIL" , 58, 1, 721, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 59, 5, 721, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 0, 3, 722, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_Q" , 3, 1, 722, "RO", 1, 0, 0, 0ull},
|
|
{"S_TAIL" , 4, 1, 722, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 5, 1, 722, "RO", 1, 0, 0, 0ull},
|
|
{"PREEMPTEE" , 6, 1, 722, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 722, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 8, 20, 722, "RO", 1, 0, 0, 0ull},
|
|
{"PREEMPTER" , 28, 1, 722, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 722, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTRS3" , 0, 17, 723, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 723, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTRS0" , 32, 17, 723, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 723, "RAZ", 1, 0, 0, 0ull},
|
|
{"PID" , 0, 6, 724, "R/W", 1, 0, 0, 0ull},
|
|
{"EID" , 6, 4, 724, "R/W", 1, 0, 0, 0ull},
|
|
{"BP_PORT" , 10, 6, 724, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_16_52" , 16, 37, 724, "RAZ", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 724, "R/W", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 61, 1, 724, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_62_63" , 62, 2, 724, "RAZ", 1, 0, 0, 0ull},
|
|
{"PID" , 0, 6, 725, "R/W", 1, 0, 0, 0ull},
|
|
{"EID" , 6, 4, 725, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_10_52" , 10, 43, 725, "RAZ", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 725, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_61_63" , 61, 3, 725, "RAZ", 1, 0, 0, 0ull},
|
|
{"PID" , 0, 6, 726, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 726, "RAZ", 1, 0, 0, 0ull},
|
|
{"RATE_PKT" , 8, 24, 726, "R/W", 1, 0, 0, 0ull},
|
|
{"RATE_WORD" , 32, 19, 726, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_51_63" , 51, 13, 726, "RAZ", 1, 0, 0, 0ull},
|
|
{"PID" , 0, 6, 727, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 727, "RAZ", 1, 0, 0, 0ull},
|
|
{"RATE_LIM" , 8, 24, 727, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 727, "RAZ", 1, 0, 0, 0ull},
|
|
{"QUEUE" , 0, 7, 728, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT" , 7, 6, 728, "WR0", 1, 0, 0, 0ull},
|
|
{"INDEX" , 13, 3, 728, "WR0", 1, 0, 0, 0ull},
|
|
{"TAIL" , 16, 1, 728, "R/W", 1, 0, 0, 0ull},
|
|
{"BUF_PTR" , 17, 36, 728, "R/W", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 728, "R/W", 1, 0, 0, 0ull},
|
|
{"STATIC_Q" , 61, 1, 728, "R/W", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 62, 1, 728, "R/W", 1, 0, 0, 0ull},
|
|
{"S_TAIL" , 63, 1, 728, "R/W", 1, 0, 0, 0ull},
|
|
{"QID" , 0, 7, 729, "R/W", 1, 0, 0, 0ull},
|
|
{"PID" , 7, 6, 729, "WR0", 1, 0, 0, 0ull},
|
|
{"RESERVED_13_52" , 13, 40, 729, "RAZ", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 729, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_61_63" , 61, 3, 729, "RAZ", 1, 0, 0, 0ull},
|
|
{"DAT_PTR" , 0, 4, 730, "RO", 1, 0, 0, 0ull},
|
|
{"DAT_DAT" , 4, 2, 730, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_CTL" , 6, 2, 730, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_QSB" , 8, 3, 730, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_QCB" , 11, 2, 730, "RO", 1, 0, 0, 0ull},
|
|
{"NCB_INB" , 13, 2, 730, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_PSB" , 15, 8, 730, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_NXT" , 23, 1, 730, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_CHK" , 24, 3, 730, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_WIF" , 27, 1, 730, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_STA" , 28, 1, 730, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_CTL" , 29, 3, 730, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_DAT" , 32, 1, 730, "RO", 1, 0, 0, 0ull},
|
|
{"IOB" , 33, 1, 730, "RO", 1, 0, 0, 0ull},
|
|
{"CSR" , 34, 1, 730, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_35_63" , 35, 29, 730, "RAZ", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 13, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_19" , 13, 7, 731, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 20, 3, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 731, "RAZ", 1, 0, 0, 0ull},
|
|
{"ASSERTS" , 0, 64, 732, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 64, 733, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 64, 734, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 64, 735, "RO", 0, 0, 0ull, 0ull},
|
|
{"ENGINE0" , 0, 4, 736, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE1" , 4, 4, 736, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE2" , 8, 4, 736, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE3" , 12, 4, 736, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE4" , 16, 4, 736, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENGINE5" , 20, 4, 736, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENGINE6" , 24, 4, 736, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENGINE7" , 28, 4, 736, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENGINE8" , 32, 4, 736, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE9" , 36, 4, 736, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_40_63" , 40, 24, 736, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 10, 737, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 737, "RAZ", 1, 0, 0, 0ull},
|
|
{"PARITY" , 0, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 1, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CURRZERO" , 2, 1, 738, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 738, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENA_PKO" , 0, 1, 739, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENA_DWB" , 1, 1, 739, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STORE_BE" , 2, 1, 739, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 3, 1, 739, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 739, "RAZ", 1, 0, 0, 0ull},
|
|
{"MODE0" , 0, 3, 740, "R/W", 0, 0, 2ull, 2ull},
|
|
{"MODE1" , 3, 3, 740, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 740, "RAZ", 1, 0, 0, 0ull},
|
|
{"PARITY" , 0, 1, 741, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 1, 1, 741, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CURRZERO" , 2, 1, 741, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 741, "RAZ", 1, 0, 0, 0ull},
|
|
{"MODE" , 0, 2, 742, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 742, "RAZ", 1, 0, 0, 0ull},
|
|
{"QID7" , 0, 1, 743, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDX3" , 1, 1, 743, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 743, "RAZ", 1, 0, 0, 0ull},
|
|
{"INDEX" , 0, 8, 744, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 8, 8, 744, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 744, "RAZ", 1, 0, 0, 0ull},
|
|
{"ADR" , 0, 1, 745, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEND" , 1, 1, 745, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBR0" , 2, 1, 745, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBR1" , 3, 1, 745, "RO", 0, 0, 0ull, 0ull},
|
|
{"FIDX" , 4, 1, 745, "RO", 0, 0, 0ull, 0ull},
|
|
{"INDEX" , 5, 1, 745, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBT0" , 6, 1, 745, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBT1" , 7, 1, 745, "RO", 0, 0, 0ull, 0ull},
|
|
{"CAM" , 8, 1, 745, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_15" , 9, 7, 745, "RAZ", 1, 1, 0, 0},
|
|
{"PP" , 16, 4, 745, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 745, "RAZ", 1, 1, 0, 0},
|
|
{"DS_PC" , 0, 32, 746, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 746, "RAZ", 1, 1, 0, 0},
|
|
{"SBE" , 0, 1, 747, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DBE" , 1, 1, 747, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SBE_IE" , 2, 1, 747, "R/W", 0, 1, 0ull, 0},
|
|
{"DBE_IE" , 3, 1, 747, "R/W", 0, 1, 0ull, 0},
|
|
{"SYN" , 4, 5, 747, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_9_11" , 9, 3, 747, "RAZ", 1, 1, 0, 0},
|
|
{"RPE" , 12, 1, 747, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPE_IE" , 13, 1, 747, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_15" , 14, 2, 747, "RAZ", 1, 1, 0, 0},
|
|
{"IOP" , 16, 13, 747, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_31" , 29, 3, 747, "RAZ", 1, 1, 0, 0},
|
|
{"IOP_IE" , 32, 13, 747, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_45_63" , 45, 19, 747, "RAZ", 1, 1, 0, 0},
|
|
{"NBR_THR" , 0, 5, 748, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PFR_DIS" , 5, 1, 748, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 748, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 32, 749, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 749, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 32, 750, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 750, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_INT" , 0, 8, 751, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 751, "RAZ", 1, 1, 0, 0},
|
|
{"INT_EN" , 0, 8, 752, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 752, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_THR" , 0, 32, 753, "R/W", 0, 1, 4294967295ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 753, "RAZ", 1, 1, 0, 0},
|
|
{"NOS_CNT" , 0, 10, 754, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_10_63" , 10, 54, 754, "RAZ", 1, 1, 0, 0},
|
|
{"NW_TIM" , 0, 10, 755, "R/W", 0, 0, 0ull, 1023ull},
|
|
{"RESERVED_10_63" , 10, 54, 755, "RAZ", 1, 1, 0, 0},
|
|
{"RST_MSK" , 0, 8, 756, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 756, "RAZ", 1, 1, 0, 0},
|
|
{"GRP_MSK" , 0, 16, 757, "R/W", 0, 0, 65535ull, 65535ull},
|
|
{"QOS0_PRI" , 16, 4, 757, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS1_PRI" , 20, 4, 757, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS2_PRI" , 24, 4, 757, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS3_PRI" , 28, 4, 757, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS4_PRI" , 32, 4, 757, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS5_PRI" , 36, 4, 757, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS6_PRI" , 40, 4, 757, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS7_PRI" , 44, 4, 757, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 757, "RAZ", 1, 1, 0, 0},
|
|
{"RND" , 0, 8, 758, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P1" , 8, 8, 758, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P2" , 16, 8, 758, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P3" , 24, 8, 758, "R/W", 0, 1, 255ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 758, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_THR" , 0, 9, 759, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_9_11" , 9, 3, 759, "RAZ", 1, 1, 0, 0},
|
|
{"MAX_THR" , 12, 9, 759, "R/W", 0, 1, 511ull, 0},
|
|
{"RESERVED_21_23" , 21, 3, 759, "RAZ", 1, 1, 0, 0},
|
|
{"FREE_CNT" , 24, 10, 759, "RO", 0, 1, 503ull, 0},
|
|
{"RESERVED_34_35" , 34, 2, 759, "RAZ", 1, 1, 0, 0},
|
|
{"BUF_CNT" , 36, 10, 759, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_46_47" , 46, 2, 759, "RAZ", 1, 1, 0, 0},
|
|
{"DES_CNT" , 48, 10, 759, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_58_63" , 58, 6, 759, "RAZ", 1, 1, 0, 0},
|
|
{"TS_PC" , 0, 32, 760, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 760, "RAZ", 1, 1, 0, 0},
|
|
{"WA_PC" , 0, 32, 761, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 761, "RAZ", 1, 1, 0, 0},
|
|
{"WA_PC" , 0, 32, 762, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 762, "RAZ", 1, 1, 0, 0},
|
|
{"WQ_INT" , 0, 16, 763, "R/W1C", 0, 1, 0ull, 0},
|
|
{"IQ_DIS" , 16, 16, 763, "R/W1", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 763, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 10, 764, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_10_11" , 10, 2, 764, "RAZ", 1, 1, 0, 0},
|
|
{"DS_CNT" , 12, 10, 764, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_22_23" , 22, 2, 764, "RAZ", 1, 1, 0, 0},
|
|
{"TC_CNT" , 24, 4, 764, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_63" , 28, 36, 764, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 765, "RAZ", 1, 1, 0, 0},
|
|
{"PC_THR" , 8, 20, 765, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_31" , 28, 4, 765, "RAZ", 1, 1, 0, 0},
|
|
{"PC" , 32, 28, 765, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 765, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_THR" , 0, 9, 766, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_9_11" , 9, 3, 766, "RAZ", 1, 1, 0, 0},
|
|
{"DS_THR" , 12, 9, 766, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_21_23" , 21, 3, 766, "RAZ", 1, 1, 0, 0},
|
|
{"TC_THR" , 24, 4, 766, "R/W", 0, 1, 0ull, 0},
|
|
{"TC_EN" , 28, 1, 766, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 766, "RAZ", 1, 1, 0, 0},
|
|
{"WS_PC" , 0, 32, 767, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 767, "RAZ", 1, 1, 0, 0},
|
|
{"IWORD" , 0, 64, 768, "RO", 1, 1, 0, 0},
|
|
{"P_DAT" , 0, 64, 769, "RO", 1, 1, 0, 0},
|
|
{"Q_DAT" , 0, 64, 770, "RO", 1, 1, 0, 0},
|
|
{"DAT" , 0, 2, 771, "RO", 1, 0, 0, 0ull},
|
|
{"NCB_INB" , 2, 2, 771, "RO", 1, 0, 0, 0ull},
|
|
{"NCB_OUB" , 4, 1, 771, "RO", 1, 0, 0, 0ull},
|
|
{"STA" , 5, 1, 771, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 771, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PTR" , 0, 33, 772, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 33, 13, 772, "R/W", 0, 1, 0ull, 0},
|
|
{"POOL" , 46, 3, 772, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB" , 49, 9, 772, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_58_63" , 58, 6, 772, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 0, 1, 773, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STORE_LE" , 1, 1, 773, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAX_READ" , 2, 4, 773, "R/W", 0, 0, 8ull, 8ull},
|
|
{"RESERVED_6_63" , 6, 58, 773, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STATE" , 0, 5, 774, "RO", 1, 1, 0, 0},
|
|
{"COMMIT" , 5, 1, 774, "RO", 1, 1, 0, 0},
|
|
{"OWORDPV" , 6, 1, 774, "RO", 1, 1, 0, 0},
|
|
{"OWORDQV" , 7, 1, 774, "RO", 1, 1, 0, 0},
|
|
{"IWIDX" , 8, 6, 774, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_14_15" , 14, 2, 774, "RAZ", 1, 1, 0, 0},
|
|
{"IRIDX" , 16, 6, 774, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_22_31" , 22, 10, 774, "RAZ", 1, 1, 0, 0},
|
|
{"LOOP" , 32, 25, 774, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_57_63" , 57, 7, 774, "RAZ", 1, 1, 0, 0},
|
|
{"CWORD" , 0, 64, 775, "RO", 1, 1, 0, 0},
|
|
{"PTR" , 0, 40, 776, "RO", 1, 1, 0, 0},
|
|
{"SIZE" , 40, 16, 776, "RO", 1, 1, 0, 0},
|
|
{"FLAGS" , 56, 8, 776, "RO", 1, 1, 0, 0},
|
|
{"INDEX" , 0, 8, 777, "RO", 1, 1, 0, 0},
|
|
{"SOD" , 8, 1, 777, "RO", 1, 1, 0, 0},
|
|
{"EOD" , 9, 1, 777, "RO", 1, 1, 0, 0},
|
|
{"WC" , 10, 1, 777, "RO", 1, 1, 0, 0},
|
|
{"P" , 11, 1, 777, "RO", 1, 1, 0, 0},
|
|
{"Q" , 12, 1, 777, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_13_63" , 13, 51, 777, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 15, 778, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_15_63" , 15, 49, 778, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OWORDP" , 0, 64, 779, "RO", 1, 1, 0, 0},
|
|
{"OWORDQ" , 0, 64, 780, "RO", 1, 1, 0, 0},
|
|
{"RWORD" , 0, 64, 781, "RO", 1, 1, 0, 0},
|
|
{"N0CREDS" , 0, 4, 782, "RO", 0, 0, 8ull, 0ull},
|
|
{"N1CREDS" , 4, 4, 782, "RO", 0, 0, 8ull, 0ull},
|
|
{"POWCREDS" , 8, 2, 782, "RO", 0, 0, 2ull, 0ull},
|
|
{"RESERVED_10_11" , 10, 2, 782, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FPACREDS" , 12, 2, 782, "RO", 0, 0, 1ull, 0ull},
|
|
{"WCCREDS" , 14, 2, 782, "RO", 0, 0, 0ull, 0ull},
|
|
{"NIWIDX0" , 16, 4, 782, "RO", 1, 1, 0, 0},
|
|
{"NIRIDX0" , 20, 4, 782, "RO", 1, 1, 0, 0},
|
|
{"NIWIDX1" , 24, 4, 782, "RO", 1, 1, 0, 0},
|
|
{"NIRIDX1" , 28, 4, 782, "RO", 1, 1, 0, 0},
|
|
{"NIRVAL6" , 32, 5, 782, "RO", 1, 1, 0, 0},
|
|
{"NIRARB6" , 37, 1, 782, "RO", 1, 1, 0, 0},
|
|
{"NIRQUE6" , 38, 2, 782, "RO", 1, 1, 0, 0},
|
|
{"NIROPC6" , 40, 3, 782, "RO", 1, 1, 0, 0},
|
|
{"NIRVAL7" , 43, 5, 782, "RO", 1, 1, 0, 0},
|
|
{"NIRQUE7" , 48, 2, 782, "RO", 1, 1, 0, 0},
|
|
{"NIROPC7" , 50, 3, 782, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_53_63" , 53, 11, 782, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PTR" , 0, 40, 783, "RO", 1, 1, 0, 0},
|
|
{"SIZE" , 40, 16, 783, "RO", 1, 1, 0, 0},
|
|
{"CNT" , 56, 8, 783, "RO", 1, 1, 0, 0},
|
|
{"CNT" , 0, 15, 784, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_15_63" , 15, 49, 784, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PTR" , 0, 40, 785, "RO", 1, 1, 0, 0},
|
|
{"SIZE" , 40, 16, 785, "RO", 1, 1, 0, 0},
|
|
{"FLAGS" , 56, 8, 785, "RO", 1, 1, 0, 0},
|
|
{"INDEX" , 0, 8, 786, "RO", 1, 1, 0, 0},
|
|
{"MUL" , 8, 8, 786, "RO", 1, 1, 0, 0},
|
|
{"P" , 16, 1, 786, "RO", 1, 1, 0, 0},
|
|
{"Q" , 17, 1, 786, "RO", 1, 1, 0, 0},
|
|
{"INI" , 18, 1, 786, "RO", 1, 1, 0, 0},
|
|
{"EOD" , 19, 1, 786, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_20_63" , 20, 44, 786, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 0, 1, 787, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 787, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 0, 1, 788, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 788, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"COEFFS" , 0, 8, 789, "R/W", 0, 0, 29ull, 29ull},
|
|
{"RESERVED_8_63" , 8, 56, 789, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"INDEX" , 0, 16, 790, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 16, 16, 790, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 790, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MEM" , 0, 1, 791, "RO", 0, 0, 0ull, 0ull},
|
|
{"RRC" , 1, 1, 791, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 791, "RAZ", 1, 1, 0, 0},
|
|
{"ENT_EN" , 0, 1, 792, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNG_EN" , 1, 1, 792, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNM_RST" , 2, 1, 792, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNG_RST" , 3, 1, 792, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EXP_ENT" , 4, 1, 792, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENT_SEL" , 5, 4, 792, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 792, "RAZ", 1, 1, 0, 0},
|
|
{"PHASE" , 0, 8, 793, "R/W", 0, 0, 100ull, 100ull},
|
|
{"SAMPLE" , 8, 4, 793, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PREAMBLE" , 12, 1, 793, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CLK_IDLE" , 13, 1, 793, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_14" , 14, 1, 793, "RAZ", 1, 1, 0, 0},
|
|
{"SAMPLE_MODE" , 15, 1, 793, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SAMPLE_HI" , 16, 5, 793, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_23" , 21, 3, 793, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 24, 1, 793, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_63" , 25, 39, 793, "RAZ", 1, 1, 0, 0},
|
|
{"REG_ADR" , 0, 5, 794, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 794, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_ADR" , 8, 5, 794, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_13_15" , 13, 3, 794, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_OP" , 16, 2, 794, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 794, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 795, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 795, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 796, "RO", 0, 1, 0ull, 0},
|
|
{"VAL" , 16, 1, 796, "RO", 0, 1, 0ull, 0},
|
|
{"PENDING" , 17, 1, 796, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 796, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 797, "R/W", 0, 1, 0ull, 0},
|
|
{"VAL" , 16, 1, 797, "RO", 0, 1, 0ull, 0},
|
|
{"PENDING" , 17, 1, 797, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 797, "RAZ", 1, 1, 0, 0},
|
|
{"INTERVAL" , 0, 22, 798, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 798, "RAZ", 1, 0, 0, 0ull},
|
|
{"COUNT" , 24, 22, 798, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_46_46" , 46, 1, 798, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENA" , 47, 1, 798, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 798, "RAZ", 1, 0, 0, 0ull},
|
|
{"BSIZE" , 0, 20, 799, "RO", 1, 0, 0, 0ull},
|
|
{"BASE" , 20, 31, 799, "RO", 1, 0, 0, 0ull},
|
|
{"BUCKET" , 51, 13, 799, "RO", 1, 0, 0, 0ull},
|
|
{"BUCKET" , 0, 7, 800, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 800, "RAZ", 1, 0, 0, 0ull},
|
|
{"CSIZE" , 8, 13, 800, "RO", 1, 0, 0, 0ull},
|
|
{"CPOOL" , 21, 3, 800, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 800, "RAZ", 1, 0, 0, 0ull},
|
|
{"RING" , 0, 4, 801, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NUM_BUCKETS" , 4, 20, 801, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIRST_BUCKET" , 24, 31, 801, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_55_63" , 55, 9, 801, "RAZ", 1, 0, 0, 0ull},
|
|
{"RING" , 0, 4, 802, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTERVAL" , 4, 22, 802, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WORDS_PER_CHUNK" , 26, 13, 802, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 39, 3, 802, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENABLE" , 42, 1, 802, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_43_63" , 43, 21, 802, "RAZ", 1, 0, 0, 0ull},
|
|
{"CTL" , 0, 1, 803, "RO", 1, 0, 0, 0ull},
|
|
{"NCB" , 1, 1, 803, "RO", 1, 0, 0, 0ull},
|
|
{"STA" , 2, 2, 803, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 803, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 16, 804, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 804, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENABLE_TIMERS" , 0, 1, 805, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENABLE_DWB" , 1, 1, 805, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 2, 1, 805, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 805, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 16, 806, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 806, "RAZ", 1, 0, 0, 0ull},
|
|
{"INDEX" , 0, 8, 807, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 8, 8, 807, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 807, "RAZ", 1, 0, 0, 0ull},
|
|
{"TDF0" , 0, 1, 808, "RO", 0, 0, 0ull, 0ull},
|
|
{"TDF1" , 1, 1, 808, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCF" , 2, 1, 808, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 808, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ENA" , 0, 1, 809, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WRAP" , 1, 1, 809, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRIG_CTL" , 2, 2, 809, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIME_GRN" , 4, 3, 809, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FULL_THR" , 7, 2, 809, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CIU_TRG" , 9, 1, 809, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CIU_THR" , 10, 1, 809, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_TRG" , 11, 1, 809, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_THR" , 12, 1, 809, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_ENA" , 13, 1, 809, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IGNORE_O" , 14, 1, 809, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 809, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WPTR" , 0, 8, 810, "RO", 0, 0, 0ull, 0ull},
|
|
{"RPTR" , 8, 8, 810, "RO", 0, 0, 0ull, 0ull},
|
|
{"CYCLES" , 16, 48, 810, "RO", 0, 0, 0ull, 0ull},
|
|
{"WPTR" , 0, 10, 811, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_11" , 10, 2, 811, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RPTR" , 12, 10, 811, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 811, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CYCLES" , 24, 40, 811, "RO", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 812, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 812, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 813, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 813, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 814, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 814, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 814, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 814, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 814, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 814, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 814, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 814, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 814, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 814, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 814, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 814, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 814, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 814, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 814, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 814, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SAA" , 16, 1, 814, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_17_63" , 17, 47, 814, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 815, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 815, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 815, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 815, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 815, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 815, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 815, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 815, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 815, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 815, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 815, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 815, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 816, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 816, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 816, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 816, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 816, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 816, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CIU_TRG" , 0, 1, 817, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CIU_THR" , 1, 1, 817, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MCD0_TRG" , 2, 1, 817, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MCD0_THR" , 3, 1, 817, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 817, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DATA" , 0, 64, 818, "RO", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 819, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 819, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 820, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 820, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 821, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 821, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 821, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 821, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 821, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 821, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 821, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 821, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 821, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 821, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 821, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 821, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 821, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 821, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 821, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 821, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SAA" , 16, 1, 821, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_17_63" , 17, 47, 821, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 822, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 822, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 822, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 822, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 822, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 822, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 822, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 822, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 822, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 822, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 822, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 822, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 823, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 823, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 823, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 823, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 823, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 823, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 824, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 824, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 825, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 825, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 826, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 826, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 826, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 826, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 826, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 826, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 826, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 826, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 826, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 826, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 826, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 826, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 826, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 826, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 826, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 826, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SAA" , 16, 1, 826, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_17_63" , 17, 47, 826, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 827, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 827, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 827, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 827, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 827, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 827, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 827, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 827, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 827, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 827, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 827, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 827, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 828, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 828, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 828, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 828, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 828, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 828, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"INEPINT" , 0, 16, 829, "RO", 0, 0, 0ull, 0ull},
|
|
{"OUTEPINT" , 16, 16, 829, "RO", 0, 0, 0ull, 0ull},
|
|
{"INEPMSK" , 0, 16, 830, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OUTEPMSK" , 16, 16, 830, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DEVSPD" , 0, 2, 831, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NZSTSOUTHSHK" , 2, 1, 831, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 831, "RAZ", 1, 1, 0, 0},
|
|
{"DEVADDR" , 4, 7, 831, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PERFRINT" , 11, 2, 831, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_17" , 13, 5, 831, "RAZ", 1, 1, 0, 0},
|
|
{"EPMISCNT" , 18, 5, 831, "R/W", 0, 0, 8ull, 0ull},
|
|
{"RESERVED_23_31" , 23, 9, 831, "RAZ", 1, 1, 0, 0},
|
|
{"RMTWKUPSIG" , 0, 1, 832, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SFTDISCON" , 1, 1, 832, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GNPINNAKSTS" , 2, 1, 832, "RO", 0, 0, 0ull, 0ull},
|
|
{"GOUTNAKSTS" , 3, 1, 832, "RO", 0, 0, 0ull, 0ull},
|
|
{"TSTCTL" , 4, 3, 832, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SGNPINNAK" , 7, 1, 832, "WO", 0, 0, 0ull, 0ull},
|
|
{"CGNPINNAK" , 8, 1, 832, "WO", 0, 0, 0ull, 0ull},
|
|
{"SGOUTNAK" , 9, 1, 832, "WO", 0, 0, 0ull, 0ull},
|
|
{"CGOUTNAK" , 10, 1, 832, "WO", 0, 0, 0ull, 0ull},
|
|
{"PWRONPRGDONE" , 11, 1, 832, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_31" , 12, 20, 832, "RAZ", 1, 1, 0, 0},
|
|
{"MPS" , 0, 11, 833, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NEXTEP" , 11, 4, 833, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBACTEP" , 15, 1, 833, "R/W", 0, 0, 1ull, 0ull},
|
|
{"DPID" , 16, 1, 833, "RO", 0, 0, 0ull, 0ull},
|
|
{"NAKSTS" , 17, 1, 833, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTYPE" , 18, 2, 833, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 833, "RAZ", 1, 1, 0, 0},
|
|
{"STALL" , 21, 1, 833, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFNUM" , 22, 4, 833, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNAK" , 26, 1, 833, "WO", 0, 0, 0ull, 0ull},
|
|
{"SNAK" , 27, 1, 833, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD0PID" , 28, 1, 833, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD1PID" , 29, 1, 833, "WO", 0, 0, 0ull, 0ull},
|
|
{"EPDIS" , 30, 1, 833, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPENA" , 31, 1, 833, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XFERCOMPL" , 0, 1, 834, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLD" , 1, 1, 834, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AHBERR" , 2, 1, 834, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TIMEOUT" , 3, 1, 834, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTKNTXFEMP" , 4, 1, 834, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTKNEPMIS" , 5, 1, 834, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INEPNAKEFF" , 6, 1, 834, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_31" , 7, 25, 834, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPLMSK" , 0, 1, 835, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLDMSK" , 1, 1, 835, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AHBERRMSK" , 2, 1, 835, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMEOUTMSK" , 3, 1, 835, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTKNTXFEMPMSK" , 4, 1, 835, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTKNEPMISMSK" , 5, 1, 835, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INEPNAKEFFMSK" , 6, 1, 835, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_31" , 7, 25, 835, "RAZ", 1, 1, 0, 0},
|
|
{"XFERSIZE" , 0, 19, 836, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKTCNT" , 19, 10, 836, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MC" , 29, 2, 836, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_31" , 31, 1, 836, "RAZ", 1, 1, 0, 0},
|
|
{"MPS" , 0, 11, 837, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_14" , 11, 4, 837, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"USBACTEP" , 15, 1, 837, "R/W", 0, 0, 1ull, 0ull},
|
|
{"DPID" , 16, 1, 837, "RO", 0, 0, 0ull, 0ull},
|
|
{"NAKSTS" , 17, 1, 837, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTYPE" , 18, 2, 837, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SNP" , 20, 1, 837, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STALL" , 21, 1, 837, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_25" , 22, 4, 837, "RAZ", 1, 1, 0, 0},
|
|
{"CNAK" , 26, 1, 837, "WO", 0, 0, 0ull, 0ull},
|
|
{"SNAK" , 27, 1, 837, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD0PID" , 28, 1, 837, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD1PID" , 29, 1, 837, "WO", 0, 0, 0ull, 0ull},
|
|
{"EPDIS" , 30, 1, 837, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPENA" , 31, 1, 837, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XFERCOMPL" , 0, 1, 838, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLD" , 1, 1, 838, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AHBERR" , 2, 1, 838, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SETUP" , 3, 1, 838, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OUTTKNEPDIS" , 4, 1, 838, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 838, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPLMSK" , 0, 1, 839, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLDMSK" , 1, 1, 839, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AHBERRMSK" , 2, 1, 839, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SETUPMSK" , 3, 1, 839, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OUTTKNEPDISMSK" , 4, 1, 839, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 839, "RAZ", 1, 1, 0, 0},
|
|
{"XFERSIZE" , 0, 19, 840, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKTCNT" , 19, 10, 840, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MC" , 29, 2, 840, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_31" , 31, 1, 840, "RAZ", 1, 1, 0, 0},
|
|
{"DPTXFSTADDR" , 0, 16, 841, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPTXFSIZE" , 16, 16, 841, "RO", 0, 0, 1896ull, 1896ull},
|
|
{"SUSPSTS" , 0, 1, 842, "RO", 0, 0, 0ull, 0ull},
|
|
{"ENUMSPD" , 1, 2, 842, "RO", 0, 0, 0ull, 0ull},
|
|
{"ERRTICERR" , 3, 1, 842, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 842, "RAZ", 1, 1, 0, 0},
|
|
{"SOFFN" , 8, 14, 842, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_31" , 22, 10, 842, "RAZ", 1, 1, 0, 0},
|
|
{"INTKNWPTR" , 0, 5, 843, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_6" , 5, 2, 843, "RAZ", 1, 1, 0, 0},
|
|
{"WRAPBIT" , 7, 1, 843, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 8, 24, 843, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 0, 32, 844, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 0, 32, 845, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 0, 32, 846, "RO", 0, 0, 0ull, 0ull},
|
|
{"GLBLINTRMSK" , 0, 1, 847, "R/W", 0, 0, 0ull, 1ull},
|
|
{"HBSTLEN" , 1, 4, 847, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMAEN" , 5, 1, 847, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_6" , 6, 1, 847, "RAZ", 1, 1, 0, 0},
|
|
{"NPTXFEMPLVL" , 7, 1, 847, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PTXFEMPLVL" , 8, 1, 847, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_9_31" , 9, 23, 847, "RAZ", 1, 1, 0, 0},
|
|
{"EPDIR" , 0, 32, 848, "RO", 0, 0, 0ull, 0ull},
|
|
{"OTGMODE" , 0, 3, 849, "RO", 0, 0, 2ull, 2ull},
|
|
{"OTGARCH" , 3, 2, 849, "RO", 0, 0, 1ull, 1ull},
|
|
{"SINGPNT" , 5, 1, 849, "RO", 0, 0, 0ull, 0ull},
|
|
{"HSPHYTYPE" , 6, 2, 849, "RO", 0, 0, 1ull, 1ull},
|
|
{"FSPHYTYPE" , 8, 2, 849, "RO", 0, 0, 0ull, 0ull},
|
|
{"NUMDEVEPS" , 10, 4, 849, "RO", 0, 0, 4ull, 4ull},
|
|
{"NUMHSTCHNL" , 14, 4, 849, "RO", 0, 0, 7ull, 7ull},
|
|
{"PERIOSUPPORT" , 18, 1, 849, "RO", 0, 0, 1ull, 1ull},
|
|
{"DYNFIFOSIZING" , 19, 1, 849, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_20_21" , 20, 2, 849, "RAZ", 1, 1, 0, 0},
|
|
{"NPTXQDEPTH" , 22, 2, 849, "RO", 0, 0, 2ull, 2ull},
|
|
{"PTXQDEPTH" , 24, 2, 849, "RO", 0, 0, 2ull, 2ull},
|
|
{"TKNQDEPTH" , 26, 5, 849, "RO", 0, 0, 30ull, 30ull},
|
|
{"RESERVED_31_31" , 31, 1, 849, "RAZ", 1, 1, 0, 0},
|
|
{"XFERSIZEWIDTH" , 0, 4, 850, "RO", 0, 0, 8ull, 8ull},
|
|
{"PKTSIZEWIDTH" , 4, 3, 850, "RO", 0, 0, 6ull, 6ull},
|
|
{"OTGEN" , 7, 1, 850, "RO", 0, 0, 1ull, 1ull},
|
|
{"I2C_SELECTION" , 8, 1, 850, "RO", 0, 0, 0ull, 0ull},
|
|
{"VENDOR_CONTROL_INTERFACE_SUPPORT", 9, 1, 850, "RO", 0, 0, 0ull, 0ull},
|
|
{"OPTFEATURE" , 10, 1, 850, "RO", 0, 0, 1ull, 1ull},
|
|
{"RSTTYPE" , 11, 1, 850, "RO", 0, 0, 0ull, 0ull},
|
|
{"AHBPHYSYNC" , 12, 1, 850, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 850, "RAZ", 1, 1, 0, 0},
|
|
{"DFIFODEPTH" , 16, 16, 850, "RO", 0, 0, 1824ull, 1824ull},
|
|
{"NUMDEVPERIOEPS" , 0, 4, 851, "RO", 0, 0, 4ull, 4ull},
|
|
{"ENABLEPWROPT" , 4, 1, 851, "RO", 0, 0, 0ull, 0ull},
|
|
{"AHBFREQ" , 5, 1, 851, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_13" , 6, 8, 851, "RAZ", 1, 1, 0, 0},
|
|
{"PHYDATAWIDTH" , 14, 2, 851, "RO", 0, 0, 1ull, 1ull},
|
|
{"NUMCTLEPS" , 16, 4, 851, "RO", 0, 0, 4ull, 4ull},
|
|
{"IDDGFLTR" , 20, 1, 851, "RO", 0, 0, 1ull, 1ull},
|
|
{"VBUSVALIDFLTR" , 21, 1, 851, "RO", 0, 0, 1ull, 1ull},
|
|
{"AVALIDFLTR" , 22, 1, 851, "RO", 0, 0, 0ull, 0ull},
|
|
{"BVALIDFLTR" , 23, 1, 851, "RO", 0, 0, 0ull, 0ull},
|
|
{"SESSENDFLTR" , 24, 1, 851, "RO", 0, 0, 0ull, 0ull},
|
|
{"ENDEDTRFIFO" , 25, 1, 851, "RO", 0, 0, 0ull, 0ull},
|
|
{"NUMDEVMODINEND" , 26, 4, 851, "RO", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_30_31" , 30, 2, 851, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 852, "RAZ", 1, 1, 0, 0},
|
|
{"MODEMISMSK" , 1, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OTGINTMSK" , 2, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SOFMSK" , 3, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RXFLVLMSK" , 4, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NPTXFEMPMSK" , 5, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GINNAKEFFMSK" , 6, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GOUTNAKEFFMSK" , 7, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ULPICKINTMSK" , 8, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"I2CINT" , 9, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ERLYSUSPMSK" , 10, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBSUSPMSK" , 11, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBRSTMSK" , 12, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENUMDONEMSK" , 13, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ISOOUTDROPMSK" , 14, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EOPFMSK" , 15, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 852, "RAZ", 1, 1, 0, 0},
|
|
{"EPMISMSK" , 17, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INEPINTMSK" , 18, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OEPINTMSK" , 19, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INCOMPISOINMSK" , 20, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INCOMPLPMSK" , 21, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FETSUSPMSK" , 22, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 852, "RAZ", 1, 1, 0, 0},
|
|
{"PRTINTMSK" , 24, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HCHINTMSK" , 25, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PTXFEMPMSK" , 26, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 852, "RAZ", 1, 1, 0, 0},
|
|
{"CONIDSTSCHNGMSK" , 28, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DISCONNINTMSK" , 29, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SESSREQINTMSK" , 30, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WKUPINTMSK" , 31, 1, 852, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CURMOD" , 0, 1, 853, "RO", 0, 0, 0ull, 0ull},
|
|
{"MODEMIS" , 1, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OTGINT" , 2, 1, 853, "RO", 0, 0, 0ull, 0ull},
|
|
{"SOF" , 3, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXFLVL" , 4, 1, 853, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPTXFEMP" , 5, 1, 853, "RO", 0, 0, 0ull, 0ull},
|
|
{"GINNAKEFF" , 6, 1, 853, "RO", 0, 0, 0ull, 0ull},
|
|
{"GOUTNAKEFF" , 7, 1, 853, "RO", 0, 0, 0ull, 0ull},
|
|
{"ULPICKINT" , 8, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I2CINT" , 9, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ERLYSUSP" , 10, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USBSUSP" , 11, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USBRST" , 12, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ENUMDONE" , 13, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ISOOUTDROP" , 14, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EOPF" , 15, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 853, "RAZ", 1, 1, 0, 0},
|
|
{"EPMIS" , 17, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IEPINT" , 18, 1, 853, "RO", 0, 0, 0ull, 0ull},
|
|
{"OEPINT" , 19, 1, 853, "RO", 0, 0, 0ull, 0ull},
|
|
{"INCOMPISOIN" , 20, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INCOMPLP" , 21, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FETSUSP" , 22, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 853, "RAZ", 1, 1, 0, 0},
|
|
{"PRTINT" , 24, 1, 853, "RO", 0, 0, 0ull, 0ull},
|
|
{"HCHINT" , 25, 1, 853, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTXFEMP" , 26, 1, 853, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 853, "RAZ", 1, 1, 0, 0},
|
|
{"CONIDSTSCHNG" , 28, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DISCONNINT" , 29, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SESSREQINT" , 30, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WKUPINT" , 31, 1, 853, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NPTXFSTADDR" , 0, 16, 854, "R/W", 0, 0, 1824ull, 456ull},
|
|
{"NPTXFDEP" , 16, 16, 854, "R/W", 0, 0, 1824ull, 912ull},
|
|
{"NPTXFSPCAVAIL" , 0, 16, 855, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPTXQSPCAVAIL" , 16, 8, 855, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPTXQTOP" , 24, 7, 855, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_31" , 31, 1, 855, "RAZ", 1, 1, 0, 0},
|
|
{"SESREQSCS" , 0, 1, 856, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SESREQ" , 1, 1, 856, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_7" , 2, 6, 856, "RAZ", 1, 1, 0, 0},
|
|
{"HSTNEGSCS" , 8, 1, 856, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HNPREQ" , 9, 1, 856, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HSTSETHNPEN" , 10, 1, 856, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DEVHNPEN" , 11, 1, 856, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_15" , 12, 4, 856, "RAZ", 1, 1, 0, 0},
|
|
{"CONIDSTS" , 16, 1, 856, "RO", 1, 1, 0, 0},
|
|
{"DBNCTIME" , 17, 1, 856, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASESVLD" , 18, 1, 856, "RO", 1, 1, 0, 0},
|
|
{"BSESVLD" , 19, 1, 856, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_20_31" , 20, 12, 856, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 857, "RAZ", 1, 1, 0, 0},
|
|
{"SESENDDET" , 2, 1, 857, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_7" , 3, 5, 857, "RAZ", 1, 1, 0, 0},
|
|
{"SESREQSUCSTSCHNG" , 8, 1, 857, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"HSTNEGSUCSTSCHNG" , 9, 1, 857, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_16" , 10, 7, 857, "RAZ", 1, 1, 0, 0},
|
|
{"HSTNEGDET" , 17, 1, 857, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ADEVTOUTCHG" , 18, 1, 857, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DBNCEDONE" , 19, 1, 857, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 857, "RAZ", 1, 1, 0, 0},
|
|
{"CSFTRST" , 0, 1, 858, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HSFTRST" , 1, 1, 858, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMCNTRRST" , 2, 1, 858, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTKNQFLSH" , 3, 1, 858, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RXFFLSH" , 4, 1, 858, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFFLSH" , 5, 1, 858, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFNUM" , 6, 5, 858, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_29" , 11, 19, 858, "RAZ", 1, 1, 0, 0},
|
|
{"DMAREQ" , 30, 1, 858, "RO", 0, 0, 0ull, 0ull},
|
|
{"AHBIDLE" , 31, 1, 858, "RO", 0, 0, 1ull, 1ull},
|
|
{"RXFDEP" , 0, 16, 859, "R/W", 0, 0, 1824ull, 456ull},
|
|
{"RESERVED_16_31" , 16, 16, 859, "RAZ", 1, 1, 0, 0},
|
|
{"EPNUM" , 0, 4, 860, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 860, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 860, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 860, "RO", 0, 0, 0ull, 0ull},
|
|
{"FN" , 21, 4, 860, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_31" , 25, 7, 860, "RAZ", 1, 1, 0, 0},
|
|
{"CHNUM" , 0, 4, 861, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 861, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 861, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 861, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 861, "RAZ", 1, 1, 0, 0},
|
|
{"EPNUM" , 0, 4, 862, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 862, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 862, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 862, "RO", 0, 0, 0ull, 0ull},
|
|
{"FN" , 21, 4, 862, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_31" , 25, 7, 862, "RAZ", 1, 1, 0, 0},
|
|
{"CHNUM" , 0, 4, 863, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 863, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 863, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 863, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 863, "RAZ", 1, 1, 0, 0},
|
|
{"SYNOPSYSID" , 0, 32, 864, "RO", 1, 1, 0, 0},
|
|
{"TOUTCAL" , 0, 3, 865, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHYIF" , 3, 1, 865, "RO", 0, 0, 1ull, 1ull},
|
|
{"ULPI_UTMI_SEL" , 4, 1, 865, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSINTF" , 5, 1, 865, "WO", 0, 0, 0ull, 0ull},
|
|
{"PHYSEL" , 6, 1, 865, "WO", 0, 0, 0ull, 0ull},
|
|
{"DDRSEL" , 7, 1, 865, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SRPCAP" , 8, 1, 865, "RO", 0, 0, 0ull, 0ull},
|
|
{"HNPCAP" , 9, 1, 865, "RO", 0, 0, 0ull, 0ull},
|
|
{"USBTRDTIM" , 10, 4, 865, "R/W", 0, 0, 5ull, 5ull},
|
|
{"RESERVED_14_14" , 14, 1, 865, "RAZ", 1, 1, 0, 0},
|
|
{"PHYLPWRCLKSEL" , 15, 1, 865, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OTGI2CSEL" , 16, 1, 865, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 865, "RAZ", 1, 1, 0, 0},
|
|
{"HAINT" , 0, 16, 866, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_31" , 16, 16, 866, "RAZ", 1, 1, 0, 0},
|
|
{"HAINTMSK" , 0, 16, 867, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_31" , 16, 16, 867, "RAZ", 1, 1, 0, 0},
|
|
{"MPS" , 0, 11, 868, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPNUM" , 11, 4, 868, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPDIR" , 15, 1, 868, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 868, "RAZ", 1, 1, 0, 0},
|
|
{"LSPDDEV" , 17, 1, 868, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPTYPE" , 18, 2, 868, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EC" , 20, 2, 868, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DEVADDR" , 22, 7, 868, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ODDFRM" , 29, 1, 868, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHDIS" , 30, 1, 868, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHENA" , 31, 1, 868, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSLSPCLKSEL" , 0, 2, 869, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSLSSUPP" , 2, 1, 869, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_31" , 3, 29, 869, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPL" , 0, 1, 870, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CHHLTD" , 1, 1, 870, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AHBERR" , 2, 1, 870, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"STALL" , 3, 1, 870, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NAK" , 4, 1, 870, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ACK" , 5, 1, 870, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NYET" , 6, 1, 870, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"XACTERR" , 7, 1, 870, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BBLERR" , 8, 1, 870, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FRMOVRUN" , 9, 1, 870, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DATATGLERR" , 10, 1, 870, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_31" , 11, 21, 870, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPLMSK" , 0, 1, 871, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHHLTDMSK" , 1, 1, 871, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AHBERRMSK" , 2, 1, 871, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STALLMSK" , 3, 1, 871, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NAKMSK" , 4, 1, 871, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ACKMSK" , 5, 1, 871, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NYETMSK" , 6, 1, 871, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XACTERRMSK" , 7, 1, 871, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BBLERRMSK" , 8, 1, 871, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMOVRUNMSK" , 9, 1, 871, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DATATGLERRMSK" , 10, 1, 871, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_31" , 11, 21, 871, "RAZ", 1, 1, 0, 0},
|
|
{"PRTADDR" , 0, 7, 872, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HUBADDR" , 7, 7, 872, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XACTPOS" , 14, 2, 872, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COMPSPLT" , 16, 1, 872, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_30" , 17, 14, 872, "RAZ", 1, 1, 0, 0},
|
|
{"SPLTENA" , 31, 1, 872, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XFERSIZE" , 0, 19, 873, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKTCNT" , 19, 10, 873, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PID" , 29, 2, 873, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DOPNG" , 31, 1, 873, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRINT" , 0, 16, 874, "R/W", 0, 0, 2959ull, 3750ull},
|
|
{"RESERVED_16_31" , 16, 16, 874, "RAZ", 1, 1, 0, 0},
|
|
{"FRNUM" , 0, 16, 875, "RO", 0, 0, 16383ull, 0ull},
|
|
{"FRREM" , 16, 16, 875, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTCONNSTS" , 0, 1, 876, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTCONNDET" , 1, 1, 876, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTENA" , 2, 1, 876, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTENCHNG" , 3, 1, 876, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTOVRCURRACT" , 4, 1, 876, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTOVRCURRCHNG" , 5, 1, 876, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTRES" , 6, 1, 876, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTSUSP" , 7, 1, 876, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTRST" , 8, 1, 876, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 876, "RAZ", 1, 1, 0, 0},
|
|
{"PRTLNSTS" , 10, 2, 876, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTPWR" , 12, 1, 876, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTTSTCTL" , 13, 4, 876, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTSPD" , 17, 2, 876, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_31" , 19, 13, 876, "RAZ", 1, 1, 0, 0},
|
|
{"PTXFSTADDR" , 0, 16, 877, "R/W", 0, 0, 3648ull, 912ull},
|
|
{"PTXFSIZE" , 16, 16, 877, "R/W", 0, 0, 256ull, 456ull},
|
|
{"PTXFSPCAVAIL" , 0, 16, 878, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTXQSPCAVAIL" , 16, 8, 878, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTXQTOP" , 24, 8, 878, "RO", 0, 0, 0ull, 0ull},
|
|
{"DATA" , 0, 32, 879, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STOPPCLK" , 0, 1, 880, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GATEHCLK" , 1, 1, 880, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PWRCLMP" , 2, 1, 880, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSTPDWNMODULE" , 3, 1, 880, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHYSUSPENDED" , 4, 1, 880, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 880, "RAZ", 1, 1, 0, 0},
|
|
{"NOF_BIS" , 0, 1, 881, "RO", 0, 0, 0ull, 0ull},
|
|
{"NIF_BIS" , 1, 1, 881, "RO", 0, 0, 0ull, 0ull},
|
|
{"USBC_BIS" , 2, 1, 881, "RO", 0, 0, 0ull, 0ull},
|
|
{"N2UF_BIS" , 3, 1, 881, "RO", 0, 0, 0ull, 0ull},
|
|
{"E2HC_BIS" , 4, 1, 881, "RO", 0, 0, 0ull, 0ull},
|
|
{"U2NF_BIS" , 5, 1, 881, "RO", 0, 0, 0ull, 0ull},
|
|
{"U2NC_BIS" , 6, 1, 881, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 881, "RAZ", 1, 1, 0, 0},
|
|
{"DIVIDE" , 0, 3, 882, "R/W", 0, 0, 4ull, 0ull},
|
|
{"HRST" , 3, 1, 882, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PRST" , 4, 1, 882, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ENABLE" , 5, 1, 882, "R/W", 0, 0, 1ull, 1ull},
|
|
{"POR" , 6, 1, 882, "R/W", 0, 0, 1ull, 0ull},
|
|
{"S_BIST" , 7, 1, 882, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SD_MODE" , 8, 2, 882, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CDIV_BYP" , 10, 1, 882, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_C_SEL" , 11, 2, 882, "R/W", 0, 0, 2ull, 0ull},
|
|
{"P_COM_ON" , 13, 1, 882, "R/W", 0, 0, 1ull, 1ull},
|
|
{"P_RTYPE" , 14, 2, 882, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 882, "RAZ", 1, 1, 0, 0},
|
|
{"HCLK_RST" , 17, 1, 882, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DIVIDE2" , 18, 2, 882, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_20_63" , 20, 44, 882, "RAZ", 1, 1, 0, 0},
|
|
{"L2C_EMOD" , 0, 2, 883, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INV_A2" , 2, 1, 883, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_TEST" , 3, 1, 883, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_STT" , 4, 1, 883, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_0PAG" , 5, 1, 883, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 883, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 884, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 884, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 885, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 885, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 886, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 886, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 887, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 887, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 888, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 888, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 889, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 889, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 890, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 890, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 891, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 891, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 892, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 892, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 893, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 893, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 894, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 894, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 895, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 895, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 896, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 896, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 897, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 897, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 898, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 898, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 899, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 899, "RAZ", 1, 1, 0, 0},
|
|
{"BURST" , 0, 4, 900, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHANNEL" , 4, 5, 900, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COUNT" , 9, 11, 900, "R/W", 0, 0, 0ull, 0ull},
|
|
{"F_ADDR" , 20, 18, 900, "R/W", 0, 0, 0ull, 0ull},
|
|
{"REQ" , 38, 1, 900, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DONE" , 39, 1, 900, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 900, "RAZ", 1, 1, 0, 0},
|
|
{"PR_PO_E" , 0, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PR_PU_F" , 1, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NR_PO_E" , 2, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NR_PU_F" , 3, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LR_PO_E" , 4, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LR_PU_F" , 5, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PT_PO_E" , 6, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PT_PU_F" , 7, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NT_PO_E" , 8, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NT_PU_F" , 9, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LT_PO_E" , 10, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LT_PU_F" , 11, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DCRED_E" , 12, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DCRED_F" , 13, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2C_S_E" , 14, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2C_A_F" , 15, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2_FI_E" , 16, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2_FI_F" , 17, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_E" , 18, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_F" , 19, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_F" , 20, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_E" , 21, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_F" , 22, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_E" , 23, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UOD_PE" , 24, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UOD_PF" , 25, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_31" , 26, 6, 901, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LTL_F_PE" , 32, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LTL_F_PF" , 33, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_RPE" , 34, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_RPF" , 35, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_DPE" , 36, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_DPF" , 37, 1, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 901, "RAZ", 1, 1, 0, 0},
|
|
{"PR_PO_E" , 0, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PR_PU_F" , 1, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NR_PO_E" , 2, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NR_PU_F" , 3, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LR_PO_E" , 4, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LR_PU_F" , 5, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PT_PO_E" , 6, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PT_PU_F" , 7, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NT_PO_E" , 8, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NT_PU_F" , 9, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LT_PO_E" , 10, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LT_PU_F" , 11, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCRED_E" , 12, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCRED_F" , 13, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"L2C_S_E" , 14, 1, 902, "R/W1C", 1, 0, 0, 0ull},
|
|
{"L2C_A_F" , 15, 1, 902, "R/W1C", 1, 0, 0, 0ull},
|
|
{"LT_FI_E" , 16, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LT_FI_F" , 17, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_E" , 18, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_F" , 19, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_F" , 20, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_E" , 21, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_F" , 22, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_E" , 23, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UOD_PE" , 24, 1, 902, "R/W1C", 1, 0, 0, 0ull},
|
|
{"UOD_PF" , 25, 1, 902, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_26_31" , 26, 6, 902, "RAZ", 1, 0, 0, 0ull},
|
|
{"LTL_F_PE" , 32, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LTL_F_PF" , 33, 1, 902, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ND4O_RPE" , 34, 1, 902, "R/W1C", 1, 0, 0, 0ull},
|
|
{"ND4O_RPF" , 35, 1, 902, "R/W1C", 1, 0, 0, 0ull},
|
|
{"ND4O_DPE" , 36, 1, 902, "R/W1C", 1, 0, 0, 0ull},
|
|
{"ND4O_DPF" , 37, 1, 902, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 902, "RAZ", 1, 1, 0, 0},
|
|
{"ATE_RESET" , 0, 1, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TDATA_IN" , 1, 8, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TADDR_IN" , 9, 4, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TDATA_SEL" , 13, 1, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BIST_ENB" , 14, 1, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VTEST_ENB" , 15, 1, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LOOP_ENB" , 16, 1, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TX_BS_EN" , 17, 1, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TX_BS_ENH" , 18, 1, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_22" , 19, 4, 903, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"HST_MODE" , 23, 1, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DM_PULLD" , 24, 1, 903, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DP_PULLD" , 25, 1, 903, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TCLK" , 26, 1, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBP_BIST" , 27, 1, 903, "R/W", 0, 0, 1ull, 1ull},
|
|
{"USBC_END" , 28, 1, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_BMODE" , 29, 1, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXPREEMPHASISTUNE" , 30, 1, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_31" , 31, 1, 903, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TDATA_OUT" , 32, 4, 903, "RO", 1, 1, 0, 0},
|
|
{"BIST_ERR" , 36, 1, 903, "RO", 0, 0, 0ull, 0ull},
|
|
{"BIST_DONE" , 37, 1, 903, "RO", 0, 0, 0ull, 0ull},
|
|
{"HSBIST" , 38, 1, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSBIST" , 39, 1, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LSBIST" , 40, 1, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRVVBUS" , 41, 1, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PORTRESET" , 42, 1, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OTGDISABLE" , 43, 1, 903, "R/W", 0, 0, 1ull, 1ull},
|
|
{"OTGTUNE" , 44, 3, 903, "R/W", 0, 0, 2ull, 2ull},
|
|
{"COMPDISTUNE" , 47, 3, 903, "R/W", 0, 0, 2ull, 2ull},
|
|
{"SQRXTUNE" , 50, 3, 903, "R/W", 0, 0, 3ull, 3ull},
|
|
{"TXHSXVTUNE" , 53, 2, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFSLSTUNE" , 55, 4, 903, "R/W", 0, 0, 3ull, 3ull},
|
|
{"TXVREFTUNE" , 59, 4, 903, "R/W", 0, 0, 7ull, 7ull},
|
|
{"TXRISETUNE" , 63, 1, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{NULL,0,0,0,0,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn52xx[] = {
|
|
/* name , ---------------type, bits, off, #field, fld of */
|
|
{"cvmx_agl_gmx_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 0, 14, 0},
|
|
{"cvmx_agl_gmx_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 1, 2, 14},
|
|
{"cvmx_agl_gmx_drv_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2, 12, 16},
|
|
{"cvmx_agl_gmx_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 3, 3, 28},
|
|
{"cvmx_agl_gmx_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 4, 7, 31},
|
|
{"cvmx_agl_gmx_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 6, 1, 38},
|
|
{"cvmx_agl_gmx_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 8, 1, 39},
|
|
{"cvmx_agl_gmx_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 10, 1, 40},
|
|
{"cvmx_agl_gmx_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 12, 1, 41},
|
|
{"cvmx_agl_gmx_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 14, 1, 42},
|
|
{"cvmx_agl_gmx_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 16, 1, 43},
|
|
{"cvmx_agl_gmx_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 18, 2, 44},
|
|
{"cvmx_agl_gmx_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 20, 4, 46},
|
|
{"cvmx_agl_gmx_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 22, 2, 50},
|
|
{"cvmx_agl_gmx_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 24, 10, 52},
|
|
{"cvmx_agl_gmx_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 26, 11, 62},
|
|
{"cvmx_agl_gmx_rx#_frm_max" , CVMX_CSR_DB_TYPE_RSL, 64, 28, 2, 73},
|
|
{"cvmx_agl_gmx_rx#_frm_min" , CVMX_CSR_DB_TYPE_RSL, 64, 30, 2, 75},
|
|
{"cvmx_agl_gmx_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 32, 2, 77},
|
|
{"cvmx_agl_gmx_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 34, 19, 79},
|
|
{"cvmx_agl_gmx_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 36, 19, 98},
|
|
{"cvmx_agl_gmx_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 38, 2, 117},
|
|
{"cvmx_agl_gmx_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 40, 2, 119},
|
|
{"cvmx_agl_gmx_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 42, 2, 121},
|
|
{"cvmx_agl_gmx_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 44, 2, 123},
|
|
{"cvmx_agl_gmx_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 46, 2, 125},
|
|
{"cvmx_agl_gmx_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 48, 2, 127},
|
|
{"cvmx_agl_gmx_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 50, 2, 129},
|
|
{"cvmx_agl_gmx_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 52, 2, 131},
|
|
{"cvmx_agl_gmx_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 54, 2, 133},
|
|
{"cvmx_agl_gmx_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 56, 2, 135},
|
|
{"cvmx_agl_gmx_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 58, 2, 137},
|
|
{"cvmx_agl_gmx_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 60, 2, 139},
|
|
{"cvmx_agl_gmx_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 62, 4, 141},
|
|
{"cvmx_agl_gmx_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 64, 2, 145},
|
|
{"cvmx_agl_gmx_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 66, 2, 147},
|
|
{"cvmx_agl_gmx_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 68, 2, 149},
|
|
{"cvmx_agl_gmx_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 70, 4, 151},
|
|
{"cvmx_agl_gmx_rx_tx_status" , CVMX_CSR_DB_TYPE_RSL, 64, 71, 4, 155},
|
|
{"cvmx_agl_gmx_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 72, 2, 159},
|
|
{"cvmx_agl_gmx_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 74, 3, 161},
|
|
{"cvmx_agl_gmx_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 75, 5, 164},
|
|
{"cvmx_agl_gmx_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 77, 3, 169},
|
|
{"cvmx_agl_gmx_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 79, 2, 172},
|
|
{"cvmx_agl_gmx_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 81, 2, 174},
|
|
{"cvmx_agl_gmx_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 83, 2, 176},
|
|
{"cvmx_agl_gmx_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 85, 2, 178},
|
|
{"cvmx_agl_gmx_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 87, 2, 180},
|
|
{"cvmx_agl_gmx_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 89, 2, 182},
|
|
{"cvmx_agl_gmx_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 91, 2, 184},
|
|
{"cvmx_agl_gmx_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 93, 2, 186},
|
|
{"cvmx_agl_gmx_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 95, 2, 188},
|
|
{"cvmx_agl_gmx_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 97, 2, 190},
|
|
{"cvmx_agl_gmx_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 99, 2, 192},
|
|
{"cvmx_agl_gmx_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 101, 2, 194},
|
|
{"cvmx_agl_gmx_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 103, 2, 196},
|
|
{"cvmx_agl_gmx_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 105, 2, 198},
|
|
{"cvmx_agl_gmx_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 107, 2, 200},
|
|
{"cvmx_agl_gmx_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 109, 2, 202},
|
|
{"cvmx_agl_gmx_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 111, 2, 204},
|
|
{"cvmx_agl_gmx_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 113, 2, 206},
|
|
{"cvmx_agl_gmx_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 115, 2, 208},
|
|
{"cvmx_agl_gmx_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 116, 2, 210},
|
|
{"cvmx_agl_gmx_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 117, 3, 212},
|
|
{"cvmx_agl_gmx_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 118, 10, 215},
|
|
{"cvmx_agl_gmx_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 119, 10, 225},
|
|
{"cvmx_agl_gmx_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 120, 2, 235},
|
|
{"cvmx_agl_gmx_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 121, 2, 237},
|
|
{"cvmx_agl_gmx_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 122, 6, 239},
|
|
{"cvmx_agl_gmx_tx_pause_pkt_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 123, 2, 245},
|
|
{"cvmx_agl_gmx_tx_pause_pkt_type", CVMX_CSR_DB_TYPE_RSL, 64, 124, 2, 247},
|
|
{"cvmx_ciu_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 125, 2, 249},
|
|
{"cvmx_ciu_dint" , CVMX_CSR_DB_TYPE_NCB, 64, 126, 2, 251},
|
|
{"cvmx_ciu_fuse" , CVMX_CSR_DB_TYPE_NCB, 64, 127, 2, 253},
|
|
{"cvmx_ciu_gstop" , CVMX_CSR_DB_TYPE_NCB, 64, 128, 2, 255},
|
|
{"cvmx_ciu_int#_en0" , CVMX_CSR_DB_TYPE_NCB, 64, 129, 22, 257},
|
|
{"cvmx_ciu_int#_en0_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 138, 22, 279},
|
|
{"cvmx_ciu_int#_en0_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 147, 22, 301},
|
|
{"cvmx_ciu_int#_en1" , CVMX_CSR_DB_TYPE_NCB, 64, 156, 7, 323},
|
|
{"cvmx_ciu_int#_en1_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 165, 7, 330},
|
|
{"cvmx_ciu_int#_en1_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 174, 7, 337},
|
|
{"cvmx_ciu_int#_en4_0" , CVMX_CSR_DB_TYPE_NCB, 64, 183, 22, 344},
|
|
{"cvmx_ciu_int#_en4_0_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 187, 22, 366},
|
|
{"cvmx_ciu_int#_en4_0_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 191, 22, 388},
|
|
{"cvmx_ciu_int#_en4_1" , CVMX_CSR_DB_TYPE_NCB, 64, 195, 7, 410},
|
|
{"cvmx_ciu_int#_en4_1_w1c" , CVMX_CSR_DB_TYPE_NCB, 64, 199, 7, 417},
|
|
{"cvmx_ciu_int#_en4_1_w1s" , CVMX_CSR_DB_TYPE_NCB, 64, 203, 7, 424},
|
|
{"cvmx_ciu_int#_sum0" , CVMX_CSR_DB_TYPE_NCB, 64, 207, 22, 431},
|
|
{"cvmx_ciu_int#_sum4" , CVMX_CSR_DB_TYPE_NCB, 64, 216, 22, 453},
|
|
{"cvmx_ciu_int_sum1" , CVMX_CSR_DB_TYPE_NCB, 64, 220, 7, 475},
|
|
{"cvmx_ciu_mbox_clr#" , CVMX_CSR_DB_TYPE_NCB, 64, 221, 2, 482},
|
|
{"cvmx_ciu_mbox_set#" , CVMX_CSR_DB_TYPE_NCB, 64, 225, 2, 484},
|
|
{"cvmx_ciu_nmi" , CVMX_CSR_DB_TYPE_NCB, 64, 229, 2, 486},
|
|
{"cvmx_ciu_pci_inta" , CVMX_CSR_DB_TYPE_NCB, 64, 230, 2, 488},
|
|
{"cvmx_ciu_pp_dbg" , CVMX_CSR_DB_TYPE_NCB, 64, 231, 2, 490},
|
|
{"cvmx_ciu_pp_poke#" , CVMX_CSR_DB_TYPE_NCB, 64, 232, 1, 492},
|
|
{"cvmx_ciu_pp_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 236, 3, 493},
|
|
{"cvmx_ciu_qlm_dcok" , CVMX_CSR_DB_TYPE_NCB, 64, 237, 2, 496},
|
|
{"cvmx_ciu_qlm_jtgc" , CVMX_CSR_DB_TYPE_NCB, 64, 238, 6, 498},
|
|
{"cvmx_ciu_qlm_jtgd" , CVMX_CSR_DB_TYPE_NCB, 64, 239, 8, 504},
|
|
{"cvmx_ciu_soft_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 240, 2, 512},
|
|
{"cvmx_ciu_soft_prst" , CVMX_CSR_DB_TYPE_NCB, 64, 241, 2, 514},
|
|
{"cvmx_ciu_soft_prst1" , CVMX_CSR_DB_TYPE_NCB, 64, 242, 2, 516},
|
|
{"cvmx_ciu_soft_rst" , CVMX_CSR_DB_TYPE_NCB, 64, 243, 2, 518},
|
|
{"cvmx_ciu_tim#" , CVMX_CSR_DB_TYPE_NCB, 64, 244, 3, 520},
|
|
{"cvmx_ciu_wdog#" , CVMX_CSR_DB_TYPE_NCB, 64, 248, 7, 523},
|
|
{"cvmx_fpa_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 252, 6, 530},
|
|
{"cvmx_fpa_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 253, 7, 536},
|
|
{"cvmx_fpa_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 254, 29, 543},
|
|
{"cvmx_fpa_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 255, 29, 572},
|
|
{"cvmx_fpa_que#_available" , CVMX_CSR_DB_TYPE_RSL, 64, 256, 2, 601},
|
|
{"cvmx_fpa_que#_page_index" , CVMX_CSR_DB_TYPE_RSL, 64, 264, 2, 603},
|
|
{"cvmx_fpa_que_act" , CVMX_CSR_DB_TYPE_RSL, 64, 272, 3, 605},
|
|
{"cvmx_fpa_que_exp" , CVMX_CSR_DB_TYPE_RSL, 64, 273, 3, 608},
|
|
{"cvmx_fpa_wart_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 274, 2, 611},
|
|
{"cvmx_fpa_wart_status" , CVMX_CSR_DB_TYPE_RSL, 64, 275, 2, 613},
|
|
{"cvmx_gmx#_bad_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 276, 7, 615},
|
|
{"cvmx_gmx#_bist" , CVMX_CSR_DB_TYPE_RSL, 64, 277, 2, 622},
|
|
{"cvmx_gmx#_clk_en" , CVMX_CSR_DB_TYPE_RSL, 64, 278, 2, 624},
|
|
{"cvmx_gmx#_hg2_control" , CVMX_CSR_DB_TYPE_RSL, 64, 279, 5, 626},
|
|
{"cvmx_gmx#_inf_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 280, 7, 631},
|
|
{"cvmx_gmx#_nxa_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 281, 2, 638},
|
|
{"cvmx_gmx#_prt#_cbfc_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 282, 8, 640},
|
|
{"cvmx_gmx#_prt#_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 283, 10, 648},
|
|
{"cvmx_gmx#_rx#_adr_cam0" , CVMX_CSR_DB_TYPE_RSL, 64, 287, 1, 658},
|
|
{"cvmx_gmx#_rx#_adr_cam1" , CVMX_CSR_DB_TYPE_RSL, 64, 291, 1, 659},
|
|
{"cvmx_gmx#_rx#_adr_cam2" , CVMX_CSR_DB_TYPE_RSL, 64, 295, 1, 660},
|
|
{"cvmx_gmx#_rx#_adr_cam3" , CVMX_CSR_DB_TYPE_RSL, 64, 299, 1, 661},
|
|
{"cvmx_gmx#_rx#_adr_cam4" , CVMX_CSR_DB_TYPE_RSL, 64, 303, 1, 662},
|
|
{"cvmx_gmx#_rx#_adr_cam5" , CVMX_CSR_DB_TYPE_RSL, 64, 307, 1, 663},
|
|
{"cvmx_gmx#_rx#_adr_cam_en" , CVMX_CSR_DB_TYPE_RSL, 64, 311, 2, 664},
|
|
{"cvmx_gmx#_rx#_adr_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 315, 4, 666},
|
|
{"cvmx_gmx#_rx#_decision" , CVMX_CSR_DB_TYPE_RSL, 64, 319, 2, 670},
|
|
{"cvmx_gmx#_rx#_frm_chk" , CVMX_CSR_DB_TYPE_RSL, 64, 323, 9, 672},
|
|
{"cvmx_gmx#_rx#_frm_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 327, 11, 681},
|
|
{"cvmx_gmx#_rx#_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 331, 2, 692},
|
|
{"cvmx_gmx#_rx#_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 335, 27, 694},
|
|
{"cvmx_gmx#_rx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 339, 27, 721},
|
|
{"cvmx_gmx#_rx#_jabber" , CVMX_CSR_DB_TYPE_RSL, 64, 343, 2, 748},
|
|
{"cvmx_gmx#_rx#_pause_drop_time", CVMX_CSR_DB_TYPE_RSL, 64, 347, 2, 750},
|
|
{"cvmx_gmx#_rx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 351, 2, 752},
|
|
{"cvmx_gmx#_rx#_stats_octs" , CVMX_CSR_DB_TYPE_RSL, 64, 355, 2, 754},
|
|
{"cvmx_gmx#_rx#_stats_octs_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 359, 2, 756},
|
|
{"cvmx_gmx#_rx#_stats_octs_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 363, 2, 758},
|
|
{"cvmx_gmx#_rx#_stats_octs_drp", CVMX_CSR_DB_TYPE_RSL, 64, 367, 2, 760},
|
|
{"cvmx_gmx#_rx#_stats_pkts" , CVMX_CSR_DB_TYPE_RSL, 64, 371, 2, 762},
|
|
{"cvmx_gmx#_rx#_stats_pkts_bad", CVMX_CSR_DB_TYPE_RSL, 64, 375, 2, 764},
|
|
{"cvmx_gmx#_rx#_stats_pkts_ctl", CVMX_CSR_DB_TYPE_RSL, 64, 379, 2, 766},
|
|
{"cvmx_gmx#_rx#_stats_pkts_dmac", CVMX_CSR_DB_TYPE_RSL, 64, 383, 2, 768},
|
|
{"cvmx_gmx#_rx#_stats_pkts_drp", CVMX_CSR_DB_TYPE_RSL, 64, 387, 2, 770},
|
|
{"cvmx_gmx#_rx#_udd_skp" , CVMX_CSR_DB_TYPE_RSL, 64, 391, 4, 772},
|
|
{"cvmx_gmx#_rx_bp_drop#" , CVMX_CSR_DB_TYPE_RSL, 64, 395, 2, 776},
|
|
{"cvmx_gmx#_rx_bp_off#" , CVMX_CSR_DB_TYPE_RSL, 64, 399, 2, 778},
|
|
{"cvmx_gmx#_rx_bp_on#" , CVMX_CSR_DB_TYPE_RSL, 64, 403, 2, 780},
|
|
{"cvmx_gmx#_rx_hg2_status" , CVMX_CSR_DB_TYPE_RSL, 64, 407, 4, 782},
|
|
{"cvmx_gmx#_rx_prt_info" , CVMX_CSR_DB_TYPE_RSL, 64, 408, 4, 786},
|
|
{"cvmx_gmx#_rx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 409, 2, 790},
|
|
{"cvmx_gmx#_rx_xaui_bad_col" , CVMX_CSR_DB_TYPE_RSL, 64, 410, 5, 792},
|
|
{"cvmx_gmx#_rx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 411, 2, 797},
|
|
{"cvmx_gmx#_smac#" , CVMX_CSR_DB_TYPE_RSL, 64, 412, 2, 799},
|
|
{"cvmx_gmx#_stat_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 416, 3, 801},
|
|
{"cvmx_gmx#_tx#_append" , CVMX_CSR_DB_TYPE_RSL, 64, 417, 5, 804},
|
|
{"cvmx_gmx#_tx#_burst" , CVMX_CSR_DB_TYPE_RSL, 64, 421, 2, 809},
|
|
{"cvmx_gmx#_tx#_cbfc_xoff" , CVMX_CSR_DB_TYPE_RSL, 64, 425, 2, 811},
|
|
{"cvmx_gmx#_tx#_cbfc_xon" , CVMX_CSR_DB_TYPE_RSL, 64, 426, 2, 813},
|
|
{"cvmx_gmx#_tx#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 427, 3, 815},
|
|
{"cvmx_gmx#_tx#_min_pkt" , CVMX_CSR_DB_TYPE_RSL, 64, 431, 2, 818},
|
|
{"cvmx_gmx#_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL, 64, 435, 2, 820},
|
|
{"cvmx_gmx#_tx#_pause_pkt_time", CVMX_CSR_DB_TYPE_RSL, 64, 439, 2, 822},
|
|
{"cvmx_gmx#_tx#_pause_togo" , CVMX_CSR_DB_TYPE_RSL, 64, 443, 3, 824},
|
|
{"cvmx_gmx#_tx#_pause_zero" , CVMX_CSR_DB_TYPE_RSL, 64, 447, 2, 827},
|
|
{"cvmx_gmx#_tx#_sgmii_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 451, 2, 829},
|
|
{"cvmx_gmx#_tx#_slot" , CVMX_CSR_DB_TYPE_RSL, 64, 455, 2, 831},
|
|
{"cvmx_gmx#_tx#_soft_pause" , CVMX_CSR_DB_TYPE_RSL, 64, 459, 2, 833},
|
|
{"cvmx_gmx#_tx#_stat0" , CVMX_CSR_DB_TYPE_RSL, 64, 463, 2, 835},
|
|
{"cvmx_gmx#_tx#_stat1" , CVMX_CSR_DB_TYPE_RSL, 64, 467, 2, 837},
|
|
{"cvmx_gmx#_tx#_stat2" , CVMX_CSR_DB_TYPE_RSL, 64, 471, 2, 839},
|
|
{"cvmx_gmx#_tx#_stat3" , CVMX_CSR_DB_TYPE_RSL, 64, 475, 2, 841},
|
|
{"cvmx_gmx#_tx#_stat4" , CVMX_CSR_DB_TYPE_RSL, 64, 479, 2, 843},
|
|
{"cvmx_gmx#_tx#_stat5" , CVMX_CSR_DB_TYPE_RSL, 64, 483, 2, 845},
|
|
{"cvmx_gmx#_tx#_stat6" , CVMX_CSR_DB_TYPE_RSL, 64, 487, 2, 847},
|
|
{"cvmx_gmx#_tx#_stat7" , CVMX_CSR_DB_TYPE_RSL, 64, 491, 2, 849},
|
|
{"cvmx_gmx#_tx#_stat8" , CVMX_CSR_DB_TYPE_RSL, 64, 495, 2, 851},
|
|
{"cvmx_gmx#_tx#_stat9" , CVMX_CSR_DB_TYPE_RSL, 64, 499, 2, 853},
|
|
{"cvmx_gmx#_tx#_stats_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 503, 2, 855},
|
|
{"cvmx_gmx#_tx#_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 507, 2, 857},
|
|
{"cvmx_gmx#_tx_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 511, 2, 859},
|
|
{"cvmx_gmx#_tx_col_attempt" , CVMX_CSR_DB_TYPE_RSL, 64, 512, 2, 861},
|
|
{"cvmx_gmx#_tx_corrupt" , CVMX_CSR_DB_TYPE_RSL, 64, 513, 2, 863},
|
|
{"cvmx_gmx#_tx_hg2_reg1" , CVMX_CSR_DB_TYPE_RSL, 64, 514, 2, 865},
|
|
{"cvmx_gmx#_tx_hg2_reg2" , CVMX_CSR_DB_TYPE_RSL, 64, 515, 2, 867},
|
|
{"cvmx_gmx#_tx_ifg" , CVMX_CSR_DB_TYPE_RSL, 64, 516, 3, 869},
|
|
{"cvmx_gmx#_tx_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 517, 8, 872},
|
|
{"cvmx_gmx#_tx_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 518, 8, 880},
|
|
{"cvmx_gmx#_tx_jam" , CVMX_CSR_DB_TYPE_RSL, 64, 519, 2, 888},
|
|
{"cvmx_gmx#_tx_lfsr" , CVMX_CSR_DB_TYPE_RSL, 64, 520, 2, 890},
|
|
{"cvmx_gmx#_tx_ovr_bp" , CVMX_CSR_DB_TYPE_RSL, 64, 521, 6, 892},
|
|
{"cvmx_gmx#_tx_pause_pkt_dmac" , CVMX_CSR_DB_TYPE_RSL, 64, 522, 2, 898},
|
|
{"cvmx_gmx#_tx_pause_pkt_type" , CVMX_CSR_DB_TYPE_RSL, 64, 523, 2, 900},
|
|
{"cvmx_gmx#_tx_prts" , CVMX_CSR_DB_TYPE_RSL, 64, 524, 2, 902},
|
|
{"cvmx_gmx#_tx_xaui_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 525, 9, 904},
|
|
{"cvmx_gmx#_xaui_ext_loopback" , CVMX_CSR_DB_TYPE_RSL, 64, 526, 3, 913},
|
|
{"cvmx_gpio_bit_cfg#" , CVMX_CSR_DB_TYPE_NCB, 64, 527, 9, 916},
|
|
{"cvmx_gpio_clk_gen#" , CVMX_CSR_DB_TYPE_NCB, 64, 543, 2, 925},
|
|
{"cvmx_gpio_int_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 547, 2, 927},
|
|
{"cvmx_gpio_rx_dat" , CVMX_CSR_DB_TYPE_NCB, 64, 548, 2, 929},
|
|
{"cvmx_gpio_tx_clr" , CVMX_CSR_DB_TYPE_NCB, 64, 549, 2, 931},
|
|
{"cvmx_gpio_tx_set" , CVMX_CSR_DB_TYPE_NCB, 64, 550, 2, 933},
|
|
{"cvmx_iob_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 551, 19, 935},
|
|
{"cvmx_iob_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 552, 7, 954},
|
|
{"cvmx_iob_dwb_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 553, 3, 961},
|
|
{"cvmx_iob_fau_timeout" , CVMX_CSR_DB_TYPE_RSL, 64, 554, 3, 964},
|
|
{"cvmx_iob_i2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 555, 3, 967},
|
|
{"cvmx_iob_inb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 556, 5, 970},
|
|
{"cvmx_iob_inb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 557, 5, 975},
|
|
{"cvmx_iob_inb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 558, 1, 980},
|
|
{"cvmx_iob_inb_data_match_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 559, 1, 981},
|
|
{"cvmx_iob_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 560, 7, 982},
|
|
{"cvmx_iob_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 561, 7, 989},
|
|
{"cvmx_iob_n2c_l2c_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 562, 3, 996},
|
|
{"cvmx_iob_n2c_rsp_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 563, 3, 999},
|
|
{"cvmx_iob_outb_com_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 564, 3, 1002},
|
|
{"cvmx_iob_outb_control_match" , CVMX_CSR_DB_TYPE_RSL, 64, 565, 5, 1005},
|
|
{"cvmx_iob_outb_control_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 566, 5, 1010},
|
|
{"cvmx_iob_outb_data_match" , CVMX_CSR_DB_TYPE_RSL, 64, 567, 1, 1015},
|
|
{"cvmx_iob_outb_data_match_enb", CVMX_CSR_DB_TYPE_RSL, 64, 568, 1, 1016},
|
|
{"cvmx_iob_outb_fpa_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 569, 3, 1017},
|
|
{"cvmx_iob_outb_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 570, 3, 1020},
|
|
{"cvmx_iob_p2c_req_pri_cnt" , CVMX_CSR_DB_TYPE_RSL, 64, 571, 3, 1023},
|
|
{"cvmx_iob_pkt_err" , CVMX_CSR_DB_TYPE_RSL, 64, 572, 2, 1026},
|
|
{"cvmx_iob_to_cmb_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 573, 4, 1028},
|
|
{"cvmx_ipd_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 574, 2, 1032},
|
|
{"cvmx_ipd_1st_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 575, 2, 1034},
|
|
{"cvmx_ipd_2nd_next_ptr_back" , CVMX_CSR_DB_TYPE_NCB, 64, 576, 2, 1036},
|
|
{"cvmx_ipd_bist_status" , CVMX_CSR_DB_TYPE_NCB, 64, 577, 19, 1038},
|
|
{"cvmx_ipd_bp_prt_red_end" , CVMX_CSR_DB_TYPE_NCB, 64, 578, 2, 1057},
|
|
{"cvmx_ipd_clk_count" , CVMX_CSR_DB_TYPE_NCB, 64, 579, 1, 1059},
|
|
{"cvmx_ipd_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 580, 15, 1060},
|
|
{"cvmx_ipd_int_enb" , CVMX_CSR_DB_TYPE_NCB, 64, 581, 13, 1075},
|
|
{"cvmx_ipd_int_sum" , CVMX_CSR_DB_TYPE_NCB, 64, 582, 13, 1088},
|
|
{"cvmx_ipd_not_1st_mbuff_skip" , CVMX_CSR_DB_TYPE_NCB, 64, 583, 2, 1101},
|
|
{"cvmx_ipd_packet_mbuff_size" , CVMX_CSR_DB_TYPE_NCB, 64, 584, 2, 1103},
|
|
{"cvmx_ipd_pkt_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 585, 2, 1105},
|
|
{"cvmx_ipd_port#_bp_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 586, 3, 1107},
|
|
{"cvmx_ipd_port#_bp_page_cnt2" , CVMX_CSR_DB_TYPE_NCB, 64, 594, 3, 1110},
|
|
{"cvmx_ipd_port_bp_counters2_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 598, 2, 1113},
|
|
{"cvmx_ipd_port_bp_counters_pair#", CVMX_CSR_DB_TYPE_NCB, 64, 602, 2, 1115},
|
|
{"cvmx_ipd_port_qos_#_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 610, 2, 1117},
|
|
{"cvmx_ipd_port_qos_int#" , CVMX_CSR_DB_TYPE_NCB, 64, 706, 1, 1119},
|
|
{"cvmx_ipd_port_qos_int_enb#" , CVMX_CSR_DB_TYPE_NCB, 64, 708, 1, 1120},
|
|
{"cvmx_ipd_prc_hold_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 710, 6, 1121},
|
|
{"cvmx_ipd_prc_port_ptr_fifo_ctl", CVMX_CSR_DB_TYPE_NCB, 64, 711, 5, 1127},
|
|
{"cvmx_ipd_ptr_count" , CVMX_CSR_DB_TYPE_NCB, 64, 712, 6, 1132},
|
|
{"cvmx_ipd_pwp_ptr_fifo_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 713, 7, 1138},
|
|
{"cvmx_ipd_qos#_red_marks" , CVMX_CSR_DB_TYPE_NCB, 64, 714, 2, 1145},
|
|
{"cvmx_ipd_que0_free_page_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 722, 2, 1147},
|
|
{"cvmx_ipd_red_port_enable" , CVMX_CSR_DB_TYPE_NCB, 64, 723, 3, 1149},
|
|
{"cvmx_ipd_red_port_enable2" , CVMX_CSR_DB_TYPE_NCB, 64, 724, 2, 1152},
|
|
{"cvmx_ipd_red_que#_param" , CVMX_CSR_DB_TYPE_NCB, 64, 725, 5, 1154},
|
|
{"cvmx_ipd_sub_port_bp_page_cnt", CVMX_CSR_DB_TYPE_NCB, 64, 733, 3, 1159},
|
|
{"cvmx_ipd_sub_port_fcs" , CVMX_CSR_DB_TYPE_NCB, 64, 734, 4, 1162},
|
|
{"cvmx_ipd_sub_port_qos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 735, 3, 1166},
|
|
{"cvmx_ipd_wqe_fpa_queue" , CVMX_CSR_DB_TYPE_NCB, 64, 736, 2, 1169},
|
|
{"cvmx_ipd_wqe_ptr_valid" , CVMX_CSR_DB_TYPE_NCB, 64, 737, 2, 1171},
|
|
{"cvmx_l2c_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 738, 8, 1173},
|
|
{"cvmx_l2c_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 739, 9, 1181},
|
|
{"cvmx_l2c_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 740, 8, 1190},
|
|
{"cvmx_l2c_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 741, 12, 1198},
|
|
{"cvmx_l2c_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 742, 9, 1210},
|
|
{"cvmx_l2c_dut" , CVMX_CSR_DB_TYPE_RSL, 64, 743, 5, 1219},
|
|
{"cvmx_l2c_grpwrr0" , CVMX_CSR_DB_TYPE_RSL, 64, 744, 2, 1224},
|
|
{"cvmx_l2c_grpwrr1" , CVMX_CSR_DB_TYPE_RSL, 64, 745, 2, 1226},
|
|
{"cvmx_l2c_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 746, 10, 1228},
|
|
{"cvmx_l2c_int_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 747, 10, 1238},
|
|
{"cvmx_l2c_lckbase" , CVMX_CSR_DB_TYPE_RSL, 64, 748, 4, 1248},
|
|
{"cvmx_l2c_lckoff" , CVMX_CSR_DB_TYPE_RSL, 64, 749, 2, 1252},
|
|
{"cvmx_l2c_lfb0" , CVMX_CSR_DB_TYPE_RSL, 64, 750, 16, 1254},
|
|
{"cvmx_l2c_lfb1" , CVMX_CSR_DB_TYPE_RSL, 64, 751, 19, 1270},
|
|
{"cvmx_l2c_lfb2" , CVMX_CSR_DB_TYPE_RSL, 64, 752, 3, 1289},
|
|
{"cvmx_l2c_lfb3" , CVMX_CSR_DB_TYPE_RSL, 64, 753, 4, 1292},
|
|
{"cvmx_l2c_oob" , CVMX_CSR_DB_TYPE_RSL, 64, 754, 3, 1296},
|
|
{"cvmx_l2c_oob1" , CVMX_CSR_DB_TYPE_RSL, 64, 755, 6, 1299},
|
|
{"cvmx_l2c_oob2" , CVMX_CSR_DB_TYPE_RSL, 64, 756, 6, 1305},
|
|
{"cvmx_l2c_oob3" , CVMX_CSR_DB_TYPE_RSL, 64, 757, 6, 1311},
|
|
{"cvmx_l2c_pfc#" , CVMX_CSR_DB_TYPE_RSL, 64, 758, 2, 1317},
|
|
{"cvmx_l2c_pfctl" , CVMX_CSR_DB_TYPE_RSL, 64, 762, 17, 1319},
|
|
{"cvmx_l2c_ppgrp" , CVMX_CSR_DB_TYPE_RSL, 64, 763, 5, 1336},
|
|
{"cvmx_l2c_spar0" , CVMX_CSR_DB_TYPE_RSL, 64, 764, 5, 1341},
|
|
{"cvmx_l2c_spar4" , CVMX_CSR_DB_TYPE_RSL, 64, 765, 2, 1346},
|
|
{"cvmx_l2d_bst0" , CVMX_CSR_DB_TYPE_RSL, 64, 766, 3, 1348},
|
|
{"cvmx_l2d_bst1" , CVMX_CSR_DB_TYPE_RSL, 64, 767, 2, 1351},
|
|
{"cvmx_l2d_bst2" , CVMX_CSR_DB_TYPE_RSL, 64, 768, 2, 1353},
|
|
{"cvmx_l2d_bst3" , CVMX_CSR_DB_TYPE_RSL, 64, 769, 2, 1355},
|
|
{"cvmx_l2d_err" , CVMX_CSR_DB_TYPE_RSL, 64, 770, 7, 1357},
|
|
{"cvmx_l2d_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 771, 5, 1364},
|
|
{"cvmx_l2d_fsyn0" , CVMX_CSR_DB_TYPE_RSL, 64, 772, 3, 1369},
|
|
{"cvmx_l2d_fsyn1" , CVMX_CSR_DB_TYPE_RSL, 64, 773, 3, 1372},
|
|
{"cvmx_l2d_fus0" , CVMX_CSR_DB_TYPE_RSL, 64, 774, 2, 1375},
|
|
{"cvmx_l2d_fus1" , CVMX_CSR_DB_TYPE_RSL, 64, 775, 2, 1377},
|
|
{"cvmx_l2d_fus2" , CVMX_CSR_DB_TYPE_RSL, 64, 776, 2, 1379},
|
|
{"cvmx_l2d_fus3" , CVMX_CSR_DB_TYPE_RSL, 64, 777, 6, 1381},
|
|
{"cvmx_l2t_err" , CVMX_CSR_DB_TYPE_RSL, 64, 778, 14, 1387},
|
|
{"cvmx_lmc#_bist_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 779, 2, 1401},
|
|
{"cvmx_lmc#_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 780, 8, 1403},
|
|
{"cvmx_lmc#_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 781, 7, 1411},
|
|
{"cvmx_lmc#_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 782, 19, 1418},
|
|
{"cvmx_lmc#_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 783, 8, 1437},
|
|
{"cvmx_lmc#_dclk_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 784, 2, 1445},
|
|
{"cvmx_lmc#_dclk_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 785, 2, 1447},
|
|
{"cvmx_lmc#_ddr2_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 786, 18, 1449},
|
|
{"cvmx_lmc#_delay_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 787, 6, 1467},
|
|
{"cvmx_lmc#_dll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 788, 5, 1473},
|
|
{"cvmx_lmc#_dual_memcfg" , CVMX_CSR_DB_TYPE_RSL, 64, 789, 5, 1478},
|
|
{"cvmx_lmc#_ecc_synd" , CVMX_CSR_DB_TYPE_RSL, 64, 790, 5, 1483},
|
|
{"cvmx_lmc#_fadr" , CVMX_CSR_DB_TYPE_RSL, 64, 791, 6, 1488},
|
|
{"cvmx_lmc#_ifb_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 792, 2, 1494},
|
|
{"cvmx_lmc#_ifb_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 793, 2, 1496},
|
|
{"cvmx_lmc#_mem_cfg0" , CVMX_CSR_DB_TYPE_RSL, 64, 794, 14, 1498},
|
|
{"cvmx_lmc#_mem_cfg1" , CVMX_CSR_DB_TYPE_RSL, 64, 795, 9, 1512},
|
|
{"cvmx_lmc#_nxm" , CVMX_CSR_DB_TYPE_RSL, 64, 796, 2, 1521},
|
|
{"cvmx_lmc#_ops_cnt_hi" , CVMX_CSR_DB_TYPE_RSL, 64, 797, 2, 1523},
|
|
{"cvmx_lmc#_ops_cnt_lo" , CVMX_CSR_DB_TYPE_RSL, 64, 798, 2, 1525},
|
|
{"cvmx_lmc#_pll_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 799, 14, 1527},
|
|
{"cvmx_lmc#_pll_status" , CVMX_CSR_DB_TYPE_RSL, 64, 800, 6, 1541},
|
|
{"cvmx_lmc#_read_level_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 801, 7, 1547},
|
|
{"cvmx_lmc#_read_level_dbg" , CVMX_CSR_DB_TYPE_RSL, 64, 802, 4, 1554},
|
|
{"cvmx_lmc#_read_level_rank#" , CVMX_CSR_DB_TYPE_RSL, 64, 803, 11, 1558},
|
|
{"cvmx_lmc#_rodt_comp_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 807, 6, 1569},
|
|
{"cvmx_lmc#_rodt_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 808, 9, 1575},
|
|
{"cvmx_lmc#_wodt_ctl0" , CVMX_CSR_DB_TYPE_RSL, 64, 809, 5, 1584},
|
|
{"cvmx_lmc#_wodt_ctl1" , CVMX_CSR_DB_TYPE_RSL, 64, 810, 5, 1589},
|
|
{"cvmx_mio_boot_bist_stat" , CVMX_CSR_DB_TYPE_RSL, 64, 811, 6, 1594},
|
|
{"cvmx_mio_boot_comp" , CVMX_CSR_DB_TYPE_RSL, 64, 812, 3, 1600},
|
|
{"cvmx_mio_boot_dma_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 813, 10, 1603},
|
|
{"cvmx_mio_boot_dma_int#" , CVMX_CSR_DB_TYPE_RSL, 64, 815, 3, 1613},
|
|
{"cvmx_mio_boot_dma_int_en#" , CVMX_CSR_DB_TYPE_RSL, 64, 817, 3, 1616},
|
|
{"cvmx_mio_boot_dma_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 819, 15, 1619},
|
|
{"cvmx_mio_boot_err" , CVMX_CSR_DB_TYPE_RSL, 64, 821, 3, 1634},
|
|
{"cvmx_mio_boot_int" , CVMX_CSR_DB_TYPE_RSL, 64, 822, 3, 1637},
|
|
{"cvmx_mio_boot_loc_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 823, 3, 1640},
|
|
{"cvmx_mio_boot_loc_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 824, 5, 1643},
|
|
{"cvmx_mio_boot_loc_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 826, 1, 1648},
|
|
{"cvmx_mio_boot_pin_defs" , CVMX_CSR_DB_TYPE_RSL, 64, 827, 9, 1649},
|
|
{"cvmx_mio_boot_reg_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 828, 13, 1658},
|
|
{"cvmx_mio_boot_reg_tim#" , CVMX_CSR_DB_TYPE_RSL, 64, 836, 13, 1671},
|
|
{"cvmx_mio_boot_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 844, 6, 1684},
|
|
{"cvmx_mio_fus_bnk_dat#" , CVMX_CSR_DB_TYPE_RSL, 64, 845, 1, 1690},
|
|
{"cvmx_mio_fus_dat0" , CVMX_CSR_DB_TYPE_RSL, 64, 849, 2, 1691},
|
|
{"cvmx_mio_fus_dat1" , CVMX_CSR_DB_TYPE_RSL, 64, 850, 2, 1693},
|
|
{"cvmx_mio_fus_dat2" , CVMX_CSR_DB_TYPE_RSL, 64, 851, 13, 1695},
|
|
{"cvmx_mio_fus_dat3" , CVMX_CSR_DB_TYPE_RSL, 64, 852, 8, 1708},
|
|
{"cvmx_mio_fus_ema" , CVMX_CSR_DB_TYPE_RSL, 64, 853, 4, 1716},
|
|
{"cvmx_mio_fus_pdf" , CVMX_CSR_DB_TYPE_RSL, 64, 854, 1, 1720},
|
|
{"cvmx_mio_fus_pll" , CVMX_CSR_DB_TYPE_RSL, 64, 855, 3, 1721},
|
|
{"cvmx_mio_fus_prog" , CVMX_CSR_DB_TYPE_RSL, 64, 856, 2, 1724},
|
|
{"cvmx_mio_fus_prog_times" , CVMX_CSR_DB_TYPE_RSL, 64, 857, 6, 1726},
|
|
{"cvmx_mio_fus_rcmd" , CVMX_CSR_DB_TYPE_RSL, 64, 858, 7, 1732},
|
|
{"cvmx_mio_fus_spr_repair_res" , CVMX_CSR_DB_TYPE_RSL, 64, 859, 4, 1739},
|
|
{"cvmx_mio_fus_spr_repair_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 860, 2, 1743},
|
|
{"cvmx_mio_fus_wadr" , CVMX_CSR_DB_TYPE_RSL, 64, 861, 2, 1745},
|
|
{"cvmx_mio_ndf_dma_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 862, 10, 1747},
|
|
{"cvmx_mio_ndf_dma_int" , CVMX_CSR_DB_TYPE_RSL, 64, 863, 2, 1757},
|
|
{"cvmx_mio_ndf_dma_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 864, 2, 1759},
|
|
{"cvmx_mio_tws#_int" , CVMX_CSR_DB_TYPE_RSL, 64, 865, 13, 1761},
|
|
{"cvmx_mio_tws#_sw_twsi" , CVMX_CSR_DB_TYPE_RSL, 64, 867, 12, 1774},
|
|
{"cvmx_mio_tws#_sw_twsi_ext" , CVMX_CSR_DB_TYPE_RSL, 64, 869, 3, 1786},
|
|
{"cvmx_mio_tws#_twsi_sw" , CVMX_CSR_DB_TYPE_RSL, 64, 871, 3, 1789},
|
|
{"cvmx_mio_uart#_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 873, 2, 1792},
|
|
{"cvmx_mio_uart#_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 875, 2, 1794},
|
|
{"cvmx_mio_uart#_far" , CVMX_CSR_DB_TYPE_RSL, 64, 877, 2, 1796},
|
|
{"cvmx_mio_uart#_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 879, 7, 1798},
|
|
{"cvmx_mio_uart#_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 881, 2, 1805},
|
|
{"cvmx_mio_uart#_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 883, 7, 1807},
|
|
{"cvmx_mio_uart#_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 885, 4, 1814},
|
|
{"cvmx_mio_uart#_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 887, 8, 1818},
|
|
{"cvmx_mio_uart#_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 889, 9, 1826},
|
|
{"cvmx_mio_uart#_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 891, 7, 1835},
|
|
{"cvmx_mio_uart#_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 893, 9, 1842},
|
|
{"cvmx_mio_uart#_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 895, 2, 1851},
|
|
{"cvmx_mio_uart#_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 897, 2, 1853},
|
|
{"cvmx_mio_uart#_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 899, 4, 1855},
|
|
{"cvmx_mio_uart#_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 901, 2, 1859},
|
|
{"cvmx_mio_uart#_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 903, 2, 1861},
|
|
{"cvmx_mio_uart#_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 905, 2, 1863},
|
|
{"cvmx_mio_uart#_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 907, 4, 1865},
|
|
{"cvmx_mio_uart#_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 909, 2, 1869},
|
|
{"cvmx_mio_uart#_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 911, 2, 1871},
|
|
{"cvmx_mio_uart#_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 913, 2, 1873},
|
|
{"cvmx_mio_uart#_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 915, 2, 1875},
|
|
{"cvmx_mio_uart#_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 917, 2, 1877},
|
|
{"cvmx_mio_uart#_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 919, 2, 1879},
|
|
{"cvmx_mio_uart#_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 921, 6, 1881},
|
|
{"cvmx_mio_uart2_dlh" , CVMX_CSR_DB_TYPE_RSL, 64, 923, 2, 1887},
|
|
{"cvmx_mio_uart2_dll" , CVMX_CSR_DB_TYPE_RSL, 64, 924, 2, 1889},
|
|
{"cvmx_mio_uart2_far" , CVMX_CSR_DB_TYPE_RSL, 64, 925, 2, 1891},
|
|
{"cvmx_mio_uart2_fcr" , CVMX_CSR_DB_TYPE_RSL, 64, 926, 7, 1893},
|
|
{"cvmx_mio_uart2_htx" , CVMX_CSR_DB_TYPE_RSL, 64, 927, 2, 1900},
|
|
{"cvmx_mio_uart2_ier" , CVMX_CSR_DB_TYPE_RSL, 64, 928, 7, 1902},
|
|
{"cvmx_mio_uart2_iir" , CVMX_CSR_DB_TYPE_RSL, 64, 929, 4, 1909},
|
|
{"cvmx_mio_uart2_lcr" , CVMX_CSR_DB_TYPE_RSL, 64, 930, 8, 1913},
|
|
{"cvmx_mio_uart2_lsr" , CVMX_CSR_DB_TYPE_RSL, 64, 931, 9, 1921},
|
|
{"cvmx_mio_uart2_mcr" , CVMX_CSR_DB_TYPE_RSL, 64, 932, 7, 1930},
|
|
{"cvmx_mio_uart2_msr" , CVMX_CSR_DB_TYPE_RSL, 64, 933, 9, 1937},
|
|
{"cvmx_mio_uart2_rbr" , CVMX_CSR_DB_TYPE_RSL, 64, 934, 2, 1946},
|
|
{"cvmx_mio_uart2_rfl" , CVMX_CSR_DB_TYPE_RSL, 64, 935, 2, 1948},
|
|
{"cvmx_mio_uart2_rfw" , CVMX_CSR_DB_TYPE_RSL, 64, 936, 4, 1950},
|
|
{"cvmx_mio_uart2_sbcr" , CVMX_CSR_DB_TYPE_RSL, 64, 937, 2, 1954},
|
|
{"cvmx_mio_uart2_scr" , CVMX_CSR_DB_TYPE_RSL, 64, 938, 2, 1956},
|
|
{"cvmx_mio_uart2_sfe" , CVMX_CSR_DB_TYPE_RSL, 64, 939, 2, 1958},
|
|
{"cvmx_mio_uart2_srr" , CVMX_CSR_DB_TYPE_RSL, 64, 940, 4, 1960},
|
|
{"cvmx_mio_uart2_srt" , CVMX_CSR_DB_TYPE_RSL, 64, 941, 2, 1964},
|
|
{"cvmx_mio_uart2_srts" , CVMX_CSR_DB_TYPE_RSL, 64, 942, 2, 1966},
|
|
{"cvmx_mio_uart2_stt" , CVMX_CSR_DB_TYPE_RSL, 64, 943, 2, 1968},
|
|
{"cvmx_mio_uart2_tfl" , CVMX_CSR_DB_TYPE_RSL, 64, 944, 2, 1970},
|
|
{"cvmx_mio_uart2_tfr" , CVMX_CSR_DB_TYPE_RSL, 64, 945, 2, 1972},
|
|
{"cvmx_mio_uart2_thr" , CVMX_CSR_DB_TYPE_RSL, 64, 946, 2, 1974},
|
|
{"cvmx_mio_uart2_usr" , CVMX_CSR_DB_TYPE_RSL, 64, 947, 6, 1976},
|
|
{"cvmx_mix#_bist" , CVMX_CSR_DB_TYPE_NCB, 64, 948, 5, 1982},
|
|
{"cvmx_mix#_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 950, 8, 1987},
|
|
{"cvmx_mix#_intena" , CVMX_CSR_DB_TYPE_NCB, 64, 952, 8, 1995},
|
|
{"cvmx_mix#_ircnt" , CVMX_CSR_DB_TYPE_NCB, 64, 954, 2, 2003},
|
|
{"cvmx_mix#_irhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 956, 3, 2005},
|
|
{"cvmx_mix#_iring1" , CVMX_CSR_DB_TYPE_NCB, 64, 958, 5, 2008},
|
|
{"cvmx_mix#_iring2" , CVMX_CSR_DB_TYPE_NCB, 64, 960, 4, 2013},
|
|
{"cvmx_mix#_isr" , CVMX_CSR_DB_TYPE_NCB, 64, 962, 8, 2017},
|
|
{"cvmx_mix#_orcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 964, 2, 2025},
|
|
{"cvmx_mix#_orhwm" , CVMX_CSR_DB_TYPE_NCB, 64, 966, 2, 2027},
|
|
{"cvmx_mix#_oring1" , CVMX_CSR_DB_TYPE_NCB, 64, 968, 5, 2029},
|
|
{"cvmx_mix#_oring2" , CVMX_CSR_DB_TYPE_NCB, 64, 970, 4, 2034},
|
|
{"cvmx_mix#_remcnt" , CVMX_CSR_DB_TYPE_NCB, 64, 972, 4, 2038},
|
|
{"cvmx_ndf_bt_pg_info" , CVMX_CSR_DB_TYPE_NCB, 64, 974, 4, 2042},
|
|
{"cvmx_ndf_cmd" , CVMX_CSR_DB_TYPE_NCB, 64, 975, 1, 2046},
|
|
{"cvmx_ndf_drbell" , CVMX_CSR_DB_TYPE_NCB, 64, 976, 2, 2047},
|
|
{"cvmx_ndf_ecc_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 977, 3, 2049},
|
|
{"cvmx_ndf_int" , CVMX_CSR_DB_TYPE_NCB, 64, 978, 8, 2052},
|
|
{"cvmx_ndf_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 979, 8, 2060},
|
|
{"cvmx_ndf_misc" , CVMX_CSR_DB_TYPE_NCB, 64, 980, 11, 2068},
|
|
{"cvmx_ndf_st_reg" , CVMX_CSR_DB_TYPE_NCB, 64, 981, 8, 2079},
|
|
{"cvmx_npei_bar1_index#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 982, 5, 2087},
|
|
{"cvmx_npei_bist_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1014, 58, 2092},
|
|
{"cvmx_npei_bist_status2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1015, 15, 2150},
|
|
{"cvmx_npei_ctl_port0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1016, 17, 2165},
|
|
{"cvmx_npei_ctl_port1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1017, 17, 2182},
|
|
{"cvmx_npei_ctl_status" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1018, 10, 2199},
|
|
{"cvmx_npei_ctl_status2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1019, 11, 2209},
|
|
{"cvmx_npei_data_out_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1020, 5, 2220},
|
|
{"cvmx_npei_dbg_data" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1021, 8, 2225},
|
|
{"cvmx_npei_dbg_select" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1022, 2, 2233},
|
|
{"cvmx_npei_dma#_counts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1023, 3, 2235},
|
|
{"cvmx_npei_dma#_dbell" , CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 1028, 2, 2238},
|
|
{"cvmx_npei_dma#_ibuff_saddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1033, 4, 2240},
|
|
{"cvmx_npei_dma#_naddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1038, 2, 2244},
|
|
{"cvmx_npei_dma0_int_level" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1043, 2, 2246},
|
|
{"cvmx_npei_dma1_int_level" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1044, 2, 2248},
|
|
{"cvmx_npei_dma_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1045, 2, 2250},
|
|
{"cvmx_npei_dma_control" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1046, 17, 2252},
|
|
{"cvmx_npei_dma_pcie_req_num" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1047, 15, 2269},
|
|
{"cvmx_npei_dma_state1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1048, 6, 2284},
|
|
{"cvmx_npei_dma_state2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1049, 6, 2290},
|
|
{"cvmx_npei_int_a_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1050, 11, 2296},
|
|
{"cvmx_npei_int_a_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1051, 11, 2307},
|
|
{"cvmx_npei_int_a_sum" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1052, 11, 2318},
|
|
{"cvmx_npei_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1053, 64, 2329},
|
|
{"cvmx_npei_int_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1054, 63, 2393},
|
|
{"cvmx_npei_int_info" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1055, 3, 2456},
|
|
{"cvmx_npei_int_sum" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1056, 64, 2459},
|
|
{"cvmx_npei_int_sum2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1057, 61, 2523},
|
|
{"cvmx_npei_last_win_rdata0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1058, 1, 2584},
|
|
{"cvmx_npei_last_win_rdata1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1059, 1, 2585},
|
|
{"cvmx_npei_mem_access_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1060, 3, 2586},
|
|
{"cvmx_npei_mem_access_subid#" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1061, 11, 2589},
|
|
{"cvmx_npei_msi_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1077, 1, 2600},
|
|
{"cvmx_npei_msi_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1078, 1, 2601},
|
|
{"cvmx_npei_msi_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1079, 1, 2602},
|
|
{"cvmx_npei_msi_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1080, 1, 2603},
|
|
{"cvmx_npei_msi_rcv0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1081, 1, 2604},
|
|
{"cvmx_npei_msi_rcv1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1082, 1, 2605},
|
|
{"cvmx_npei_msi_rcv2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1083, 1, 2606},
|
|
{"cvmx_npei_msi_rcv3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1084, 1, 2607},
|
|
{"cvmx_npei_msi_rd_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1085, 3, 2608},
|
|
{"cvmx_npei_msi_w1c_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1086, 1, 2611},
|
|
{"cvmx_npei_msi_w1c_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1087, 1, 2612},
|
|
{"cvmx_npei_msi_w1c_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1088, 1, 2613},
|
|
{"cvmx_npei_msi_w1c_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1089, 1, 2614},
|
|
{"cvmx_npei_msi_w1s_enb0" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1090, 1, 2615},
|
|
{"cvmx_npei_msi_w1s_enb1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1091, 1, 2616},
|
|
{"cvmx_npei_msi_w1s_enb2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1092, 1, 2617},
|
|
{"cvmx_npei_msi_w1s_enb3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1093, 1, 2618},
|
|
{"cvmx_npei_msi_wr_map" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1094, 3, 2619},
|
|
{"cvmx_npei_pcie_credit_cnt" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1095, 7, 2622},
|
|
{"cvmx_npei_pcie_msi_rcv" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1096, 2, 2629},
|
|
{"cvmx_npei_pcie_msi_rcv_b1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1097, 3, 2631},
|
|
{"cvmx_npei_pcie_msi_rcv_b2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1098, 3, 2634},
|
|
{"cvmx_npei_pcie_msi_rcv_b3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1099, 3, 2637},
|
|
{"cvmx_npei_pkt#_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1100, 3, 2640},
|
|
{"cvmx_npei_pkt#_in_bp" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1132, 2, 2643},
|
|
{"cvmx_npei_pkt#_instr_baddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1164, 2, 2645},
|
|
{"cvmx_npei_pkt#_instr_baoff_dbell", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1196, 2, 2647},
|
|
{"cvmx_npei_pkt#_instr_fifo_rsize", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1228, 5, 2649},
|
|
{"cvmx_npei_pkt#_instr_header" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1260, 13, 2654},
|
|
{"cvmx_npei_pkt#_slist_baddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1292, 2, 2667},
|
|
{"cvmx_npei_pkt#_slist_baoff_dbell", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1324, 2, 2669},
|
|
{"cvmx_npei_pkt#_slist_fifo_rsize", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1356, 2, 2671},
|
|
{"cvmx_npei_pkt_cnt_int" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1388, 2, 2673},
|
|
{"cvmx_npei_pkt_cnt_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1389, 2, 2675},
|
|
{"cvmx_npei_pkt_data_out_es" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1390, 1, 2677},
|
|
{"cvmx_npei_pkt_data_out_ns" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1391, 2, 2678},
|
|
{"cvmx_npei_pkt_data_out_ror" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1392, 2, 2680},
|
|
{"cvmx_npei_pkt_dpaddr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1393, 2, 2682},
|
|
{"cvmx_npei_pkt_in_bp" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1394, 2, 2684},
|
|
{"cvmx_npei_pkt_in_done#_cnts" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1395, 2, 2686},
|
|
{"cvmx_npei_pkt_in_instr_counts", CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1427, 2, 2688},
|
|
{"cvmx_npei_pkt_in_pcie_port" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1428, 1, 2690},
|
|
{"cvmx_npei_pkt_input_control" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1429, 10, 2691},
|
|
{"cvmx_npei_pkt_instr_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1430, 2, 2701},
|
|
{"cvmx_npei_pkt_instr_rd_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1431, 1, 2703},
|
|
{"cvmx_npei_pkt_instr_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1432, 2, 2704},
|
|
{"cvmx_npei_pkt_int_levels" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1433, 3, 2706},
|
|
{"cvmx_npei_pkt_iptr" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1434, 2, 2709},
|
|
{"cvmx_npei_pkt_out_bmode" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1435, 2, 2711},
|
|
{"cvmx_npei_pkt_out_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1436, 2, 2713},
|
|
{"cvmx_npei_pkt_output_wmark" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1437, 2, 2715},
|
|
{"cvmx_npei_pkt_pcie_port" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1438, 1, 2717},
|
|
{"cvmx_npei_pkt_port_in_rst" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1439, 2, 2718},
|
|
{"cvmx_npei_pkt_slist_es" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1440, 1, 2720},
|
|
{"cvmx_npei_pkt_slist_id_size" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1441, 3, 2721},
|
|
{"cvmx_npei_pkt_slist_ns" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1442, 2, 2724},
|
|
{"cvmx_npei_pkt_slist_ror" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1443, 2, 2726},
|
|
{"cvmx_npei_pkt_time_int" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1444, 2, 2728},
|
|
{"cvmx_npei_pkt_time_int_enb" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1445, 2, 2730},
|
|
{"cvmx_npei_rsl_int_blocks" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1446, 29, 2732},
|
|
{"cvmx_npei_scratch_1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1447, 1, 2761},
|
|
{"cvmx_npei_state1" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1448, 4, 2762},
|
|
{"cvmx_npei_state2" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1449, 7, 2766},
|
|
{"cvmx_npei_state3" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1450, 5, 2773},
|
|
{"cvmx_npei_win_rd_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 1451, 4, 2778},
|
|
{"cvmx_npei_win_rd_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 1452, 1, 2782},
|
|
{"cvmx_npei_win_wr_addr" , CVMX_CSR_DB_TYPE_PEXP, 64, 1453, 4, 2783},
|
|
{"cvmx_npei_win_wr_data" , CVMX_CSR_DB_TYPE_PEXP, 64, 1454, 1, 2787},
|
|
{"cvmx_npei_win_wr_mask" , CVMX_CSR_DB_TYPE_PEXP, 64, 1455, 2, 2788},
|
|
{"cvmx_npei_window_ctl" , CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 1456, 2, 2790},
|
|
{"cvmx_pcieep_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1457, 2, 2792},
|
|
{"cvmx_pcieep_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1458, 24, 2794},
|
|
{"cvmx_pcieep_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1459, 4, 2818},
|
|
{"cvmx_pcieep_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1460, 5, 2822},
|
|
{"cvmx_pcieep_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1461, 5, 2827},
|
|
{"cvmx_pcieep_cfg004_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1462, 2, 2832},
|
|
{"cvmx_pcieep_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1463, 1, 2834},
|
|
{"cvmx_pcieep_cfg005_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1464, 1, 2835},
|
|
{"cvmx_pcieep_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1465, 5, 2836},
|
|
{"cvmx_pcieep_cfg006_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1466, 2, 2841},
|
|
{"cvmx_pcieep_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1467, 1, 2843},
|
|
{"cvmx_pcieep_cfg007_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1468, 1, 2844},
|
|
{"cvmx_pcieep_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1469, 4, 2845},
|
|
{"cvmx_pcieep_cfg008_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1470, 2, 2849},
|
|
{"cvmx_pcieep_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1471, 2, 2851},
|
|
{"cvmx_pcieep_cfg009_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1472, 1, 2853},
|
|
{"cvmx_pcieep_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1473, 1, 2854},
|
|
{"cvmx_pcieep_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1474, 2, 2855},
|
|
{"cvmx_pcieep_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1475, 3, 2857},
|
|
{"cvmx_pcieep_cfg012_mask" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1476, 2, 2860},
|
|
{"cvmx_pcieep_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1477, 2, 2862},
|
|
{"cvmx_pcieep_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1478, 4, 2864},
|
|
{"cvmx_pcieep_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1479, 10, 2868},
|
|
{"cvmx_pcieep_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1480, 12, 2878},
|
|
{"cvmx_pcieep_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1481, 7, 2890},
|
|
{"cvmx_pcieep_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1482, 2, 2897},
|
|
{"cvmx_pcieep_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1483, 1, 2899},
|
|
{"cvmx_pcieep_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1484, 2, 2900},
|
|
{"cvmx_pcieep_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1485, 7, 2902},
|
|
{"cvmx_pcieep_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1486, 11, 2909},
|
|
{"cvmx_pcieep_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1487, 19, 2920},
|
|
{"cvmx_pcieep_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1488, 11, 2939},
|
|
{"cvmx_pcieep_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1489, 17, 2950},
|
|
{"cvmx_pcieep_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1490, 12, 2967},
|
|
{"cvmx_pcieep_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1491, 22, 2979},
|
|
{"cvmx_pcieep_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1492, 3, 3001},
|
|
{"cvmx_pcieep_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1493, 3, 3004},
|
|
{"cvmx_pcieep_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1494, 1, 3007},
|
|
{"cvmx_pcieep_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1495, 1, 3008},
|
|
{"cvmx_pcieep_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1496, 1, 3009},
|
|
{"cvmx_pcieep_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1497, 1, 3010},
|
|
{"cvmx_pcieep_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1498, 3, 3011},
|
|
{"cvmx_pcieep_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1499, 14, 3014},
|
|
{"cvmx_pcieep_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1500, 14, 3028},
|
|
{"cvmx_pcieep_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1501, 14, 3042},
|
|
{"cvmx_pcieep_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1502, 9, 3056},
|
|
{"cvmx_pcieep_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1503, 9, 3065},
|
|
{"cvmx_pcieep_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1504, 6, 3074},
|
|
{"cvmx_pcieep_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1505, 1, 3080},
|
|
{"cvmx_pcieep_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1506, 1, 3081},
|
|
{"cvmx_pcieep_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1507, 1, 3082},
|
|
{"cvmx_pcieep_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1508, 1, 3083},
|
|
{"cvmx_pcieep_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1509, 2, 3084},
|
|
{"cvmx_pcieep_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1510, 1, 3086},
|
|
{"cvmx_pcieep_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1511, 6, 3087},
|
|
{"cvmx_pcieep_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1512, 6, 3093},
|
|
{"cvmx_pcieep_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1513, 13, 3099},
|
|
{"cvmx_pcieep_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1514, 5, 3112},
|
|
{"cvmx_pcieep_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1515, 8, 3117},
|
|
{"cvmx_pcieep_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1516, 19, 3125},
|
|
{"cvmx_pcieep_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1517, 3, 3144},
|
|
{"cvmx_pcieep_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1518, 1, 3147},
|
|
{"cvmx_pcieep_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1519, 1, 3148},
|
|
{"cvmx_pcieep_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1520, 3, 3149},
|
|
{"cvmx_pcieep_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1521, 3, 3152},
|
|
{"cvmx_pcieep_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1522, 3, 3155},
|
|
{"cvmx_pcieep_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1523, 4, 3158},
|
|
{"cvmx_pcieep_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1524, 4, 3162},
|
|
{"cvmx_pcieep_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1525, 4, 3166},
|
|
{"cvmx_pcieep_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1526, 7, 3170},
|
|
{"cvmx_pcieep_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1527, 5, 3177},
|
|
{"cvmx_pcieep_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1528, 5, 3182},
|
|
{"cvmx_pcieep_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1529, 4, 3187},
|
|
{"cvmx_pcieep_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1530, 4, 3191},
|
|
{"cvmx_pcieep_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1531, 4, 3195},
|
|
{"cvmx_pcieep_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1532, 1, 3199},
|
|
{"cvmx_pcieep_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 1533, 1, 3200},
|
|
{"cvmx_pcierc#_cfg000" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1534, 2, 3201},
|
|
{"cvmx_pcierc#_cfg001" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1536, 24, 3203},
|
|
{"cvmx_pcierc#_cfg002" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1538, 4, 3227},
|
|
{"cvmx_pcierc#_cfg003" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1540, 5, 3231},
|
|
{"cvmx_pcierc#_cfg004" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1542, 1, 3236},
|
|
{"cvmx_pcierc#_cfg005" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1544, 1, 3237},
|
|
{"cvmx_pcierc#_cfg006" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1546, 4, 3238},
|
|
{"cvmx_pcierc#_cfg007" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1548, 17, 3242},
|
|
{"cvmx_pcierc#_cfg008" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1550, 4, 3259},
|
|
{"cvmx_pcierc#_cfg009" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1552, 6, 3263},
|
|
{"cvmx_pcierc#_cfg010" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1554, 1, 3269},
|
|
{"cvmx_pcierc#_cfg011" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1556, 1, 3270},
|
|
{"cvmx_pcierc#_cfg012" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1558, 2, 3271},
|
|
{"cvmx_pcierc#_cfg013" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1560, 2, 3273},
|
|
{"cvmx_pcierc#_cfg014" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1562, 1, 3275},
|
|
{"cvmx_pcierc#_cfg015" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1564, 15, 3276},
|
|
{"cvmx_pcierc#_cfg016" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1566, 10, 3291},
|
|
{"cvmx_pcierc#_cfg017" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1568, 12, 3301},
|
|
{"cvmx_pcierc#_cfg020" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1570, 7, 3313},
|
|
{"cvmx_pcierc#_cfg021" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1572, 2, 3320},
|
|
{"cvmx_pcierc#_cfg022" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1574, 1, 3322},
|
|
{"cvmx_pcierc#_cfg023" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1576, 2, 3323},
|
|
{"cvmx_pcierc#_cfg028" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1578, 7, 3325},
|
|
{"cvmx_pcierc#_cfg029" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1580, 11, 3332},
|
|
{"cvmx_pcierc#_cfg030" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1582, 19, 3343},
|
|
{"cvmx_pcierc#_cfg031" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1584, 11, 3362},
|
|
{"cvmx_pcierc#_cfg032" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1586, 20, 3373},
|
|
{"cvmx_pcierc#_cfg033" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1588, 12, 3393},
|
|
{"cvmx_pcierc#_cfg034" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1590, 22, 3405},
|
|
{"cvmx_pcierc#_cfg035" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1592, 8, 3427},
|
|
{"cvmx_pcierc#_cfg036" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1594, 4, 3435},
|
|
{"cvmx_pcierc#_cfg037" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1596, 3, 3439},
|
|
{"cvmx_pcierc#_cfg038" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1598, 3, 3442},
|
|
{"cvmx_pcierc#_cfg039" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1600, 1, 3445},
|
|
{"cvmx_pcierc#_cfg040" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1602, 1, 3446},
|
|
{"cvmx_pcierc#_cfg041" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1604, 1, 3447},
|
|
{"cvmx_pcierc#_cfg042" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1606, 1, 3448},
|
|
{"cvmx_pcierc#_cfg064" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1608, 3, 3449},
|
|
{"cvmx_pcierc#_cfg065" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1610, 14, 3452},
|
|
{"cvmx_pcierc#_cfg066" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1612, 14, 3466},
|
|
{"cvmx_pcierc#_cfg067" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1614, 14, 3480},
|
|
{"cvmx_pcierc#_cfg068" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1616, 9, 3494},
|
|
{"cvmx_pcierc#_cfg069" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1618, 9, 3503},
|
|
{"cvmx_pcierc#_cfg070" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1620, 6, 3512},
|
|
{"cvmx_pcierc#_cfg071" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1622, 1, 3518},
|
|
{"cvmx_pcierc#_cfg072" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1624, 1, 3519},
|
|
{"cvmx_pcierc#_cfg073" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1626, 1, 3520},
|
|
{"cvmx_pcierc#_cfg074" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1628, 1, 3521},
|
|
{"cvmx_pcierc#_cfg075" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1630, 4, 3522},
|
|
{"cvmx_pcierc#_cfg076" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1632, 9, 3526},
|
|
{"cvmx_pcierc#_cfg077" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1634, 2, 3535},
|
|
{"cvmx_pcierc#_cfg448" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1636, 2, 3537},
|
|
{"cvmx_pcierc#_cfg449" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1638, 1, 3539},
|
|
{"cvmx_pcierc#_cfg450" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1640, 6, 3540},
|
|
{"cvmx_pcierc#_cfg451" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1642, 6, 3546},
|
|
{"cvmx_pcierc#_cfg452" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1644, 13, 3552},
|
|
{"cvmx_pcierc#_cfg453" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1646, 5, 3565},
|
|
{"cvmx_pcierc#_cfg454" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1648, 8, 3570},
|
|
{"cvmx_pcierc#_cfg455" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1650, 19, 3578},
|
|
{"cvmx_pcierc#_cfg456" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1652, 3, 3597},
|
|
{"cvmx_pcierc#_cfg458" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1654, 1, 3600},
|
|
{"cvmx_pcierc#_cfg459" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1656, 1, 3601},
|
|
{"cvmx_pcierc#_cfg460" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1658, 3, 3602},
|
|
{"cvmx_pcierc#_cfg461" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1660, 3, 3605},
|
|
{"cvmx_pcierc#_cfg462" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1662, 3, 3608},
|
|
{"cvmx_pcierc#_cfg463" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1664, 4, 3611},
|
|
{"cvmx_pcierc#_cfg464" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1666, 4, 3615},
|
|
{"cvmx_pcierc#_cfg465" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1668, 4, 3619},
|
|
{"cvmx_pcierc#_cfg466" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1670, 7, 3623},
|
|
{"cvmx_pcierc#_cfg467" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1672, 5, 3630},
|
|
{"cvmx_pcierc#_cfg468" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1674, 5, 3635},
|
|
{"cvmx_pcierc#_cfg490" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1676, 4, 3640},
|
|
{"cvmx_pcierc#_cfg491" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1678, 4, 3644},
|
|
{"cvmx_pcierc#_cfg492" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1680, 4, 3648},
|
|
{"cvmx_pcierc#_cfg516" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1682, 1, 3652},
|
|
{"cvmx_pcierc#_cfg517" , CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 1684, 1, 3653},
|
|
{"cvmx_pcs#_an#_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1686, 9, 3654},
|
|
{"cvmx_pcs#_an#_ext_st_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1690, 6, 3663},
|
|
{"cvmx_pcs#_an#_lp_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1694, 9, 3669},
|
|
{"cvmx_pcs#_an#_results_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1698, 6, 3678},
|
|
{"cvmx_pcs#_int#_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1702, 13, 3684},
|
|
{"cvmx_pcs#_int#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1706, 13, 3697},
|
|
{"cvmx_pcs#_link#_timer_count_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1710, 2, 3710},
|
|
{"cvmx_pcs#_log_anl#_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1714, 4, 3712},
|
|
{"cvmx_pcs#_misc#_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1718, 8, 3716},
|
|
{"cvmx_pcs#_mr#_control_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1722, 13, 3724},
|
|
{"cvmx_pcs#_mr#_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1726, 17, 3737},
|
|
{"cvmx_pcs#_rx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1730, 7, 3754},
|
|
{"cvmx_pcs#_rx#_sync_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1734, 3, 3761},
|
|
{"cvmx_pcs#_sgm#_an_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1738, 8, 3764},
|
|
{"cvmx_pcs#_sgm#_lp_adv_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1742, 7, 3772},
|
|
{"cvmx_pcs#_tx#_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1746, 4, 3779},
|
|
{"cvmx_pcs#_tx_rx#_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1750, 5, 3783},
|
|
{"cvmx_pcsx#_10gbx_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1754, 8, 3788},
|
|
{"cvmx_pcsx#_bist_status_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1756, 2, 3796},
|
|
{"cvmx_pcsx#_bit_lock_status_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1758, 5, 3798},
|
|
{"cvmx_pcsx#_control1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1760, 10, 3803},
|
|
{"cvmx_pcsx#_control2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1762, 2, 3813},
|
|
{"cvmx_pcsx#_int_en_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1764, 7, 3815},
|
|
{"cvmx_pcsx#_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1766, 7, 3822},
|
|
{"cvmx_pcsx#_log_anl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1768, 6, 3829},
|
|
{"cvmx_pcsx#_misc_ctl_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1770, 5, 3835},
|
|
{"cvmx_pcsx#_rx_sync_states_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1772, 5, 3840},
|
|
{"cvmx_pcsx#_spd_abil_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1774, 3, 3845},
|
|
{"cvmx_pcsx#_status1_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1776, 6, 3848},
|
|
{"cvmx_pcsx#_status2_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1778, 9, 3854},
|
|
{"cvmx_pcsx#_tx_rx_polarity_reg", CVMX_CSR_DB_TYPE_RSL, 64, 1780, 5, 3863},
|
|
{"cvmx_pcsx#_tx_rx_states_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1782, 10, 3868},
|
|
{"cvmx_pesc#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1784, 14, 3878},
|
|
{"cvmx_pesc#_bist_status2" , CVMX_CSR_DB_TYPE_RSL, 64, 1786, 15, 3892},
|
|
{"cvmx_pesc#_cfg_rd" , CVMX_CSR_DB_TYPE_RSL, 64, 1788, 2, 3907},
|
|
{"cvmx_pesc#_cfg_wr" , CVMX_CSR_DB_TYPE_RSL, 64, 1790, 2, 3909},
|
|
{"cvmx_pesc#_cpl_lut_valid" , CVMX_CSR_DB_TYPE_RSL, 64, 1792, 2, 3911},
|
|
{"cvmx_pesc#_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1794, 16, 3913},
|
|
{"cvmx_pesc#_ctl_status2" , CVMX_CSR_DB_TYPE_RSL, 64, 1796, 3, 3929},
|
|
{"cvmx_pesc#_dbg_info" , CVMX_CSR_DB_TYPE_RSL, 64, 1798, 32, 3932},
|
|
{"cvmx_pesc#_dbg_info_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1800, 32, 3964},
|
|
{"cvmx_pesc#_diag_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1802, 5, 3996},
|
|
{"cvmx_pesc#_p2n_bar0_start" , CVMX_CSR_DB_TYPE_RSL, 64, 1804, 2, 4001},
|
|
{"cvmx_pesc#_p2n_bar1_start" , CVMX_CSR_DB_TYPE_RSL, 64, 1806, 2, 4003},
|
|
{"cvmx_pesc#_p2n_bar2_start" , CVMX_CSR_DB_TYPE_RSL, 64, 1808, 2, 4005},
|
|
{"cvmx_pesc#_p2p_bar#_end" , CVMX_CSR_DB_TYPE_RSL, 64, 1810, 2, 4007},
|
|
{"cvmx_pesc#_p2p_bar#_start" , CVMX_CSR_DB_TYPE_RSL, 64, 1818, 2, 4009},
|
|
{"cvmx_pesc#_tlp_credits" , CVMX_CSR_DB_TYPE_RSL, 64, 1826, 8, 4011},
|
|
{"cvmx_pip_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 1828, 2, 4019},
|
|
{"cvmx_pip_dec_ipsec#" , CVMX_CSR_DB_TYPE_RSL, 64, 1829, 4, 4021},
|
|
{"cvmx_pip_dsa_src_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 1833, 16, 4025},
|
|
{"cvmx_pip_dsa_vid_grp" , CVMX_CSR_DB_TYPE_RSL, 64, 1834, 16, 4041},
|
|
{"cvmx_pip_frm_len_chk#" , CVMX_CSR_DB_TYPE_RSL, 64, 1835, 3, 4057},
|
|
{"cvmx_pip_gbl_cfg" , CVMX_CSR_DB_TYPE_RSL, 64, 1837, 8, 4060},
|
|
{"cvmx_pip_gbl_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 1838, 22, 4068},
|
|
{"cvmx_pip_hg_pri_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 1839, 6, 4090},
|
|
{"cvmx_pip_int_en" , CVMX_CSR_DB_TYPE_RSL, 64, 1840, 14, 4096},
|
|
{"cvmx_pip_int_reg" , CVMX_CSR_DB_TYPE_RSL, 64, 1841, 14, 4110},
|
|
{"cvmx_pip_ip_offset" , CVMX_CSR_DB_TYPE_RSL, 64, 1842, 2, 4124},
|
|
{"cvmx_pip_prt_cfg#" , CVMX_CSR_DB_TYPE_RSL, 64, 1843, 28, 4126},
|
|
{"cvmx_pip_prt_tag#" , CVMX_CSR_DB_TYPE_RSL, 64, 1855, 25, 4154},
|
|
{"cvmx_pip_qos_diff#" , CVMX_CSR_DB_TYPE_RSL, 64, 1867, 2, 4179},
|
|
{"cvmx_pip_qos_vlan#" , CVMX_CSR_DB_TYPE_RSL, 64, 1931, 4, 4181},
|
|
{"cvmx_pip_qos_watch#" , CVMX_CSR_DB_TYPE_RSL, 64, 1939, 9, 4185},
|
|
{"cvmx_pip_raw_word" , CVMX_CSR_DB_TYPE_RSL, 64, 1947, 2, 4194},
|
|
{"cvmx_pip_sft_rst" , CVMX_CSR_DB_TYPE_RSL, 64, 1948, 2, 4196},
|
|
{"cvmx_pip_stat0_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1949, 2, 4198},
|
|
{"cvmx_pip_stat1_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1961, 2, 4200},
|
|
{"cvmx_pip_stat2_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1973, 2, 4202},
|
|
{"cvmx_pip_stat3_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1985, 2, 4204},
|
|
{"cvmx_pip_stat4_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 1997, 2, 4206},
|
|
{"cvmx_pip_stat5_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2009, 2, 4208},
|
|
{"cvmx_pip_stat6_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2021, 2, 4210},
|
|
{"cvmx_pip_stat7_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2033, 2, 4212},
|
|
{"cvmx_pip_stat8_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2045, 2, 4214},
|
|
{"cvmx_pip_stat9_prt#" , CVMX_CSR_DB_TYPE_RSL, 64, 2057, 2, 4216},
|
|
{"cvmx_pip_stat_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2069, 2, 4218},
|
|
{"cvmx_pip_stat_inb_errs#" , CVMX_CSR_DB_TYPE_RSL, 64, 2070, 2, 4220},
|
|
{"cvmx_pip_stat_inb_octs#" , CVMX_CSR_DB_TYPE_RSL, 64, 2082, 2, 4222},
|
|
{"cvmx_pip_stat_inb_pkts#" , CVMX_CSR_DB_TYPE_RSL, 64, 2094, 2, 4224},
|
|
{"cvmx_pip_tag_inc#" , CVMX_CSR_DB_TYPE_RSL, 64, 2106, 2, 4226},
|
|
{"cvmx_pip_tag_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2170, 2, 4228},
|
|
{"cvmx_pip_tag_secret" , CVMX_CSR_DB_TYPE_RSL, 64, 2171, 3, 4230},
|
|
{"cvmx_pip_todo_entry" , CVMX_CSR_DB_TYPE_RSL, 64, 2172, 3, 4233},
|
|
{"cvmx_pko_mem_count0" , CVMX_CSR_DB_TYPE_RSL, 64, 2173, 2, 4236},
|
|
{"cvmx_pko_mem_count1" , CVMX_CSR_DB_TYPE_RSL, 64, 2174, 2, 4238},
|
|
{"cvmx_pko_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2175, 4, 4240},
|
|
{"cvmx_pko_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2176, 5, 4244},
|
|
{"cvmx_pko_mem_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 2177, 4, 4249},
|
|
{"cvmx_pko_mem_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 2178, 8, 4253},
|
|
{"cvmx_pko_mem_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 2179, 4, 4261},
|
|
{"cvmx_pko_mem_debug13" , CVMX_CSR_DB_TYPE_RSL, 64, 2180, 5, 4265},
|
|
{"cvmx_pko_mem_debug14" , CVMX_CSR_DB_TYPE_RSL, 64, 2181, 1, 4270},
|
|
{"cvmx_pko_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2182, 5, 4271},
|
|
{"cvmx_pko_mem_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2183, 1, 4276},
|
|
{"cvmx_pko_mem_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 2184, 13, 4277},
|
|
{"cvmx_pko_mem_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 2185, 4, 4290},
|
|
{"cvmx_pko_mem_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 2186, 13, 4294},
|
|
{"cvmx_pko_mem_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 2187, 6, 4307},
|
|
{"cvmx_pko_mem_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 2188, 9, 4313},
|
|
{"cvmx_pko_mem_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 2189, 4, 4322},
|
|
{"cvmx_pko_mem_port_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 2190, 7, 4326},
|
|
{"cvmx_pko_mem_port_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 2191, 5, 4333},
|
|
{"cvmx_pko_mem_port_rate0" , CVMX_CSR_DB_TYPE_RSL, 64, 2192, 5, 4338},
|
|
{"cvmx_pko_mem_port_rate1" , CVMX_CSR_DB_TYPE_RSL, 64, 2193, 4, 4343},
|
|
{"cvmx_pko_mem_queue_ptrs" , CVMX_CSR_DB_TYPE_RSL, 64, 2194, 9, 4347},
|
|
{"cvmx_pko_mem_queue_qos" , CVMX_CSR_DB_TYPE_RSL, 64, 2195, 5, 4356},
|
|
{"cvmx_pko_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2196, 16, 4361},
|
|
{"cvmx_pko_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2197, 4, 4377},
|
|
{"cvmx_pko_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2198, 1, 4381},
|
|
{"cvmx_pko_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2199, 1, 4382},
|
|
{"cvmx_pko_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2200, 1, 4383},
|
|
{"cvmx_pko_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2201, 1, 4384},
|
|
{"cvmx_pko_reg_engine_inflight", CVMX_CSR_DB_TYPE_RSL, 64, 2202, 11, 4385},
|
|
{"cvmx_pko_reg_engine_thresh" , CVMX_CSR_DB_TYPE_RSL, 64, 2203, 2, 4396},
|
|
{"cvmx_pko_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2204, 4, 4398},
|
|
{"cvmx_pko_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2205, 5, 4402},
|
|
{"cvmx_pko_reg_gmx_port_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2206, 3, 4407},
|
|
{"cvmx_pko_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2207, 4, 4410},
|
|
{"cvmx_pko_reg_queue_mode" , CVMX_CSR_DB_TYPE_RSL, 64, 2208, 2, 4414},
|
|
{"cvmx_pko_reg_queue_ptrs1" , CVMX_CSR_DB_TYPE_RSL, 64, 2209, 3, 4416},
|
|
{"cvmx_pko_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2210, 3, 4419},
|
|
{"cvmx_pow_bist_stat" , CVMX_CSR_DB_TYPE_NCB, 64, 2211, 12, 4422},
|
|
{"cvmx_pow_ds_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2212, 2, 4434},
|
|
{"cvmx_pow_ecc_err" , CVMX_CSR_DB_TYPE_NCB, 64, 2213, 13, 4436},
|
|
{"cvmx_pow_int_ctl" , CVMX_CSR_DB_TYPE_NCB, 64, 2214, 3, 4449},
|
|
{"cvmx_pow_iq_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2215, 2, 4452},
|
|
{"cvmx_pow_iq_com_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2223, 2, 4454},
|
|
{"cvmx_pow_iq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 2224, 2, 4456},
|
|
{"cvmx_pow_iq_int_en" , CVMX_CSR_DB_TYPE_NCB, 64, 2225, 2, 4458},
|
|
{"cvmx_pow_iq_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2226, 2, 4460},
|
|
{"cvmx_pow_nos_cnt" , CVMX_CSR_DB_TYPE_NCB, 64, 2234, 2, 4462},
|
|
{"cvmx_pow_nw_tim" , CVMX_CSR_DB_TYPE_NCB, 64, 2235, 2, 4464},
|
|
{"cvmx_pow_pf_rst_msk" , CVMX_CSR_DB_TYPE_NCB, 64, 2236, 2, 4466},
|
|
{"cvmx_pow_pp_grp_msk#" , CVMX_CSR_DB_TYPE_NCB, 64, 2237, 10, 4468},
|
|
{"cvmx_pow_qos_rnd#" , CVMX_CSR_DB_TYPE_NCB, 64, 2241, 5, 4478},
|
|
{"cvmx_pow_qos_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2249, 10, 4483},
|
|
{"cvmx_pow_ts_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2257, 2, 4493},
|
|
{"cvmx_pow_wa_com_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2258, 2, 4495},
|
|
{"cvmx_pow_wa_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2259, 2, 4497},
|
|
{"cvmx_pow_wq_int" , CVMX_CSR_DB_TYPE_NCB, 64, 2267, 3, 4499},
|
|
{"cvmx_pow_wq_int_cnt#" , CVMX_CSR_DB_TYPE_NCB, 64, 2268, 6, 4502},
|
|
{"cvmx_pow_wq_int_pc" , CVMX_CSR_DB_TYPE_NCB, 64, 2284, 5, 4508},
|
|
{"cvmx_pow_wq_int_thr#" , CVMX_CSR_DB_TYPE_NCB, 64, 2285, 7, 4513},
|
|
{"cvmx_pow_ws_pc#" , CVMX_CSR_DB_TYPE_NCB, 64, 2301, 2, 4520},
|
|
{"cvmx_rad_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2317, 1, 4522},
|
|
{"cvmx_rad_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2318, 1, 4523},
|
|
{"cvmx_rad_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2319, 1, 4524},
|
|
{"cvmx_rad_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2320, 5, 4525},
|
|
{"cvmx_rad_reg_cmd_buf" , CVMX_CSR_DB_TYPE_RSL, 64, 2321, 5, 4530},
|
|
{"cvmx_rad_reg_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2322, 4, 4535},
|
|
{"cvmx_rad_reg_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2323, 10, 4539},
|
|
{"cvmx_rad_reg_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2324, 1, 4549},
|
|
{"cvmx_rad_reg_debug10" , CVMX_CSR_DB_TYPE_RSL, 64, 2325, 3, 4550},
|
|
{"cvmx_rad_reg_debug11" , CVMX_CSR_DB_TYPE_RSL, 64, 2326, 7, 4553},
|
|
{"cvmx_rad_reg_debug12" , CVMX_CSR_DB_TYPE_RSL, 64, 2327, 2, 4560},
|
|
{"cvmx_rad_reg_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2328, 1, 4562},
|
|
{"cvmx_rad_reg_debug3" , CVMX_CSR_DB_TYPE_RSL, 64, 2329, 1, 4563},
|
|
{"cvmx_rad_reg_debug4" , CVMX_CSR_DB_TYPE_RSL, 64, 2330, 1, 4564},
|
|
{"cvmx_rad_reg_debug5" , CVMX_CSR_DB_TYPE_RSL, 64, 2331, 18, 4565},
|
|
{"cvmx_rad_reg_debug6" , CVMX_CSR_DB_TYPE_RSL, 64, 2332, 3, 4583},
|
|
{"cvmx_rad_reg_debug7" , CVMX_CSR_DB_TYPE_RSL, 64, 2333, 2, 4586},
|
|
{"cvmx_rad_reg_debug8" , CVMX_CSR_DB_TYPE_RSL, 64, 2334, 3, 4588},
|
|
{"cvmx_rad_reg_debug9" , CVMX_CSR_DB_TYPE_RSL, 64, 2335, 7, 4591},
|
|
{"cvmx_rad_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2336, 2, 4598},
|
|
{"cvmx_rad_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2337, 2, 4600},
|
|
{"cvmx_rad_reg_polynomial" , CVMX_CSR_DB_TYPE_RSL, 64, 2338, 2, 4602},
|
|
{"cvmx_rad_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2339, 3, 4604},
|
|
{"cvmx_rnm_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2340, 3, 4607},
|
|
{"cvmx_rnm_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2341, 7, 4610},
|
|
{"cvmx_smi#_clk" , CVMX_CSR_DB_TYPE_RSL, 64, 2342, 10, 4617},
|
|
{"cvmx_smi#_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2344, 6, 4627},
|
|
{"cvmx_smi#_en" , CVMX_CSR_DB_TYPE_RSL, 64, 2346, 2, 4633},
|
|
{"cvmx_smi#_rd_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2348, 4, 4635},
|
|
{"cvmx_smi#_wr_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2350, 4, 4639},
|
|
{"cvmx_tim_mem_debug0" , CVMX_CSR_DB_TYPE_RSL, 64, 2352, 6, 4643},
|
|
{"cvmx_tim_mem_debug1" , CVMX_CSR_DB_TYPE_RSL, 64, 2353, 3, 4649},
|
|
{"cvmx_tim_mem_debug2" , CVMX_CSR_DB_TYPE_RSL, 64, 2354, 5, 4652},
|
|
{"cvmx_tim_mem_ring0" , CVMX_CSR_DB_TYPE_RSL, 64, 2355, 4, 4657},
|
|
{"cvmx_tim_mem_ring1" , CVMX_CSR_DB_TYPE_RSL, 64, 2356, 6, 4661},
|
|
{"cvmx_tim_reg_bist_result" , CVMX_CSR_DB_TYPE_RSL, 64, 2357, 4, 4667},
|
|
{"cvmx_tim_reg_error" , CVMX_CSR_DB_TYPE_RSL, 64, 2358, 2, 4671},
|
|
{"cvmx_tim_reg_flags" , CVMX_CSR_DB_TYPE_RSL, 64, 2359, 4, 4673},
|
|
{"cvmx_tim_reg_int_mask" , CVMX_CSR_DB_TYPE_RSL, 64, 2360, 2, 4677},
|
|
{"cvmx_tim_reg_read_idx" , CVMX_CSR_DB_TYPE_RSL, 64, 2361, 3, 4679},
|
|
{"cvmx_tra_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2362, 4, 4682},
|
|
{"cvmx_tra_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2363, 12, 4686},
|
|
{"cvmx_tra_cycles_since" , CVMX_CSR_DB_TYPE_RSL, 64, 2364, 3, 4698},
|
|
{"cvmx_tra_cycles_since1" , CVMX_CSR_DB_TYPE_RSL, 64, 2365, 5, 4701},
|
|
{"cvmx_tra_filt_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2366, 2, 4706},
|
|
{"cvmx_tra_filt_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2367, 2, 4708},
|
|
{"cvmx_tra_filt_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2368, 18, 4710},
|
|
{"cvmx_tra_filt_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2369, 12, 4728},
|
|
{"cvmx_tra_filt_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2370, 6, 4740},
|
|
{"cvmx_tra_int_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2371, 5, 4746},
|
|
{"cvmx_tra_read_dat" , CVMX_CSR_DB_TYPE_RSL, 64, 2372, 1, 4751},
|
|
{"cvmx_tra_trig0_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2373, 2, 4752},
|
|
{"cvmx_tra_trig0_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2374, 2, 4754},
|
|
{"cvmx_tra_trig0_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2375, 18, 4756},
|
|
{"cvmx_tra_trig0_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2376, 12, 4774},
|
|
{"cvmx_tra_trig0_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2377, 6, 4786},
|
|
{"cvmx_tra_trig1_adr_adr" , CVMX_CSR_DB_TYPE_RSL, 64, 2378, 2, 4792},
|
|
{"cvmx_tra_trig1_adr_msk" , CVMX_CSR_DB_TYPE_RSL, 64, 2379, 2, 4794},
|
|
{"cvmx_tra_trig1_cmd" , CVMX_CSR_DB_TYPE_RSL, 64, 2380, 18, 4796},
|
|
{"cvmx_tra_trig1_did" , CVMX_CSR_DB_TYPE_RSL, 64, 2381, 12, 4814},
|
|
{"cvmx_tra_trig1_sid" , CVMX_CSR_DB_TYPE_RSL, 64, 2382, 6, 4826},
|
|
{"cvmx_usbc#_daint" , CVMX_CSR_DB_TYPE_NCB, 32, 2383, 2, 4832},
|
|
{"cvmx_usbc#_daintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 2385, 2, 4834},
|
|
{"cvmx_usbc#_dcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 2387, 8, 4836},
|
|
{"cvmx_usbc#_dctl" , CVMX_CSR_DB_TYPE_NCB, 32, 2389, 11, 4844},
|
|
{"cvmx_usbc#_diepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 2391, 15, 4855},
|
|
{"cvmx_usbc#_diepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 2401, 8, 4870},
|
|
{"cvmx_usbc#_diepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 2411, 8, 4878},
|
|
{"cvmx_usbc#_dieptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 2413, 4, 4886},
|
|
{"cvmx_usbc#_doepctl#" , CVMX_CSR_DB_TYPE_NCB, 32, 2423, 15, 4890},
|
|
{"cvmx_usbc#_doepint#" , CVMX_CSR_DB_TYPE_NCB, 32, 2433, 6, 4905},
|
|
{"cvmx_usbc#_doepmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 2443, 6, 4911},
|
|
{"cvmx_usbc#_doeptsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 2445, 4, 4917},
|
|
{"cvmx_usbc#_dptxfsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 2455, 2, 4921},
|
|
{"cvmx_usbc#_dsts" , CVMX_CSR_DB_TYPE_NCB, 32, 2463, 6, 4923},
|
|
{"cvmx_usbc#_dtknqr1" , CVMX_CSR_DB_TYPE_NCB, 32, 2465, 4, 4929},
|
|
{"cvmx_usbc#_dtknqr2" , CVMX_CSR_DB_TYPE_NCB, 32, 2467, 1, 4933},
|
|
{"cvmx_usbc#_dtknqr3" , CVMX_CSR_DB_TYPE_NCB, 32, 2469, 1, 4934},
|
|
{"cvmx_usbc#_dtknqr4" , CVMX_CSR_DB_TYPE_NCB, 32, 2471, 1, 4935},
|
|
{"cvmx_usbc#_gahbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 2473, 7, 4936},
|
|
{"cvmx_usbc#_ghwcfg1" , CVMX_CSR_DB_TYPE_NCB, 32, 2475, 1, 4943},
|
|
{"cvmx_usbc#_ghwcfg2" , CVMX_CSR_DB_TYPE_NCB, 32, 2477, 14, 4944},
|
|
{"cvmx_usbc#_ghwcfg3" , CVMX_CSR_DB_TYPE_NCB, 32, 2479, 10, 4958},
|
|
{"cvmx_usbc#_ghwcfg4" , CVMX_CSR_DB_TYPE_NCB, 32, 2481, 14, 4968},
|
|
{"cvmx_usbc#_gintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 2483, 32, 4982},
|
|
{"cvmx_usbc#_gintsts" , CVMX_CSR_DB_TYPE_NCB, 32, 2485, 32, 5014},
|
|
{"cvmx_usbc#_gnptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 2487, 2, 5046},
|
|
{"cvmx_usbc#_gnptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 2489, 4, 5048},
|
|
{"cvmx_usbc#_gotgctl" , CVMX_CSR_DB_TYPE_NCB, 32, 2491, 13, 5052},
|
|
{"cvmx_usbc#_gotgint" , CVMX_CSR_DB_TYPE_NCB, 32, 2493, 10, 5065},
|
|
{"cvmx_usbc#_grstctl" , CVMX_CSR_DB_TYPE_NCB, 32, 2495, 10, 5075},
|
|
{"cvmx_usbc#_grxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 2497, 2, 5085},
|
|
{"cvmx_usbc#_grxstspd" , CVMX_CSR_DB_TYPE_NCB, 32, 2499, 6, 5087},
|
|
{"cvmx_usbc#_grxstsph" , CVMX_CSR_DB_TYPE_NCB, 32, 2501, 5, 5093},
|
|
{"cvmx_usbc#_grxstsrd" , CVMX_CSR_DB_TYPE_NCB, 32, 2503, 6, 5098},
|
|
{"cvmx_usbc#_grxstsrh" , CVMX_CSR_DB_TYPE_NCB, 32, 2505, 5, 5104},
|
|
{"cvmx_usbc#_gsnpsid" , CVMX_CSR_DB_TYPE_NCB, 32, 2507, 1, 5109},
|
|
{"cvmx_usbc#_gusbcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 2509, 13, 5110},
|
|
{"cvmx_usbc#_haint" , CVMX_CSR_DB_TYPE_NCB, 32, 2511, 2, 5123},
|
|
{"cvmx_usbc#_haintmsk" , CVMX_CSR_DB_TYPE_NCB, 32, 2513, 2, 5125},
|
|
{"cvmx_usbc#_hcchar#" , CVMX_CSR_DB_TYPE_NCB, 32, 2515, 11, 5127},
|
|
{"cvmx_usbc#_hcfg" , CVMX_CSR_DB_TYPE_NCB, 32, 2531, 3, 5138},
|
|
{"cvmx_usbc#_hcint#" , CVMX_CSR_DB_TYPE_NCB, 32, 2533, 12, 5141},
|
|
{"cvmx_usbc#_hcintmsk#" , CVMX_CSR_DB_TYPE_NCB, 32, 2549, 12, 5153},
|
|
{"cvmx_usbc#_hcsplt#" , CVMX_CSR_DB_TYPE_NCB, 32, 2565, 6, 5165},
|
|
{"cvmx_usbc#_hctsiz#" , CVMX_CSR_DB_TYPE_NCB, 32, 2581, 4, 5171},
|
|
{"cvmx_usbc#_hfir" , CVMX_CSR_DB_TYPE_NCB, 32, 2597, 2, 5175},
|
|
{"cvmx_usbc#_hfnum" , CVMX_CSR_DB_TYPE_NCB, 32, 2599, 2, 5177},
|
|
{"cvmx_usbc#_hprt" , CVMX_CSR_DB_TYPE_NCB, 32, 2601, 15, 5179},
|
|
{"cvmx_usbc#_hptxfsiz" , CVMX_CSR_DB_TYPE_NCB, 32, 2603, 2, 5194},
|
|
{"cvmx_usbc#_hptxsts" , CVMX_CSR_DB_TYPE_NCB, 32, 2605, 3, 5196},
|
|
{"cvmx_usbc#_nptxdfifo#" , CVMX_CSR_DB_TYPE_NCB, 32, 2607, 1, 5199},
|
|
{"cvmx_usbc#_pcgcctl" , CVMX_CSR_DB_TYPE_NCB, 32, 2623, 6, 5200},
|
|
{"cvmx_usbn#_bist_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2625, 8, 5206},
|
|
{"cvmx_usbn#_clk_ctl" , CVMX_CSR_DB_TYPE_RSL, 64, 2627, 15, 5214},
|
|
{"cvmx_usbn#_ctl_status" , CVMX_CSR_DB_TYPE_NCB, 64, 2629, 6, 5229},
|
|
{"cvmx_usbn#_dma0_inb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 2631, 2, 5235},
|
|
{"cvmx_usbn#_dma0_inb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 2633, 2, 5237},
|
|
{"cvmx_usbn#_dma0_inb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 2635, 2, 5239},
|
|
{"cvmx_usbn#_dma0_inb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 2637, 2, 5241},
|
|
{"cvmx_usbn#_dma0_inb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 2639, 2, 5243},
|
|
{"cvmx_usbn#_dma0_inb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 2641, 2, 5245},
|
|
{"cvmx_usbn#_dma0_inb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 2643, 2, 5247},
|
|
{"cvmx_usbn#_dma0_inb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 2645, 2, 5249},
|
|
{"cvmx_usbn#_dma0_outb_chn0" , CVMX_CSR_DB_TYPE_NCB, 64, 2647, 2, 5251},
|
|
{"cvmx_usbn#_dma0_outb_chn1" , CVMX_CSR_DB_TYPE_NCB, 64, 2649, 2, 5253},
|
|
{"cvmx_usbn#_dma0_outb_chn2" , CVMX_CSR_DB_TYPE_NCB, 64, 2651, 2, 5255},
|
|
{"cvmx_usbn#_dma0_outb_chn3" , CVMX_CSR_DB_TYPE_NCB, 64, 2653, 2, 5257},
|
|
{"cvmx_usbn#_dma0_outb_chn4" , CVMX_CSR_DB_TYPE_NCB, 64, 2655, 2, 5259},
|
|
{"cvmx_usbn#_dma0_outb_chn5" , CVMX_CSR_DB_TYPE_NCB, 64, 2657, 2, 5261},
|
|
{"cvmx_usbn#_dma0_outb_chn6" , CVMX_CSR_DB_TYPE_NCB, 64, 2659, 2, 5263},
|
|
{"cvmx_usbn#_dma0_outb_chn7" , CVMX_CSR_DB_TYPE_NCB, 64, 2661, 2, 5265},
|
|
{"cvmx_usbn#_dma_test" , CVMX_CSR_DB_TYPE_NCB, 64, 2663, 7, 5267},
|
|
{"cvmx_usbn#_int_enb" , CVMX_CSR_DB_TYPE_RSL, 64, 2665, 34, 5274},
|
|
{"cvmx_usbn#_int_sum" , CVMX_CSR_DB_TYPE_RSL, 64, 2667, 34, 5308},
|
|
{"cvmx_usbn#_usbp_ctl_status" , CVMX_CSR_DB_TYPE_RSL, 64, 2669, 35, 5342},
|
|
{NULL,0,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
|
|
/* name , --------------address, ---------------type, bits, csr offset */
|
|
{"AGL_GMX_BAD_REG" , 0x11800E0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 0},
|
|
{"AGL_GMX_BIST" , 0x11800E0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 1},
|
|
{"AGL_GMX_DRV_CTL" , 0x11800E00007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 2},
|
|
{"AGL_GMX_INF_MODE" , 0x11800E00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 3},
|
|
{"AGL_GMX_PRT0_CFG" , 0x11800E0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
|
|
{"AGL_GMX_PRT1_CFG" , 0x11800E0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 4},
|
|
{"AGL_GMX_RX0_ADR_CAM0" , 0x11800E0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
|
|
{"AGL_GMX_RX1_ADR_CAM0" , 0x11800E0000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 5},
|
|
{"AGL_GMX_RX0_ADR_CAM1" , 0x11800E0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
|
|
{"AGL_GMX_RX1_ADR_CAM1" , 0x11800E0000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 6},
|
|
{"AGL_GMX_RX0_ADR_CAM2" , 0x11800E0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
|
|
{"AGL_GMX_RX1_ADR_CAM2" , 0x11800E0000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 7},
|
|
{"AGL_GMX_RX0_ADR_CAM3" , 0x11800E0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
|
|
{"AGL_GMX_RX1_ADR_CAM3" , 0x11800E0000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 8},
|
|
{"AGL_GMX_RX0_ADR_CAM4" , 0x11800E00001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
|
|
{"AGL_GMX_RX1_ADR_CAM4" , 0x11800E00009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 9},
|
|
{"AGL_GMX_RX0_ADR_CAM5" , 0x11800E00001A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
|
|
{"AGL_GMX_RX1_ADR_CAM5" , 0x11800E00009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 10},
|
|
{"AGL_GMX_RX0_ADR_CAM_EN" , 0x11800E0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
|
|
{"AGL_GMX_RX1_ADR_CAM_EN" , 0x11800E0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 11},
|
|
{"AGL_GMX_RX0_ADR_CTL" , 0x11800E0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"AGL_GMX_RX1_ADR_CTL" , 0x11800E0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 12},
|
|
{"AGL_GMX_RX0_DECISION" , 0x11800E0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"AGL_GMX_RX1_DECISION" , 0x11800E0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 13},
|
|
{"AGL_GMX_RX0_FRM_CHK" , 0x11800E0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"AGL_GMX_RX1_FRM_CHK" , 0x11800E0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 14},
|
|
{"AGL_GMX_RX0_FRM_CTL" , 0x11800E0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
|
|
{"AGL_GMX_RX1_FRM_CTL" , 0x11800E0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 15},
|
|
{"AGL_GMX_RX0_FRM_MAX" , 0x11800E0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"AGL_GMX_RX1_FRM_MAX" , 0x11800E0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 16},
|
|
{"AGL_GMX_RX0_FRM_MIN" , 0x11800E0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
|
|
{"AGL_GMX_RX1_FRM_MIN" , 0x11800E0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 17},
|
|
{"AGL_GMX_RX0_IFG" , 0x11800E0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
|
|
{"AGL_GMX_RX1_IFG" , 0x11800E0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 18},
|
|
{"AGL_GMX_RX0_INT_EN" , 0x11800E0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
|
|
{"AGL_GMX_RX1_INT_EN" , 0x11800E0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 19},
|
|
{"AGL_GMX_RX0_INT_REG" , 0x11800E0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
|
|
{"AGL_GMX_RX1_INT_REG" , 0x11800E0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 20},
|
|
{"AGL_GMX_RX0_JABBER" , 0x11800E0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
|
|
{"AGL_GMX_RX1_JABBER" , 0x11800E0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 21},
|
|
{"AGL_GMX_RX0_PAUSE_DROP_TIME" , 0x11800E0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
|
|
{"AGL_GMX_RX1_PAUSE_DROP_TIME" , 0x11800E0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 22},
|
|
{"AGL_GMX_RX0_STATS_CTL" , 0x11800E0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
|
|
{"AGL_GMX_RX1_STATS_CTL" , 0x11800E0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 23},
|
|
{"AGL_GMX_RX0_STATS_OCTS" , 0x11800E0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
|
|
{"AGL_GMX_RX1_STATS_OCTS" , 0x11800E0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 24},
|
|
{"AGL_GMX_RX0_STATS_OCTS_CTL" , 0x11800E0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 25},
|
|
{"AGL_GMX_RX1_STATS_OCTS_CTL" , 0x11800E0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 25},
|
|
{"AGL_GMX_RX0_STATS_OCTS_DMAC" , 0x11800E00000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 26},
|
|
{"AGL_GMX_RX1_STATS_OCTS_DMAC" , 0x11800E00008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 26},
|
|
{"AGL_GMX_RX0_STATS_OCTS_DRP" , 0x11800E00000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 27},
|
|
{"AGL_GMX_RX1_STATS_OCTS_DRP" , 0x11800E00008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 27},
|
|
{"AGL_GMX_RX0_STATS_PKTS" , 0x11800E0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 28},
|
|
{"AGL_GMX_RX1_STATS_PKTS" , 0x11800E0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 28},
|
|
{"AGL_GMX_RX0_STATS_PKTS_BAD" , 0x11800E00000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 29},
|
|
{"AGL_GMX_RX1_STATS_PKTS_BAD" , 0x11800E00008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 29},
|
|
{"AGL_GMX_RX0_STATS_PKTS_CTL" , 0x11800E0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 30},
|
|
{"AGL_GMX_RX1_STATS_PKTS_CTL" , 0x11800E0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 30},
|
|
{"AGL_GMX_RX0_STATS_PKTS_DMAC" , 0x11800E00000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 31},
|
|
{"AGL_GMX_RX1_STATS_PKTS_DMAC" , 0x11800E00008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 31},
|
|
{"AGL_GMX_RX0_STATS_PKTS_DRP" , 0x11800E00000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
|
|
{"AGL_GMX_RX1_STATS_PKTS_DRP" , 0x11800E00008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 32},
|
|
{"AGL_GMX_RX0_UDD_SKP" , 0x11800E0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
|
|
{"AGL_GMX_RX1_UDD_SKP" , 0x11800E0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 33},
|
|
{"AGL_GMX_RX_BP_DROP0" , 0x11800E0000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 34},
|
|
{"AGL_GMX_RX_BP_DROP1" , 0x11800E0000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 34},
|
|
{"AGL_GMX_RX_BP_OFF0" , 0x11800E0000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
|
|
{"AGL_GMX_RX_BP_OFF1" , 0x11800E0000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 35},
|
|
{"AGL_GMX_RX_BP_ON0" , 0x11800E0000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
|
|
{"AGL_GMX_RX_BP_ON1" , 0x11800E0000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 36},
|
|
{"AGL_GMX_RX_PRT_INFO" , 0x11800E00004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 37},
|
|
{"AGL_GMX_RX_TX_STATUS" , 0x11800E00007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 38},
|
|
{"AGL_GMX_SMAC0" , 0x11800E0000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
|
|
{"AGL_GMX_SMAC1" , 0x11800E0000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 39},
|
|
{"AGL_GMX_STAT_BP" , 0x11800E0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 40},
|
|
{"AGL_GMX_TX0_APPEND" , 0x11800E0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
|
|
{"AGL_GMX_TX1_APPEND" , 0x11800E0000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 41},
|
|
{"AGL_GMX_TX0_CTL" , 0x11800E0000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
|
|
{"AGL_GMX_TX1_CTL" , 0x11800E0000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 42},
|
|
{"AGL_GMX_TX0_MIN_PKT" , 0x11800E0000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
|
|
{"AGL_GMX_TX1_MIN_PKT" , 0x11800E0000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 43},
|
|
{"AGL_GMX_TX0_PAUSE_PKT_INTERVAL", 0x11800E0000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
|
|
{"AGL_GMX_TX1_PAUSE_PKT_INTERVAL", 0x11800E0000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 44},
|
|
{"AGL_GMX_TX0_PAUSE_PKT_TIME" , 0x11800E0000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
|
|
{"AGL_GMX_TX1_PAUSE_PKT_TIME" , 0x11800E0000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 45},
|
|
{"AGL_GMX_TX0_PAUSE_TOGO" , 0x11800E0000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
|
|
{"AGL_GMX_TX1_PAUSE_TOGO" , 0x11800E0000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 46},
|
|
{"AGL_GMX_TX0_PAUSE_ZERO" , 0x11800E0000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
|
|
{"AGL_GMX_TX1_PAUSE_ZERO" , 0x11800E0000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 47},
|
|
{"AGL_GMX_TX0_SOFT_PAUSE" , 0x11800E0000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
|
|
{"AGL_GMX_TX1_SOFT_PAUSE" , 0x11800E0000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 48},
|
|
{"AGL_GMX_TX0_STAT0" , 0x11800E0000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
|
|
{"AGL_GMX_TX1_STAT0" , 0x11800E0000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 49},
|
|
{"AGL_GMX_TX0_STAT1" , 0x11800E0000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
|
|
{"AGL_GMX_TX1_STAT1" , 0x11800E0000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 50},
|
|
{"AGL_GMX_TX0_STAT2" , 0x11800E0000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
|
|
{"AGL_GMX_TX1_STAT2" , 0x11800E0000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 51},
|
|
{"AGL_GMX_TX0_STAT3" , 0x11800E0000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
|
|
{"AGL_GMX_TX1_STAT3" , 0x11800E0000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 52},
|
|
{"AGL_GMX_TX0_STAT4" , 0x11800E00002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
|
|
{"AGL_GMX_TX1_STAT4" , 0x11800E0000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 53},
|
|
{"AGL_GMX_TX0_STAT5" , 0x11800E00002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
|
|
{"AGL_GMX_TX1_STAT5" , 0x11800E0000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 54},
|
|
{"AGL_GMX_TX0_STAT6" , 0x11800E00002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
|
|
{"AGL_GMX_TX1_STAT6" , 0x11800E0000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 55},
|
|
{"AGL_GMX_TX0_STAT7" , 0x11800E00002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
|
|
{"AGL_GMX_TX1_STAT7" , 0x11800E0000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 56},
|
|
{"AGL_GMX_TX0_STAT8" , 0x11800E00002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
|
|
{"AGL_GMX_TX1_STAT8" , 0x11800E0000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 57},
|
|
{"AGL_GMX_TX0_STAT9" , 0x11800E00002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
|
|
{"AGL_GMX_TX1_STAT9" , 0x11800E0000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 58},
|
|
{"AGL_GMX_TX0_STATS_CTL" , 0x11800E0000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
|
|
{"AGL_GMX_TX1_STATS_CTL" , 0x11800E0000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 59},
|
|
{"AGL_GMX_TX0_THRESH" , 0x11800E0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
|
|
{"AGL_GMX_TX1_THRESH" , 0x11800E0000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 60},
|
|
{"AGL_GMX_TX_BP" , 0x11800E00004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 61},
|
|
{"AGL_GMX_TX_COL_ATTEMPT" , 0x11800E0000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 62},
|
|
{"AGL_GMX_TX_IFG" , 0x11800E0000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 63},
|
|
{"AGL_GMX_TX_INT_EN" , 0x11800E0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 64},
|
|
{"AGL_GMX_TX_INT_REG" , 0x11800E0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 65},
|
|
{"AGL_GMX_TX_JAM" , 0x11800E0000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 66},
|
|
{"AGL_GMX_TX_LFSR" , 0x11800E00004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 67},
|
|
{"AGL_GMX_TX_OVR_BP" , 0x11800E00004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 68},
|
|
{"AGL_GMX_TX_PAUSE_PKT_DMAC" , 0x11800E00004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 69},
|
|
{"AGL_GMX_TX_PAUSE_PKT_TYPE" , 0x11800E00004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 70},
|
|
{"CIU_BIST" , 0x1070000000730ull, CVMX_CSR_DB_TYPE_NCB, 64, 71},
|
|
{"CIU_DINT" , 0x1070000000720ull, CVMX_CSR_DB_TYPE_NCB, 64, 72},
|
|
{"CIU_FUSE" , 0x1070000000728ull, CVMX_CSR_DB_TYPE_NCB, 64, 73},
|
|
{"CIU_GSTOP" , 0x1070000000710ull, CVMX_CSR_DB_TYPE_NCB, 64, 74},
|
|
{"CIU_INT0_EN0" , 0x1070000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT1_EN0" , 0x1070000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT2_EN0" , 0x1070000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT3_EN0" , 0x1070000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT4_EN0" , 0x1070000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT5_EN0" , 0x1070000000250ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT6_EN0" , 0x1070000000260ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT7_EN0" , 0x1070000000270ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT32_EN0" , 0x1070000000400ull, CVMX_CSR_DB_TYPE_NCB, 64, 75},
|
|
{"CIU_INT0_EN0_W1C" , 0x1070000002200ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT1_EN0_W1C" , 0x1070000002210ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT2_EN0_W1C" , 0x1070000002220ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT3_EN0_W1C" , 0x1070000002230ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT4_EN0_W1C" , 0x1070000002240ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT5_EN0_W1C" , 0x1070000002250ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT6_EN0_W1C" , 0x1070000002260ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT7_EN0_W1C" , 0x1070000002270ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT32_EN0_W1C" , 0x1070000002400ull, CVMX_CSR_DB_TYPE_NCB, 64, 76},
|
|
{"CIU_INT0_EN0_W1S" , 0x1070000006200ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT1_EN0_W1S" , 0x1070000006210ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT2_EN0_W1S" , 0x1070000006220ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT3_EN0_W1S" , 0x1070000006230ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT4_EN0_W1S" , 0x1070000006240ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT5_EN0_W1S" , 0x1070000006250ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT6_EN0_W1S" , 0x1070000006260ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT7_EN0_W1S" , 0x1070000006270ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT32_EN0_W1S" , 0x1070000006400ull, CVMX_CSR_DB_TYPE_NCB, 64, 77},
|
|
{"CIU_INT0_EN1" , 0x1070000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT1_EN1" , 0x1070000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT2_EN1" , 0x1070000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT3_EN1" , 0x1070000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT4_EN1" , 0x1070000000248ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT5_EN1" , 0x1070000000258ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT6_EN1" , 0x1070000000268ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT7_EN1" , 0x1070000000278ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT32_EN1" , 0x1070000000408ull, CVMX_CSR_DB_TYPE_NCB, 64, 78},
|
|
{"CIU_INT0_EN1_W1C" , 0x1070000002208ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT1_EN1_W1C" , 0x1070000002218ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT2_EN1_W1C" , 0x1070000002228ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT3_EN1_W1C" , 0x1070000002238ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT4_EN1_W1C" , 0x1070000002248ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT5_EN1_W1C" , 0x1070000002258ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT6_EN1_W1C" , 0x1070000002268ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT7_EN1_W1C" , 0x1070000002278ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT32_EN1_W1C" , 0x1070000002408ull, CVMX_CSR_DB_TYPE_NCB, 64, 79},
|
|
{"CIU_INT0_EN1_W1S" , 0x1070000006208ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT1_EN1_W1S" , 0x1070000006218ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT2_EN1_W1S" , 0x1070000006228ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT3_EN1_W1S" , 0x1070000006238ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT4_EN1_W1S" , 0x1070000006248ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT5_EN1_W1S" , 0x1070000006258ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT6_EN1_W1S" , 0x1070000006268ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT7_EN1_W1S" , 0x1070000006278ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT32_EN1_W1S" , 0x1070000006408ull, CVMX_CSR_DB_TYPE_NCB, 64, 80},
|
|
{"CIU_INT0_EN4_0" , 0x1070000000C80ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
|
|
{"CIU_INT1_EN4_0" , 0x1070000000C90ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
|
|
{"CIU_INT2_EN4_0" , 0x1070000000CA0ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
|
|
{"CIU_INT3_EN4_0" , 0x1070000000CB0ull, CVMX_CSR_DB_TYPE_NCB, 64, 81},
|
|
{"CIU_INT0_EN4_0_W1C" , 0x1070000002C80ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_INT1_EN4_0_W1C" , 0x1070000002C90ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_INT2_EN4_0_W1C" , 0x1070000002CA0ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_INT3_EN4_0_W1C" , 0x1070000002CB0ull, CVMX_CSR_DB_TYPE_NCB, 64, 82},
|
|
{"CIU_INT0_EN4_0_W1S" , 0x1070000006C80ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_INT1_EN4_0_W1S" , 0x1070000006C90ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_INT2_EN4_0_W1S" , 0x1070000006CA0ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_INT3_EN4_0_W1S" , 0x1070000006CB0ull, CVMX_CSR_DB_TYPE_NCB, 64, 83},
|
|
{"CIU_INT0_EN4_1" , 0x1070000000C88ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
|
|
{"CIU_INT1_EN4_1" , 0x1070000000C98ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
|
|
{"CIU_INT2_EN4_1" , 0x1070000000CA8ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
|
|
{"CIU_INT3_EN4_1" , 0x1070000000CB8ull, CVMX_CSR_DB_TYPE_NCB, 64, 84},
|
|
{"CIU_INT0_EN4_1_W1C" , 0x1070000002C88ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
|
|
{"CIU_INT1_EN4_1_W1C" , 0x1070000002C98ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
|
|
{"CIU_INT2_EN4_1_W1C" , 0x1070000002CA8ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
|
|
{"CIU_INT3_EN4_1_W1C" , 0x1070000002CB8ull, CVMX_CSR_DB_TYPE_NCB, 64, 85},
|
|
{"CIU_INT0_EN4_1_W1S" , 0x1070000006C88ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
|
|
{"CIU_INT1_EN4_1_W1S" , 0x1070000006C98ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
|
|
{"CIU_INT2_EN4_1_W1S" , 0x1070000006CA8ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
|
|
{"CIU_INT3_EN4_1_W1S" , 0x1070000006CB8ull, CVMX_CSR_DB_TYPE_NCB, 64, 86},
|
|
{"CIU_INT0_SUM0" , 0x1070000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT1_SUM0" , 0x1070000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT2_SUM0" , 0x1070000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT3_SUM0" , 0x1070000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT4_SUM0" , 0x1070000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT5_SUM0" , 0x1070000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT6_SUM0" , 0x1070000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT7_SUM0" , 0x1070000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT32_SUM0" , 0x1070000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 87},
|
|
{"CIU_INT0_SUM4" , 0x1070000000C00ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
|
|
{"CIU_INT1_SUM4" , 0x1070000000C08ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
|
|
{"CIU_INT2_SUM4" , 0x1070000000C10ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
|
|
{"CIU_INT3_SUM4" , 0x1070000000C18ull, CVMX_CSR_DB_TYPE_NCB, 64, 88},
|
|
{"CIU_INT_SUM1" , 0x1070000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 89},
|
|
{"CIU_MBOX_CLR0" , 0x1070000000680ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
|
|
{"CIU_MBOX_CLR1" , 0x1070000000688ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
|
|
{"CIU_MBOX_CLR2" , 0x1070000000690ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
|
|
{"CIU_MBOX_CLR3" , 0x1070000000698ull, CVMX_CSR_DB_TYPE_NCB, 64, 90},
|
|
{"CIU_MBOX_SET0" , 0x1070000000600ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
|
|
{"CIU_MBOX_SET1" , 0x1070000000608ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
|
|
{"CIU_MBOX_SET2" , 0x1070000000610ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
|
|
{"CIU_MBOX_SET3" , 0x1070000000618ull, CVMX_CSR_DB_TYPE_NCB, 64, 91},
|
|
{"CIU_NMI" , 0x1070000000718ull, CVMX_CSR_DB_TYPE_NCB, 64, 92},
|
|
{"CIU_PCI_INTA" , 0x1070000000750ull, CVMX_CSR_DB_TYPE_NCB, 64, 93},
|
|
{"CIU_PP_DBG" , 0x1070000000708ull, CVMX_CSR_DB_TYPE_NCB, 64, 94},
|
|
{"CIU_PP_POKE0" , 0x1070000000580ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
|
|
{"CIU_PP_POKE1" , 0x1070000000588ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
|
|
{"CIU_PP_POKE2" , 0x1070000000590ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
|
|
{"CIU_PP_POKE3" , 0x1070000000598ull, CVMX_CSR_DB_TYPE_NCB, 64, 95},
|
|
{"CIU_PP_RST" , 0x1070000000700ull, CVMX_CSR_DB_TYPE_NCB, 64, 96},
|
|
{"CIU_QLM_DCOK" , 0x1070000000760ull, CVMX_CSR_DB_TYPE_NCB, 64, 97},
|
|
{"CIU_QLM_JTGC" , 0x1070000000768ull, CVMX_CSR_DB_TYPE_NCB, 64, 98},
|
|
{"CIU_QLM_JTGD" , 0x1070000000770ull, CVMX_CSR_DB_TYPE_NCB, 64, 99},
|
|
{"CIU_SOFT_BIST" , 0x1070000000738ull, CVMX_CSR_DB_TYPE_NCB, 64, 100},
|
|
{"CIU_SOFT_PRST" , 0x1070000000748ull, CVMX_CSR_DB_TYPE_NCB, 64, 101},
|
|
{"CIU_SOFT_PRST1" , 0x1070000000758ull, CVMX_CSR_DB_TYPE_NCB, 64, 102},
|
|
{"CIU_SOFT_RST" , 0x1070000000740ull, CVMX_CSR_DB_TYPE_NCB, 64, 103},
|
|
{"CIU_TIM0" , 0x1070000000480ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
|
|
{"CIU_TIM1" , 0x1070000000488ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
|
|
{"CIU_TIM2" , 0x1070000000490ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
|
|
{"CIU_TIM3" , 0x1070000000498ull, CVMX_CSR_DB_TYPE_NCB, 64, 104},
|
|
{"CIU_WDOG0" , 0x1070000000500ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
|
|
{"CIU_WDOG1" , 0x1070000000508ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
|
|
{"CIU_WDOG2" , 0x1070000000510ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
|
|
{"CIU_WDOG3" , 0x1070000000518ull, CVMX_CSR_DB_TYPE_NCB, 64, 105},
|
|
{"FPA_BIST_STATUS" , 0x11800280000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 106},
|
|
{"FPA_CTL_STATUS" , 0x1180028000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 107},
|
|
{"FPA_INT_ENB" , 0x1180028000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 108},
|
|
{"FPA_INT_SUM" , 0x1180028000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 109},
|
|
{"FPA_QUE0_AVAILABLE" , 0x1180028000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"FPA_QUE1_AVAILABLE" , 0x11800280000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"FPA_QUE2_AVAILABLE" , 0x11800280000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"FPA_QUE3_AVAILABLE" , 0x11800280000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"FPA_QUE4_AVAILABLE" , 0x11800280000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"FPA_QUE5_AVAILABLE" , 0x11800280000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"FPA_QUE6_AVAILABLE" , 0x11800280000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"FPA_QUE7_AVAILABLE" , 0x11800280000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 110},
|
|
{"FPA_QUE0_PAGE_INDEX" , 0x11800280000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"FPA_QUE1_PAGE_INDEX" , 0x11800280000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"FPA_QUE2_PAGE_INDEX" , 0x1180028000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"FPA_QUE3_PAGE_INDEX" , 0x1180028000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"FPA_QUE4_PAGE_INDEX" , 0x1180028000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"FPA_QUE5_PAGE_INDEX" , 0x1180028000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"FPA_QUE6_PAGE_INDEX" , 0x1180028000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"FPA_QUE7_PAGE_INDEX" , 0x1180028000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 111},
|
|
{"FPA_QUE_ACT" , 0x1180028000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 112},
|
|
{"FPA_QUE_EXP" , 0x1180028000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 113},
|
|
{"FPA_WART_CTL" , 0x11800280000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 114},
|
|
{"FPA_WART_STATUS" , 0x11800280000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 115},
|
|
{"GMX0_BAD_REG" , 0x1180008000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 116},
|
|
{"GMX0_BIST" , 0x1180008000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 117},
|
|
{"GMX0_CLK_EN" , 0x11800080007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 118},
|
|
{"GMX0_HG2_CONTROL" , 0x1180008000550ull, CVMX_CSR_DB_TYPE_RSL, 64, 119},
|
|
{"GMX0_INF_MODE" , 0x11800080007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 120},
|
|
{"GMX0_NXA_ADR" , 0x1180008000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 121},
|
|
{"GMX0_PRT000_CBFC_CTL" , 0x1180008000580ull, CVMX_CSR_DB_TYPE_RSL, 64, 122},
|
|
{"GMX0_PRT000_CFG" , 0x1180008000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_PRT001_CFG" , 0x1180008000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_PRT002_CFG" , 0x1180008001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_PRT003_CFG" , 0x1180008001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 123},
|
|
{"GMX0_RX000_ADR_CAM0" , 0x1180008000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX001_ADR_CAM0" , 0x1180008000980ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX002_ADR_CAM0" , 0x1180008001180ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX003_ADR_CAM0" , 0x1180008001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 124},
|
|
{"GMX0_RX000_ADR_CAM1" , 0x1180008000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_RX001_ADR_CAM1" , 0x1180008000988ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_RX002_ADR_CAM1" , 0x1180008001188ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_RX003_ADR_CAM1" , 0x1180008001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 125},
|
|
{"GMX0_RX000_ADR_CAM2" , 0x1180008000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_RX001_ADR_CAM2" , 0x1180008000990ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_RX002_ADR_CAM2" , 0x1180008001190ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_RX003_ADR_CAM2" , 0x1180008001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 126},
|
|
{"GMX0_RX000_ADR_CAM3" , 0x1180008000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_RX001_ADR_CAM3" , 0x1180008000998ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_RX002_ADR_CAM3" , 0x1180008001198ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_RX003_ADR_CAM3" , 0x1180008001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 127},
|
|
{"GMX0_RX000_ADR_CAM4" , 0x11800080001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_RX001_ADR_CAM4" , 0x11800080009A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_RX002_ADR_CAM4" , 0x11800080011A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_RX003_ADR_CAM4" , 0x11800080019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 128},
|
|
{"GMX0_RX000_ADR_CAM5" , 0x11800080001A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_RX001_ADR_CAM5" , 0x11800080009A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_RX002_ADR_CAM5" , 0x11800080011A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_RX003_ADR_CAM5" , 0x11800080019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 129},
|
|
{"GMX0_RX000_ADR_CAM_EN" , 0x1180008000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_RX001_ADR_CAM_EN" , 0x1180008000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_RX002_ADR_CAM_EN" , 0x1180008001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_RX003_ADR_CAM_EN" , 0x1180008001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 130},
|
|
{"GMX0_RX000_ADR_CTL" , 0x1180008000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_RX001_ADR_CTL" , 0x1180008000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_RX002_ADR_CTL" , 0x1180008001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_RX003_ADR_CTL" , 0x1180008001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 131},
|
|
{"GMX0_RX000_DECISION" , 0x1180008000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_RX001_DECISION" , 0x1180008000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_RX002_DECISION" , 0x1180008001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_RX003_DECISION" , 0x1180008001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 132},
|
|
{"GMX0_RX000_FRM_CHK" , 0x1180008000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_RX001_FRM_CHK" , 0x1180008000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_RX002_FRM_CHK" , 0x1180008001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_RX003_FRM_CHK" , 0x1180008001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 133},
|
|
{"GMX0_RX000_FRM_CTL" , 0x1180008000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_RX001_FRM_CTL" , 0x1180008000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_RX002_FRM_CTL" , 0x1180008001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_RX003_FRM_CTL" , 0x1180008001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 134},
|
|
{"GMX0_RX000_IFG" , 0x1180008000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_RX001_IFG" , 0x1180008000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_RX002_IFG" , 0x1180008001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_RX003_IFG" , 0x1180008001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 135},
|
|
{"GMX0_RX000_INT_EN" , 0x1180008000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_RX001_INT_EN" , 0x1180008000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_RX002_INT_EN" , 0x1180008001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_RX003_INT_EN" , 0x1180008001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 136},
|
|
{"GMX0_RX000_INT_REG" , 0x1180008000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_RX001_INT_REG" , 0x1180008000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_RX002_INT_REG" , 0x1180008001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_RX003_INT_REG" , 0x1180008001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 137},
|
|
{"GMX0_RX000_JABBER" , 0x1180008000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_RX001_JABBER" , 0x1180008000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_RX002_JABBER" , 0x1180008001038ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_RX003_JABBER" , 0x1180008001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 138},
|
|
{"GMX0_RX000_PAUSE_DROP_TIME" , 0x1180008000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_RX001_PAUSE_DROP_TIME" , 0x1180008000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_RX002_PAUSE_DROP_TIME" , 0x1180008001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_RX003_PAUSE_DROP_TIME" , 0x1180008001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 139},
|
|
{"GMX0_RX000_STATS_CTL" , 0x1180008000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_RX001_STATS_CTL" , 0x1180008000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_RX002_STATS_CTL" , 0x1180008001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_RX003_STATS_CTL" , 0x1180008001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 140},
|
|
{"GMX0_RX000_STATS_OCTS" , 0x1180008000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_RX001_STATS_OCTS" , 0x1180008000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_RX002_STATS_OCTS" , 0x1180008001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_RX003_STATS_OCTS" , 0x1180008001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 141},
|
|
{"GMX0_RX000_STATS_OCTS_CTL" , 0x1180008000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_RX001_STATS_OCTS_CTL" , 0x1180008000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_RX002_STATS_OCTS_CTL" , 0x1180008001098ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_RX003_STATS_OCTS_CTL" , 0x1180008001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 142},
|
|
{"GMX0_RX000_STATS_OCTS_DMAC" , 0x11800080000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_RX001_STATS_OCTS_DMAC" , 0x11800080008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_RX002_STATS_OCTS_DMAC" , 0x11800080010A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_RX003_STATS_OCTS_DMAC" , 0x11800080018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 143},
|
|
{"GMX0_RX000_STATS_OCTS_DRP" , 0x11800080000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX0_RX001_STATS_OCTS_DRP" , 0x11800080008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX0_RX002_STATS_OCTS_DRP" , 0x11800080010B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX0_RX003_STATS_OCTS_DRP" , 0x11800080018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 144},
|
|
{"GMX0_RX000_STATS_PKTS" , 0x1180008000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX0_RX001_STATS_PKTS" , 0x1180008000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX0_RX002_STATS_PKTS" , 0x1180008001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX0_RX003_STATS_PKTS" , 0x1180008001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 145},
|
|
{"GMX0_RX000_STATS_PKTS_BAD" , 0x11800080000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX0_RX001_STATS_PKTS_BAD" , 0x11800080008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX0_RX002_STATS_PKTS_BAD" , 0x11800080010C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX0_RX003_STATS_PKTS_BAD" , 0x11800080018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 146},
|
|
{"GMX0_RX000_STATS_PKTS_CTL" , 0x1180008000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX0_RX001_STATS_PKTS_CTL" , 0x1180008000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX0_RX002_STATS_PKTS_CTL" , 0x1180008001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX0_RX003_STATS_PKTS_CTL" , 0x1180008001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 147},
|
|
{"GMX0_RX000_STATS_PKTS_DMAC" , 0x11800080000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX0_RX001_STATS_PKTS_DMAC" , 0x11800080008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX0_RX002_STATS_PKTS_DMAC" , 0x11800080010A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX0_RX003_STATS_PKTS_DMAC" , 0x11800080018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 148},
|
|
{"GMX0_RX000_STATS_PKTS_DRP" , 0x11800080000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX0_RX001_STATS_PKTS_DRP" , 0x11800080008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX0_RX002_STATS_PKTS_DRP" , 0x11800080010B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX0_RX003_STATS_PKTS_DRP" , 0x11800080018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 149},
|
|
{"GMX0_RX000_UDD_SKP" , 0x1180008000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX0_RX001_UDD_SKP" , 0x1180008000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX0_RX002_UDD_SKP" , 0x1180008001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX0_RX003_UDD_SKP" , 0x1180008001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 150},
|
|
{"GMX0_RX_BP_DROP000" , 0x1180008000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX0_RX_BP_DROP001" , 0x1180008000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX0_RX_BP_DROP002" , 0x1180008000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX0_RX_BP_DROP003" , 0x1180008000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 151},
|
|
{"GMX0_RX_BP_OFF000" , 0x1180008000460ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX0_RX_BP_OFF001" , 0x1180008000468ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX0_RX_BP_OFF002" , 0x1180008000470ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX0_RX_BP_OFF003" , 0x1180008000478ull, CVMX_CSR_DB_TYPE_RSL, 64, 152},
|
|
{"GMX0_RX_BP_ON000" , 0x1180008000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX0_RX_BP_ON001" , 0x1180008000448ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX0_RX_BP_ON002" , 0x1180008000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX0_RX_BP_ON003" , 0x1180008000458ull, CVMX_CSR_DB_TYPE_RSL, 64, 153},
|
|
{"GMX0_RX_HG2_STATUS" , 0x1180008000548ull, CVMX_CSR_DB_TYPE_RSL, 64, 154},
|
|
{"GMX0_RX_PRT_INFO" , 0x11800080004E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 155},
|
|
{"GMX0_RX_PRTS" , 0x1180008000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 156},
|
|
{"GMX0_RX_XAUI_BAD_COL" , 0x1180008000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 157},
|
|
{"GMX0_RX_XAUI_CTL" , 0x1180008000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 158},
|
|
{"GMX0_SMAC000" , 0x1180008000230ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_SMAC001" , 0x1180008000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_SMAC002" , 0x1180008001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_SMAC003" , 0x1180008001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 159},
|
|
{"GMX0_STAT_BP" , 0x1180008000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 160},
|
|
{"GMX0_TX000_APPEND" , 0x1180008000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
|
|
{"GMX0_TX001_APPEND" , 0x1180008000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
|
|
{"GMX0_TX002_APPEND" , 0x1180008001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
|
|
{"GMX0_TX003_APPEND" , 0x1180008001A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 161},
|
|
{"GMX0_TX000_BURST" , 0x1180008000228ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
|
|
{"GMX0_TX001_BURST" , 0x1180008000A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
|
|
{"GMX0_TX002_BURST" , 0x1180008001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
|
|
{"GMX0_TX003_BURST" , 0x1180008001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 162},
|
|
{"GMX0_TX000_CBFC_XOFF" , 0x11800080005A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 163},
|
|
{"GMX0_TX000_CBFC_XON" , 0x11800080005C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 164},
|
|
{"GMX0_TX000_CTL" , 0x1180008000270ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX0_TX001_CTL" , 0x1180008000A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX0_TX002_CTL" , 0x1180008001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX0_TX003_CTL" , 0x1180008001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 165},
|
|
{"GMX0_TX000_MIN_PKT" , 0x1180008000240ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX0_TX001_MIN_PKT" , 0x1180008000A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX0_TX002_MIN_PKT" , 0x1180008001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX0_TX003_MIN_PKT" , 0x1180008001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 166},
|
|
{"GMX0_TX000_PAUSE_PKT_INTERVAL", 0x1180008000248ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX001_PAUSE_PKT_INTERVAL", 0x1180008000A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX002_PAUSE_PKT_INTERVAL", 0x1180008001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX003_PAUSE_PKT_INTERVAL", 0x1180008001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 167},
|
|
{"GMX0_TX000_PAUSE_PKT_TIME" , 0x1180008000238ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
|
|
{"GMX0_TX001_PAUSE_PKT_TIME" , 0x1180008000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
|
|
{"GMX0_TX002_PAUSE_PKT_TIME" , 0x1180008001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
|
|
{"GMX0_TX003_PAUSE_PKT_TIME" , 0x1180008001A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 168},
|
|
{"GMX0_TX000_PAUSE_TOGO" , 0x1180008000258ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"GMX0_TX001_PAUSE_TOGO" , 0x1180008000A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"GMX0_TX002_PAUSE_TOGO" , 0x1180008001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"GMX0_TX003_PAUSE_TOGO" , 0x1180008001A58ull, CVMX_CSR_DB_TYPE_RSL, 64, 169},
|
|
{"GMX0_TX000_PAUSE_ZERO" , 0x1180008000260ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"GMX0_TX001_PAUSE_ZERO" , 0x1180008000A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"GMX0_TX002_PAUSE_ZERO" , 0x1180008001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"GMX0_TX003_PAUSE_ZERO" , 0x1180008001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 170},
|
|
{"GMX0_TX000_SGMII_CTL" , 0x1180008000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"GMX0_TX001_SGMII_CTL" , 0x1180008000B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"GMX0_TX002_SGMII_CTL" , 0x1180008001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"GMX0_TX003_SGMII_CTL" , 0x1180008001B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 171},
|
|
{"GMX0_TX000_SLOT" , 0x1180008000220ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"GMX0_TX001_SLOT" , 0x1180008000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"GMX0_TX002_SLOT" , 0x1180008001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"GMX0_TX003_SLOT" , 0x1180008001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 172},
|
|
{"GMX0_TX000_SOFT_PAUSE" , 0x1180008000250ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"GMX0_TX001_SOFT_PAUSE" , 0x1180008000A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"GMX0_TX002_SOFT_PAUSE" , 0x1180008001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"GMX0_TX003_SOFT_PAUSE" , 0x1180008001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 173},
|
|
{"GMX0_TX000_STAT0" , 0x1180008000280ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"GMX0_TX001_STAT0" , 0x1180008000A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"GMX0_TX002_STAT0" , 0x1180008001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"GMX0_TX003_STAT0" , 0x1180008001A80ull, CVMX_CSR_DB_TYPE_RSL, 64, 174},
|
|
{"GMX0_TX000_STAT1" , 0x1180008000288ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"GMX0_TX001_STAT1" , 0x1180008000A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"GMX0_TX002_STAT1" , 0x1180008001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"GMX0_TX003_STAT1" , 0x1180008001A88ull, CVMX_CSR_DB_TYPE_RSL, 64, 175},
|
|
{"GMX0_TX000_STAT2" , 0x1180008000290ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"GMX0_TX001_STAT2" , 0x1180008000A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"GMX0_TX002_STAT2" , 0x1180008001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"GMX0_TX003_STAT2" , 0x1180008001A90ull, CVMX_CSR_DB_TYPE_RSL, 64, 176},
|
|
{"GMX0_TX000_STAT3" , 0x1180008000298ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
|
|
{"GMX0_TX001_STAT3" , 0x1180008000A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
|
|
{"GMX0_TX002_STAT3" , 0x1180008001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
|
|
{"GMX0_TX003_STAT3" , 0x1180008001A98ull, CVMX_CSR_DB_TYPE_RSL, 64, 177},
|
|
{"GMX0_TX000_STAT4" , 0x11800080002A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
|
|
{"GMX0_TX001_STAT4" , 0x1180008000AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
|
|
{"GMX0_TX002_STAT4" , 0x11800080012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
|
|
{"GMX0_TX003_STAT4" , 0x1180008001AA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 178},
|
|
{"GMX0_TX000_STAT5" , 0x11800080002A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
|
|
{"GMX0_TX001_STAT5" , 0x1180008000AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
|
|
{"GMX0_TX002_STAT5" , 0x11800080012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
|
|
{"GMX0_TX003_STAT5" , 0x1180008001AA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 179},
|
|
{"GMX0_TX000_STAT6" , 0x11800080002B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
|
|
{"GMX0_TX001_STAT6" , 0x1180008000AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
|
|
{"GMX0_TX002_STAT6" , 0x11800080012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
|
|
{"GMX0_TX003_STAT6" , 0x1180008001AB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 180},
|
|
{"GMX0_TX000_STAT7" , 0x11800080002B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
|
|
{"GMX0_TX001_STAT7" , 0x1180008000AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
|
|
{"GMX0_TX002_STAT7" , 0x11800080012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
|
|
{"GMX0_TX003_STAT7" , 0x1180008001AB8ull, CVMX_CSR_DB_TYPE_RSL, 64, 181},
|
|
{"GMX0_TX000_STAT8" , 0x11800080002C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
|
|
{"GMX0_TX001_STAT8" , 0x1180008000AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
|
|
{"GMX0_TX002_STAT8" , 0x11800080012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
|
|
{"GMX0_TX003_STAT8" , 0x1180008001AC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 182},
|
|
{"GMX0_TX000_STAT9" , 0x11800080002C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
|
|
{"GMX0_TX001_STAT9" , 0x1180008000AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
|
|
{"GMX0_TX002_STAT9" , 0x11800080012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
|
|
{"GMX0_TX003_STAT9" , 0x1180008001AC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 183},
|
|
{"GMX0_TX000_STATS_CTL" , 0x1180008000268ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
|
|
{"GMX0_TX001_STATS_CTL" , 0x1180008000A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
|
|
{"GMX0_TX002_STATS_CTL" , 0x1180008001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
|
|
{"GMX0_TX003_STATS_CTL" , 0x1180008001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 184},
|
|
{"GMX0_TX000_THRESH" , 0x1180008000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
|
|
{"GMX0_TX001_THRESH" , 0x1180008000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
|
|
{"GMX0_TX002_THRESH" , 0x1180008001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
|
|
{"GMX0_TX003_THRESH" , 0x1180008001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 185},
|
|
{"GMX0_TX_BP" , 0x11800080004D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 186},
|
|
{"GMX0_TX_COL_ATTEMPT" , 0x1180008000498ull, CVMX_CSR_DB_TYPE_RSL, 64, 187},
|
|
{"GMX0_TX_CORRUPT" , 0x11800080004D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 188},
|
|
{"GMX0_TX_HG2_REG1" , 0x1180008000558ull, CVMX_CSR_DB_TYPE_RSL, 64, 189},
|
|
{"GMX0_TX_HG2_REG2" , 0x1180008000560ull, CVMX_CSR_DB_TYPE_RSL, 64, 190},
|
|
{"GMX0_TX_IFG" , 0x1180008000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 191},
|
|
{"GMX0_TX_INT_EN" , 0x1180008000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 192},
|
|
{"GMX0_TX_INT_REG" , 0x1180008000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 193},
|
|
{"GMX0_TX_JAM" , 0x1180008000490ull, CVMX_CSR_DB_TYPE_RSL, 64, 194},
|
|
{"GMX0_TX_LFSR" , 0x11800080004F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 195},
|
|
{"GMX0_TX_OVR_BP" , 0x11800080004C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 196},
|
|
{"GMX0_TX_PAUSE_PKT_DMAC" , 0x11800080004A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 197},
|
|
{"GMX0_TX_PAUSE_PKT_TYPE" , 0x11800080004A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 198},
|
|
{"GMX0_TX_PRTS" , 0x1180008000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 199},
|
|
{"GMX0_TX_XAUI_CTL" , 0x1180008000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 200},
|
|
{"GMX0_XAUI_EXT_LOOPBACK" , 0x1180008000540ull, CVMX_CSR_DB_TYPE_RSL, 64, 201},
|
|
{"GPIO_BIT_CFG0" , 0x1070000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"GPIO_BIT_CFG1" , 0x1070000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"GPIO_BIT_CFG2" , 0x1070000000810ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"GPIO_BIT_CFG3" , 0x1070000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"GPIO_BIT_CFG4" , 0x1070000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"GPIO_BIT_CFG5" , 0x1070000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"GPIO_BIT_CFG6" , 0x1070000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"GPIO_BIT_CFG7" , 0x1070000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"GPIO_BIT_CFG8" , 0x1070000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"GPIO_BIT_CFG9" , 0x1070000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"GPIO_BIT_CFG10" , 0x1070000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"GPIO_BIT_CFG11" , 0x1070000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"GPIO_BIT_CFG12" , 0x1070000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"GPIO_BIT_CFG13" , 0x1070000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"GPIO_BIT_CFG14" , 0x1070000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"GPIO_BIT_CFG15" , 0x1070000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 202},
|
|
{"GPIO_CLK_GEN0" , 0x10700000008C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
|
|
{"GPIO_CLK_GEN1" , 0x10700000008C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
|
|
{"GPIO_CLK_GEN2" , 0x10700000008D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
|
|
{"GPIO_CLK_GEN3" , 0x10700000008D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 203},
|
|
{"GPIO_INT_CLR" , 0x1070000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 204},
|
|
{"GPIO_RX_DAT" , 0x1070000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 205},
|
|
{"GPIO_TX_CLR" , 0x1070000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 206},
|
|
{"GPIO_TX_SET" , 0x1070000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 207},
|
|
{"IOB_BIST_STATUS" , 0x11800F00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 208},
|
|
{"IOB_CTL_STATUS" , 0x11800F0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 209},
|
|
{"IOB_DWB_PRI_CNT" , 0x11800F0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 210},
|
|
{"IOB_FAU_TIMEOUT" , 0x11800F0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 211},
|
|
{"IOB_I2C_PRI_CNT" , 0x11800F0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 212},
|
|
{"IOB_INB_CONTROL_MATCH" , 0x11800F0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 213},
|
|
{"IOB_INB_CONTROL_MATCH_ENB" , 0x11800F0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 214},
|
|
{"IOB_INB_DATA_MATCH" , 0x11800F0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 215},
|
|
{"IOB_INB_DATA_MATCH_ENB" , 0x11800F0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 216},
|
|
{"IOB_INT_ENB" , 0x11800F0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 217},
|
|
{"IOB_INT_SUM" , 0x11800F0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 218},
|
|
{"IOB_N2C_L2C_PRI_CNT" , 0x11800F0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 219},
|
|
{"IOB_N2C_RSP_PRI_CNT" , 0x11800F0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 220},
|
|
{"IOB_OUTB_COM_PRI_CNT" , 0x11800F0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 221},
|
|
{"IOB_OUTB_CONTROL_MATCH" , 0x11800F0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 222},
|
|
{"IOB_OUTB_CONTROL_MATCH_ENB" , 0x11800F00000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 223},
|
|
{"IOB_OUTB_DATA_MATCH" , 0x11800F0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 224},
|
|
{"IOB_OUTB_DATA_MATCH_ENB" , 0x11800F00000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 225},
|
|
{"IOB_OUTB_FPA_PRI_CNT" , 0x11800F0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 226},
|
|
{"IOB_OUTB_REQ_PRI_CNT" , 0x11800F0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 227},
|
|
{"IOB_P2C_REQ_PRI_CNT" , 0x11800F0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 228},
|
|
{"IOB_PKT_ERR" , 0x11800F0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 229},
|
|
{"IOB_TO_CMB_CREDITS" , 0x11800F00000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 230},
|
|
{"IPD_1ST_MBUFF_SKIP" , 0x14F0000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 231},
|
|
{"IPD_1ST_NEXT_PTR_BACK" , 0x14F0000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 232},
|
|
{"IPD_2ND_NEXT_PTR_BACK" , 0x14F0000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 233},
|
|
{"IPD_BIST_STATUS" , 0x14F00000007F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 234},
|
|
{"IPD_BP_PRT_RED_END" , 0x14F0000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 235},
|
|
{"IPD_CLK_COUNT" , 0x14F0000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 236},
|
|
{"IPD_CTL_STATUS" , 0x14F0000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 237},
|
|
{"IPD_INT_ENB" , 0x14F0000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 238},
|
|
{"IPD_INT_SUM" , 0x14F0000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 239},
|
|
{"IPD_NOT_1ST_MBUFF_SKIP" , 0x14F0000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 240},
|
|
{"IPD_PACKET_MBUFF_SIZE" , 0x14F0000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 241},
|
|
{"IPD_PKT_PTR_VALID" , 0x14F0000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 242},
|
|
{"IPD_PORT0_BP_PAGE_CNT" , 0x14F0000000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
|
|
{"IPD_PORT1_BP_PAGE_CNT" , 0x14F0000000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
|
|
{"IPD_PORT2_BP_PAGE_CNT" , 0x14F0000000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
|
|
{"IPD_PORT3_BP_PAGE_CNT" , 0x14F0000000040ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
|
|
{"IPD_PORT32_BP_PAGE_CNT" , 0x14F0000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
|
|
{"IPD_PORT33_BP_PAGE_CNT" , 0x14F0000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
|
|
{"IPD_PORT34_BP_PAGE_CNT" , 0x14F0000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
|
|
{"IPD_PORT35_BP_PAGE_CNT" , 0x14F0000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 243},
|
|
{"IPD_PORT36_BP_PAGE_CNT2" , 0x14F0000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
|
|
{"IPD_PORT37_BP_PAGE_CNT2" , 0x14F0000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
|
|
{"IPD_PORT38_BP_PAGE_CNT2" , 0x14F0000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
|
|
{"IPD_PORT39_BP_PAGE_CNT2" , 0x14F0000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 244},
|
|
{"IPD_PORT_BP_COUNTERS2_PAIR36", 0x14F0000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
|
|
{"IPD_PORT_BP_COUNTERS2_PAIR37", 0x14F0000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
|
|
{"IPD_PORT_BP_COUNTERS2_PAIR38", 0x14F0000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
|
|
{"IPD_PORT_BP_COUNTERS2_PAIR39", 0x14F00000003A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 245},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR0" , 0x14F00000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR1" , 0x14F00000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR2" , 0x14F00000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR3" , 0x14F00000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR32" , 0x14F00000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR33" , 0x14F00000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR34" , 0x14F00000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_PORT_BP_COUNTERS_PAIR35" , 0x14F00000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 246},
|
|
{"IPD_PORT_QOS_0_CNT" , 0x14F0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_1_CNT" , 0x14F0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_2_CNT" , 0x14F0000000898ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_3_CNT" , 0x14F00000008A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_4_CNT" , 0x14F00000008A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_5_CNT" , 0x14F00000008B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_6_CNT" , 0x14F00000008B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_7_CNT" , 0x14F00000008C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_8_CNT" , 0x14F00000008C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_9_CNT" , 0x14F00000008D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_10_CNT" , 0x14F00000008D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_11_CNT" , 0x14F00000008E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_12_CNT" , 0x14F00000008E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_13_CNT" , 0x14F00000008F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_14_CNT" , 0x14F00000008F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_15_CNT" , 0x14F0000000900ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_16_CNT" , 0x14F0000000908ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_17_CNT" , 0x14F0000000910ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_18_CNT" , 0x14F0000000918ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_19_CNT" , 0x14F0000000920ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_20_CNT" , 0x14F0000000928ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_21_CNT" , 0x14F0000000930ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_22_CNT" , 0x14F0000000938ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_23_CNT" , 0x14F0000000940ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_24_CNT" , 0x14F0000000948ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_25_CNT" , 0x14F0000000950ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_26_CNT" , 0x14F0000000958ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_27_CNT" , 0x14F0000000960ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_28_CNT" , 0x14F0000000968ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_29_CNT" , 0x14F0000000970ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_30_CNT" , 0x14F0000000978ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_31_CNT" , 0x14F0000000980ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_256_CNT" , 0x14F0000001088ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_257_CNT" , 0x14F0000001090ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_258_CNT" , 0x14F0000001098ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_259_CNT" , 0x14F00000010A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_260_CNT" , 0x14F00000010A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_261_CNT" , 0x14F00000010B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_262_CNT" , 0x14F00000010B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_263_CNT" , 0x14F00000010C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_264_CNT" , 0x14F00000010C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_265_CNT" , 0x14F00000010D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_266_CNT" , 0x14F00000010D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_267_CNT" , 0x14F00000010E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_268_CNT" , 0x14F00000010E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_269_CNT" , 0x14F00000010F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_270_CNT" , 0x14F00000010F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_271_CNT" , 0x14F0000001100ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_272_CNT" , 0x14F0000001108ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_273_CNT" , 0x14F0000001110ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_274_CNT" , 0x14F0000001118ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_275_CNT" , 0x14F0000001120ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_276_CNT" , 0x14F0000001128ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_277_CNT" , 0x14F0000001130ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_278_CNT" , 0x14F0000001138ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_279_CNT" , 0x14F0000001140ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_280_CNT" , 0x14F0000001148ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_281_CNT" , 0x14F0000001150ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_282_CNT" , 0x14F0000001158ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_283_CNT" , 0x14F0000001160ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_284_CNT" , 0x14F0000001168ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_285_CNT" , 0x14F0000001170ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_286_CNT" , 0x14F0000001178ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_287_CNT" , 0x14F0000001180ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_288_CNT" , 0x14F0000001188ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_289_CNT" , 0x14F0000001190ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_290_CNT" , 0x14F0000001198ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_291_CNT" , 0x14F00000011A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_292_CNT" , 0x14F00000011A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_293_CNT" , 0x14F00000011B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_294_CNT" , 0x14F00000011B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_295_CNT" , 0x14F00000011C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_296_CNT" , 0x14F00000011C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_297_CNT" , 0x14F00000011D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_298_CNT" , 0x14F00000011D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_299_CNT" , 0x14F00000011E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_300_CNT" , 0x14F00000011E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_301_CNT" , 0x14F00000011F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_302_CNT" , 0x14F00000011F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_303_CNT" , 0x14F0000001200ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_304_CNT" , 0x14F0000001208ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_305_CNT" , 0x14F0000001210ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_306_CNT" , 0x14F0000001218ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_307_CNT" , 0x14F0000001220ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_308_CNT" , 0x14F0000001228ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_309_CNT" , 0x14F0000001230ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_310_CNT" , 0x14F0000001238ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_311_CNT" , 0x14F0000001240ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_312_CNT" , 0x14F0000001248ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_313_CNT" , 0x14F0000001250ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_314_CNT" , 0x14F0000001258ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_315_CNT" , 0x14F0000001260ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_316_CNT" , 0x14F0000001268ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_317_CNT" , 0x14F0000001270ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_318_CNT" , 0x14F0000001278ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_319_CNT" , 0x14F0000001280ull, CVMX_CSR_DB_TYPE_NCB, 64, 247},
|
|
{"IPD_PORT_QOS_INT0" , 0x14F0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
|
|
{"IPD_PORT_QOS_INT4" , 0x14F0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 248},
|
|
{"IPD_PORT_QOS_INT_ENB0" , 0x14F0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
|
|
{"IPD_PORT_QOS_INT_ENB4" , 0x14F0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 249},
|
|
{"IPD_PRC_HOLD_PTR_FIFO_CTL" , 0x14F0000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 250},
|
|
{"IPD_PRC_PORT_PTR_FIFO_CTL" , 0x14F0000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 251},
|
|
{"IPD_PTR_COUNT" , 0x14F0000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 252},
|
|
{"IPD_PWP_PTR_FIFO_CTL" , 0x14F0000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 253},
|
|
{"IPD_QOS0_RED_MARKS" , 0x14F0000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
|
|
{"IPD_QOS1_RED_MARKS" , 0x14F0000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
|
|
{"IPD_QOS2_RED_MARKS" , 0x14F0000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
|
|
{"IPD_QOS3_RED_MARKS" , 0x14F0000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
|
|
{"IPD_QOS4_RED_MARKS" , 0x14F0000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
|
|
{"IPD_QOS5_RED_MARKS" , 0x14F00000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
|
|
{"IPD_QOS6_RED_MARKS" , 0x14F00000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
|
|
{"IPD_QOS7_RED_MARKS" , 0x14F00000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 254},
|
|
{"IPD_QUE0_FREE_PAGE_CNT" , 0x14F0000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 255},
|
|
{"IPD_RED_PORT_ENABLE" , 0x14F00000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 256},
|
|
{"IPD_RED_PORT_ENABLE2" , 0x14F00000003A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 257},
|
|
{"IPD_RED_QUE0_PARAM" , 0x14F00000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
|
|
{"IPD_RED_QUE1_PARAM" , 0x14F00000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
|
|
{"IPD_RED_QUE2_PARAM" , 0x14F00000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
|
|
{"IPD_RED_QUE3_PARAM" , 0x14F00000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
|
|
{"IPD_RED_QUE4_PARAM" , 0x14F0000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
|
|
{"IPD_RED_QUE5_PARAM" , 0x14F0000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
|
|
{"IPD_RED_QUE6_PARAM" , 0x14F0000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
|
|
{"IPD_RED_QUE7_PARAM" , 0x14F0000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 258},
|
|
{"IPD_SUB_PORT_BP_PAGE_CNT" , 0x14F0000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 259},
|
|
{"IPD_SUB_PORT_FCS" , 0x14F0000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 260},
|
|
{"IPD_SUB_PORT_QOS_CNT" , 0x14F0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 261},
|
|
{"IPD_WQE_FPA_QUEUE" , 0x14F0000000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 262},
|
|
{"IPD_WQE_PTR_VALID" , 0x14F0000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 263},
|
|
{"L2C_BST0" , 0x11800800007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 264},
|
|
{"L2C_BST1" , 0x11800800007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 265},
|
|
{"L2C_BST2" , 0x11800800007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 266},
|
|
{"L2C_CFG" , 0x1180080000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 267},
|
|
{"L2C_DBG" , 0x1180080000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 268},
|
|
{"L2C_DUT" , 0x1180080000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 269},
|
|
{"L2C_GRPWRR0" , 0x11800800000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 270},
|
|
{"L2C_GRPWRR1" , 0x11800800000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 271},
|
|
{"L2C_INT_EN" , 0x1180080000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 272},
|
|
{"L2C_INT_STAT" , 0x11800800000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 273},
|
|
{"L2C_LCKBASE" , 0x1180080000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 274},
|
|
{"L2C_LCKOFF" , 0x1180080000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 275},
|
|
{"L2C_LFB0" , 0x1180080000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 276},
|
|
{"L2C_LFB1" , 0x1180080000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 277},
|
|
{"L2C_LFB2" , 0x1180080000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 278},
|
|
{"L2C_LFB3" , 0x11800800000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 279},
|
|
{"L2C_OOB" , 0x11800800000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 280},
|
|
{"L2C_OOB1" , 0x11800800000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 281},
|
|
{"L2C_OOB2" , 0x11800800000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 282},
|
|
{"L2C_OOB3" , 0x11800800000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 283},
|
|
{"L2C_PFC0" , 0x1180080000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
|
|
{"L2C_PFC1" , 0x11800800000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
|
|
{"L2C_PFC2" , 0x11800800000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
|
|
{"L2C_PFC3" , 0x11800800000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 284},
|
|
{"L2C_PFCTL" , 0x1180080000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 285},
|
|
{"L2C_PPGRP" , 0x11800800000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 286},
|
|
{"L2C_SPAR0" , 0x1180080000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 287},
|
|
{"L2C_SPAR4" , 0x1180080000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 288},
|
|
{"L2D_BST0" , 0x1180080000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 289},
|
|
{"L2D_BST1" , 0x1180080000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 290},
|
|
{"L2D_BST2" , 0x1180080000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 291},
|
|
{"L2D_BST3" , 0x1180080000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 292},
|
|
{"L2D_ERR" , 0x1180080000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 293},
|
|
{"L2D_FADR" , 0x1180080000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 294},
|
|
{"L2D_FSYN0" , 0x1180080000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 295},
|
|
{"L2D_FSYN1" , 0x1180080000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 296},
|
|
{"L2D_FUS0" , 0x11800800007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 297},
|
|
{"L2D_FUS1" , 0x11800800007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 298},
|
|
{"L2D_FUS2" , 0x11800800007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 299},
|
|
{"L2D_FUS3" , 0x11800800007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 300},
|
|
{"L2T_ERR" , 0x1180080000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 301},
|
|
{"LMC0_BIST_CTL" , 0x11800880000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 302},
|
|
{"LMC0_BIST_RESULT" , 0x11800880000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 303},
|
|
{"LMC0_COMP_CTL" , 0x1180088000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 304},
|
|
{"LMC0_CTL" , 0x1180088000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 305},
|
|
{"LMC0_CTL1" , 0x1180088000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 306},
|
|
{"LMC0_DCLK_CNT_HI" , 0x1180088000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 307},
|
|
{"LMC0_DCLK_CNT_LO" , 0x1180088000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 308},
|
|
{"LMC0_DDR2_CTL" , 0x1180088000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 309},
|
|
{"LMC0_DELAY_CFG" , 0x1180088000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 310},
|
|
{"LMC0_DLL_CTL" , 0x11800880000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 311},
|
|
{"LMC0_DUAL_MEMCFG" , 0x1180088000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 312},
|
|
{"LMC0_ECC_SYND" , 0x1180088000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 313},
|
|
{"LMC0_FADR" , 0x1180088000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 314},
|
|
{"LMC0_IFB_CNT_HI" , 0x1180088000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 315},
|
|
{"LMC0_IFB_CNT_LO" , 0x1180088000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 316},
|
|
{"LMC0_MEM_CFG0" , 0x1180088000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 317},
|
|
{"LMC0_MEM_CFG1" , 0x1180088000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 318},
|
|
{"LMC0_NXM" , 0x11800880000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 319},
|
|
{"LMC0_OPS_CNT_HI" , 0x1180088000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 320},
|
|
{"LMC0_OPS_CNT_LO" , 0x1180088000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 321},
|
|
{"LMC0_PLL_CTL" , 0x11800880000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 322},
|
|
{"LMC0_PLL_STATUS" , 0x11800880000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 323},
|
|
{"LMC0_READ_LEVEL_CTL" , 0x1180088000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 324},
|
|
{"LMC0_READ_LEVEL_DBG" , 0x1180088000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 325},
|
|
{"LMC0_READ_LEVEL_RANK000" , 0x1180088000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
|
|
{"LMC0_READ_LEVEL_RANK001" , 0x1180088000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
|
|
{"LMC0_READ_LEVEL_RANK002" , 0x1180088000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
|
|
{"LMC0_READ_LEVEL_RANK003" , 0x1180088000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 326},
|
|
{"LMC0_RODT_COMP_CTL" , 0x11800880000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 327},
|
|
{"LMC0_RODT_CTL" , 0x1180088000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 328},
|
|
{"LMC0_WODT_CTL0" , 0x1180088000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 329},
|
|
{"LMC0_WODT_CTL1" , 0x1180088000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 330},
|
|
{"MIO_BOOT_BIST_STAT" , 0x11800000000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 331},
|
|
{"MIO_BOOT_COMP" , 0x11800000000B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 332},
|
|
{"MIO_BOOT_DMA_CFG0" , 0x1180000000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
|
|
{"MIO_BOOT_DMA_CFG1" , 0x1180000000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 333},
|
|
{"MIO_BOOT_DMA_INT0" , 0x1180000000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 334},
|
|
{"MIO_BOOT_DMA_INT1" , 0x1180000000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 334},
|
|
{"MIO_BOOT_DMA_INT_EN0" , 0x1180000000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 335},
|
|
{"MIO_BOOT_DMA_INT_EN1" , 0x1180000000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 335},
|
|
{"MIO_BOOT_DMA_TIM0" , 0x1180000000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 336},
|
|
{"MIO_BOOT_DMA_TIM1" , 0x1180000000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 336},
|
|
{"MIO_BOOT_ERR" , 0x11800000000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 337},
|
|
{"MIO_BOOT_INT" , 0x11800000000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 338},
|
|
{"MIO_BOOT_LOC_ADR" , 0x1180000000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 339},
|
|
{"MIO_BOOT_LOC_CFG0" , 0x1180000000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 340},
|
|
{"MIO_BOOT_LOC_CFG1" , 0x1180000000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 340},
|
|
{"MIO_BOOT_LOC_DAT" , 0x1180000000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 341},
|
|
{"MIO_BOOT_PIN_DEFS" , 0x11800000000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 342},
|
|
{"MIO_BOOT_REG_CFG0" , 0x1180000000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
|
|
{"MIO_BOOT_REG_CFG1" , 0x1180000000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
|
|
{"MIO_BOOT_REG_CFG2" , 0x1180000000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
|
|
{"MIO_BOOT_REG_CFG3" , 0x1180000000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
|
|
{"MIO_BOOT_REG_CFG4" , 0x1180000000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
|
|
{"MIO_BOOT_REG_CFG5" , 0x1180000000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
|
|
{"MIO_BOOT_REG_CFG6" , 0x1180000000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
|
|
{"MIO_BOOT_REG_CFG7" , 0x1180000000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 343},
|
|
{"MIO_BOOT_REG_TIM0" , 0x1180000000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
|
|
{"MIO_BOOT_REG_TIM1" , 0x1180000000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
|
|
{"MIO_BOOT_REG_TIM2" , 0x1180000000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
|
|
{"MIO_BOOT_REG_TIM3" , 0x1180000000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
|
|
{"MIO_BOOT_REG_TIM4" , 0x1180000000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
|
|
{"MIO_BOOT_REG_TIM5" , 0x1180000000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
|
|
{"MIO_BOOT_REG_TIM6" , 0x1180000000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
|
|
{"MIO_BOOT_REG_TIM7" , 0x1180000000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 344},
|
|
{"MIO_BOOT_THR" , 0x11800000000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 345},
|
|
{"MIO_FUS_BNK_DAT0" , 0x1180000001520ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
|
|
{"MIO_FUS_BNK_DAT1" , 0x1180000001528ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
|
|
{"MIO_FUS_BNK_DAT2" , 0x1180000001530ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
|
|
{"MIO_FUS_BNK_DAT3" , 0x1180000001538ull, CVMX_CSR_DB_TYPE_RSL, 64, 346},
|
|
{"MIO_FUS_DAT0" , 0x1180000001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 347},
|
|
{"MIO_FUS_DAT1" , 0x1180000001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 348},
|
|
{"MIO_FUS_DAT2" , 0x1180000001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 349},
|
|
{"MIO_FUS_DAT3" , 0x1180000001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 350},
|
|
{"MIO_FUS_EMA" , 0x1180000001550ull, CVMX_CSR_DB_TYPE_RSL, 64, 351},
|
|
{"MIO_FUS_PDF" , 0x1180000001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 352},
|
|
{"MIO_FUS_PLL" , 0x1180000001580ull, CVMX_CSR_DB_TYPE_RSL, 64, 353},
|
|
{"MIO_FUS_PROG" , 0x1180000001510ull, CVMX_CSR_DB_TYPE_RSL, 64, 354},
|
|
{"MIO_FUS_PROG_TIMES" , 0x1180000001518ull, CVMX_CSR_DB_TYPE_RSL, 64, 355},
|
|
{"MIO_FUS_RCMD" , 0x1180000001500ull, CVMX_CSR_DB_TYPE_RSL, 64, 356},
|
|
{"MIO_FUS_SPR_REPAIR_RES" , 0x1180000001548ull, CVMX_CSR_DB_TYPE_RSL, 64, 357},
|
|
{"MIO_FUS_SPR_REPAIR_SUM" , 0x1180000001540ull, CVMX_CSR_DB_TYPE_RSL, 64, 358},
|
|
{"MIO_FUS_WADR" , 0x1180000001508ull, CVMX_CSR_DB_TYPE_RSL, 64, 359},
|
|
{"MIO_NDF_DMA_CFG" , 0x1180000000168ull, CVMX_CSR_DB_TYPE_RSL, 64, 360},
|
|
{"MIO_NDF_DMA_INT" , 0x1180000000170ull, CVMX_CSR_DB_TYPE_RSL, 64, 361},
|
|
{"MIO_NDF_DMA_INT_EN" , 0x1180000000178ull, CVMX_CSR_DB_TYPE_RSL, 64, 362},
|
|
{"MIO_TWS0_INT" , 0x1180000001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
|
|
{"MIO_TWS1_INT" , 0x1180000001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 363},
|
|
{"MIO_TWS0_SW_TWSI" , 0x1180000001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 364},
|
|
{"MIO_TWS1_SW_TWSI" , 0x1180000001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 364},
|
|
{"MIO_TWS0_SW_TWSI_EXT" , 0x1180000001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
|
|
{"MIO_TWS1_SW_TWSI_EXT" , 0x1180000001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 365},
|
|
{"MIO_TWS0_TWSI_SW" , 0x1180000001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
|
|
{"MIO_TWS1_TWSI_SW" , 0x1180000001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 366},
|
|
{"MIO_UART0_DLH" , 0x1180000000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
|
|
{"MIO_UART1_DLH" , 0x1180000000C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 367},
|
|
{"MIO_UART0_DLL" , 0x1180000000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
|
|
{"MIO_UART1_DLL" , 0x1180000000C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 368},
|
|
{"MIO_UART0_FAR" , 0x1180000000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
|
|
{"MIO_UART1_FAR" , 0x1180000000D20ull, CVMX_CSR_DB_TYPE_RSL, 64, 369},
|
|
{"MIO_UART0_FCR" , 0x1180000000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
|
|
{"MIO_UART1_FCR" , 0x1180000000C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 370},
|
|
{"MIO_UART0_HTX" , 0x1180000000B08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
|
|
{"MIO_UART1_HTX" , 0x1180000000F08ull, CVMX_CSR_DB_TYPE_RSL, 64, 371},
|
|
{"MIO_UART0_IER" , 0x1180000000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
|
|
{"MIO_UART1_IER" , 0x1180000000C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 372},
|
|
{"MIO_UART0_IIR" , 0x1180000000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
|
|
{"MIO_UART1_IIR" , 0x1180000000C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 373},
|
|
{"MIO_UART0_LCR" , 0x1180000000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
|
|
{"MIO_UART1_LCR" , 0x1180000000C18ull, CVMX_CSR_DB_TYPE_RSL, 64, 374},
|
|
{"MIO_UART0_LSR" , 0x1180000000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
|
|
{"MIO_UART1_LSR" , 0x1180000000C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 375},
|
|
{"MIO_UART0_MCR" , 0x1180000000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
|
|
{"MIO_UART1_MCR" , 0x1180000000C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 376},
|
|
{"MIO_UART0_MSR" , 0x1180000000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
|
|
{"MIO_UART1_MSR" , 0x1180000000C30ull, CVMX_CSR_DB_TYPE_RSL, 64, 377},
|
|
{"MIO_UART0_RBR" , 0x1180000000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
|
|
{"MIO_UART1_RBR" , 0x1180000000C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 378},
|
|
{"MIO_UART0_RFL" , 0x1180000000A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
|
|
{"MIO_UART1_RFL" , 0x1180000000E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 379},
|
|
{"MIO_UART0_RFW" , 0x1180000000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
|
|
{"MIO_UART1_RFW" , 0x1180000000D30ull, CVMX_CSR_DB_TYPE_RSL, 64, 380},
|
|
{"MIO_UART0_SBCR" , 0x1180000000A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
|
|
{"MIO_UART1_SBCR" , 0x1180000000E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 381},
|
|
{"MIO_UART0_SCR" , 0x1180000000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
|
|
{"MIO_UART1_SCR" , 0x1180000000C38ull, CVMX_CSR_DB_TYPE_RSL, 64, 382},
|
|
{"MIO_UART0_SFE" , 0x1180000000A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
|
|
{"MIO_UART1_SFE" , 0x1180000000E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 383},
|
|
{"MIO_UART0_SRR" , 0x1180000000A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
|
|
{"MIO_UART1_SRR" , 0x1180000000E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 384},
|
|
{"MIO_UART0_SRT" , 0x1180000000A38ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
|
|
{"MIO_UART1_SRT" , 0x1180000000E38ull, CVMX_CSR_DB_TYPE_RSL, 64, 385},
|
|
{"MIO_UART0_SRTS" , 0x1180000000A18ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
|
|
{"MIO_UART1_SRTS" , 0x1180000000E18ull, CVMX_CSR_DB_TYPE_RSL, 64, 386},
|
|
{"MIO_UART0_STT" , 0x1180000000B00ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
|
|
{"MIO_UART1_STT" , 0x1180000000F00ull, CVMX_CSR_DB_TYPE_RSL, 64, 387},
|
|
{"MIO_UART0_TFL" , 0x1180000000A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
|
|
{"MIO_UART1_TFL" , 0x1180000000E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 388},
|
|
{"MIO_UART0_TFR" , 0x1180000000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
|
|
{"MIO_UART1_TFR" , 0x1180000000D28ull, CVMX_CSR_DB_TYPE_RSL, 64, 389},
|
|
{"MIO_UART0_THR" , 0x1180000000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
|
|
{"MIO_UART1_THR" , 0x1180000000C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 390},
|
|
{"MIO_UART0_USR" , 0x1180000000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
|
|
{"MIO_UART1_USR" , 0x1180000000D38ull, CVMX_CSR_DB_TYPE_RSL, 64, 391},
|
|
{"MIO_UART2_DLH" , 0x1180000000488ull, CVMX_CSR_DB_TYPE_RSL, 64, 392},
|
|
{"MIO_UART2_DLL" , 0x1180000000480ull, CVMX_CSR_DB_TYPE_RSL, 64, 393},
|
|
{"MIO_UART2_FAR" , 0x1180000000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 394},
|
|
{"MIO_UART2_FCR" , 0x1180000000450ull, CVMX_CSR_DB_TYPE_RSL, 64, 395},
|
|
{"MIO_UART2_HTX" , 0x1180000000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 396},
|
|
{"MIO_UART2_IER" , 0x1180000000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 397},
|
|
{"MIO_UART2_IIR" , 0x1180000000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 398},
|
|
{"MIO_UART2_LCR" , 0x1180000000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 399},
|
|
{"MIO_UART2_LSR" , 0x1180000000428ull, CVMX_CSR_DB_TYPE_RSL, 64, 400},
|
|
{"MIO_UART2_MCR" , 0x1180000000420ull, CVMX_CSR_DB_TYPE_RSL, 64, 401},
|
|
{"MIO_UART2_MSR" , 0x1180000000430ull, CVMX_CSR_DB_TYPE_RSL, 64, 402},
|
|
{"MIO_UART2_RBR" , 0x1180000000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 403},
|
|
{"MIO_UART2_RFL" , 0x1180000000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 404},
|
|
{"MIO_UART2_RFW" , 0x1180000000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 405},
|
|
{"MIO_UART2_SBCR" , 0x1180000000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 406},
|
|
{"MIO_UART2_SCR" , 0x1180000000438ull, CVMX_CSR_DB_TYPE_RSL, 64, 407},
|
|
{"MIO_UART2_SFE" , 0x1180000000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 408},
|
|
{"MIO_UART2_SRR" , 0x1180000000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 409},
|
|
{"MIO_UART2_SRT" , 0x1180000000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 410},
|
|
{"MIO_UART2_SRTS" , 0x1180000000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 411},
|
|
{"MIO_UART2_STT" , 0x1180000000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 412},
|
|
{"MIO_UART2_TFL" , 0x1180000000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 413},
|
|
{"MIO_UART2_TFR" , 0x1180000000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 414},
|
|
{"MIO_UART2_THR" , 0x1180000000440ull, CVMX_CSR_DB_TYPE_RSL, 64, 415},
|
|
{"MIO_UART2_USR" , 0x1180000000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 416},
|
|
{"MIX0_BIST" , 0x1070000100078ull, CVMX_CSR_DB_TYPE_NCB, 64, 417},
|
|
{"MIX1_BIST" , 0x1070000100878ull, CVMX_CSR_DB_TYPE_NCB, 64, 417},
|
|
{"MIX0_CTL" , 0x1070000100020ull, CVMX_CSR_DB_TYPE_NCB, 64, 418},
|
|
{"MIX1_CTL" , 0x1070000100820ull, CVMX_CSR_DB_TYPE_NCB, 64, 418},
|
|
{"MIX0_INTENA" , 0x1070000100050ull, CVMX_CSR_DB_TYPE_NCB, 64, 419},
|
|
{"MIX1_INTENA" , 0x1070000100850ull, CVMX_CSR_DB_TYPE_NCB, 64, 419},
|
|
{"MIX0_IRCNT" , 0x1070000100030ull, CVMX_CSR_DB_TYPE_NCB, 64, 420},
|
|
{"MIX1_IRCNT" , 0x1070000100830ull, CVMX_CSR_DB_TYPE_NCB, 64, 420},
|
|
{"MIX0_IRHWM" , 0x1070000100028ull, CVMX_CSR_DB_TYPE_NCB, 64, 421},
|
|
{"MIX1_IRHWM" , 0x1070000100828ull, CVMX_CSR_DB_TYPE_NCB, 64, 421},
|
|
{"MIX0_IRING1" , 0x1070000100010ull, CVMX_CSR_DB_TYPE_NCB, 64, 422},
|
|
{"MIX1_IRING1" , 0x1070000100810ull, CVMX_CSR_DB_TYPE_NCB, 64, 422},
|
|
{"MIX0_IRING2" , 0x1070000100018ull, CVMX_CSR_DB_TYPE_NCB, 64, 423},
|
|
{"MIX1_IRING2" , 0x1070000100818ull, CVMX_CSR_DB_TYPE_NCB, 64, 423},
|
|
{"MIX0_ISR" , 0x1070000100048ull, CVMX_CSR_DB_TYPE_NCB, 64, 424},
|
|
{"MIX1_ISR" , 0x1070000100848ull, CVMX_CSR_DB_TYPE_NCB, 64, 424},
|
|
{"MIX0_ORCNT" , 0x1070000100040ull, CVMX_CSR_DB_TYPE_NCB, 64, 425},
|
|
{"MIX1_ORCNT" , 0x1070000100840ull, CVMX_CSR_DB_TYPE_NCB, 64, 425},
|
|
{"MIX0_ORHWM" , 0x1070000100038ull, CVMX_CSR_DB_TYPE_NCB, 64, 426},
|
|
{"MIX1_ORHWM" , 0x1070000100838ull, CVMX_CSR_DB_TYPE_NCB, 64, 426},
|
|
{"MIX0_ORING1" , 0x1070000100000ull, CVMX_CSR_DB_TYPE_NCB, 64, 427},
|
|
{"MIX1_ORING1" , 0x1070000100800ull, CVMX_CSR_DB_TYPE_NCB, 64, 427},
|
|
{"MIX0_ORING2" , 0x1070000100008ull, CVMX_CSR_DB_TYPE_NCB, 64, 428},
|
|
{"MIX1_ORING2" , 0x1070000100808ull, CVMX_CSR_DB_TYPE_NCB, 64, 428},
|
|
{"MIX0_REMCNT" , 0x1070000100058ull, CVMX_CSR_DB_TYPE_NCB, 64, 429},
|
|
{"MIX1_REMCNT" , 0x1070000100858ull, CVMX_CSR_DB_TYPE_NCB, 64, 429},
|
|
{"NDF_BT_PG_INFO" , 0x1070001000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 430},
|
|
{"NDF_CMD" , 0x1070001000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 431},
|
|
{"NDF_DRBELL" , 0x1070001000030ull, CVMX_CSR_DB_TYPE_NCB, 64, 432},
|
|
{"NDF_ECC_CNT" , 0x1070001000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 433},
|
|
{"NDF_INT" , 0x1070001000020ull, CVMX_CSR_DB_TYPE_NCB, 64, 434},
|
|
{"NDF_INT_EN" , 0x1070001000028ull, CVMX_CSR_DB_TYPE_NCB, 64, 435},
|
|
{"NDF_MISC" , 0x1070001000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 436},
|
|
{"NDF_ST_REG" , 0x1070001000038ull, CVMX_CSR_DB_TYPE_NCB, 64, 437},
|
|
{"NPEI_BAR1_INDEX0" , 0x11F0000008000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX1" , 0x11F0000008010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX2" , 0x11F0000008020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX3" , 0x11F0000008030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX4" , 0x11F0000008040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX5" , 0x11F0000008050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX6" , 0x11F0000008060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX7" , 0x11F0000008070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX8" , 0x11F0000008080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX9" , 0x11F0000008090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX10" , 0x11F00000080A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX11" , 0x11F00000080B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX12" , 0x11F00000080C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX13" , 0x11F00000080D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX14" , 0x11F00000080E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX15" , 0x11F00000080F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX16" , 0x11F0000008100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX17" , 0x11F0000008110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX18" , 0x11F0000008120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX19" , 0x11F0000008130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX20" , 0x11F0000008140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX21" , 0x11F0000008150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX22" , 0x11F0000008160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX23" , 0x11F0000008170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX24" , 0x11F0000008180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX25" , 0x11F0000008190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX26" , 0x11F00000081A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX27" , 0x11F00000081B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX28" , 0x11F00000081C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX29" , 0x11F00000081D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX30" , 0x11F00000081E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BAR1_INDEX31" , 0x11F00000081F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 438},
|
|
{"NPEI_BIST_STATUS" , 0x11F0000008580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 439},
|
|
{"NPEI_BIST_STATUS2" , 0x11F0000008680ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 440},
|
|
{"NPEI_CTL_PORT0" , 0x11F0000008250ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 441},
|
|
{"NPEI_CTL_PORT1" , 0x11F0000008260ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 442},
|
|
{"NPEI_CTL_STATUS" , 0x11F0000008570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 443},
|
|
{"NPEI_CTL_STATUS2" , 0x11F000000BC00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 444},
|
|
{"NPEI_DATA_OUT_CNT" , 0x11F00000085F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 445},
|
|
{"NPEI_DBG_DATA" , 0x11F0000008510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 446},
|
|
{"NPEI_DBG_SELECT" , 0x11F0000008500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 447},
|
|
{"NPEI_DMA0_COUNTS" , 0x11F0000008450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 448},
|
|
{"NPEI_DMA1_COUNTS" , 0x11F0000008460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 448},
|
|
{"NPEI_DMA2_COUNTS" , 0x11F0000008470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 448},
|
|
{"NPEI_DMA3_COUNTS" , 0x11F0000008480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 448},
|
|
{"NPEI_DMA4_COUNTS" , 0x11F0000008490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 448},
|
|
{"NPEI_DMA0_DBELL" , 0x11F00000083B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 449},
|
|
{"NPEI_DMA1_DBELL" , 0x11F00000083C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 449},
|
|
{"NPEI_DMA2_DBELL" , 0x11F00000083D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 449},
|
|
{"NPEI_DMA3_DBELL" , 0x11F00000083E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 449},
|
|
{"NPEI_DMA4_DBELL" , 0x11F00000083F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 32, 449},
|
|
{"NPEI_DMA0_IBUFF_SADDR" , 0x11F0000008400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 450},
|
|
{"NPEI_DMA1_IBUFF_SADDR" , 0x11F0000008410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 450},
|
|
{"NPEI_DMA2_IBUFF_SADDR" , 0x11F0000008420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 450},
|
|
{"NPEI_DMA3_IBUFF_SADDR" , 0x11F0000008430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 450},
|
|
{"NPEI_DMA4_IBUFF_SADDR" , 0x11F0000008440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 450},
|
|
{"NPEI_DMA0_NADDR" , 0x11F00000084A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 451},
|
|
{"NPEI_DMA1_NADDR" , 0x11F00000084B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 451},
|
|
{"NPEI_DMA2_NADDR" , 0x11F00000084C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 451},
|
|
{"NPEI_DMA3_NADDR" , 0x11F00000084D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 451},
|
|
{"NPEI_DMA4_NADDR" , 0x11F00000084E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 451},
|
|
{"NPEI_DMA0_INT_LEVEL" , 0x11F00000085C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 452},
|
|
{"NPEI_DMA1_INT_LEVEL" , 0x11F00000085D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 453},
|
|
{"NPEI_DMA_CNTS" , 0x11F00000085E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 454},
|
|
{"NPEI_DMA_CONTROL" , 0x11F00000083A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 455},
|
|
{"NPEI_DMA_PCIE_REQ_NUM" , 0x11F00000085B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 456},
|
|
{"NPEI_DMA_STATE1" , 0x11F00000086C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 457},
|
|
{"NPEI_DMA_STATE2" , 0x11F00000086D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 458},
|
|
{"NPEI_INT_A_ENB" , 0x11F0000008560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 459},
|
|
{"NPEI_INT_A_ENB2" , 0x11F000000BCE0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 460},
|
|
{"NPEI_INT_A_SUM" , 0x11F0000008550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 461},
|
|
{"NPEI_INT_ENB" , 0x11F0000008540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 462},
|
|
{"NPEI_INT_ENB2" , 0x11F000000BCD0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 463},
|
|
{"NPEI_INT_INFO" , 0x11F0000008590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 464},
|
|
{"NPEI_INT_SUM" , 0x11F0000008530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 465},
|
|
{"NPEI_INT_SUM2" , 0x11F000000BCC0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 466},
|
|
{"NPEI_LAST_WIN_RDATA0" , 0x11F0000008600ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 467},
|
|
{"NPEI_LAST_WIN_RDATA1" , 0x11F0000008610ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 468},
|
|
{"NPEI_MEM_ACCESS_CTL" , 0x11F00000084F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 469},
|
|
{"NPEI_MEM_ACCESS_SUBID12" , 0x11F0000008280ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
|
|
{"NPEI_MEM_ACCESS_SUBID13" , 0x11F0000008290ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
|
|
{"NPEI_MEM_ACCESS_SUBID14" , 0x11F00000082A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
|
|
{"NPEI_MEM_ACCESS_SUBID15" , 0x11F00000082B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
|
|
{"NPEI_MEM_ACCESS_SUBID16" , 0x11F00000082C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
|
|
{"NPEI_MEM_ACCESS_SUBID17" , 0x11F00000082D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
|
|
{"NPEI_MEM_ACCESS_SUBID18" , 0x11F00000082E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
|
|
{"NPEI_MEM_ACCESS_SUBID19" , 0x11F00000082F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
|
|
{"NPEI_MEM_ACCESS_SUBID20" , 0x11F0000008300ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
|
|
{"NPEI_MEM_ACCESS_SUBID21" , 0x11F0000008310ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
|
|
{"NPEI_MEM_ACCESS_SUBID22" , 0x11F0000008320ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
|
|
{"NPEI_MEM_ACCESS_SUBID23" , 0x11F0000008330ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
|
|
{"NPEI_MEM_ACCESS_SUBID24" , 0x11F0000008340ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
|
|
{"NPEI_MEM_ACCESS_SUBID25" , 0x11F0000008350ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
|
|
{"NPEI_MEM_ACCESS_SUBID26" , 0x11F0000008360ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
|
|
{"NPEI_MEM_ACCESS_SUBID27" , 0x11F0000008370ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 470},
|
|
{"NPEI_MSI_ENB0" , 0x11F000000BC50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 471},
|
|
{"NPEI_MSI_ENB1" , 0x11F000000BC60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 472},
|
|
{"NPEI_MSI_ENB2" , 0x11F000000BC70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 473},
|
|
{"NPEI_MSI_ENB3" , 0x11F000000BC80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 474},
|
|
{"NPEI_MSI_RCV0" , 0x11F000000BC10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 475},
|
|
{"NPEI_MSI_RCV1" , 0x11F000000BC20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 476},
|
|
{"NPEI_MSI_RCV2" , 0x11F000000BC30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 477},
|
|
{"NPEI_MSI_RCV3" , 0x11F000000BC40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 478},
|
|
{"NPEI_MSI_RD_MAP" , 0x11F000000BCA0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 479},
|
|
{"NPEI_MSI_W1C_ENB0" , 0x11F000000BCF0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 480},
|
|
{"NPEI_MSI_W1C_ENB1" , 0x11F000000BD00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 481},
|
|
{"NPEI_MSI_W1C_ENB2" , 0x11F000000BD10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 482},
|
|
{"NPEI_MSI_W1C_ENB3" , 0x11F000000BD20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 483},
|
|
{"NPEI_MSI_W1S_ENB0" , 0x11F000000BD30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 484},
|
|
{"NPEI_MSI_W1S_ENB1" , 0x11F000000BD40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 485},
|
|
{"NPEI_MSI_W1S_ENB2" , 0x11F000000BD50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 486},
|
|
{"NPEI_MSI_W1S_ENB3" , 0x11F000000BD60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 487},
|
|
{"NPEI_MSI_WR_MAP" , 0x11F000000BC90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 488},
|
|
{"NPEI_PCIE_CREDIT_CNT" , 0x11F000000BD70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 489},
|
|
{"NPEI_PCIE_MSI_RCV" , 0x11F000000BCB0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 490},
|
|
{"NPEI_PCIE_MSI_RCV_B1" , 0x11F0000008650ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 491},
|
|
{"NPEI_PCIE_MSI_RCV_B2" , 0x11F0000008660ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 492},
|
|
{"NPEI_PCIE_MSI_RCV_B3" , 0x11F0000008670ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 493},
|
|
{"NPEI_PKT0_CNTS" , 0x11F000000A400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT1_CNTS" , 0x11F000000A410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT2_CNTS" , 0x11F000000A420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT3_CNTS" , 0x11F000000A430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT4_CNTS" , 0x11F000000A440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT5_CNTS" , 0x11F000000A450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT6_CNTS" , 0x11F000000A460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT7_CNTS" , 0x11F000000A470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT8_CNTS" , 0x11F000000A480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT9_CNTS" , 0x11F000000A490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT10_CNTS" , 0x11F000000A4A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT11_CNTS" , 0x11F000000A4B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT12_CNTS" , 0x11F000000A4C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT13_CNTS" , 0x11F000000A4D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT14_CNTS" , 0x11F000000A4E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT15_CNTS" , 0x11F000000A4F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT16_CNTS" , 0x11F000000A500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT17_CNTS" , 0x11F000000A510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT18_CNTS" , 0x11F000000A520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT19_CNTS" , 0x11F000000A530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT20_CNTS" , 0x11F000000A540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT21_CNTS" , 0x11F000000A550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT22_CNTS" , 0x11F000000A560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT23_CNTS" , 0x11F000000A570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT24_CNTS" , 0x11F000000A580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT25_CNTS" , 0x11F000000A590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT26_CNTS" , 0x11F000000A5A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT27_CNTS" , 0x11F000000A5B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT28_CNTS" , 0x11F000000A5C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT29_CNTS" , 0x11F000000A5D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT30_CNTS" , 0x11F000000A5E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT31_CNTS" , 0x11F000000A5F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 494},
|
|
{"NPEI_PKT0_IN_BP" , 0x11F000000B800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT1_IN_BP" , 0x11F000000B810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT2_IN_BP" , 0x11F000000B820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT3_IN_BP" , 0x11F000000B830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT4_IN_BP" , 0x11F000000B840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT5_IN_BP" , 0x11F000000B850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT6_IN_BP" , 0x11F000000B860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT7_IN_BP" , 0x11F000000B870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT8_IN_BP" , 0x11F000000B880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT9_IN_BP" , 0x11F000000B890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT10_IN_BP" , 0x11F000000B8A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT11_IN_BP" , 0x11F000000B8B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT12_IN_BP" , 0x11F000000B8C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT13_IN_BP" , 0x11F000000B8D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT14_IN_BP" , 0x11F000000B8E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT15_IN_BP" , 0x11F000000B8F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT16_IN_BP" , 0x11F000000B900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT17_IN_BP" , 0x11F000000B910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT18_IN_BP" , 0x11F000000B920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT19_IN_BP" , 0x11F000000B930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT20_IN_BP" , 0x11F000000B940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT21_IN_BP" , 0x11F000000B950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT22_IN_BP" , 0x11F000000B960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT23_IN_BP" , 0x11F000000B970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT24_IN_BP" , 0x11F000000B980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT25_IN_BP" , 0x11F000000B990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT26_IN_BP" , 0x11F000000B9A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT27_IN_BP" , 0x11F000000B9B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT28_IN_BP" , 0x11F000000B9C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT29_IN_BP" , 0x11F000000B9D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT30_IN_BP" , 0x11F000000B9E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT31_IN_BP" , 0x11F000000B9F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 495},
|
|
{"NPEI_PKT0_INSTR_BADDR" , 0x11F000000A800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT1_INSTR_BADDR" , 0x11F000000A810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT2_INSTR_BADDR" , 0x11F000000A820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT3_INSTR_BADDR" , 0x11F000000A830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT4_INSTR_BADDR" , 0x11F000000A840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT5_INSTR_BADDR" , 0x11F000000A850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT6_INSTR_BADDR" , 0x11F000000A860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT7_INSTR_BADDR" , 0x11F000000A870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT8_INSTR_BADDR" , 0x11F000000A880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT9_INSTR_BADDR" , 0x11F000000A890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT10_INSTR_BADDR" , 0x11F000000A8A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT11_INSTR_BADDR" , 0x11F000000A8B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT12_INSTR_BADDR" , 0x11F000000A8C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT13_INSTR_BADDR" , 0x11F000000A8D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT14_INSTR_BADDR" , 0x11F000000A8E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT15_INSTR_BADDR" , 0x11F000000A8F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT16_INSTR_BADDR" , 0x11F000000A900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT17_INSTR_BADDR" , 0x11F000000A910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT18_INSTR_BADDR" , 0x11F000000A920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT19_INSTR_BADDR" , 0x11F000000A930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT20_INSTR_BADDR" , 0x11F000000A940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT21_INSTR_BADDR" , 0x11F000000A950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT22_INSTR_BADDR" , 0x11F000000A960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT23_INSTR_BADDR" , 0x11F000000A970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT24_INSTR_BADDR" , 0x11F000000A980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT25_INSTR_BADDR" , 0x11F000000A990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT26_INSTR_BADDR" , 0x11F000000A9A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT27_INSTR_BADDR" , 0x11F000000A9B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT28_INSTR_BADDR" , 0x11F000000A9C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT29_INSTR_BADDR" , 0x11F000000A9D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT30_INSTR_BADDR" , 0x11F000000A9E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT31_INSTR_BADDR" , 0x11F000000A9F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 496},
|
|
{"NPEI_PKT0_INSTR_BAOFF_DBELL" , 0x11F000000AC00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT1_INSTR_BAOFF_DBELL" , 0x11F000000AC10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT2_INSTR_BAOFF_DBELL" , 0x11F000000AC20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT3_INSTR_BAOFF_DBELL" , 0x11F000000AC30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT4_INSTR_BAOFF_DBELL" , 0x11F000000AC40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT5_INSTR_BAOFF_DBELL" , 0x11F000000AC50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT6_INSTR_BAOFF_DBELL" , 0x11F000000AC60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT7_INSTR_BAOFF_DBELL" , 0x11F000000AC70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT8_INSTR_BAOFF_DBELL" , 0x11F000000AC80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT9_INSTR_BAOFF_DBELL" , 0x11F000000AC90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT10_INSTR_BAOFF_DBELL", 0x11F000000ACA0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT11_INSTR_BAOFF_DBELL", 0x11F000000ACB0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT12_INSTR_BAOFF_DBELL", 0x11F000000ACC0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT13_INSTR_BAOFF_DBELL", 0x11F000000ACD0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT14_INSTR_BAOFF_DBELL", 0x11F000000ACE0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT15_INSTR_BAOFF_DBELL", 0x11F000000ACF0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT16_INSTR_BAOFF_DBELL", 0x11F000000AD00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT17_INSTR_BAOFF_DBELL", 0x11F000000AD10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT18_INSTR_BAOFF_DBELL", 0x11F000000AD20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT19_INSTR_BAOFF_DBELL", 0x11F000000AD30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT20_INSTR_BAOFF_DBELL", 0x11F000000AD40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT21_INSTR_BAOFF_DBELL", 0x11F000000AD50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT22_INSTR_BAOFF_DBELL", 0x11F000000AD60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT23_INSTR_BAOFF_DBELL", 0x11F000000AD70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT24_INSTR_BAOFF_DBELL", 0x11F000000AD80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT25_INSTR_BAOFF_DBELL", 0x11F000000AD90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT26_INSTR_BAOFF_DBELL", 0x11F000000ADA0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT27_INSTR_BAOFF_DBELL", 0x11F000000ADB0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT28_INSTR_BAOFF_DBELL", 0x11F000000ADC0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT29_INSTR_BAOFF_DBELL", 0x11F000000ADD0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT30_INSTR_BAOFF_DBELL", 0x11F000000ADE0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT31_INSTR_BAOFF_DBELL", 0x11F000000ADF0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 497},
|
|
{"NPEI_PKT0_INSTR_FIFO_RSIZE" , 0x11F000000B000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT1_INSTR_FIFO_RSIZE" , 0x11F000000B010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT2_INSTR_FIFO_RSIZE" , 0x11F000000B020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT3_INSTR_FIFO_RSIZE" , 0x11F000000B030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT4_INSTR_FIFO_RSIZE" , 0x11F000000B040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT5_INSTR_FIFO_RSIZE" , 0x11F000000B050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT6_INSTR_FIFO_RSIZE" , 0x11F000000B060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT7_INSTR_FIFO_RSIZE" , 0x11F000000B070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT8_INSTR_FIFO_RSIZE" , 0x11F000000B080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT9_INSTR_FIFO_RSIZE" , 0x11F000000B090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT10_INSTR_FIFO_RSIZE" , 0x11F000000B0A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT11_INSTR_FIFO_RSIZE" , 0x11F000000B0B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT12_INSTR_FIFO_RSIZE" , 0x11F000000B0C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT13_INSTR_FIFO_RSIZE" , 0x11F000000B0D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT14_INSTR_FIFO_RSIZE" , 0x11F000000B0E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT15_INSTR_FIFO_RSIZE" , 0x11F000000B0F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT16_INSTR_FIFO_RSIZE" , 0x11F000000B100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT17_INSTR_FIFO_RSIZE" , 0x11F000000B110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT18_INSTR_FIFO_RSIZE" , 0x11F000000B120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT19_INSTR_FIFO_RSIZE" , 0x11F000000B130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT20_INSTR_FIFO_RSIZE" , 0x11F000000B140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT21_INSTR_FIFO_RSIZE" , 0x11F000000B150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT22_INSTR_FIFO_RSIZE" , 0x11F000000B160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT23_INSTR_FIFO_RSIZE" , 0x11F000000B170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT24_INSTR_FIFO_RSIZE" , 0x11F000000B180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT25_INSTR_FIFO_RSIZE" , 0x11F000000B190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT26_INSTR_FIFO_RSIZE" , 0x11F000000B1A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT27_INSTR_FIFO_RSIZE" , 0x11F000000B1B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT28_INSTR_FIFO_RSIZE" , 0x11F000000B1C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT29_INSTR_FIFO_RSIZE" , 0x11F000000B1D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT30_INSTR_FIFO_RSIZE" , 0x11F000000B1E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT31_INSTR_FIFO_RSIZE" , 0x11F000000B1F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 498},
|
|
{"NPEI_PKT0_INSTR_HEADER" , 0x11F000000B400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT1_INSTR_HEADER" , 0x11F000000B410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT2_INSTR_HEADER" , 0x11F000000B420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT3_INSTR_HEADER" , 0x11F000000B430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT4_INSTR_HEADER" , 0x11F000000B440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT5_INSTR_HEADER" , 0x11F000000B450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT6_INSTR_HEADER" , 0x11F000000B460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT7_INSTR_HEADER" , 0x11F000000B470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT8_INSTR_HEADER" , 0x11F000000B480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT9_INSTR_HEADER" , 0x11F000000B490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT10_INSTR_HEADER" , 0x11F000000B4A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT11_INSTR_HEADER" , 0x11F000000B4B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT12_INSTR_HEADER" , 0x11F000000B4C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT13_INSTR_HEADER" , 0x11F000000B4D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT14_INSTR_HEADER" , 0x11F000000B4E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT15_INSTR_HEADER" , 0x11F000000B4F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT16_INSTR_HEADER" , 0x11F000000B500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT17_INSTR_HEADER" , 0x11F000000B510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT18_INSTR_HEADER" , 0x11F000000B520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT19_INSTR_HEADER" , 0x11F000000B530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT20_INSTR_HEADER" , 0x11F000000B540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT21_INSTR_HEADER" , 0x11F000000B550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT22_INSTR_HEADER" , 0x11F000000B560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT23_INSTR_HEADER" , 0x11F000000B570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT24_INSTR_HEADER" , 0x11F000000B580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT25_INSTR_HEADER" , 0x11F000000B590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT26_INSTR_HEADER" , 0x11F000000B5A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT27_INSTR_HEADER" , 0x11F000000B5B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT28_INSTR_HEADER" , 0x11F000000B5C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT29_INSTR_HEADER" , 0x11F000000B5D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT30_INSTR_HEADER" , 0x11F000000B5E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT31_INSTR_HEADER" , 0x11F000000B5F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 499},
|
|
{"NPEI_PKT0_SLIST_BADDR" , 0x11F0000009400ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT1_SLIST_BADDR" , 0x11F0000009410ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT2_SLIST_BADDR" , 0x11F0000009420ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT3_SLIST_BADDR" , 0x11F0000009430ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT4_SLIST_BADDR" , 0x11F0000009440ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT5_SLIST_BADDR" , 0x11F0000009450ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT6_SLIST_BADDR" , 0x11F0000009460ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT7_SLIST_BADDR" , 0x11F0000009470ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT8_SLIST_BADDR" , 0x11F0000009480ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT9_SLIST_BADDR" , 0x11F0000009490ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT10_SLIST_BADDR" , 0x11F00000094A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT11_SLIST_BADDR" , 0x11F00000094B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT12_SLIST_BADDR" , 0x11F00000094C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT13_SLIST_BADDR" , 0x11F00000094D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT14_SLIST_BADDR" , 0x11F00000094E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT15_SLIST_BADDR" , 0x11F00000094F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT16_SLIST_BADDR" , 0x11F0000009500ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT17_SLIST_BADDR" , 0x11F0000009510ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT18_SLIST_BADDR" , 0x11F0000009520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT19_SLIST_BADDR" , 0x11F0000009530ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT20_SLIST_BADDR" , 0x11F0000009540ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT21_SLIST_BADDR" , 0x11F0000009550ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT22_SLIST_BADDR" , 0x11F0000009560ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT23_SLIST_BADDR" , 0x11F0000009570ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT24_SLIST_BADDR" , 0x11F0000009580ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT25_SLIST_BADDR" , 0x11F0000009590ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT26_SLIST_BADDR" , 0x11F00000095A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT27_SLIST_BADDR" , 0x11F00000095B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT28_SLIST_BADDR" , 0x11F00000095C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT29_SLIST_BADDR" , 0x11F00000095D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT30_SLIST_BADDR" , 0x11F00000095E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT31_SLIST_BADDR" , 0x11F00000095F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 500},
|
|
{"NPEI_PKT0_SLIST_BAOFF_DBELL" , 0x11F0000009800ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT1_SLIST_BAOFF_DBELL" , 0x11F0000009810ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT2_SLIST_BAOFF_DBELL" , 0x11F0000009820ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT3_SLIST_BAOFF_DBELL" , 0x11F0000009830ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT4_SLIST_BAOFF_DBELL" , 0x11F0000009840ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT5_SLIST_BAOFF_DBELL" , 0x11F0000009850ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT6_SLIST_BAOFF_DBELL" , 0x11F0000009860ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT7_SLIST_BAOFF_DBELL" , 0x11F0000009870ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT8_SLIST_BAOFF_DBELL" , 0x11F0000009880ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT9_SLIST_BAOFF_DBELL" , 0x11F0000009890ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT10_SLIST_BAOFF_DBELL", 0x11F00000098A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT11_SLIST_BAOFF_DBELL", 0x11F00000098B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT12_SLIST_BAOFF_DBELL", 0x11F00000098C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT13_SLIST_BAOFF_DBELL", 0x11F00000098D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT14_SLIST_BAOFF_DBELL", 0x11F00000098E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT15_SLIST_BAOFF_DBELL", 0x11F00000098F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT16_SLIST_BAOFF_DBELL", 0x11F0000009900ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT17_SLIST_BAOFF_DBELL", 0x11F0000009910ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT18_SLIST_BAOFF_DBELL", 0x11F0000009920ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT19_SLIST_BAOFF_DBELL", 0x11F0000009930ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT20_SLIST_BAOFF_DBELL", 0x11F0000009940ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT21_SLIST_BAOFF_DBELL", 0x11F0000009950ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT22_SLIST_BAOFF_DBELL", 0x11F0000009960ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT23_SLIST_BAOFF_DBELL", 0x11F0000009970ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT24_SLIST_BAOFF_DBELL", 0x11F0000009980ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT25_SLIST_BAOFF_DBELL", 0x11F0000009990ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT26_SLIST_BAOFF_DBELL", 0x11F00000099A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT27_SLIST_BAOFF_DBELL", 0x11F00000099B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT28_SLIST_BAOFF_DBELL", 0x11F00000099C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT29_SLIST_BAOFF_DBELL", 0x11F00000099D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT30_SLIST_BAOFF_DBELL", 0x11F00000099E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT31_SLIST_BAOFF_DBELL", 0x11F00000099F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 501},
|
|
{"NPEI_PKT0_SLIST_FIFO_RSIZE" , 0x11F0000009C00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT1_SLIST_FIFO_RSIZE" , 0x11F0000009C10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT2_SLIST_FIFO_RSIZE" , 0x11F0000009C20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT3_SLIST_FIFO_RSIZE" , 0x11F0000009C30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT4_SLIST_FIFO_RSIZE" , 0x11F0000009C40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT5_SLIST_FIFO_RSIZE" , 0x11F0000009C50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT6_SLIST_FIFO_RSIZE" , 0x11F0000009C60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT7_SLIST_FIFO_RSIZE" , 0x11F0000009C70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT8_SLIST_FIFO_RSIZE" , 0x11F0000009C80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT9_SLIST_FIFO_RSIZE" , 0x11F0000009C90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT10_SLIST_FIFO_RSIZE" , 0x11F0000009CA0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT11_SLIST_FIFO_RSIZE" , 0x11F0000009CB0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT12_SLIST_FIFO_RSIZE" , 0x11F0000009CC0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT13_SLIST_FIFO_RSIZE" , 0x11F0000009CD0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT14_SLIST_FIFO_RSIZE" , 0x11F0000009CE0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT15_SLIST_FIFO_RSIZE" , 0x11F0000009CF0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT16_SLIST_FIFO_RSIZE" , 0x11F0000009D00ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT17_SLIST_FIFO_RSIZE" , 0x11F0000009D10ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT18_SLIST_FIFO_RSIZE" , 0x11F0000009D20ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT19_SLIST_FIFO_RSIZE" , 0x11F0000009D30ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT20_SLIST_FIFO_RSIZE" , 0x11F0000009D40ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT21_SLIST_FIFO_RSIZE" , 0x11F0000009D50ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT22_SLIST_FIFO_RSIZE" , 0x11F0000009D60ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT23_SLIST_FIFO_RSIZE" , 0x11F0000009D70ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT24_SLIST_FIFO_RSIZE" , 0x11F0000009D80ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT25_SLIST_FIFO_RSIZE" , 0x11F0000009D90ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT26_SLIST_FIFO_RSIZE" , 0x11F0000009DA0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT27_SLIST_FIFO_RSIZE" , 0x11F0000009DB0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT28_SLIST_FIFO_RSIZE" , 0x11F0000009DC0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT29_SLIST_FIFO_RSIZE" , 0x11F0000009DD0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT30_SLIST_FIFO_RSIZE" , 0x11F0000009DE0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT31_SLIST_FIFO_RSIZE" , 0x11F0000009DF0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 502},
|
|
{"NPEI_PKT_CNT_INT" , 0x11F0000009110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 503},
|
|
{"NPEI_PKT_CNT_INT_ENB" , 0x11F0000009130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 504},
|
|
{"NPEI_PKT_DATA_OUT_ES" , 0x11F00000090B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 505},
|
|
{"NPEI_PKT_DATA_OUT_NS" , 0x11F00000090A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 506},
|
|
{"NPEI_PKT_DATA_OUT_ROR" , 0x11F0000009090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 507},
|
|
{"NPEI_PKT_DPADDR" , 0x11F0000009080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 508},
|
|
{"NPEI_PKT_IN_BP" , 0x11F00000086B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 509},
|
|
{"NPEI_PKT_IN_DONE0_CNTS" , 0x11F000000A000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE1_CNTS" , 0x11F000000A010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE2_CNTS" , 0x11F000000A020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE3_CNTS" , 0x11F000000A030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE4_CNTS" , 0x11F000000A040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE5_CNTS" , 0x11F000000A050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE6_CNTS" , 0x11F000000A060ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE7_CNTS" , 0x11F000000A070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE8_CNTS" , 0x11F000000A080ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE9_CNTS" , 0x11F000000A090ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE10_CNTS" , 0x11F000000A0A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE11_CNTS" , 0x11F000000A0B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE12_CNTS" , 0x11F000000A0C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE13_CNTS" , 0x11F000000A0D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE14_CNTS" , 0x11F000000A0E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE15_CNTS" , 0x11F000000A0F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE16_CNTS" , 0x11F000000A100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE17_CNTS" , 0x11F000000A110ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE18_CNTS" , 0x11F000000A120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE19_CNTS" , 0x11F000000A130ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE20_CNTS" , 0x11F000000A140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE21_CNTS" , 0x11F000000A150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE22_CNTS" , 0x11F000000A160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE23_CNTS" , 0x11F000000A170ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE24_CNTS" , 0x11F000000A180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE25_CNTS" , 0x11F000000A190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE26_CNTS" , 0x11F000000A1A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE27_CNTS" , 0x11F000000A1B0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE28_CNTS" , 0x11F000000A1C0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE29_CNTS" , 0x11F000000A1D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE30_CNTS" , 0x11F000000A1E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_DONE31_CNTS" , 0x11F000000A1F0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 510},
|
|
{"NPEI_PKT_IN_INSTR_COUNTS" , 0x11F00000086A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 511},
|
|
{"NPEI_PKT_IN_PCIE_PORT" , 0x11F00000091A0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 512},
|
|
{"NPEI_PKT_INPUT_CONTROL" , 0x11F0000009150ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 513},
|
|
{"NPEI_PKT_INSTR_ENB" , 0x11F0000009000ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 514},
|
|
{"NPEI_PKT_INSTR_RD_SIZE" , 0x11F0000009190ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 515},
|
|
{"NPEI_PKT_INSTR_SIZE" , 0x11F0000009020ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 516},
|
|
{"NPEI_PKT_INT_LEVELS" , 0x11F0000009100ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 517},
|
|
{"NPEI_PKT_IPTR" , 0x11F0000009070ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 518},
|
|
{"NPEI_PKT_OUT_BMODE" , 0x11F00000090D0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 519},
|
|
{"NPEI_PKT_OUT_ENB" , 0x11F0000009010ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 520},
|
|
{"NPEI_PKT_OUTPUT_WMARK" , 0x11F0000009160ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 521},
|
|
{"NPEI_PKT_PCIE_PORT" , 0x11F00000090E0ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 522},
|
|
{"NPEI_PKT_PORT_IN_RST" , 0x11F0000008690ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 523},
|
|
{"NPEI_PKT_SLIST_ES" , 0x11F0000009050ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 524},
|
|
{"NPEI_PKT_SLIST_ID_SIZE" , 0x11F0000009180ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 525},
|
|
{"NPEI_PKT_SLIST_NS" , 0x11F0000009040ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 526},
|
|
{"NPEI_PKT_SLIST_ROR" , 0x11F0000009030ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 527},
|
|
{"NPEI_PKT_TIME_INT" , 0x11F0000009120ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 528},
|
|
{"NPEI_PKT_TIME_INT_ENB" , 0x11F0000009140ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 529},
|
|
{"NPEI_RSL_INT_BLOCKS" , 0x11F0000008520ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 530},
|
|
{"NPEI_SCRATCH_1" , 0x11F0000008270ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 531},
|
|
{"NPEI_STATE1" , 0x11F0000008620ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 532},
|
|
{"NPEI_STATE2" , 0x11F0000008630ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 533},
|
|
{"NPEI_STATE3" , 0x11F0000008640ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 534},
|
|
{"NPEI_WIN_RD_ADDR" , 0x210ull, CVMX_CSR_DB_TYPE_PEXP, 64, 535},
|
|
{"NPEI_WIN_RD_DATA" , 0x240ull, CVMX_CSR_DB_TYPE_PEXP, 64, 536},
|
|
{"NPEI_WIN_WR_ADDR" , 0x200ull, CVMX_CSR_DB_TYPE_PEXP, 64, 537},
|
|
{"NPEI_WIN_WR_DATA" , 0x220ull, CVMX_CSR_DB_TYPE_PEXP, 64, 538},
|
|
{"NPEI_WIN_WR_MASK" , 0x230ull, CVMX_CSR_DB_TYPE_PEXP, 64, 539},
|
|
{"NPEI_WINDOW_CTL" , 0x11F0000008380ull, CVMX_CSR_DB_TYPE_PEXP_NCB, 64, 540},
|
|
{"PCIEEP_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 541},
|
|
{"PCIEEP_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 542},
|
|
{"PCIEEP_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 543},
|
|
{"PCIEEP_CFG003" , 0xCull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 544},
|
|
{"PCIEEP_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 545},
|
|
{"PCIEEP_CFG004_MASK" , 0x80000010ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 546},
|
|
{"PCIEEP_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 547},
|
|
{"PCIEEP_CFG005_MASK" , 0x80000014ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 548},
|
|
{"PCIEEP_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 549},
|
|
{"PCIEEP_CFG006_MASK" , 0x80000018ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 550},
|
|
{"PCIEEP_CFG007" , 0x1Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 551},
|
|
{"PCIEEP_CFG007_MASK" , 0x8000001Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 552},
|
|
{"PCIEEP_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 553},
|
|
{"PCIEEP_CFG008_MASK" , 0x80000020ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 554},
|
|
{"PCIEEP_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 555},
|
|
{"PCIEEP_CFG009_MASK" , 0x80000024ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 556},
|
|
{"PCIEEP_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 557},
|
|
{"PCIEEP_CFG011" , 0x2Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 558},
|
|
{"PCIEEP_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 559},
|
|
{"PCIEEP_CFG012_MASK" , 0x80000030ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 560},
|
|
{"PCIEEP_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 561},
|
|
{"PCIEEP_CFG015" , 0x3Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 562},
|
|
{"PCIEEP_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 563},
|
|
{"PCIEEP_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 564},
|
|
{"PCIEEP_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 565},
|
|
{"PCIEEP_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 566},
|
|
{"PCIEEP_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 567},
|
|
{"PCIEEP_CFG023" , 0x5Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 568},
|
|
{"PCIEEP_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 569},
|
|
{"PCIEEP_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 570},
|
|
{"PCIEEP_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 571},
|
|
{"PCIEEP_CFG031" , 0x7Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 572},
|
|
{"PCIEEP_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 573},
|
|
{"PCIEEP_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 574},
|
|
{"PCIEEP_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 575},
|
|
{"PCIEEP_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 576},
|
|
{"PCIEEP_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 577},
|
|
{"PCIEEP_CFG039" , 0x9Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 578},
|
|
{"PCIEEP_CFG040" , 0xA0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 579},
|
|
{"PCIEEP_CFG041" , 0xA4ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 580},
|
|
{"PCIEEP_CFG042" , 0xA8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 581},
|
|
{"PCIEEP_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 582},
|
|
{"PCIEEP_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 583},
|
|
{"PCIEEP_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 584},
|
|
{"PCIEEP_CFG067" , 0x10Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 585},
|
|
{"PCIEEP_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 586},
|
|
{"PCIEEP_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 587},
|
|
{"PCIEEP_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 588},
|
|
{"PCIEEP_CFG071" , 0x11Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 589},
|
|
{"PCIEEP_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 590},
|
|
{"PCIEEP_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 591},
|
|
{"PCIEEP_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 592},
|
|
{"PCIEEP_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 593},
|
|
{"PCIEEP_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 594},
|
|
{"PCIEEP_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 595},
|
|
{"PCIEEP_CFG451" , 0x70Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 596},
|
|
{"PCIEEP_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 597},
|
|
{"PCIEEP_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 598},
|
|
{"PCIEEP_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 599},
|
|
{"PCIEEP_CFG455" , 0x71Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 600},
|
|
{"PCIEEP_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 601},
|
|
{"PCIEEP_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 602},
|
|
{"PCIEEP_CFG459" , 0x72Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 603},
|
|
{"PCIEEP_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 604},
|
|
{"PCIEEP_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 605},
|
|
{"PCIEEP_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 606},
|
|
{"PCIEEP_CFG463" , 0x73Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 607},
|
|
{"PCIEEP_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 608},
|
|
{"PCIEEP_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 609},
|
|
{"PCIEEP_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 610},
|
|
{"PCIEEP_CFG467" , 0x74Cull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 611},
|
|
{"PCIEEP_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 612},
|
|
{"PCIEEP_CFG490" , 0x7A8ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 613},
|
|
{"PCIEEP_CFG491" , 0x7ACull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 614},
|
|
{"PCIEEP_CFG492" , 0x7B0ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 615},
|
|
{"PCIEEP_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 616},
|
|
{"PCIEEP_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGEP, 32, 617},
|
|
{"PCIERC0_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 618},
|
|
{"PCIERC1_CFG000" , 0x0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 618},
|
|
{"PCIERC0_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 619},
|
|
{"PCIERC1_CFG001" , 0x4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 619},
|
|
{"PCIERC0_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 620},
|
|
{"PCIERC1_CFG002" , 0x8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 620},
|
|
{"PCIERC0_CFG003" , 0xCull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 621},
|
|
{"PCIERC1_CFG003" , 0xCull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 621},
|
|
{"PCIERC0_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 622},
|
|
{"PCIERC1_CFG004" , 0x10ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 622},
|
|
{"PCIERC0_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 623},
|
|
{"PCIERC1_CFG005" , 0x14ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 623},
|
|
{"PCIERC0_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 624},
|
|
{"PCIERC1_CFG006" , 0x18ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 624},
|
|
{"PCIERC0_CFG007" , 0x1Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 625},
|
|
{"PCIERC1_CFG007" , 0x1Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 625},
|
|
{"PCIERC0_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 626},
|
|
{"PCIERC1_CFG008" , 0x20ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 626},
|
|
{"PCIERC0_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 627},
|
|
{"PCIERC1_CFG009" , 0x24ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 627},
|
|
{"PCIERC0_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 628},
|
|
{"PCIERC1_CFG010" , 0x28ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 628},
|
|
{"PCIERC0_CFG011" , 0x2Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 629},
|
|
{"PCIERC1_CFG011" , 0x2Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 629},
|
|
{"PCIERC0_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 630},
|
|
{"PCIERC1_CFG012" , 0x30ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 630},
|
|
{"PCIERC0_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 631},
|
|
{"PCIERC1_CFG013" , 0x34ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 631},
|
|
{"PCIERC0_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 632},
|
|
{"PCIERC1_CFG014" , 0x38ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 632},
|
|
{"PCIERC0_CFG015" , 0x3Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 633},
|
|
{"PCIERC1_CFG015" , 0x3Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 633},
|
|
{"PCIERC0_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 634},
|
|
{"PCIERC1_CFG016" , 0x40ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 634},
|
|
{"PCIERC0_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 635},
|
|
{"PCIERC1_CFG017" , 0x44ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 635},
|
|
{"PCIERC0_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 636},
|
|
{"PCIERC1_CFG020" , 0x50ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 636},
|
|
{"PCIERC0_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 637},
|
|
{"PCIERC1_CFG021" , 0x54ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 637},
|
|
{"PCIERC0_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 638},
|
|
{"PCIERC1_CFG022" , 0x58ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 638},
|
|
{"PCIERC0_CFG023" , 0x5Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 639},
|
|
{"PCIERC1_CFG023" , 0x5Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 639},
|
|
{"PCIERC0_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 640},
|
|
{"PCIERC1_CFG028" , 0x70ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 640},
|
|
{"PCIERC0_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 641},
|
|
{"PCIERC1_CFG029" , 0x74ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 641},
|
|
{"PCIERC0_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 642},
|
|
{"PCIERC1_CFG030" , 0x78ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 642},
|
|
{"PCIERC0_CFG031" , 0x7Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 643},
|
|
{"PCIERC1_CFG031" , 0x7Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 643},
|
|
{"PCIERC0_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 644},
|
|
{"PCIERC1_CFG032" , 0x80ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 644},
|
|
{"PCIERC0_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 645},
|
|
{"PCIERC1_CFG033" , 0x84ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 645},
|
|
{"PCIERC0_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 646},
|
|
{"PCIERC1_CFG034" , 0x88ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 646},
|
|
{"PCIERC0_CFG035" , 0x8Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 647},
|
|
{"PCIERC1_CFG035" , 0x8Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 647},
|
|
{"PCIERC0_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 648},
|
|
{"PCIERC1_CFG036" , 0x90ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 648},
|
|
{"PCIERC0_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 649},
|
|
{"PCIERC1_CFG037" , 0x94ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 649},
|
|
{"PCIERC0_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 650},
|
|
{"PCIERC1_CFG038" , 0x98ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 650},
|
|
{"PCIERC0_CFG039" , 0x9Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 651},
|
|
{"PCIERC1_CFG039" , 0x9Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 651},
|
|
{"PCIERC0_CFG040" , 0xA0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 652},
|
|
{"PCIERC1_CFG040" , 0xA0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 652},
|
|
{"PCIERC0_CFG041" , 0xA4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 653},
|
|
{"PCIERC1_CFG041" , 0xA4ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 653},
|
|
{"PCIERC0_CFG042" , 0xA8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 654},
|
|
{"PCIERC1_CFG042" , 0xA8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 654},
|
|
{"PCIERC0_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 655},
|
|
{"PCIERC1_CFG064" , 0x100ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 655},
|
|
{"PCIERC0_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 656},
|
|
{"PCIERC1_CFG065" , 0x104ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 656},
|
|
{"PCIERC0_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 657},
|
|
{"PCIERC1_CFG066" , 0x108ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 657},
|
|
{"PCIERC0_CFG067" , 0x10Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 658},
|
|
{"PCIERC1_CFG067" , 0x10Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 658},
|
|
{"PCIERC0_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 659},
|
|
{"PCIERC1_CFG068" , 0x110ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 659},
|
|
{"PCIERC0_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 660},
|
|
{"PCIERC1_CFG069" , 0x114ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 660},
|
|
{"PCIERC0_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 661},
|
|
{"PCIERC1_CFG070" , 0x118ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 661},
|
|
{"PCIERC0_CFG071" , 0x11Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 662},
|
|
{"PCIERC1_CFG071" , 0x11Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 662},
|
|
{"PCIERC0_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 663},
|
|
{"PCIERC1_CFG072" , 0x120ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 663},
|
|
{"PCIERC0_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 664},
|
|
{"PCIERC1_CFG073" , 0x124ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 664},
|
|
{"PCIERC0_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 665},
|
|
{"PCIERC1_CFG074" , 0x128ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 665},
|
|
{"PCIERC0_CFG075" , 0x12Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 666},
|
|
{"PCIERC1_CFG075" , 0x12Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 666},
|
|
{"PCIERC0_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 667},
|
|
{"PCIERC1_CFG076" , 0x130ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 667},
|
|
{"PCIERC0_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 668},
|
|
{"PCIERC1_CFG077" , 0x134ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 668},
|
|
{"PCIERC0_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 669},
|
|
{"PCIERC1_CFG448" , 0x700ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 669},
|
|
{"PCIERC0_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 670},
|
|
{"PCIERC1_CFG449" , 0x704ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 670},
|
|
{"PCIERC0_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 671},
|
|
{"PCIERC1_CFG450" , 0x708ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 671},
|
|
{"PCIERC0_CFG451" , 0x70Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 672},
|
|
{"PCIERC1_CFG451" , 0x70Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 672},
|
|
{"PCIERC0_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 673},
|
|
{"PCIERC1_CFG452" , 0x710ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 673},
|
|
{"PCIERC0_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 674},
|
|
{"PCIERC1_CFG453" , 0x714ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 674},
|
|
{"PCIERC0_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 675},
|
|
{"PCIERC1_CFG454" , 0x718ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 675},
|
|
{"PCIERC0_CFG455" , 0x71Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 676},
|
|
{"PCIERC1_CFG455" , 0x71Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 676},
|
|
{"PCIERC0_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 677},
|
|
{"PCIERC1_CFG456" , 0x720ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 677},
|
|
{"PCIERC0_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 678},
|
|
{"PCIERC1_CFG458" , 0x728ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 678},
|
|
{"PCIERC0_CFG459" , 0x72Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 679},
|
|
{"PCIERC1_CFG459" , 0x72Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 679},
|
|
{"PCIERC0_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 680},
|
|
{"PCIERC1_CFG460" , 0x730ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 680},
|
|
{"PCIERC0_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 681},
|
|
{"PCIERC1_CFG461" , 0x734ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 681},
|
|
{"PCIERC0_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 682},
|
|
{"PCIERC1_CFG462" , 0x738ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 682},
|
|
{"PCIERC0_CFG463" , 0x73Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 683},
|
|
{"PCIERC1_CFG463" , 0x73Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 683},
|
|
{"PCIERC0_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 684},
|
|
{"PCIERC1_CFG464" , 0x740ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 684},
|
|
{"PCIERC0_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 685},
|
|
{"PCIERC1_CFG465" , 0x744ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 685},
|
|
{"PCIERC0_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 686},
|
|
{"PCIERC1_CFG466" , 0x748ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 686},
|
|
{"PCIERC0_CFG467" , 0x74Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 687},
|
|
{"PCIERC1_CFG467" , 0x74Cull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 687},
|
|
{"PCIERC0_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 688},
|
|
{"PCIERC1_CFG468" , 0x750ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 688},
|
|
{"PCIERC0_CFG490" , 0x7A8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 689},
|
|
{"PCIERC1_CFG490" , 0x7A8ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 689},
|
|
{"PCIERC0_CFG491" , 0x7ACull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 690},
|
|
{"PCIERC1_CFG491" , 0x7ACull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 690},
|
|
{"PCIERC0_CFG492" , 0x7B0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 691},
|
|
{"PCIERC1_CFG492" , 0x7B0ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 691},
|
|
{"PCIERC0_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 692},
|
|
{"PCIERC1_CFG516" , 0x810ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 692},
|
|
{"PCIERC0_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 693},
|
|
{"PCIERC1_CFG517" , 0x814ull, CVMX_CSR_DB_TYPE_PCICONFIGRC, 32, 693},
|
|
{"PCS0_AN000_ADV_REG" , 0x11800B0001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PCS0_AN001_ADV_REG" , 0x11800B0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PCS0_AN002_ADV_REG" , 0x11800B0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PCS0_AN003_ADV_REG" , 0x11800B0001C10ull, CVMX_CSR_DB_TYPE_RSL, 64, 694},
|
|
{"PCS0_AN000_EXT_ST_REG" , 0x11800B0001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
|
|
{"PCS0_AN001_EXT_ST_REG" , 0x11800B0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
|
|
{"PCS0_AN002_EXT_ST_REG" , 0x11800B0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
|
|
{"PCS0_AN003_EXT_ST_REG" , 0x11800B0001C28ull, CVMX_CSR_DB_TYPE_RSL, 64, 695},
|
|
{"PCS0_AN000_LP_ABIL_REG" , 0x11800B0001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
|
|
{"PCS0_AN001_LP_ABIL_REG" , 0x11800B0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
|
|
{"PCS0_AN002_LP_ABIL_REG" , 0x11800B0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
|
|
{"PCS0_AN003_LP_ABIL_REG" , 0x11800B0001C18ull, CVMX_CSR_DB_TYPE_RSL, 64, 696},
|
|
{"PCS0_AN000_RESULTS_REG" , 0x11800B0001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
|
|
{"PCS0_AN001_RESULTS_REG" , 0x11800B0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
|
|
{"PCS0_AN002_RESULTS_REG" , 0x11800B0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
|
|
{"PCS0_AN003_RESULTS_REG" , 0x11800B0001C20ull, CVMX_CSR_DB_TYPE_RSL, 64, 697},
|
|
{"PCS0_INT000_EN_REG" , 0x11800B0001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
|
|
{"PCS0_INT001_EN_REG" , 0x11800B0001488ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
|
|
{"PCS0_INT002_EN_REG" , 0x11800B0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
|
|
{"PCS0_INT003_EN_REG" , 0x11800B0001C88ull, CVMX_CSR_DB_TYPE_RSL, 64, 698},
|
|
{"PCS0_INT000_REG" , 0x11800B0001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
|
|
{"PCS0_INT001_REG" , 0x11800B0001480ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
|
|
{"PCS0_INT002_REG" , 0x11800B0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
|
|
{"PCS0_INT003_REG" , 0x11800B0001C80ull, CVMX_CSR_DB_TYPE_RSL, 64, 699},
|
|
{"PCS0_LINK000_TIMER_COUNT_REG", 0x11800B0001040ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
|
|
{"PCS0_LINK001_TIMER_COUNT_REG", 0x11800B0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
|
|
{"PCS0_LINK002_TIMER_COUNT_REG", 0x11800B0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
|
|
{"PCS0_LINK003_TIMER_COUNT_REG", 0x11800B0001C40ull, CVMX_CSR_DB_TYPE_RSL, 64, 700},
|
|
{"PCS0_LOG_ANL000_REG" , 0x11800B0001090ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
|
|
{"PCS0_LOG_ANL001_REG" , 0x11800B0001490ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
|
|
{"PCS0_LOG_ANL002_REG" , 0x11800B0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
|
|
{"PCS0_LOG_ANL003_REG" , 0x11800B0001C90ull, CVMX_CSR_DB_TYPE_RSL, 64, 701},
|
|
{"PCS0_MISC000_CTL_REG" , 0x11800B0001078ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
|
|
{"PCS0_MISC001_CTL_REG" , 0x11800B0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
|
|
{"PCS0_MISC002_CTL_REG" , 0x11800B0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
|
|
{"PCS0_MISC003_CTL_REG" , 0x11800B0001C78ull, CVMX_CSR_DB_TYPE_RSL, 64, 702},
|
|
{"PCS0_MR000_CONTROL_REG" , 0x11800B0001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PCS0_MR001_CONTROL_REG" , 0x11800B0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PCS0_MR002_CONTROL_REG" , 0x11800B0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PCS0_MR003_CONTROL_REG" , 0x11800B0001C00ull, CVMX_CSR_DB_TYPE_RSL, 64, 703},
|
|
{"PCS0_MR000_STATUS_REG" , 0x11800B0001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
|
|
{"PCS0_MR001_STATUS_REG" , 0x11800B0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
|
|
{"PCS0_MR002_STATUS_REG" , 0x11800B0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
|
|
{"PCS0_MR003_STATUS_REG" , 0x11800B0001C08ull, CVMX_CSR_DB_TYPE_RSL, 64, 704},
|
|
{"PCS0_RX000_STATES_REG" , 0x11800B0001058ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
|
|
{"PCS0_RX001_STATES_REG" , 0x11800B0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
|
|
{"PCS0_RX002_STATES_REG" , 0x11800B0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
|
|
{"PCS0_RX003_STATES_REG" , 0x11800B0001C58ull, CVMX_CSR_DB_TYPE_RSL, 64, 705},
|
|
{"PCS0_RX000_SYNC_REG" , 0x11800B0001050ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
|
|
{"PCS0_RX001_SYNC_REG" , 0x11800B0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
|
|
{"PCS0_RX002_SYNC_REG" , 0x11800B0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
|
|
{"PCS0_RX003_SYNC_REG" , 0x11800B0001C50ull, CVMX_CSR_DB_TYPE_RSL, 64, 706},
|
|
{"PCS0_SGM000_AN_ADV_REG" , 0x11800B0001068ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
|
|
{"PCS0_SGM001_AN_ADV_REG" , 0x11800B0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
|
|
{"PCS0_SGM002_AN_ADV_REG" , 0x11800B0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
|
|
{"PCS0_SGM003_AN_ADV_REG" , 0x11800B0001C68ull, CVMX_CSR_DB_TYPE_RSL, 64, 707},
|
|
{"PCS0_SGM000_LP_ADV_REG" , 0x11800B0001070ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
|
|
{"PCS0_SGM001_LP_ADV_REG" , 0x11800B0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
|
|
{"PCS0_SGM002_LP_ADV_REG" , 0x11800B0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
|
|
{"PCS0_SGM003_LP_ADV_REG" , 0x11800B0001C70ull, CVMX_CSR_DB_TYPE_RSL, 64, 708},
|
|
{"PCS0_TX000_STATES_REG" , 0x11800B0001060ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
|
|
{"PCS0_TX001_STATES_REG" , 0x11800B0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
|
|
{"PCS0_TX002_STATES_REG" , 0x11800B0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
|
|
{"PCS0_TX003_STATES_REG" , 0x11800B0001C60ull, CVMX_CSR_DB_TYPE_RSL, 64, 709},
|
|
{"PCS0_TX_RX000_POLARITY_REG" , 0x11800B0001048ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
|
|
{"PCS0_TX_RX001_POLARITY_REG" , 0x11800B0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
|
|
{"PCS0_TX_RX002_POLARITY_REG" , 0x11800B0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
|
|
{"PCS0_TX_RX003_POLARITY_REG" , 0x11800B0001C48ull, CVMX_CSR_DB_TYPE_RSL, 64, 710},
|
|
{"PCSX0_10GBX_STATUS_REG" , 0x11800B0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 711},
|
|
{"PCSX1_10GBX_STATUS_REG" , 0x11800B8000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 711},
|
|
{"PCSX0_BIST_STATUS_REG" , 0x11800B0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 712},
|
|
{"PCSX1_BIST_STATUS_REG" , 0x11800B8000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 712},
|
|
{"PCSX0_BIT_LOCK_STATUS_REG" , 0x11800B0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 713},
|
|
{"PCSX1_BIT_LOCK_STATUS_REG" , 0x11800B8000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 713},
|
|
{"PCSX0_CONTROL1_REG" , 0x11800B0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 714},
|
|
{"PCSX1_CONTROL1_REG" , 0x11800B8000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 714},
|
|
{"PCSX0_CONTROL2_REG" , 0x11800B0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 715},
|
|
{"PCSX1_CONTROL2_REG" , 0x11800B8000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 715},
|
|
{"PCSX0_INT_EN_REG" , 0x11800B0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 716},
|
|
{"PCSX1_INT_EN_REG" , 0x11800B8000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 716},
|
|
{"PCSX0_INT_REG" , 0x11800B0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 717},
|
|
{"PCSX1_INT_REG" , 0x11800B8000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 717},
|
|
{"PCSX0_LOG_ANL_REG" , 0x11800B0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 718},
|
|
{"PCSX1_LOG_ANL_REG" , 0x11800B8000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 718},
|
|
{"PCSX0_MISC_CTL_REG" , 0x11800B0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 719},
|
|
{"PCSX1_MISC_CTL_REG" , 0x11800B8000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 719},
|
|
{"PCSX0_RX_SYNC_STATES_REG" , 0x11800B0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 720},
|
|
{"PCSX1_RX_SYNC_STATES_REG" , 0x11800B8000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 720},
|
|
{"PCSX0_SPD_ABIL_REG" , 0x11800B0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 721},
|
|
{"PCSX1_SPD_ABIL_REG" , 0x11800B8000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 721},
|
|
{"PCSX0_STATUS1_REG" , 0x11800B0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 722},
|
|
{"PCSX1_STATUS1_REG" , 0x11800B8000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 722},
|
|
{"PCSX0_STATUS2_REG" , 0x11800B0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 723},
|
|
{"PCSX1_STATUS2_REG" , 0x11800B8000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 723},
|
|
{"PCSX0_TX_RX_POLARITY_REG" , 0x11800B0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
|
|
{"PCSX1_TX_RX_POLARITY_REG" , 0x11800B8000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 724},
|
|
{"PCSX0_TX_RX_STATES_REG" , 0x11800B0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
|
|
{"PCSX1_TX_RX_STATES_REG" , 0x11800B8000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 725},
|
|
{"PESC0_BIST_STATUS" , 0x11800C8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 726},
|
|
{"PESC1_BIST_STATUS" , 0x11800D0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 726},
|
|
{"PESC0_BIST_STATUS2" , 0x11800C8000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 727},
|
|
{"PESC1_BIST_STATUS2" , 0x11800D0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 727},
|
|
{"PESC0_CFG_RD" , 0x11800C8000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 728},
|
|
{"PESC1_CFG_RD" , 0x11800D0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 728},
|
|
{"PESC0_CFG_WR" , 0x11800C8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 729},
|
|
{"PESC1_CFG_WR" , 0x11800D0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 729},
|
|
{"PESC0_CPL_LUT_VALID" , 0x11800C8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
|
|
{"PESC1_CPL_LUT_VALID" , 0x11800D0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 730},
|
|
{"PESC0_CTL_STATUS" , 0x11800C8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 731},
|
|
{"PESC1_CTL_STATUS" , 0x11800D0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 731},
|
|
{"PESC0_CTL_STATUS2" , 0x11800C8000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 732},
|
|
{"PESC1_CTL_STATUS2" , 0x11800D0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 732},
|
|
{"PESC0_DBG_INFO" , 0x11800C8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 733},
|
|
{"PESC1_DBG_INFO" , 0x11800D0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 733},
|
|
{"PESC0_DBG_INFO_EN" , 0x11800C80000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 734},
|
|
{"PESC1_DBG_INFO_EN" , 0x11800D00000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 734},
|
|
{"PESC0_DIAG_STATUS" , 0x11800C8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 735},
|
|
{"PESC1_DIAG_STATUS" , 0x11800D0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 735},
|
|
{"PESC0_P2N_BAR0_START" , 0x11800C8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 736},
|
|
{"PESC1_P2N_BAR0_START" , 0x11800D0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 736},
|
|
{"PESC0_P2N_BAR1_START" , 0x11800C8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 737},
|
|
{"PESC1_P2N_BAR1_START" , 0x11800D0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 737},
|
|
{"PESC0_P2N_BAR2_START" , 0x11800C8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
|
|
{"PESC1_P2N_BAR2_START" , 0x11800D0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 738},
|
|
{"PESC0_P2P_BAR000_END" , 0x11800C8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PESC0_P2P_BAR001_END" , 0x11800C8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PESC0_P2P_BAR002_END" , 0x11800C8000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PESC0_P2P_BAR003_END" , 0x11800C8000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PESC1_P2P_BAR000_END" , 0x11800D0000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PESC1_P2P_BAR001_END" , 0x11800D0000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PESC1_P2P_BAR002_END" , 0x11800D0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PESC1_P2P_BAR003_END" , 0x11800D0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 739},
|
|
{"PESC0_P2P_BAR000_START" , 0x11800C8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PESC0_P2P_BAR001_START" , 0x11800C8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PESC0_P2P_BAR002_START" , 0x11800C8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PESC0_P2P_BAR003_START" , 0x11800C8000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PESC1_P2P_BAR000_START" , 0x11800D0000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PESC1_P2P_BAR001_START" , 0x11800D0000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PESC1_P2P_BAR002_START" , 0x11800D0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PESC1_P2P_BAR003_START" , 0x11800D0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 740},
|
|
{"PESC0_TLP_CREDITS" , 0x11800C8000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PESC1_TLP_CREDITS" , 0x11800D0000038ull, CVMX_CSR_DB_TYPE_RSL, 64, 741},
|
|
{"PIP_BIST_STATUS" , 0x11800A0000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 742},
|
|
{"PIP_DEC_IPSEC0" , 0x11800A0000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
|
|
{"PIP_DEC_IPSEC1" , 0x11800A0000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
|
|
{"PIP_DEC_IPSEC2" , 0x11800A0000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
|
|
{"PIP_DEC_IPSEC3" , 0x11800A0000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 743},
|
|
{"PIP_DSA_SRC_GRP" , 0x11800A0000190ull, CVMX_CSR_DB_TYPE_RSL, 64, 744},
|
|
{"PIP_DSA_VID_GRP" , 0x11800A0000198ull, CVMX_CSR_DB_TYPE_RSL, 64, 745},
|
|
{"PIP_FRM_LEN_CHK0" , 0x11800A0000180ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
|
|
{"PIP_FRM_LEN_CHK1" , 0x11800A0000188ull, CVMX_CSR_DB_TYPE_RSL, 64, 746},
|
|
{"PIP_GBL_CFG" , 0x11800A0000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 747},
|
|
{"PIP_GBL_CTL" , 0x11800A0000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 748},
|
|
{"PIP_HG_PRI_QOS" , 0x11800A00001A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 749},
|
|
{"PIP_INT_EN" , 0x11800A0000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 750},
|
|
{"PIP_INT_REG" , 0x11800A0000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 751},
|
|
{"PIP_IP_OFFSET" , 0x11800A0000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 752},
|
|
{"PIP_PRT_CFG0" , 0x11800A0000200ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_PRT_CFG1" , 0x11800A0000208ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_PRT_CFG2" , 0x11800A0000210ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_PRT_CFG3" , 0x11800A0000218ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_PRT_CFG32" , 0x11800A0000300ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_PRT_CFG33" , 0x11800A0000308ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_PRT_CFG34" , 0x11800A0000310ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_PRT_CFG35" , 0x11800A0000318ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_PRT_CFG36" , 0x11800A0000320ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_PRT_CFG37" , 0x11800A0000328ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_PRT_CFG38" , 0x11800A0000330ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_PRT_CFG39" , 0x11800A0000338ull, CVMX_CSR_DB_TYPE_RSL, 64, 753},
|
|
{"PIP_PRT_TAG0" , 0x11800A0000400ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_PRT_TAG1" , 0x11800A0000408ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_PRT_TAG2" , 0x11800A0000410ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_PRT_TAG3" , 0x11800A0000418ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_PRT_TAG32" , 0x11800A0000500ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_PRT_TAG33" , 0x11800A0000508ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_PRT_TAG34" , 0x11800A0000510ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_PRT_TAG35" , 0x11800A0000518ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_PRT_TAG36" , 0x11800A0000520ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_PRT_TAG37" , 0x11800A0000528ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_PRT_TAG38" , 0x11800A0000530ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_PRT_TAG39" , 0x11800A0000538ull, CVMX_CSR_DB_TYPE_RSL, 64, 754},
|
|
{"PIP_QOS_DIFF0" , 0x11800A0000600ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF1" , 0x11800A0000608ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF2" , 0x11800A0000610ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF3" , 0x11800A0000618ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF4" , 0x11800A0000620ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF5" , 0x11800A0000628ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF6" , 0x11800A0000630ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF7" , 0x11800A0000638ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF8" , 0x11800A0000640ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF9" , 0x11800A0000648ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF10" , 0x11800A0000650ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF11" , 0x11800A0000658ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF12" , 0x11800A0000660ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF13" , 0x11800A0000668ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF14" , 0x11800A0000670ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF15" , 0x11800A0000678ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF16" , 0x11800A0000680ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF17" , 0x11800A0000688ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF18" , 0x11800A0000690ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF19" , 0x11800A0000698ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF20" , 0x11800A00006A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF21" , 0x11800A00006A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF22" , 0x11800A00006B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF23" , 0x11800A00006B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF24" , 0x11800A00006C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF25" , 0x11800A00006C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF26" , 0x11800A00006D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF27" , 0x11800A00006D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF28" , 0x11800A00006E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF29" , 0x11800A00006E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF30" , 0x11800A00006F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF31" , 0x11800A00006F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF32" , 0x11800A0000700ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF33" , 0x11800A0000708ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF34" , 0x11800A0000710ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF35" , 0x11800A0000718ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF36" , 0x11800A0000720ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF37" , 0x11800A0000728ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF38" , 0x11800A0000730ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF39" , 0x11800A0000738ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF40" , 0x11800A0000740ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF41" , 0x11800A0000748ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF42" , 0x11800A0000750ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF43" , 0x11800A0000758ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF44" , 0x11800A0000760ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF45" , 0x11800A0000768ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF46" , 0x11800A0000770ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF47" , 0x11800A0000778ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF48" , 0x11800A0000780ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF49" , 0x11800A0000788ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF50" , 0x11800A0000790ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF51" , 0x11800A0000798ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF52" , 0x11800A00007A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF53" , 0x11800A00007A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF54" , 0x11800A00007B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF55" , 0x11800A00007B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF56" , 0x11800A00007C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF57" , 0x11800A00007C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF58" , 0x11800A00007D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF59" , 0x11800A00007D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF60" , 0x11800A00007E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF61" , 0x11800A00007E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF62" , 0x11800A00007F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_DIFF63" , 0x11800A00007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 755},
|
|
{"PIP_QOS_VLAN0" , 0x11800A00000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
|
|
{"PIP_QOS_VLAN1" , 0x11800A00000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
|
|
{"PIP_QOS_VLAN2" , 0x11800A00000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
|
|
{"PIP_QOS_VLAN3" , 0x11800A00000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
|
|
{"PIP_QOS_VLAN4" , 0x11800A00000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
|
|
{"PIP_QOS_VLAN5" , 0x11800A00000E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
|
|
{"PIP_QOS_VLAN6" , 0x11800A00000F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
|
|
{"PIP_QOS_VLAN7" , 0x11800A00000F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 756},
|
|
{"PIP_QOS_WATCH0" , 0x11800A0000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
|
|
{"PIP_QOS_WATCH1" , 0x11800A0000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
|
|
{"PIP_QOS_WATCH2" , 0x11800A0000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
|
|
{"PIP_QOS_WATCH3" , 0x11800A0000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
|
|
{"PIP_QOS_WATCH4" , 0x11800A0000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
|
|
{"PIP_QOS_WATCH5" , 0x11800A0000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
|
|
{"PIP_QOS_WATCH6" , 0x11800A0000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
|
|
{"PIP_QOS_WATCH7" , 0x11800A0000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 757},
|
|
{"PIP_RAW_WORD" , 0x11800A00000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 758},
|
|
{"PIP_SFT_RST" , 0x11800A0000030ull, CVMX_CSR_DB_TYPE_RSL, 64, 759},
|
|
{"PIP_STAT0_PRT0" , 0x11800A0000800ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_STAT0_PRT1" , 0x11800A0000850ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_STAT0_PRT2" , 0x11800A00008A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_STAT0_PRT3" , 0x11800A00008F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_STAT0_PRT32" , 0x11800A0001200ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_STAT0_PRT33" , 0x11800A0001250ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_STAT0_PRT34" , 0x11800A00012A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_STAT0_PRT35" , 0x11800A00012F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_STAT0_PRT36" , 0x11800A0001340ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_STAT0_PRT37" , 0x11800A0001390ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_STAT0_PRT38" , 0x11800A00013E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_STAT0_PRT39" , 0x11800A0001430ull, CVMX_CSR_DB_TYPE_RSL, 64, 760},
|
|
{"PIP_STAT1_PRT0" , 0x11800A0000808ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
|
|
{"PIP_STAT1_PRT1" , 0x11800A0000858ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
|
|
{"PIP_STAT1_PRT2" , 0x11800A00008A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
|
|
{"PIP_STAT1_PRT3" , 0x11800A00008F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
|
|
{"PIP_STAT1_PRT32" , 0x11800A0001208ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
|
|
{"PIP_STAT1_PRT33" , 0x11800A0001258ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
|
|
{"PIP_STAT1_PRT34" , 0x11800A00012A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
|
|
{"PIP_STAT1_PRT35" , 0x11800A00012F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
|
|
{"PIP_STAT1_PRT36" , 0x11800A0001348ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
|
|
{"PIP_STAT1_PRT37" , 0x11800A0001398ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
|
|
{"PIP_STAT1_PRT38" , 0x11800A00013E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
|
|
{"PIP_STAT1_PRT39" , 0x11800A0001438ull, CVMX_CSR_DB_TYPE_RSL, 64, 761},
|
|
{"PIP_STAT2_PRT0" , 0x11800A0000810ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
|
|
{"PIP_STAT2_PRT1" , 0x11800A0000860ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
|
|
{"PIP_STAT2_PRT2" , 0x11800A00008B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
|
|
{"PIP_STAT2_PRT3" , 0x11800A0000900ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
|
|
{"PIP_STAT2_PRT32" , 0x11800A0001210ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
|
|
{"PIP_STAT2_PRT33" , 0x11800A0001260ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
|
|
{"PIP_STAT2_PRT34" , 0x11800A00012B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
|
|
{"PIP_STAT2_PRT35" , 0x11800A0001300ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
|
|
{"PIP_STAT2_PRT36" , 0x11800A0001350ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
|
|
{"PIP_STAT2_PRT37" , 0x11800A00013A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
|
|
{"PIP_STAT2_PRT38" , 0x11800A00013F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
|
|
{"PIP_STAT2_PRT39" , 0x11800A0001440ull, CVMX_CSR_DB_TYPE_RSL, 64, 762},
|
|
{"PIP_STAT3_PRT0" , 0x11800A0000818ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
|
|
{"PIP_STAT3_PRT1" , 0x11800A0000868ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
|
|
{"PIP_STAT3_PRT2" , 0x11800A00008B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
|
|
{"PIP_STAT3_PRT3" , 0x11800A0000908ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
|
|
{"PIP_STAT3_PRT32" , 0x11800A0001218ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
|
|
{"PIP_STAT3_PRT33" , 0x11800A0001268ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
|
|
{"PIP_STAT3_PRT34" , 0x11800A00012B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
|
|
{"PIP_STAT3_PRT35" , 0x11800A0001308ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
|
|
{"PIP_STAT3_PRT36" , 0x11800A0001358ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
|
|
{"PIP_STAT3_PRT37" , 0x11800A00013A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
|
|
{"PIP_STAT3_PRT38" , 0x11800A00013F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
|
|
{"PIP_STAT3_PRT39" , 0x11800A0001448ull, CVMX_CSR_DB_TYPE_RSL, 64, 763},
|
|
{"PIP_STAT4_PRT0" , 0x11800A0000820ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
|
|
{"PIP_STAT4_PRT1" , 0x11800A0000870ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
|
|
{"PIP_STAT4_PRT2" , 0x11800A00008C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
|
|
{"PIP_STAT4_PRT3" , 0x11800A0000910ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
|
|
{"PIP_STAT4_PRT32" , 0x11800A0001220ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
|
|
{"PIP_STAT4_PRT33" , 0x11800A0001270ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
|
|
{"PIP_STAT4_PRT34" , 0x11800A00012C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
|
|
{"PIP_STAT4_PRT35" , 0x11800A0001310ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
|
|
{"PIP_STAT4_PRT36" , 0x11800A0001360ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
|
|
{"PIP_STAT4_PRT37" , 0x11800A00013B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
|
|
{"PIP_STAT4_PRT38" , 0x11800A0001400ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
|
|
{"PIP_STAT4_PRT39" , 0x11800A0001450ull, CVMX_CSR_DB_TYPE_RSL, 64, 764},
|
|
{"PIP_STAT5_PRT0" , 0x11800A0000828ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
|
|
{"PIP_STAT5_PRT1" , 0x11800A0000878ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
|
|
{"PIP_STAT5_PRT2" , 0x11800A00008C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
|
|
{"PIP_STAT5_PRT3" , 0x11800A0000918ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
|
|
{"PIP_STAT5_PRT32" , 0x11800A0001228ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
|
|
{"PIP_STAT5_PRT33" , 0x11800A0001278ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
|
|
{"PIP_STAT5_PRT34" , 0x11800A00012C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
|
|
{"PIP_STAT5_PRT35" , 0x11800A0001318ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
|
|
{"PIP_STAT5_PRT36" , 0x11800A0001368ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
|
|
{"PIP_STAT5_PRT37" , 0x11800A00013B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
|
|
{"PIP_STAT5_PRT38" , 0x11800A0001408ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
|
|
{"PIP_STAT5_PRT39" , 0x11800A0001458ull, CVMX_CSR_DB_TYPE_RSL, 64, 765},
|
|
{"PIP_STAT6_PRT0" , 0x11800A0000830ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
|
|
{"PIP_STAT6_PRT1" , 0x11800A0000880ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
|
|
{"PIP_STAT6_PRT2" , 0x11800A00008D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
|
|
{"PIP_STAT6_PRT3" , 0x11800A0000920ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
|
|
{"PIP_STAT6_PRT32" , 0x11800A0001230ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
|
|
{"PIP_STAT6_PRT33" , 0x11800A0001280ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
|
|
{"PIP_STAT6_PRT34" , 0x11800A00012D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
|
|
{"PIP_STAT6_PRT35" , 0x11800A0001320ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
|
|
{"PIP_STAT6_PRT36" , 0x11800A0001370ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
|
|
{"PIP_STAT6_PRT37" , 0x11800A00013C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
|
|
{"PIP_STAT6_PRT38" , 0x11800A0001410ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
|
|
{"PIP_STAT6_PRT39" , 0x11800A0001460ull, CVMX_CSR_DB_TYPE_RSL, 64, 766},
|
|
{"PIP_STAT7_PRT0" , 0x11800A0000838ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
|
|
{"PIP_STAT7_PRT1" , 0x11800A0000888ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
|
|
{"PIP_STAT7_PRT2" , 0x11800A00008D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
|
|
{"PIP_STAT7_PRT3" , 0x11800A0000928ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
|
|
{"PIP_STAT7_PRT32" , 0x11800A0001238ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
|
|
{"PIP_STAT7_PRT33" , 0x11800A0001288ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
|
|
{"PIP_STAT7_PRT34" , 0x11800A00012D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
|
|
{"PIP_STAT7_PRT35" , 0x11800A0001328ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
|
|
{"PIP_STAT7_PRT36" , 0x11800A0001378ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
|
|
{"PIP_STAT7_PRT37" , 0x11800A00013C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
|
|
{"PIP_STAT7_PRT38" , 0x11800A0001418ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
|
|
{"PIP_STAT7_PRT39" , 0x11800A0001468ull, CVMX_CSR_DB_TYPE_RSL, 64, 767},
|
|
{"PIP_STAT8_PRT0" , 0x11800A0000840ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
|
|
{"PIP_STAT8_PRT1" , 0x11800A0000890ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
|
|
{"PIP_STAT8_PRT2" , 0x11800A00008E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
|
|
{"PIP_STAT8_PRT3" , 0x11800A0000930ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
|
|
{"PIP_STAT8_PRT32" , 0x11800A0001240ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
|
|
{"PIP_STAT8_PRT33" , 0x11800A0001290ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
|
|
{"PIP_STAT8_PRT34" , 0x11800A00012E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
|
|
{"PIP_STAT8_PRT35" , 0x11800A0001330ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
|
|
{"PIP_STAT8_PRT36" , 0x11800A0001380ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
|
|
{"PIP_STAT8_PRT37" , 0x11800A00013D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
|
|
{"PIP_STAT8_PRT38" , 0x11800A0001420ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
|
|
{"PIP_STAT8_PRT39" , 0x11800A0001470ull, CVMX_CSR_DB_TYPE_RSL, 64, 768},
|
|
{"PIP_STAT9_PRT0" , 0x11800A0000848ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
|
|
{"PIP_STAT9_PRT1" , 0x11800A0000898ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
|
|
{"PIP_STAT9_PRT2" , 0x11800A00008E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
|
|
{"PIP_STAT9_PRT3" , 0x11800A0000938ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
|
|
{"PIP_STAT9_PRT32" , 0x11800A0001248ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
|
|
{"PIP_STAT9_PRT33" , 0x11800A0001298ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
|
|
{"PIP_STAT9_PRT34" , 0x11800A00012E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
|
|
{"PIP_STAT9_PRT35" , 0x11800A0001338ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
|
|
{"PIP_STAT9_PRT36" , 0x11800A0001388ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
|
|
{"PIP_STAT9_PRT37" , 0x11800A00013D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
|
|
{"PIP_STAT9_PRT38" , 0x11800A0001428ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
|
|
{"PIP_STAT9_PRT39" , 0x11800A0001478ull, CVMX_CSR_DB_TYPE_RSL, 64, 769},
|
|
{"PIP_STAT_CTL" , 0x11800A0000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 770},
|
|
{"PIP_STAT_INB_ERRS0" , 0x11800A0001A10ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
|
|
{"PIP_STAT_INB_ERRS1" , 0x11800A0001A30ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
|
|
{"PIP_STAT_INB_ERRS2" , 0x11800A0001A50ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
|
|
{"PIP_STAT_INB_ERRS3" , 0x11800A0001A70ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
|
|
{"PIP_STAT_INB_ERRS32" , 0x11800A0001E10ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
|
|
{"PIP_STAT_INB_ERRS33" , 0x11800A0001E30ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
|
|
{"PIP_STAT_INB_ERRS34" , 0x11800A0001E50ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
|
|
{"PIP_STAT_INB_ERRS35" , 0x11800A0001E70ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
|
|
{"PIP_STAT_INB_ERRS36" , 0x11800A0001E90ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
|
|
{"PIP_STAT_INB_ERRS37" , 0x11800A0001EB0ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
|
|
{"PIP_STAT_INB_ERRS38" , 0x11800A0001ED0ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
|
|
{"PIP_STAT_INB_ERRS39" , 0x11800A0001EF0ull, CVMX_CSR_DB_TYPE_RSL, 64, 771},
|
|
{"PIP_STAT_INB_OCTS0" , 0x11800A0001A08ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
|
|
{"PIP_STAT_INB_OCTS1" , 0x11800A0001A28ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
|
|
{"PIP_STAT_INB_OCTS2" , 0x11800A0001A48ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
|
|
{"PIP_STAT_INB_OCTS3" , 0x11800A0001A68ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
|
|
{"PIP_STAT_INB_OCTS32" , 0x11800A0001E08ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
|
|
{"PIP_STAT_INB_OCTS33" , 0x11800A0001E28ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
|
|
{"PIP_STAT_INB_OCTS34" , 0x11800A0001E48ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
|
|
{"PIP_STAT_INB_OCTS35" , 0x11800A0001E68ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
|
|
{"PIP_STAT_INB_OCTS36" , 0x11800A0001E88ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
|
|
{"PIP_STAT_INB_OCTS37" , 0x11800A0001EA8ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
|
|
{"PIP_STAT_INB_OCTS38" , 0x11800A0001EC8ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
|
|
{"PIP_STAT_INB_OCTS39" , 0x11800A0001EE8ull, CVMX_CSR_DB_TYPE_RSL, 64, 772},
|
|
{"PIP_STAT_INB_PKTS0" , 0x11800A0001A00ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
|
|
{"PIP_STAT_INB_PKTS1" , 0x11800A0001A20ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
|
|
{"PIP_STAT_INB_PKTS2" , 0x11800A0001A40ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
|
|
{"PIP_STAT_INB_PKTS3" , 0x11800A0001A60ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
|
|
{"PIP_STAT_INB_PKTS32" , 0x11800A0001E00ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
|
|
{"PIP_STAT_INB_PKTS33" , 0x11800A0001E20ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
|
|
{"PIP_STAT_INB_PKTS34" , 0x11800A0001E40ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
|
|
{"PIP_STAT_INB_PKTS35" , 0x11800A0001E60ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
|
|
{"PIP_STAT_INB_PKTS36" , 0x11800A0001E80ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
|
|
{"PIP_STAT_INB_PKTS37" , 0x11800A0001EA0ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
|
|
{"PIP_STAT_INB_PKTS38" , 0x11800A0001EC0ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
|
|
{"PIP_STAT_INB_PKTS39" , 0x11800A0001EE0ull, CVMX_CSR_DB_TYPE_RSL, 64, 773},
|
|
{"PIP_TAG_INC0" , 0x11800A0001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC1" , 0x11800A0001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC2" , 0x11800A0001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC3" , 0x11800A0001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC4" , 0x11800A0001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC5" , 0x11800A0001828ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC6" , 0x11800A0001830ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC7" , 0x11800A0001838ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC8" , 0x11800A0001840ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC9" , 0x11800A0001848ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC10" , 0x11800A0001850ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC11" , 0x11800A0001858ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC12" , 0x11800A0001860ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC13" , 0x11800A0001868ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC14" , 0x11800A0001870ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC15" , 0x11800A0001878ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC16" , 0x11800A0001880ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC17" , 0x11800A0001888ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC18" , 0x11800A0001890ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC19" , 0x11800A0001898ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC20" , 0x11800A00018A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC21" , 0x11800A00018A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC22" , 0x11800A00018B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC23" , 0x11800A00018B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC24" , 0x11800A00018C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC25" , 0x11800A00018C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC26" , 0x11800A00018D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC27" , 0x11800A00018D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC28" , 0x11800A00018E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC29" , 0x11800A00018E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC30" , 0x11800A00018F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC31" , 0x11800A00018F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC32" , 0x11800A0001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC33" , 0x11800A0001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC34" , 0x11800A0001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC35" , 0x11800A0001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC36" , 0x11800A0001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC37" , 0x11800A0001928ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC38" , 0x11800A0001930ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC39" , 0x11800A0001938ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC40" , 0x11800A0001940ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC41" , 0x11800A0001948ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC42" , 0x11800A0001950ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC43" , 0x11800A0001958ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC44" , 0x11800A0001960ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC45" , 0x11800A0001968ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC46" , 0x11800A0001970ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC47" , 0x11800A0001978ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC48" , 0x11800A0001980ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC49" , 0x11800A0001988ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC50" , 0x11800A0001990ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC51" , 0x11800A0001998ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC52" , 0x11800A00019A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC53" , 0x11800A00019A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC54" , 0x11800A00019B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC55" , 0x11800A00019B8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC56" , 0x11800A00019C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC57" , 0x11800A00019C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC58" , 0x11800A00019D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC59" , 0x11800A00019D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC60" , 0x11800A00019E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC61" , 0x11800A00019E8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC62" , 0x11800A00019F0ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_INC63" , 0x11800A00019F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 774},
|
|
{"PIP_TAG_MASK" , 0x11800A0000070ull, CVMX_CSR_DB_TYPE_RSL, 64, 775},
|
|
{"PIP_TAG_SECRET" , 0x11800A0000068ull, CVMX_CSR_DB_TYPE_RSL, 64, 776},
|
|
{"PIP_TODO_ENTRY" , 0x11800A0000078ull, CVMX_CSR_DB_TYPE_RSL, 64, 777},
|
|
{"PKO_MEM_COUNT0" , 0x1180050001080ull, CVMX_CSR_DB_TYPE_RSL, 64, 778},
|
|
{"PKO_MEM_COUNT1" , 0x1180050001088ull, CVMX_CSR_DB_TYPE_RSL, 64, 779},
|
|
{"PKO_MEM_DEBUG0" , 0x1180050001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 780},
|
|
{"PKO_MEM_DEBUG1" , 0x1180050001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 781},
|
|
{"PKO_MEM_DEBUG10" , 0x1180050001150ull, CVMX_CSR_DB_TYPE_RSL, 64, 782},
|
|
{"PKO_MEM_DEBUG11" , 0x1180050001158ull, CVMX_CSR_DB_TYPE_RSL, 64, 783},
|
|
{"PKO_MEM_DEBUG12" , 0x1180050001160ull, CVMX_CSR_DB_TYPE_RSL, 64, 784},
|
|
{"PKO_MEM_DEBUG13" , 0x1180050001168ull, CVMX_CSR_DB_TYPE_RSL, 64, 785},
|
|
{"PKO_MEM_DEBUG14" , 0x1180050001170ull, CVMX_CSR_DB_TYPE_RSL, 64, 786},
|
|
{"PKO_MEM_DEBUG2" , 0x1180050001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 787},
|
|
{"PKO_MEM_DEBUG3" , 0x1180050001118ull, CVMX_CSR_DB_TYPE_RSL, 64, 788},
|
|
{"PKO_MEM_DEBUG4" , 0x1180050001120ull, CVMX_CSR_DB_TYPE_RSL, 64, 789},
|
|
{"PKO_MEM_DEBUG5" , 0x1180050001128ull, CVMX_CSR_DB_TYPE_RSL, 64, 790},
|
|
{"PKO_MEM_DEBUG6" , 0x1180050001130ull, CVMX_CSR_DB_TYPE_RSL, 64, 791},
|
|
{"PKO_MEM_DEBUG7" , 0x1180050001138ull, CVMX_CSR_DB_TYPE_RSL, 64, 792},
|
|
{"PKO_MEM_DEBUG8" , 0x1180050001140ull, CVMX_CSR_DB_TYPE_RSL, 64, 793},
|
|
{"PKO_MEM_DEBUG9" , 0x1180050001148ull, CVMX_CSR_DB_TYPE_RSL, 64, 794},
|
|
{"PKO_MEM_PORT_PTRS" , 0x1180050001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 795},
|
|
{"PKO_MEM_PORT_QOS" , 0x1180050001018ull, CVMX_CSR_DB_TYPE_RSL, 64, 796},
|
|
{"PKO_MEM_PORT_RATE0" , 0x1180050001020ull, CVMX_CSR_DB_TYPE_RSL, 64, 797},
|
|
{"PKO_MEM_PORT_RATE1" , 0x1180050001028ull, CVMX_CSR_DB_TYPE_RSL, 64, 798},
|
|
{"PKO_MEM_QUEUE_PTRS" , 0x1180050001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 799},
|
|
{"PKO_MEM_QUEUE_QOS" , 0x1180050001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 800},
|
|
{"PKO_REG_BIST_RESULT" , 0x1180050000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 801},
|
|
{"PKO_REG_CMD_BUF" , 0x1180050000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 802},
|
|
{"PKO_REG_DEBUG0" , 0x1180050000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 803},
|
|
{"PKO_REG_DEBUG1" , 0x11800500000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 804},
|
|
{"PKO_REG_DEBUG2" , 0x11800500000A8ull, CVMX_CSR_DB_TYPE_RSL, 64, 805},
|
|
{"PKO_REG_DEBUG3" , 0x11800500000B0ull, CVMX_CSR_DB_TYPE_RSL, 64, 806},
|
|
{"PKO_REG_ENGINE_INFLIGHT" , 0x1180050000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 807},
|
|
{"PKO_REG_ENGINE_THRESH" , 0x1180050000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 808},
|
|
{"PKO_REG_ERROR" , 0x1180050000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 809},
|
|
{"PKO_REG_FLAGS" , 0x1180050000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 810},
|
|
{"PKO_REG_GMX_PORT_MODE" , 0x1180050000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 811},
|
|
{"PKO_REG_INT_MASK" , 0x1180050000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 812},
|
|
{"PKO_REG_QUEUE_MODE" , 0x1180050000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 813},
|
|
{"PKO_REG_QUEUE_PTRS1" , 0x1180050000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 814},
|
|
{"PKO_REG_READ_IDX" , 0x1180050000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 815},
|
|
{"POW_BIST_STAT" , 0x16700000003F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 816},
|
|
{"POW_DS_PC" , 0x1670000000398ull, CVMX_CSR_DB_TYPE_NCB, 64, 817},
|
|
{"POW_ECC_ERR" , 0x1670000000218ull, CVMX_CSR_DB_TYPE_NCB, 64, 818},
|
|
{"POW_INT_CTL" , 0x1670000000220ull, CVMX_CSR_DB_TYPE_NCB, 64, 819},
|
|
{"POW_IQ_CNT0" , 0x1670000000340ull, CVMX_CSR_DB_TYPE_NCB, 64, 820},
|
|
{"POW_IQ_CNT1" , 0x1670000000348ull, CVMX_CSR_DB_TYPE_NCB, 64, 820},
|
|
{"POW_IQ_CNT2" , 0x1670000000350ull, CVMX_CSR_DB_TYPE_NCB, 64, 820},
|
|
{"POW_IQ_CNT3" , 0x1670000000358ull, CVMX_CSR_DB_TYPE_NCB, 64, 820},
|
|
{"POW_IQ_CNT4" , 0x1670000000360ull, CVMX_CSR_DB_TYPE_NCB, 64, 820},
|
|
{"POW_IQ_CNT5" , 0x1670000000368ull, CVMX_CSR_DB_TYPE_NCB, 64, 820},
|
|
{"POW_IQ_CNT6" , 0x1670000000370ull, CVMX_CSR_DB_TYPE_NCB, 64, 820},
|
|
{"POW_IQ_CNT7" , 0x1670000000378ull, CVMX_CSR_DB_TYPE_NCB, 64, 820},
|
|
{"POW_IQ_COM_CNT" , 0x1670000000388ull, CVMX_CSR_DB_TYPE_NCB, 64, 821},
|
|
{"POW_IQ_INT" , 0x1670000000238ull, CVMX_CSR_DB_TYPE_NCB, 64, 822},
|
|
{"POW_IQ_INT_EN" , 0x1670000000240ull, CVMX_CSR_DB_TYPE_NCB, 64, 823},
|
|
{"POW_IQ_THR0" , 0x16700000003A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
|
|
{"POW_IQ_THR1" , 0x16700000003A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
|
|
{"POW_IQ_THR2" , 0x16700000003B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
|
|
{"POW_IQ_THR3" , 0x16700000003B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
|
|
{"POW_IQ_THR4" , 0x16700000003C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
|
|
{"POW_IQ_THR5" , 0x16700000003C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
|
|
{"POW_IQ_THR6" , 0x16700000003D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
|
|
{"POW_IQ_THR7" , 0x16700000003D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 824},
|
|
{"POW_NOS_CNT" , 0x1670000000228ull, CVMX_CSR_DB_TYPE_NCB, 64, 825},
|
|
{"POW_NW_TIM" , 0x1670000000210ull, CVMX_CSR_DB_TYPE_NCB, 64, 826},
|
|
{"POW_PF_RST_MSK" , 0x1670000000230ull, CVMX_CSR_DB_TYPE_NCB, 64, 827},
|
|
{"POW_PP_GRP_MSK0" , 0x1670000000000ull, CVMX_CSR_DB_TYPE_NCB, 64, 828},
|
|
{"POW_PP_GRP_MSK1" , 0x1670000000008ull, CVMX_CSR_DB_TYPE_NCB, 64, 828},
|
|
{"POW_PP_GRP_MSK2" , 0x1670000000010ull, CVMX_CSR_DB_TYPE_NCB, 64, 828},
|
|
{"POW_PP_GRP_MSK3" , 0x1670000000018ull, CVMX_CSR_DB_TYPE_NCB, 64, 828},
|
|
{"POW_QOS_RND0" , 0x16700000001C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 829},
|
|
{"POW_QOS_RND1" , 0x16700000001C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 829},
|
|
{"POW_QOS_RND2" , 0x16700000001D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 829},
|
|
{"POW_QOS_RND3" , 0x16700000001D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 829},
|
|
{"POW_QOS_RND4" , 0x16700000001E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 829},
|
|
{"POW_QOS_RND5" , 0x16700000001E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 829},
|
|
{"POW_QOS_RND6" , 0x16700000001F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 829},
|
|
{"POW_QOS_RND7" , 0x16700000001F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 829},
|
|
{"POW_QOS_THR0" , 0x1670000000180ull, CVMX_CSR_DB_TYPE_NCB, 64, 830},
|
|
{"POW_QOS_THR1" , 0x1670000000188ull, CVMX_CSR_DB_TYPE_NCB, 64, 830},
|
|
{"POW_QOS_THR2" , 0x1670000000190ull, CVMX_CSR_DB_TYPE_NCB, 64, 830},
|
|
{"POW_QOS_THR3" , 0x1670000000198ull, CVMX_CSR_DB_TYPE_NCB, 64, 830},
|
|
{"POW_QOS_THR4" , 0x16700000001A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 830},
|
|
{"POW_QOS_THR5" , 0x16700000001A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 830},
|
|
{"POW_QOS_THR6" , 0x16700000001B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 830},
|
|
{"POW_QOS_THR7" , 0x16700000001B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 830},
|
|
{"POW_TS_PC" , 0x1670000000390ull, CVMX_CSR_DB_TYPE_NCB, 64, 831},
|
|
{"POW_WA_COM_PC" , 0x1670000000380ull, CVMX_CSR_DB_TYPE_NCB, 64, 832},
|
|
{"POW_WA_PC0" , 0x1670000000300ull, CVMX_CSR_DB_TYPE_NCB, 64, 833},
|
|
{"POW_WA_PC1" , 0x1670000000308ull, CVMX_CSR_DB_TYPE_NCB, 64, 833},
|
|
{"POW_WA_PC2" , 0x1670000000310ull, CVMX_CSR_DB_TYPE_NCB, 64, 833},
|
|
{"POW_WA_PC3" , 0x1670000000318ull, CVMX_CSR_DB_TYPE_NCB, 64, 833},
|
|
{"POW_WA_PC4" , 0x1670000000320ull, CVMX_CSR_DB_TYPE_NCB, 64, 833},
|
|
{"POW_WA_PC5" , 0x1670000000328ull, CVMX_CSR_DB_TYPE_NCB, 64, 833},
|
|
{"POW_WA_PC6" , 0x1670000000330ull, CVMX_CSR_DB_TYPE_NCB, 64, 833},
|
|
{"POW_WA_PC7" , 0x1670000000338ull, CVMX_CSR_DB_TYPE_NCB, 64, 833},
|
|
{"POW_WQ_INT" , 0x1670000000200ull, CVMX_CSR_DB_TYPE_NCB, 64, 834},
|
|
{"POW_WQ_INT_CNT0" , 0x1670000000100ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
|
|
{"POW_WQ_INT_CNT1" , 0x1670000000108ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
|
|
{"POW_WQ_INT_CNT2" , 0x1670000000110ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
|
|
{"POW_WQ_INT_CNT3" , 0x1670000000118ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
|
|
{"POW_WQ_INT_CNT4" , 0x1670000000120ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
|
|
{"POW_WQ_INT_CNT5" , 0x1670000000128ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
|
|
{"POW_WQ_INT_CNT6" , 0x1670000000130ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
|
|
{"POW_WQ_INT_CNT7" , 0x1670000000138ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
|
|
{"POW_WQ_INT_CNT8" , 0x1670000000140ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
|
|
{"POW_WQ_INT_CNT9" , 0x1670000000148ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
|
|
{"POW_WQ_INT_CNT10" , 0x1670000000150ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
|
|
{"POW_WQ_INT_CNT11" , 0x1670000000158ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
|
|
{"POW_WQ_INT_CNT12" , 0x1670000000160ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
|
|
{"POW_WQ_INT_CNT13" , 0x1670000000168ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
|
|
{"POW_WQ_INT_CNT14" , 0x1670000000170ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
|
|
{"POW_WQ_INT_CNT15" , 0x1670000000178ull, CVMX_CSR_DB_TYPE_NCB, 64, 835},
|
|
{"POW_WQ_INT_PC" , 0x1670000000208ull, CVMX_CSR_DB_TYPE_NCB, 64, 836},
|
|
{"POW_WQ_INT_THR0" , 0x1670000000080ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
|
|
{"POW_WQ_INT_THR1" , 0x1670000000088ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
|
|
{"POW_WQ_INT_THR2" , 0x1670000000090ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
|
|
{"POW_WQ_INT_THR3" , 0x1670000000098ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
|
|
{"POW_WQ_INT_THR4" , 0x16700000000A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
|
|
{"POW_WQ_INT_THR5" , 0x16700000000A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
|
|
{"POW_WQ_INT_THR6" , 0x16700000000B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
|
|
{"POW_WQ_INT_THR7" , 0x16700000000B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
|
|
{"POW_WQ_INT_THR8" , 0x16700000000C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
|
|
{"POW_WQ_INT_THR9" , 0x16700000000C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
|
|
{"POW_WQ_INT_THR10" , 0x16700000000D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
|
|
{"POW_WQ_INT_THR11" , 0x16700000000D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
|
|
{"POW_WQ_INT_THR12" , 0x16700000000E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
|
|
{"POW_WQ_INT_THR13" , 0x16700000000E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
|
|
{"POW_WQ_INT_THR14" , 0x16700000000F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
|
|
{"POW_WQ_INT_THR15" , 0x16700000000F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 837},
|
|
{"POW_WS_PC0" , 0x1670000000280ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
|
|
{"POW_WS_PC1" , 0x1670000000288ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
|
|
{"POW_WS_PC2" , 0x1670000000290ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
|
|
{"POW_WS_PC3" , 0x1670000000298ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
|
|
{"POW_WS_PC4" , 0x16700000002A0ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
|
|
{"POW_WS_PC5" , 0x16700000002A8ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
|
|
{"POW_WS_PC6" , 0x16700000002B0ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
|
|
{"POW_WS_PC7" , 0x16700000002B8ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
|
|
{"POW_WS_PC8" , 0x16700000002C0ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
|
|
{"POW_WS_PC9" , 0x16700000002C8ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
|
|
{"POW_WS_PC10" , 0x16700000002D0ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
|
|
{"POW_WS_PC11" , 0x16700000002D8ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
|
|
{"POW_WS_PC12" , 0x16700000002E0ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
|
|
{"POW_WS_PC13" , 0x16700000002E8ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
|
|
{"POW_WS_PC14" , 0x16700000002F0ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
|
|
{"POW_WS_PC15" , 0x16700000002F8ull, CVMX_CSR_DB_TYPE_NCB, 64, 838},
|
|
{"RAD_MEM_DEBUG0" , 0x1180070001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 839},
|
|
{"RAD_MEM_DEBUG1" , 0x1180070001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 840},
|
|
{"RAD_MEM_DEBUG2" , 0x1180070001010ull, CVMX_CSR_DB_TYPE_RSL, 64, 841},
|
|
{"RAD_REG_BIST_RESULT" , 0x1180070000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 842},
|
|
{"RAD_REG_CMD_BUF" , 0x1180070000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 843},
|
|
{"RAD_REG_CTL" , 0x1180070000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 844},
|
|
{"RAD_REG_DEBUG0" , 0x1180070000100ull, CVMX_CSR_DB_TYPE_RSL, 64, 845},
|
|
{"RAD_REG_DEBUG1" , 0x1180070000108ull, CVMX_CSR_DB_TYPE_RSL, 64, 846},
|
|
{"RAD_REG_DEBUG10" , 0x1180070000150ull, CVMX_CSR_DB_TYPE_RSL, 64, 847},
|
|
{"RAD_REG_DEBUG11" , 0x1180070000158ull, CVMX_CSR_DB_TYPE_RSL, 64, 848},
|
|
{"RAD_REG_DEBUG12" , 0x1180070000160ull, CVMX_CSR_DB_TYPE_RSL, 64, 849},
|
|
{"RAD_REG_DEBUG2" , 0x1180070000110ull, CVMX_CSR_DB_TYPE_RSL, 64, 850},
|
|
{"RAD_REG_DEBUG3" , 0x1180070000118ull, CVMX_CSR_DB_TYPE_RSL, 64, 851},
|
|
{"RAD_REG_DEBUG4" , 0x1180070000120ull, CVMX_CSR_DB_TYPE_RSL, 64, 852},
|
|
{"RAD_REG_DEBUG5" , 0x1180070000128ull, CVMX_CSR_DB_TYPE_RSL, 64, 853},
|
|
{"RAD_REG_DEBUG6" , 0x1180070000130ull, CVMX_CSR_DB_TYPE_RSL, 64, 854},
|
|
{"RAD_REG_DEBUG7" , 0x1180070000138ull, CVMX_CSR_DB_TYPE_RSL, 64, 855},
|
|
{"RAD_REG_DEBUG8" , 0x1180070000140ull, CVMX_CSR_DB_TYPE_RSL, 64, 856},
|
|
{"RAD_REG_DEBUG9" , 0x1180070000148ull, CVMX_CSR_DB_TYPE_RSL, 64, 857},
|
|
{"RAD_REG_ERROR" , 0x1180070000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 858},
|
|
{"RAD_REG_INT_MASK" , 0x1180070000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 859},
|
|
{"RAD_REG_POLYNOMIAL" , 0x1180070000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 860},
|
|
{"RAD_REG_READ_IDX" , 0x1180070000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 861},
|
|
{"RNM_BIST_STATUS" , 0x1180040000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 862},
|
|
{"RNM_CTL_STATUS" , 0x1180040000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 863},
|
|
{"SMI0_CLK" , 0x1180000001818ull, CVMX_CSR_DB_TYPE_RSL, 64, 864},
|
|
{"SMI1_CLK" , 0x1180000001918ull, CVMX_CSR_DB_TYPE_RSL, 64, 864},
|
|
{"SMI0_CMD" , 0x1180000001800ull, CVMX_CSR_DB_TYPE_RSL, 64, 865},
|
|
{"SMI1_CMD" , 0x1180000001900ull, CVMX_CSR_DB_TYPE_RSL, 64, 865},
|
|
{"SMI0_EN" , 0x1180000001820ull, CVMX_CSR_DB_TYPE_RSL, 64, 866},
|
|
{"SMI1_EN" , 0x1180000001920ull, CVMX_CSR_DB_TYPE_RSL, 64, 866},
|
|
{"SMI0_RD_DAT" , 0x1180000001810ull, CVMX_CSR_DB_TYPE_RSL, 64, 867},
|
|
{"SMI1_RD_DAT" , 0x1180000001910ull, CVMX_CSR_DB_TYPE_RSL, 64, 867},
|
|
{"SMI0_WR_DAT" , 0x1180000001808ull, CVMX_CSR_DB_TYPE_RSL, 64, 868},
|
|
{"SMI1_WR_DAT" , 0x1180000001908ull, CVMX_CSR_DB_TYPE_RSL, 64, 868},
|
|
{"TIM_MEM_DEBUG0" , 0x1180058001100ull, CVMX_CSR_DB_TYPE_RSL, 64, 869},
|
|
{"TIM_MEM_DEBUG1" , 0x1180058001108ull, CVMX_CSR_DB_TYPE_RSL, 64, 870},
|
|
{"TIM_MEM_DEBUG2" , 0x1180058001110ull, CVMX_CSR_DB_TYPE_RSL, 64, 871},
|
|
{"TIM_MEM_RING0" , 0x1180058001000ull, CVMX_CSR_DB_TYPE_RSL, 64, 872},
|
|
{"TIM_MEM_RING1" , 0x1180058001008ull, CVMX_CSR_DB_TYPE_RSL, 64, 873},
|
|
{"TIM_REG_BIST_RESULT" , 0x1180058000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 874},
|
|
{"TIM_REG_ERROR" , 0x1180058000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 875},
|
|
{"TIM_REG_FLAGS" , 0x1180058000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 876},
|
|
{"TIM_REG_INT_MASK" , 0x1180058000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 877},
|
|
{"TIM_REG_READ_IDX" , 0x1180058000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 878},
|
|
{"TRA_BIST_STATUS" , 0x11800A8000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 879},
|
|
{"TRA_CTL" , 0x11800A8000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 880},
|
|
{"TRA_CYCLES_SINCE" , 0x11800A8000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 881},
|
|
{"TRA_CYCLES_SINCE1" , 0x11800A8000028ull, CVMX_CSR_DB_TYPE_RSL, 64, 882},
|
|
{"TRA_FILT_ADR_ADR" , 0x11800A8000058ull, CVMX_CSR_DB_TYPE_RSL, 64, 883},
|
|
{"TRA_FILT_ADR_MSK" , 0x11800A8000060ull, CVMX_CSR_DB_TYPE_RSL, 64, 884},
|
|
{"TRA_FILT_CMD" , 0x11800A8000040ull, CVMX_CSR_DB_TYPE_RSL, 64, 885},
|
|
{"TRA_FILT_DID" , 0x11800A8000050ull, CVMX_CSR_DB_TYPE_RSL, 64, 886},
|
|
{"TRA_FILT_SID" , 0x11800A8000048ull, CVMX_CSR_DB_TYPE_RSL, 64, 887},
|
|
{"TRA_INT_STATUS" , 0x11800A8000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 888},
|
|
{"TRA_READ_DAT" , 0x11800A8000020ull, CVMX_CSR_DB_TYPE_RSL, 64, 889},
|
|
{"TRA_TRIG0_ADR_ADR" , 0x11800A8000098ull, CVMX_CSR_DB_TYPE_RSL, 64, 890},
|
|
{"TRA_TRIG0_ADR_MSK" , 0x11800A80000A0ull, CVMX_CSR_DB_TYPE_RSL, 64, 891},
|
|
{"TRA_TRIG0_CMD" , 0x11800A8000080ull, CVMX_CSR_DB_TYPE_RSL, 64, 892},
|
|
{"TRA_TRIG0_DID" , 0x11800A8000090ull, CVMX_CSR_DB_TYPE_RSL, 64, 893},
|
|
{"TRA_TRIG0_SID" , 0x11800A8000088ull, CVMX_CSR_DB_TYPE_RSL, 64, 894},
|
|
{"TRA_TRIG1_ADR_ADR" , 0x11800A80000D8ull, CVMX_CSR_DB_TYPE_RSL, 64, 895},
|
|
{"TRA_TRIG1_ADR_MSK" , 0x11800A80000E0ull, CVMX_CSR_DB_TYPE_RSL, 64, 896},
|
|
{"TRA_TRIG1_CMD" , 0x11800A80000C0ull, CVMX_CSR_DB_TYPE_RSL, 64, 897},
|
|
{"TRA_TRIG1_DID" , 0x11800A80000D0ull, CVMX_CSR_DB_TYPE_RSL, 64, 898},
|
|
{"TRA_TRIG1_SID" , 0x11800A80000C8ull, CVMX_CSR_DB_TYPE_RSL, 64, 899},
|
|
{"USBC0_DAINT" , 0x16F0010000818ull, CVMX_CSR_DB_TYPE_NCB, 32, 900},
|
|
{"USBC1_DAINT" , 0x17F0010000818ull, CVMX_CSR_DB_TYPE_NCB, 32, 900},
|
|
{"USBC0_DAINTMSK" , 0x16F001000081Cull, CVMX_CSR_DB_TYPE_NCB, 32, 901},
|
|
{"USBC1_DAINTMSK" , 0x17F001000081Cull, CVMX_CSR_DB_TYPE_NCB, 32, 901},
|
|
{"USBC0_DCFG" , 0x16F0010000800ull, CVMX_CSR_DB_TYPE_NCB, 32, 902},
|
|
{"USBC1_DCFG" , 0x17F0010000800ull, CVMX_CSR_DB_TYPE_NCB, 32, 902},
|
|
{"USBC0_DCTL" , 0x16F0010000804ull, CVMX_CSR_DB_TYPE_NCB, 32, 903},
|
|
{"USBC1_DCTL" , 0x17F0010000804ull, CVMX_CSR_DB_TYPE_NCB, 32, 903},
|
|
{"USBC0_DIEPCTL000" , 0x16F0010000900ull, CVMX_CSR_DB_TYPE_NCB, 32, 904},
|
|
{"USBC0_DIEPCTL001" , 0x16F0010000920ull, CVMX_CSR_DB_TYPE_NCB, 32, 904},
|
|
{"USBC0_DIEPCTL002" , 0x16F0010000940ull, CVMX_CSR_DB_TYPE_NCB, 32, 904},
|
|
{"USBC0_DIEPCTL003" , 0x16F0010000960ull, CVMX_CSR_DB_TYPE_NCB, 32, 904},
|
|
{"USBC0_DIEPCTL004" , 0x16F0010000980ull, CVMX_CSR_DB_TYPE_NCB, 32, 904},
|
|
{"USBC1_DIEPCTL000" , 0x17F0010000900ull, CVMX_CSR_DB_TYPE_NCB, 32, 904},
|
|
{"USBC1_DIEPCTL001" , 0x17F0010000920ull, CVMX_CSR_DB_TYPE_NCB, 32, 904},
|
|
{"USBC1_DIEPCTL002" , 0x17F0010000940ull, CVMX_CSR_DB_TYPE_NCB, 32, 904},
|
|
{"USBC1_DIEPCTL003" , 0x17F0010000960ull, CVMX_CSR_DB_TYPE_NCB, 32, 904},
|
|
{"USBC1_DIEPCTL004" , 0x17F0010000980ull, CVMX_CSR_DB_TYPE_NCB, 32, 904},
|
|
{"USBC0_DIEPINT000" , 0x16F0010000908ull, CVMX_CSR_DB_TYPE_NCB, 32, 905},
|
|
{"USBC0_DIEPINT001" , 0x16F0010000928ull, CVMX_CSR_DB_TYPE_NCB, 32, 905},
|
|
{"USBC0_DIEPINT002" , 0x16F0010000948ull, CVMX_CSR_DB_TYPE_NCB, 32, 905},
|
|
{"USBC0_DIEPINT003" , 0x16F0010000968ull, CVMX_CSR_DB_TYPE_NCB, 32, 905},
|
|
{"USBC0_DIEPINT004" , 0x16F0010000988ull, CVMX_CSR_DB_TYPE_NCB, 32, 905},
|
|
{"USBC1_DIEPINT000" , 0x17F0010000908ull, CVMX_CSR_DB_TYPE_NCB, 32, 905},
|
|
{"USBC1_DIEPINT001" , 0x17F0010000928ull, CVMX_CSR_DB_TYPE_NCB, 32, 905},
|
|
{"USBC1_DIEPINT002" , 0x17F0010000948ull, CVMX_CSR_DB_TYPE_NCB, 32, 905},
|
|
{"USBC1_DIEPINT003" , 0x17F0010000968ull, CVMX_CSR_DB_TYPE_NCB, 32, 905},
|
|
{"USBC1_DIEPINT004" , 0x17F0010000988ull, CVMX_CSR_DB_TYPE_NCB, 32, 905},
|
|
{"USBC0_DIEPMSK" , 0x16F0010000810ull, CVMX_CSR_DB_TYPE_NCB, 32, 906},
|
|
{"USBC1_DIEPMSK" , 0x17F0010000810ull, CVMX_CSR_DB_TYPE_NCB, 32, 906},
|
|
{"USBC0_DIEPTSIZ000" , 0x16F0010000910ull, CVMX_CSR_DB_TYPE_NCB, 32, 907},
|
|
{"USBC0_DIEPTSIZ001" , 0x16F0010000930ull, CVMX_CSR_DB_TYPE_NCB, 32, 907},
|
|
{"USBC0_DIEPTSIZ002" , 0x16F0010000950ull, CVMX_CSR_DB_TYPE_NCB, 32, 907},
|
|
{"USBC0_DIEPTSIZ003" , 0x16F0010000970ull, CVMX_CSR_DB_TYPE_NCB, 32, 907},
|
|
{"USBC0_DIEPTSIZ004" , 0x16F0010000990ull, CVMX_CSR_DB_TYPE_NCB, 32, 907},
|
|
{"USBC1_DIEPTSIZ000" , 0x17F0010000910ull, CVMX_CSR_DB_TYPE_NCB, 32, 907},
|
|
{"USBC1_DIEPTSIZ001" , 0x17F0010000930ull, CVMX_CSR_DB_TYPE_NCB, 32, 907},
|
|
{"USBC1_DIEPTSIZ002" , 0x17F0010000950ull, CVMX_CSR_DB_TYPE_NCB, 32, 907},
|
|
{"USBC1_DIEPTSIZ003" , 0x17F0010000970ull, CVMX_CSR_DB_TYPE_NCB, 32, 907},
|
|
{"USBC1_DIEPTSIZ004" , 0x17F0010000990ull, CVMX_CSR_DB_TYPE_NCB, 32, 907},
|
|
{"USBC0_DOEPCTL000" , 0x16F0010000B00ull, CVMX_CSR_DB_TYPE_NCB, 32, 908},
|
|
{"USBC0_DOEPCTL001" , 0x16F0010000B20ull, CVMX_CSR_DB_TYPE_NCB, 32, 908},
|
|
{"USBC0_DOEPCTL002" , 0x16F0010000B40ull, CVMX_CSR_DB_TYPE_NCB, 32, 908},
|
|
{"USBC0_DOEPCTL003" , 0x16F0010000B60ull, CVMX_CSR_DB_TYPE_NCB, 32, 908},
|
|
{"USBC0_DOEPCTL004" , 0x16F0010000B80ull, CVMX_CSR_DB_TYPE_NCB, 32, 908},
|
|
{"USBC1_DOEPCTL000" , 0x17F0010000B00ull, CVMX_CSR_DB_TYPE_NCB, 32, 908},
|
|
{"USBC1_DOEPCTL001" , 0x17F0010000B20ull, CVMX_CSR_DB_TYPE_NCB, 32, 908},
|
|
{"USBC1_DOEPCTL002" , 0x17F0010000B40ull, CVMX_CSR_DB_TYPE_NCB, 32, 908},
|
|
{"USBC1_DOEPCTL003" , 0x17F0010000B60ull, CVMX_CSR_DB_TYPE_NCB, 32, 908},
|
|
{"USBC1_DOEPCTL004" , 0x17F0010000B80ull, CVMX_CSR_DB_TYPE_NCB, 32, 908},
|
|
{"USBC0_DOEPINT000" , 0x16F0010000B08ull, CVMX_CSR_DB_TYPE_NCB, 32, 909},
|
|
{"USBC0_DOEPINT001" , 0x16F0010000B28ull, CVMX_CSR_DB_TYPE_NCB, 32, 909},
|
|
{"USBC0_DOEPINT002" , 0x16F0010000B48ull, CVMX_CSR_DB_TYPE_NCB, 32, 909},
|
|
{"USBC0_DOEPINT003" , 0x16F0010000B68ull, CVMX_CSR_DB_TYPE_NCB, 32, 909},
|
|
{"USBC0_DOEPINT004" , 0x16F0010000B88ull, CVMX_CSR_DB_TYPE_NCB, 32, 909},
|
|
{"USBC1_DOEPINT000" , 0x17F0010000B08ull, CVMX_CSR_DB_TYPE_NCB, 32, 909},
|
|
{"USBC1_DOEPINT001" , 0x17F0010000B28ull, CVMX_CSR_DB_TYPE_NCB, 32, 909},
|
|
{"USBC1_DOEPINT002" , 0x17F0010000B48ull, CVMX_CSR_DB_TYPE_NCB, 32, 909},
|
|
{"USBC1_DOEPINT003" , 0x17F0010000B68ull, CVMX_CSR_DB_TYPE_NCB, 32, 909},
|
|
{"USBC1_DOEPINT004" , 0x17F0010000B88ull, CVMX_CSR_DB_TYPE_NCB, 32, 909},
|
|
{"USBC0_DOEPMSK" , 0x16F0010000814ull, CVMX_CSR_DB_TYPE_NCB, 32, 910},
|
|
{"USBC1_DOEPMSK" , 0x17F0010000814ull, CVMX_CSR_DB_TYPE_NCB, 32, 910},
|
|
{"USBC0_DOEPTSIZ000" , 0x16F0010000B10ull, CVMX_CSR_DB_TYPE_NCB, 32, 911},
|
|
{"USBC0_DOEPTSIZ001" , 0x16F0010000B30ull, CVMX_CSR_DB_TYPE_NCB, 32, 911},
|
|
{"USBC0_DOEPTSIZ002" , 0x16F0010000B50ull, CVMX_CSR_DB_TYPE_NCB, 32, 911},
|
|
{"USBC0_DOEPTSIZ003" , 0x16F0010000B70ull, CVMX_CSR_DB_TYPE_NCB, 32, 911},
|
|
{"USBC0_DOEPTSIZ004" , 0x16F0010000B90ull, CVMX_CSR_DB_TYPE_NCB, 32, 911},
|
|
{"USBC1_DOEPTSIZ000" , 0x17F0010000B10ull, CVMX_CSR_DB_TYPE_NCB, 32, 911},
|
|
{"USBC1_DOEPTSIZ001" , 0x17F0010000B30ull, CVMX_CSR_DB_TYPE_NCB, 32, 911},
|
|
{"USBC1_DOEPTSIZ002" , 0x17F0010000B50ull, CVMX_CSR_DB_TYPE_NCB, 32, 911},
|
|
{"USBC1_DOEPTSIZ003" , 0x17F0010000B70ull, CVMX_CSR_DB_TYPE_NCB, 32, 911},
|
|
{"USBC1_DOEPTSIZ004" , 0x17F0010000B90ull, CVMX_CSR_DB_TYPE_NCB, 32, 911},
|
|
{"USBC0_DPTXFSIZ001" , 0x16F0010000104ull, CVMX_CSR_DB_TYPE_NCB, 32, 912},
|
|
{"USBC0_DPTXFSIZ002" , 0x16F0010000108ull, CVMX_CSR_DB_TYPE_NCB, 32, 912},
|
|
{"USBC0_DPTXFSIZ003" , 0x16F001000010Cull, CVMX_CSR_DB_TYPE_NCB, 32, 912},
|
|
{"USBC0_DPTXFSIZ004" , 0x16F0010000110ull, CVMX_CSR_DB_TYPE_NCB, 32, 912},
|
|
{"USBC1_DPTXFSIZ001" , 0x17F0010000104ull, CVMX_CSR_DB_TYPE_NCB, 32, 912},
|
|
{"USBC1_DPTXFSIZ002" , 0x17F0010000108ull, CVMX_CSR_DB_TYPE_NCB, 32, 912},
|
|
{"USBC1_DPTXFSIZ003" , 0x17F001000010Cull, CVMX_CSR_DB_TYPE_NCB, 32, 912},
|
|
{"USBC1_DPTXFSIZ004" , 0x17F0010000110ull, CVMX_CSR_DB_TYPE_NCB, 32, 912},
|
|
{"USBC0_DSTS" , 0x16F0010000808ull, CVMX_CSR_DB_TYPE_NCB, 32, 913},
|
|
{"USBC1_DSTS" , 0x17F0010000808ull, CVMX_CSR_DB_TYPE_NCB, 32, 913},
|
|
{"USBC0_DTKNQR1" , 0x16F0010000820ull, CVMX_CSR_DB_TYPE_NCB, 32, 914},
|
|
{"USBC1_DTKNQR1" , 0x17F0010000820ull, CVMX_CSR_DB_TYPE_NCB, 32, 914},
|
|
{"USBC0_DTKNQR2" , 0x16F0010000824ull, CVMX_CSR_DB_TYPE_NCB, 32, 915},
|
|
{"USBC1_DTKNQR2" , 0x17F0010000824ull, CVMX_CSR_DB_TYPE_NCB, 32, 915},
|
|
{"USBC0_DTKNQR3" , 0x16F0010000830ull, CVMX_CSR_DB_TYPE_NCB, 32, 916},
|
|
{"USBC1_DTKNQR3" , 0x17F0010000830ull, CVMX_CSR_DB_TYPE_NCB, 32, 916},
|
|
{"USBC0_DTKNQR4" , 0x16F0010000834ull, CVMX_CSR_DB_TYPE_NCB, 32, 917},
|
|
{"USBC1_DTKNQR4" , 0x17F0010000834ull, CVMX_CSR_DB_TYPE_NCB, 32, 917},
|
|
{"USBC0_GAHBCFG" , 0x16F0010000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 918},
|
|
{"USBC1_GAHBCFG" , 0x17F0010000008ull, CVMX_CSR_DB_TYPE_NCB, 32, 918},
|
|
{"USBC0_GHWCFG1" , 0x16F0010000044ull, CVMX_CSR_DB_TYPE_NCB, 32, 919},
|
|
{"USBC1_GHWCFG1" , 0x17F0010000044ull, CVMX_CSR_DB_TYPE_NCB, 32, 919},
|
|
{"USBC0_GHWCFG2" , 0x16F0010000048ull, CVMX_CSR_DB_TYPE_NCB, 32, 920},
|
|
{"USBC1_GHWCFG2" , 0x17F0010000048ull, CVMX_CSR_DB_TYPE_NCB, 32, 920},
|
|
{"USBC0_GHWCFG3" , 0x16F001000004Cull, CVMX_CSR_DB_TYPE_NCB, 32, 921},
|
|
{"USBC1_GHWCFG3" , 0x17F001000004Cull, CVMX_CSR_DB_TYPE_NCB, 32, 921},
|
|
{"USBC0_GHWCFG4" , 0x16F0010000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 922},
|
|
{"USBC1_GHWCFG4" , 0x17F0010000050ull, CVMX_CSR_DB_TYPE_NCB, 32, 922},
|
|
{"USBC0_GINTMSK" , 0x16F0010000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 923},
|
|
{"USBC1_GINTMSK" , 0x17F0010000018ull, CVMX_CSR_DB_TYPE_NCB, 32, 923},
|
|
{"USBC0_GINTSTS" , 0x16F0010000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 924},
|
|
{"USBC1_GINTSTS" , 0x17F0010000014ull, CVMX_CSR_DB_TYPE_NCB, 32, 924},
|
|
{"USBC0_GNPTXFSIZ" , 0x16F0010000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 925},
|
|
{"USBC1_GNPTXFSIZ" , 0x17F0010000028ull, CVMX_CSR_DB_TYPE_NCB, 32, 925},
|
|
{"USBC0_GNPTXSTS" , 0x16F001000002Cull, CVMX_CSR_DB_TYPE_NCB, 32, 926},
|
|
{"USBC1_GNPTXSTS" , 0x17F001000002Cull, CVMX_CSR_DB_TYPE_NCB, 32, 926},
|
|
{"USBC0_GOTGCTL" , 0x16F0010000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 927},
|
|
{"USBC1_GOTGCTL" , 0x17F0010000000ull, CVMX_CSR_DB_TYPE_NCB, 32, 927},
|
|
{"USBC0_GOTGINT" , 0x16F0010000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 928},
|
|
{"USBC1_GOTGINT" , 0x17F0010000004ull, CVMX_CSR_DB_TYPE_NCB, 32, 928},
|
|
{"USBC0_GRSTCTL" , 0x16F0010000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 929},
|
|
{"USBC1_GRSTCTL" , 0x17F0010000010ull, CVMX_CSR_DB_TYPE_NCB, 32, 929},
|
|
{"USBC0_GRXFSIZ" , 0x16F0010000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 930},
|
|
{"USBC1_GRXFSIZ" , 0x17F0010000024ull, CVMX_CSR_DB_TYPE_NCB, 32, 930},
|
|
{"USBC0_GRXSTSPD" , 0x16F0010040020ull, CVMX_CSR_DB_TYPE_NCB, 32, 931},
|
|
{"USBC1_GRXSTSPD" , 0x17F0010040020ull, CVMX_CSR_DB_TYPE_NCB, 32, 931},
|
|
{"USBC0_GRXSTSPH" , 0x16F0010000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 932},
|
|
{"USBC1_GRXSTSPH" , 0x17F0010000020ull, CVMX_CSR_DB_TYPE_NCB, 32, 932},
|
|
{"USBC0_GRXSTSRD" , 0x16F001004001Cull, CVMX_CSR_DB_TYPE_NCB, 32, 933},
|
|
{"USBC1_GRXSTSRD" , 0x17F001004001Cull, CVMX_CSR_DB_TYPE_NCB, 32, 933},
|
|
{"USBC0_GRXSTSRH" , 0x16F001000001Cull, CVMX_CSR_DB_TYPE_NCB, 32, 934},
|
|
{"USBC1_GRXSTSRH" , 0x17F001000001Cull, CVMX_CSR_DB_TYPE_NCB, 32, 934},
|
|
{"USBC0_GSNPSID" , 0x16F0010000040ull, CVMX_CSR_DB_TYPE_NCB, 32, 935},
|
|
{"USBC1_GSNPSID" , 0x17F0010000040ull, CVMX_CSR_DB_TYPE_NCB, 32, 935},
|
|
{"USBC0_GUSBCFG" , 0x16F001000000Cull, CVMX_CSR_DB_TYPE_NCB, 32, 936},
|
|
{"USBC1_GUSBCFG" , 0x17F001000000Cull, CVMX_CSR_DB_TYPE_NCB, 32, 936},
|
|
{"USBC0_HAINT" , 0x16F0010000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 937},
|
|
{"USBC1_HAINT" , 0x17F0010000414ull, CVMX_CSR_DB_TYPE_NCB, 32, 937},
|
|
{"USBC0_HAINTMSK" , 0x16F0010000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 938},
|
|
{"USBC1_HAINTMSK" , 0x17F0010000418ull, CVMX_CSR_DB_TYPE_NCB, 32, 938},
|
|
{"USBC0_HCCHAR000" , 0x16F0010000500ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
|
|
{"USBC0_HCCHAR001" , 0x16F0010000520ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
|
|
{"USBC0_HCCHAR002" , 0x16F0010000540ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
|
|
{"USBC0_HCCHAR003" , 0x16F0010000560ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
|
|
{"USBC0_HCCHAR004" , 0x16F0010000580ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
|
|
{"USBC0_HCCHAR005" , 0x16F00100005A0ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
|
|
{"USBC0_HCCHAR006" , 0x16F00100005C0ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
|
|
{"USBC0_HCCHAR007" , 0x16F00100005E0ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
|
|
{"USBC1_HCCHAR000" , 0x17F0010000500ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
|
|
{"USBC1_HCCHAR001" , 0x17F0010000520ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
|
|
{"USBC1_HCCHAR002" , 0x17F0010000540ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
|
|
{"USBC1_HCCHAR003" , 0x17F0010000560ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
|
|
{"USBC1_HCCHAR004" , 0x17F0010000580ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
|
|
{"USBC1_HCCHAR005" , 0x17F00100005A0ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
|
|
{"USBC1_HCCHAR006" , 0x17F00100005C0ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
|
|
{"USBC1_HCCHAR007" , 0x17F00100005E0ull, CVMX_CSR_DB_TYPE_NCB, 32, 939},
|
|
{"USBC0_HCFG" , 0x16F0010000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 940},
|
|
{"USBC1_HCFG" , 0x17F0010000400ull, CVMX_CSR_DB_TYPE_NCB, 32, 940},
|
|
{"USBC0_HCINT000" , 0x16F0010000508ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
|
|
{"USBC0_HCINT001" , 0x16F0010000528ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
|
|
{"USBC0_HCINT002" , 0x16F0010000548ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
|
|
{"USBC0_HCINT003" , 0x16F0010000568ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
|
|
{"USBC0_HCINT004" , 0x16F0010000588ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
|
|
{"USBC0_HCINT005" , 0x16F00100005A8ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
|
|
{"USBC0_HCINT006" , 0x16F00100005C8ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
|
|
{"USBC0_HCINT007" , 0x16F00100005E8ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
|
|
{"USBC1_HCINT000" , 0x17F0010000508ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
|
|
{"USBC1_HCINT001" , 0x17F0010000528ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
|
|
{"USBC1_HCINT002" , 0x17F0010000548ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
|
|
{"USBC1_HCINT003" , 0x17F0010000568ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
|
|
{"USBC1_HCINT004" , 0x17F0010000588ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
|
|
{"USBC1_HCINT005" , 0x17F00100005A8ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
|
|
{"USBC1_HCINT006" , 0x17F00100005C8ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
|
|
{"USBC1_HCINT007" , 0x17F00100005E8ull, CVMX_CSR_DB_TYPE_NCB, 32, 941},
|
|
{"USBC0_HCINTMSK000" , 0x16F001000050Cull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
|
|
{"USBC0_HCINTMSK001" , 0x16F001000052Cull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
|
|
{"USBC0_HCINTMSK002" , 0x16F001000054Cull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
|
|
{"USBC0_HCINTMSK003" , 0x16F001000056Cull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
|
|
{"USBC0_HCINTMSK004" , 0x16F001000058Cull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
|
|
{"USBC0_HCINTMSK005" , 0x16F00100005ACull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
|
|
{"USBC0_HCINTMSK006" , 0x16F00100005CCull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
|
|
{"USBC0_HCINTMSK007" , 0x16F00100005ECull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
|
|
{"USBC1_HCINTMSK000" , 0x17F001000050Cull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
|
|
{"USBC1_HCINTMSK001" , 0x17F001000052Cull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
|
|
{"USBC1_HCINTMSK002" , 0x17F001000054Cull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
|
|
{"USBC1_HCINTMSK003" , 0x17F001000056Cull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
|
|
{"USBC1_HCINTMSK004" , 0x17F001000058Cull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
|
|
{"USBC1_HCINTMSK005" , 0x17F00100005ACull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
|
|
{"USBC1_HCINTMSK006" , 0x17F00100005CCull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
|
|
{"USBC1_HCINTMSK007" , 0x17F00100005ECull, CVMX_CSR_DB_TYPE_NCB, 32, 942},
|
|
{"USBC0_HCSPLT000" , 0x16F0010000504ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
|
|
{"USBC0_HCSPLT001" , 0x16F0010000524ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
|
|
{"USBC0_HCSPLT002" , 0x16F0010000544ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
|
|
{"USBC0_HCSPLT003" , 0x16F0010000564ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
|
|
{"USBC0_HCSPLT004" , 0x16F0010000584ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
|
|
{"USBC0_HCSPLT005" , 0x16F00100005A4ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
|
|
{"USBC0_HCSPLT006" , 0x16F00100005C4ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
|
|
{"USBC0_HCSPLT007" , 0x16F00100005E4ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
|
|
{"USBC1_HCSPLT000" , 0x17F0010000504ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
|
|
{"USBC1_HCSPLT001" , 0x17F0010000524ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
|
|
{"USBC1_HCSPLT002" , 0x17F0010000544ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
|
|
{"USBC1_HCSPLT003" , 0x17F0010000564ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
|
|
{"USBC1_HCSPLT004" , 0x17F0010000584ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
|
|
{"USBC1_HCSPLT005" , 0x17F00100005A4ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
|
|
{"USBC1_HCSPLT006" , 0x17F00100005C4ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
|
|
{"USBC1_HCSPLT007" , 0x17F00100005E4ull, CVMX_CSR_DB_TYPE_NCB, 32, 943},
|
|
{"USBC0_HCTSIZ000" , 0x16F0010000510ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
|
|
{"USBC0_HCTSIZ001" , 0x16F0010000530ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
|
|
{"USBC0_HCTSIZ002" , 0x16F0010000550ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
|
|
{"USBC0_HCTSIZ003" , 0x16F0010000570ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
|
|
{"USBC0_HCTSIZ004" , 0x16F0010000590ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
|
|
{"USBC0_HCTSIZ005" , 0x16F00100005B0ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
|
|
{"USBC0_HCTSIZ006" , 0x16F00100005D0ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
|
|
{"USBC0_HCTSIZ007" , 0x16F00100005F0ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
|
|
{"USBC1_HCTSIZ000" , 0x17F0010000510ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
|
|
{"USBC1_HCTSIZ001" , 0x17F0010000530ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
|
|
{"USBC1_HCTSIZ002" , 0x17F0010000550ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
|
|
{"USBC1_HCTSIZ003" , 0x17F0010000570ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
|
|
{"USBC1_HCTSIZ004" , 0x17F0010000590ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
|
|
{"USBC1_HCTSIZ005" , 0x17F00100005B0ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
|
|
{"USBC1_HCTSIZ006" , 0x17F00100005D0ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
|
|
{"USBC1_HCTSIZ007" , 0x17F00100005F0ull, CVMX_CSR_DB_TYPE_NCB, 32, 944},
|
|
{"USBC0_HFIR" , 0x16F0010000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 945},
|
|
{"USBC1_HFIR" , 0x17F0010000404ull, CVMX_CSR_DB_TYPE_NCB, 32, 945},
|
|
{"USBC0_HFNUM" , 0x16F0010000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 946},
|
|
{"USBC1_HFNUM" , 0x17F0010000408ull, CVMX_CSR_DB_TYPE_NCB, 32, 946},
|
|
{"USBC0_HPRT" , 0x16F0010000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 947},
|
|
{"USBC1_HPRT" , 0x17F0010000440ull, CVMX_CSR_DB_TYPE_NCB, 32, 947},
|
|
{"USBC0_HPTXFSIZ" , 0x16F0010000100ull, CVMX_CSR_DB_TYPE_NCB, 32, 948},
|
|
{"USBC1_HPTXFSIZ" , 0x17F0010000100ull, CVMX_CSR_DB_TYPE_NCB, 32, 948},
|
|
{"USBC0_HPTXSTS" , 0x16F0010000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 949},
|
|
{"USBC1_HPTXSTS" , 0x17F0010000410ull, CVMX_CSR_DB_TYPE_NCB, 32, 949},
|
|
{"USBC0_NPTXDFIFO000" , 0x16F0010001000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
|
|
{"USBC0_NPTXDFIFO001" , 0x16F0010002000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
|
|
{"USBC0_NPTXDFIFO002" , 0x16F0010003000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
|
|
{"USBC0_NPTXDFIFO003" , 0x16F0010004000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
|
|
{"USBC0_NPTXDFIFO004" , 0x16F0010005000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
|
|
{"USBC0_NPTXDFIFO005" , 0x16F0010006000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
|
|
{"USBC0_NPTXDFIFO006" , 0x16F0010007000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
|
|
{"USBC0_NPTXDFIFO007" , 0x16F0010008000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
|
|
{"USBC1_NPTXDFIFO000" , 0x17F0010001000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
|
|
{"USBC1_NPTXDFIFO001" , 0x17F0010002000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
|
|
{"USBC1_NPTXDFIFO002" , 0x17F0010003000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
|
|
{"USBC1_NPTXDFIFO003" , 0x17F0010004000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
|
|
{"USBC1_NPTXDFIFO004" , 0x17F0010005000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
|
|
{"USBC1_NPTXDFIFO005" , 0x17F0010006000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
|
|
{"USBC1_NPTXDFIFO006" , 0x17F0010007000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
|
|
{"USBC1_NPTXDFIFO007" , 0x17F0010008000ull, CVMX_CSR_DB_TYPE_NCB, 32, 950},
|
|
{"USBC0_PCGCCTL" , 0x16F0010000E00ull, CVMX_CSR_DB_TYPE_NCB, 32, 951},
|
|
{"USBC1_PCGCCTL" , 0x17F0010000E00ull, CVMX_CSR_DB_TYPE_NCB, 32, 951},
|
|
{"USBN0_BIST_STATUS" , 0x11800680007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
|
|
{"USBN1_BIST_STATUS" , 0x11800780007F8ull, CVMX_CSR_DB_TYPE_RSL, 64, 952},
|
|
{"USBN0_CLK_CTL" , 0x1180068000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
|
|
{"USBN1_CLK_CTL" , 0x1180078000010ull, CVMX_CSR_DB_TYPE_RSL, 64, 953},
|
|
{"USBN0_CTL_STATUS" , 0x16F0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 954},
|
|
{"USBN1_CTL_STATUS" , 0x17F0000000800ull, CVMX_CSR_DB_TYPE_NCB, 64, 954},
|
|
{"USBN0_DMA0_INB_CHN0" , 0x16F0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 955},
|
|
{"USBN1_DMA0_INB_CHN0" , 0x17F0000000818ull, CVMX_CSR_DB_TYPE_NCB, 64, 955},
|
|
{"USBN0_DMA0_INB_CHN1" , 0x16F0000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 956},
|
|
{"USBN1_DMA0_INB_CHN1" , 0x17F0000000820ull, CVMX_CSR_DB_TYPE_NCB, 64, 956},
|
|
{"USBN0_DMA0_INB_CHN2" , 0x16F0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 957},
|
|
{"USBN1_DMA0_INB_CHN2" , 0x17F0000000828ull, CVMX_CSR_DB_TYPE_NCB, 64, 957},
|
|
{"USBN0_DMA0_INB_CHN3" , 0x16F0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 958},
|
|
{"USBN1_DMA0_INB_CHN3" , 0x17F0000000830ull, CVMX_CSR_DB_TYPE_NCB, 64, 958},
|
|
{"USBN0_DMA0_INB_CHN4" , 0x16F0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 959},
|
|
{"USBN1_DMA0_INB_CHN4" , 0x17F0000000838ull, CVMX_CSR_DB_TYPE_NCB, 64, 959},
|
|
{"USBN0_DMA0_INB_CHN5" , 0x16F0000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 960},
|
|
{"USBN1_DMA0_INB_CHN5" , 0x17F0000000840ull, CVMX_CSR_DB_TYPE_NCB, 64, 960},
|
|
{"USBN0_DMA0_INB_CHN6" , 0x16F0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 961},
|
|
{"USBN1_DMA0_INB_CHN6" , 0x17F0000000848ull, CVMX_CSR_DB_TYPE_NCB, 64, 961},
|
|
{"USBN0_DMA0_INB_CHN7" , 0x16F0000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 962},
|
|
{"USBN1_DMA0_INB_CHN7" , 0x17F0000000850ull, CVMX_CSR_DB_TYPE_NCB, 64, 962},
|
|
{"USBN0_DMA0_OUTB_CHN0" , 0x16F0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 963},
|
|
{"USBN1_DMA0_OUTB_CHN0" , 0x17F0000000858ull, CVMX_CSR_DB_TYPE_NCB, 64, 963},
|
|
{"USBN0_DMA0_OUTB_CHN1" , 0x16F0000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 964},
|
|
{"USBN1_DMA0_OUTB_CHN1" , 0x17F0000000860ull, CVMX_CSR_DB_TYPE_NCB, 64, 964},
|
|
{"USBN0_DMA0_OUTB_CHN2" , 0x16F0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 965},
|
|
{"USBN1_DMA0_OUTB_CHN2" , 0x17F0000000868ull, CVMX_CSR_DB_TYPE_NCB, 64, 965},
|
|
{"USBN0_DMA0_OUTB_CHN3" , 0x16F0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 966},
|
|
{"USBN1_DMA0_OUTB_CHN3" , 0x17F0000000870ull, CVMX_CSR_DB_TYPE_NCB, 64, 966},
|
|
{"USBN0_DMA0_OUTB_CHN4" , 0x16F0000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 967},
|
|
{"USBN1_DMA0_OUTB_CHN4" , 0x17F0000000878ull, CVMX_CSR_DB_TYPE_NCB, 64, 967},
|
|
{"USBN0_DMA0_OUTB_CHN5" , 0x16F0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 968},
|
|
{"USBN1_DMA0_OUTB_CHN5" , 0x17F0000000880ull, CVMX_CSR_DB_TYPE_NCB, 64, 968},
|
|
{"USBN0_DMA0_OUTB_CHN6" , 0x16F0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 969},
|
|
{"USBN1_DMA0_OUTB_CHN6" , 0x17F0000000888ull, CVMX_CSR_DB_TYPE_NCB, 64, 969},
|
|
{"USBN0_DMA0_OUTB_CHN7" , 0x16F0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 970},
|
|
{"USBN1_DMA0_OUTB_CHN7" , 0x17F0000000890ull, CVMX_CSR_DB_TYPE_NCB, 64, 970},
|
|
{"USBN0_DMA_TEST" , 0x16F0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 971},
|
|
{"USBN1_DMA_TEST" , 0x17F0000000808ull, CVMX_CSR_DB_TYPE_NCB, 64, 971},
|
|
{"USBN0_INT_ENB" , 0x1180068000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 972},
|
|
{"USBN1_INT_ENB" , 0x1180078000008ull, CVMX_CSR_DB_TYPE_RSL, 64, 972},
|
|
{"USBN0_INT_SUM" , 0x1180068000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 973},
|
|
{"USBN1_INT_SUM" , 0x1180078000000ull, CVMX_CSR_DB_TYPE_RSL, 64, 973},
|
|
{"USBN0_USBP_CTL_STATUS" , 0x1180068000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 974},
|
|
{"USBN1_USBP_CTL_STATUS" , 0x1180078000018ull, CVMX_CSR_DB_TYPE_RSL, 64, 974},
|
|
{NULL,0,0,0,0}
|
|
};
|
|
static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
|
|
/* name , bit, width, csr, type, rst un, typ un, reset, typical */
|
|
{"RESERVED_0_1" , 0, 2, 0, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OUT_OVR" , 2, 2, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_21" , 4, 18, 0, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LOSTSTAT" , 22, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_25" , 23, 3, 0, "RAZ", 1, 1, 0, 0},
|
|
{"STATOVR" , 26, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_31" , 27, 5, 0, "RAZ", 1, 1, 0, 0},
|
|
{"OVRFLW" , 32, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXPOP" , 33, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXPSH" , 34, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OVRFLW1" , 35, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXPOP1" , 36, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXPSH1" , 37, 1, 0, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 0, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 10, 1, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 1, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 5, 2, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 2, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL" , 8, 5, 2, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_13_15" , 13, 3, 2, "RAZ", 1, 1, 0, 0},
|
|
{"BYP_EN" , 16, 1, 2, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 2, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL1" , 32, 5, 2, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_37_39" , 37, 3, 2, "RAZ", 1, 1, 0, 0},
|
|
{"PCTL1" , 40, 5, 2, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_45_47" , 45, 3, 2, "RAZ", 1, 1, 0, 0},
|
|
{"BYP_EN1" , 48, 1, 2, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 2, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 3, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 1, 1, 3, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 3, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 4, "R/W", 0, 1, 0ull, 0},
|
|
{"SPEED" , 1, 1, 4, "RO", 0, 0, 0ull, 0ull},
|
|
{"DUPLEX" , 2, 1, 4, "R/W", 0, 1, 1ull, 0},
|
|
{"SLOTTIME" , 3, 1, 4, "RO", 0, 0, 0ull, 0ull},
|
|
{"RX_EN" , 4, 1, 4, "R/W", 0, 1, 0ull, 0},
|
|
{"TX_EN" , 5, 1, 4, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 4, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 64, 5, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 6, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 7, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 8, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 9, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 10, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 0, 8, 11, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 11, "RAZ", 1, 1, 0, 0},
|
|
{"BCST" , 0, 1, 12, "R/W", 0, 1, 1ull, 0},
|
|
{"MCST" , 1, 2, 12, "R/W", 0, 1, 0ull, 0},
|
|
{"CAM_MODE" , 3, 1, 12, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 12, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 5, 13, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_5_63" , 5, 59, 13, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_1" , 1, 1, 14, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 2, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"JABBER" , 3, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCSERR" , 4, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"ALNERR" , 5, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"LENERR" , 6, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RCVERR" , 7, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SKPERR" , 8, 1, 14, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_9_63" , 9, 55, 14, "RAZ", 1, 1, 0, 0},
|
|
{"PRE_CHK" , 0, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PRE_STRP" , 1, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_DRP" , 2, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_BCK" , 3, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_MCST" , 4, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_SMAC" , 5, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRE_FREE" , 6, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"VLAN_LEN" , 7, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PAD_LEN" , 8, 1, 15, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRE_ALIGN" , 9, 1, 15, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_10_63" , 10, 54, 15, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 16, 16, "R/W", 0, 0, 1536ull, 1536ull},
|
|
{"RESERVED_16_63" , 16, 48, 16, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 16, 17, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_16_63" , 16, 48, 17, "RAZ", 1, 1, 0, 0},
|
|
{"IFG" , 0, 4, 18, "R/W", 0, 0, 12ull, 12ull},
|
|
{"RESERVED_4_63" , 4, 60, 18, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 19, "RAZ", 1, 1, 0, 0},
|
|
{"MAXERR" , 2, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"JABBER" , 3, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ALNERR" , 5, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 6, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RCVERR" , 7, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 19, "RAZ", 1, 1, 0, 0},
|
|
{"OVRERR" , 10, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_18" , 16, 3, 19, "RAZ", 1, 1, 0, 0},
|
|
{"PAUSE_DRP" , 19, 1, 19, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 19, "RAZ", 1, 1, 0, 0},
|
|
{"MINERR" , 0, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 20, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 2, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"JABBER" , 3, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ALNERR" , 5, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 6, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RCVERR" , 7, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 20, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OVRERR" , 10, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_18" , 16, 3, 20, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PAUSE_DRP" , 19, 1, 20, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 20, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 21, "R/W", 0, 0, 10240ull, 10240ull},
|
|
{"RESERVED_16_63" , 16, 48, 21, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 16, 22, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 22, "RAZ", 1, 1, 0, 0},
|
|
{"RD_CLR" , 0, 1, 23, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 23, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 24, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 24, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 25, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 25, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 26, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 26, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 27, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 27, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 28, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 28, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 29, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 29, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 30, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 30, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 31, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 31, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 32, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 32, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 7, 33, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 33, "RAZ", 1, 1, 0, 0},
|
|
{"FCSSEL" , 8, 1, 33, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 33, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 34, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_6_63" , 6, 58, 34, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 35, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_6_63" , 6, 58, 35, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 9, 36, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_9_63" , 9, 55, 36, "RAZ", 1, 1, 0, 0},
|
|
{"COMMIT" , 0, 2, 37, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_15" , 2, 14, 37, "RAZ", 1, 1, 0, 0},
|
|
{"DROP" , 16, 2, 37, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 37, "RAZ", 1, 1, 0, 0},
|
|
{"RX" , 0, 2, 38, "RC", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_3" , 2, 2, 38, "RAZ", 1, 1, 0, 0},
|
|
{"TX" , 4, 2, 38, "RC", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 38, "RAZ", 1, 1, 0, 0},
|
|
{"SMAC" , 0, 48, 39, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 39, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 40, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP" , 16, 1, 40, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 40, "RAZ", 1, 1, 0, 0},
|
|
{"PREAMBLE" , 0, 1, 41, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PAD" , 1, 1, 41, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCS" , 2, 1, 41, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FORCE_FCS" , 3, 1, 41, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 41, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL_EN" , 0, 1, 42, "R/W", 0, 0, 1ull, 1ull},
|
|
{"XSDEF_EN" , 1, 1, 42, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 42, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_SIZE" , 0, 8, 43, "R/W", 0, 0, 59ull, 59ull},
|
|
{"RESERVED_8_63" , 8, 56, 43, "RAZ", 1, 1, 0, 0},
|
|
{"INTERVAL" , 0, 16, 44, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 44, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 45, "R/W", 0, 1, 96ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 45, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 46, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_16_63" , 16, 48, 46, "RAZ", 1, 1, 0, 0},
|
|
{"SEND" , 0, 1, 47, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 47, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 48, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 48, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL" , 0, 32, 49, "RC/W", 0, 1, 0ull, 0},
|
|
{"XSDEF" , 32, 32, 49, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCOL" , 0, 32, 50, "RC/W", 0, 1, 0ull, 0},
|
|
{"SCOL" , 32, 32, 50, "RC/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 51, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 51, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 52, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 52, "RAZ", 1, 1, 0, 0},
|
|
{"HIST0" , 0, 32, 53, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST1" , 32, 32, 53, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST2" , 0, 32, 54, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST3" , 32, 32, 54, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST4" , 0, 32, 55, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST5" , 32, 32, 55, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST6" , 0, 32, 56, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST7" , 32, 32, 56, "RC/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 0, 32, 57, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 32, 32, 57, "RC/W", 0, 1, 0ull, 0},
|
|
{"CTL" , 0, 32, 58, "RC/W", 0, 1, 0ull, 0},
|
|
{"UNDFLW" , 32, 32, 58, "RC/W", 0, 1, 0ull, 0},
|
|
{"RD_CLR" , 0, 1, 59, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 59, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 6, 60, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_6_63" , 6, 58, 60, "RAZ", 1, 1, 0, 0},
|
|
{"BP" , 0, 2, 61, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 61, "RAZ", 1, 1, 0, 0},
|
|
{"LIMIT" , 0, 5, 62, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_5_63" , 5, 59, 62, "RAZ", 1, 1, 0, 0},
|
|
{"IFG1" , 0, 4, 63, "R/W", 0, 1, 8ull, 0},
|
|
{"IFG2" , 4, 4, 63, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 63, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 64, "RAZ", 1, 1, 0, 0},
|
|
{"UNDFLW" , 2, 2, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 64, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL" , 8, 2, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_11" , 10, 2, 64, "RAZ", 1, 1, 0, 0},
|
|
{"XSDEF" , 12, 2, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_15" , 14, 2, 64, "RAZ", 1, 1, 0, 0},
|
|
{"LATE_COL" , 16, 2, 64, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 64, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 65, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 65, "RAZ", 1, 1, 0, 0},
|
|
{"UNDFLW" , 2, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 65, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL" , 8, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_11" , 10, 2, 65, "RAZ", 1, 1, 0, 0},
|
|
{"XSDEF" , 12, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_15" , 14, 2, 65, "RAZ", 1, 1, 0, 0},
|
|
{"LATE_COL" , 16, 2, 65, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 65, "RAZ", 1, 1, 0, 0},
|
|
{"JAM" , 0, 8, 66, "R/W", 0, 1, 238ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 66, "RAZ", 1, 1, 0, 0},
|
|
{"LFSR" , 0, 16, 67, "R/W", 0, 1, 65535ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 67, "RAZ", 1, 1, 0, 0},
|
|
{"IGN_FULL" , 0, 2, 68, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_3" , 2, 2, 68, "RAZ", 1, 1, 0, 0},
|
|
{"BP" , 4, 2, 68, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 68, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 8, 2, 68, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 68, "RAZ", 1, 1, 0, 0},
|
|
{"DMAC" , 0, 48, 69, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
|
|
{"RESERVED_48_63" , 48, 16, 69, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 70, "R/W", 0, 0, 34824ull, 34824ull},
|
|
{"RESERVED_16_63" , 16, 48, 70, "RAZ", 1, 1, 0, 0},
|
|
{"BIST" , 0, 3, 71, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 71, "RAZ", 1, 1, 0, 0},
|
|
{"DINT" , 0, 4, 72, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 72, "RAZ", 1, 1, 0, 0},
|
|
{"FUSE" , 0, 4, 73, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_4_63" , 4, 60, 73, "RAZ", 1, 1, 0, 0},
|
|
{"GSTOP" , 0, 1, 74, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 74, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 75, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_49" , 49, 1, 75, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_51_51" , 51, 1, 75, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_57_58" , 57, 2, 75, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TWSI2" , 59, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POWIQ" , 60, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPDPPTHR" , 61, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MII" , 62, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BOOTDMA" , 63, 1, 75, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WORKQ" , 0, 16, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 76, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_49" , 49, 1, 76, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_51_51" , 51, 1, 76, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_57_58" , 57, 2, 76, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TWSI2" , 59, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"POWIQ" , 60, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IPDPPTHR" , 61, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MII" , 62, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BOOTDMA" , 63, 1, 76, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WORKQ" , 0, 16, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 77, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_49" , 49, 1, 77, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_51_51" , 51, 1, 77, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_57_58" , 57, 2, 77, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TWSI2" , 59, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"POWIQ" , 60, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"IPDPPTHR" , 61, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"MII" , 62, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"BOOTDMA" , 63, 1, 77, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"WDOG" , 0, 4, 78, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_15" , 4, 12, 78, "RAZ", 1, 1, 0, 0},
|
|
{"UART2" , 16, 1, 78, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USB1" , 17, 1, 78, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MII1" , 18, 1, 78, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NAND" , 19, 1, 78, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 78, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 4, 79, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_15" , 4, 12, 79, "RAZ", 1, 1, 0, 0},
|
|
{"UART2" , 16, 1, 79, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USB1" , 17, 1, 79, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MII1" , 18, 1, 79, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NAND" , 19, 1, 79, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 79, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 4, 80, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_15" , 4, 12, 80, "RAZ", 1, 1, 0, 0},
|
|
{"UART2" , 16, 1, 80, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"USB1" , 17, 1, 80, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"MII1" , 18, 1, 80, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"NAND" , 19, 1, 80, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 80, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 81, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 1, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_49" , 49, 1, 81, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_51_51" , 51, 1, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_57_58" , 57, 2, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TWSI2" , 59, 1, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POWIQ" , 60, 1, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPDPPTHR" , 61, 1, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MII" , 62, 1, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BOOTDMA" , 63, 1, 81, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WORKQ" , 0, 16, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 82, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_49" , 49, 1, 82, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_51_51" , 51, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_57_58" , 57, 2, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TWSI2" , 59, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"POWIQ" , 60, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IPDPPTHR" , 61, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MII" , 62, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BOOTDMA" , 63, 1, 82, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WORKQ" , 0, 16, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_44" , 44, 1, 83, "RAZ", 1, 1, 0, 0},
|
|
{"TWSI" , 45, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_49" , 49, 1, 83, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_51_51" , 51, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_57_58" , 57, 2, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"TWSI2" , 59, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"POWIQ" , 60, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"IPDPPTHR" , 61, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"MII" , 62, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"BOOTDMA" , 63, 1, 83, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"WDOG" , 0, 4, 84, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_15" , 4, 12, 84, "RAZ", 1, 1, 0, 0},
|
|
{"UART2" , 16, 1, 84, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USB1" , 17, 1, 84, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MII1" , 18, 1, 84, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NAND" , 19, 1, 84, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 84, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 4, 85, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_15" , 4, 12, 85, "RAZ", 1, 1, 0, 0},
|
|
{"UART2" , 16, 1, 85, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USB1" , 17, 1, 85, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MII1" , 18, 1, 85, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NAND" , 19, 1, 85, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 85, "RAZ", 1, 1, 0, 0},
|
|
{"WDOG" , 0, 4, 86, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_15" , 4, 12, 86, "RAZ", 1, 1, 0, 0},
|
|
{"UART2" , 16, 1, 86, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"USB1" , 17, 1, 86, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"MII1" , 18, 1, 86, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"NAND" , 19, 1, 86, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 86, "RAZ", 1, 1, 0, 0},
|
|
{"WORKQ" , 0, 16, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"WDOG_SUM" , 44, 1, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"TWSI" , 45, 1, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_49" , 49, 1, 87, "RAZ", 1, 1, 0, 0},
|
|
{"IPD_DRP" , 50, 1, 87, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_51_51" , 51, 1, 87, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 87, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_57_58" , 57, 2, 87, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TWSI2" , 59, 1, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"POWIQ" , 60, 1, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPDPPTHR" , 61, 1, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"MII" , 62, 1, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"BOOTDMA" , 63, 1, 87, "RO", 0, 0, 0ull, 0ull},
|
|
{"WORKQ" , 0, 16, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"GPIO" , 16, 16, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"MBOX" , 32, 2, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"UART" , 34, 2, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_INT" , 36, 4, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCI_MSI" , 40, 4, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"WDOG_SUM" , 44, 1, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"TWSI" , 45, 1, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"RML" , 46, 1, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"TRACE" , 47, 1, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX_DRP" , 48, 1, 88, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_49" , 49, 1, 88, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IPD_DRP" , 50, 1, 88, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_51_51" , 51, 1, 88, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 52, 4, 88, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USB" , 56, 1, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_57_58" , 57, 2, 88, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"TWSI2" , 59, 1, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"POWIQ" , 60, 1, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPDPPTHR" , 61, 1, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"MII" , 62, 1, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"BOOTDMA" , 63, 1, 88, "RO", 0, 0, 0ull, 0ull},
|
|
{"WDOG" , 0, 4, 89, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_15" , 4, 12, 89, "RAZ", 1, 1, 0, 0},
|
|
{"UART2" , 16, 1, 89, "RO", 0, 0, 0ull, 0ull},
|
|
{"USB1" , 17, 1, 89, "RO", 0, 0, 0ull, 0ull},
|
|
{"MII1" , 18, 1, 89, "RO", 0, 0, 0ull, 0ull},
|
|
{"NAND" , 19, 1, 89, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 89, "RAZ", 1, 1, 0, 0},
|
|
{"BITS" , 0, 32, 90, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 90, "RAZ", 1, 1, 0, 0},
|
|
{"BITS" , 0, 32, 91, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 91, "RAZ", 1, 1, 0, 0},
|
|
{"NMI" , 0, 4, 92, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 92, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 0, 2, 93, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 93, "RAZ", 1, 1, 0, 0},
|
|
{"PPDBG" , 0, 4, 94, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 94, "RAZ", 1, 1, 0, 0},
|
|
{"POKE" , 0, 64, 95, "RAZ", 1, 1, 0, 0},
|
|
{"RST0" , 0, 1, 96, "R/W", 1, 1, 0, 0},
|
|
{"RST" , 1, 3, 96, "R/W", 0, 0, 32767ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 96, "RAZ", 1, 1, 0, 0},
|
|
{"QLM_DCOK" , 0, 2, 97, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 97, "RAZ", 1, 1, 0, 0},
|
|
{"BYPASS" , 0, 2, 98, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_3" , 2, 2, 98, "RAZ", 1, 1, 0, 0},
|
|
{"MUX_SEL" , 4, 1, 98, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 98, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_DIV" , 8, 3, 98, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_11_63" , 11, 53, 98, "RAZ", 1, 1, 0, 0},
|
|
{"SHFT_REG" , 0, 32, 99, "R/W", 0, 1, 0ull, 0},
|
|
{"SHFT_CNT" , 32, 5, 99, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_37_39" , 37, 3, 99, "RAZ", 1, 1, 0, 0},
|
|
{"SELECT" , 40, 2, 99, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_42_60" , 42, 19, 99, "RAZ", 1, 1, 0, 0},
|
|
{"UPDATE" , 61, 1, 99, "R/W", 0, 1, 0ull, 0},
|
|
{"SHIFT" , 62, 1, 99, "R/W", 0, 1, 0ull, 0},
|
|
{"CAPTURE" , 63, 1, 99, "R/W", 0, 1, 0ull, 0},
|
|
{"SOFT_BIST" , 0, 1, 100, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 100, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_PRST" , 0, 1, 101, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 101, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_PRST" , 0, 1, 102, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 102, "RAZ", 1, 1, 0, 0},
|
|
{"SOFT_RST" , 0, 1, 103, "WO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 103, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 36, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ONE_SHOT" , 36, 1, 104, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 104, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 0, 2, 105, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STATE" , 2, 2, 105, "RO", 0, 0, 0ull, 0ull},
|
|
{"LEN" , 4, 16, 105, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT" , 20, 24, 105, "RO", 0, 0, 0ull, 0ull},
|
|
{"DSTOP" , 44, 1, 105, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GSTOPEN" , 45, 1, 105, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_46_63" , 46, 18, 105, "RAZ", 1, 1, 0, 0},
|
|
{"FDR" , 0, 1, 106, "RO", 0, 0, 0ull, 0ull},
|
|
{"FFR" , 1, 1, 106, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPF1" , 2, 1, 106, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPF0" , 3, 1, 106, "RO", 0, 0, 0ull, 0ull},
|
|
{"FRD" , 4, 1, 106, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 106, "RAZ", 1, 1, 0, 0},
|
|
{"MEM0_ERR" , 0, 7, 107, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM1_ERR" , 7, 7, 107, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 14, 1, 107, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USE_STT" , 15, 1, 107, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USE_LDT" , 16, 1, 107, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 17, 1, 107, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 107, "RAZ", 1, 1, 0, 0},
|
|
{"FED0_SBE" , 0, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED0_DBE" , 1, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED1_SBE" , 2, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FED1_DBE" , 3, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_UND" , 4, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_COFF" , 5, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q0_PERR" , 6, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_UND" , 7, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_COFF" , 8, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q1_PERR" , 9, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_UND" , 10, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_COFF" , 11, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q2_PERR" , 12, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_UND" , 13, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_COFF" , 14, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q3_PERR" , 15, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_UND" , 16, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_COFF" , 17, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q4_PERR" , 18, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_UND" , 19, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_COFF" , 20, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q5_PERR" , 21, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_UND" , 22, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_COFF" , 23, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q6_PERR" , 24, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_UND" , 25, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_COFF" , 26, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"Q7_PERR" , 27, 1, 108, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 108, "RAZ", 1, 1, 0, 0},
|
|
{"FED0_SBE" , 0, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED0_DBE" , 1, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED1_SBE" , 2, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FED1_DBE" , 3, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_UND" , 4, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_COFF" , 5, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q0_PERR" , 6, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_UND" , 7, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_COFF" , 8, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q1_PERR" , 9, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_UND" , 10, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_COFF" , 11, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q2_PERR" , 12, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_UND" , 13, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_COFF" , 14, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q3_PERR" , 15, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_UND" , 16, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_COFF" , 17, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q4_PERR" , 18, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_UND" , 19, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_COFF" , 20, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q5_PERR" , 21, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_UND" , 22, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_COFF" , 23, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q6_PERR" , 24, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_UND" , 25, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_COFF" , 26, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"Q7_PERR" , 27, 1, 109, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_63" , 28, 36, 109, "RAZ", 1, 1, 0, 0},
|
|
{"QUE_SIZ" , 0, 29, 110, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 110, "RAZ", 1, 1, 0, 0},
|
|
{"PG_NUM" , 0, 25, 111, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 111, "RAZ", 1, 1, 0, 0},
|
|
{"ACT_INDX" , 0, 26, 112, "RO", 0, 1, 0ull, 0},
|
|
{"ACT_QUE" , 26, 3, 112, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 112, "RAZ", 0, 0, 0ull, 7ull},
|
|
{"EXP_INDX" , 0, 26, 113, "RO", 0, 1, 0ull, 0},
|
|
{"EXP_QUE" , 26, 3, 113, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 113, "RAZ", 0, 0, 0ull, 7ull},
|
|
{"CTL" , 0, 16, 114, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 114, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 32, 115, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 115, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 116, "RAZ", 1, 1, 0, 0},
|
|
{"OUT_OVR" , 2, 4, 116, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_21" , 6, 16, 116, "RAZ", 1, 1, 0, 0},
|
|
{"LOSTSTAT" , 22, 4, 116, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"STATOVR" , 26, 1, 116, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INB_NXA" , 27, 4, 116, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 116, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 16, 117, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 117, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_EN" , 0, 1, 118, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 118, "RAZ", 1, 1, 0, 0},
|
|
{"LOGL_EN" , 0, 16, 119, "R/W", 0, 1, 65535ull, 0},
|
|
{"PHYS_EN" , 16, 1, 119, "R/W", 0, 1, 1ull, 0},
|
|
{"HG2RX_EN" , 17, 1, 119, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HG2TX_EN" , 18, 1, 119, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 119, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 1, 120, "RO", 0, 1, 0ull, 0},
|
|
{"EN" , 1, 1, 120, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_3" , 2, 2, 120, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 4, 2, 120, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_7" , 6, 2, 120, "RAZ", 1, 1, 0, 0},
|
|
{"SPEED" , 8, 2, 120, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_10_63" , 10, 54, 120, "RAZ", 1, 1, 0, 0},
|
|
{"PRT" , 0, 6, 121, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 121, "RAZ", 1, 1, 0, 0},
|
|
{"RX_EN" , 0, 1, 122, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TX_EN" , 1, 1, 122, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRP_EN" , 2, 1, 122, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BCK_EN" , 3, 1, 122, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_15" , 4, 12, 122, "RAZ", 1, 1, 0, 0},
|
|
{"PHYS_BP" , 16, 16, 122, "R/W", 0, 1, 65535ull, 0},
|
|
{"LOGL_EN" , 32, 16, 122, "R/W", 0, 0, 255ull, 255ull},
|
|
{"PHYS_EN" , 48, 16, 122, "R/W", 0, 0, 255ull, 255ull},
|
|
{"EN" , 0, 1, 123, "R/W", 0, 1, 0ull, 0},
|
|
{"SPEED" , 1, 1, 123, "R/W", 0, 1, 1ull, 0},
|
|
{"DUPLEX" , 2, 1, 123, "R/W", 0, 1, 1ull, 0},
|
|
{"SLOTTIME" , 3, 1, 123, "R/W", 0, 1, 1ull, 0},
|
|
{"RESERVED_4_7" , 4, 4, 123, "RAZ", 1, 1, 0, 0},
|
|
{"SPEED_MSB" , 8, 1, 123, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_9_11" , 9, 3, 123, "RAZ", 1, 1, 0, 0},
|
|
{"RX_IDLE" , 12, 1, 123, "RO", 0, 1, 1ull, 0},
|
|
{"TX_IDLE" , 13, 1, 123, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_14_63" , 14, 50, 123, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 64, 124, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 125, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 126, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 127, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 128, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR" , 0, 64, 129, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 0, 8, 130, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 130, "RAZ", 1, 1, 0, 0},
|
|
{"BCST" , 0, 1, 131, "R/W", 0, 1, 1ull, 0},
|
|
{"MCST" , 1, 2, 131, "R/W", 0, 1, 0ull, 0},
|
|
{"CAM_MODE" , 3, 1, 131, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 131, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 5, 132, "R/W", 0, 0, 24ull, 24ull},
|
|
{"RESERVED_5_63" , 5, 59, 132, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 133, "RAZ", 1, 1, 0, 0},
|
|
{"CAREXT" , 1, 1, 133, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_2" , 2, 1, 133, "RAZ", 1, 1, 0, 0},
|
|
{"JABBER" , 3, 1, 133, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCSERR" , 4, 1, 133, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_5_6" , 5, 2, 133, "RAZ", 1, 1, 0, 0},
|
|
{"RCVERR" , 7, 1, 133, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SKPERR" , 8, 1, 133, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_9_63" , 9, 55, 133, "RAZ", 1, 1, 0, 0},
|
|
{"PRE_CHK" , 0, 1, 134, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PRE_STRP" , 1, 1, 134, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_DRP" , 2, 1, 134, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_BCK" , 3, 1, 134, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_MCST" , 4, 1, 134, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTL_SMAC" , 5, 1, 134, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRE_FREE" , 6, 1, 134, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_7_8" , 7, 2, 134, "RAZ", 1, 1, 0, 0},
|
|
{"PRE_ALIGN" , 9, 1, 134, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NULL_DIS" , 10, 1, 134, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 134, "RAZ", 1, 1, 0, 0},
|
|
{"IFG" , 0, 4, 135, "R/W", 0, 0, 8ull, 8ull},
|
|
{"RESERVED_4_63" , 4, 60, 135, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 136, "RAZ", 1, 1, 0, 0},
|
|
{"CAREXT" , 1, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 136, "RAZ", 1, 1, 0, 0},
|
|
{"JABBER" , 3, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_6" , 5, 2, 136, "RAZ", 1, 1, 0, 0},
|
|
{"RCVERR" , 7, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 136, "RAZ", 1, 1, 0, 0},
|
|
{"OVRERR" , 10, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_18" , 16, 3, 136, "RAZ", 1, 1, 0, 0},
|
|
{"PAUSE_DRP" , 19, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LOC_FAULT" , 20, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"REM_FAULT" , 21, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAD_SEQ" , 22, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAD_TERM" , 23, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UNSOP" , 24, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UNEOP" , 25, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UNDAT" , 26, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HG2FLD" , 27, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HG2CC" , 28, 1, 136, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 136, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 137, "RAZ", 1, 1, 0, 0},
|
|
{"CAREXT" , 1, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 137, "RAZ", 1, 1, 0, 0},
|
|
{"JABBER" , 3, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCSERR" , 4, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_6" , 5, 2, 137, "RAZ", 1, 1, 0, 0},
|
|
{"RCVERR" , 7, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPERR" , 8, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 137, "RAZ", 1, 1, 0, 0},
|
|
{"OVRERR" , 10, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCTERR" , 11, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RSVERR" , 12, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FALERR" , 13, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"COLDET" , 14, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IFGERR" , 15, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_18" , 16, 3, 137, "RAZ", 1, 1, 0, 0},
|
|
{"PAUSE_DRP" , 19, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LOC_FAULT" , 20, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"REM_FAULT" , 21, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BAD_SEQ" , 22, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BAD_TERM" , 23, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UNSOP" , 24, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UNEOP" , 25, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UNDAT" , 26, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"HG2FLD" , 27, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"HG2CC" , 28, 1, 137, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 137, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 138, "R/W", 0, 0, 10240ull, 10240ull},
|
|
{"RESERVED_16_63" , 16, 48, 138, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 16, 139, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 139, "RAZ", 1, 1, 0, 0},
|
|
{"RD_CLR" , 0, 1, 140, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 140, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 141, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 141, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 142, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 142, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 143, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 143, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 48, 144, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 144, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 145, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 145, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 146, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 146, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 147, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 147, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 148, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 148, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 149, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 149, "RAZ", 1, 1, 0, 0},
|
|
{"LEN" , 0, 7, 150, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 150, "RAZ", 1, 1, 0, 0},
|
|
{"FCSSEL" , 8, 1, 150, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 150, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 151, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_6_63" , 6, 58, 151, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 6, 152, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_6_63" , 6, 58, 152, "RAZ", 1, 1, 0, 0},
|
|
{"MARK" , 0, 9, 153, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_9_63" , 9, 55, 153, "RAZ", 1, 1, 0, 0},
|
|
{"LGTIM2GO" , 0, 16, 154, "RO", 0, 1, 0ull, 0},
|
|
{"XOF" , 16, 16, 154, "RO", 0, 0, 0ull, 0ull},
|
|
{"PHTIM2GO" , 32, 16, 154, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 154, "RAZ", 1, 1, 0, 0},
|
|
{"COMMIT" , 0, 4, 155, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_15" , 4, 12, 155, "RAZ", 1, 1, 0, 0},
|
|
{"DROP" , 16, 4, 155, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 155, "RAZ", 1, 1, 0, 0},
|
|
{"PRTS" , 0, 3, 156, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_3_63" , 3, 61, 156, "RAZ", 1, 1, 0, 0},
|
|
{"LANE_RXD" , 0, 32, 157, "RO", 0, 1, 0ull, 0},
|
|
{"LANE_RXC" , 32, 4, 157, "RO", 0, 1, 0ull, 0},
|
|
{"STATE" , 36, 3, 157, "RO", 0, 1, 0ull, 0},
|
|
{"VAL" , 39, 1, 157, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_40_63" , 40, 24, 157, "RAZ", 1, 1, 0, 0},
|
|
{"STATUS" , 0, 2, 158, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 158, "RAZ", 1, 1, 0, 0},
|
|
{"SMAC" , 0, 48, 159, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 159, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 16, 160, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP" , 16, 1, 160, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_63" , 17, 47, 160, "RAZ", 1, 1, 0, 0},
|
|
{"PREAMBLE" , 0, 1, 161, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PAD" , 1, 1, 161, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FCS" , 2, 1, 161, "R/W", 0, 0, 1ull, 1ull},
|
|
{"FORCE_FCS" , 3, 1, 161, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_63" , 4, 60, 161, "RAZ", 1, 1, 0, 0},
|
|
{"BURST" , 0, 16, 162, "R/W", 0, 0, 8192ull, 8192ull},
|
|
{"RESERVED_16_63" , 16, 48, 162, "RAZ", 1, 1, 0, 0},
|
|
{"XOFF" , 0, 16, 163, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 163, "RAZ", 1, 1, 0, 0},
|
|
{"XON" , 0, 16, 164, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 164, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL_EN" , 0, 1, 165, "R/W", 0, 0, 1ull, 1ull},
|
|
{"XSDEF_EN" , 1, 1, 165, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 165, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_SIZE" , 0, 8, 166, "R/W", 0, 0, 59ull, 59ull},
|
|
{"RESERVED_8_63" , 8, 56, 166, "RAZ", 1, 1, 0, 0},
|
|
{"INTERVAL" , 0, 16, 167, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 167, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 168, "R/W", 0, 1, 96ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 168, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 169, "RO", 1, 1, 0, 0},
|
|
{"MSG_TIME" , 16, 16, 169, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 169, "RAZ", 1, 1, 0, 0},
|
|
{"SEND" , 0, 1, 170, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 170, "RAZ", 1, 1, 0, 0},
|
|
{"ALIGN" , 0, 1, 171, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 171, "RAZ", 1, 1, 0, 0},
|
|
{"SLOT" , 0, 10, 172, "R/W", 0, 0, 512ull, 512ull},
|
|
{"RESERVED_10_63" , 10, 54, 172, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 16, 173, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 173, "RAZ", 1, 1, 0, 0},
|
|
{"XSCOL" , 0, 32, 174, "RC/W", 0, 1, 0ull, 0},
|
|
{"XSDEF" , 32, 32, 174, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCOL" , 0, 32, 175, "RC/W", 0, 1, 0ull, 0},
|
|
{"SCOL" , 32, 32, 175, "RC/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 176, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 176, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 177, "RC/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 177, "RAZ", 1, 1, 0, 0},
|
|
{"HIST0" , 0, 32, 178, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST1" , 32, 32, 178, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST2" , 0, 32, 179, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST3" , 32, 32, 179, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST4" , 0, 32, 180, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST5" , 32, 32, 180, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST6" , 0, 32, 181, "RC/W", 0, 1, 0ull, 0},
|
|
{"HIST7" , 32, 32, 181, "RC/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 0, 32, 182, "RC/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 32, 32, 182, "RC/W", 0, 1, 0ull, 0},
|
|
{"CTL" , 0, 32, 183, "RC/W", 0, 1, 0ull, 0},
|
|
{"UNDFLW" , 32, 32, 183, "RC/W", 0, 1, 0ull, 0},
|
|
{"RD_CLR" , 0, 1, 184, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 184, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 9, 185, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_9_63" , 9, 55, 185, "RAZ", 1, 1, 0, 0},
|
|
{"BP" , 0, 4, 186, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 186, "RAZ", 1, 1, 0, 0},
|
|
{"LIMIT" , 0, 5, 187, "R/W", 0, 0, 16ull, 16ull},
|
|
{"RESERVED_5_63" , 5, 59, 187, "RAZ", 1, 1, 0, 0},
|
|
{"CORRUPT" , 0, 4, 188, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_4_63" , 4, 60, 188, "RAZ", 1, 1, 0, 0},
|
|
{"TX_XOF" , 0, 16, 189, "R/W1", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 189, "RAZ", 1, 1, 0, 0},
|
|
{"TX_XON" , 0, 16, 190, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 190, "RAZ", 1, 1, 0, 0},
|
|
{"IFG1" , 0, 4, 191, "R/W", 0, 1, 8ull, 0},
|
|
{"IFG2" , 4, 4, 191, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 191, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 192, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 192, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 4, 192, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 192, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 4, 192, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 4, 192, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LATE_COL" , 16, 4, 192, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 192, "RAZ", 1, 1, 0, 0},
|
|
{"PKO_NXA" , 0, 1, 193, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 193, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UNDFLW" , 2, 4, 193, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 193, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XSCOL" , 8, 4, 193, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"XSDEF" , 12, 4, 193, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LATE_COL" , 16, 4, 193, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 193, "RAZ", 1, 1, 0, 0},
|
|
{"JAM" , 0, 8, 194, "R/W", 0, 1, 238ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 194, "RAZ", 1, 1, 0, 0},
|
|
{"LFSR" , 0, 16, 195, "R/W", 0, 1, 65535ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 195, "RAZ", 1, 1, 0, 0},
|
|
{"IGN_FULL" , 0, 4, 196, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP" , 4, 4, 196, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EN" , 8, 4, 196, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_31" , 12, 20, 196, "RAZ", 1, 1, 0, 0},
|
|
{"TX_PRT_BP" , 32, 16, 196, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 196, "RAZ", 1, 1, 0, 0},
|
|
{"DMAC" , 0, 48, 197, "R/W", 0, 0, 1652522221569ull, 1652522221569ull},
|
|
{"RESERVED_48_63" , 48, 16, 197, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 198, "R/W", 0, 0, 34824ull, 34824ull},
|
|
{"RESERVED_16_63" , 16, 48, 198, "RAZ", 1, 1, 0, 0},
|
|
{"PRTS" , 0, 5, 199, "R/W", 0, 1, 4ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 199, "RAZ", 1, 1, 0, 0},
|
|
{"DIC_EN" , 0, 1, 200, "R/W", 0, 0, 0ull, 1ull},
|
|
{"UNI_EN" , 1, 1, 200, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_3" , 2, 2, 200, "RAZ", 1, 1, 0, 0},
|
|
{"LS" , 4, 2, 200, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LS_BYP" , 6, 1, 200, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 200, "RAZ", 1, 1, 0, 0},
|
|
{"HG_EN" , 8, 1, 200, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HG_PAUSE_HGI" , 9, 2, 200, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_11_63" , 11, 53, 200, "RAZ", 1, 1, 0, 0},
|
|
{"THRESH" , 0, 4, 201, "R/W", 0, 0, 6ull, 6ull},
|
|
{"EN" , 4, 1, 201, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 201, "RAZ", 1, 1, 0, 0},
|
|
{"TX_OE" , 0, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RX_XOR" , 1, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_EN" , 2, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INT_TYPE" , 3, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_CNT" , 4, 4, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIL_SEL" , 8, 4, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLK_SEL" , 12, 2, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLK_GEN" , 14, 1, 202, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 202, "RAZ", 1, 1, 0, 0},
|
|
{"N" , 0, 32, 203, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 203, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 16, 204, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 204, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 205, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 205, "RAZ", 1, 1, 0, 0},
|
|
{"CLR" , 0, 16, 206, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 206, "RAZ", 1, 1, 0, 0},
|
|
{"SET" , 0, 16, 207, "R/W1", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 207, "RAZ", 1, 1, 0, 0},
|
|
{"ICD" , 0, 1, 208, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBD" , 1, 1, 208, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRP1" , 2, 1, 208, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRP0" , 3, 1, 208, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRN1" , 4, 1, 208, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICRN0" , 5, 1, 208, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBRQ1" , 6, 1, 208, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBRQ0" , 7, 1, 208, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNRT" , 8, 1, 208, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBR1" , 9, 1, 208, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBR0" , 10, 1, 208, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBDR1" , 11, 1, 208, "RO", 0, 0, 0ull, 0ull},
|
|
{"IBDR0" , 12, 1, 208, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNR0" , 13, 1, 208, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNR1" , 14, 1, 208, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICR1" , 15, 1, 208, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICR0" , 16, 1, 208, "RO", 0, 0, 0ull, 0ull},
|
|
{"ICNRCB" , 17, 1, 208, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 208, "RAZ", 1, 1, 0, 0},
|
|
{"FAU_END" , 0, 1, 209, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB_ENB" , 1, 1, 209, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PKO_ENB" , 2, 1, 209, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INB_MAT" , 3, 1, 209, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OUTB_MAT" , 4, 1, 209, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RR_MODE" , 5, 1, 209, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 209, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 210, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 210, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 210, "RAZ", 1, 1, 0, 0},
|
|
{"TOUT_VAL" , 0, 12, 211, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TOUT_ENB" , 12, 1, 211, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 211, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 212, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 212, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 212, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 8, 213, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 8, 9, 213, "R/W", 0, 1, 0ull, 0},
|
|
{"OPC" , 17, 4, 213, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 21, 8, 213, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 213, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 8, 214, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 8, 9, 214, "R/W", 0, 1, 0ull, 0},
|
|
{"OPC" , 17, 4, 214, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 21, 8, 214, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 214, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 215, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 216, "R/W", 0, 1, 0ull, 0},
|
|
{"NP_SOP" , 0, 1, 217, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NP_EOP" , 1, 1, 217, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_SOP" , 2, 1, 217, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_EOP" , 3, 1, 217, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NP_DAT" , 4, 1, 217, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_DAT" , 5, 1, 217, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 217, "RAZ", 1, 1, 0, 0},
|
|
{"NP_SOP" , 0, 1, 218, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NP_EOP" , 1, 1, 218, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_SOP" , 2, 1, 218, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_EOP" , 3, 1, 218, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NP_DAT" , 4, 1, 218, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P_DAT" , 5, 1, 218, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 218, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 219, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 219, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 219, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 220, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 220, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 220, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 221, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 221, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 221, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 9, 222, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 9, 8, 222, "R/W", 0, 1, 0ull, 0},
|
|
{"EOT" , 17, 1, 222, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 18, 8, 222, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_26_63" , 26, 38, 222, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 9, 223, "R/W", 0, 1, 0ull, 0},
|
|
{"DST" , 9, 8, 223, "R/W", 0, 1, 0ull, 0},
|
|
{"EOT" , 17, 1, 223, "R/W", 0, 1, 0ull, 0},
|
|
{"MASK" , 18, 8, 223, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_26_63" , 26, 38, 223, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 224, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 225, "R/W", 0, 1, 0ull, 0},
|
|
{"CNT_VAL" , 0, 15, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 226, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 226, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 227, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 227, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 227, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 15, 228, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT_ENB" , 15, 1, 228, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 228, "RAZ", 1, 1, 0, 0},
|
|
{"PORT" , 0, 6, 229, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 229, "RAZ", 1, 1, 0, 0},
|
|
{"NCB_WR" , 0, 3, 230, "R/W", 0, 1, 0ull, 0},
|
|
{"NCB_RD" , 3, 3, 230, "R/W", 0, 1, 0ull, 0},
|
|
{"PKO_RD" , 6, 3, 230, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_9_63" , 9, 55, 230, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP_SZ" , 0, 6, 231, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 231, "RAZ", 1, 1, 0, 0},
|
|
{"BACK" , 0, 4, 232, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 232, "RAZ", 1, 1, 0, 0},
|
|
{"BACK" , 0, 4, 233, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 233, "RAZ", 1, 1, 0, 0},
|
|
{"PWP" , 0, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_NEW" , 1, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_OLD" , 2, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRC_OFF" , 3, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ0" , 4, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ1" , 5, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM_WORD" , 6, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM0" , 7, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM1" , 8, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM2" , 9, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"PBM3" , 10, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPQ_PBE0" , 11, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPQ_PBE1" , 12, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_POW" , 13, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_WP1" , 14, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"PWQ_WQED" , 15, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSR_NCMD" , 16, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSR_MEM" , 17, 1, 234, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 234, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_ENB" , 0, 40, 235, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 235, "RAZ", 1, 1, 0, 0},
|
|
{"CLK_CNT" , 0, 64, 236, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPD_EN" , 0, 1, 237, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OPC_MODE" , 1, 2, 237, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PBP_EN" , 3, 1, 237, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WQE_LEND" , 4, 1, 237, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKT_LEND" , 5, 1, 237, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NADDBUF" , 6, 1, 237, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDPKT" , 7, 1, 237, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 8, 1, 237, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LEN_M8" , 9, 1, 237, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PKT_OFF" , 10, 1, 237, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IPD_FULL" , 11, 1, 237, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PQ_NABUF" , 12, 1, 237, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PQ_APKT" , 13, 1, 237, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NO_WPTR" , 14, 1, 237, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 237, "RAZ", 1, 1, 0, 0},
|
|
{"PRC_PAR0" , 0, 1, 238, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR1" , 1, 1, 238, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR2" , 2, 1, 238, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR3" , 3, 1, 238, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_SUB" , 4, 1, 238, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DC_OVR" , 5, 1, 238, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CC_OVR" , 6, 1, 238, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C_COLL" , 7, 1, 238, "R/W", 0, 0, 0ull, 0ull},
|
|
{"D_COLL" , 8, 1, 238, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BC_OVR" , 9, 1, 238, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PQ_ADD" , 10, 1, 238, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PQ_SUB" , 11, 1, 238, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 238, "RAZ", 1, 1, 0, 0},
|
|
{"PRC_PAR0" , 0, 1, 239, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR1" , 1, 1, 239, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR2" , 2, 1, 239, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRC_PAR3" , 3, 1, 239, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BP_SUB" , 4, 1, 239, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DC_OVR" , 5, 1, 239, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CC_OVR" , 6, 1, 239, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C_COLL" , 7, 1, 239, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"D_COLL" , 8, 1, 239, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BC_OVR" , 9, 1, 239, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PQ_ADD" , 10, 1, 239, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PQ_SUB" , 11, 1, 239, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 239, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP_SZ" , 0, 6, 240, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 240, "RAZ", 1, 1, 0, 0},
|
|
{"MB_SIZE" , 0, 12, 241, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_12_63" , 12, 52, 241, "RAZ", 1, 1, 0, 0},
|
|
{"PTR" , 0, 29, 242, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 242, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 17, 243, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_ENB" , 17, 1, 243, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 243, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 17, 244, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BP_ENB" , 17, 1, 244, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 244, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 25, 245, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 245, "RAZ", 1, 1, 0, 0},
|
|
{"CNT_VAL" , 0, 25, 246, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_25_63" , 25, 39, 246, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 247, "RO", 0, 1, 0ull, 0},
|
|
{"WMARK" , 32, 32, 247, "R/W", 0, 1, 4294967295ull, 0},
|
|
{"INTR" , 0, 64, 248, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 0, 64, 249, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RADDR" , 0, 3, 250, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 3, 1, 250, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 4, 29, 250, "RO", 1, 1, 0, 0},
|
|
{"PRADDR" , 33, 3, 250, "RO", 1, 1, 0, 0},
|
|
{"MAX_PKT" , 36, 3, 250, "RO", 0, 0, 5ull, 5ull},
|
|
{"RESERVED_39_63" , 39, 25, 250, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 7, 251, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 7, 1, 251, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 8, 29, 251, "RO", 1, 1, 0, 0},
|
|
{"MAX_PKT" , 37, 7, 251, "RO", 0, 0, 12ull, 12ull},
|
|
{"RESERVED_44_63" , 44, 20, 251, "RAZ", 1, 1, 0, 0},
|
|
{"WQE_PCNT" , 0, 7, 252, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_PCNT" , 7, 7, 252, "RO", 0, 0, 0ull, 0ull},
|
|
{"PFIF_CNT" , 14, 3, 252, "RO", 0, 0, 0ull, 0ull},
|
|
{"WQEV_CNT" , 17, 1, 252, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTV_CNT" , 18, 1, 252, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 252, "RAZ", 1, 1, 0, 0},
|
|
{"RADDR" , 0, 8, 253, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CENA" , 8, 1, 253, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PTR" , 9, 29, 253, "RO", 1, 1, 0, 0},
|
|
{"PRADDR" , 38, 8, 253, "RO", 1, 1, 0, 0},
|
|
{"WRADDR" , 46, 8, 253, "RO", 1, 1, 0, 0},
|
|
{"MAX_CNTS" , 54, 7, 253, "RO", 0, 0, 8ull, 8ull},
|
|
{"RESERVED_61_63" , 61, 3, 253, "RAZ", 1, 1, 0, 0},
|
|
{"PASS" , 0, 32, 254, "R/W", 0, 1, 0ull, 0},
|
|
{"DROP" , 32, 32, 254, "R/W", 0, 1, 0ull, 0},
|
|
{"Q0_PCNT" , 0, 32, 255, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 255, "RAZ", 1, 1, 0, 0},
|
|
{"PRT_ENB" , 0, 36, 256, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AVG_DLY" , 36, 14, 256, "R/W", 0, 1, 0ull, 0},
|
|
{"PRB_DLY" , 50, 14, 256, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRT_ENB" , 0, 4, 257, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 257, "RAZ", 1, 1, 0, 0},
|
|
{"PRB_CON" , 0, 32, 258, "R/W", 0, 1, 0ull, 0},
|
|
{"AVG_CON" , 32, 8, 258, "R/W", 0, 1, 0ull, 0},
|
|
{"NEW_CON" , 40, 8, 258, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_PCNT" , 48, 1, 258, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 258, "RAZ", 1, 1, 0, 0},
|
|
{"PAGE_CNT" , 0, 25, 259, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT" , 25, 6, 259, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 259, "RAZ", 1, 1, 0, 0},
|
|
{"PORT_BIT" , 0, 32, 260, "R/W", 0, 0, 4294967295ull, 4294967295ull},
|
|
{"RESERVED_32_35" , 32, 4, 260, "RAZ", 1, 1, 0, 0},
|
|
{"PORT_BIT2" , 36, 4, 260, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_40_63" , 40, 24, 260, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 261, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT_QOS" , 32, 9, 261, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_41_63" , 41, 23, 261, "RAZ", 1, 1, 0, 0},
|
|
{"WQE_POOL" , 0, 3, 262, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_3_63" , 3, 61, 262, "RAZ", 1, 1, 0, 0},
|
|
{"PTR" , 0, 29, 263, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 263, "RAZ", 1, 1, 0, 0},
|
|
{"WLB_DAT" , 0, 4, 264, "RO", 0, 0, 0ull, 0ull},
|
|
{"STIN_MSK" , 4, 1, 264, "RO", 0, 0, 0ull, 0ull},
|
|
{"DT" , 5, 1, 264, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTCNT" , 6, 10, 264, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_18" , 16, 3, 264, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WLB_MSK" , 19, 4, 264, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTBNK" , 23, 1, 264, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 264, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"L2T" , 0, 9, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"VAB_VWCF" , 9, 1, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"ILC" , 10, 1, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_11" , 11, 1, 265, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VWDF" , 12, 4, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"PLC0" , 16, 1, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"PLC1" , 17, 1, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"PLC2" , 18, 1, 265, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 265, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"XRDDAT" , 0, 1, 266, "RO", 0, 0, 0ull, 0ull},
|
|
{"XRDMSK" , 1, 1, 266, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 266, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IPCBST" , 3, 1, 266, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 266, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RMDF" , 8, 4, 266, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRB" , 12, 4, 266, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 266, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LRF_ARB_MODE" , 0, 1, 267, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RFB_ARB_MODE" , 1, 1, 267, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RSP_ARB_MODE" , 2, 1, 267, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MWF_CRD" , 3, 4, 267, "R/W", 0, 0, 2ull, 2ull},
|
|
{"IDXALIAS" , 7, 1, 267, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPEN" , 8, 1, 267, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FPEMPTY" , 9, 1, 267, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FPEXP" , 10, 4, 267, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_17" , 14, 4, 267, "RAZ", 1, 1, 0, 0},
|
|
{"LBIST" , 18, 1, 267, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BSTRUN" , 19, 1, 267, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 267, "RAZ", 1, 1, 0, 0},
|
|
{"L2T" , 0, 1, 268, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2D" , 1, 1, 268, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FINV" , 2, 1, 268, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SET" , 3, 3, 268, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PPNUM" , 6, 2, 268, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_9" , 8, 2, 268, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_DMP" , 10, 1, 268, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LFB_ENUM" , 11, 3, 268, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 268, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DT_TAG" , 0, 29, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"DT_VLD" , 29, 1, 269, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_30" , 30, 1, 269, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DTENA" , 31, 1, 269, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 269, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PLC0RMSK" , 0, 32, 270, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PLC1RMSK" , 32, 32, 270, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PLC2RMSK" , 0, 32, 271, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ILCRMSK" , 32, 32, 271, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OOB1EN" , 0, 1, 272, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OOB2EN" , 1, 1, 272, "R/W", 0, 0, 0ull, 1ull},
|
|
{"OOB3EN" , 2, 1, 272, "R/W", 0, 0, 0ull, 1ull},
|
|
{"L2TSECEN" , 3, 1, 272, "R/W", 0, 0, 0ull, 1ull},
|
|
{"L2TDEDEN" , 4, 1, 272, "R/W", 0, 0, 0ull, 1ull},
|
|
{"L2DSECEN" , 5, 1, 272, "R/W", 0, 0, 0ull, 1ull},
|
|
{"L2DDEDEN" , 6, 1, 272, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LCKENA" , 7, 1, 272, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LCK2ENA" , 8, 1, 272, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_9_63" , 9, 55, 272, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OOB1" , 0, 1, 273, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OOB2" , 1, 1, 273, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OOB3" , 2, 1, 273, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"L2TSEC" , 3, 1, 273, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"L2TDED" , 4, 1, 273, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"L2DSEC" , 5, 1, 273, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"L2DDED" , 6, 1, 273, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK" , 7, 1, 273, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK2" , 8, 1, 273, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 273, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_ENA" , 0, 1, 274, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_3" , 1, 3, 274, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_BASE" , 4, 27, 274, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 274, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LCK_OFFSET" , 0, 10, 275, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 275, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VLD" , 0, 1, 276, "RO", 0, 0, 0ull, 0ull},
|
|
{"CMD" , 1, 4, 276, "RO", 0, 0, 0ull, 0ull},
|
|
{"SID" , 5, 9, 276, "RO", 0, 0, 0ull, 0ull},
|
|
{"VABNUM" , 14, 3, 276, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_17" , 17, 1, 276, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SET" , 18, 3, 276, "RO", 0, 0, 0ull, 0ull},
|
|
{"IHD" , 21, 1, 276, "RO", 0, 0, 0ull, 0ull},
|
|
{"ITL" , 22, 1, 276, "RO", 0, 0, 0ull, 0ull},
|
|
{"INXT" , 23, 3, 276, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_26" , 26, 1, 276, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VAM" , 27, 1, 276, "RO", 0, 0, 0ull, 0ull},
|
|
{"STCFL" , 28, 1, 276, "RO", 0, 0, 0ull, 0ull},
|
|
{"STINV" , 29, 1, 276, "RO", 0, 0, 0ull, 0ull},
|
|
{"STPND" , 30, 1, 276, "RO", 0, 0, 0ull, 0ull},
|
|
{"STCPND" , 31, 1, 276, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 276, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"VLD" , 0, 1, 277, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTPRB" , 1, 1, 277, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRBRTY" , 2, 1, 277, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTMFL" , 3, 1, 277, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTVTM" , 4, 1, 277, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTRSC" , 5, 1, 277, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTRSP" , 6, 1, 277, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTDT" , 7, 1, 277, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTRDA" , 8, 1, 277, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTSTM" , 9, 1, 277, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWRM" , 10, 1, 277, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWHF" , 11, 1, 277, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTWHP" , 12, 1, 277, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTDQ" , 13, 1, 277, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTDW" , 14, 1, 277, "RO", 0, 0, 0ull, 0ull},
|
|
{"WTRSP" , 15, 1, 277, "RO", 0, 0, 0ull, 0ull},
|
|
{"BID" , 16, 2, 277, "RO", 0, 0, 0ull, 0ull},
|
|
{"DSGOING" , 18, 1, 277, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 277, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_IDX" , 0, 9, 278, "RO", 0, 0, 0ull, 0ull},
|
|
{"LFB_TAG" , 9, 18, 278, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_63" , 27, 37, 278, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LFB_HWM" , 0, 3, 279, "R/W", 0, 0, 7ull, 7ull},
|
|
{"RESERVED_3_3" , 3, 1, 279, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STPARTDIS" , 4, 1, 279, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_63" , 5, 59, 279, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STENA" , 0, 1, 280, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWBENA" , 1, 1, 280, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 280, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 0, 14, 281, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_19" , 14, 6, 281, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SADR" , 20, 14, 281, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_35" , 34, 2, 281, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSRC" , 36, 1, 281, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 37, 27, 281, "RO", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 0, 14, 282, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_19" , 14, 6, 282, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SADR" , 20, 14, 282, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_35" , 34, 2, 282, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSRC" , 36, 1, 282, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 37, 27, 282, "RO", 0, 0, 0ull, 0ull},
|
|
{"SIZE" , 0, 14, 283, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_19" , 14, 6, 283, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SADR" , 20, 14, 283, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_35" , 34, 2, 283, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSRC" , 36, 1, 283, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 37, 27, 283, "RO", 0, 0, 0ull, 0ull},
|
|
{"PFCNT0" , 0, 36, 284, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 284, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CNT0SEL" , 0, 6, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0CLR" , 6, 1, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0ENA" , 7, 1, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1SEL" , 8, 6, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1CLR" , 14, 1, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1ENA" , 15, 1, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2SEL" , 16, 6, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2CLR" , 22, 1, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2ENA" , 23, 1, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3SEL" , 24, 6, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3CLR" , 30, 1, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3ENA" , 31, 1, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT0RDCLR" , 32, 1, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT1RDCLR" , 33, 1, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT2RDCLR" , 34, 1, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNT3RDCLR" , 35, 1, 285, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 285, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP0GRP" , 0, 2, 286, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP1GRP" , 2, 2, 286, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP2GRP" , 4, 2, 286, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PP3GRP" , 6, 2, 286, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 286, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSK0" , 0, 8, 287, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK1" , 8, 8, 287, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK2" , 16, 8, 287, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSK3" , 24, 8, 287, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 287, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"UMSKIOB" , 0, 8, 288, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 288, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q0STAT" , 0, 34, 289, "RO", 0, 0, 0ull, 0ull},
|
|
{"FTL" , 34, 1, 289, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_35_63" , 35, 29, 289, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q1STAT" , 0, 34, 290, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 290, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q2STAT" , 0, 34, 291, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 291, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q3STAT" , 0, 34, 292, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 292, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 0, 1, 293, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_INTENA" , 1, 1, 293, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DED_INTENA" , 2, 1, 293, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 3, 1, 293, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 4, 1, 293, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BMHCLSEL" , 5, 1, 293, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 293, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 0, 10, 294, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_10" , 10, 1, 294, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSET" , 11, 3, 294, "RO", 0, 0, 0ull, 0ull},
|
|
{"FOWMSK" , 14, 4, 294, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 294, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW0" , 0, 10, 295, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW1" , 10, 10, 295, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 295, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW2" , 0, 10, 296, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSYN_OW3" , 10, 10, 296, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 296, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q0FUS" , 0, 34, 297, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 297, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q1FUS" , 0, 34, 298, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 298, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q2FUS" , 0, 34, 299, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_34_63" , 34, 30, 299, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"Q3FUS" , 0, 34, 300, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRIP_256K" , 34, 1, 300, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRIP_128K" , 35, 1, 300, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_36" , 36, 1, 300, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EMA_CTL" , 37, 3, 300, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 300, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 0, 1, 301, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_INTENA" , 1, 1, 301, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DED_INTENA" , 2, 1, 301, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 3, 1, 301, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 4, 1, 301, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FSYN" , 5, 6, 301, "RO", 0, 0, 0ull, 0ull},
|
|
{"FADR" , 11, 9, 301, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 301, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FSET" , 21, 3, 301, "RO", 0, 0, 0ull, 0ull},
|
|
{"LCKERR" , 24, 1, 301, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK_INTENA" , 25, 1, 301, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LCKERR2" , 26, 1, 301, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LCK_INTENA2" , 27, 1, 301, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_28_63" , 28, 36, 301, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"START" , 0, 1, 302, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 302, "RAZ", 1, 0, 0, 0ull},
|
|
{"MRD" , 0, 3, 303, "RO", 1, 0, 0, 0ull},
|
|
{"MRF" , 3, 1, 303, "RO", 1, 0, 0, 0ull},
|
|
{"MWC" , 4, 1, 303, "RO", 1, 0, 0, 0ull},
|
|
{"MWD" , 5, 3, 303, "RO", 1, 0, 0, 0ull},
|
|
{"MWF" , 8, 1, 303, "RO", 1, 0, 0, 0ull},
|
|
{"CSRE2D" , 9, 1, 303, "RO", 1, 0, 0, 0ull},
|
|
{"CSRD2E" , 10, 1, 303, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_11_63" , 11, 53, 303, "RAZ", 1, 0, 0, 0ull},
|
|
{"PCTL_DAT" , 0, 5, 304, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_11" , 5, 7, 304, "RAZ", 0, 1, 0ull, 0},
|
|
{"PCTL_CSR" , 12, 4, 304, "R/W", 0, 1, 15ull, 0},
|
|
{"NCTL_DAT" , 16, 4, 304, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_27" , 20, 8, 304, "RAZ", 0, 1, 0ull, 0},
|
|
{"NCTL_CSR" , 28, 4, 304, "R/W", 0, 1, 15ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 304, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DIC" , 0, 2, 305, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QS_DIC" , 2, 2, 305, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TSKW" , 4, 2, 305, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SIL_LAT" , 6, 2, 305, "R/W", 0, 0, 1ull, 1ull},
|
|
{"BPRCH" , 8, 1, 305, "R/W", 0, 1, 0ull, 0},
|
|
{"FPRCH2" , 9, 1, 305, "R/W", 0, 0, 0ull, 1ull},
|
|
{"MODE32B" , 10, 1, 305, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRESET" , 11, 1, 305, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INORDER_MRF" , 12, 1, 305, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INORDER_MWF" , 13, 1, 305, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"R2R_SLOT" , 14, 1, 305, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RDIMM_ENA" , 15, 1, 305, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_17" , 16, 2, 305, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MAX_WRITE_BATCH" , 18, 4, 305, "R/W", 0, 0, 8ull, 8ull},
|
|
{"XOR_BANK" , 22, 1, 305, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SLOW_SCF" , 23, 1, 305, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DDR__PCTL" , 24, 4, 305, "RO", 1, 1, 0, 0},
|
|
{"DDR__NCTL" , 28, 4, 305, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 305, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 306, "RAZ", 0, 1, 0ull, 0},
|
|
{"DCC_ENABLE" , 8, 1, 306, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SIL_MODE" , 9, 1, 306, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEQUENCE" , 10, 3, 306, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDLEPOWER" , 13, 3, 306, "R/W", 0, 0, 0ull, 6ull},
|
|
{"FORCEWRITE" , 16, 4, 306, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECC_ADR" , 20, 1, 306, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_21_63" , 21, 43, 306, "RAZ", 1, 1, 0, 0},
|
|
{"DCLKCNT_HI" , 0, 32, 307, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 307, "RAZ", 1, 1, 0, 0},
|
|
{"DCLKCNT_LO" , 0, 32, 308, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 308, "RAZ", 1, 1, 0, 0},
|
|
{"DDR2" , 0, 1, 309, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RDQS" , 1, 1, 309, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLL90_BYP" , 2, 1, 309, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLL90_VLU" , 3, 5, 309, "R/W", 0, 1, 0ull, 0},
|
|
{"QDLL_ENA" , 8, 1, 309, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ODT_ENA" , 9, 1, 309, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DDR2T" , 10, 1, 309, "R/W", 0, 1, 0ull, 0},
|
|
{"CRIP_MODE" , 11, 1, 309, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TFAW" , 12, 5, 309, "R/W", 0, 0, 0ull, 9ull},
|
|
{"DDR_EOF" , 17, 4, 309, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SILO_HC" , 21, 1, 309, "R/W", 0, 1, 1ull, 0},
|
|
{"TWR" , 22, 3, 309, "R/W", 0, 0, 3ull, 1ull},
|
|
{"BWCNT" , 25, 1, 309, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POCAS" , 26, 1, 309, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDLAT" , 27, 3, 309, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BURST8" , 30, 1, 309, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BANK8" , 31, 1, 309, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 309, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CLK" , 0, 4, 310, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_4" , 4, 1, 310, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CMD" , 5, 4, 310, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 310, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DQ" , 10, 4, 310, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 310, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DLL90_VLU" , 0, 5, 311, "R/W", 0, 1, 0ull, 0},
|
|
{"DLL90_ENA" , 5, 1, 311, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLL90_BYP" , 6, 1, 311, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRESET" , 7, 1, 311, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 311, "RAZ", 1, 1, 0, 0},
|
|
{"CS_MASK" , 0, 8, 312, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_15" , 8, 8, 312, "RAZ", 0, 1, 0ull, 0},
|
|
{"ROW_LSB" , 16, 3, 312, "R/W", 0, 1, 3ull, 0},
|
|
{"BANK8" , 19, 1, 312, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_63" , 20, 44, 312, "RAZ", 0, 1, 0ull, 0},
|
|
{"MRDSYN0" , 0, 8, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN1" , 8, 8, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN2" , 16, 8, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRDSYN3" , 24, 8, 313, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 313, "RAZ", 1, 1, 0, 0},
|
|
{"FCOL" , 0, 12, 314, "RO", 0, 0, 0ull, 0ull},
|
|
{"FROW" , 12, 14, 314, "RO", 0, 0, 0ull, 0ull},
|
|
{"FBANK" , 26, 3, 314, "RO", 0, 0, 0ull, 0ull},
|
|
{"FBUNK" , 29, 1, 314, "RO", 0, 0, 0ull, 0ull},
|
|
{"FDIMM" , 30, 2, 314, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 314, "RAZ", 1, 1, 0, 0},
|
|
{"IFBCNT_HI" , 0, 32, 315, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 315, "RAZ", 1, 1, 0, 0},
|
|
{"IFBCNT_LO" , 0, 32, 316, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 316, "RAZ", 1, 1, 0, 0},
|
|
{"INIT_START" , 0, 1, 317, "WR0", 0, 0, 0ull, 0ull},
|
|
{"ECC_ENA" , 1, 1, 317, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ROW_LSB" , 2, 3, 317, "R/W", 0, 1, 3ull, 0},
|
|
{"PBANK_LSB" , 5, 4, 317, "R/W", 0, 1, 5ull, 0},
|
|
{"REF_INT" , 9, 6, 317, "R/W", 0, 0, 1ull, 2ull},
|
|
{"TCL" , 15, 4, 317, "R/W", 0, 1, 3ull, 0},
|
|
{"INTR_SEC_ENA" , 19, 1, 317, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INTR_DED_ENA" , 20, 1, 317, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SEC_ERR" , 21, 4, 317, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DED_ERR" , 25, 4, 317, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BUNK_ENA" , 29, 1, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"SILO_QC" , 30, 1, 317, "R/W", 0, 1, 0ull, 0},
|
|
{"RESET" , 31, 1, 317, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 317, "RAZ", 1, 1, 0, 0},
|
|
{"TRAS" , 0, 5, 318, "R/W", 0, 0, 12ull, 12ull},
|
|
{"TRCD" , 5, 4, 318, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TWTR" , 9, 4, 318, "R/W", 0, 0, 2ull, 2ull},
|
|
{"TRP" , 13, 4, 318, "R/W", 0, 0, 5ull, 4ull},
|
|
{"TRFC" , 17, 5, 318, "R/W", 0, 0, 6ull, 7ull},
|
|
{"TMRD" , 22, 3, 318, "R/W", 0, 0, 2ull, 2ull},
|
|
{"CASLAT" , 25, 3, 318, "R/W", 0, 0, 4ull, 4ull},
|
|
{"TRRD" , 28, 3, 318, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_31_63" , 31, 33, 318, "RAZ", 1, 1, 0, 0},
|
|
{"CS_MASK" , 0, 8, 319, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 319, "RAZ", 1, 1, 0, 0},
|
|
{"OPSCNT_HI" , 0, 32, 320, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 320, "RAZ", 1, 1, 0, 0},
|
|
{"OPSCNT_LO" , 0, 32, 321, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 321, "RAZ", 1, 1, 0, 0},
|
|
{"EN2" , 0, 1, 322, "R/W", 0, 1, 0ull, 0},
|
|
{"EN4" , 1, 1, 322, "R/W", 0, 1, 0ull, 0},
|
|
{"EN6" , 2, 1, 322, "R/W", 0, 1, 0ull, 0},
|
|
{"EN8" , 3, 1, 322, "R/W", 0, 1, 1ull, 0},
|
|
{"EN12" , 4, 1, 322, "R/W", 0, 1, 0ull, 0},
|
|
{"EN16" , 5, 1, 322, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_7" , 6, 2, 322, "RAZ", 0, 1, 0ull, 0},
|
|
{"CLKR" , 8, 6, 322, "R/W", 0, 1, 0ull, 0},
|
|
{"CLKF" , 14, 12, 322, "R/W", 0, 1, 31ull, 0},
|
|
{"RESET_N" , 26, 1, 322, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DIV_RESET" , 27, 1, 322, "R/W", 0, 0, 1ull, 0ull},
|
|
{"FASTEN_N" , 28, 1, 322, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BYPASS" , 29, 1, 322, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_63" , 30, 34, 322, "RAZ", 0, 1, 0ull, 0},
|
|
{"FBSLIP" , 0, 1, 323, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RFSLIP" , 1, 1, 323, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_21" , 2, 20, 323, "RAZ", 1, 1, 0, 0},
|
|
{"DDR__PCTL" , 22, 5, 323, "RO", 1, 1, 0, 0},
|
|
{"DDR__NCTL" , 27, 5, 323, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 323, "RAZ", 1, 1, 0, 0},
|
|
{"BNK" , 0, 3, 324, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 324, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"COL" , 4, 12, 324, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROW" , 16, 16, 324, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PATTERN" , 32, 8, 324, "R/W", 0, 0, 170ull, 170ull},
|
|
{"RANKMASK" , 40, 4, 324, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_44_63" , 44, 20, 324, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"BYTE" , 0, 4, 325, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_15" , 4, 12, 325, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"BITMASK" , 16, 16, 325, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 325, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"BYTE0" , 0, 4, 326, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE1" , 4, 4, 326, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE2" , 8, 4, 326, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE3" , 12, 4, 326, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE4" , 16, 4, 326, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE5" , 20, 4, 326, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE6" , 24, 4, 326, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE7" , 28, 4, 326, "R/W", 0, 1, 0ull, 0},
|
|
{"BYTE8" , 32, 4, 326, "R/W", 0, 1, 0ull, 0},
|
|
{"STATUS" , 36, 2, 326, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_38_63" , 38, 26, 326, "RAZ", 1, 0, 0, 0ull},
|
|
{"PCTL" , 0, 5, 327, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 327, "RAZ", 0, 1, 0ull, 0},
|
|
{"NCTL" , 8, 4, 327, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_12_15" , 12, 4, 327, "RAZ", 0, 1, 0ull, 0},
|
|
{"ENABLE" , 16, 1, 327, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_17_63" , 17, 47, 327, "RAZ", 0, 1, 0ull, 0},
|
|
{"RODT_LO0" , 0, 4, 328, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_LO1" , 4, 4, 328, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_LO2" , 8, 4, 328, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_LO3" , 12, 4, 328, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI0" , 16, 4, 328, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI1" , 20, 4, 328, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI2" , 24, 4, 328, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RODT_HI3" , 28, 4, 328, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_32_63" , 32, 32, 328, "RAZ", 1, 1, 0, 0},
|
|
{"WODT_D0_R0" , 0, 8, 329, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D0_R1" , 8, 8, 329, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D1_R0" , 16, 8, 329, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D1_R1" , 24, 8, 329, "R/W", 0, 0, 255ull, 255ull},
|
|
{"RESERVED_32_63" , 32, 32, 329, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WODT_D2_R0" , 0, 8, 330, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D2_R1" , 8, 8, 330, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D3_R0" , 16, 8, 330, "R/W", 0, 0, 255ull, 255ull},
|
|
{"WODT_D3_R1" , 24, 8, 330, "R/W", 0, 0, 255ull, 255ull},
|
|
{"RESERVED_32_63" , 32, 32, 330, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"NCBI" , 0, 1, 331, "RO", 0, 0, 0ull, 0ull},
|
|
{"LOC" , 1, 1, 331, "RO", 0, 0, 0ull, 0ull},
|
|
{"DMA" , 2, 1, 331, "RO", 0, 0, 0ull, 0ull},
|
|
{"NCBO_0" , 3, 1, 331, "RO", 0, 0, 0ull, 0ull},
|
|
{"NDF" , 4, 2, 331, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 331, "RAZ", 1, 1, 0, 0},
|
|
{"NCTL" , 0, 5, 332, "R/W", 1, 1, 0, 0},
|
|
{"PCTL" , 5, 5, 332, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_10_63" , 10, 54, 332, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 36, 333, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 36, 20, 333, "R/W", 0, 1, 0ull, 0},
|
|
{"ENDIAN" , 56, 1, 333, "R/W", 0, 1, 0ull, 0},
|
|
{"SWAP8" , 57, 1, 333, "R/W", 0, 1, 0ull, 0},
|
|
{"SWAP16" , 58, 1, 333, "R/W", 0, 1, 0ull, 0},
|
|
{"SWAP32" , 59, 1, 333, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_60" , 60, 1, 333, "RAZ", 1, 1, 0, 0},
|
|
{"CLR" , 61, 1, 333, "R/W", 0, 1, 0ull, 0},
|
|
{"RW" , 62, 1, 333, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 63, 1, 333, "R/W", 0, 1, 0ull, 0},
|
|
{"DONE" , 0, 1, 334, "R/W1C", 0, 1, 0ull, 0},
|
|
{"DMARQ" , 1, 1, 334, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_2_63" , 2, 62, 334, "RAZ", 1, 1, 0, 0},
|
|
{"DONE" , 0, 1, 335, "R/W", 0, 1, 0ull, 0},
|
|
{"DMARQ" , 1, 1, 335, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 335, "RAZ", 1, 1, 0, 0},
|
|
{"DMARQ" , 0, 6, 336, "R/W", 0, 1, 63ull, 0},
|
|
{"DMACK_S" , 6, 6, 336, "R/W", 0, 1, 63ull, 0},
|
|
{"OE_A" , 12, 6, 336, "R/W", 0, 1, 63ull, 0},
|
|
{"OE_N" , 18, 6, 336, "R/W", 0, 1, 63ull, 0},
|
|
{"WE_A" , 24, 6, 336, "R/W", 0, 1, 63ull, 0},
|
|
{"WE_N" , 30, 6, 336, "R/W", 0, 1, 63ull, 0},
|
|
{"DMACK_H" , 36, 6, 336, "R/W", 0, 1, 63ull, 0},
|
|
{"PAUSE" , 42, 6, 336, "R/W", 0, 1, 63ull, 0},
|
|
{"RESERVED_48_54" , 48, 7, 336, "RAZ", 1, 1, 0, 0},
|
|
{"WIDTH" , 55, 1, 336, "R/W", 0, 1, 0ull, 0},
|
|
{"DDR" , 56, 1, 336, "R/W", 0, 1, 0ull, 0},
|
|
{"RD_DLY" , 57, 3, 336, "R/W", 0, 1, 0ull, 0},
|
|
{"TIM_MULT" , 60, 2, 336, "R/W", 0, 1, 0ull, 0},
|
|
{"DMARQ_PI" , 62, 1, 336, "R/W", 0, 1, 0ull, 0},
|
|
{"DMACK_PI" , 63, 1, 336, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR_ERR" , 0, 1, 337, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WAIT_ERR" , 1, 1, 337, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 337, "RAZ", 1, 1, 0, 0},
|
|
{"ADR_INT" , 0, 1, 338, "R/W", 0, 1, 0ull, 0},
|
|
{"WAIT_INT" , 1, 1, 338, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 338, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 339, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 3, 5, 339, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 339, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 340, "RAZ", 1, 1, 0, 0},
|
|
{"BASE" , 3, 25, 340, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_30" , 28, 3, 340, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 31, 1, 340, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 340, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 64, 341, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 342, "RAZ", 1, 1, 0, 0},
|
|
{"NAND" , 8, 1, 342, "RO", 1, 1, 0, 0},
|
|
{"TERM" , 9, 2, 342, "RO", 1, 1, 0, 0},
|
|
{"DMACK_P0" , 11, 1, 342, "RO", 1, 1, 0, 0},
|
|
{"DMACK_P1" , 12, 1, 342, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_13_13" , 13, 1, 342, "RAZ", 1, 1, 0, 0},
|
|
{"WIDTH" , 14, 1, 342, "RO", 1, 1, 0, 0},
|
|
{"ALE" , 15, 1, 342, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_16_63" , 16, 48, 342, "RAZ", 1, 1, 0, 0},
|
|
{"BASE" , 0, 16, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 16, 12, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"WIDTH" , 28, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"ALE" , 29, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"ORBIT" , 30, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 31, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"OE_EXT" , 32, 2, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"WE_EXT" , 34, 2, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"SAM" , 36, 1, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RD_DLY" , 37, 3, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"TIM_MULT" , 40, 2, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"DMACK" , 42, 2, 343, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 343, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 6, 344, "R/W", 0, 1, 63ull, 0},
|
|
{"CE" , 6, 6, 344, "R/W", 0, 1, 63ull, 0},
|
|
{"OE" , 12, 6, 344, "R/W", 0, 1, 63ull, 0},
|
|
{"WE" , 18, 6, 344, "R/W", 0, 1, 63ull, 0},
|
|
{"RD_HLD" , 24, 6, 344, "R/W", 0, 1, 63ull, 0},
|
|
{"WR_HLD" , 30, 6, 344, "R/W", 0, 1, 63ull, 0},
|
|
{"PAUSE" , 36, 6, 344, "R/W", 0, 1, 63ull, 0},
|
|
{"WAIT" , 42, 6, 344, "R/W", 0, 1, 63ull, 0},
|
|
{"PAGE" , 48, 6, 344, "R/W", 0, 1, 63ull, 0},
|
|
{"ALE" , 54, 6, 344, "R/W", 0, 1, 63ull, 0},
|
|
{"PAGES" , 60, 2, 344, "R/W", 0, 1, 0ull, 0},
|
|
{"WAITM" , 62, 1, 344, "R/W", 0, 1, 0ull, 0},
|
|
{"PAGEM" , 63, 1, 344, "R/W", 0, 1, 0ull, 0},
|
|
{"FIF_THR" , 0, 6, 345, "R/W", 0, 0, 25ull, 25ull},
|
|
{"RESERVED_6_7" , 6, 2, 345, "RAZ", 1, 1, 0, 0},
|
|
{"FIF_CNT" , 8, 6, 345, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_15" , 14, 2, 345, "RAZ", 1, 1, 0, 0},
|
|
{"DMA_THR" , 16, 6, 345, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_22_63" , 22, 42, 345, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 64, 346, "R/W", 1, 1, 0, 0},
|
|
{"MAN_INFO" , 0, 32, 347, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 347, "RAZ", 1, 1, 0, 0},
|
|
{"MAN_INFO" , 0, 32, 348, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_32_63" , 32, 32, 348, "RAZ", 1, 1, 0, 0},
|
|
{"PP_DIS" , 0, 4, 349, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_4_15" , 4, 12, 349, "RO", 1, 1, 0, 0},
|
|
{"CHIP_ID" , 16, 8, 349, "RO", 1, 1, 0, 0},
|
|
{"BIST_DIS" , 24, 1, 349, "RO", 1, 1, 0, 0},
|
|
{"RST_SHT" , 25, 1, 349, "RO", 1, 1, 0, 0},
|
|
{"NOCRYPTO" , 26, 1, 349, "RO", 1, 1, 0, 0},
|
|
{"NOMUL" , 27, 1, 349, "RO", 1, 1, 0, 0},
|
|
{"NODFA_CP2" , 28, 1, 349, "RO", 1, 1, 0, 0},
|
|
{"NOKASU" , 29, 1, 349, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_30_31" , 30, 2, 349, "RAZ", 1, 1, 0, 0},
|
|
{"RAID_EN" , 32, 1, 349, "RO", 1, 1, 0, 0},
|
|
{"FUS318" , 33, 1, 349, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_34_63" , 34, 30, 349, "RAZ", 1, 1, 0, 0},
|
|
{"ICACHE" , 0, 24, 350, "RO", 1, 1, 0, 0},
|
|
{"NODFA_DTE" , 24, 1, 350, "RO", 1, 1, 0, 0},
|
|
{"NOZIP" , 25, 1, 350, "RO", 1, 1, 0, 0},
|
|
{"EFUS_IGN" , 26, 1, 350, "RO", 1, 1, 0, 0},
|
|
{"EFUS_LCK" , 27, 1, 350, "RO", 1, 1, 0, 0},
|
|
{"BAR2_EN" , 28, 1, 350, "RO", 1, 1, 0, 0},
|
|
{"ZIP_CRIP" , 29, 2, 350, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_31_63" , 31, 33, 350, "RAZ", 1, 1, 0, 0},
|
|
{"EMA" , 0, 3, 351, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 351, "RAZ", 1, 1, 0, 0},
|
|
{"EFF_EMA" , 4, 3, 351, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 351, "RAZ", 1, 1, 0, 0},
|
|
{"PDF" , 0, 64, 352, "RO", 1, 1, 0, 0},
|
|
{"FBSLIP" , 0, 1, 353, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RFSLIP" , 1, 1, 353, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 353, "RAZ", 1, 1, 0, 0},
|
|
{"PROG" , 0, 1, 354, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_1_63" , 1, 63, 354, "RAZ", 1, 1, 0, 0},
|
|
{"SETUP" , 0, 8, 355, "R/W", 0, 1, 3ull, 0},
|
|
{"SCLK_HI" , 8, 12, 355, "R/W", 0, 1, 100ull, 0},
|
|
{"SCLK_LO" , 20, 4, 355, "R/W", 0, 1, 2ull, 0},
|
|
{"OUT" , 24, 8, 355, "R/W", 0, 1, 3ull, 0},
|
|
{"PROG_PIN" , 32, 1, 355, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_33_63" , 33, 31, 355, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 8, 356, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EFUSE" , 8, 1, 356, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 356, "RAZ", 1, 1, 0, 0},
|
|
{"PEND" , 12, 1, 356, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 356, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 16, 8, 356, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_24_63" , 24, 40, 356, "RAZ", 1, 1, 0, 0},
|
|
{"REPAIR0" , 0, 14, 357, "RO", 0, 0, 0ull, 0ull},
|
|
{"REPAIR1" , 14, 14, 357, "RO", 0, 0, 0ull, 0ull},
|
|
{"REPAIR2" , 28, 14, 357, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_42_63" , 42, 22, 357, "RAZ", 1, 1, 0, 0},
|
|
{"TOO_MANY" , 0, 1, 358, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 358, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 3, 359, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_3_63" , 3, 61, 359, "RAZ", 1, 1, 0, 0},
|
|
{"ADR" , 0, 36, 360, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 36, 20, 360, "R/W", 0, 1, 0ull, 0},
|
|
{"ENDIAN" , 56, 1, 360, "R/W", 0, 1, 0ull, 0},
|
|
{"SWAP8" , 57, 1, 360, "R/W", 0, 1, 0ull, 0},
|
|
{"SWAP16" , 58, 1, 360, "R/W", 0, 1, 0ull, 0},
|
|
{"SWAP32" , 59, 1, 360, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_60" , 60, 1, 360, "RAZ", 1, 1, 0, 0},
|
|
{"CLR" , 61, 1, 360, "R/W", 0, 1, 0ull, 0},
|
|
{"RW" , 62, 1, 360, "R/W", 0, 1, 0ull, 0},
|
|
{"EN" , 63, 1, 360, "R/W", 0, 1, 0ull, 0},
|
|
{"DONE" , 0, 1, 361, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 361, "RAZ", 1, 1, 0, 0},
|
|
{"DONE" , 0, 1, 362, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 362, "RAZ", 1, 1, 0, 0},
|
|
{"ST_INT" , 0, 1, 363, "R/W1C", 0, 1, 0ull, 0},
|
|
{"TS_INT" , 1, 1, 363, "R/W1C", 0, 1, 0ull, 0},
|
|
{"CORE_INT" , 2, 1, 363, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_3" , 3, 1, 363, "RAZ", 1, 1, 0, 0},
|
|
{"ST_EN" , 4, 1, 363, "R/W", 0, 1, 0ull, 0},
|
|
{"TS_EN" , 5, 1, 363, "R/W", 0, 1, 0ull, 0},
|
|
{"CORE_EN" , 6, 1, 363, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_7" , 7, 1, 363, "RAZ", 1, 1, 0, 0},
|
|
{"SDA_OVR" , 8, 1, 363, "R/W", 0, 1, 0ull, 0},
|
|
{"SCL_OVR" , 9, 1, 363, "R/W", 0, 1, 0ull, 0},
|
|
{"SDA" , 10, 1, 363, "RO", 1, 1, 0, 0},
|
|
{"SCL" , 11, 1, 363, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_12_63" , 12, 52, 363, "RAZ", 1, 1, 0, 0},
|
|
{"D" , 0, 32, 364, "R/W", 0, 1, 0ull, 0},
|
|
{"EOP_IA" , 32, 3, 364, "R/W", 0, 1, 0ull, 0},
|
|
{"IA" , 35, 5, 364, "R/W", 0, 1, 0ull, 0},
|
|
{"A" , 40, 10, 364, "R/W", 0, 1, 0ull, 0},
|
|
{"SCR" , 50, 2, 364, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 52, 3, 364, "R/W", 0, 1, 0ull, 0},
|
|
{"SOVR" , 55, 1, 364, "R/W", 0, 1, 0ull, 0},
|
|
{"R" , 56, 1, 364, "R/W", 0, 1, 0ull, 0},
|
|
{"OP" , 57, 4, 364, "R/W", 0, 1, 0ull, 0},
|
|
{"EIA" , 61, 1, 364, "R/W", 0, 1, 0ull, 0},
|
|
{"SLONLY" , 62, 1, 364, "R/W", 0, 1, 0ull, 0},
|
|
{"V" , 63, 1, 364, "RC/W", 0, 1, 0ull, 0},
|
|
{"D" , 0, 32, 365, "R/W", 0, 1, 0ull, 0},
|
|
{"IA" , 32, 8, 365, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_40_63" , 40, 24, 365, "RAZ", 1, 1, 0, 0},
|
|
{"D" , 0, 32, 366, "R/W", 1, 1, 0, 0},
|
|
{"RESERVED_32_61" , 32, 30, 366, "RAZ", 1, 1, 0, 0},
|
|
{"V" , 62, 2, 366, "RC/W", 0, 1, 0ull, 0},
|
|
{"DLH" , 0, 8, 367, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 367, "RAZ", 1, 1, 0, 0},
|
|
{"DLL" , 0, 8, 368, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 368, "RAZ", 1, 1, 0, 0},
|
|
{"FAR" , 0, 1, 369, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 369, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 370, "WO", 0, 1, 0ull, 0},
|
|
{"RXFR" , 1, 1, 370, "WO", 0, 1, 0ull, 0},
|
|
{"TXFR" , 2, 1, 370, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_3" , 3, 1, 370, "RAZ", 0, 1, 0ull, 0},
|
|
{"TXTRIG" , 4, 2, 370, "WO", 0, 1, 0ull, 0},
|
|
{"RXTRIG" , 6, 2, 370, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 370, "RAZ", 1, 1, 0, 0},
|
|
{"HTX" , 0, 1, 371, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 371, "RAZ", 1, 1, 0, 0},
|
|
{"ERBFI" , 0, 1, 372, "R/W", 0, 1, 0ull, 0},
|
|
{"ETBEI" , 1, 1, 372, "R/W", 0, 1, 0ull, 0},
|
|
{"ELSI" , 2, 1, 372, "R/W", 0, 1, 0ull, 0},
|
|
{"EDSSI" , 3, 1, 372, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_6" , 4, 3, 372, "RAZ", 0, 1, 0ull, 0},
|
|
{"PTIME" , 7, 1, 372, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 372, "RAZ", 1, 1, 0, 0},
|
|
{"IID" , 0, 4, 373, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_4_5" , 4, 2, 373, "RAZ", 0, 1, 0ull, 0},
|
|
{"FEN" , 6, 2, 373, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 373, "RAZ", 1, 1, 0, 0},
|
|
{"CLS" , 0, 2, 374, "R/W", 0, 1, 0ull, 0},
|
|
{"STOP" , 2, 1, 374, "R/W", 0, 1, 0ull, 0},
|
|
{"PEN" , 3, 1, 374, "R/W", 0, 1, 0ull, 0},
|
|
{"EPS" , 4, 1, 374, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_5" , 5, 1, 374, "RAZ", 0, 1, 0ull, 0},
|
|
{"BRK" , 6, 1, 374, "R/W", 0, 1, 0ull, 0},
|
|
{"DLAB" , 7, 1, 374, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 374, "RAZ", 1, 1, 0, 0},
|
|
{"DR" , 0, 1, 375, "RO", 0, 1, 0ull, 0},
|
|
{"OE" , 1, 1, 375, "RC", 0, 1, 0ull, 0},
|
|
{"PE" , 2, 1, 375, "RC", 0, 1, 0ull, 0},
|
|
{"FE" , 3, 1, 375, "RC", 0, 1, 0ull, 0},
|
|
{"BI" , 4, 1, 375, "RC", 0, 1, 0ull, 0},
|
|
{"THRE" , 5, 1, 375, "RO", 0, 1, 1ull, 0},
|
|
{"TEMT" , 6, 1, 375, "RO", 0, 1, 1ull, 0},
|
|
{"FERR" , 7, 1, 375, "RC", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 375, "RAZ", 1, 1, 0, 0},
|
|
{"DTR" , 0, 1, 376, "R/W", 0, 1, 0ull, 0},
|
|
{"RTS" , 1, 1, 376, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT1" , 2, 1, 376, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT2" , 3, 1, 376, "R/W", 0, 1, 0ull, 0},
|
|
{"LOOP" , 4, 1, 376, "R/W", 0, 1, 0ull, 0},
|
|
{"AFCE" , 5, 1, 376, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 376, "RAZ", 0, 1, 0ull, 0},
|
|
{"DCTS" , 0, 1, 377, "RC", 0, 1, 0ull, 0},
|
|
{"DDSR" , 1, 1, 377, "RC", 0, 1, 0ull, 0},
|
|
{"TERI" , 2, 1, 377, "RC", 0, 1, 0ull, 0},
|
|
{"DDCD" , 3, 1, 377, "RC", 0, 1, 0ull, 0},
|
|
{"CTS" , 4, 1, 377, "RO", 1, 1, 0, 0},
|
|
{"DSR" , 5, 1, 377, "RO", 0, 1, 0ull, 0},
|
|
{"RI" , 6, 1, 377, "RO", 0, 1, 0ull, 0},
|
|
{"DCD" , 7, 1, 377, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 377, "RAZ", 1, 1, 0, 0},
|
|
{"RBR" , 0, 8, 378, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 378, "RAZ", 1, 1, 0, 0},
|
|
{"RFL" , 0, 7, 379, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 379, "RAZ", 1, 1, 0, 0},
|
|
{"RFWD" , 0, 8, 380, "WO", 0, 1, 0ull, 0},
|
|
{"RFPE" , 8, 1, 380, "WO", 0, 1, 0ull, 0},
|
|
{"RFFE" , 9, 1, 380, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_10_63" , 10, 54, 380, "RAZ", 1, 1, 0, 0},
|
|
{"SBCR" , 0, 1, 381, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 381, "RAZ", 1, 1, 0, 0},
|
|
{"SCR" , 0, 8, 382, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 382, "RAZ", 1, 1, 0, 0},
|
|
{"SFE" , 0, 1, 383, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 383, "RAZ", 1, 1, 0, 0},
|
|
{"USR" , 0, 1, 384, "WO", 0, 1, 0ull, 0},
|
|
{"SRFR" , 1, 1, 384, "WO", 0, 1, 0ull, 0},
|
|
{"STFR" , 2, 1, 384, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_63" , 3, 61, 384, "RAZ", 1, 1, 0, 0},
|
|
{"SRT" , 0, 2, 385, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 385, "RAZ", 1, 1, 0, 0},
|
|
{"SRTS" , 0, 1, 386, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 386, "RAZ", 1, 1, 0, 0},
|
|
{"STT" , 0, 2, 387, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 387, "RAZ", 1, 1, 0, 0},
|
|
{"TFL" , 0, 7, 388, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 388, "RAZ", 1, 1, 0, 0},
|
|
{"TFR" , 0, 8, 389, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 389, "RAZ", 1, 1, 0, 0},
|
|
{"THR" , 0, 8, 390, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 390, "RAZ", 1, 1, 0, 0},
|
|
{"BUSY" , 0, 1, 391, "RO", 0, 1, 0ull, 0},
|
|
{"TFNF" , 1, 1, 391, "RO", 0, 1, 1ull, 0},
|
|
{"TFE" , 2, 1, 391, "RO", 0, 1, 1ull, 0},
|
|
{"RFNE" , 3, 1, 391, "RO", 0, 1, 0ull, 0},
|
|
{"RFF" , 4, 1, 391, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 391, "RAZ", 1, 1, 0, 0},
|
|
{"DLH" , 0, 8, 392, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 392, "RAZ", 1, 1, 0, 0},
|
|
{"DLL" , 0, 8, 393, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 393, "RAZ", 1, 1, 0, 0},
|
|
{"FAR" , 0, 1, 394, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 394, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 395, "WO", 0, 1, 0ull, 0},
|
|
{"RXFR" , 1, 1, 395, "WO", 0, 1, 0ull, 0},
|
|
{"TXFR" , 2, 1, 395, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_3" , 3, 1, 395, "RAZ", 0, 1, 0ull, 0},
|
|
{"TXTRIG" , 4, 2, 395, "WO", 0, 1, 0ull, 0},
|
|
{"RXTRIG" , 6, 2, 395, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 395, "RAZ", 1, 1, 0, 0},
|
|
{"HTX" , 0, 1, 396, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 396, "RAZ", 1, 1, 0, 0},
|
|
{"ERBFI" , 0, 1, 397, "R/W", 0, 1, 0ull, 0},
|
|
{"ETBEI" , 1, 1, 397, "R/W", 0, 1, 0ull, 0},
|
|
{"ELSI" , 2, 1, 397, "R/W", 0, 1, 0ull, 0},
|
|
{"EDSSI" , 3, 1, 397, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_6" , 4, 3, 397, "RAZ", 0, 1, 0ull, 0},
|
|
{"PTIME" , 7, 1, 397, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 397, "RAZ", 1, 1, 0, 0},
|
|
{"IID" , 0, 4, 398, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_4_5" , 4, 2, 398, "RAZ", 0, 1, 0ull, 0},
|
|
{"FEN" , 6, 2, 398, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 398, "RAZ", 1, 1, 0, 0},
|
|
{"CLS" , 0, 2, 399, "R/W", 0, 1, 0ull, 0},
|
|
{"STOP" , 2, 1, 399, "R/W", 0, 1, 0ull, 0},
|
|
{"PEN" , 3, 1, 399, "R/W", 0, 1, 0ull, 0},
|
|
{"EPS" , 4, 1, 399, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_5" , 5, 1, 399, "RAZ", 0, 1, 0ull, 0},
|
|
{"BRK" , 6, 1, 399, "R/W", 0, 1, 0ull, 0},
|
|
{"DLAB" , 7, 1, 399, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 399, "RAZ", 1, 1, 0, 0},
|
|
{"DR" , 0, 1, 400, "RO", 0, 1, 0ull, 0},
|
|
{"OE" , 1, 1, 400, "RC", 0, 1, 0ull, 0},
|
|
{"PE" , 2, 1, 400, "RC", 0, 1, 0ull, 0},
|
|
{"FE" , 3, 1, 400, "RC", 0, 1, 0ull, 0},
|
|
{"BI" , 4, 1, 400, "RC", 0, 1, 0ull, 0},
|
|
{"THRE" , 5, 1, 400, "RO", 0, 1, 1ull, 0},
|
|
{"TEMT" , 6, 1, 400, "RO", 0, 1, 1ull, 0},
|
|
{"FERR" , 7, 1, 400, "RC", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 400, "RAZ", 1, 1, 0, 0},
|
|
{"DTR" , 0, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RTS" , 1, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT1" , 2, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT2" , 3, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"LOOP" , 4, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"AFCE" , 5, 1, 401, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_63" , 6, 58, 401, "RAZ", 0, 1, 0ull, 0},
|
|
{"DCTS" , 0, 1, 402, "RC", 0, 1, 0ull, 0},
|
|
{"DDSR" , 1, 1, 402, "RC", 0, 1, 0ull, 0},
|
|
{"TERI" , 2, 1, 402, "RC", 0, 1, 0ull, 0},
|
|
{"DDCD" , 3, 1, 402, "RC", 0, 1, 0ull, 0},
|
|
{"CTS" , 4, 1, 402, "RO", 1, 1, 0, 0},
|
|
{"DSR" , 5, 1, 402, "RO", 0, 1, 0ull, 0},
|
|
{"RI" , 6, 1, 402, "RO", 0, 1, 0ull, 0},
|
|
{"DCD" , 7, 1, 402, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 402, "RAZ", 1, 1, 0, 0},
|
|
{"RBR" , 0, 8, 403, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 403, "RAZ", 1, 1, 0, 0},
|
|
{"RFL" , 0, 7, 404, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 404, "RAZ", 1, 1, 0, 0},
|
|
{"RFWD" , 0, 8, 405, "WO", 0, 1, 0ull, 0},
|
|
{"RFPE" , 8, 1, 405, "WO", 0, 1, 0ull, 0},
|
|
{"RFFE" , 9, 1, 405, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_10_63" , 10, 54, 405, "RAZ", 1, 1, 0, 0},
|
|
{"SBCR" , 0, 1, 406, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 406, "RAZ", 1, 1, 0, 0},
|
|
{"SCR" , 0, 8, 407, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 407, "RAZ", 1, 1, 0, 0},
|
|
{"SFE" , 0, 1, 408, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 408, "RAZ", 1, 1, 0, 0},
|
|
{"USR" , 0, 1, 409, "WO", 0, 1, 0ull, 0},
|
|
{"SRFR" , 1, 1, 409, "WO", 0, 1, 0ull, 0},
|
|
{"STFR" , 2, 1, 409, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_3_63" , 3, 61, 409, "RAZ", 1, 1, 0, 0},
|
|
{"SRT" , 0, 2, 410, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 410, "RAZ", 1, 1, 0, 0},
|
|
{"SRTS" , 0, 1, 411, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_1_63" , 1, 63, 411, "RAZ", 1, 1, 0, 0},
|
|
{"STT" , 0, 2, 412, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_2_63" , 2, 62, 412, "RAZ", 1, 1, 0, 0},
|
|
{"TFL" , 0, 7, 413, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 413, "RAZ", 1, 1, 0, 0},
|
|
{"TFR" , 0, 8, 414, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 414, "RAZ", 1, 1, 0, 0},
|
|
{"THR" , 0, 8, 415, "WO", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 415, "RAZ", 1, 1, 0, 0},
|
|
{"BUSY" , 0, 1, 416, "RO", 0, 1, 0ull, 0},
|
|
{"TFNF" , 1, 1, 416, "RO", 0, 1, 1ull, 0},
|
|
{"TFE" , 2, 1, 416, "RO", 0, 1, 1ull, 0},
|
|
{"RFNE" , 3, 1, 416, "RO", 0, 1, 0ull, 0},
|
|
{"RFF" , 4, 1, 416, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_63" , 5, 59, 416, "RAZ", 1, 1, 0, 0},
|
|
{"ORFDAT" , 0, 1, 417, "RO", 0, 0, 0ull, 0ull},
|
|
{"IRFDAT" , 1, 1, 417, "RO", 0, 0, 0ull, 0ull},
|
|
{"IPFDAT" , 2, 1, 417, "RO", 0, 0, 0ull, 0ull},
|
|
{"MRQDAT" , 3, 1, 417, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 417, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MRQ_HWM" , 0, 2, 418, "R/W", 0, 0, 1ull, 1ull},
|
|
{"NBTARB" , 2, 1, 418, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LENDIAN" , 3, 1, 418, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 4, 1, 418, "R/W", 0, 0, 1ull, 0ull},
|
|
{"EN" , 5, 1, 418, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BUSY" , 6, 1, 418, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRC_STRIP" , 7, 1, 418, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 418, "RAZ", 1, 1, 0, 0},
|
|
{"OVFENA" , 0, 1, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IVFENA" , 1, 1, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OTHENA" , 2, 1, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ITHENA" , 3, 1, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DATA_DRPENA" , 4, 1, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IRUNENA" , 5, 1, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ORUNENA" , 6, 1, 419, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 419, "RAZ", 1, 1, 0, 0},
|
|
{"IRCNT" , 0, 20, 420, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 420, "RAZ", 1, 1, 0, 0},
|
|
{"IRHWM" , 0, 20, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IBPLWM" , 20, 20, 421, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 421, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 422, "RAZ", 1, 1, 0, 0},
|
|
{"IBASE" , 3, 33, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_39" , 36, 4, 422, "RAZ", 1, 1, 0, 0},
|
|
{"ISIZE" , 40, 20, 422, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 422, "RAZ", 1, 1, 0, 0},
|
|
{"IDBELL" , 0, 20, 423, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_31" , 20, 12, 423, "RAZ", 1, 1, 0, 0},
|
|
{"ITLPTR" , 32, 20, 423, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_52_63" , 52, 12, 423, "RAZ", 1, 1, 0, 0},
|
|
{"ODBLOVF" , 0, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IDBLOVF" , 1, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ORTHRESH" , 2, 1, 424, "RO", 0, 0, 0ull, 0ull},
|
|
{"IRTHRESH" , 3, 1, 424, "RO", 0, 0, 0ull, 0ull},
|
|
{"DATA_DRP" , 4, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IRUN" , 5, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ORUN" , 6, 1, 424, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 424, "RAZ", 1, 1, 0, 0},
|
|
{"ORCNT" , 0, 20, 425, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 425, "RAZ", 1, 1, 0, 0},
|
|
{"ORHWM" , 0, 20, 426, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 426, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_2" , 0, 3, 427, "RAZ", 1, 1, 0, 0},
|
|
{"OBASE" , 3, 33, 427, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_39" , 36, 4, 427, "RAZ", 1, 1, 0, 0},
|
|
{"OSIZE" , 40, 20, 427, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 427, "RAZ", 1, 1, 0, 0},
|
|
{"ODBELL" , 0, 20, 428, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_20_31" , 20, 12, 428, "RAZ", 1, 1, 0, 0},
|
|
{"OTLPTR" , 32, 20, 428, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_52_63" , 52, 12, 428, "RAZ", 1, 1, 0, 0},
|
|
{"OREMCNT" , 0, 20, 429, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 429, "RAZ", 1, 1, 0, 0},
|
|
{"IREMCNT" , 32, 20, 429, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_52_63" , 52, 12, 429, "RAZ", 1, 1, 0, 0},
|
|
{"SIZE" , 0, 3, 430, "R/W", 0, 1, 0ull, 0},
|
|
{"ADR_CYC" , 3, 4, 430, "R/W", 0, 1, 8ull, 0},
|
|
{"T_MULT" , 7, 4, 430, "R/W", 0, 1, 9ull, 0},
|
|
{"RESERVED_11_63" , 11, 53, 430, "RAZ", 1, 1, 0, 0},
|
|
{"NF_CMD" , 0, 64, 431, "R/W", 0, 1, 0ull, 0},
|
|
{"CNT" , 0, 8, 432, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 432, "RAZ", 1, 1, 0, 0},
|
|
{"ECC_ERR" , 0, 8, 433, "RO", 0, 1, 0ull, 0},
|
|
{"XOR_ECC" , 8, 24, 433, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 433, "RAZ", 1, 1, 0, 0},
|
|
{"EMPTY" , 0, 1, 434, "R/W1C", 0, 1, 0ull, 0},
|
|
{"FULL" , 1, 1, 434, "R/W1C", 0, 1, 0ull, 0},
|
|
{"WDOG" , 2, 1, 434, "R/W1C", 0, 1, 0ull, 0},
|
|
{"SM_BAD" , 3, 1, 434, "R/W1C", 0, 1, 0ull, 0},
|
|
{"ECC_1BIT" , 4, 1, 434, "R/W1C", 0, 1, 0ull, 0},
|
|
{"ECC_MULT" , 5, 1, 434, "R/W1C", 0, 1, 0ull, 0},
|
|
{"OVRF" , 6, 1, 434, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 434, "RAZ", 1, 1, 0, 0},
|
|
{"EMPTY" , 0, 1, 435, "R/W", 0, 1, 0ull, 0},
|
|
{"FULL" , 1, 1, 435, "R/W", 0, 1, 0ull, 0},
|
|
{"WDOG" , 2, 1, 435, "R/W", 0, 1, 0ull, 0},
|
|
{"SM_BAD" , 3, 1, 435, "R/W", 0, 1, 0ull, 0},
|
|
{"ECC_1BIT" , 4, 1, 435, "R/W", 0, 1, 0ull, 0},
|
|
{"ECC_MULT" , 5, 1, 435, "R/W", 0, 1, 0ull, 0},
|
|
{"OVRF" , 6, 1, 435, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 435, "RAZ", 1, 1, 0, 0},
|
|
{"RST_FF" , 0, 1, 436, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EX_DIS" , 1, 1, 436, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BT_DIS" , 2, 1, 436, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BT_DMA" , 3, 1, 436, "R/W", 0, 1, 0ull, 0},
|
|
{"RD_CMD" , 4, 1, 436, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RD_VAL" , 5, 1, 436, "RO", 0, 1, 0ull, 0},
|
|
{"RD_DONE" , 6, 1, 436, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FR_BYT" , 7, 11, 436, "RO", 0, 1, 0ull, 0},
|
|
{"WAIT_CNT" , 18, 6, 436, "R/W", 0, 1, 20ull, 0},
|
|
{"NBR_HWM" , 24, 3, 436, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_27_63" , 27, 37, 436, "RAZ", 1, 1, 0, 0},
|
|
{"MAIN_SM" , 0, 3, 437, "RO", 0, 1, 0ull, 0},
|
|
{"MAIN_BAD" , 3, 1, 437, "RO", 0, 1, 0ull, 0},
|
|
{"RD_FF" , 4, 2, 437, "RO", 0, 1, 0ull, 0},
|
|
{"RD_FF_BAD" , 6, 1, 437, "RO", 0, 1, 0ull, 0},
|
|
{"BT_SM" , 7, 4, 437, "RO", 0, 1, 0ull, 0},
|
|
{"EXE_SM" , 11, 4, 437, "RO", 0, 1, 0ull, 0},
|
|
{"EXE_IDLE" , 15, 1, 437, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 437, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR_V" , 0, 1, 438, "R/W", 0, 1, 0ull, 0},
|
|
{"END_SWP" , 1, 2, 438, "R/W", 0, 1, 0ull, 0},
|
|
{"CA" , 3, 1, 438, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ADDR_IDX" , 4, 14, 438, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_31" , 18, 14, 438, "RAZ", 1, 1, 0, 0},
|
|
{"NCB_CMD" , 0, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSI" , 1, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF4" , 2, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF3" , 3, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF2" , 4, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF1" , 5, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"DIF0" , 6, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSM1" , 7, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSM0" , 8, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_P1" , 9, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_P0" , 10, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_N" , 11, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_C1" , 12, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_C0" , 13, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_P1" , 14, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_P0" , 15, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_N" , 16, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_C1" , 17, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_C0" , 18, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_CO" , 19, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_NO" , 20, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N0_PO" , 21, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_CO" , 22, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_NO" , 23, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"P2N1_PO" , 24, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"CPL_P1" , 25, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"CPL_P0" , 26, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"N2P1_O" , 27, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"N2P1_C" , 28, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"N2P0_O" , 29, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"N2P0_C" , 30, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"D4_PST" , 31, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"D3_PST" , 32, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"D2_PST" , 33, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"D1_PST" , 34, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"D0_PST" , 35, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_39" , 36, 4, 439, "RAZ", 1, 1, 0, 0},
|
|
{"DS_MEM" , 40, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"D4_MEM" , 41, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"D3_MEM" , 42, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"D2_MEM" , 43, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"D1_MEM" , 44, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"D0_MEM" , 45, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_POP1" , 46, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_POP0" , 47, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_48_49" , 48, 2, 439, "RAZ", 1, 1, 0, 0},
|
|
{"PKT_POF" , 50, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_PFM" , 51, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_IMEM" , 52, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCSR_SL" , 53, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCSR_ID" , 54, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCSR_CNT" , 55, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCSR_IM" , 56, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCSR_INT" , 57, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_PIF" , 58, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCR_GIM" , 59, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_60_62" , 60, 3, 439, "RAZ", 1, 1, 0, 0},
|
|
{"PKT_RDF" , 63, 1, 439, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_BLK" , 0, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_GL" , 1, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_GD" , 2, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"PSC_P1" , 3, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"PSC_P0" , 4, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKT_RD" , 5, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"NWE_WR1" , 6, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"NWE_WR0" , 7, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"NWE_ST" , 8, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"NRD_ST" , 9, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRD_ERR" , 10, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRD_ST1" , 11, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRD_ST0" , 12, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRD_TAG" , 13, 1, 440, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 440, "RAZ", 1, 1, 0, 0},
|
|
{"WAIT_COM" , 0, 1, 441, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAR2_CAX" , 1, 1, 441, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAR2_ESX" , 2, 2, 441, "R/W", 0, 1, 0ull, 0},
|
|
{"BAR2_ENB" , 4, 1, 441, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PTLP_RO" , 5, 1, 441, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_6_6" , 6, 1, 441, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CTLP_RO" , 7, 1, 441, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INTA_MAP" , 8, 2, 441, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTB_MAP" , 10, 2, 441, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INTC_MAP" , 12, 2, 441, "R/W", 0, 0, 2ull, 2ull},
|
|
{"INTD_MAP" , 14, 2, 441, "R/W", 0, 0, 3ull, 3ull},
|
|
{"INTA" , 16, 1, 441, "RO", 0, 0, 1ull, 1ull},
|
|
{"INTB" , 17, 1, 441, "RO", 0, 0, 1ull, 1ull},
|
|
{"INTC" , 18, 1, 441, "RO", 0, 0, 1ull, 1ull},
|
|
{"INTD" , 19, 1, 441, "RO", 0, 0, 1ull, 1ull},
|
|
{"WAITL_COM" , 20, 1, 441, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_21_63" , 21, 43, 441, "RAZ", 1, 1, 0, 0},
|
|
{"WAIT_COM" , 0, 1, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAR2_CAX" , 1, 1, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BAR2_ESX" , 2, 2, 442, "R/W", 0, 1, 0ull, 0},
|
|
{"BAR2_ENB" , 4, 1, 442, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PTLP_RO" , 5, 1, 442, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_6_6" , 6, 1, 442, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CTLP_RO" , 7, 1, 442, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INTA_MAP" , 8, 2, 442, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTB_MAP" , 10, 2, 442, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INTC_MAP" , 12, 2, 442, "R/W", 0, 0, 2ull, 2ull},
|
|
{"INTD_MAP" , 14, 2, 442, "R/W", 0, 0, 3ull, 3ull},
|
|
{"INTA" , 16, 1, 442, "RO", 0, 0, 1ull, 1ull},
|
|
{"INTB" , 17, 1, 442, "RO", 0, 0, 1ull, 1ull},
|
|
{"INTC" , 18, 1, 442, "RO", 0, 0, 1ull, 1ull},
|
|
{"INTD" , 19, 1, 442, "RO", 0, 0, 1ull, 1ull},
|
|
{"WAITL_COM" , 20, 1, 442, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_21_63" , 21, 43, 442, "RAZ", 1, 1, 0, 0},
|
|
{"CHIP_REV" , 0, 8, 443, "RO", 1, 1, 0, 0},
|
|
{"HOST_MODE" , 8, 1, 443, "RO", 1, 1, 0, 0},
|
|
{"PKT_BP" , 9, 4, 443, "R/W", 0, 0, 15ull, 15ull},
|
|
{"ARB" , 13, 1, 443, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LNK_RST" , 14, 1, 443, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RING_EN" , 15, 1, 443, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CFG_RTRY" , 16, 16, 443, "R/W", 0, 0, 0ull, 32ull},
|
|
{"P0_NTAGS" , 32, 6, 443, "R/W", 0, 0, 32ull, 32ull},
|
|
{"P1_NTAGS" , 38, 6, 443, "R/W", 0, 0, 32ull, 32ull},
|
|
{"RESERVED_44_63" , 44, 20, 443, "RAZ", 1, 1, 0, 0},
|
|
{"C0_B0_D" , 0, 1, 444, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C0_WI_D" , 1, 1, 444, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C1_B0_D" , 2, 1, 444, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C1_WI_D" , 3, 1, 444, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C0_B1_S" , 4, 3, 444, "R/W", 0, 0, 1ull, 1ull},
|
|
{"C1_B1_S" , 7, 3, 444, "R/W", 0, 0, 1ull, 1ull},
|
|
{"C0_W_FLT" , 10, 1, 444, "R/W", 0, 0, 0ull, 0ull},
|
|
{"C1_W_FLT" , 11, 1, 444, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRRS" , 12, 3, 444, "R/W", 0, 0, 2ull, 2ull},
|
|
{"MPS" , 15, 1, 444, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 444, "RAZ", 1, 1, 0, 0},
|
|
{"P0_FCNT" , 0, 6, 445, "RO", 0, 1, 0ull, 0},
|
|
{"P0_UCNT" , 6, 16, 445, "RO", 0, 1, 0ull, 0},
|
|
{"P1_FCNT" , 22, 6, 445, "RO", 0, 1, 0ull, 0},
|
|
{"P1_UCNT" , 28, 16, 445, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 445, "RAZ", 1, 1, 0, 0},
|
|
{"DATA" , 0, 17, 446, "RO", 0, 1, 0ull, 0},
|
|
{"DSEL_EXT" , 17, 1, 446, "R/W", 0, 0, 1ull, 0ull},
|
|
{"C_MUL" , 18, 5, 446, "RO", 1, 1, 0, 0},
|
|
{"QLM1_SPD" , 23, 2, 446, "RO", 1, 1, 0, 0},
|
|
{"QLM1_MODE" , 25, 2, 446, "RO", 1, 1, 0, 0},
|
|
{"QLM0_REV_LANES" , 27, 1, 446, "RO", 1, 1, 0, 0},
|
|
{"QLM0_LINK_WIDTH" , 28, 1, 446, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_29_63" , 29, 35, 446, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_SEL" , 0, 16, 447, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 447, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 32, 448, "RO", 0, 0, 0ull, 0ull},
|
|
{"FCNT" , 32, 7, 448, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_39_63" , 39, 25, 448, "RAZ", 1, 1, 0, 0},
|
|
{"DBELL" , 0, 16, 449, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_31" , 16, 16, 449, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_6" , 0, 7, 450, "RAZ", 1, 1, 0, 0},
|
|
{"SADDR" , 7, 29, 450, "R/W", 0, 1, 0ull, 0},
|
|
{"IDLE" , 36, 1, 450, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_37_63" , 37, 27, 450, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 451, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 451, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 452, "R/W", 0, 1, 0ull, 0},
|
|
{"TIME" , 32, 32, 452, "R/W", 0, 1, 0ull, 0},
|
|
{"CNT" , 0, 32, 453, "R/W", 0, 1, 0ull, 0},
|
|
{"TIME" , 32, 32, 453, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA0" , 0, 32, 454, "R/W", 0, 1, 0ull, 0},
|
|
{"DMA1" , 32, 32, 454, "R/W", 0, 1, 0ull, 0},
|
|
{"CSIZE" , 0, 14, 455, "R/W", 0, 1, 0ull, 0},
|
|
{"O_MODE" , 14, 1, 455, "R/W", 0, 0, 0ull, 1ull},
|
|
{"O_ES" , 15, 2, 455, "R/W", 0, 1, 0ull, 0},
|
|
{"O_NS" , 17, 1, 455, "R/W", 0, 1, 0ull, 0},
|
|
{"O_RO" , 18, 1, 455, "R/W", 0, 1, 0ull, 0},
|
|
{"O_ADD1" , 19, 1, 455, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA_QUE" , 20, 3, 455, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB_ICHK" , 23, 9, 455, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB_DENB" , 32, 1, 455, "R/W", 0, 0, 0ull, 1ull},
|
|
{"B0_LEND" , 33, 1, 455, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA0_ENB" , 34, 1, 455, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1_ENB" , 35, 1, 455, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA2_ENB" , 36, 1, 455, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA3_ENB" , 37, 1, 455, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA4_ENB" , 38, 1, 455, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P_32B_M" , 39, 1, 455, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 455, "RAZ", 1, 1, 0, 0},
|
|
{"DMA_CNT" , 0, 5, 456, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 456, "RAZ", 1, 1, 0, 0},
|
|
{"DMA0_CNT" , 8, 5, 456, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_13_15" , 13, 3, 456, "RAZ", 1, 1, 0, 0},
|
|
{"DMA1_CNT" , 16, 5, 456, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_21_23" , 21, 3, 456, "RAZ", 1, 1, 0, 0},
|
|
{"DMA2_CNT" , 24, 5, 456, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_29_31" , 29, 3, 456, "RAZ", 1, 1, 0, 0},
|
|
{"DMA3_CNT" , 32, 5, 456, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_37_39" , 37, 3, 456, "RAZ", 1, 1, 0, 0},
|
|
{"DMA4_CNT" , 40, 5, 456, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_45_47" , 45, 3, 456, "RAZ", 1, 1, 0, 0},
|
|
{"PKT_CNT" , 48, 5, 456, "R/W", 0, 1, 16ull, 0},
|
|
{"RESERVED_53_62" , 53, 10, 456, "RAZ", 1, 1, 0, 0},
|
|
{"DMA_ARB" , 63, 1, 456, "R/W", 0, 1, 1ull, 0},
|
|
{"D0_DWE" , 0, 8, 457, "RO", 0, 1, 1ull, 0},
|
|
{"D1_DWE" , 8, 8, 457, "RO", 0, 1, 1ull, 0},
|
|
{"D2_DWE" , 16, 8, 457, "RO", 0, 1, 1ull, 0},
|
|
{"D3_DWE" , 24, 8, 457, "RO", 0, 1, 1ull, 0},
|
|
{"D4_DWE" , 32, 8, 457, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_40_63" , 40, 24, 457, "RAZ", 1, 1, 0, 0},
|
|
{"PRD" , 0, 10, 458, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_10_15" , 10, 6, 458, "RAZ", 1, 1, 0, 0},
|
|
{"NDRE" , 16, 5, 458, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_21_23" , 21, 3, 458, "RAZ", 1, 1, 0, 0},
|
|
{"NDWE" , 24, 4, 458, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_28_63" , 28, 36, 458, "RAZ", 1, 1, 0, 0},
|
|
{"DMA0_CPL" , 0, 1, 459, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1_CPL" , 1, 1, 459, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PINS_ERR" , 2, 1, 459, "R/W", 0, 0, 0ull, 1ull},
|
|
{"POP_ERR" , 3, 1, 459, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PDI_ERR" , 4, 1, 459, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PGL_ERR" , 5, 1, 459, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P0_RDLK" , 6, 1, 459, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_RDLK" , 7, 1, 459, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PIN_BP" , 8, 1, 459, "R/W", 0, 0, 0ull, 1ull},
|
|
{"POUT_ERR" , 9, 1, 459, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_10_63" , 10, 54, 459, "RAZ", 0, 1, 0ull, 0},
|
|
{"DMA0_CPL" , 0, 1, 460, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1_CPL" , 1, 1, 460, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PINS_ERR" , 2, 1, 460, "R/W", 0, 0, 0ull, 1ull},
|
|
{"POP_ERR" , 3, 1, 460, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PDI_ERR" , 4, 1, 460, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PGL_ERR" , 5, 1, 460, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P0_RDLK" , 6, 1, 460, "R/W", 0, 0, 0ull, 1ull},
|
|
{"P1_RDLK" , 7, 1, 460, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PIN_BP" , 8, 1, 460, "R/W", 0, 0, 0ull, 1ull},
|
|
{"POUT_ERR" , 9, 1, 460, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_10_63" , 10, 54, 460, "RAZ", 0, 1, 0ull, 0},
|
|
{"DMA0_CPL" , 0, 1, 461, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1_CPL" , 1, 1, 461, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PINS_ERR" , 2, 1, 461, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"POP_ERR" , 3, 1, 461, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PDI_ERR" , 4, 1, 461, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PGL_ERR" , 5, 1, 461, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P0_RDLK" , 6, 1, 461, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"P1_RDLK" , 7, 1, 461, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PIN_BP" , 8, 1, 461, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"POUT_ERR" , 9, 1, 461, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 461, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RML_RTO" , 0, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RML_WTO" , 1, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BAR0_TO" , 2, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOB2BIG" , 3, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA0DBO" , 4, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1DBO" , 5, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA2DBO" , 6, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA3DBO" , 7, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA4DBO" , 8, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA0FI" , 9, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1FI" , 10, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DCNT0" , 11, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DCNT1" , 12, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DTIME0" , 13, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DTIME1" , 14, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSLDBOF" , 15, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PIDBOF" , 16, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCNT" , 17, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PTIME" , 18, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_AERI" , 19, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CRS0_ER" , 20, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_SE" , 21, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CRS0_DR" , 22, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_WAKE" , 23, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_PMEI" , 24, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_HPINT" , 25, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_AERI" , 26, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CRS1_ER" , 27, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_SE" , 28, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CRS1_DR" , 29, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_WAKE" , 30, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_PMEI" , 31, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_HPINT" , 32, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_B0" , 33, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_B1" , 34, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_B2" , 35, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_WI" , 36, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_BX" , 37, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_B0" , 38, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_B1" , 39, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_B2" , 40, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_WI" , 41, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_BX" , 42, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_B0" , 43, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_B1" , 44, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_B2" , 45, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_WI" , 46, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_BX" , 47, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_B0" , 48, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_B1" , 49, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_B2" , 50, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_WI" , 51, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_BX" , 52, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_WF" , 53, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_WF" , 54, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_WF" , 55, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_WF" , 56, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_EXC" , 57, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_EXC" , 58, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_LDWN" , 59, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_LDWN" , 60, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INT_A" , 61, 1, 462, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_62_62" , 62, 1, 462, "RAZ", 0, 1, 0ull, 0},
|
|
{"MIO_INTA" , 63, 1, 462, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RML_RTO" , 0, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RML_WTO" , 1, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BAR0_TO" , 2, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOB2BIG" , 3, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA0DBO" , 4, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1DBO" , 5, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA2DBO" , 6, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA3DBO" , 7, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA4DBO" , 8, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA0FI" , 9, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DMA1FI" , 10, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DCNT0" , 11, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DCNT1" , 12, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DTIME0" , 13, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DTIME1" , 14, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSLDBOF" , 15, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PIDBOF" , 16, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PCNT" , 17, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PTIME" , 18, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_AERI" , 19, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CRS0_ER" , 20, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_SE" , 21, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CRS0_DR" , 22, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_WAKE" , 23, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_PMEI" , 24, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_HPINT" , 25, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_AERI" , 26, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CRS1_ER" , 27, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_SE" , 28, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"CRS1_DR" , 29, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_WAKE" , 30, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_PMEI" , 31, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_HPINT" , 32, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_B0" , 33, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_B1" , 34, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_B2" , 35, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_WI" , 36, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_BX" , 37, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_B0" , 38, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_B1" , 39, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_B2" , 40, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_WI" , 41, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_BX" , 42, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_B0" , 43, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_B1" , 44, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_B2" , 45, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_WI" , 46, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_BX" , 47, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_B0" , 48, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_B1" , 49, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_B2" , 50, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_WI" , 51, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_BX" , 52, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UN_WF" , 53, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UN_WF" , 54, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_UP_WF" , 55, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_UP_WF" , 56, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_EXC" , 57, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_EXC" , 58, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C0_LDWN" , 59, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"C1_LDWN" , 60, 1, 463, "R/W", 0, 0, 0ull, 1ull},
|
|
{"INT_A" , 61, 1, 463, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_62_63" , 62, 2, 463, "RAZ", 0, 1, 0ull, 0},
|
|
{"PSLDBOF" , 0, 6, 464, "RO", 0, 1, 0ull, 0},
|
|
{"PIDBOF" , 6, 6, 464, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_12_63" , 12, 52, 464, "RAZ", 1, 1, 0, 0},
|
|
{"RML_RTO" , 0, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RML_WTO" , 1, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BAR0_TO" , 2, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IOB2BIG" , 3, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA0DBO" , 4, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1DBO" , 5, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA2DBO" , 6, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA3DBO" , 7, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA4DBO" , 8, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA0FI" , 9, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DMA1FI" , 10, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT0" , 11, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCNT1" , 12, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME0" , 13, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DTIME1" , 14, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PSLDBOF" , 15, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PIDBOF" , 16, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PCNT" , 17, 1, 465, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTIME" , 18, 1, 465, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_AERI" , 19, 1, 465, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRS0_ER" , 20, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_SE" , 21, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CRS0_DR" , 22, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_WAKE" , 23, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_PMEI" , 24, 1, 465, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_HPINT" , 25, 1, 465, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_AERI" , 26, 1, 465, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRS1_ER" , 27, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_SE" , 28, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CRS1_DR" , 29, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_WAKE" , 30, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_PMEI" , 31, 1, 465, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_HPINT" , 32, 1, 465, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_B0" , 33, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_B1" , 34, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_B2" , 35, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_WI" , 36, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_BX" , 37, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_B0" , 38, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_B1" , 39, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_B2" , 40, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_WI" , 41, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_BX" , 42, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_B0" , 43, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_B1" , 44, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_B2" , 45, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_WI" , 46, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_BX" , 47, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_B0" , 48, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_B1" , 49, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_B2" , 50, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_WI" , 51, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_BX" , 52, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_WF" , 53, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_WF" , 54, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_WF" , 55, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_WF" , 56, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C0_EXC" , 57, 1, 465, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_EXC" , 58, 1, 465, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_LDWN" , 59, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"C1_LDWN" , 60, 1, 465, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INT_A" , 61, 1, 465, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_62_62" , 62, 1, 465, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO_INTA" , 63, 1, 465, "RO", 0, 0, 0ull, 0ull},
|
|
{"RML_RTO" , 0, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"RML_WTO" , 1, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"BAR0_TO" , 2, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"IOB2BIG" , 3, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"DMA0DBO" , 4, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"DMA1DBO" , 5, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"DMA2DBO" , 6, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"DMA3DBO" , 7, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_8" , 8, 1, 466, "RAZ", 1, 1, 0, 0},
|
|
{"DMA0FI" , 9, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"DMA1FI" , 10, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"DCNT0" , 11, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"DCNT1" , 12, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTIME0" , 13, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTIME1" , 14, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_18" , 15, 4, 466, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"C0_AERI" , 19, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRS0_ER" , 20, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_SE" , 21, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRS0_DR" , 22, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_WAKE" , 23, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_PMEI" , 24, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_HPINT" , 25, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_AERI" , 26, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRS1_ER" , 27, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_SE" , 28, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"CRS1_DR" , 29, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_WAKE" , 30, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_PMEI" , 31, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_HPINT" , 32, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_B0" , 33, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_B1" , 34, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_B2" , 35, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_WI" , 36, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_BX" , 37, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_B0" , 38, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_B1" , 39, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_B2" , 40, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_WI" , 41, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_BX" , 42, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_B0" , 43, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_B1" , 44, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_B2" , 45, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_WI" , 46, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_BX" , 47, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_B0" , 48, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_B1" , 49, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_B2" , 50, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_WI" , 51, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_BX" , 52, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UN_WF" , 53, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UN_WF" , 54, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_UP_WF" , 55, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_UP_WF" , 56, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_EXC" , 57, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_EXC" , 58, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C0_LDWN" , 59, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"C1_LDWN" , 60, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"INT_A" , 61, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_62_62" , 62, 1, 466, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO_INTA" , 63, 1, 466, "RO", 0, 0, 0ull, 0ull},
|
|
{"DATA" , 0, 64, 467, "RO", 0, 1, 0ull, 0},
|
|
{"DATA" , 0, 64, 468, "RO", 0, 1, 0ull, 0},
|
|
{"TIMER" , 0, 10, 469, "R/W", 0, 0, 0ull, 50ull},
|
|
{"MAX_WORD" , 10, 4, 469, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 469, "RAZ", 1, 1, 0, 0},
|
|
{"BA" , 0, 30, 470, "R/W", 0, 1, 0ull, 0},
|
|
{"ROW" , 30, 1, 470, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR" , 31, 1, 470, "R/W", 0, 1, 0ull, 0},
|
|
{"NSW" , 32, 1, 470, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR" , 33, 1, 470, "R/W", 0, 1, 0ull, 0},
|
|
{"ESW" , 34, 2, 470, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR" , 36, 2, 470, "R/W", 0, 1, 0ull, 0},
|
|
{"NMERGE" , 38, 1, 470, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PORT" , 39, 2, 470, "R/W", 0, 1, 0ull, 0},
|
|
{"ZERO" , 41, 1, 470, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_42_63" , 42, 22, 470, "RAZ", 1, 1, 0, 0},
|
|
{"ENB" , 0, 64, 471, "R/W", 0, 0, 0ull, 18446744073709551615ull},
|
|
{"ENB" , 0, 64, 472, "R/W", 0, 0, 0ull, 18446744073709551615ull},
|
|
{"ENB" , 0, 64, 473, "R/W", 0, 0, 0ull, 18446744073709551615ull},
|
|
{"ENB" , 0, 64, 474, "R/W", 0, 0, 0ull, 18446744073709551615ull},
|
|
{"INTR" , 0, 64, 475, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTR" , 0, 64, 476, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTR" , 0, 64, 477, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTR" , 0, 64, 478, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MSI_INT" , 0, 8, 479, "R/W", 0, 1, 0ull, 0},
|
|
{"RD_INT" , 8, 8, 479, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 479, "RAZ", 1, 1, 0, 0},
|
|
{"CLR" , 0, 64, 480, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLR" , 0, 64, 481, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLR" , 0, 64, 482, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CLR" , 0, 64, 483, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SET" , 0, 64, 484, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SET" , 0, 64, 485, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SET" , 0, 64, 486, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SET" , 0, 64, 487, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSI_INT" , 0, 8, 488, "R/W", 0, 1, 0ull, 0},
|
|
{"CIU_INT" , 8, 8, 488, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 488, "RAZ", 1, 1, 0, 0},
|
|
{"P0_PCNT" , 0, 8, 489, "R/W", 0, 0, 128ull, 128ull},
|
|
{"P0_NCNT" , 8, 8, 489, "R/W", 0, 0, 16ull, 16ull},
|
|
{"P0_CCNT" , 16, 8, 489, "R/W", 0, 0, 128ull, 128ull},
|
|
{"P1_PCNT" , 24, 8, 489, "R/W", 0, 0, 128ull, 128ull},
|
|
{"P1_NCNT" , 32, 8, 489, "R/W", 0, 0, 16ull, 16ull},
|
|
{"P1_CCNT" , 40, 8, 489, "R/W", 0, 0, 128ull, 128ull},
|
|
{"RESERVED_48_63" , 48, 16, 489, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 0, 8, 490, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 490, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 491, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 8, 8, 491, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 491, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_15" , 0, 16, 492, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 16, 8, 492, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_24_63" , 24, 40, 492, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_23" , 0, 24, 493, "RAZ", 1, 1, 0, 0},
|
|
{"INTR" , 24, 8, 493, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 493, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 494, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMER" , 32, 22, 494, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_54_63" , 54, 10, 494, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 495, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WMARK" , 32, 32, 495, "R/W", 0, 1, 4294967295ull, 0},
|
|
{"RESERVED_0_2" , 0, 3, 496, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 3, 61, 496, "R/W", 0, 1, 0ull, 0},
|
|
{"DBELL" , 0, 32, 497, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AOFF" , 32, 32, 497, "RO", 0, 1, 0ull, 0},
|
|
{"RSIZE" , 0, 32, 498, "R/W", 0, 1, 0ull, 0},
|
|
{"FCNT" , 32, 5, 498, "RO", 0, 1, 0ull, 0},
|
|
{"WRP" , 37, 9, 498, "RO", 0, 1, 0ull, 0},
|
|
{"RRP" , 46, 9, 498, "RO", 0, 1, 0ull, 0},
|
|
{"MAX" , 55, 9, 498, "RO", 0, 1, 16ull, 0},
|
|
{"RESERVED_0_5" , 0, 6, 499, "RAZ", 0, 1, 0ull, 0},
|
|
{"SKP_LEN" , 6, 7, 499, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_13_13" , 13, 1, 499, "RAZ", 0, 1, 0ull, 0},
|
|
{"PAR_MODE" , 14, 2, 499, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_20" , 16, 5, 499, "RAZ", 0, 1, 0ull, 0},
|
|
{"USE_IHDR" , 21, 1, 499, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_22_27" , 22, 6, 499, "R/W", 0, 1, 0ull, 0},
|
|
{"RSKP_LEN" , 28, 7, 499, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_35_35" , 35, 1, 499, "RAZ", 0, 1, 0ull, 0},
|
|
{"RPARMODE" , 36, 2, 499, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_38_42" , 38, 5, 499, "RAZ", 0, 1, 0ull, 0},
|
|
{"PBP" , 43, 1, 499, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_44_63" , 44, 20, 499, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_3" , 0, 4, 500, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 4, 60, 500, "R/W", 0, 1, 0ull, 0},
|
|
{"DBELL" , 0, 32, 501, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AOFF" , 32, 32, 501, "RO", 0, 1, 0ull, 0},
|
|
{"RSIZE" , 0, 32, 502, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 502, "RAZ", 0, 1, 0ull, 0},
|
|
{"PORT" , 0, 32, 503, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 503, "RAZ", 1, 1, 0, 0},
|
|
{"PORT" , 0, 32, 504, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 504, "RAZ", 1, 1, 0, 0},
|
|
{"ES" , 0, 64, 505, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR" , 0, 32, 506, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 506, "RAZ", 1, 1, 0, 0},
|
|
{"ROR" , 0, 32, 507, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 507, "RAZ", 1, 1, 0, 0},
|
|
{"DPTR" , 0, 32, 508, "R/W", 0, 0, 0ull, 4294967295ull},
|
|
{"RESERVED_32_63" , 32, 32, 508, "RAZ", 1, 1, 0, 0},
|
|
{"BP" , 0, 32, 509, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 509, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 510, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 510, "RAZ", 0, 1, 0ull, 0},
|
|
{"RD_CNT" , 0, 32, 511, "RO", 0, 1, 0ull, 0},
|
|
{"WR_CNT" , 32, 32, 511, "RO", 0, 1, 0ull, 0},
|
|
{"PP" , 0, 64, 512, "R/W", 0, 1, 0ull, 0},
|
|
{"ROR" , 0, 1, 513, "R/W", 0, 1, 0ull, 0},
|
|
{"ESR" , 1, 2, 513, "R/W", 0, 1, 0ull, 0},
|
|
{"NSR" , 3, 1, 513, "R/W", 0, 1, 0ull, 0},
|
|
{"USE_CSR" , 4, 1, 513, "R/W", 0, 0, 0ull, 1ull},
|
|
{"D_ROR" , 5, 1, 513, "R/W", 0, 1, 0ull, 0},
|
|
{"D_ESR" , 6, 2, 513, "R/W", 0, 1, 0ull, 0},
|
|
{"D_NSR" , 8, 1, 513, "R/W", 0, 1, 0ull, 0},
|
|
{"PBP_DHI" , 9, 13, 513, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKT_RR" , 22, 1, 513, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_23_63" , 23, 41, 513, "RAZ", 1, 1, 0, 0},
|
|
{"ENB" , 0, 32, 514, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 514, "RAZ", 1, 1, 0, 0},
|
|
{"RDSIZE" , 0, 64, 515, "R/W", 0, 1, 0ull, 0},
|
|
{"IS_64B" , 0, 32, 516, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 516, "RAZ", 1, 1, 0, 0},
|
|
{"CNT" , 0, 32, 517, "R/W", 0, 1, 0ull, 0},
|
|
{"TIME" , 32, 22, 517, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_54_63" , 54, 10, 517, "RAZ", 1, 1, 0, 0},
|
|
{"IPTR" , 0, 32, 518, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 518, "RAZ", 1, 1, 0, 0},
|
|
{"BMODE" , 0, 32, 519, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 519, "RAZ", 1, 1, 0, 0},
|
|
{"ENB" , 0, 32, 520, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 520, "RAZ", 1, 1, 0, 0},
|
|
{"WMARK" , 0, 32, 521, "R/W", 0, 0, 0ull, 14ull},
|
|
{"RESERVED_32_63" , 32, 32, 521, "RAZ", 1, 1, 0, 0},
|
|
{"PP" , 0, 64, 522, "R/W", 0, 1, 0ull, 0},
|
|
{"OUT_RST" , 0, 32, 523, "RO", 0, 1, 0ull, 0},
|
|
{"IN_RST" , 32, 32, 523, "RO", 0, 1, 0ull, 0},
|
|
{"ES" , 0, 64, 524, "R/W", 0, 1, 0ull, 0},
|
|
{"BSIZE" , 0, 16, 525, "R/W", 0, 1, 0ull, 0},
|
|
{"ISIZE" , 16, 7, 525, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_23_63" , 23, 41, 525, "RAZ", 1, 1, 0, 0},
|
|
{"NSR" , 0, 32, 526, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 526, "RAZ", 1, 1, 0, 0},
|
|
{"ROR" , 0, 32, 527, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 527, "RAZ", 1, 1, 0, 0},
|
|
{"PORT" , 0, 32, 528, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 528, "RAZ", 1, 1, 0, 0},
|
|
{"PORT" , 0, 32, 529, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 529, "RAZ", 1, 1, 0, 0},
|
|
{"MIO" , 0, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX0" , 1, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"GMX1" , 2, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPEI" , 3, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"KEY" , 4, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"FPA" , 5, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"DFA" , 6, 1, 530, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ZIP" , 7, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_8" , 8, 1, 530, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"IPD" , 9, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 10, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"TIM" , 11, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"POW" , 12, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"USB" , 13, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"RAD" , 14, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"USB1" , 15, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"L2C" , 16, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"LMC0" , 17, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"SPX0" , 18, 1, 530, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"SPX1" , 19, 1, 530, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PIP" , 20, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_21" , 21, 1, 530, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ASXPCS0" , 22, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASXPCS1" , 23, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_24_27" , 24, 4, 530, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"AGL" , 28, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"LMC1" , 29, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"IOB" , 30, 1, 530, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 530, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DATA" , 0, 64, 531, "R/W", 0, 1, 0ull, 0},
|
|
{"CSR" , 0, 39, 532, "RO", 0, 1, 1ull, 0},
|
|
{"ARB" , 39, 1, 532, "RO", 0, 1, 0ull, 0},
|
|
{"CPL0" , 40, 12, 532, "RO", 0, 1, 1ull, 0},
|
|
{"CPL1" , 52, 12, 532, "RO", 0, 1, 1ull, 0},
|
|
{"NND" , 0, 8, 533, "RO", 0, 1, 1ull, 0},
|
|
{"NNP0" , 8, 8, 533, "RO", 0, 1, 1ull, 0},
|
|
{"CSM0" , 16, 15, 533, "RO", 0, 1, 1ull, 0},
|
|
{"CSM1" , 31, 15, 533, "RO", 0, 1, 1ull, 0},
|
|
{"RAC" , 46, 1, 533, "RO", 0, 1, 1ull, 0},
|
|
{"NPEI" , 47, 1, 533, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 533, "RAZ", 1, 1, 0, 0},
|
|
{"NSM0" , 0, 13, 534, "RO", 0, 1, 1ull, 0},
|
|
{"NSM1" , 13, 13, 534, "RO", 0, 1, 1ull, 0},
|
|
{"PSM0" , 26, 15, 534, "RO", 0, 1, 1ull, 0},
|
|
{"PSM1" , 41, 15, 534, "RO", 0, 1, 1ull, 0},
|
|
{"RESERVED_56_63" , 56, 8, 534, "RAZ", 1, 1, 0, 0},
|
|
{"RD_ADDR" , 0, 48, 535, "R/W", 0, 1, 0ull, 0},
|
|
{"IOBIT" , 48, 1, 535, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LD_CMD" , 49, 2, 535, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_51_63" , 51, 13, 535, "RAZ", 1, 1, 0, 0},
|
|
{"RD_DATA" , 0, 64, 536, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_0_1" , 0, 2, 537, "RAZ", 1, 1, 0, 0},
|
|
{"WR_ADDR" , 2, 46, 537, "R/W", 0, 1, 0ull, 0},
|
|
{"IOBIT" , 48, 1, 537, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 537, "RAZ", 1, 1, 0, 0},
|
|
{"WR_DATA" , 0, 64, 538, "R/W", 0, 1, 0ull, 0},
|
|
{"WR_MASK" , 0, 8, 539, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 539, "RAZ", 1, 1, 0, 0},
|
|
{"TIME" , 0, 32, 540, "R/W", 0, 0, 0ull, 2097152ull},
|
|
{"RESERVED_32_63" , 32, 32, 540, "RAZ", 1, 1, 0, 0},
|
|
{"VENDID" , 0, 16, 541, "RO/WRSL", 0, 0, 6013ull, 6013ull},
|
|
{"DEVID" , 16, 16, 541, "RO/WRSL", 0, 0, 128ull, 128ull},
|
|
{"ISAE" , 0, 1, 542, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSAE" , 1, 1, 542, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ME" , 2, 1, 542, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SCSE" , 3, 1, 542, "RO", 0, 0, 0ull, 0ull},
|
|
{"MWICE" , 4, 1, 542, "RO", 0, 0, 0ull, 0ull},
|
|
{"VPS" , 5, 1, 542, "RO", 0, 0, 0ull, 0ull},
|
|
{"PER" , 6, 1, 542, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDS_WCC" , 7, 1, 542, "RO", 0, 0, 0ull, 0ull},
|
|
{"SEE" , 8, 1, 542, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FBBE" , 9, 1, 542, "RO", 0, 0, 0ull, 0ull},
|
|
{"I_DIS" , 10, 1, 542, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_18" , 11, 8, 542, "RAZ", 1, 1, 0, 0},
|
|
{"I_STAT" , 19, 1, 542, "RO", 0, 0, 0ull, 0ull},
|
|
{"CL" , 20, 1, 542, "RO", 0, 0, 1ull, 1ull},
|
|
{"M66" , 21, 1, 542, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_22" , 22, 1, 542, "RAZ", 1, 1, 0, 0},
|
|
{"FBB" , 23, 1, 542, "RO", 0, 0, 0ull, 0ull},
|
|
{"MDPE" , 24, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DEVT" , 25, 2, 542, "RO", 0, 0, 0ull, 0ull},
|
|
{"STA" , 27, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTA" , 28, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RMA" , 29, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SSE" , 30, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPE" , 31, 1, 542, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RID" , 0, 8, 543, "RO/WRSL", 0, 0, 8ull, 8ull},
|
|
{"PI" , 8, 8, 543, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"SC" , 16, 8, 543, "RO/WRSL", 0, 0, 48ull, 48ull},
|
|
{"BCC" , 24, 8, 543, "RO/WRSL", 0, 0, 11ull, 11ull},
|
|
{"CLS" , 0, 8, 544, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LT" , 8, 8, 544, "RO", 0, 0, 0ull, 0ull},
|
|
{"CHF" , 16, 7, 544, "RO", 0, 0, 0ull, 0ull},
|
|
{"MFD" , 23, 1, 544, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"BIST" , 24, 8, 544, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSPC" , 0, 1, 545, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 545, "RO/WRSL", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 545, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_13" , 4, 10, 545, "RAZ", 1, 1, 0, 0},
|
|
{"LBAB" , 14, 18, 545, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 0, 1, 546, "WORSL", 0, 0, 1ull, 1ull},
|
|
{"LMASK" , 1, 31, 546, "WORSL", 0, 0, 8191ull, 8191ull},
|
|
{"UBAB" , 0, 32, 547, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMASK" , 0, 32, 548, "WORSL", 0, 0, 0ull, 0ull},
|
|
{"MSPC" , 0, 1, 549, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 549, "RO/WRSL", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 549, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_25" , 4, 22, 549, "RAZ", 1, 1, 0, 0},
|
|
{"LBAB" , 26, 6, 549, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 0, 1, 550, "WORSL", 0, 0, 1ull, 1ull},
|
|
{"LMASK" , 1, 31, 550, "WORSL", 0, 0, 33554431ull, 33554431ull},
|
|
{"UBAB" , 0, 32, 551, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMASK" , 0, 32, 552, "WORSL", 0, 0, 0ull, 0ull},
|
|
{"MSPC" , 0, 1, 553, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"TYP" , 1, 2, 553, "RO/WRSL", 0, 0, 2ull, 2ull},
|
|
{"PF" , 3, 1, 553, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_4_31" , 4, 28, 553, "RAZ", 1, 1, 0, 0},
|
|
{"ENB" , 0, 1, 554, "WORSL", 0, 0, 1ull, 1ull},
|
|
{"LMASK" , 1, 31, 554, "WORSL", 0, 0, 2147483647ull, 2147483647ull},
|
|
{"RESERVED_0_6" , 0, 7, 555, "RAZ", 1, 1, 0, 0},
|
|
{"UBAB" , 7, 25, 555, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMASK" , 0, 32, 556, "WORSL", 0, 0, 127ull, 127ull},
|
|
{"CISP" , 0, 32, 557, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"SSVID" , 0, 16, 558, "RO/WRSL", 0, 0, 6013ull, 6013ull},
|
|
{"SSID" , 16, 16, 558, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"ER_EN" , 0, 1, 559, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_15" , 1, 15, 559, "RAZ", 1, 1, 0, 0},
|
|
{"ERADDR" , 16, 16, 559, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENB" , 0, 1, 560, "WORSL", 0, 0, 1ull, 1ull},
|
|
{"MASK" , 1, 31, 560, "WORSL", 0, 0, 2147483647ull, 2147483647ull},
|
|
{"CP" , 0, 8, 561, "RO/WRSL", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_8_31" , 8, 24, 561, "RAZ", 1, 1, 0, 0},
|
|
{"IL" , 0, 8, 562, "R/W", 0, 0, 255ull, 255ull},
|
|
{"INTA" , 8, 8, 562, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"MG" , 16, 8, 562, "RO", 0, 0, 0ull, 0ull},
|
|
{"ML" , 24, 8, 562, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMCID" , 0, 8, 563, "RO", 0, 0, 1ull, 0ull},
|
|
{"NCP" , 8, 8, 563, "RO/WRSL", 0, 0, 80ull, 0ull},
|
|
{"PMSV" , 16, 3, 563, "RO/WRSL", 0, 0, 3ull, 0ull},
|
|
{"PME_CLOCK" , 19, 1, 563, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 563, "RAZ", 1, 1, 0, 0},
|
|
{"DSI" , 21, 1, 563, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"AUXC" , 22, 3, 563, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"D1S" , 25, 1, 563, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"D2S" , 26, 1, 563, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PMES" , 27, 5, 563, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PS" , 0, 2, 564, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 564, "RAZ", 1, 1, 0, 0},
|
|
{"NSR" , 3, 1, 564, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 564, "RAZ", 1, 1, 0, 0},
|
|
{"PMEENS" , 8, 1, 564, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMDS" , 9, 4, 564, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMEDSIA" , 13, 2, 564, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMESS" , 15, 1, 564, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_21" , 16, 6, 564, "RAZ", 1, 1, 0, 0},
|
|
{"BD3H" , 22, 1, 564, "RO", 0, 0, 0ull, 0ull},
|
|
{"BPCCEE" , 23, 1, 564, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMDIA" , 24, 8, 564, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSICID" , 0, 8, 565, "RO", 0, 0, 5ull, 5ull},
|
|
{"NCP" , 8, 8, 565, "RO/WRSL", 0, 0, 112ull, 112ull},
|
|
{"MSIEN" , 16, 1, 565, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MMC" , 17, 3, 565, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"MME" , 20, 3, 565, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M64" , 23, 1, 565, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_24_31" , 24, 8, 565, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 566, "RAZ", 1, 1, 0, 0},
|
|
{"LMSI" , 2, 30, 566, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSI" , 0, 32, 567, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSIMD" , 0, 16, 568, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_31" , 16, 16, 568, "RAZ", 1, 1, 0, 0},
|
|
{"PCIEID" , 0, 8, 569, "RO", 0, 0, 16ull, 16ull},
|
|
{"NCP" , 8, 8, 569, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PCIECV" , 16, 4, 569, "RO", 0, 0, 2ull, 2ull},
|
|
{"DPT" , 20, 4, 569, "RO", 0, 0, 0ull, 0ull},
|
|
{"SI" , 24, 1, 569, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"IMN" , 25, 5, 569, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_31" , 30, 2, 569, "RAZ", 1, 1, 0, 0},
|
|
{"MPSS" , 0, 3, 570, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"PFS" , 3, 2, 570, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"ETFS" , 5, 1, 570, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"EL0AL" , 6, 3, 570, "RO/WRSL", 0, 0, 4ull, 4ull},
|
|
{"EL1AL" , 9, 3, 570, "RO/WRSL", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_12_14" , 12, 3, 570, "RAZ", 1, 1, 0, 0},
|
|
{"RBER" , 15, 1, 570, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_16_17" , 16, 2, 570, "RAZ", 1, 1, 0, 0},
|
|
{"CSPLV" , 18, 8, 570, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSPLS" , 26, 2, 570, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_31" , 28, 4, 570, "RAZ", 1, 1, 0, 0},
|
|
{"CE_EN" , 0, 1, 571, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NFE_EN" , 1, 1, 571, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FE_EN" , 2, 1, 571, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UR_EN" , 3, 1, 571, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RO_EN" , 4, 1, 571, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MPS" , 5, 3, 571, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ETF_EN" , 8, 1, 571, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PF_EN" , 9, 1, 571, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AP_EN" , 10, 1, 571, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NS_EN" , 11, 1, 571, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MRRS" , 12, 3, 571, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_15_15" , 15, 1, 571, "RAZ", 1, 1, 0, 0},
|
|
{"CE_D" , 16, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NFE_D" , 17, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FE_D" , 18, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UR_D" , 19, 1, 571, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AP_D" , 20, 1, 571, "RO", 0, 0, 0ull, 0ull},
|
|
{"TP" , 21, 1, 571, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_31" , 22, 10, 571, "RAZ", 1, 1, 0, 0},
|
|
{"MLS" , 0, 4, 572, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"MLW" , 4, 6, 572, "RO/WRSL", 0, 0, 8ull, 8ull},
|
|
{"ASLPMS" , 10, 2, 572, "RO/WRSL", 0, 0, 3ull, 3ull},
|
|
{"L0EL" , 12, 3, 572, "RO/WRSL", 0, 0, 6ull, 6ull},
|
|
{"L1EL" , 15, 3, 572, "RO/WRSL", 0, 0, 6ull, 6ull},
|
|
{"CPM" , 18, 1, 572, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"SDERC" , 19, 1, 572, "RO", 0, 0, 0ull, 0ull},
|
|
{"DLLARC" , 20, 1, 572, "RO", 0, 0, 0ull, 0ull},
|
|
{"LBNC" , 21, 1, 572, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 572, "RAZ", 1, 1, 0, 0},
|
|
{"PNUM" , 24, 8, 572, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"ASLPC" , 0, 2, 573, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 573, "RAZ", 1, 1, 0, 0},
|
|
{"RCB" , 3, 1, 573, "RO", 0, 0, 0ull, 0ull},
|
|
{"LD" , 4, 1, 573, "RO", 0, 0, 0ull, 0ull},
|
|
{"RL" , 5, 1, 573, "RO", 0, 0, 0ull, 0ull},
|
|
{"CCC" , 6, 1, 573, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ES" , 7, 1, 573, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECPM" , 8, 1, 573, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HAWD" , 9, 1, 573, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_15" , 10, 6, 573, "RAZ", 1, 1, 0, 0},
|
|
{"LS" , 16, 4, 573, "RO", 0, 0, 1ull, 1ull},
|
|
{"NLW" , 20, 6, 573, "RO", 0, 0, 0ull, 8ull},
|
|
{"RESERVED_26_26" , 26, 1, 573, "RAZ", 1, 1, 0, 0},
|
|
{"LT" , 27, 1, 573, "RO", 0, 0, 0ull, 0ull},
|
|
{"SCC" , 28, 1, 573, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"DLLA" , 29, 1, 573, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_31" , 30, 2, 573, "RAZ", 1, 1, 0, 0},
|
|
{"ABP" , 0, 1, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PCP" , 1, 1, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"MRLSP" , 2, 1, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"AIP" , 3, 1, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PIP" , 4, 1, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"HP_S" , 5, 1, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"HP_C" , 6, 1, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"SP_LV" , 7, 8, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"SP_LS" , 15, 2, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"EMIP" , 17, 1, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"NCCS" , 18, 1, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"PS_NUM" , 19, 13, 574, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"ABP_EN" , 0, 1, 575, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PF_EN" , 1, 1, 575, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRLS_EN" , 2, 1, 575, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PD_EN" , 3, 1, 575, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CCINT_EN" , 4, 1, 575, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HPINT_EN" , 5, 1, 575, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AIC" , 6, 2, 575, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PIC" , 8, 2, 575, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCC" , 10, 1, 575, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EMIC" , 11, 1, 575, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLLS_EN" , 12, 1, 575, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 575, "RAZ", 1, 1, 0, 0},
|
|
{"ABP_D" , 16, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PF_D" , 17, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRLS_C" , 18, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PD_C" , 19, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CCINT_D" , 20, 1, 575, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRLSS" , 21, 1, 575, "RO", 0, 0, 0ull, 0ull},
|
|
{"PDS" , 22, 1, 575, "RO", 0, 0, 0ull, 0ull},
|
|
{"EMIS" , 23, 1, 575, "RO", 0, 0, 0ull, 0ull},
|
|
{"DLLS_C" , 24, 1, 575, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_31" , 25, 7, 575, "RAZ", 1, 1, 0, 0},
|
|
{"CTRS" , 0, 4, 576, "RO", 0, 0, 0ull, 0ull},
|
|
{"CTDS" , 4, 1, 576, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_5_31" , 5, 27, 576, "RAZ", 1, 1, 0, 0},
|
|
{"CTV" , 0, 4, 577, "RO", 0, 0, 0ull, 0ull},
|
|
{"CTD" , 4, 1, 577, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 577, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 578, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 579, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 580, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 581, "RAZ", 1, 1, 0, 0},
|
|
{"PCIEEC" , 0, 16, 582, "RO", 0, 0, 1ull, 0ull},
|
|
{"CV" , 16, 4, 582, "RO", 0, 0, 1ull, 0ull},
|
|
{"NCO" , 20, 12, 582, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_3" , 0, 4, 583, "RAZ", 1, 1, 0, 0},
|
|
{"DLPES" , 4, 1, 583, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SDES" , 5, 1, 583, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_11" , 6, 6, 583, "RAZ", 1, 1, 0, 0},
|
|
{"PTLPS" , 12, 1, 583, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCPES" , 13, 1, 583, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CTS" , 14, 1, 583, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CAS" , 15, 1, 583, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UCS" , 16, 1, 583, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ROS" , 17, 1, 583, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MTLPS" , 18, 1, 583, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ECRCES" , 19, 1, 583, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"URES" , 20, 1, 583, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 583, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_3" , 0, 4, 584, "RAZ", 1, 1, 0, 0},
|
|
{"DLPEM" , 4, 1, 584, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SDEM" , 5, 1, 584, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_11" , 6, 6, 584, "RAZ", 1, 1, 0, 0},
|
|
{"PTLPM" , 12, 1, 584, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCPEM" , 13, 1, 584, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CTM" , 14, 1, 584, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAM" , 15, 1, 584, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UCM" , 16, 1, 584, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROM" , 17, 1, 584, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MTLPM" , 18, 1, 584, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECRCEM" , 19, 1, 584, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UREM" , 20, 1, 584, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 584, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_3" , 0, 4, 585, "RAZ", 1, 1, 0, 0},
|
|
{"DLPES" , 4, 1, 585, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SDES" , 5, 1, 585, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_11" , 6, 6, 585, "RAZ", 1, 1, 0, 0},
|
|
{"PTLPS" , 12, 1, 585, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCPES" , 13, 1, 585, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTS" , 14, 1, 585, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAS" , 15, 1, 585, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UCS" , 16, 1, 585, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROS" , 17, 1, 585, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MTLPS" , 18, 1, 585, "R/W", 0, 0, 1ull, 1ull},
|
|
{"ECRCES" , 19, 1, 585, "R/W", 0, 0, 0ull, 0ull},
|
|
{"URES" , 20, 1, 585, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 585, "RAZ", 1, 1, 0, 0},
|
|
{"RES" , 0, 1, 586, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_5" , 1, 5, 586, "RAZ", 1, 1, 0, 0},
|
|
{"BTLPS" , 6, 1, 586, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BDLLPS" , 7, 1, 586, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RNRS" , 8, 1, 586, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 586, "RAZ", 1, 1, 0, 0},
|
|
{"RTTS" , 12, 1, 586, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ANFES" , 13, 1, 586, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_31" , 14, 18, 586, "RAZ", 1, 1, 0, 0},
|
|
{"REM" , 0, 1, 587, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_5" , 1, 5, 587, "RAZ", 1, 1, 0, 0},
|
|
{"BTLPM" , 6, 1, 587, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BDLLPM" , 7, 1, 587, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNRM" , 8, 1, 587, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 587, "RAZ", 1, 1, 0, 0},
|
|
{"RTTM" , 12, 1, 587, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ANFEM" , 13, 1, 587, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_14_31" , 14, 18, 587, "RAZ", 1, 1, 0, 0},
|
|
{"FEP" , 0, 5, 588, "RO", 0, 0, 0ull, 0ull},
|
|
{"GC" , 5, 1, 588, "RO", 0, 0, 1ull, 1ull},
|
|
{"GE" , 6, 1, 588, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CC" , 7, 1, 588, "RO", 0, 0, 1ull, 1ull},
|
|
{"CE" , 8, 1, 588, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_31" , 9, 23, 588, "RAZ", 1, 1, 0, 0},
|
|
{"DWORD1" , 0, 32, 589, "RO", 0, 0, 0ull, 0ull},
|
|
{"DWORD2" , 0, 32, 590, "RO", 0, 0, 0ull, 0ull},
|
|
{"DWORD3" , 0, 32, 591, "RO", 0, 0, 0ull, 0ull},
|
|
{"DWORD4" , 0, 32, 592, "RO", 0, 0, 0ull, 0ull},
|
|
{"RTLTL" , 0, 16, 593, "R/W", 0, 0, 4143ull, 4143ull},
|
|
{"RTL" , 16, 16, 593, "R/W", 0, 0, 12429ull, 12429ull},
|
|
{"OMR" , 0, 32, 594, "R/W", 0, 1, 4294967295ull, 0},
|
|
{"LINK_NUM" , 0, 8, 595, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_14" , 8, 7, 595, "RAZ", 1, 1, 0, 0},
|
|
{"FORCE_LINK" , 15, 1, 595, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LINK_STATE" , 16, 6, 595, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 595, "RAZ", 1, 1, 0, 0},
|
|
{"LPEC" , 24, 8, 595, "R/W", 0, 0, 7ull, 7ull},
|
|
{"ACK_FREQ" , 0, 8, 596, "R/W", 0, 0, 0ull, 0ull},
|
|
{"N_FTS" , 8, 8, 596, "R/W", 0, 0, 128ull, 128ull},
|
|
{"N_FTS_CC" , 16, 8, 596, "R/W", 0, 0, 128ull, 128ull},
|
|
{"L0EL" , 24, 3, 596, "R/W", 0, 0, 3ull, 3ull},
|
|
{"L1EL" , 27, 3, 596, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_30_31" , 30, 2, 596, "RAZ", 1, 1, 0, 0},
|
|
{"OMR" , 0, 1, 597, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SD" , 1, 1, 597, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LE" , 2, 1, 597, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RA" , 3, 1, 597, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_4" , 4, 1, 597, "RAZ", 1, 1, 0, 0},
|
|
{"DLLLE" , 5, 1, 597, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_6" , 6, 1, 597, "RAZ", 1, 1, 0, 0},
|
|
{"FLM" , 7, 1, 597, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_15" , 8, 8, 597, "RO", 0, 0, 1ull, 1ull},
|
|
{"LME" , 16, 6, 597, "R/W", 0, 0, 7ull, 7ull},
|
|
{"RESERVED_22_24" , 22, 3, 597, "RAZ", 1, 1, 0, 0},
|
|
{"ECCRC" , 25, 1, 597, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_31" , 26, 6, 597, "RAZ", 1, 1, 0, 0},
|
|
{"ILST" , 0, 24, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCD" , 24, 1, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ACK_NAK" , 25, 1, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_30" , 26, 5, 598, "RAZ", 1, 1, 0, 0},
|
|
{"DLLD" , 31, 1, 598, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NTSS" , 0, 4, 599, "R/W", 0, 0, 10ull, 10ull},
|
|
{"RESERVED_4_7" , 4, 4, 599, "RO", 1, 1, 0, 0},
|
|
{"NSKPS" , 8, 3, 599, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_11_13" , 11, 3, 599, "RAZ", 1, 1, 0, 0},
|
|
{"TMRT" , 14, 5, 599, "R/W", 0, 0, 8ull, 8ull},
|
|
{"TMANLT" , 19, 5, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TMFCWT" , 24, 5, 599, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_31" , 29, 3, 599, "RO", 1, 1, 0, 0},
|
|
{"SKPIV" , 0, 11, 600, "R/W", 0, 0, 1280ull, 1280ull},
|
|
{"RESERVED_11_14" , 11, 4, 600, "RAZ", 1, 1, 0, 0},
|
|
{"DFCWT" , 15, 1, 600, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_FUN" , 16, 1, 600, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_POIS_FILT" , 17, 1, 600, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_BAR_MATCH" , 18, 1, 600, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CFG1_FILT" , 19, 1, 600, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_LK_FILT" , 20, 1, 600, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_TAG_ERR" , 21, 1, 600, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_RID_ERR" , 22, 1, 600, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_FUN_ERR" , 23, 1, 600, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_TC_ERR" , 24, 1, 600, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_ATTR_ERR" , 25, 1, 600, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_LEN_ERR" , 26, 1, 600, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_ECRC_FILT" , 27, 1, 600, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_ECRC_FILT" , 28, 1, 600, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSG_CTRL" , 29, 1, 600, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_IO_FILT" , 30, 1, 600, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CFG0_FILT" , 31, 1, 600, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_VEND0_DRP" , 0, 1, 601, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_VEND1_DRP" , 1, 1, 601, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_31" , 2, 30, 601, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_INFO_L32" , 0, 32, 602, "RO", 0, 0, 0ull, 0ull},
|
|
{"DBG_INFO_U32" , 0, 32, 603, "RO", 0, 0, 0ull, 0ull},
|
|
{"TPDFCC" , 0, 12, 604, "RO", 0, 0, 0ull, 0ull},
|
|
{"TPHFCC" , 12, 8, 604, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 604, "RAZ", 1, 1, 0, 0},
|
|
{"TCDFCC" , 0, 12, 605, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCHFCC" , 12, 8, 605, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 605, "RAZ", 1, 1, 0, 0},
|
|
{"TCDFCC" , 0, 12, 606, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCHFCC" , 12, 8, 606, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 606, "RAZ", 1, 1, 0, 0},
|
|
{"RTLPFCCNR" , 0, 1, 607, "RO", 0, 0, 0ull, 0ull},
|
|
{"TRBNE" , 1, 1, 607, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQNE" , 2, 1, 607, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_31" , 3, 29, 607, "RAZ", 1, 1, 0, 0},
|
|
{"WRR_VC0" , 0, 8, 608, "RO", 0, 0, 15ull, 15ull},
|
|
{"WRR_VC1" , 8, 8, 608, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC2" , 16, 8, 608, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC3" , 24, 8, 608, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC4" , 0, 8, 609, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC5" , 8, 8, 609, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC6" , 16, 8, 609, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC7" , 24, 8, 609, "RO", 0, 0, 0ull, 0ull},
|
|
{"DATA_CREDITS" , 0, 12, 610, "RO/WRSL", 0, 0, 128ull, 128ull},
|
|
{"HEADER_CREDITS" , 12, 8, 610, "RO/WRSL", 0, 0, 35ull, 35ull},
|
|
{"RESERVED_20_20" , 20, 1, 610, "RAZ", 1, 1, 0, 0},
|
|
{"QUEUE_MODE" , 21, 3, 610, "RO/WRSL", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_24_29" , 24, 6, 610, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE_ORDERING" , 30, 1, 610, "RO/WRSL", 0, 0, 1ull, 1ull},
|
|
{"RX_QUEUE_ORDER" , 31, 1, 610, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"DATA_CREDITS" , 0, 12, 611, "RO/WRSL", 0, 0, 4ull, 4ull},
|
|
{"HEADER_CREDITS" , 12, 8, 611, "RO/WRSL", 0, 0, 8ull, 8ull},
|
|
{"RESERVED_20_20" , 20, 1, 611, "RAZ", 1, 1, 0, 0},
|
|
{"QUEUE_MODE" , 21, 3, 611, "RO/WRSL", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_24_31" , 24, 8, 611, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_CREDITS" , 0, 12, 612, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"HEADER_CREDITS" , 12, 8, 612, "RO/WRSL", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 612, "RAZ", 1, 1, 0, 0},
|
|
{"QUEUE_MODE" , 21, 3, 612, "RO/WRSL", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_24_31" , 24, 8, 612, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_DEPTH" , 0, 14, 613, "RO/WRSL", 0, 0, 331ull, 331ull},
|
|
{"RESERVED_14_15" , 14, 2, 613, "RAZ", 1, 1, 0, 0},
|
|
{"HEADER_DEPTH" , 16, 10, 613, "RO/WRSL", 0, 0, 41ull, 41ull},
|
|
{"RESERVED_26_31" , 26, 6, 613, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_DEPTH" , 0, 14, 614, "RO/WRSL", 0, 0, 56ull, 56ull},
|
|
{"RESERVED_14_15" , 14, 2, 614, "RAZ", 1, 1, 0, 0},
|
|
{"HEADER_DEPTH" , 16, 10, 614, "RO/WRSL", 0, 0, 14ull, 14ull},
|
|
{"RESERVED_26_31" , 26, 6, 614, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_DEPTH" , 0, 14, 615, "RO/WRSL", 0, 0, 360ull, 360ull},
|
|
{"RESERVED_14_15" , 14, 2, 615, "RAZ", 1, 1, 0, 0},
|
|
{"HEADER_DEPTH" , 16, 10, 615, "RO/WRSL", 0, 0, 70ull, 70ull},
|
|
{"RESERVED_26_31" , 26, 6, 615, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_STAT" , 0, 32, 616, "RO", 0, 0, 0ull, 0ull},
|
|
{"PHY_CTRL" , 0, 32, 617, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VENDID" , 0, 16, 618, "R/W", 0, 0, 6013ull, 6013ull},
|
|
{"DEVID" , 16, 16, 618, "R/W", 0, 0, 128ull, 128ull},
|
|
{"ISAE" , 0, 1, 619, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSAE" , 1, 1, 619, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ME" , 2, 1, 619, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SCSE" , 3, 1, 619, "RO", 0, 0, 0ull, 0ull},
|
|
{"MWICE" , 4, 1, 619, "RO", 0, 0, 0ull, 0ull},
|
|
{"VPS" , 5, 1, 619, "RO", 0, 0, 0ull, 0ull},
|
|
{"PER" , 6, 1, 619, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDS_WCC" , 7, 1, 619, "RO", 0, 0, 0ull, 0ull},
|
|
{"SEE" , 8, 1, 619, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FBBE" , 9, 1, 619, "RO", 0, 0, 0ull, 0ull},
|
|
{"I_DIS" , 10, 1, 619, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_18" , 11, 8, 619, "RAZ", 1, 1, 0, 0},
|
|
{"I_STAT" , 19, 1, 619, "RO", 0, 0, 0ull, 0ull},
|
|
{"CL" , 20, 1, 619, "RO", 0, 0, 1ull, 1ull},
|
|
{"M66" , 21, 1, 619, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_22" , 22, 1, 619, "RO", 1, 1, 0, 0},
|
|
{"FBB" , 23, 1, 619, "RO", 0, 0, 0ull, 0ull},
|
|
{"MDPE" , 24, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DEVT" , 25, 2, 619, "RO", 0, 0, 0ull, 0ull},
|
|
{"STA" , 27, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTA" , 28, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RMA" , 29, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SSE" , 30, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPE" , 31, 1, 619, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RID" , 0, 8, 620, "R/W", 0, 0, 8ull, 8ull},
|
|
{"PI" , 8, 8, 620, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SC" , 16, 8, 620, "R/W", 0, 0, 48ull, 48ull},
|
|
{"BCC" , 24, 8, 620, "R/W", 0, 0, 11ull, 11ull},
|
|
{"CLS" , 0, 8, 621, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LT" , 8, 8, 621, "RO", 0, 0, 0ull, 0ull},
|
|
{"CHF" , 16, 7, 621, "RO", 0, 0, 1ull, 1ull},
|
|
{"MFD" , 23, 1, 621, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BIST" , 24, 8, 621, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_31" , 0, 32, 622, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 623, "RO", 1, 1, 0, 0},
|
|
{"PBNUM" , 0, 8, 624, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SBNUM" , 8, 8, 624, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SUBBNUM" , 16, 8, 624, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SLT" , 24, 8, 624, "RO", 0, 0, 0ull, 0ull},
|
|
{"IO32A" , 0, 1, 625, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_3" , 1, 3, 625, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LIO_BASE" , 4, 4, 625, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IO32B" , 8, 1, 625, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_9_11" , 9, 3, 625, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LIO_LIMI" , 12, 4, 625, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_20" , 16, 5, 625, "RAZ", 1, 1, 0, 0},
|
|
{"M66" , 21, 1, 625, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_22" , 22, 1, 625, "RO", 1, 1, 0, 0},
|
|
{"FBB" , 23, 1, 625, "RO", 0, 0, 0ull, 0ull},
|
|
{"MDPE" , 24, 1, 625, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DEVT" , 25, 2, 625, "RO", 0, 0, 0ull, 0ull},
|
|
{"STA" , 27, 1, 625, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTA" , 28, 1, 625, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RMA" , 29, 1, 625, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SSE" , 30, 1, 625, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPE" , 31, 1, 625, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_3" , 0, 4, 626, "RO", 1, 1, 0, 0},
|
|
{"MB_ADDR" , 4, 12, 626, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_19" , 16, 4, 626, "RO", 1, 1, 0, 0},
|
|
{"ML_ADDR" , 20, 12, 626, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM64A" , 0, 1, 627, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_3" , 1, 3, 627, "RO", 1, 1, 0, 0},
|
|
{"LMEM_BASE" , 4, 12, 627, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MEM64B" , 16, 1, 627, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_17_19" , 17, 3, 627, "RO", 1, 1, 0, 0},
|
|
{"LMEM_LIMIT" , 20, 12, 627, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMEM_BASE" , 0, 32, 628, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMEM_LIMIT" , 0, 32, 629, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UIO_BASE" , 0, 16, 630, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UIO_LIMIT" , 16, 16, 630, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CP" , 0, 8, 631, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_8_31" , 8, 24, 631, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 632, "RAZ", 1, 1, 0, 0},
|
|
{"IL" , 0, 8, 633, "R/W", 0, 0, 255ull, 255ull},
|
|
{"INTA" , 8, 8, 633, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PERE" , 16, 1, 633, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SEE" , 17, 1, 633, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ISAE" , 18, 1, 633, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VGAE" , 19, 1, 633, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VGA16D" , 20, 1, 633, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAM" , 21, 1, 633, "RO", 0, 0, 0ull, 0ull},
|
|
{"SBRST" , 22, 1, 633, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FBBE" , 23, 1, 633, "RO", 0, 0, 0ull, 0ull},
|
|
{"PDT" , 24, 1, 633, "RO", 0, 0, 0ull, 0ull},
|
|
{"SDT" , 25, 1, 633, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTS" , 26, 1, 633, "RO", 0, 0, 0ull, 0ull},
|
|
{"DTSEES" , 27, 1, 633, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_31" , 28, 4, 633, "RO", 1, 1, 0, 0},
|
|
{"PMCID" , 0, 8, 634, "RO", 0, 0, 1ull, 1ull},
|
|
{"NCP" , 8, 8, 634, "R/W", 0, 0, 80ull, 80ull},
|
|
{"PMSV" , 16, 3, 634, "R/W", 0, 0, 3ull, 3ull},
|
|
{"PME_CLOCK" , 19, 1, 634, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 634, "RAZ", 1, 1, 0, 0},
|
|
{"DSI" , 21, 1, 634, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AUXC" , 22, 3, 634, "R/W", 0, 0, 0ull, 0ull},
|
|
{"D1S" , 25, 1, 634, "R/W", 0, 0, 0ull, 0ull},
|
|
{"D2S" , 26, 1, 634, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMES" , 27, 5, 634, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PS" , 0, 2, 635, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 635, "RAZ", 1, 1, 0, 0},
|
|
{"NSR" , 3, 1, 635, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 635, "RAZ", 1, 1, 0, 0},
|
|
{"PMEENS" , 8, 1, 635, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMDS" , 9, 4, 635, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMEDSIA" , 13, 2, 635, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMESS" , 15, 1, 635, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_21" , 16, 6, 635, "RAZ", 1, 1, 0, 0},
|
|
{"BD3H" , 22, 1, 635, "RO", 0, 0, 0ull, 0ull},
|
|
{"BPCCEE" , 23, 1, 635, "RO", 0, 0, 0ull, 0ull},
|
|
{"PMDIA" , 24, 8, 635, "RO", 0, 0, 0ull, 0ull},
|
|
{"MSICID" , 0, 8, 636, "RO", 0, 0, 5ull, 5ull},
|
|
{"NCP" , 8, 8, 636, "R/W", 0, 0, 112ull, 112ull},
|
|
{"MSIEN" , 16, 1, 636, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MMC" , 17, 3, 636, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MME" , 20, 3, 636, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M64" , 23, 1, 636, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_24_31" , 24, 8, 636, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 637, "RAZ", 1, 1, 0, 0},
|
|
{"LMSI" , 2, 30, 637, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UMSI" , 0, 32, 638, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSIMD" , 0, 16, 639, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_31" , 16, 16, 639, "RAZ", 1, 1, 0, 0},
|
|
{"PCIEID" , 0, 8, 640, "RO", 0, 0, 16ull, 16ull},
|
|
{"NCP" , 8, 8, 640, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCIECV" , 16, 4, 640, "RO", 0, 0, 2ull, 2ull},
|
|
{"DPT" , 20, 4, 640, "RO", 0, 0, 4ull, 4ull},
|
|
{"SI" , 24, 1, 640, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IMN" , 25, 5, 640, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_30_31" , 30, 2, 640, "RAZ", 1, 1, 0, 0},
|
|
{"MPSS" , 0, 3, 641, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PFS" , 3, 2, 641, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ETFS" , 5, 1, 641, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EL0AL" , 6, 3, 641, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EL1AL" , 9, 3, 641, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_14" , 12, 3, 641, "RAZ", 1, 1, 0, 0},
|
|
{"RBER" , 15, 1, 641, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_16_17" , 16, 2, 641, "RAZ", 1, 1, 0, 0},
|
|
{"CSPLV" , 18, 8, 641, "RO", 0, 0, 0ull, 0ull},
|
|
{"CSPLS" , 26, 2, 641, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_31" , 28, 4, 641, "RAZ", 1, 1, 0, 0},
|
|
{"CE_EN" , 0, 1, 642, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NFE_EN" , 1, 1, 642, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FE_EN" , 2, 1, 642, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UR_EN" , 3, 1, 642, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RO_EN" , 4, 1, 642, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MPS" , 5, 3, 642, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ETF_EN" , 8, 1, 642, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PF_EN" , 9, 1, 642, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AP_EN" , 10, 1, 642, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NS_EN" , 11, 1, 642, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MRRS" , 12, 3, 642, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_15_15" , 15, 1, 642, "RAZ", 1, 1, 0, 0},
|
|
{"CE_D" , 16, 1, 642, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NFE_D" , 17, 1, 642, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FE_D" , 18, 1, 642, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UR_D" , 19, 1, 642, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AP_D" , 20, 1, 642, "RO", 0, 0, 0ull, 0ull},
|
|
{"TP" , 21, 1, 642, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_31" , 22, 10, 642, "RAZ", 1, 1, 0, 0},
|
|
{"MLS" , 0, 4, 643, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MLW" , 4, 6, 643, "R/W", 0, 0, 8ull, 8ull},
|
|
{"ASLPMS" , 10, 2, 643, "R/W", 0, 0, 3ull, 3ull},
|
|
{"L0EL" , 12, 3, 643, "R/W", 0, 0, 6ull, 6ull},
|
|
{"L1EL" , 15, 3, 643, "R/W", 0, 0, 6ull, 6ull},
|
|
{"CPM" , 18, 1, 643, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SDERC" , 19, 1, 643, "RO", 0, 0, 0ull, 0ull},
|
|
{"DLLARC" , 20, 1, 643, "RO", 0, 0, 1ull, 1ull},
|
|
{"LBNC" , 21, 1, 643, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_22_23" , 22, 2, 643, "RAZ", 1, 1, 0, 0},
|
|
{"PNUM" , 24, 8, 643, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ASLPC" , 0, 2, 644, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 644, "RAZ", 1, 1, 0, 0},
|
|
{"RCB" , 3, 1, 644, "R/W", 0, 0, 1ull, 1ull},
|
|
{"LD" , 4, 1, 644, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RL" , 5, 1, 644, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CCC" , 6, 1, 644, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ES" , 7, 1, 644, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECPM" , 8, 1, 644, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HAWD" , 9, 1, 644, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LBM_INT_ENB" , 10, 1, 644, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LAB_INT_ENB" , 11, 1, 644, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_15" , 12, 4, 644, "RAZ", 1, 1, 0, 0},
|
|
{"LS" , 16, 4, 644, "RO", 0, 0, 1ull, 1ull},
|
|
{"NLW" , 20, 6, 644, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_26" , 26, 1, 644, "RAZ", 1, 1, 0, 0},
|
|
{"LT" , 27, 1, 644, "RO", 0, 0, 0ull, 0ull},
|
|
{"SCC" , 28, 1, 644, "R/W", 0, 0, 1ull, 0ull},
|
|
{"DLLA" , 29, 1, 644, "RO", 0, 0, 0ull, 1ull},
|
|
{"LBM" , 30, 1, 644, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LAB" , 31, 1, 644, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ABP" , 0, 1, 645, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PCP" , 1, 1, 645, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRLSP" , 2, 1, 645, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AIP" , 3, 1, 645, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PIP" , 4, 1, 645, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HP_S" , 5, 1, 645, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HP_C" , 6, 1, 645, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SP_LV" , 7, 8, 645, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SP_LS" , 15, 2, 645, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EMIP" , 17, 1, 645, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NCCS" , 18, 1, 645, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PS_NUM" , 19, 13, 645, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ABP_EN" , 0, 1, 646, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PF_EN" , 1, 1, 646, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRLS_EN" , 2, 1, 646, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PD_EN" , 3, 1, 646, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CCINT_EN" , 4, 1, 646, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HPINT_EN" , 5, 1, 646, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AIC" , 6, 2, 646, "R/W", 0, 0, 3ull, 3ull},
|
|
{"PIC" , 8, 2, 646, "R/W", 0, 0, 3ull, 3ull},
|
|
{"PCC" , 10, 1, 646, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EMIC" , 11, 1, 646, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLLS_EN" , 12, 1, 646, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 646, "RAZ", 1, 1, 0, 0},
|
|
{"ABP_D" , 16, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PF_D" , 17, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRLS_C" , 18, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PD_C" , 19, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CCINT_D" , 20, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRLSS" , 21, 1, 646, "RO", 0, 0, 0ull, 0ull},
|
|
{"PDS" , 22, 1, 646, "RO", 0, 0, 1ull, 1ull},
|
|
{"EMIS" , 23, 1, 646, "RO", 0, 0, 0ull, 0ull},
|
|
{"DLLS_C" , 24, 1, 646, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_31" , 25, 7, 646, "RAZ", 1, 1, 0, 0},
|
|
{"SECEE" , 0, 1, 647, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SENFEE" , 1, 1, 647, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SEFEE" , 2, 1, 647, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PMEIE" , 3, 1, 647, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CRSSVE" , 4, 1, 647, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_15" , 5, 11, 647, "RAZ", 1, 1, 0, 0},
|
|
{"CRSSV" , 16, 1, 647, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 647, "RAZ", 1, 1, 0, 0},
|
|
{"PME_RID" , 0, 16, 648, "RO", 0, 0, 0ull, 0ull},
|
|
{"PME_STAT" , 16, 1, 648, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PME_PEND" , 17, 1, 648, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_31" , 18, 14, 648, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CTRS" , 0, 4, 649, "RO", 0, 0, 0ull, 0ull},
|
|
{"CTDS" , 4, 1, 649, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_5_31" , 5, 27, 649, "RAZ", 1, 1, 0, 0},
|
|
{"CTV" , 0, 4, 650, "RO", 0, 0, 0ull, 0ull},
|
|
{"CTD" , 4, 1, 650, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 650, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 651, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 652, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 653, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_31" , 0, 32, 654, "RAZ", 1, 1, 0, 0},
|
|
{"PCIEEC" , 0, 16, 655, "RO", 0, 0, 1ull, 1ull},
|
|
{"CV" , 16, 4, 655, "RO", 0, 0, 1ull, 1ull},
|
|
{"NCO" , 20, 12, 655, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_3" , 0, 4, 656, "RAZ", 1, 1, 0, 0},
|
|
{"DLPES" , 4, 1, 656, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SDES" , 5, 1, 656, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_11" , 6, 6, 656, "RAZ", 1, 1, 0, 0},
|
|
{"PTLPS" , 12, 1, 656, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCPES" , 13, 1, 656, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CTS" , 14, 1, 656, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CAS" , 15, 1, 656, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UCS" , 16, 1, 656, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ROS" , 17, 1, 656, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MTLPS" , 18, 1, 656, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ECRCES" , 19, 1, 656, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"URES" , 20, 1, 656, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 656, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_3" , 0, 4, 657, "RAZ", 1, 1, 0, 0},
|
|
{"DLPEM" , 4, 1, 657, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SDEM" , 5, 1, 657, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_11" , 6, 6, 657, "RAZ", 1, 1, 0, 0},
|
|
{"PTLPM" , 12, 1, 657, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCPEM" , 13, 1, 657, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CTM" , 14, 1, 657, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAM" , 15, 1, 657, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UCM" , 16, 1, 657, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROM" , 17, 1, 657, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MTLPM" , 18, 1, 657, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECRCEM" , 19, 1, 657, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UREM" , 20, 1, 657, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 657, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_3" , 0, 4, 658, "RAZ", 1, 1, 0, 0},
|
|
{"DLPES" , 4, 1, 658, "R/W", 0, 0, 1ull, 1ull},
|
|
{"SDES" , 5, 1, 658, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_11" , 6, 6, 658, "RAZ", 1, 1, 0, 0},
|
|
{"PTLPS" , 12, 1, 658, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCPES" , 13, 1, 658, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CTS" , 14, 1, 658, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAS" , 15, 1, 658, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UCS" , 16, 1, 658, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ROS" , 17, 1, 658, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MTLPS" , 18, 1, 658, "R/W", 0, 0, 1ull, 1ull},
|
|
{"ECRCES" , 19, 1, 658, "R/W", 0, 0, 0ull, 0ull},
|
|
{"URES" , 20, 1, 658, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 658, "RAZ", 1, 1, 0, 0},
|
|
{"RES" , 0, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_5" , 1, 5, 659, "RAZ", 1, 1, 0, 0},
|
|
{"BTLPS" , 6, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BDLLPS" , 7, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RNRS" , 8, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 659, "RAZ", 1, 1, 0, 0},
|
|
{"RTTS" , 12, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ANFES" , 13, 1, 659, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_31" , 14, 18, 659, "RAZ", 1, 1, 0, 0},
|
|
{"REM" , 0, 1, 660, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_5" , 1, 5, 660, "RAZ", 1, 1, 0, 0},
|
|
{"BTLPM" , 6, 1, 660, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BDLLPM" , 7, 1, 660, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNRM" , 8, 1, 660, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 660, "RAZ", 1, 1, 0, 0},
|
|
{"RTTM" , 12, 1, 660, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ANFEM" , 13, 1, 660, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_14_31" , 14, 18, 660, "RAZ", 1, 1, 0, 0},
|
|
{"FEP" , 0, 5, 661, "RO", 0, 0, 0ull, 0ull},
|
|
{"GC" , 5, 1, 661, "RO", 0, 0, 1ull, 1ull},
|
|
{"GE" , 6, 1, 661, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CC" , 7, 1, 661, "RO", 0, 0, 1ull, 1ull},
|
|
{"CE" , 8, 1, 661, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_31" , 9, 23, 661, "RAZ", 1, 1, 0, 0},
|
|
{"DWORD1" , 0, 32, 662, "RO", 0, 0, 0ull, 0ull},
|
|
{"DWORD2" , 0, 32, 663, "RO", 0, 0, 0ull, 0ull},
|
|
{"DWORD3" , 0, 32, 664, "RO", 0, 0, 0ull, 0ull},
|
|
{"DWORD4" , 0, 32, 665, "RO", 0, 0, 0ull, 0ull},
|
|
{"CERE" , 0, 1, 666, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NFERE" , 1, 1, 666, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FERE" , 2, 1, 666, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_31" , 3, 29, 666, "RAZ", 1, 1, 0, 0},
|
|
{"ECR" , 0, 1, 667, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MULTI_ECR" , 1, 1, 667, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EFNFR" , 2, 1, 667, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MULTI_EFNFR" , 3, 1, 667, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FUF" , 4, 1, 667, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NFEMR" , 5, 1, 667, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FEMR" , 6, 1, 667, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_26" , 7, 20, 667, "RAZ", 1, 1, 0, 0},
|
|
{"AEIMN" , 27, 5, 667, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECSI" , 0, 16, 668, "RO", 0, 0, 0ull, 0ull},
|
|
{"EFNFSI" , 16, 16, 668, "RO", 0, 0, 0ull, 0ull},
|
|
{"RTLTL" , 0, 16, 669, "R/W", 0, 0, 4143ull, 4143ull},
|
|
{"RTL" , 16, 16, 669, "R/W", 0, 0, 12429ull, 12429ull},
|
|
{"OMR" , 0, 32, 670, "R/W", 0, 1, 4294967295ull, 0},
|
|
{"LINK_NUM" , 0, 8, 671, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_8_14" , 8, 7, 671, "RAZ", 1, 1, 0, 0},
|
|
{"FORCE_LINK" , 15, 1, 671, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LINK_STATE" , 16, 6, 671, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 671, "RAZ", 1, 1, 0, 0},
|
|
{"LPEC" , 24, 8, 671, "RO", 0, 0, 7ull, 7ull},
|
|
{"ACK_FREQ" , 0, 8, 672, "R/W", 0, 0, 0ull, 0ull},
|
|
{"N_FTS" , 8, 8, 672, "R/W", 0, 0, 128ull, 128ull},
|
|
{"N_FTS_CC" , 16, 8, 672, "R/W", 0, 0, 128ull, 128ull},
|
|
{"L0EL" , 24, 3, 672, "R/W", 0, 0, 3ull, 3ull},
|
|
{"L1EL" , 27, 3, 672, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_30_31" , 30, 2, 672, "RAZ", 1, 1, 0, 0},
|
|
{"OMR" , 0, 1, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SD" , 1, 1, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LE" , 2, 1, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RA" , 3, 1, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_4" , 4, 1, 673, "RAZ", 1, 1, 0, 0},
|
|
{"DLLLE" , 5, 1, 673, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_6" , 6, 1, 673, "RAZ", 1, 1, 0, 0},
|
|
{"FLM" , 7, 1, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_15" , 8, 8, 673, "RO", 0, 0, 1ull, 1ull},
|
|
{"LME" , 16, 6, 673, "R/W", 0, 0, 15ull, 15ull},
|
|
{"RESERVED_22_24" , 22, 3, 673, "RAZ", 1, 1, 0, 0},
|
|
{"ECCRC" , 25, 1, 673, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_31" , 26, 6, 673, "RAZ", 1, 1, 0, 0},
|
|
{"ILST" , 0, 24, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCD" , 24, 1, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ACK_NAK" , 25, 1, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_30" , 26, 5, 674, "RAZ", 1, 1, 0, 0},
|
|
{"DLLD" , 31, 1, 674, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NTSS" , 0, 4, 675, "R/W", 0, 0, 10ull, 10ull},
|
|
{"RESERVED_4_7" , 4, 4, 675, "RO", 1, 1, 0, 0},
|
|
{"NSKPS" , 8, 3, 675, "R/W", 0, 0, 3ull, 3ull},
|
|
{"RESERVED_11_13" , 11, 3, 675, "RAZ", 1, 1, 0, 0},
|
|
{"TMRT" , 14, 5, 675, "R/W", 0, 0, 8ull, 8ull},
|
|
{"TMANLT" , 19, 5, 675, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TMFCWT" , 24, 5, 675, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_31" , 29, 3, 675, "RO", 1, 1, 0, 0},
|
|
{"SKPIV" , 0, 11, 676, "R/W", 0, 0, 1280ull, 1280ull},
|
|
{"RESERVED_11_14" , 11, 4, 676, "RAZ", 1, 1, 0, 0},
|
|
{"DFCWT" , 15, 1, 676, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_FUN" , 16, 1, 676, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_POIS_FILT" , 17, 1, 676, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_BAR_MATCH" , 18, 1, 676, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CFG1_FILT" , 19, 1, 676, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_LK_FILT" , 20, 1, 676, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_TAG_ERR" , 21, 1, 676, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_RID_ERR" , 22, 1, 676, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_FUN_ERR" , 23, 1, 676, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_TC_ERR" , 24, 1, 676, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_ATTR_ERR" , 25, 1, 676, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_LEN_ERR" , 26, 1, 676, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_ECRC_FILT" , 27, 1, 676, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CPL_ECRC_FILT" , 28, 1, 676, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MSG_CTRL" , 29, 1, 676, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_IO_FILT" , 30, 1, 676, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_CFG0_FILT" , 31, 1, 676, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_VEND0_DRP" , 0, 1, 677, "R/W", 0, 0, 0ull, 0ull},
|
|
{"M_VEND1_DRP" , 1, 1, 677, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_31" , 2, 30, 677, "RAZ", 1, 1, 0, 0},
|
|
{"DBG_INFO_L32" , 0, 32, 678, "RO", 0, 0, 0ull, 0ull},
|
|
{"DBG_INFO_U32" , 0, 32, 679, "RO", 0, 0, 0ull, 0ull},
|
|
{"TPDFCC" , 0, 12, 680, "RO", 0, 0, 0ull, 0ull},
|
|
{"TPHFCC" , 12, 8, 680, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 680, "RAZ", 1, 1, 0, 0},
|
|
{"TCDFCC" , 0, 12, 681, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCHFCC" , 12, 8, 681, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 681, "RAZ", 1, 1, 0, 0},
|
|
{"TCDFCC" , 0, 12, 682, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCHFCC" , 12, 8, 682, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 682, "RAZ", 1, 1, 0, 0},
|
|
{"RTLPFCCNR" , 0, 1, 683, "RO", 0, 0, 0ull, 0ull},
|
|
{"TRBNE" , 1, 1, 683, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQNE" , 2, 1, 683, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_31" , 3, 29, 683, "RAZ", 1, 1, 0, 0},
|
|
{"WRR_VC0" , 0, 8, 684, "RO", 0, 0, 15ull, 15ull},
|
|
{"WRR_VC1" , 8, 8, 684, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC2" , 16, 8, 684, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC3" , 24, 8, 684, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC4" , 0, 8, 685, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC5" , 8, 8, 685, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC6" , 16, 8, 685, "RO", 0, 0, 0ull, 0ull},
|
|
{"WRR_VC7" , 24, 8, 685, "RO", 0, 0, 0ull, 0ull},
|
|
{"DATA_CREDITS" , 0, 12, 686, "R/W", 0, 0, 128ull, 128ull},
|
|
{"HEADER_CREDITS" , 12, 8, 686, "R/W", 0, 0, 35ull, 35ull},
|
|
{"RESERVED_20_20" , 20, 1, 686, "RAZ", 1, 1, 0, 0},
|
|
{"QUEUE_MODE" , 21, 3, 686, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_24_29" , 24, 6, 686, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE_ORDERING" , 30, 1, 686, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RX_QUEUE_ORDER" , 31, 1, 686, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DATA_CREDITS" , 0, 12, 687, "R/W", 0, 0, 4ull, 4ull},
|
|
{"HEADER_CREDITS" , 12, 8, 687, "R/W", 0, 0, 8ull, 8ull},
|
|
{"RESERVED_20_20" , 20, 1, 687, "RAZ", 1, 1, 0, 0},
|
|
{"QUEUE_MODE" , 21, 3, 687, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_24_31" , 24, 8, 687, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_CREDITS" , 0, 12, 688, "R/W", 0, 0, 128ull, 128ull},
|
|
{"HEADER_CREDITS" , 12, 8, 688, "R/W", 0, 0, 64ull, 64ull},
|
|
{"RESERVED_20_20" , 20, 1, 688, "RAZ", 1, 1, 0, 0},
|
|
{"QUEUE_MODE" , 21, 3, 688, "R/W", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_24_31" , 24, 8, 688, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_DEPTH" , 0, 14, 689, "R/W", 0, 0, 331ull, 331ull},
|
|
{"RESERVED_14_15" , 14, 2, 689, "RAZ", 1, 1, 0, 0},
|
|
{"HEADER_DEPTH" , 16, 10, 689, "R/W", 0, 0, 41ull, 41ull},
|
|
{"RESERVED_26_31" , 26, 6, 689, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_DEPTH" , 0, 14, 690, "R/W", 0, 0, 56ull, 56ull},
|
|
{"RESERVED_14_15" , 14, 2, 690, "RAZ", 1, 1, 0, 0},
|
|
{"HEADER_DEPTH" , 16, 10, 690, "R/W", 0, 0, 14ull, 14ull},
|
|
{"RESERVED_26_31" , 26, 6, 690, "RAZ", 1, 1, 0, 0},
|
|
{"DATA_DEPTH" , 0, 14, 691, "R/W", 0, 0, 360ull, 360ull},
|
|
{"RESERVED_14_15" , 14, 2, 691, "RAZ", 1, 1, 0, 0},
|
|
{"HEADER_DEPTH" , 16, 10, 691, "R/W", 0, 0, 70ull, 70ull},
|
|
{"RESERVED_26_31" , 26, 6, 691, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_STAT" , 0, 32, 692, "RO", 0, 0, 0ull, 0ull},
|
|
{"PHY_CTRL" , 0, 32, 693, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_4" , 0, 5, 694, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FD" , 5, 1, 694, "R/W", 0, 0, 1ull, 1ull},
|
|
{"HFD" , 6, 1, 694, "R/W", 0, 0, 1ull, 1ull},
|
|
{"PAUSE" , 7, 2, 694, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 694, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"REM_FLT" , 12, 2, 694, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_14" , 14, 1, 694, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"NP" , 15, 1, 694, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 694, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_11" , 0, 12, 695, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"THOU_THD" , 12, 1, 695, "RO", 0, 0, 0ull, 0ull},
|
|
{"THOU_TFD" , 13, 1, 695, "RO", 0, 0, 0ull, 0ull},
|
|
{"THOU_XHD" , 14, 1, 695, "RO", 0, 0, 1ull, 1ull},
|
|
{"THOU_XFD" , 15, 1, 695, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_16_63" , 16, 48, 695, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_4" , 0, 5, 696, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FD" , 5, 1, 696, "RO", 0, 0, 0ull, 0ull},
|
|
{"HFD" , 6, 1, 696, "RO", 0, 0, 0ull, 0ull},
|
|
{"PAUSE" , 7, 2, 696, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_11" , 9, 3, 696, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"REM_FLT" , 12, 2, 696, "RO", 0, 0, 0ull, 0ull},
|
|
{"ACK" , 14, 1, 696, "RO", 0, 1, 0ull, 0},
|
|
{"NP" , 15, 1, 696, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 696, "RAZ", 1, 1, 0, 0},
|
|
{"LINK_OK" , 0, 1, 697, "RO", 0, 0, 0ull, 0ull},
|
|
{"DUP" , 1, 1, 697, "RO", 0, 0, 0ull, 0ull},
|
|
{"AN_CPT" , 2, 1, 697, "RO", 0, 0, 0ull, 1ull},
|
|
{"SPD" , 3, 2, 697, "RO", 0, 0, 0ull, 0ull},
|
|
{"PAUSE" , 5, 2, 697, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 697, "RAZ", 1, 1, 0, 0},
|
|
{"LNKSPD_EN" , 0, 1, 698, "R/W", 0, 0, 0ull, 1ull},
|
|
{"XMIT_EN" , 1, 1, 698, "R/W", 0, 0, 0ull, 1ull},
|
|
{"AN_ERR_EN" , 2, 1, 698, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXFIFU_EN" , 3, 1, 698, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXFIFO_EN" , 4, 1, 698, "R/W", 0, 0, 0ull, 1ull},
|
|
{"TXBAD_EN" , 5, 1, 698, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXERR_EN" , 6, 1, 698, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXBAD_EN" , 7, 1, 698, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXLOCK_EN" , 8, 1, 698, "R/W", 0, 0, 0ull, 1ull},
|
|
{"AN_BAD_EN" , 9, 1, 698, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SYNC_BAD_EN" , 10, 1, 698, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DUP" , 11, 1, 698, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_12_63" , 12, 52, 698, "RAZ", 1, 1, 0, 0},
|
|
{"LNKSPD" , 0, 1, 699, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"XMIT" , 1, 1, 699, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AN_ERR" , 2, 1, 699, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXFIFU" , 3, 1, 699, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXFIFO" , 4, 1, 699, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TXBAD" , 5, 1, 699, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXERR" , 6, 1, 699, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXBAD" , 7, 1, 699, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXLOCK" , 8, 1, 699, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AN_BAD" , 9, 1, 699, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SYNC_BAD" , 10, 1, 699, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DUP" , 11, 1, 699, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_63" , 12, 52, 699, "RAZ", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 16, 700, "R/W", 0, 1, 1094ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 700, "RAZ", 1, 1, 0, 0},
|
|
{"PKT_SZ" , 0, 2, 701, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LA_EN" , 2, 1, 701, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LAFIFOVFL" , 3, 1, 701, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 701, "RAZ", 1, 1, 0, 0},
|
|
{"SAMP_PT" , 0, 7, 702, "R/W", 0, 1, 1ull, 0},
|
|
{"AN_OVRD" , 7, 1, 702, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MODE" , 8, 1, 702, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAC_PHY" , 9, 1, 702, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LOOPBCK2" , 10, 1, 702, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GMXENO" , 11, 1, 702, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SGMII" , 12, 1, 702, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_13_63" , 13, 51, 702, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_4" , 0, 5, 703, "RAZ", 1, 1, 0, 0},
|
|
{"UNI" , 5, 1, 703, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SPDMSB" , 6, 1, 703, "R/W", 0, 0, 1ull, 1ull},
|
|
{"COLTST" , 7, 1, 703, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DUP" , 8, 1, 703, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RST_AN" , 9, 1, 703, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_10" , 10, 1, 703, "RAZ", 1, 1, 0, 0},
|
|
{"PWR_DN" , 11, 1, 703, "R/W", 0, 0, 1ull, 0ull},
|
|
{"AN_EN" , 12, 1, 703, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SPDLSB" , 13, 1, 703, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LOOPBCK1" , 14, 1, 703, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 15, 1, 703, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 703, "RAZ", 1, 1, 0, 0},
|
|
{"EXTND" , 0, 1, 704, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 704, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LNK_ST" , 2, 1, 704, "RO", 0, 0, 0ull, 1ull},
|
|
{"AN_ABIL" , 3, 1, 704, "RO", 0, 0, 1ull, 1ull},
|
|
{"RM_FLT" , 4, 1, 704, "RO", 0, 0, 0ull, 0ull},
|
|
{"AN_CPT" , 5, 1, 704, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRB_SUP" , 6, 1, 704, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_7_7" , 7, 1, 704, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"EXT_ST" , 8, 1, 704, "RO", 0, 0, 1ull, 1ull},
|
|
{"HUN_T2HD" , 9, 1, 704, "RO", 0, 0, 0ull, 0ull},
|
|
{"HUN_T2FD" , 10, 1, 704, "RO", 0, 0, 0ull, 0ull},
|
|
{"TEN_HD" , 11, 1, 704, "RO", 0, 0, 0ull, 0ull},
|
|
{"TEN_FD" , 12, 1, 704, "RO", 0, 0, 0ull, 0ull},
|
|
{"HUN_XHD" , 13, 1, 704, "RO", 0, 0, 0ull, 0ull},
|
|
{"HUN_XFD" , 14, 1, 704, "RO", 0, 0, 0ull, 0ull},
|
|
{"HUN_T4" , 15, 1, 704, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 704, "RAZ", 1, 1, 0, 0},
|
|
{"AN_ST" , 0, 4, 705, "RO", 0, 0, 0ull, 0ull},
|
|
{"AN_BAD" , 4, 1, 705, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYNC" , 5, 4, 705, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYNC_BAD" , 9, 1, 705, "RO", 0, 0, 0ull, 0ull},
|
|
{"RX_ST" , 10, 5, 705, "RO", 0, 0, 0ull, 0ull},
|
|
{"RX_BAD" , 15, 1, 705, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 705, "RAZ", 1, 1, 0, 0},
|
|
{"BIT_LOCK" , 0, 1, 706, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYNC" , 1, 1, 706, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 706, "RAZ", 1, 1, 0, 0},
|
|
{"ONE" , 0, 1, 707, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_9" , 1, 9, 707, "RAZ", 0, 1, 0ull, 0},
|
|
{"SPEED" , 10, 2, 707, "R/W", 0, 0, 2ull, 2ull},
|
|
{"DUP" , 12, 1, 707, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_13_13" , 13, 1, 707, "RAZ", 0, 1, 0ull, 0},
|
|
{"ACK" , 14, 1, 707, "RO", 0, 0, 0ull, 0ull},
|
|
{"LINK" , 15, 1, 707, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_16_63" , 16, 48, 707, "RAZ", 1, 1, 0, 0},
|
|
{"ONE" , 0, 1, 708, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_9" , 1, 9, 708, "RAZ", 0, 1, 0ull, 0},
|
|
{"SPEED" , 10, 2, 708, "RO", 0, 0, 0ull, 2ull},
|
|
{"DUP" , 12, 1, 708, "RO", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_13_14" , 13, 2, 708, "RAZ", 0, 1, 0ull, 0},
|
|
{"LINK" , 15, 1, 708, "RO", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_16_63" , 16, 48, 708, "RAZ", 1, 1, 0, 0},
|
|
{"ORD_ST" , 0, 4, 709, "RO", 0, 0, 0ull, 0ull},
|
|
{"TX_BAD" , 4, 1, 709, "RO", 0, 0, 0ull, 0ull},
|
|
{"XMIT" , 5, 2, 709, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_7_63" , 7, 57, 709, "RAZ", 1, 1, 0, 0},
|
|
{"TXPLRT" , 0, 1, 710, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RXPLRT" , 1, 1, 710, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AUTORXPL" , 2, 1, 710, "RO", 0, 0, 0ull, 0ull},
|
|
{"RXOVRD" , 3, 1, 710, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 710, "RAZ", 1, 1, 0, 0},
|
|
{"L0SYNC" , 0, 1, 711, "RO", 0, 0, 0ull, 1ull},
|
|
{"L1SYNC" , 1, 1, 711, "RO", 0, 0, 0ull, 1ull},
|
|
{"L2SYNC" , 2, 1, 711, "RO", 0, 0, 0ull, 1ull},
|
|
{"L3SYNC" , 3, 1, 711, "RO", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_4_10" , 4, 7, 711, "RAZ", 1, 1, 0, 0},
|
|
{"PATTST" , 11, 1, 711, "RO", 0, 0, 0ull, 0ull},
|
|
{"ALIGND" , 12, 1, 711, "RO", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_13_63" , 13, 51, 711, "RAZ", 1, 1, 0, 0},
|
|
{"BIST_STATUS" , 0, 1, 712, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 712, "RAZ", 1, 1, 0, 0},
|
|
{"BITLCK0" , 0, 1, 713, "RO", 0, 1, 0ull, 0},
|
|
{"BITLCK1" , 1, 1, 713, "RO", 0, 1, 0ull, 0},
|
|
{"BITLCK2" , 2, 1, 713, "RO", 0, 1, 0ull, 0},
|
|
{"BITLCK3" , 3, 1, 713, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 713, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 714, "RAZ", 1, 1, 0, 0},
|
|
{"SPD" , 2, 4, 714, "RO", 0, 0, 0ull, 0ull},
|
|
{"SPDSEL0" , 6, 1, 714, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_7_10" , 7, 4, 714, "RAZ", 1, 1, 0, 0},
|
|
{"LO_PWR" , 11, 1, 714, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_12" , 12, 1, 714, "RAZ", 1, 1, 0, 0},
|
|
{"SPDSEL1" , 13, 1, 714, "RO", 0, 0, 1ull, 1ull},
|
|
{"LOOPBCK1" , 14, 1, 714, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 15, 1, 714, "R/W", 0, 0, 1ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 714, "RAZ", 1, 1, 0, 0},
|
|
{"TYPE" , 0, 2, 715, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 715, "RAZ", 1, 1, 0, 0},
|
|
{"TXFLT_EN" , 0, 1, 716, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXBAD_EN" , 1, 1, 716, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RXSYNBAD_EN" , 2, 1, 716, "R/W", 0, 0, 0ull, 1ull},
|
|
{"BITLCKLS_EN" , 3, 1, 716, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SYNLOS_EN" , 4, 1, 716, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ALGNLOS_EN" , 5, 1, 716, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_6_63" , 6, 58, 716, "RAZ", 1, 1, 0, 0},
|
|
{"TXFLT" , 0, 1, 717, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXBAD" , 1, 1, 717, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXSYNBAD" , 2, 1, 717, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BITLCKLS" , 3, 1, 717, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SYNLOS" , 4, 1, 717, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ALGNLOS" , 5, 1, 717, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 717, "RAZ", 1, 1, 0, 0},
|
|
{"PKT_SZ" , 0, 2, 718, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LA_EN" , 2, 1, 718, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LAFIFOVFL" , 3, 1, 718, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DROP_LN" , 4, 2, 718, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENC_MODE" , 6, 1, 718, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 718, "RAZ", 1, 1, 0, 0},
|
|
{"GMXENO" , 0, 1, 719, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XAUI" , 1, 1, 719, "RO", 1, 1, 0, 0},
|
|
{"RX_SWAP" , 2, 1, 719, "R/W", 0, 1, 0ull, 0},
|
|
{"TX_SWAP" , 3, 1, 719, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_4_63" , 4, 60, 719, "RAZ", 1, 1, 0, 0},
|
|
{"SYNC0ST" , 0, 4, 720, "RO", 0, 1, 0ull, 0},
|
|
{"SYNC1ST" , 4, 4, 720, "RO", 0, 1, 0ull, 0},
|
|
{"SYNC2ST" , 8, 4, 720, "RO", 0, 1, 0ull, 0},
|
|
{"SYNC3ST" , 12, 4, 720, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 720, "RAZ", 1, 1, 0, 0},
|
|
{"TENGB" , 0, 1, 721, "RO", 0, 0, 1ull, 1ull},
|
|
{"TENPASST" , 1, 1, 721, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 721, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 722, "RAZ", 1, 1, 0, 0},
|
|
{"LPABLE" , 1, 1, 722, "RO", 0, 0, 1ull, 1ull},
|
|
{"RCV_LNK" , 2, 1, 722, "RO", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_3_6" , 3, 4, 722, "RAZ", 1, 1, 0, 0},
|
|
{"FLT" , 7, 1, 722, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 722, "RAZ", 1, 1, 0, 0},
|
|
{"TENGB_R" , 0, 1, 723, "RO", 0, 0, 0ull, 0ull},
|
|
{"TENGB_X" , 1, 1, 723, "RO", 0, 0, 1ull, 1ull},
|
|
{"TENGB_W" , 2, 1, 723, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_9" , 3, 7, 723, "RAZ", 1, 1, 0, 0},
|
|
{"RCVFLT" , 10, 1, 723, "RC", 0, 0, 0ull, 0ull},
|
|
{"XMTFLT" , 11, 1, 723, "RC", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_13" , 12, 2, 723, "RAZ", 1, 1, 0, 0},
|
|
{"DEV" , 14, 2, 723, "RO", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_16_63" , 16, 48, 723, "RAZ", 1, 1, 0, 0},
|
|
{"TXPLRT" , 0, 1, 724, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RXPLRT" , 1, 1, 724, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XOR_TXPLRT" , 2, 4, 724, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XOR_RXPLRT" , 6, 4, 724, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 724, "RAZ", 1, 1, 0, 0},
|
|
{"TX_ST" , 0, 3, 725, "RO", 0, 1, 0ull, 0},
|
|
{"RX_ST" , 3, 2, 725, "RO", 0, 1, 0ull, 0},
|
|
{"ALGN_ST" , 5, 3, 725, "RO", 0, 1, 0ull, 0},
|
|
{"RXBAD" , 8, 1, 725, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYN0BAD" , 9, 1, 725, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYN1BAD" , 10, 1, 725, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYN2BAD" , 11, 1, 725, "RO", 0, 0, 0ull, 0ull},
|
|
{"SYN3BAD" , 12, 1, 725, "RO", 0, 0, 0ull, 0ull},
|
|
{"TERM_ERR" , 13, 1, 725, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 725, "RAZ", 1, 1, 0, 0},
|
|
{"SOT" , 0, 1, 726, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQHDR0" , 1, 1, 726, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQHDR1" , 2, 1, 726, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQDATA4" , 3, 1, 726, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQDATA3" , 4, 1, 726, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQDATA2" , 5, 1, 726, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQDATA1" , 6, 1, 726, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQDATA0" , 7, 1, 726, "RO", 0, 0, 0ull, 0ull},
|
|
{"RETRY" , 8, 1, 726, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTLP_OR" , 9, 1, 726, "RO", 0, 0, 0ull, 0ull},
|
|
{"NTLP_OR" , 10, 1, 726, "RO", 0, 0, 0ull, 0ull},
|
|
{"CTLP_OR" , 11, 1, 726, "RO", 0, 0, 0ull, 0ull},
|
|
{"RQDATA5" , 12, 1, 726, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 726, "RAZ", 1, 1, 0, 0},
|
|
{"PPF" , 0, 1, 727, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEF_TC0" , 1, 1, 727, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEF_TCF1" , 2, 1, 727, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEF_TNF" , 3, 1, 727, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEF_TPF0" , 4, 1, 727, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEF_TPF1" , 5, 1, 727, "RO", 0, 0, 0ull, 0ull},
|
|
{"RSL_P2E" , 6, 1, 727, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEAI_P2E" , 7, 1, 727, "RO", 0, 0, 0ull, 0ull},
|
|
{"DBG_P2E" , 8, 1, 727, "RO", 0, 0, 0ull, 0ull},
|
|
{"E2P_RSL" , 9, 1, 727, "RO", 0, 0, 0ull, 0ull},
|
|
{"E2P_P" , 10, 1, 727, "RO", 0, 0, 0ull, 0ull},
|
|
{"E2P_N" , 11, 1, 727, "RO", 0, 0, 0ull, 0ull},
|
|
{"E2P_CPL" , 12, 1, 727, "RO", 0, 0, 0ull, 0ull},
|
|
{"CTO_P2E" , 13, 1, 727, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_63" , 14, 50, 727, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 32, 728, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 32, 32, 728, "R/W", 0, 1, 0ull, 0},
|
|
{"ADDR" , 0, 32, 729, "R/W", 0, 1, 0ull, 0},
|
|
{"DATA" , 32, 32, 729, "R/W", 0, 1, 0ull, 0},
|
|
{"TAG" , 0, 32, 730, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 730, "RAZ", 1, 1, 0, 0},
|
|
{"INV_LCRC" , 0, 1, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INV_ECRC" , 1, 1, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_2" , 2, 1, 731, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RO_CTLP" , 3, 1, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LNK_ENB" , 4, 1, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DLY_ONE" , 5, 1, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NF_ECRC" , 6, 1, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_8" , 7, 2, 731, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OB_P_CMD" , 9, 1, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PM_XPME" , 10, 1, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PM_XTOFF" , 11, 1, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LANE_SWP" , 12, 1, 731, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QLM_CFG" , 13, 2, 731, "RO", 1, 1, 0, 0},
|
|
{"PBUS" , 15, 8, 731, "RO", 1, 1, 0, 0},
|
|
{"DNUM" , 23, 5, 731, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_28_63" , 28, 36, 731, "RAZ", 1, 1, 0, 0},
|
|
{"PCIERST" , 0, 1, 732, "RO", 0, 0, 0ull, 0ull},
|
|
{"PCLK_RUN" , 1, 1, 732, "R/W1C", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_2_63" , 2, 62, 732, "RAZ", 1, 1, 0, 0},
|
|
{"SPOISON" , 0, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTLPMAL" , 1, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTLPLLE" , 2, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RECRCE" , 3, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPOISON" , 4, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RCEMRC" , 5, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RNFEMRC" , 6, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RFEMRC" , 7, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPMERC" , 8, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPTAMRC" , 9, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RUMEP" , 10, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RVDM" , 11, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ACTO" , 12, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTE" , 13, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MRE" , 14, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RDWDLE" , 15, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RTWDLE" , 16, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DPEOOSD" , 17, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCPVWT" , 18, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPE" , 19, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FCUV" , 20, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQO" , 21, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RAUC" , 22, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RACUR" , 23, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RACCA" , 24, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CAAR" , 25, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RARWDNS" , 26, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RAMTLP" , 27, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RACPP" , 28, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RAWWPP" , 29, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ECRC_E" , 30, 1, 733, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 733, "RAZ", 1, 1, 0, 0},
|
|
{"SPOISON" , 0, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RTLPMAL" , 1, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RTLPLLE" , 2, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RECRCE" , 3, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RPOISON" , 4, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RCEMRC" , 5, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNFEMRC" , 6, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RFEMRC" , 7, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RPMERC" , 8, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RPTAMRC" , 9, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RUMEP" , 10, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RVDM" , 11, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ACTO" , 12, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RTE" , 13, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MRE" , 14, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RDWDLE" , 15, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RTWDLE" , 16, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DPEOOSD" , 17, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCPVWT" , 18, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RPE" , 19, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FCUV" , 20, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQO" , 21, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RAUC" , 22, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RACUR" , 23, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RACCA" , 24, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CAAR" , 25, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RARWDNS" , 26, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RAMTLP" , 27, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RACPP" , 28, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RAWWPP" , 29, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ECRC_E" , 30, 1, 734, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_63" , 31, 33, 734, "RAZ", 1, 1, 0, 0},
|
|
{"AUX_EN" , 0, 1, 735, "RO", 0, 0, 0ull, 0ull},
|
|
{"PM_EN" , 1, 1, 735, "RO", 0, 0, 0ull, 0ull},
|
|
{"PM_STAT" , 2, 1, 735, "RO", 0, 0, 0ull, 0ull},
|
|
{"PM_DST" , 3, 1, 735, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 735, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_0_13" , 0, 14, 736, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 14, 50, 736, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_25" , 0, 26, 737, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 26, 38, 737, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_38" , 0, 39, 738, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 39, 25, 738, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_0_11" , 0, 12, 739, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 12, 52, 739, "R/W", 0, 1, 4503599627370495ull, 0},
|
|
{"RESERVED_0_11" , 0, 12, 740, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 12, 52, 740, "R/W", 0, 1, 4503599627370495ull, 0},
|
|
{"NPEI_P" , 0, 8, 741, "R/W", 0, 0, 128ull, 128ull},
|
|
{"NPEI_NP" , 8, 8, 741, "R/W", 0, 0, 16ull, 16ull},
|
|
{"NPEI_CPL" , 16, 8, 741, "R/W", 0, 0, 128ull, 128ull},
|
|
{"PESC_P" , 24, 8, 741, "R/W", 0, 0, 128ull, 128ull},
|
|
{"PESC_NP" , 32, 8, 741, "R/W", 0, 0, 16ull, 16ull},
|
|
{"PESC_CPL" , 40, 8, 741, "R/W", 0, 0, 128ull, 128ull},
|
|
{"PEAI_PPF" , 48, 8, 741, "R/W", 0, 0, 128ull, 128ull},
|
|
{"RESERVED_56_63" , 56, 8, 741, "RAZ", 1, 1, 0, 0},
|
|
{"BIST" , 0, 18, 742, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 742, "RAZ", 1, 1, 0, 0},
|
|
{"DPRT" , 0, 16, 743, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UDP" , 16, 1, 743, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP" , 17, 1, 743, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_18_63" , 18, 46, 743, "RAZ", 1, 1, 0, 0},
|
|
{"MAP0" , 0, 4, 744, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP1" , 4, 4, 744, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP2" , 8, 4, 744, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP3" , 12, 4, 744, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP4" , 16, 4, 744, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP5" , 20, 4, 744, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP6" , 24, 4, 744, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP7" , 28, 4, 744, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP8" , 32, 4, 744, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP9" , 36, 4, 744, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP10" , 40, 4, 744, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP11" , 44, 4, 744, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP12" , 48, 4, 744, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP13" , 52, 4, 744, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP14" , 56, 4, 744, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP15" , 60, 4, 744, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP0" , 0, 4, 745, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP1" , 4, 4, 745, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP2" , 8, 4, 745, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP3" , 12, 4, 745, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP4" , 16, 4, 745, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP5" , 20, 4, 745, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP6" , 24, 4, 745, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP7" , 28, 4, 745, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP8" , 32, 4, 745, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP9" , 36, 4, 745, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP10" , 40, 4, 745, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP11" , 44, 4, 745, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP12" , 48, 4, 745, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP13" , 52, 4, 745, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP14" , 56, 4, 745, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAP15" , 60, 4, 745, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MINLEN" , 0, 16, 746, "R/W", 0, 0, 64ull, 64ull},
|
|
{"MAXLEN" , 16, 16, 746, "R/W", 0, 0, 1536ull, 1536ull},
|
|
{"RESERVED_32_63" , 32, 32, 746, "RAZ", 1, 1, 0, 0},
|
|
{"NIP_SHF" , 0, 3, 747, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_7" , 3, 5, 747, "RAZ", 1, 1, 0, 0},
|
|
{"RAW_SHF" , 8, 3, 747, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_15" , 11, 5, 747, "RAZ", 1, 1, 0, 0},
|
|
{"MAX_L2" , 16, 1, 747, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_UDP" , 17, 1, 747, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TAG_SYN" , 18, 1, 747, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_63" , 19, 45, 747, "RAZ", 1, 1, 0, 0},
|
|
{"IP_CHK" , 0, 1, 748, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP_MAL" , 1, 1, 748, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP_HOP" , 2, 1, 748, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP4_OPTS" , 3, 1, 748, "R/W", 0, 0, 1ull, 1ull},
|
|
{"IP6_EEXT" , 4, 2, 748, "R/W", 0, 0, 1ull, 3ull},
|
|
{"RESERVED_6_7" , 6, 2, 748, "RAZ", 1, 1, 0, 0},
|
|
{"L4_MAL" , 8, 1, 748, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_PRT" , 9, 1, 748, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_CHK" , 10, 1, 748, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L4_LEN" , 11, 1, 748, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TCP_FLAG" , 12, 1, 748, "R/W", 0, 0, 1ull, 1ull},
|
|
{"L2_MAL" , 13, 1, 748, "R/W", 0, 0, 1ull, 1ull},
|
|
{"VS_QOS" , 14, 1, 748, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VS_WQE" , 15, 1, 748, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IGNRS" , 16, 1, 748, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_19" , 17, 3, 748, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RING_EN" , 20, 1, 748, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_23" , 21, 3, 748, "RAZ", 1, 1, 0, 0},
|
|
{"DSA_GRP_SID" , 24, 1, 748, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DSA_GRP_SCMD" , 25, 1, 748, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DSA_GRP_TVID" , 26, 1, 748, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_63" , 27, 37, 748, "RAZ", 1, 1, 0, 0},
|
|
{"PRI" , 0, 6, 749, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_6_7" , 6, 2, 749, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 8, 3, 749, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_11_11" , 11, 1, 749, "RAZ", 1, 1, 0, 0},
|
|
{"UP_QOS" , 12, 1, 749, "RAZ", 0, 1, 0ull, 0},
|
|
{"RESERVED_13_63" , 13, 51, 749, "RAZ", 1, 1, 0, 0},
|
|
{"PKTDRP" , 0, 1, 750, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 750, "RAZ", 1, 1, 0, 0},
|
|
{"BCKPRS" , 2, 1, 750, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 3, 1, 750, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BADTAG" , 4, 1, 750, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SKPRUNT" , 5, 1, 750, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TODOOVR" , 6, 1, 750, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FEPERR" , 7, 1, 750, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BEPERR" , 8, 1, 750, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MINERR" , 9, 1, 750, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 10, 1, 750, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 11, 1, 750, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PUNYERR" , 12, 1, 750, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 750, "RAZ", 1, 1, 0, 0},
|
|
{"PKTDRP" , 0, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_1" , 1, 1, 751, "RAZ", 1, 1, 0, 0},
|
|
{"BCKPRS" , 2, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTNXA" , 3, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BADTAG" , 4, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SKPRUNT" , 5, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TODOOVR" , 6, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FEPERR" , 7, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BEPERR" , 8, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MINERR" , 9, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MAXERR" , 10, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LENERR" , 11, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PUNYERR" , 12, 1, 751, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_63" , 13, 51, 751, "RAZ", 1, 1, 0, 0},
|
|
{"OFFSET" , 0, 3, 752, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 752, "RAZ", 1, 1, 0, 0},
|
|
{"SKIP" , 0, 7, 753, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 753, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 8, 2, 753, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DSA_EN" , 10, 1, 753, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HIGIG_EN" , 11, 1, 753, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CRC_EN" , 12, 1, 753, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 753, "RAZ", 1, 1, 0, 0},
|
|
{"QOS_VLAN" , 16, 1, 753, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS_DIFF" , 17, 1, 753, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS_VOD" , 18, 1, 753, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS_VSEL" , 19, 1, 753, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS_WAT" , 20, 4, 753, "R/W", 0, 0, 0ull, 0ull},
|
|
{"QOS" , 24, 3, 753, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HG_QOS" , 27, 1, 753, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRP_WAT" , 28, 4, 753, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INST_HDR" , 32, 1, 753, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DYN_RS" , 33, 1, 753, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TAG_INC" , 34, 2, 753, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RAWDRP" , 36, 1, 753, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_37_39" , 37, 3, 753, "RAZ", 1, 1, 0, 0},
|
|
{"QOS_WAT_47" , 40, 4, 753, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRP_WAT_47" , 44, 4, 753, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MINERR_EN" , 48, 1, 753, "R/W", 0, 0, 1ull, 1ull},
|
|
{"MAXERR_EN" , 49, 1, 753, "R/W", 0, 0, 1ull, 1ull},
|
|
{"LENERR_EN" , 50, 1, 753, "R/W", 0, 0, 1ull, 1ull},
|
|
{"VLAN_LEN" , 51, 1, 753, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PAD_LEN" , 52, 1, 753, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_53_63" , 53, 11, 753, "RAZ", 1, 1, 0, 0},
|
|
{"GRP" , 0, 4, 754, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NON_TAG_TYPE" , 4, 2, 754, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_TAG_TYPE" , 6, 2, 754, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_TAG_TYPE" , 8, 2, 754, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP4_TAG_TYPE" , 10, 2, 754, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TCP6_TAG_TYPE" , 12, 2, 754, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_SRC_FLAG" , 14, 1, 754, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_SRC_FLAG" , 15, 1, 754, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_DST_FLAG" , 16, 1, 754, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_DST_FLAG" , 17, 1, 754, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_PCTL_FLAG" , 18, 1, 754, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_NXTH_FLAG" , 19, 1, 754, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_SPRT_FLAG" , 20, 1, 754, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_SPRT_FLAG" , 21, 1, 754, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP4_DPRT_FLAG" , 22, 1, 754, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IP6_DPRT_FLAG" , 23, 1, 754, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_PRT_FLAG" , 24, 1, 754, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_VLAN" , 25, 1, 754, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC_VS" , 26, 2, 754, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TAG_MODE" , 28, 2, 754, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAG_MSKIP" , 30, 1, 754, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAG" , 31, 1, 754, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAGMASK" , 32, 4, 754, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GRPTAGBASE" , 36, 4, 754, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 754, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 0, 3, 755, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 755, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 0, 3, 756, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 756, "RAZ", 1, 1, 0, 0},
|
|
{"QOS1" , 4, 3, 756, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 756, "RAZ", 1, 1, 0, 0},
|
|
{"MATCH_VALUE" , 0, 16, 757, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MATCH_TYPE" , 16, 3, 757, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_19" , 19, 1, 757, "RAZ", 1, 1, 0, 0},
|
|
{"QOS" , 20, 3, 757, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 757, "RAZ", 1, 1, 0, 0},
|
|
{"GRP" , 24, 4, 757, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_28_31" , 28, 4, 757, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 32, 16, 757, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 757, "RAZ", 1, 1, 0, 0},
|
|
{"WORD" , 0, 56, 758, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_56_63" , 56, 8, 758, "RAZ", 1, 1, 0, 0},
|
|
{"RST" , 0, 1, 759, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 759, "RAZ", 1, 1, 0, 0},
|
|
{"DRP_OCTS" , 0, 32, 760, "R/W", 0, 1, 0ull, 0},
|
|
{"DRP_PKTS" , 32, 32, 760, "R/W", 0, 1, 0ull, 0},
|
|
{"OCTS" , 0, 48, 761, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 761, "RAZ", 1, 1, 0, 0},
|
|
{"RAW" , 0, 32, 762, "R/W", 0, 1, 0ull, 0},
|
|
{"PKTS" , 32, 32, 762, "R/W", 0, 1, 0ull, 0},
|
|
{"MCST" , 0, 32, 763, "R/W", 0, 1, 0ull, 0},
|
|
{"BCST" , 32, 32, 763, "R/W", 0, 1, 0ull, 0},
|
|
{"H64" , 0, 32, 764, "R/W", 0, 1, 0ull, 0},
|
|
{"H65TO127" , 32, 32, 764, "R/W", 0, 1, 0ull, 0},
|
|
{"H128TO255" , 0, 32, 765, "R/W", 0, 1, 0ull, 0},
|
|
{"H256TO511" , 32, 32, 765, "R/W", 0, 1, 0ull, 0},
|
|
{"H512TO1023" , 0, 32, 766, "R/W", 0, 1, 0ull, 0},
|
|
{"H1024TO1518" , 32, 32, 766, "R/W", 0, 1, 0ull, 0},
|
|
{"H1519" , 0, 32, 767, "R/W", 0, 1, 0ull, 0},
|
|
{"FCS" , 32, 32, 767, "R/W", 0, 1, 0ull, 0},
|
|
{"UNDERSZ" , 0, 32, 768, "R/W", 0, 1, 0ull, 0},
|
|
{"FRAG" , 32, 32, 768, "R/W", 0, 1, 0ull, 0},
|
|
{"OVERSZ" , 0, 32, 769, "R/W", 0, 1, 0ull, 0},
|
|
{"JABBER" , 32, 32, 769, "R/W", 0, 1, 0ull, 0},
|
|
{"RDCLR" , 0, 1, 770, "R/W", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 770, "RAZ", 1, 1, 0, 0},
|
|
{"ERRS" , 0, 16, 771, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_16_63" , 16, 48, 771, "RAZ", 1, 1, 0, 0},
|
|
{"OCTS" , 0, 48, 772, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 772, "RAZ", 1, 1, 0, 0},
|
|
{"PKTS" , 0, 32, 773, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 773, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 8, 774, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_8_63" , 8, 56, 774, "RAZ", 1, 1, 0, 0},
|
|
{"MASK" , 0, 16, 775, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 775, "RAZ", 1, 1, 0, 0},
|
|
{"SRC" , 0, 16, 776, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DST" , 16, 16, 776, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 776, "RAZ", 1, 1, 0, 0},
|
|
{"ENTRY" , 0, 62, 777, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_62_62" , 62, 1, 777, "RAZ", 1, 1, 0, 0},
|
|
{"VAL" , 63, 1, 777, "RO", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 32, 778, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 778, "RAZ", 1, 1, 0, 0},
|
|
{"COUNT" , 0, 48, 779, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 779, "RAZ", 1, 1, 0, 0},
|
|
{"SIZE" , 0, 16, 780, "RO", 1, 0, 0, 0ull},
|
|
{"SEGS" , 16, 6, 780, "RO", 1, 0, 0, 0ull},
|
|
{"CMD" , 22, 14, 780, "RO", 1, 0, 0, 0ull},
|
|
{"FAU" , 36, 28, 780, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 781, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 781, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 781, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 781, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 781, "RO", 1, 0, 0, 0ull},
|
|
{"PTRS2" , 0, 17, 782, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 782, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTRS1" , 32, 17, 782, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 782, "RAZ", 1, 0, 0, 0ull},
|
|
{"MOD" , 0, 3, 783, "RO", 1, 0, 0, 0ull},
|
|
{"CNT" , 3, 13, 783, "RO", 1, 0, 0, 0ull},
|
|
{"CHK" , 16, 1, 783, "RO", 1, 0, 0, 0ull},
|
|
{"LEN" , 17, 1, 783, "RO", 1, 0, 0, 0ull},
|
|
{"SOP" , 18, 1, 783, "RO", 1, 0, 0, 0ull},
|
|
{"UID" , 19, 3, 783, "RO", 1, 0, 0, 0ull},
|
|
{"MAJ" , 22, 1, 783, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 783, "RAZ", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 16, 784, "RO", 1, 0, 0, 0ull},
|
|
{"SEGS" , 16, 6, 784, "RO", 1, 0, 0, 0ull},
|
|
{"CMD" , 22, 14, 784, "RO", 1, 0, 0, 0ull},
|
|
{"FAU" , 36, 28, 784, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 785, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 785, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 785, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 785, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 785, "RO", 1, 0, 0, 0ull},
|
|
{"DATA" , 0, 64, 786, "RO", 1, 0, 0, 0ull},
|
|
{"PTR" , 0, 40, 787, "RO", 1, 0, 0, 0ull},
|
|
{"SIZE" , 40, 16, 787, "RO", 1, 0, 0, 0ull},
|
|
{"POOL" , 56, 3, 787, "RO", 1, 0, 0, 0ull},
|
|
{"BACK" , 59, 4, 787, "RO", 1, 0, 0, 0ull},
|
|
{"I" , 63, 1, 787, "RO", 1, 0, 0, 0ull},
|
|
{"DATA" , 0, 64, 788, "RO", 1, 0, 0, 0ull},
|
|
{"MAJOR" , 0, 3, 789, "RO", 1, 0, 0, 0ull},
|
|
{"MINOR" , 3, 2, 789, "RO", 1, 0, 0, 0ull},
|
|
{"WAIT" , 5, 1, 789, "RO", 1, 0, 0, 0ull},
|
|
{"CHK_MODE" , 6, 1, 789, "RO", 1, 0, 0, 0ull},
|
|
{"CHK_ONCE" , 7, 1, 789, "RO", 1, 0, 0, 0ull},
|
|
{"INIT_DWRITE" , 8, 1, 789, "RO", 1, 0, 0, 0ull},
|
|
{"DREAD_SOP" , 9, 1, 789, "RO", 1, 0, 0, 0ull},
|
|
{"UID" , 10, 2, 789, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_OFF" , 12, 6, 789, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_SIZ" , 18, 16, 789, "RO", 1, 0, 0, 0ull},
|
|
{"CMND_SEGS" , 34, 6, 789, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_OFF" , 40, 16, 789, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_SIZ" , 56, 8, 789, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_SIZ" , 0, 8, 790, "RO", 1, 0, 0, 0ull},
|
|
{"CURR_PTR" , 8, 40, 790, "RO", 1, 0, 0, 0ull},
|
|
{"NXT_INFLT" , 48, 6, 790, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_54_63" , 54, 10, 790, "RAZ", 1, 0, 0, 0ull},
|
|
{"QID_BASE" , 0, 8, 791, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFF" , 8, 4, 791, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFFMAX" , 12, 4, 791, "RO", 1, 0, 0, 0ull},
|
|
{"QCB_RIDX" , 16, 5, 791, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 21, 3, 791, "RO", 1, 0, 0, 0ull},
|
|
{"STATC" , 24, 1, 791, "RO", 1, 0, 0, 0ull},
|
|
{"ACTIVE" , 25, 1, 791, "RO", 1, 0, 0, 0ull},
|
|
{"PREEMPTED" , 26, 1, 791, "RO", 1, 0, 0, 0ull},
|
|
{"PREEMPTEE" , 27, 1, 791, "RO", 1, 0, 0, 0ull},
|
|
{"PREEMPTER" , 28, 1, 791, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFFTHS" , 29, 4, 791, "RO", 1, 0, 0, 0ull},
|
|
{"QID_OFFRES" , 33, 4, 791, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_37_63" , 37, 27, 791, "RAZ", 1, 0, 0, 0ull},
|
|
{"QCB_RIDX" , 0, 6, 792, "RO", 1, 0, 0, 0ull},
|
|
{"QCB_WIDX" , 6, 6, 792, "RO", 1, 0, 0, 0ull},
|
|
{"BUF_PTR" , 12, 33, 792, "RO", 1, 0, 0, 0ull},
|
|
{"BUF_SIZ" , 45, 13, 792, "RO", 1, 0, 0, 0ull},
|
|
{"TAIL" , 58, 1, 792, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 59, 5, 792, "RO", 1, 0, 0, 0ull},
|
|
{"QOS" , 0, 3, 793, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_Q" , 3, 1, 793, "RO", 1, 0, 0, 0ull},
|
|
{"S_TAIL" , 4, 1, 793, "RO", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 5, 1, 793, "RO", 1, 0, 0, 0ull},
|
|
{"PREEMPTEE" , 6, 1, 793, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 793, "RAZ", 1, 0, 0, 0ull},
|
|
{"DOORBELL" , 8, 20, 793, "RO", 1, 0, 0, 0ull},
|
|
{"PREEMPTER" , 28, 1, 793, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_29_63" , 29, 35, 793, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTRS3" , 0, 17, 794, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 794, "RAZ", 1, 0, 0, 0ull},
|
|
{"PTRS0" , 32, 17, 794, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_49_63" , 49, 15, 794, "RAZ", 1, 0, 0, 0ull},
|
|
{"PID" , 0, 6, 795, "R/W", 1, 0, 0, 0ull},
|
|
{"EID" , 6, 4, 795, "R/W", 1, 0, 0, 0ull},
|
|
{"BP_PORT" , 10, 6, 795, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_16_52" , 16, 37, 795, "RAZ", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 795, "R/W", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 61, 1, 795, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_62_63" , 62, 2, 795, "RAZ", 1, 0, 0, 0ull},
|
|
{"PID" , 0, 6, 796, "R/W", 1, 0, 0, 0ull},
|
|
{"EID" , 6, 4, 796, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_10_52" , 10, 43, 796, "RAZ", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 796, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_61_63" , 61, 3, 796, "RAZ", 1, 0, 0, 0ull},
|
|
{"PID" , 0, 6, 797, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 797, "RAZ", 1, 0, 0, 0ull},
|
|
{"RATE_PKT" , 8, 24, 797, "R/W", 1, 0, 0, 0ull},
|
|
{"RATE_WORD" , 32, 19, 797, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_51_63" , 51, 13, 797, "RAZ", 1, 0, 0, 0ull},
|
|
{"PID" , 0, 6, 798, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_6_7" , 6, 2, 798, "RAZ", 1, 0, 0, 0ull},
|
|
{"RATE_LIM" , 8, 24, 798, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 798, "RAZ", 1, 0, 0, 0ull},
|
|
{"QUEUE" , 0, 7, 799, "R/W", 1, 0, 0, 0ull},
|
|
{"PORT" , 7, 6, 799, "WR0", 1, 0, 0, 0ull},
|
|
{"INDEX" , 13, 3, 799, "WR0", 1, 0, 0, 0ull},
|
|
{"TAIL" , 16, 1, 799, "R/W", 1, 0, 0, 0ull},
|
|
{"BUF_PTR" , 17, 36, 799, "R/W", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 799, "R/W", 1, 0, 0, 0ull},
|
|
{"STATIC_Q" , 61, 1, 799, "R/W", 1, 0, 0, 0ull},
|
|
{"STATIC_P" , 62, 1, 799, "R/W", 1, 0, 0, 0ull},
|
|
{"S_TAIL" , 63, 1, 799, "R/W", 1, 0, 0, 0ull},
|
|
{"QID" , 0, 7, 800, "R/W", 1, 0, 0, 0ull},
|
|
{"PID" , 7, 6, 800, "WR0", 1, 0, 0, 0ull},
|
|
{"RESERVED_13_52" , 13, 40, 800, "RAZ", 1, 0, 0, 0ull},
|
|
{"QOS_MASK" , 53, 8, 800, "R/W", 1, 0, 0, 0ull},
|
|
{"RESERVED_61_63" , 61, 3, 800, "RAZ", 1, 0, 0, 0ull},
|
|
{"DAT_PTR" , 0, 4, 801, "RO", 1, 0, 0, 0ull},
|
|
{"DAT_DAT" , 4, 2, 801, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_CTL" , 6, 2, 801, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_QSB" , 8, 3, 801, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_QCB" , 11, 2, 801, "RO", 1, 0, 0, 0ull},
|
|
{"NCB_INB" , 13, 2, 801, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_PSB" , 15, 8, 801, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_NXT" , 23, 1, 801, "RO", 1, 0, 0, 0ull},
|
|
{"PRT_CHK" , 24, 3, 801, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_WIF" , 27, 1, 801, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_STA" , 28, 1, 801, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_CTL" , 29, 3, 801, "RO", 1, 0, 0, 0ull},
|
|
{"OUT_DAT" , 32, 1, 801, "RO", 1, 0, 0, 0ull},
|
|
{"IOB" , 33, 1, 801, "RO", 1, 0, 0, 0ull},
|
|
{"CSR" , 34, 1, 801, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_35_63" , 35, 29, 801, "RAZ", 1, 0, 0, 0ull},
|
|
{"SIZE" , 0, 13, 802, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_19" , 13, 7, 802, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 20, 3, 802, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_63" , 23, 41, 802, "RAZ", 1, 0, 0, 0ull},
|
|
{"ASSERTS" , 0, 64, 803, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 64, 804, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 64, 805, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 64, 806, "RO", 0, 0, 0ull, 0ull},
|
|
{"ENGINE0" , 0, 4, 807, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE1" , 4, 4, 807, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE2" , 8, 4, 807, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE3" , 12, 4, 807, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE4" , 16, 4, 807, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENGINE5" , 20, 4, 807, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENGINE6" , 24, 4, 807, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENGINE7" , 28, 4, 807, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENGINE8" , 32, 4, 807, "R/W", 0, 0, 4ull, 4ull},
|
|
{"ENGINE9" , 36, 4, 807, "R/W", 0, 0, 4ull, 4ull},
|
|
{"RESERVED_40_63" , 40, 24, 807, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 10, 808, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_63" , 10, 54, 808, "RAZ", 1, 0, 0, 0ull},
|
|
{"PARITY" , 0, 1, 809, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 1, 1, 809, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CURRZERO" , 2, 1, 809, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 809, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENA_PKO" , 0, 1, 810, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENA_DWB" , 1, 1, 810, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STORE_BE" , 2, 1, 810, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 3, 1, 810, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 810, "RAZ", 1, 0, 0, 0ull},
|
|
{"MODE0" , 0, 3, 811, "R/W", 0, 0, 2ull, 2ull},
|
|
{"MODE1" , 3, 3, 811, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 811, "RAZ", 1, 0, 0, 0ull},
|
|
{"PARITY" , 0, 1, 812, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 1, 1, 812, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CURRZERO" , 2, 1, 812, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 812, "RAZ", 1, 0, 0, 0ull},
|
|
{"MODE" , 0, 2, 813, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 813, "RAZ", 1, 0, 0, 0ull},
|
|
{"QID7" , 0, 1, 814, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IDX3" , 1, 1, 814, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 814, "RAZ", 1, 0, 0, 0ull},
|
|
{"INDEX" , 0, 8, 815, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 8, 8, 815, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 815, "RAZ", 1, 0, 0, 0ull},
|
|
{"ADR" , 0, 1, 816, "RO", 0, 0, 0ull, 0ull},
|
|
{"PEND" , 1, 1, 816, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBR0" , 2, 1, 816, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBR1" , 3, 1, 816, "RO", 0, 0, 0ull, 0ull},
|
|
{"FIDX" , 4, 1, 816, "RO", 0, 0, 0ull, 0ull},
|
|
{"INDEX" , 5, 1, 816, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBT0" , 6, 1, 816, "RO", 0, 0, 0ull, 0ull},
|
|
{"NBT1" , 7, 1, 816, "RO", 0, 0, 0ull, 0ull},
|
|
{"CAM" , 8, 1, 816, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_15" , 9, 7, 816, "RAZ", 1, 1, 0, 0},
|
|
{"PP" , 16, 4, 816, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 816, "RAZ", 1, 1, 0, 0},
|
|
{"DS_PC" , 0, 32, 817, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 817, "RAZ", 1, 1, 0, 0},
|
|
{"SBE" , 0, 1, 818, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DBE" , 1, 1, 818, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SBE_IE" , 2, 1, 818, "R/W", 0, 1, 0ull, 0},
|
|
{"DBE_IE" , 3, 1, 818, "R/W", 0, 1, 0ull, 0},
|
|
{"SYN" , 4, 5, 818, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_9_11" , 9, 3, 818, "RAZ", 1, 1, 0, 0},
|
|
{"RPE" , 12, 1, 818, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RPE_IE" , 13, 1, 818, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_14_15" , 14, 2, 818, "RAZ", 1, 1, 0, 0},
|
|
{"IOP" , 16, 13, 818, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_29_31" , 29, 3, 818, "RAZ", 1, 1, 0, 0},
|
|
{"IOP_IE" , 32, 13, 818, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_45_63" , 45, 19, 818, "RAZ", 1, 1, 0, 0},
|
|
{"NBR_THR" , 0, 5, 819, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PFR_DIS" , 5, 1, 819, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 819, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 32, 820, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 820, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 32, 821, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 821, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_INT" , 0, 8, 822, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 822, "RAZ", 1, 1, 0, 0},
|
|
{"INT_EN" , 0, 8, 823, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 823, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_THR" , 0, 32, 824, "R/W", 0, 1, 4294967295ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 824, "RAZ", 1, 1, 0, 0},
|
|
{"NOS_CNT" , 0, 10, 825, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_10_63" , 10, 54, 825, "RAZ", 1, 1, 0, 0},
|
|
{"NW_TIM" , 0, 10, 826, "R/W", 0, 0, 0ull, 1023ull},
|
|
{"RESERVED_10_63" , 10, 54, 826, "RAZ", 1, 1, 0, 0},
|
|
{"RST_MSK" , 0, 8, 827, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_8_63" , 8, 56, 827, "RAZ", 1, 1, 0, 0},
|
|
{"GRP_MSK" , 0, 16, 828, "R/W", 0, 0, 65535ull, 65535ull},
|
|
{"QOS0_PRI" , 16, 4, 828, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS1_PRI" , 20, 4, 828, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS2_PRI" , 24, 4, 828, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS3_PRI" , 28, 4, 828, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS4_PRI" , 32, 4, 828, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS5_PRI" , 36, 4, 828, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS6_PRI" , 40, 4, 828, "R/W", 0, 1, 0ull, 0},
|
|
{"QOS7_PRI" , 44, 4, 828, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_48_63" , 48, 16, 828, "RAZ", 1, 1, 0, 0},
|
|
{"RND" , 0, 8, 829, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P1" , 8, 8, 829, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P2" , 16, 8, 829, "R/W", 0, 1, 255ull, 0},
|
|
{"RND_P3" , 24, 8, 829, "R/W", 0, 1, 255ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 829, "RAZ", 1, 1, 0, 0},
|
|
{"MIN_THR" , 0, 9, 830, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_9_11" , 9, 3, 830, "RAZ", 1, 1, 0, 0},
|
|
{"MAX_THR" , 12, 9, 830, "R/W", 0, 1, 511ull, 0},
|
|
{"RESERVED_21_23" , 21, 3, 830, "RAZ", 1, 1, 0, 0},
|
|
{"FREE_CNT" , 24, 10, 830, "RO", 0, 1, 503ull, 0},
|
|
{"RESERVED_34_35" , 34, 2, 830, "RAZ", 1, 1, 0, 0},
|
|
{"BUF_CNT" , 36, 10, 830, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_46_47" , 46, 2, 830, "RAZ", 1, 1, 0, 0},
|
|
{"DES_CNT" , 48, 10, 830, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_58_63" , 58, 6, 830, "RAZ", 1, 1, 0, 0},
|
|
{"TS_PC" , 0, 32, 831, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 831, "RAZ", 1, 1, 0, 0},
|
|
{"WA_PC" , 0, 32, 832, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 832, "RAZ", 1, 1, 0, 0},
|
|
{"WA_PC" , 0, 32, 833, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 833, "RAZ", 1, 1, 0, 0},
|
|
{"WQ_INT" , 0, 16, 834, "R/W1C", 0, 1, 0ull, 0},
|
|
{"IQ_DIS" , 16, 16, 834, "R/W1", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 834, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_CNT" , 0, 10, 835, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_10_11" , 10, 2, 835, "RAZ", 1, 1, 0, 0},
|
|
{"DS_CNT" , 12, 10, 835, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_22_23" , 22, 2, 835, "RAZ", 1, 1, 0, 0},
|
|
{"TC_CNT" , 24, 4, 835, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_63" , 28, 36, 835, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_7" , 0, 8, 836, "RAZ", 1, 1, 0, 0},
|
|
{"PC_THR" , 8, 20, 836, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_28_31" , 28, 4, 836, "RAZ", 1, 1, 0, 0},
|
|
{"PC" , 32, 28, 836, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_60_63" , 60, 4, 836, "RAZ", 1, 1, 0, 0},
|
|
{"IQ_THR" , 0, 9, 837, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_9_11" , 9, 3, 837, "RAZ", 1, 1, 0, 0},
|
|
{"DS_THR" , 12, 9, 837, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_21_23" , 21, 3, 837, "RAZ", 1, 1, 0, 0},
|
|
{"TC_THR" , 24, 4, 837, "R/W", 0, 1, 0ull, 0},
|
|
{"TC_EN" , 28, 1, 837, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_29_63" , 29, 35, 837, "RAZ", 1, 1, 0, 0},
|
|
{"WS_PC" , 0, 32, 838, "R/W1C", 0, 1, 0ull, 0},
|
|
{"RESERVED_32_63" , 32, 32, 838, "RAZ", 1, 1, 0, 0},
|
|
{"IWORD" , 0, 64, 839, "RO", 1, 1, 0, 0},
|
|
{"P_DAT" , 0, 64, 840, "RO", 1, 1, 0, 0},
|
|
{"Q_DAT" , 0, 64, 841, "RO", 1, 1, 0, 0},
|
|
{"DAT" , 0, 2, 842, "RO", 1, 0, 0, 0ull},
|
|
{"NCB_INB" , 2, 2, 842, "RO", 1, 0, 0, 0ull},
|
|
{"NCB_OUB" , 4, 1, 842, "RO", 1, 0, 0, 0ull},
|
|
{"STA" , 5, 1, 842, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 842, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PTR" , 0, 33, 843, "R/W", 0, 1, 0ull, 0},
|
|
{"SIZE" , 33, 13, 843, "R/W", 0, 1, 0ull, 0},
|
|
{"POOL" , 46, 3, 843, "R/W", 0, 1, 0ull, 0},
|
|
{"DWB" , 49, 9, 843, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_58_63" , 58, 6, 843, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 0, 1, 844, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STORE_LE" , 1, 1, 844, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MAX_READ" , 2, 4, 844, "R/W", 0, 0, 8ull, 8ull},
|
|
{"RESERVED_6_63" , 6, 58, 844, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"STATE" , 0, 5, 845, "RO", 1, 1, 0, 0},
|
|
{"COMMIT" , 5, 1, 845, "RO", 1, 1, 0, 0},
|
|
{"OWORDPV" , 6, 1, 845, "RO", 1, 1, 0, 0},
|
|
{"OWORDQV" , 7, 1, 845, "RO", 1, 1, 0, 0},
|
|
{"IWIDX" , 8, 6, 845, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_14_15" , 14, 2, 845, "RAZ", 1, 1, 0, 0},
|
|
{"IRIDX" , 16, 6, 845, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_22_31" , 22, 10, 845, "RAZ", 1, 1, 0, 0},
|
|
{"LOOP" , 32, 25, 845, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_57_63" , 57, 7, 845, "RAZ", 1, 1, 0, 0},
|
|
{"CWORD" , 0, 64, 846, "RO", 1, 1, 0, 0},
|
|
{"PTR" , 0, 40, 847, "RO", 1, 1, 0, 0},
|
|
{"SIZE" , 40, 16, 847, "RO", 1, 1, 0, 0},
|
|
{"FLAGS" , 56, 8, 847, "RO", 1, 1, 0, 0},
|
|
{"INDEX" , 0, 8, 848, "RO", 1, 1, 0, 0},
|
|
{"SOD" , 8, 1, 848, "RO", 1, 1, 0, 0},
|
|
{"EOD" , 9, 1, 848, "RO", 1, 1, 0, 0},
|
|
{"WC" , 10, 1, 848, "RO", 1, 1, 0, 0},
|
|
{"P" , 11, 1, 848, "RO", 1, 1, 0, 0},
|
|
{"Q" , 12, 1, 848, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_13_63" , 13, 51, 848, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ASSERTS" , 0, 15, 849, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_15_63" , 15, 49, 849, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"OWORDP" , 0, 64, 850, "RO", 1, 1, 0, 0},
|
|
{"OWORDQ" , 0, 64, 851, "RO", 1, 1, 0, 0},
|
|
{"RWORD" , 0, 64, 852, "RO", 1, 1, 0, 0},
|
|
{"N0CREDS" , 0, 4, 853, "RO", 0, 0, 8ull, 0ull},
|
|
{"N1CREDS" , 4, 4, 853, "RO", 0, 0, 8ull, 0ull},
|
|
{"POWCREDS" , 8, 2, 853, "RO", 0, 0, 2ull, 0ull},
|
|
{"RESERVED_10_11" , 10, 2, 853, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"FPACREDS" , 12, 2, 853, "RO", 0, 0, 1ull, 0ull},
|
|
{"WCCREDS" , 14, 2, 853, "RO", 0, 0, 0ull, 0ull},
|
|
{"NIWIDX0" , 16, 4, 853, "RO", 1, 1, 0, 0},
|
|
{"NIRIDX0" , 20, 4, 853, "RO", 1, 1, 0, 0},
|
|
{"NIWIDX1" , 24, 4, 853, "RO", 1, 1, 0, 0},
|
|
{"NIRIDX1" , 28, 4, 853, "RO", 1, 1, 0, 0},
|
|
{"NIRVAL6" , 32, 5, 853, "RO", 1, 1, 0, 0},
|
|
{"NIRARB6" , 37, 1, 853, "RO", 1, 1, 0, 0},
|
|
{"NIRQUE6" , 38, 2, 853, "RO", 1, 1, 0, 0},
|
|
{"NIROPC6" , 40, 3, 853, "RO", 1, 1, 0, 0},
|
|
{"NIRVAL7" , 43, 5, 853, "RO", 1, 1, 0, 0},
|
|
{"NIRQUE7" , 48, 2, 853, "RO", 1, 1, 0, 0},
|
|
{"NIROPC7" , 50, 3, 853, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_53_63" , 53, 11, 853, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PTR" , 0, 40, 854, "RO", 1, 1, 0, 0},
|
|
{"SIZE" , 40, 16, 854, "RO", 1, 1, 0, 0},
|
|
{"CNT" , 56, 8, 854, "RO", 1, 1, 0, 0},
|
|
{"CNT" , 0, 15, 855, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_15_63" , 15, 49, 855, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PTR" , 0, 40, 856, "RO", 1, 1, 0, 0},
|
|
{"SIZE" , 40, 16, 856, "RO", 1, 1, 0, 0},
|
|
{"FLAGS" , 56, 8, 856, "RO", 1, 1, 0, 0},
|
|
{"INDEX" , 0, 8, 857, "RO", 1, 1, 0, 0},
|
|
{"MUL" , 8, 8, 857, "RO", 1, 1, 0, 0},
|
|
{"P" , 16, 1, 857, "RO", 1, 1, 0, 0},
|
|
{"Q" , 17, 1, 857, "RO", 1, 1, 0, 0},
|
|
{"INI" , 18, 1, 857, "RO", 1, 1, 0, 0},
|
|
{"EOD" , 19, 1, 857, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_20_63" , 20, 44, 857, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 0, 1, 858, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 858, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DOORBELL" , 0, 1, 859, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_1_63" , 1, 63, 859, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"COEFFS" , 0, 8, 860, "R/W", 0, 0, 29ull, 29ull},
|
|
{"RESERVED_8_63" , 8, 56, 860, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"INDEX" , 0, 16, 861, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 16, 16, 861, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_32_63" , 32, 32, 861, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MEM" , 0, 1, 862, "RO", 0, 0, 0ull, 0ull},
|
|
{"RRC" , 1, 1, 862, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_63" , 2, 62, 862, "RAZ", 1, 1, 0, 0},
|
|
{"ENT_EN" , 0, 1, 863, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNG_EN" , 1, 1, 863, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNM_RST" , 2, 1, 863, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RNG_RST" , 3, 1, 863, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EXP_ENT" , 4, 1, 863, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENT_SEL" , 5, 4, 863, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_63" , 9, 55, 863, "RAZ", 1, 1, 0, 0},
|
|
{"PHASE" , 0, 8, 864, "R/W", 0, 0, 100ull, 100ull},
|
|
{"SAMPLE" , 8, 4, 864, "R/W", 0, 0, 2ull, 2ull},
|
|
{"PREAMBLE" , 12, 1, 864, "R/W", 0, 0, 1ull, 1ull},
|
|
{"CLK_IDLE" , 13, 1, 864, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_14_14" , 14, 1, 864, "RAZ", 1, 1, 0, 0},
|
|
{"SAMPLE_MODE" , 15, 1, 864, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SAMPLE_HI" , 16, 5, 864, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_23" , 21, 3, 864, "RAZ", 1, 1, 0, 0},
|
|
{"MODE" , 24, 1, 864, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_63" , 25, 39, 864, "RAZ", 1, 1, 0, 0},
|
|
{"REG_ADR" , 0, 5, 865, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_5_7" , 5, 3, 865, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_ADR" , 8, 5, 865, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_13_15" , 13, 3, 865, "RAZ", 1, 1, 0, 0},
|
|
{"PHY_OP" , 16, 2, 865, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 865, "RAZ", 1, 1, 0, 0},
|
|
{"EN" , 0, 1, 866, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_1_63" , 1, 63, 866, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 867, "RO", 0, 1, 0ull, 0},
|
|
{"VAL" , 16, 1, 867, "RO", 0, 1, 0ull, 0},
|
|
{"PENDING" , 17, 1, 867, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 867, "RAZ", 1, 1, 0, 0},
|
|
{"DAT" , 0, 16, 868, "R/W", 0, 1, 0ull, 0},
|
|
{"VAL" , 16, 1, 868, "RO", 0, 1, 0ull, 0},
|
|
{"PENDING" , 17, 1, 868, "RO", 0, 1, 0ull, 0},
|
|
{"RESERVED_18_63" , 18, 46, 868, "RAZ", 1, 1, 0, 0},
|
|
{"INTERVAL" , 0, 22, 869, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 869, "RAZ", 1, 0, 0, 0ull},
|
|
{"COUNT" , 24, 22, 869, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_46_46" , 46, 1, 869, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENA" , 47, 1, 869, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_48_63" , 48, 16, 869, "RAZ", 1, 0, 0, 0ull},
|
|
{"BSIZE" , 0, 20, 870, "RO", 1, 0, 0, 0ull},
|
|
{"BASE" , 20, 31, 870, "RO", 1, 0, 0, 0ull},
|
|
{"BUCKET" , 51, 13, 870, "RO", 1, 0, 0, 0ull},
|
|
{"BUCKET" , 0, 7, 871, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_7_7" , 7, 1, 871, "RAZ", 1, 0, 0, 0ull},
|
|
{"CSIZE" , 8, 13, 871, "RO", 1, 0, 0, 0ull},
|
|
{"CPOOL" , 21, 3, 871, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_24_63" , 24, 40, 871, "RAZ", 1, 0, 0, 0ull},
|
|
{"RING" , 0, 4, 872, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NUM_BUCKETS" , 4, 20, 872, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FIRST_BUCKET" , 24, 31, 872, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_55_63" , 55, 9, 872, "RAZ", 1, 0, 0, 0ull},
|
|
{"RING" , 0, 4, 873, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTERVAL" , 4, 22, 873, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WORDS_PER_CHUNK" , 26, 13, 873, "R/W", 0, 0, 0ull, 0ull},
|
|
{"POOL" , 39, 3, 873, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENABLE" , 42, 1, 873, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_43_63" , 43, 21, 873, "RAZ", 1, 0, 0, 0ull},
|
|
{"CTL" , 0, 1, 874, "RO", 1, 0, 0, 0ull},
|
|
{"NCB" , 1, 1, 874, "RO", 1, 0, 0, 0ull},
|
|
{"STA" , 2, 2, 874, "RO", 1, 0, 0, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 874, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 16, 875, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 875, "RAZ", 1, 0, 0, 0ull},
|
|
{"ENABLE_TIMERS" , 0, 1, 876, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENABLE_DWB" , 1, 1, 876, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESET" , 2, 1, 876, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 876, "RAZ", 1, 0, 0, 0ull},
|
|
{"MASK" , 0, 16, 877, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 877, "RAZ", 1, 0, 0, 0ull},
|
|
{"INDEX" , 0, 8, 878, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INC" , 8, 8, 878, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_63" , 16, 48, 878, "RAZ", 1, 0, 0, 0ull},
|
|
{"TDF0" , 0, 1, 879, "RO", 0, 0, 0ull, 0ull},
|
|
{"TDF1" , 1, 1, 879, "RO", 0, 0, 0ull, 0ull},
|
|
{"TCF" , 2, 1, 879, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_63" , 3, 61, 879, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ENA" , 0, 1, 880, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WRAP" , 1, 1, 880, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TRIG_CTL" , 2, 2, 880, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIME_GRN" , 4, 3, 880, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FULL_THR" , 7, 2, 880, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CIU_TRG" , 9, 1, 880, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CIU_THR" , 10, 1, 880, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_TRG" , 11, 1, 880, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_THR" , 12, 1, 880, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MCD0_ENA" , 13, 1, 880, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IGNORE_O" , 14, 1, 880, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_15_63" , 15, 49, 880, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"WPTR" , 0, 8, 881, "RO", 0, 0, 0ull, 0ull},
|
|
{"RPTR" , 8, 8, 881, "RO", 0, 0, 0ull, 0ull},
|
|
{"CYCLES" , 16, 48, 881, "RO", 0, 0, 0ull, 0ull},
|
|
{"WPTR" , 0, 10, 882, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_11" , 10, 2, 882, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"RPTR" , 12, 10, 882, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_23" , 22, 2, 882, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CYCLES" , 24, 40, 882, "RO", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 883, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 883, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 884, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 884, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 885, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 885, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 885, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 885, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 885, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 885, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 885, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 885, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 885, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 885, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 885, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 885, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 885, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 885, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 885, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 885, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SAA" , 16, 1, 885, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_17_63" , 17, 47, 885, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 886, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 886, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 886, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 886, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 886, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 886, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 886, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 886, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 886, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 886, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 886, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 886, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 887, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 887, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 887, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 887, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 887, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 887, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"CIU_TRG" , 0, 1, 888, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CIU_THR" , 1, 1, 888, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MCD0_TRG" , 2, 1, 888, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"MCD0_THR" , 3, 1, 888, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_63" , 4, 60, 888, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DATA" , 0, 64, 889, "RO", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 890, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 890, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 891, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 891, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 892, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 892, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 892, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 892, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 892, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 892, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 892, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 892, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 892, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 892, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 892, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 892, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 892, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 892, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 892, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 892, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SAA" , 16, 1, 892, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_17_63" , 17, 47, 892, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 893, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 893, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 893, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 893, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 893, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 893, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 893, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 893, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 893, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 893, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 893, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 893, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 894, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 894, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 895, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 895, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"ADR" , 0, 36, 896, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_36_63" , 36, 28, 896, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 0, 1, 897, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PL2" , 1, 1, 897, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PSL1" , 2, 1, 897, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDD" , 3, 1, 897, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDI" , 4, 1, 897, "R/W", 0, 0, 0ull, 1ull},
|
|
{"LDT" , 5, 1, 897, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STF" , 6, 1, 897, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STC" , 7, 1, 897, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STP" , 8, 1, 897, "R/W", 0, 0, 0ull, 1ull},
|
|
{"STT" , 9, 1, 897, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD8" , 10, 1, 897, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD16" , 11, 1, 897, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD32" , 12, 1, 897, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBLD64" , 13, 1, 897, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBST" , 14, 1, 897, "R/W", 0, 0, 0ull, 1ull},
|
|
{"IOBDMA" , 15, 1, 897, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SAA" , 16, 1, 897, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_17_63" , 17, 47, 897, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"MIO" , 0, 1, 898, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL3" , 1, 2, 898, "R/W", 0, 0, 0ull, 3ull},
|
|
{"PCI" , 3, 1, 898, "R/W", 0, 0, 0ull, 1ull},
|
|
{"KEY" , 4, 1, 898, "R/W", 0, 0, 0ull, 1ull},
|
|
{"FPA" , 5, 1, 898, "R/W", 0, 0, 0ull, 1ull},
|
|
{"DFA" , 6, 1, 898, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ZIP" , 7, 1, 898, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RNG" , 8, 1, 898, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL2" , 9, 3, 898, "R/W", 0, 0, 0ull, 7ull},
|
|
{"POW" , 12, 1, 898, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ILLEGAL" , 13, 19, 898, "R/W", 0, 0, 0ull, 524287ull},
|
|
{"RESERVED_32_63" , 32, 32, 898, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"PP" , 0, 16, 899, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKI" , 16, 1, 899, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKO" , 17, 1, 899, "R/W", 0, 0, 0ull, 0ull},
|
|
{"IOBREQ" , 18, 1, 899, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DWB" , 19, 1, 899, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_63" , 20, 44, 899, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"INEPINT" , 0, 16, 900, "RO", 0, 0, 0ull, 0ull},
|
|
{"OUTEPINT" , 16, 16, 900, "RO", 0, 0, 0ull, 0ull},
|
|
{"INEPMSK" , 0, 16, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OUTEPMSK" , 16, 16, 901, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DEVSPD" , 0, 2, 902, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NZSTSOUTHSHK" , 2, 1, 902, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_3" , 3, 1, 902, "RAZ", 1, 1, 0, 0},
|
|
{"DEVADDR" , 4, 7, 902, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PERFRINT" , 11, 2, 902, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_17" , 13, 5, 902, "RAZ", 1, 1, 0, 0},
|
|
{"EPMISCNT" , 18, 5, 902, "R/W", 0, 0, 8ull, 0ull},
|
|
{"RESERVED_23_31" , 23, 9, 902, "RAZ", 1, 1, 0, 0},
|
|
{"RMTWKUPSIG" , 0, 1, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SFTDISCON" , 1, 1, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GNPINNAKSTS" , 2, 1, 903, "RO", 0, 0, 0ull, 0ull},
|
|
{"GOUTNAKSTS" , 3, 1, 903, "RO", 0, 0, 0ull, 0ull},
|
|
{"TSTCTL" , 4, 3, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SGNPINNAK" , 7, 1, 903, "WO", 0, 0, 0ull, 0ull},
|
|
{"CGNPINNAK" , 8, 1, 903, "WO", 0, 0, 0ull, 0ull},
|
|
{"SGOUTNAK" , 9, 1, 903, "WO", 0, 0, 0ull, 0ull},
|
|
{"CGOUTNAK" , 10, 1, 903, "WO", 0, 0, 0ull, 0ull},
|
|
{"PWRONPRGDONE" , 11, 1, 903, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_31" , 12, 20, 903, "RAZ", 1, 1, 0, 0},
|
|
{"MPS" , 0, 11, 904, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NEXTEP" , 11, 4, 904, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBACTEP" , 15, 1, 904, "R/W", 0, 0, 1ull, 0ull},
|
|
{"DPID" , 16, 1, 904, "RO", 0, 0, 0ull, 0ull},
|
|
{"NAKSTS" , 17, 1, 904, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTYPE" , 18, 2, 904, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_20" , 20, 1, 904, "RAZ", 1, 1, 0, 0},
|
|
{"STALL" , 21, 1, 904, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFNUM" , 22, 4, 904, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CNAK" , 26, 1, 904, "WO", 0, 0, 0ull, 0ull},
|
|
{"SNAK" , 27, 1, 904, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD0PID" , 28, 1, 904, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD1PID" , 29, 1, 904, "WO", 0, 0, 0ull, 0ull},
|
|
{"EPDIS" , 30, 1, 904, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPENA" , 31, 1, 904, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XFERCOMPL" , 0, 1, 905, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLD" , 1, 1, 905, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AHBERR" , 2, 1, 905, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"TIMEOUT" , 3, 1, 905, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTKNTXFEMP" , 4, 1, 905, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INTKNEPMIS" , 5, 1, 905, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INEPNAKEFF" , 6, 1, 905, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_31" , 7, 25, 905, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPLMSK" , 0, 1, 906, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLDMSK" , 1, 1, 906, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AHBERRMSK" , 2, 1, 906, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TIMEOUTMSK" , 3, 1, 906, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTKNTXFEMPMSK" , 4, 1, 906, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTKNEPMISMSK" , 5, 1, 906, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INEPNAKEFFMSK" , 6, 1, 906, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_31" , 7, 25, 906, "RAZ", 1, 1, 0, 0},
|
|
{"XFERSIZE" , 0, 19, 907, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKTCNT" , 19, 10, 907, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MC" , 29, 2, 907, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_31" , 31, 1, 907, "RAZ", 1, 1, 0, 0},
|
|
{"MPS" , 0, 11, 908, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_14" , 11, 4, 908, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"USBACTEP" , 15, 1, 908, "R/W", 0, 0, 1ull, 0ull},
|
|
{"DPID" , 16, 1, 908, "RO", 0, 0, 0ull, 0ull},
|
|
{"NAKSTS" , 17, 1, 908, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTYPE" , 18, 2, 908, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SNP" , 20, 1, 908, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STALL" , 21, 1, 908, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_25" , 22, 4, 908, "RAZ", 1, 1, 0, 0},
|
|
{"CNAK" , 26, 1, 908, "WO", 0, 0, 0ull, 0ull},
|
|
{"SNAK" , 27, 1, 908, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD0PID" , 28, 1, 908, "WO", 0, 0, 0ull, 0ull},
|
|
{"SETD1PID" , 29, 1, 908, "WO", 0, 0, 0ull, 0ull},
|
|
{"EPDIS" , 30, 1, 908, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPENA" , 31, 1, 908, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XFERCOMPL" , 0, 1, 909, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLD" , 1, 1, 909, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AHBERR" , 2, 1, 909, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SETUP" , 3, 1, 909, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OUTTKNEPDIS" , 4, 1, 909, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 909, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPLMSK" , 0, 1, 910, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPDISBLDMSK" , 1, 1, 910, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AHBERRMSK" , 2, 1, 910, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SETUPMSK" , 3, 1, 910, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OUTTKNEPDISMSK" , 4, 1, 910, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 910, "RAZ", 1, 1, 0, 0},
|
|
{"XFERSIZE" , 0, 19, 911, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKTCNT" , 19, 10, 911, "R/W", 0, 0, 0ull, 0ull},
|
|
{"MC" , 29, 2, 911, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_31" , 31, 1, 911, "RAZ", 1, 1, 0, 0},
|
|
{"DPTXFSTADDR" , 0, 16, 912, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPTXFSIZE" , 16, 16, 912, "RO", 0, 0, 1896ull, 1896ull},
|
|
{"SUSPSTS" , 0, 1, 913, "RO", 0, 0, 0ull, 0ull},
|
|
{"ENUMSPD" , 1, 2, 913, "RO", 0, 0, 0ull, 0ull},
|
|
{"ERRTICERR" , 3, 1, 913, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_4_7" , 4, 4, 913, "RAZ", 1, 1, 0, 0},
|
|
{"SOFFN" , 8, 14, 913, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_22_31" , 22, 10, 913, "RAZ", 1, 1, 0, 0},
|
|
{"INTKNWPTR" , 0, 5, 914, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_6" , 5, 2, 914, "RAZ", 1, 1, 0, 0},
|
|
{"WRAPBIT" , 7, 1, 914, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 8, 24, 914, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 0, 32, 915, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 0, 32, 916, "RO", 0, 0, 0ull, 0ull},
|
|
{"EPTKN" , 0, 32, 917, "RO", 0, 0, 0ull, 0ull},
|
|
{"GLBLINTRMSK" , 0, 1, 918, "R/W", 0, 0, 0ull, 1ull},
|
|
{"HBSTLEN" , 1, 4, 918, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMAEN" , 5, 1, 918, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_6" , 6, 1, 918, "RAZ", 1, 1, 0, 0},
|
|
{"NPTXFEMPLVL" , 7, 1, 918, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PTXFEMPLVL" , 8, 1, 918, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_9_31" , 9, 23, 918, "RAZ", 1, 1, 0, 0},
|
|
{"EPDIR" , 0, 32, 919, "RO", 0, 0, 0ull, 0ull},
|
|
{"OTGMODE" , 0, 3, 920, "RO", 0, 0, 2ull, 2ull},
|
|
{"OTGARCH" , 3, 2, 920, "RO", 0, 0, 1ull, 1ull},
|
|
{"SINGPNT" , 5, 1, 920, "RO", 0, 0, 0ull, 0ull},
|
|
{"HSPHYTYPE" , 6, 2, 920, "RO", 0, 0, 1ull, 1ull},
|
|
{"FSPHYTYPE" , 8, 2, 920, "RO", 0, 0, 0ull, 0ull},
|
|
{"NUMDEVEPS" , 10, 4, 920, "RO", 0, 0, 4ull, 4ull},
|
|
{"NUMHSTCHNL" , 14, 4, 920, "RO", 0, 0, 7ull, 7ull},
|
|
{"PERIOSUPPORT" , 18, 1, 920, "RO", 0, 0, 1ull, 1ull},
|
|
{"DYNFIFOSIZING" , 19, 1, 920, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_20_21" , 20, 2, 920, "RAZ", 1, 1, 0, 0},
|
|
{"NPTXQDEPTH" , 22, 2, 920, "RO", 0, 0, 2ull, 2ull},
|
|
{"PTXQDEPTH" , 24, 2, 920, "RO", 0, 0, 2ull, 2ull},
|
|
{"TKNQDEPTH" , 26, 5, 920, "RO", 0, 0, 30ull, 30ull},
|
|
{"RESERVED_31_31" , 31, 1, 920, "RAZ", 1, 1, 0, 0},
|
|
{"XFERSIZEWIDTH" , 0, 4, 921, "RO", 0, 0, 8ull, 8ull},
|
|
{"PKTSIZEWIDTH" , 4, 3, 921, "RO", 0, 0, 6ull, 6ull},
|
|
{"OTGEN" , 7, 1, 921, "RO", 0, 0, 1ull, 1ull},
|
|
{"I2C_SELECTION" , 8, 1, 921, "RO", 0, 0, 0ull, 0ull},
|
|
{"VENDOR_CONTROL_INTERFACE_SUPPORT", 9, 1, 921, "RO", 0, 0, 0ull, 0ull},
|
|
{"OPTFEATURE" , 10, 1, 921, "RO", 0, 0, 1ull, 1ull},
|
|
{"RSTTYPE" , 11, 1, 921, "RO", 0, 0, 0ull, 0ull},
|
|
{"AHBPHYSYNC" , 12, 1, 921, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_13_15" , 13, 3, 921, "RAZ", 1, 1, 0, 0},
|
|
{"DFIFODEPTH" , 16, 16, 921, "RO", 0, 0, 1824ull, 1824ull},
|
|
{"NUMDEVPERIOEPS" , 0, 4, 922, "RO", 0, 0, 4ull, 4ull},
|
|
{"ENABLEPWROPT" , 4, 1, 922, "RO", 0, 0, 0ull, 0ull},
|
|
{"AHBFREQ" , 5, 1, 922, "RO", 0, 0, 1ull, 1ull},
|
|
{"RESERVED_6_13" , 6, 8, 922, "RAZ", 1, 1, 0, 0},
|
|
{"PHYDATAWIDTH" , 14, 2, 922, "RO", 0, 0, 1ull, 1ull},
|
|
{"NUMCTLEPS" , 16, 4, 922, "RO", 0, 0, 4ull, 4ull},
|
|
{"IDDGFLTR" , 20, 1, 922, "RO", 0, 0, 1ull, 1ull},
|
|
{"VBUSVALIDFLTR" , 21, 1, 922, "RO", 0, 0, 1ull, 1ull},
|
|
{"AVALIDFLTR" , 22, 1, 922, "RO", 0, 0, 0ull, 0ull},
|
|
{"BVALIDFLTR" , 23, 1, 922, "RO", 0, 0, 0ull, 0ull},
|
|
{"SESSENDFLTR" , 24, 1, 922, "RO", 0, 0, 0ull, 0ull},
|
|
{"ENDEDTRFIFO" , 25, 1, 922, "RO", 0, 0, 0ull, 0ull},
|
|
{"NUMDEVMODINEND" , 26, 4, 922, "RO", 0, 0, 2ull, 2ull},
|
|
{"RESERVED_30_31" , 30, 2, 922, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_0" , 0, 1, 923, "RAZ", 1, 1, 0, 0},
|
|
{"MODEMISMSK" , 1, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OTGINTMSK" , 2, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SOFMSK" , 3, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RXFLVLMSK" , 4, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NPTXFEMPMSK" , 5, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GINNAKEFFMSK" , 6, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GOUTNAKEFFMSK" , 7, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ULPICKINTMSK" , 8, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"I2CINT" , 9, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ERLYSUSPMSK" , 10, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBSUSPMSK" , 11, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBRSTMSK" , 12, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ENUMDONEMSK" , 13, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ISOOUTDROPMSK" , 14, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EOPFMSK" , 15, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 923, "RAZ", 1, 1, 0, 0},
|
|
{"EPMISMSK" , 17, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INEPINTMSK" , 18, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OEPINTMSK" , 19, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INCOMPISOINMSK" , 20, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INCOMPLPMSK" , 21, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FETSUSPMSK" , 22, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 923, "RAZ", 1, 1, 0, 0},
|
|
{"PRTINTMSK" , 24, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HCHINTMSK" , 25, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PTXFEMPMSK" , 26, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 923, "RAZ", 1, 1, 0, 0},
|
|
{"CONIDSTSCHNGMSK" , 28, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DISCONNINTMSK" , 29, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SESSREQINTMSK" , 30, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"WKUPINTMSK" , 31, 1, 923, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CURMOD" , 0, 1, 924, "RO", 0, 0, 0ull, 0ull},
|
|
{"MODEMIS" , 1, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"OTGINT" , 2, 1, 924, "RO", 0, 0, 0ull, 0ull},
|
|
{"SOF" , 3, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RXFLVL" , 4, 1, 924, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPTXFEMP" , 5, 1, 924, "RO", 0, 0, 0ull, 0ull},
|
|
{"GINNAKEFF" , 6, 1, 924, "RO", 0, 0, 0ull, 0ull},
|
|
{"GOUTNAKEFF" , 7, 1, 924, "RO", 0, 0, 0ull, 0ull},
|
|
{"ULPICKINT" , 8, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"I2CINT" , 9, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ERLYSUSP" , 10, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USBSUSP" , 11, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"USBRST" , 12, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ENUMDONE" , 13, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ISOOUTDROP" , 14, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"EOPF" , 15, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 924, "RAZ", 1, 1, 0, 0},
|
|
{"EPMIS" , 17, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"IEPINT" , 18, 1, 924, "RO", 0, 0, 0ull, 0ull},
|
|
{"OEPINT" , 19, 1, 924, "RO", 0, 0, 0ull, 0ull},
|
|
{"INCOMPISOIN" , 20, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"INCOMPLP" , 21, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FETSUSP" , 22, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_23_23" , 23, 1, 924, "RAZ", 1, 1, 0, 0},
|
|
{"PRTINT" , 24, 1, 924, "RO", 0, 0, 0ull, 0ull},
|
|
{"HCHINT" , 25, 1, 924, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTXFEMP" , 26, 1, 924, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_27_27" , 27, 1, 924, "RAZ", 1, 1, 0, 0},
|
|
{"CONIDSTSCHNG" , 28, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DISCONNINT" , 29, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"SESSREQINT" , 30, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"WKUPINT" , 31, 1, 924, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NPTXFSTADDR" , 0, 16, 925, "R/W", 0, 0, 1824ull, 456ull},
|
|
{"NPTXFDEP" , 16, 16, 925, "R/W", 0, 0, 1824ull, 912ull},
|
|
{"NPTXFSPCAVAIL" , 0, 16, 926, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPTXQSPCAVAIL" , 16, 8, 926, "RO", 0, 0, 0ull, 0ull},
|
|
{"NPTXQTOP" , 24, 7, 926, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_31_31" , 31, 1, 926, "RAZ", 1, 1, 0, 0},
|
|
{"SESREQSCS" , 0, 1, 927, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SESREQ" , 1, 1, 927, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_2_7" , 2, 6, 927, "RAZ", 1, 1, 0, 0},
|
|
{"HSTNEGSCS" , 8, 1, 927, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HNPREQ" , 9, 1, 927, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HSTSETHNPEN" , 10, 1, 927, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DEVHNPEN" , 11, 1, 927, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_12_15" , 12, 4, 927, "RAZ", 1, 1, 0, 0},
|
|
{"CONIDSTS" , 16, 1, 927, "RO", 1, 1, 0, 0},
|
|
{"DBNCTIME" , 17, 1, 927, "RO", 0, 0, 0ull, 0ull},
|
|
{"ASESVLD" , 18, 1, 927, "RO", 1, 1, 0, 0},
|
|
{"BSESVLD" , 19, 1, 927, "RO", 1, 1, 0, 0},
|
|
{"RESERVED_20_31" , 20, 12, 927, "RAZ", 1, 1, 0, 0},
|
|
{"RESERVED_0_1" , 0, 2, 928, "RAZ", 1, 1, 0, 0},
|
|
{"SESENDDET" , 2, 1, 928, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_7" , 3, 5, 928, "RAZ", 1, 1, 0, 0},
|
|
{"SESREQSUCSTSCHNG" , 8, 1, 928, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"HSTNEGSUCSTSCHNG" , 9, 1, 928, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_10_16" , 10, 7, 928, "RAZ", 1, 1, 0, 0},
|
|
{"HSTNEGDET" , 17, 1, 928, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ADEVTOUTCHG" , 18, 1, 928, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DBNCEDONE" , 19, 1, 928, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_20_31" , 20, 12, 928, "RAZ", 1, 1, 0, 0},
|
|
{"CSFTRST" , 0, 1, 929, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HSFTRST" , 1, 1, 929, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMCNTRRST" , 2, 1, 929, "R/W", 0, 0, 0ull, 0ull},
|
|
{"INTKNQFLSH" , 3, 1, 929, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RXFFLSH" , 4, 1, 929, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFFLSH" , 5, 1, 929, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFNUM" , 6, 5, 929, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_29" , 11, 19, 929, "RAZ", 1, 1, 0, 0},
|
|
{"DMAREQ" , 30, 1, 929, "RO", 0, 0, 0ull, 0ull},
|
|
{"AHBIDLE" , 31, 1, 929, "RO", 0, 0, 1ull, 1ull},
|
|
{"RXFDEP" , 0, 16, 930, "R/W", 0, 0, 1824ull, 456ull},
|
|
{"RESERVED_16_31" , 16, 16, 930, "RAZ", 1, 1, 0, 0},
|
|
{"EPNUM" , 0, 4, 931, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 931, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 931, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 931, "RO", 0, 0, 0ull, 0ull},
|
|
{"FN" , 21, 4, 931, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_31" , 25, 7, 931, "RAZ", 1, 1, 0, 0},
|
|
{"CHNUM" , 0, 4, 932, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 932, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 932, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 932, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 932, "RAZ", 1, 1, 0, 0},
|
|
{"EPNUM" , 0, 4, 933, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 933, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 933, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 933, "RO", 0, 0, 0ull, 0ull},
|
|
{"FN" , 21, 4, 933, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_25_31" , 25, 7, 933, "RAZ", 1, 1, 0, 0},
|
|
{"CHNUM" , 0, 4, 934, "RO", 0, 0, 0ull, 0ull},
|
|
{"BCNT" , 4, 11, 934, "RO", 0, 0, 0ull, 0ull},
|
|
{"DPID" , 15, 2, 934, "RO", 0, 0, 0ull, 0ull},
|
|
{"PKTSTS" , 17, 4, 934, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_21_31" , 21, 11, 934, "RAZ", 1, 1, 0, 0},
|
|
{"SYNOPSYSID" , 0, 32, 935, "RO", 1, 1, 0, 0},
|
|
{"TOUTCAL" , 0, 3, 936, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHYIF" , 3, 1, 936, "RO", 0, 0, 1ull, 1ull},
|
|
{"ULPI_UTMI_SEL" , 4, 1, 936, "RO", 0, 0, 0ull, 0ull},
|
|
{"FSINTF" , 5, 1, 936, "WO", 0, 0, 0ull, 0ull},
|
|
{"PHYSEL" , 6, 1, 936, "WO", 0, 0, 0ull, 0ull},
|
|
{"DDRSEL" , 7, 1, 936, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SRPCAP" , 8, 1, 936, "RO", 0, 0, 0ull, 0ull},
|
|
{"HNPCAP" , 9, 1, 936, "RO", 0, 0, 0ull, 0ull},
|
|
{"USBTRDTIM" , 10, 4, 936, "R/W", 0, 0, 5ull, 5ull},
|
|
{"RESERVED_14_14" , 14, 1, 936, "RAZ", 1, 1, 0, 0},
|
|
{"PHYLPWRCLKSEL" , 15, 1, 936, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OTGI2CSEL" , 16, 1, 936, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_31" , 17, 15, 936, "RAZ", 1, 1, 0, 0},
|
|
{"HAINT" , 0, 16, 937, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_31" , 16, 16, 937, "RAZ", 1, 1, 0, 0},
|
|
{"HAINTMSK" , 0, 16, 938, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_31" , 16, 16, 938, "RAZ", 1, 1, 0, 0},
|
|
{"MPS" , 0, 11, 939, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPNUM" , 11, 4, 939, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPDIR" , 15, 1, 939, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 939, "RAZ", 1, 1, 0, 0},
|
|
{"LSPDDEV" , 17, 1, 939, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EPTYPE" , 18, 2, 939, "R/W", 0, 0, 0ull, 0ull},
|
|
{"EC" , 20, 2, 939, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DEVADDR" , 22, 7, 939, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ODDFRM" , 29, 1, 939, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHDIS" , 30, 1, 939, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHENA" , 31, 1, 939, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSLSPCLKSEL" , 0, 2, 940, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSLSSUPP" , 2, 1, 940, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_3_31" , 3, 29, 940, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPL" , 0, 1, 941, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"CHHLTD" , 1, 1, 941, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"AHBERR" , 2, 1, 941, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"STALL" , 3, 1, 941, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NAK" , 4, 1, 941, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ACK" , 5, 1, 941, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NYET" , 6, 1, 941, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"XACTERR" , 7, 1, 941, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"BBLERR" , 8, 1, 941, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"FRMOVRUN" , 9, 1, 941, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DATATGLERR" , 10, 1, 941, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_31" , 11, 21, 941, "RAZ", 1, 1, 0, 0},
|
|
{"XFERCOMPLMSK" , 0, 1, 942, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHHLTDMSK" , 1, 1, 942, "R/W", 0, 0, 0ull, 0ull},
|
|
{"AHBERRMSK" , 2, 1, 942, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STALLMSK" , 3, 1, 942, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NAKMSK" , 4, 1, 942, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ACKMSK" , 5, 1, 942, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NYETMSK" , 6, 1, 942, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XACTERRMSK" , 7, 1, 942, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BBLERRMSK" , 8, 1, 942, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRMOVRUNMSK" , 9, 1, 942, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DATATGLERRMSK" , 10, 1, 942, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_11_31" , 11, 21, 942, "RAZ", 1, 1, 0, 0},
|
|
{"PRTADDR" , 0, 7, 943, "R/W", 0, 0, 0ull, 0ull},
|
|
{"HUBADDR" , 7, 7, 943, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XACTPOS" , 14, 2, 943, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COMPSPLT" , 16, 1, 943, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_17_30" , 17, 14, 943, "RAZ", 1, 1, 0, 0},
|
|
{"SPLTENA" , 31, 1, 943, "R/W", 0, 0, 0ull, 0ull},
|
|
{"XFERSIZE" , 0, 19, 944, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PKTCNT" , 19, 10, 944, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PID" , 29, 2, 944, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DOPNG" , 31, 1, 944, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FRINT" , 0, 16, 945, "R/W", 0, 0, 2959ull, 3750ull},
|
|
{"RESERVED_16_31" , 16, 16, 945, "RAZ", 1, 1, 0, 0},
|
|
{"FRNUM" , 0, 16, 946, "RO", 0, 0, 16383ull, 0ull},
|
|
{"FRREM" , 16, 16, 946, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTCONNSTS" , 0, 1, 947, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTCONNDET" , 1, 1, 947, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTENA" , 2, 1, 947, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTENCHNG" , 3, 1, 947, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTOVRCURRACT" , 4, 1, 947, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTOVRCURRCHNG" , 5, 1, 947, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PRTRES" , 6, 1, 947, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTSUSP" , 7, 1, 947, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTRST" , 8, 1, 947, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_9_9" , 9, 1, 947, "RAZ", 1, 1, 0, 0},
|
|
{"PRTLNSTS" , 10, 2, 947, "RO", 0, 0, 0ull, 0ull},
|
|
{"PRTPWR" , 12, 1, 947, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTTSTCTL" , 13, 4, 947, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PRTSPD" , 17, 2, 947, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_31" , 19, 13, 947, "RAZ", 1, 1, 0, 0},
|
|
{"PTXFSTADDR" , 0, 16, 948, "R/W", 0, 0, 3648ull, 912ull},
|
|
{"PTXFSIZE" , 16, 16, 948, "R/W", 0, 0, 256ull, 456ull},
|
|
{"PTXFSPCAVAIL" , 0, 16, 949, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTXQSPCAVAIL" , 16, 8, 949, "RO", 0, 0, 0ull, 0ull},
|
|
{"PTXQTOP" , 24, 8, 949, "RO", 0, 0, 0ull, 0ull},
|
|
{"DATA" , 0, 32, 950, "R/W", 0, 0, 0ull, 0ull},
|
|
{"STOPPCLK" , 0, 1, 951, "R/W", 0, 0, 0ull, 0ull},
|
|
{"GATEHCLK" , 1, 1, 951, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PWRCLMP" , 2, 1, 951, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RSTPDWNMODULE" , 3, 1, 951, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PHYSUSPENDED" , 4, 1, 951, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_5_31" , 5, 27, 951, "RAZ", 1, 1, 0, 0},
|
|
{"NOF_BIS" , 0, 1, 952, "RO", 0, 0, 0ull, 0ull},
|
|
{"NIF_BIS" , 1, 1, 952, "RO", 0, 0, 0ull, 0ull},
|
|
{"USBC_BIS" , 2, 1, 952, "RO", 0, 0, 0ull, 0ull},
|
|
{"N2UF_BIS" , 3, 1, 952, "RO", 0, 0, 0ull, 0ull},
|
|
{"E2HC_BIS" , 4, 1, 952, "RO", 0, 0, 0ull, 0ull},
|
|
{"U2NF_BIS" , 5, 1, 952, "RO", 0, 0, 0ull, 0ull},
|
|
{"U2NC_BIS" , 6, 1, 952, "RO", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_7_63" , 7, 57, 952, "RAZ", 1, 1, 0, 0},
|
|
{"DIVIDE" , 0, 3, 953, "R/W", 0, 0, 4ull, 0ull},
|
|
{"HRST" , 3, 1, 953, "R/W", 0, 0, 0ull, 1ull},
|
|
{"PRST" , 4, 1, 953, "R/W", 0, 0, 0ull, 1ull},
|
|
{"ENABLE" , 5, 1, 953, "R/W", 0, 0, 1ull, 1ull},
|
|
{"POR" , 6, 1, 953, "R/W", 0, 0, 1ull, 0ull},
|
|
{"S_BIST" , 7, 1, 953, "R/W", 0, 0, 0ull, 1ull},
|
|
{"SD_MODE" , 8, 2, 953, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CDIV_BYP" , 10, 1, 953, "R/W", 0, 0, 0ull, 0ull},
|
|
{"P_C_SEL" , 11, 2, 953, "R/W", 0, 0, 2ull, 0ull},
|
|
{"P_COM_ON" , 13, 1, 953, "R/W", 0, 0, 1ull, 1ull},
|
|
{"P_RTYPE" , 14, 2, 953, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_16_16" , 16, 1, 953, "RAZ", 1, 1, 0, 0},
|
|
{"HCLK_RST" , 17, 1, 953, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DIVIDE2" , 18, 2, 953, "R/W", 0, 0, 0ull, 1ull},
|
|
{"RESERVED_20_63" , 20, 44, 953, "RAZ", 1, 1, 0, 0},
|
|
{"L2C_EMOD" , 0, 2, 954, "R/W", 0, 0, 1ull, 1ull},
|
|
{"INV_A2" , 2, 1, 954, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_TEST" , 3, 1, 954, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_STT" , 4, 1, 954, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_0PAG" , 5, 1, 954, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_6_63" , 6, 58, 954, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 955, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 955, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 956, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 956, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 957, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 957, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 958, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 958, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 959, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 959, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 960, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 960, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 961, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 961, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 962, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 962, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 963, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 963, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 964, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 964, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 965, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 965, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 966, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 966, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 967, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 967, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 968, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 968, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 969, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 969, "RAZ", 1, 1, 0, 0},
|
|
{"ADDR" , 0, 36, 970, "R/W", 0, 1, 0ull, 0},
|
|
{"RESERVED_36_63" , 36, 28, 970, "RAZ", 1, 1, 0, 0},
|
|
{"BURST" , 0, 4, 971, "R/W", 0, 0, 0ull, 0ull},
|
|
{"CHANNEL" , 4, 5, 971, "R/W", 0, 0, 0ull, 0ull},
|
|
{"COUNT" , 9, 11, 971, "R/W", 0, 0, 0ull, 0ull},
|
|
{"F_ADDR" , 20, 18, 971, "R/W", 0, 0, 0ull, 0ull},
|
|
{"REQ" , 38, 1, 971, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DONE" , 39, 1, 971, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_40_63" , 40, 24, 971, "RAZ", 1, 1, 0, 0},
|
|
{"PR_PO_E" , 0, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PR_PU_F" , 1, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NR_PO_E" , 2, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NR_PU_F" , 3, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LR_PO_E" , 4, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LR_PU_F" , 5, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PT_PO_E" , 6, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PT_PU_F" , 7, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NT_PO_E" , 8, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"NT_PU_F" , 9, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LT_PO_E" , 10, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LT_PU_F" , 11, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DCRED_E" , 12, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DCRED_F" , 13, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2C_S_E" , 14, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2C_A_F" , 15, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2_FI_E" , 16, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"L2_FI_F" , 17, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_E" , 18, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_F" , 19, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_F" , 20, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_E" , 21, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_F" , 22, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_E" , 23, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UOD_PE" , 24, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"UOD_PF" , 25, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_26_31" , 26, 6, 972, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"LTL_F_PE" , 32, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LTL_F_PF" , 33, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_RPE" , 34, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_RPF" , 35, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_DPE" , 36, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"ND4O_DPF" , 37, 1, 972, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 972, "RAZ", 1, 1, 0, 0},
|
|
{"PR_PO_E" , 0, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PR_PU_F" , 1, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NR_PO_E" , 2, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NR_PU_F" , 3, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LR_PO_E" , 4, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LR_PU_F" , 5, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PT_PO_E" , 6, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"PT_PU_F" , 7, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NT_PO_E" , 8, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"NT_PU_F" , 9, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LT_PO_E" , 10, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LT_PU_F" , 11, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCRED_E" , 12, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"DCRED_F" , 13, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"L2C_S_E" , 14, 1, 973, "R/W1C", 1, 0, 0, 0ull},
|
|
{"L2C_A_F" , 15, 1, 973, "R/W1C", 1, 0, 0, 0ull},
|
|
{"LT_FI_E" , 16, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LT_FI_F" , 17, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_E" , 18, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RG_FI_F" , 19, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_F" , 20, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q2_E" , 21, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_F" , 22, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"RQ_Q3_E" , 23, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"UOD_PE" , 24, 1, 973, "R/W1C", 1, 0, 0, 0ull},
|
|
{"UOD_PF" , 25, 1, 973, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_26_31" , 26, 6, 973, "RAZ", 1, 0, 0, 0ull},
|
|
{"LTL_F_PE" , 32, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"LTL_F_PF" , 33, 1, 973, "R/W1C", 0, 0, 0ull, 0ull},
|
|
{"ND4O_RPE" , 34, 1, 973, "R/W1C", 1, 0, 0, 0ull},
|
|
{"ND4O_RPF" , 35, 1, 973, "R/W1C", 1, 0, 0, 0ull},
|
|
{"ND4O_DPE" , 36, 1, 973, "R/W1C", 1, 0, 0, 0ull},
|
|
{"ND4O_DPF" , 37, 1, 973, "R/W1C", 1, 0, 0, 0ull},
|
|
{"RESERVED_38_63" , 38, 26, 973, "RAZ", 1, 1, 0, 0},
|
|
{"ATE_RESET" , 0, 1, 974, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TDATA_IN" , 1, 8, 974, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TADDR_IN" , 9, 4, 974, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TDATA_SEL" , 13, 1, 974, "R/W", 0, 0, 0ull, 0ull},
|
|
{"BIST_ENB" , 14, 1, 974, "R/W", 0, 0, 0ull, 0ull},
|
|
{"VTEST_ENB" , 15, 1, 974, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LOOP_ENB" , 16, 1, 974, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TX_BS_EN" , 17, 1, 974, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TX_BS_ENH" , 18, 1, 974, "R/W", 0, 0, 0ull, 0ull},
|
|
{"RESERVED_19_22" , 19, 4, 974, "RAZ", 0, 0, 0ull, 0ull},
|
|
{"HST_MODE" , 23, 1, 974, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DM_PULLD" , 24, 1, 974, "R/W", 0, 0, 1ull, 1ull},
|
|
{"DP_PULLD" , 25, 1, 974, "R/W", 0, 0, 1ull, 1ull},
|
|
{"TCLK" , 26, 1, 974, "R/W", 0, 0, 0ull, 0ull},
|
|
{"USBP_BIST" , 27, 1, 974, "R/W", 0, 0, 1ull, 1ull},
|
|
{"USBC_END" , 28, 1, 974, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DMA_BMODE" , 29, 1, 974, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXPREEMPHASISTUNE" , 30, 1, 974, "R/W", 0, 0, 0ull, 0ull},
|
|
{"SIDDQ" , 31, 1, 974, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TDATA_OUT" , 32, 4, 974, "RO", 1, 1, 0, 0},
|
|
{"BIST_ERR" , 36, 1, 974, "RO", 0, 0, 0ull, 0ull},
|
|
{"BIST_DONE" , 37, 1, 974, "RO", 0, 0, 0ull, 0ull},
|
|
{"HSBIST" , 38, 1, 974, "R/W", 0, 0, 0ull, 0ull},
|
|
{"FSBIST" , 39, 1, 974, "R/W", 0, 0, 0ull, 0ull},
|
|
{"LSBIST" , 40, 1, 974, "R/W", 0, 0, 0ull, 0ull},
|
|
{"DRVVBUS" , 41, 1, 974, "R/W", 0, 0, 0ull, 0ull},
|
|
{"PORTRESET" , 42, 1, 974, "R/W", 0, 0, 0ull, 0ull},
|
|
{"OTGDISABLE" , 43, 1, 974, "R/W", 0, 0, 1ull, 1ull},
|
|
{"OTGTUNE" , 44, 3, 974, "R/W", 0, 0, 2ull, 2ull},
|
|
{"COMPDISTUNE" , 47, 3, 974, "R/W", 0, 0, 2ull, 2ull},
|
|
{"SQRXTUNE" , 50, 3, 974, "R/W", 0, 0, 3ull, 3ull},
|
|
{"TXHSXVTUNE" , 53, 2, 974, "R/W", 0, 0, 0ull, 0ull},
|
|
{"TXFSLSTUNE" , 55, 4, 974, "R/W", 0, 0, 3ull, 3ull},
|
|
{"TXVREFTUNE" , 59, 4, 974, "R/W", 0, 0, 7ull, 7ull},
|
|
{"TXRISETUNE" , 63, 1, 974, "R/W", 0, 0, 0ull, 0ull},
|
|
{NULL,0,0,0,0,0,0,0,0}
|
|
};
|
|
|
|
|
|
const CVMX_CSR_DB_TYPE *cvmx_csr_db[] = {
|
|
cvmx_csr_db_cn38xxp2,
|
|
cvmx_csr_db_cn31xx,
|
|
cvmx_csr_db_cn30xx,
|
|
cvmx_csr_db_cn38xx,
|
|
cvmx_csr_db_cn58xxp1,
|
|
cvmx_csr_db_cn58xx,
|
|
cvmx_csr_db_cn56xxp1,
|
|
cvmx_csr_db_cn56xx,
|
|
cvmx_csr_db_cn50xx,
|
|
cvmx_csr_db_cn52xxp1,
|
|
cvmx_csr_db_cn52xx,
|
|
NULL
|
|
};
|
|
const CVMX_CSR_DB_ADDRESS_TYPE *cvmx_csr_db_addresses[] = {
|
|
cvmx_csr_db_addresses_cn38xxp2,
|
|
cvmx_csr_db_addresses_cn31xx,
|
|
cvmx_csr_db_addresses_cn30xx,
|
|
cvmx_csr_db_addresses_cn38xx,
|
|
cvmx_csr_db_addresses_cn58xxp1,
|
|
cvmx_csr_db_addresses_cn58xx,
|
|
cvmx_csr_db_addresses_cn56xxp1,
|
|
cvmx_csr_db_addresses_cn56xx,
|
|
cvmx_csr_db_addresses_cn50xx,
|
|
cvmx_csr_db_addresses_cn52xxp1,
|
|
cvmx_csr_db_addresses_cn52xx,
|
|
NULL
|
|
};
|
|
const CVMX_CSR_DB_FIELD_TYPE *cvmx_csr_db_fields[] = {
|
|
cvmx_csr_db_fields_cn38xxp2,
|
|
cvmx_csr_db_fields_cn31xx,
|
|
cvmx_csr_db_fields_cn30xx,
|
|
cvmx_csr_db_fields_cn38xx,
|
|
cvmx_csr_db_fields_cn58xxp1,
|
|
cvmx_csr_db_fields_cn58xx,
|
|
cvmx_csr_db_fields_cn56xxp1,
|
|
cvmx_csr_db_fields_cn56xx,
|
|
cvmx_csr_db_fields_cn50xx,
|
|
cvmx_csr_db_fields_cn52xxp1,
|
|
cvmx_csr_db_fields_cn52xx,
|
|
NULL
|
|
};
|