7e1f6dfe9d
- The MD functions critical_enter/exit are renamed to start with a cpu_ prefix. - MI wrapper functions critical_enter/exit maintain a per-thread nesting count and a per-thread critical section saved state set when entering a critical section while at nesting level 0 and restored when exiting to nesting level 0. This moves the saved state out of spin mutexes so that interlocking spin mutexes works properly. - Most low-level MD code that used critical_enter/exit now use cpu_critical_enter/exit. MI code such as device drivers and spin mutexes use the MI wrappers. Note that since the MI wrappers store the state in the current thread, they do not have any return values or arguments. - mtx_intr_enable() is replaced with a constant CRITICAL_FORK which is assigned to curthread->td_savecrit during fork_exit(). Tested on: i386, alpha
306 lines
6.0 KiB
C
306 lines
6.0 KiB
C
/*-
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* Copyright (c) 1998 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_CPUFUNC_H_
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#define _MACHINE_CPUFUNC_H_
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#ifdef _KERNEL
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#include <sys/types.h>
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#include <machine/ia64_cpu.h>
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#define CRITICAL_FORK (ia64_get_psr() |= IA64_PSR_I)
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#ifdef __GNUC__
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static __inline void
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breakpoint(void)
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{
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__asm __volatile("break 0x80100"); /* XXX use linux value */
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}
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#endif
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extern u_int64_t ia64_port_base;
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static __inline volatile void *
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ia64_port_address(u_int port)
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{
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return (volatile void *)(ia64_port_base
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| ((port >> 2) << 12)
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| (port & ((1 << 12) - 1)));
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}
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static __inline volatile void *
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ia64_memory_address(u_int64_t addr)
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{
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return (volatile void *) IA64_PHYS_TO_RR6(addr);
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}
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static __inline u_int8_t
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inb(u_int port)
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{
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volatile u_int8_t *p = ia64_port_address(port);
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u_int8_t v = *p;
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ia64_mf_a();
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ia64_mf();
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return v;
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}
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static __inline u_int16_t
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inw(u_int port)
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{
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volatile u_int16_t *p = ia64_port_address(port);
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u_int16_t v = *p;
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ia64_mf_a();
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ia64_mf();
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return v;
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}
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static __inline u_int32_t
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inl(u_int port)
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{
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volatile u_int32_t *p = ia64_port_address(port);
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u_int32_t v = *p;
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ia64_mf_a();
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ia64_mf();
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return v;
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}
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static __inline void
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insb(u_int port, void *addr, size_t count)
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{
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u_int8_t *p = addr;
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while (count--)
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*p++ = inb(port);
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}
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static __inline void
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insw(u_int port, void *addr, size_t count)
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{
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u_int16_t *p = addr;
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while (count--)
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*p++ = inw(port);
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}
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static __inline void
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insl(u_int port, void *addr, size_t count)
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{
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u_int32_t *p = addr;
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while (count--)
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*p++ = inl(port);
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}
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static __inline void
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outb(u_int port, u_int8_t data)
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{
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volatile u_int8_t *p = ia64_port_address(port);
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*p = data;
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ia64_mf_a();
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ia64_mf();
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}
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static __inline void
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outw(u_int port, u_int16_t data)
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{
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volatile u_int16_t *p = ia64_port_address(port);
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*p = data;
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ia64_mf_a();
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ia64_mf();
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}
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static __inline void
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outl(u_int port, u_int32_t data)
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{
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volatile u_int32_t *p = ia64_port_address(port);
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*p = data;
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ia64_mf_a();
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ia64_mf();
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}
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static __inline void
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outsb(u_int port, const void *addr, size_t count)
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{
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const u_int8_t *p = addr;
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while (count--)
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outb(port, *p++);
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}
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static __inline void
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outsw(u_int port, const void *addr, size_t count)
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{
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const u_int16_t *p = addr;
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while (count--)
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outw(port, *p++);
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}
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static __inline void
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outsl(u_int port, const void *addr, size_t count)
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{
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const u_int32_t *p = addr;
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while (count--)
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outl(port, *p++);
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}
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static __inline u_int8_t
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readb(u_int addr)
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{
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volatile u_int8_t *p = ia64_memory_address(addr);
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u_int8_t v = *p;
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ia64_mf_a();
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ia64_mf();
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return v;
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}
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static __inline u_int16_t
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readw(u_int addr)
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{
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volatile u_int16_t *p = ia64_memory_address(addr);
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u_int16_t v = *p;
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ia64_mf_a();
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ia64_mf();
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return v;
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}
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static __inline u_int32_t
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readl(u_int addr)
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{
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volatile u_int32_t *p = ia64_memory_address(addr);
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u_int32_t v = *p;
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ia64_mf_a();
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ia64_mf();
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return v;
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}
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static __inline void
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writeb(u_int addr, u_int8_t data)
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{
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volatile u_int8_t *p = ia64_memory_address(addr);
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*p = data;
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ia64_mf_a();
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ia64_mf();
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}
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static __inline void
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writew(u_int addr, u_int16_t data)
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{
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volatile u_int16_t *p = ia64_memory_address(addr);
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*p = data;
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ia64_mf_a();
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ia64_mf();
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}
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static __inline void
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writel(u_int addr, u_int32_t data)
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{
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volatile u_int32_t *p = ia64_memory_address(addr);
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*p = data;
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ia64_mf_a();
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ia64_mf();
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}
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static __inline void
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memcpy_fromio(u_int8_t *addr, size_t ofs, size_t count)
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{
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volatile u_int8_t *p = ia64_memory_address(ofs);
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while (count--)
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*addr++ = *p++;
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}
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static __inline void
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memcpy_io(size_t dst, size_t src, size_t count)
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{
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volatile u_int8_t *dp = ia64_memory_address(dst);
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volatile u_int8_t *sp = ia64_memory_address(src);
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while (count--)
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*dp++ = *sp++;
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}
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static __inline void
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memcpy_toio(size_t ofs, u_int8_t *addr, size_t count)
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{
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volatile u_int8_t *p = ia64_memory_address(ofs);
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while (count--)
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*p++ = *addr++;
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}
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static __inline void
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memset_io(size_t ofs, u_int8_t value, size_t count)
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{
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volatile u_int8_t *p = ia64_memory_address(ofs);
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while (count--)
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*p++ = value;
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}
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static __inline void
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memsetw(u_int16_t *addr, int val, size_t size)
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{
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while (size--)
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*addr++ = val;
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}
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static __inline void
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memsetw_io(size_t ofs, u_int16_t value, size_t count)
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{
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volatile u_int16_t *p = ia64_memory_address(ofs);
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while (count--)
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*p++ = value;
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}
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static __inline void
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disable_intr(void)
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{
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__asm __volatile ("rsm psr.i;;");
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}
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static __inline void
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enable_intr(void)
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{
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__asm __volatile (";; ssm psr.i;; srlz.d");
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}
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static __inline critical_t
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cpu_critical_enter(void)
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{
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critical_t psr;
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__asm __volatile ("mov %0=psr;;" : "=r" (psr));
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disable_intr();
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return (psr);
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}
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static __inline void
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cpu_critical_exit(critical_t psr)
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{
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__asm __volatile ("mov psr.l=%0;; srlz.d" :: "r" (psr));
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}
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#endif /* _KERNEL */
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#endif /* !_MACHINE_CPUFUNC_H_ */
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