153 lines
3.5 KiB
ArmAsm
153 lines
3.5 KiB
ArmAsm
/*-
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* Copyright (c) 2001 Jake Burkholder.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <machine/asm.h>
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__FBSDID("$FreeBSD$");
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#include <machine/asi.h>
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#include <machine/asmacros.h>
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#include <machine/pstate.h>
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#include <machine/upa.h>
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#include "assym.s"
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.register %g2,#ignore
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.globl kernbase
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.set kernbase,KERNBASE
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/*
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* void _start(caddr_t metadata, u_long o1, u_long o2, u_long o3,
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* u_long ofw_vec)
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*/
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ENTRY(btext)
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ENTRY(_start)
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/*
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* Initialize misc state to known values. Interrupts disabled, normal
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* globals, windows flushed (cr = 0, cs = nwindows - 1), no clean
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* windows, pil 0, and floating point disabled.
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*/
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wrpr %g0, PSTATE_NORMAL, %pstate
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flushw
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wrpr %g0, 0, %cleanwin
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wrpr %g0, 0, %pil
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wr %g0, 0, %fprs
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wrpr %g0, 0, %tick
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/*
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* Get onto our per-cpu panic stack, which precedes the struct pcpu in
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* the per-cpu page.
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*/
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SET(pcpu0 + (PCPU_PAGES * PAGE_SIZE) - PC_SIZEOF, %l1, %l0)
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sub %l0, SPOFF + CCFSZ, %sp
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/*
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* Enable interrupts.
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*/
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wrpr %g0, PSTATE_KERNEL, %pstate
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/*
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* Do initial bootstrap to setup pmap and thread0.
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*/
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call sparc64_init
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nop
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/*
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* Get onto thread0's kstack.
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*/
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sub PCB_REG, SPOFF + CCFSZ, %sp
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/*
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* And away we go. This doesn't return.
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*/
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call mi_startup
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nop
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sir
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! NOTREACHED
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END(_start)
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/*
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* void cpu_setregs(struct pcpu *pc)
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*/
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ENTRY(cpu_setregs)
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ldx [%o0 + PC_CURPCB], %o1
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/*
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* Disable interrupts, normal globals.
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*/
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wrpr %g0, PSTATE_NORMAL, %pstate
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/*
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* Normal %g6 points to the current thread's pcb, and %g7 points to
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* the per-cpu data structure.
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*/
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mov %o1, PCB_REG
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mov %o0, PCPU_REG
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/*
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* Alternate globals.
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*/
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wrpr %g0, PSTATE_ALT, %pstate
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/*
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* Alternate %g5 points to a per-cpu panic stack, %g6 points to the
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* current thread's pcb, and %g7 points to the per-cpu data structure.
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*/
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mov %o0, ASP_REG
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mov %o1, PCB_REG
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mov %o0, PCPU_REG
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/*
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* Interrupt globals.
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*/
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wrpr %g0, PSTATE_INTR, %pstate
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/*
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* Interrupt %g7 points to the per-cpu data structure.
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*/
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mov %o0, PCPU_REG
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/*
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* Normal globals again.
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*/
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wrpr %g0, PSTATE_NORMAL, %pstate
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/*
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* Force trap level 1 and take over the trap table.
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*/
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SET(tl0_base, %o2, %o1)
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wrpr %g0, 1, %tl
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wrpr %o1, 0, %tba
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/*
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* Re-enable interrupts.
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*/
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wrpr %g0, PSTATE_KERNEL, %pstate
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retl
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nop
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END(cpu_setregs)
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