7faf44ba96
a tendency to grow unwieldy so we may want to revisit this in due
time.
o Simplify the CPU reset function by writing to the reset control
register irrespective of whether the CPU has one and automatically
falling back to the debug control register if we didn't reset the
CPU. The side-effect is that we now properly reset future processors
without first having to add the system version to the list.
308 lines
7.4 KiB
C
308 lines
7.4 KiB
C
/*-
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* Copyright (c) 2008-2009 Semihalf, Rafal Jaworowski
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <sys/pcpu.h>
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#include <sys/proc.h>
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#include <sys/smp.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/hid.h>
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#include <machine/platform.h>
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#include <machine/platformvar.h>
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#include <machine/smp.h>
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#include <machine/spr.h>
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#include <machine/vmparam.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/openfirm.h>
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#include <powerpc/mpc85xx/mpc85xx.h>
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#include "platform_if.h"
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#ifdef SMP
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extern void *ap_pcpu;
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extern uint8_t __boot_page[]; /* Boot page body */
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extern uint32_t kernload; /* Kernel physical load address */
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#endif
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extern uint32_t *bootinfo;
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static int cpu, maxcpu;
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static int bare_probe(platform_t);
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static void bare_mem_regions(platform_t, struct mem_region **phys, int *physsz,
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struct mem_region **avail, int *availsz);
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static u_long bare_timebase_freq(platform_t, struct cpuref *cpuref);
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static int bare_smp_first_cpu(platform_t, struct cpuref *cpuref);
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static int bare_smp_next_cpu(platform_t, struct cpuref *cpuref);
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static int bare_smp_get_bsp(platform_t, struct cpuref *cpuref);
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static int bare_smp_start_cpu(platform_t, struct pcpu *cpu);
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static void e500_reset(platform_t);
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static platform_method_t bare_methods[] = {
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PLATFORMMETHOD(platform_probe, bare_probe),
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PLATFORMMETHOD(platform_mem_regions, bare_mem_regions),
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PLATFORMMETHOD(platform_timebase_freq, bare_timebase_freq),
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PLATFORMMETHOD(platform_smp_first_cpu, bare_smp_first_cpu),
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PLATFORMMETHOD(platform_smp_next_cpu, bare_smp_next_cpu),
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PLATFORMMETHOD(platform_smp_get_bsp, bare_smp_get_bsp),
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PLATFORMMETHOD(platform_smp_start_cpu, bare_smp_start_cpu),
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PLATFORMMETHOD(platform_reset, e500_reset),
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{ 0, 0 }
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};
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static platform_def_t bare_platform = {
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"bare metal",
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bare_methods,
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0
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};
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PLATFORM_DEF(bare_platform);
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static int
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bare_probe(platform_t plat)
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{
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uint32_t ver, sr;
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int i, law_max, tgt;
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ver = SVR_VER(mfspr(SPR_SVR));
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if (ver == SVR_MPC8572E || ver == SVR_MPC8572 ||
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ver == SVR_P1020E || ver == SVR_P1020 ||
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ver == SVR_P2020E || ver == SVR_P2020)
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maxcpu = 2;
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else
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maxcpu = 1;
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/*
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* Clear local access windows. Skip DRAM entries, so we don't shoot
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* ourselves in the foot.
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*/
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law_max = law_getmax();
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for (i = 0; i < law_max; i++) {
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sr = ccsr_read4(OCP85XX_LAWSR(i));
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if ((sr & 0x80000000) == 0)
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continue;
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tgt = (sr & 0x01f00000) >> 20;
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if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 ||
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tgt == OCP85XX_TGTIF_RAM_INTL)
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continue;
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ccsr_write4(OCP85XX_LAWSR(i), sr & 0x7fffffff);
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}
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return (BUS_PROBE_GENERIC);
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}
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#define MEM_REGIONS 8
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static struct mem_region avail_regions[MEM_REGIONS];
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void
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bare_mem_regions(platform_t plat, struct mem_region **phys, int *physsz,
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struct mem_region **avail, int *availsz)
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{
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uint32_t memsize;
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int i, rv;
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rv = fdt_get_mem_regions(avail_regions, availsz, &memsize);
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if (rv != 0)
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return;
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for (i = 0; i < *availsz; i++) {
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if (avail_regions[i].mr_start < 1048576) {
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avail_regions[i].mr_size =
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avail_regions[i].mr_size -
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(1048576 - avail_regions[i].mr_start);
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avail_regions[i].mr_start = 1048576;
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}
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}
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*avail = avail_regions;
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/* On the bare metal platform phys == avail memory */
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*physsz = *availsz;
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*phys = *avail;
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}
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static u_long
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bare_timebase_freq(platform_t plat, struct cpuref *cpuref)
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{
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u_long ticks;
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phandle_t cpus, child;
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pcell_t freq;
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if (bootinfo != NULL) {
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/* Backward compatibility. See 8-STABLE. */
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ticks = bootinfo[3] >> 3;
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} else
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ticks = 0;
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if ((cpus = OF_finddevice("/cpus")) == 0)
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goto out;
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if ((child = OF_child(cpus)) == 0)
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goto out;
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freq = 0;
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if (OF_getprop(child, "bus-frequency", (void *)&freq,
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sizeof(freq)) <= 0)
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goto out;
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/*
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* Time Base and Decrementer are updated every 8 CCB bus clocks.
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* HID0[SEL_TBCLK] = 0
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*/
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if (freq != 0)
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ticks = freq / 8;
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out:
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if (ticks <= 0)
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panic("Unable to determine timebase frequency!");
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return (ticks);
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}
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static int
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bare_smp_first_cpu(platform_t plat, struct cpuref *cpuref)
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{
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cpu = 0;
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cpuref->cr_cpuid = cpu;
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cpuref->cr_hwref = cpuref->cr_cpuid;
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if (bootverbose)
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printf("powerpc_smp_first_cpu: cpuid %d\n", cpuref->cr_cpuid);
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cpu++;
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return (0);
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}
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static int
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bare_smp_next_cpu(platform_t plat, struct cpuref *cpuref)
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{
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if (cpu >= maxcpu)
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return (ENOENT);
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cpuref->cr_cpuid = cpu++;
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cpuref->cr_hwref = cpuref->cr_cpuid;
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if (bootverbose)
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printf("powerpc_smp_next_cpu: cpuid %d\n", cpuref->cr_cpuid);
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return (0);
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}
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static int
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bare_smp_get_bsp(platform_t plat, struct cpuref *cpuref)
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{
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cpuref->cr_cpuid = mfspr(SPR_PIR);
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cpuref->cr_hwref = cpuref->cr_cpuid;
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return (0);
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}
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static int
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bare_smp_start_cpu(platform_t plat, struct pcpu *pc)
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{
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#ifdef SMP
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uint32_t bptr, eebpcr;
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int timeout;
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eebpcr = ccsr_read4(OCP85XX_EEBPCR);
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if ((eebpcr & (pc->pc_cpumask << 24)) != 0) {
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printf("%s: CPU=%d already out of hold-off state!\n",
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__func__, pc->pc_cpuid);
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return (ENXIO);
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}
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ap_pcpu = pc;
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__asm __volatile("msync; isync");
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/*
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* Set BPTR to the physical address of the boot page
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*/
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bptr = ((uint32_t)__boot_page - KERNBASE) + kernload;
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ccsr_write4(OCP85XX_BPTR, (bptr >> 12) | 0x80000000);
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/*
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* Release AP from hold-off state
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*/
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eebpcr |= (pc->pc_cpumask << 24);
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ccsr_write4(OCP85XX_EEBPCR, eebpcr);
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__asm __volatile("isync; msync");
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timeout = 500;
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while (!pc->pc_awake && timeout--)
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DELAY(1000); /* wait 1ms */
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return ((pc->pc_awake) ? 0 : EBUSY);
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#else
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/* No SMP support */
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return (ENXIO);
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#endif
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}
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static void
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e500_reset(platform_t plat)
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{
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/*
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* Try the dedicated reset register first.
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* If the SoC doesn't have one, we'll fall
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* back to using the debug control register.
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*/
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ccsr_write4(OCP85XX_RSTCR, 2);
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/* Clear DBCR0, disables debug interrupts and events. */
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mtspr(SPR_DBCR0, 0);
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__asm __volatile("isync");
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/* Enable Debug Interrupts in MSR. */
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mtmsr(mfmsr() | PSL_DE);
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/* Enable debug interrupts and issue reset. */
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mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM);
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printf("Reset failed...\n");
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while (1);
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}
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