4527ee3e06
particular interest in (and support for) SRI International and the University of Cambridge's BERI FPGA soft-core processor. This includes micro device drivers for the Altera JTAG UART console, memory-mapped flash, and the Altera SD Card IP core in both boot2 and loader. boot2 can be written to the on-board Intel StrataFlash on the DE4 board, and loader can be placed in StrataFlash or the SD Card. Plenty of XXX comments, but works quite well locally in practice and I am using it daily. Although I had originally ported the ARM version of boot2, the current version is x86-derived as that proved more feature-complete. As we don't currently use partitions on our flash disks, support for that has been commented out relative to x86, but would be easy to add back. FDT support has not yet been hooked up, although some skeleton parts have been put in place for that. This may well be a useful starting point for ports to other 32-bit and 64-bit MIPS-ISA systems. This merge is synchronised to CheriBSD github commit e41d74fd719525d4dd7a7ee499114679165eeaf6, but with some additions of $FreeBSD. MFC after: 3 weeks Sponsored by: DARPA, AFRAL
50 lines
1.8 KiB
ArmAsm
50 lines
1.8 KiB
ArmAsm
/*-
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* Copyright (c) 2013 Robert N. M. Watson
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <machine/asm.h>
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__FBSDID("$FreeBSD$");
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.set mips64
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.set noreorder
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.set nobopt
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.set noat
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ASM_ENTRY(__start)
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VECTOR(_loader_start, unknown)
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/* Not much here yet. */
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jal main
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nop
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/* If main() returns, spin. */
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loop:
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b loop
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nop
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VECTOR_END(_loader_start)
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