04b6fa8330
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
272 lines
7.3 KiB
ArmAsm
272 lines
7.3 KiB
ArmAsm
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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#undef __ASSEMBLY__
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#define __ASSEMBLY__
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#ifdef __linux__
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#else
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#include <machine/asm.h>
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#include <machine/regdef.h>
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#endif
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#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
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#include <asm/octeon/cvmx-asm.h>
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#include <asm/octeon/octeon-boot-info.h>
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#else
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#include "executive-config.h"
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#include "cvmx-asm.h"
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#ifndef __OCTEON_NEWLIB__
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#include "../../bootloader/u-boot/include/octeon_mem_map.h"
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#else
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#include "octeon-boot-info.h"
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#endif
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#endif
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/* The registers saving/restoring is split into two because k0 is stored in the COP0_DESAVE register. */
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#define REGS0 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25
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#define REGS1 27,28,29,30,31
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#define SAVE_REGISTER(reg) \
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sd reg, 0(k0); \
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addi k0, 8
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#define RESTORE_REGISTER(reg) \
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ld reg, -8(k0); \
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addi k0, -8
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#define SAVE_COP0(reg) \
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dmfc0 k1,reg; \
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sd k1, 0(k0); \
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addi k0, 8
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#define RESTORE_COP0(reg) \
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ld k1, -8(k0); \
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addi k0, -8; \
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dmtc0 k1,reg
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#define SAVE_ADDRESS(addr) \
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dli k1, addr; \
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ld k1, 0(k1); \
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sd k1, 0(k0); \
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addi k0, 8
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#define RESTORE_ADDRESS(addr) \
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dli t0, addr; \
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ld k1, -8(k0); \
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sd k1, 0(t0); \
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addi k0, -8
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#define REG_SAVE_BASE_DIV_4 (BOOTLOADER_DEBUG_REG_SAVE_BASE >> 2)
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#define HW_INSTRUCTION_BREAKPOINT_STATUS (0xFFFFFFFFFF301000)
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#define HW_INSTRUCTION_BREAKPOINT_ADDRESS(num) (0xFFFFFFFFFF301100 + 0x100 * (num))
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#define HW_INSTRUCTION_BREAKPOINT_ADDRESS_MASK(num) (0xFFFFFFFFFF301108 + 0x100 * (num))
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#define HW_INSTRUCTION_BREAKPOINT_ASID(num) (0xFFFFFFFFFF301110 + 0x100 * (num))
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#define HW_INSTRUCTION_BREAKPOINT_CONTROL(num) (0xFFFFFFFFFF301118 + 0x100 * (num))
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#define HW_DATA_BREAKPOINT_STATUS (0xFFFFFFFFFF302000)
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#define HW_DATA_BREAKPOINT_ADDRESS(num) (0xFFFFFFFFFF302100 + 0x100 * (num))
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#define HW_DATA_BREAKPOINT_ADDRESS_MASK(num) (0xFFFFFFFFFF302108 + 0x100 * (num))
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#define HW_DATA_BREAKPOINT_ASID(num) (0xFFFFFFFFFF302110 + 0x100 * (num))
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#define HW_DATA_BREAKPOINT_CONTROL(num) (0xFFFFFFFFFF302118 + 0x100 * (num))
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#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
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#define loadaddr(reg, addr, shift) \
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dla reg, addr##_all; \
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mfc0 $1, $15, 1; \
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andi $1, 0xff; \
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sll $1, shift; \
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add reg, reg, $1
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#else
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#define loadaddr(reg, addr, shift) \
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dla reg, addr
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#endif
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.set noreorder
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.set noat
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.text
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// Detect debug-mode exception, save all registers, create a stack and then
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// call the stage3 C function.
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.ent __cvmx_debug_handler_stage2
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.globl __cvmx_debug_handler_stage2
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__cvmx_debug_handler_stage2:
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// Save off k0 in COP0_DESAVE
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dmtc0 k0, COP0_DESAVE
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// Use reserved space in kseg0 to save off some temp regs
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mfc0 k0, $15, 1 // read exception base reg.
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andi k0, 0xff // mask off core ID
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sll k0, 12 // multiply by 4096 (512 dwords) DEBUG_NUMREGS
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addiu k0, REG_SAVE_BASE_DIV_4
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addiu k0, REG_SAVE_BASE_DIV_4
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addiu k0, REG_SAVE_BASE_DIV_4
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addiu k0, REG_SAVE_BASE_DIV_4
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// add base offset - after exeption vectors for all cores
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rotr k0, k0, 31 // set bit 31 for kseg0 access
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addi k0, 1
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rotr k0, k0, 1
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// save off k1 and at ($1) off to the bootloader reg save area
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// at is used by dla
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sd $1, 8(k0) // save at for temp usage
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sd k1, 216(k0) // save k1 for temp usage
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// Detect debug-mode exception.
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// If COP0_MULTICOREDEBUG[DExecC] is set,
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dmfc0 k1, COP0_MULTICOREDEBUG
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bbit0 k1, 16, noexc
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nop
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// COP0_DEBUG[DINT,DIB,DDBS,DBp,DSS] are not set and
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dmfc0 k1, COP0_DEBUG
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andi k1, 0x3f
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bnez k1, noexc
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nop
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// COP0_DEBUG[DExecC] is set.
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dmfc0 k1, COP0_DEBUG
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dext k1,k1,10,5
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beqz k1,noexc
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nop
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// We don't handle debug-mode exceptions in delay-slots so DEBUG[DBD]
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// should not be set. If yes spin forever.
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dmfc0 k1, COP0_DEBUG
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1:
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bbit1 k1, 31, 1b
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nop
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// It's a debug-mode exception. Flag the occurence. Also if it's
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// expected just ignore it but returning the subsequent instruction
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// after the fault.
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loadaddr (k1, __cvmx_debug_mode_exception_occured, 3)
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sd k1, 0(k1)
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loadaddr (k1, __cvmx_debug_mode_exception_ignore, 3)
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ld k1, 0(k1)
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beqz k1, noexc
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nop
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// Restore k1 and at from the bootloader reg save area
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ld $1, 8(k0) // save at for temp usage
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ld k1, 216(k0) // save k1 for temp usage
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dmfc0 k0, COP0_DEPC
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// Skip the faulting instruction.
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daddiu k0, 4
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jr k0
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dmfc0 k0, COP0_DESAVE
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noexc:
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loadaddr (k1, __cvmx_debug_save_regs_area, 8)
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// Restore at
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ld $1, 8(k0) // restore at for temp usage
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.irp n, REGS0
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sd $\n, 0(k1)
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addiu k1, 8
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.endr
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move $25, k1
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ld k1, 216(k0) // restore k1 for temp usage
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move k0, $25
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// Store out k0, we can use $25 here because we just saved it
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dmfc0 $25, COP0_DESAVE
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sd $25, 0(k0)
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addiu k0, 8
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.irp n, REGS1
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sd $\n, 0(k0)
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addiu k0, 8
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.endr
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loadaddr(sp, __cvmx_debug_stack_top, 3)
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// Load the stack pointer as a pointer size.
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#ifdef _ABIN32
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lw sp,0(sp)
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#else
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ld sp,0(sp)
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#endif
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jal __cvmx_debug_handler_stage3
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nop
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loadaddr(k0, __cvmx_debug_save_regs_area, 8)
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.irp n, REGS0
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ld $\n, 0(k0)
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addiu k0, 8
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.endr
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// Restore k0 to COP0_DESAVE via k1
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ld k1, 0(k0)
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addiu k0, 8
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dmtc0 k1, COP0_DESAVE
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.irp n, REGS1
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ld $\n, 0(k0)
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addiu k0, 8
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.endr
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dmfc0 k0, COP0_DESAVE
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// Flush the icache; by adding and removing SW breakpoints we change
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// the instruction stream.
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synci 0($0)
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deret
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nop
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.end __cvmx_debug_handler_stage2
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