811ff4dd37
Setting the IG4_REG_RX_TL register to 1 was actually generating an interrupt after 2 bytes were available in the Rx fifo. We need to set the register to 0 to get an interrupt for 1 byte already. Obtained from: DragonflyBSD (02f0bf2) |
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ig4_acpi.c | ||
ig4_iic.c | ||
ig4_pci.c | ||
ig4_reg.h | ||
ig4_var.h |