240 lines
10 KiB
C
240 lines
10 KiB
C
/* $NetBSD: mii.h,v 1.18 2014/06/16 14:43:22 msaitoh Exp $ */
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/*-
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* Copyright (c) 1997 Manuel Bouyer. All rights reserved.
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*
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* Modification to match BSD/OS 3.0 MII interface by Jason R. Thorpe,
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* Numerical Aerospace Simulation Facility, NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_MII_MII_H_
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#define _DEV_MII_MII_H_
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/*
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* Registers common to all PHYs.
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*/
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#define MII_NPHY 32 /* max # of PHYs per MII */
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/*
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* MII commands, used if a device must drive the MII lines
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* manually.
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*/
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#define MII_COMMAND_START 0x01
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#define MII_COMMAND_READ 0x02
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#define MII_COMMAND_WRITE 0x01
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#define MII_COMMAND_ACK 0x02
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#define MII_BMCR 0x00 /* Basic mode control register (rw) */
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#define BMCR_RESET 0x8000 /* reset */
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#define BMCR_LOOP 0x4000 /* loopback */
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#define BMCR_SPEED0 0x2000 /* speed selection (LSB) */
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#define BMCR_AUTOEN 0x1000 /* autonegotiation enable */
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#define BMCR_PDOWN 0x0800 /* power down */
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#define BMCR_ISO 0x0400 /* isolate */
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#define BMCR_STARTNEG 0x0200 /* restart autonegotiation */
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#define BMCR_FDX 0x0100 /* Set duplex mode */
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#define BMCR_CTEST 0x0080 /* collision test */
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#define BMCR_SPEED1 0x0040 /* speed selection (MSB) */
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#define BMCR_S10 0x0000 /* 10 Mb/s */
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#define BMCR_S100 BMCR_SPEED0 /* 100 Mb/s */
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#define BMCR_S1000 BMCR_SPEED1 /* 1000 Mb/s */
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#define BMCR_SPEED(x) ((x) & (BMCR_SPEED0|BMCR_SPEED1))
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#define MII_BMSR 0x01 /* Basic mode status register (ro) */
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#define BMSR_100T4 0x8000 /* 100 base T4 capable */
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#define BMSR_100TXFDX 0x4000 /* 100 base Tx full duplex capable */
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#define BMSR_100TXHDX 0x2000 /* 100 base Tx half duplex capable */
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#define BMSR_10TFDX 0x1000 /* 10 base T full duplex capable */
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#define BMSR_10THDX 0x0800 /* 10 base T half duplex capable */
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#define BMSR_100T2FDX 0x0400 /* 100 base T2 full duplex capable */
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#define BMSR_100T2HDX 0x0200 /* 100 base T2 half duplex capable */
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#define BMSR_EXTSTAT 0x0100 /* Extended status in register 15 */
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#define BMSR_MFPS 0x0040 /* MII Frame Preamble Suppression */
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#define BMSR_ACOMP 0x0020 /* Autonegotiation complete */
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#define BMSR_RFAULT 0x0010 /* Link partner fault */
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#define BMSR_ANEG 0x0008 /* Autonegotiation capable */
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#define BMSR_LINK 0x0004 /* Link status */
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#define BMSR_JABBER 0x0002 /* Jabber detected */
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#define BMSR_EXTCAP 0x0001 /* Extended capability */
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#define BMSR_DEFCAPMASK 0xffffffff
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/*
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* Note that the EXTSTAT bit indicates that there is extended status
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* info available in register 15, but 802.3 section 22.2.4.3 also
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* states that all 1000 Mb/s capable PHYs will set this bit to 1.
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*/
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#define BMSR_MEDIAMASK (BMSR_100T4|BMSR_100TXFDX|BMSR_100TXHDX| \
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BMSR_10TFDX|BMSR_10THDX|BMSR_100T2FDX|BMSR_100T2HDX)
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/*
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* Convert BMSR media capabilities to ANAR bits for autonegotiation.
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* Note the shift chopps off the BMSR_ANEG bit.
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*/
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#define BMSR_MEDIA_TO_ANAR(x) (((x) & BMSR_MEDIAMASK) >> 6)
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#define MII_PHYIDR1 0x02 /* ID register 1 (ro) */
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#define MII_PHYIDR2 0x03 /* ID register 2 (ro) */
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#define IDR2_OUILSB 0xfc00 /* OUI LSB */
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#define IDR2_MODEL 0x03f0 /* vendor model */
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#define IDR2_REV 0x000f /* vendor revision */
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#define MII_ANAR 0x04 /* Autonegotiation advertisement (rw) */
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/* section 28.2.4.1 and 37.2.6.1 */
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#define ANAR_NP 0x8000 /* Next page (ro) */
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#define ANAR_ACK 0x4000 /* link partner abilities acknowledged (ro) */
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#define ANAR_RF 0x2000 /* remote fault (ro) */
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/* Annex 28B.2 */
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#define ANAR_FC 0x0400 /* local device supports PAUSE */
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#define ANAR_T4 0x0200 /* local device supports 100bT4 */
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#define ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */
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#define ANAR_TX 0x0080 /* local device supports 100bTx */
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#define ANAR_10_FD 0x0040 /* local device supports 10bT FD */
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#define ANAR_10 0x0020 /* local device supports 10bT */
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#define ANAR_CSMA 0x0001 /* protocol selector CSMA/CD */
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#define ANAR_PAUSE_NONE (0 << 10)
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#define ANAR_PAUSE_SYM (1 << 10)
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#define ANAR_PAUSE_ASYM (2 << 10)
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#define ANAR_PAUSE_TOWARDS (3 << 10)
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/* Annex 28D */
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#define ANAR_X_FD 0x0020 /* local device supports 1000BASE-X FD */
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#define ANAR_X_HD 0x0040 /* local device supports 1000BASE-X HD */
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#define ANAR_X_PAUSE_NONE (0 << 7)
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#define ANAR_X_PAUSE_SYM (1 << 7)
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#define ANAR_X_PAUSE_ASYM (2 << 7)
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#define ANAR_X_PAUSE_TOWARDS (3 << 7)
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#define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */
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/* section 28.2.4.1 and 37.2.6.1 */
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#define ANLPAR_NP 0x8000 /* Next page (ro) */
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#define ANLPAR_ACK 0x4000 /* link partner accepted ACK (ro) */
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#define ANLPAR_RF 0x2000 /* remote fault (ro) */
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#define ANLPAR_FC 0x0400 /* link partner supports PAUSE */
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#define ANLPAR_T4 0x0200 /* link partner supports 100bT4 */
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#define ANLPAR_TX_FD 0x0100 /* link partner supports 100bTx FD */
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#define ANLPAR_TX 0x0080 /* link partner supports 100bTx */
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#define ANLPAR_10_FD 0x0040 /* link partner supports 10bT FD */
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#define ANLPAR_10 0x0020 /* link partner supports 10bT */
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#define ANLPAR_CSMA 0x0001 /* protocol selector CSMA/CD */
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#define ANLPAR_PAUSE_MASK (3 << 10)
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#define ANLPAR_PAUSE_NONE (0 << 10)
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#define ANLPAR_PAUSE_SYM (1 << 10)
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#define ANLPAR_PAUSE_ASYM (2 << 10)
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#define ANLPAR_PAUSE_TOWARDS (3 << 10)
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#define ANLPAR_X_FD 0x0020 /* local device supports 1000BASE-X FD */
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#define ANLPAR_X_HD 0x0040 /* local device supports 1000BASE-X HD */
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#define ANLPAR_X_PAUSE_MASK (3 << 7)
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#define ANLPAR_X_PAUSE_NONE (0 << 7)
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#define ANLPAR_X_PAUSE_SYM (1 << 7)
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#define ANLPAR_X_PAUSE_ASYM (2 << 7)
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#define ANLPAR_X_PAUSE_TOWARDS (3 << 7)
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#define MII_ANER 0x06 /* Autonegotiation expansion (ro) */
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/* section 28.2.4.1 and 37.2.6.1 */
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#define ANER_MLF 0x0010 /* multiple link detection fault */
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#define ANER_LPNP 0x0008 /* link parter next page-able */
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#define ANER_NP 0x0004 /* next page-able */
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#define ANER_PAGE_RX 0x0002 /* Page received */
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#define ANER_LPAN 0x0001 /* link parter autoneg-able */
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#define MII_ANNP 0x07 /* Autonegotiation next page */
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/* section 28.2.4.1 and 37.2.6.1 */
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#define MII_ANLPRNP 0x08 /* Autonegotiation link partner rx next page */
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/* section 32.5.1 and 37.2.6.1 */
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/* This is also the 1000baseT control register */
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#define MII_100T2CR 0x09 /* 100base-T2 control register */
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#define GTCR_TEST_MASK 0xe000 /* see 802.3ab ss. 40.6.1.1.2 */
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#define GTCR_MAN_MS 0x1000 /* enable manual master/slave control */
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#define GTCR_ADV_MS 0x0800 /* 1 = adv. master, 0 = adv. slave */
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#define GTCR_PORT_TYPE 0x0400 /* 1 = DCE, 0 = DTE (NIC) */
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#define GTCR_ADV_1000TFDX 0x0200 /* adv. 1000baseT FDX */
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#define GTCR_ADV_1000THDX 0x0100 /* adv. 1000baseT HDX */
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/* This is also the 1000baseT status register */
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#define MII_100T2SR 0x0a /* 100base-T2 status register */
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#define GTSR_MAN_MS_FLT 0x8000 /* master/slave config fault */
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#define GTSR_MS_RES 0x4000 /* result: 1 = master, 0 = slave */
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#define GTSR_LRS 0x2000 /* local rx status, 1 = ok */
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#define GTSR_RRS 0x1000 /* remote rx status, 1 = ok */
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#define GTSR_LP_1000TFDX 0x0800 /* link partner 1000baseT FDX capable */
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#define GTSR_LP_1000THDX 0x0400 /* link partner 1000baseT HDX capable */
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#define GTSR_LP_ASM_DIR 0x0200 /* link partner asym. pause dir. capable */
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#define GTSR_IDLE_ERR 0x00ff /* IDLE error count */
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#define MII_PSECR 0x0b /* PSE control register */
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#define PSECR_PACTLMASK 0x000c /* pair control mask */
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#define PSECR_PSEENMASK 0x0003 /* PSE enable mask */
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#define PSECR_PINOUTB 0x0008 /* PSE pinout Alternative B */
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#define PSECR_PINOUTA 0x0004 /* PSE pinout Alternative A */
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#define PSECR_FOPOWTST 0x0002 /* Force Power Test Mode */
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#define PSECR_PSEEN 0x0001 /* PSE Enabled */
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#define PSECR_PSEDIS 0x0000 /* PSE Disabled */
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#define MII_PSESR 0x0c /* PSE status register */
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#define PSESR_PWRDENIED 0x1000 /* Power Denied */
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#define PSESR_VALSIG 0x0800 /* Valid PD signature detected */
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#define PSESR_INVALSIG 0x0400 /* Invalid PD signature detected */
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#define PSESR_SHORTCIRC 0x0200 /* Short circuit condition detected */
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#define PSESR_OVERLOAD 0x0100 /* Overload condition detected */
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#define PSESR_MPSABSENT 0x0080 /* MPS absent condition detected */
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#define PSESR_PDCLMASK 0x0070 /* PD Class mask */
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#define PSESR_STATMASK 0x000e /* PSE Status mask */
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#define PSESR_PAIRCTABL 0x0001 /* PAIR Control Ability */
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#define PSESR_PDCL_4 (4 << 4) /* Class 4 */
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#define PSESR_PDCL_3 (3 << 4) /* Class 3 */
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#define PSESR_PDCL_2 (2 << 4) /* Class 2 */
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#define PSESR_PDCL_1 (1 << 4) /* Class 1 */
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#define PSESR_PDCL_0 (0 << 4) /* Class 0 */
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#define MII_MMDACR 0x0d /* MMD access control register */
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#define MMDACR_FUNCMASK 0xc000 /* function */
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#define MMDACR_DADDRMASK 0x001f /* device address */
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#define MMDACR_FN_ADDRESS (0 << 14) /* address */
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#define MMDACR_FN_DATANPI (1 << 14) /* data, no post increment */
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#define MMDACR_FN_DATAPIRW (2 << 14) /* data, post increment on r/w */
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#define MMDACR_FN_DATAPIW (3 << 14) /* data, post increment on wr only */
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#define MII_MMDAADR 0x0e /* MMD access address data register */
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#define MII_EXTSR 0x0f /* Extended status register */
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#define EXTSR_1000XFDX 0x8000 /* 1000X full-duplex capable */
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#define EXTSR_1000XHDX 0x4000 /* 1000X half-duplex capable */
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#define EXTSR_1000TFDX 0x2000 /* 1000T full-duplex capable */
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#define EXTSR_1000THDX 0x1000 /* 1000T half-duplex capable */
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#define EXTSR_MEDIAMASK (EXTSR_1000XFDX|EXTSR_1000XHDX| \
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EXTSR_1000TFDX|EXTSR_1000THDX)
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#endif /* _DEV_MII_MII_H_ */
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