529 lines
22 KiB
C
529 lines
22 KiB
C
/*-
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* Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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* 3. Neither the names of the above-listed copyright holders nor the names
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* of any contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2 as published by the Free
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* Software Foundation.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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* $FreeBSD$
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*/
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/*
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* Defintions for the Atheros Wireless LAN controller driver.
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*/
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#ifndef _DEV_ATH_ATHVAR_H
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#define _DEV_ATH_ATHVAR_H
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#include <sys/taskqueue.h>
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#include <contrib/dev/ath/ah.h>
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#include <net80211/ieee80211_radiotap.h>
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#include <dev/ath/if_athioctl.h>
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#include <dev/ath/if_athrate.h>
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#define ATH_TIMEOUT 1000
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#define ATH_RXBUF 40 /* number of RX buffers */
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#define ATH_TXBUF 100 /* number of TX buffers */
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#define ATH_TXDESC 10 /* number of descriptors per buffer */
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#define ATH_TXMAXTRY 11 /* max number of transmit attempts */
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#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */
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#define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */
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#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */
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#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */
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/*
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* The key cache is used for h/w cipher state and also for
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* tracking station state such as the current tx antenna.
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* We also setup a mapping table between key cache slot indices
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* and station state to short-circuit node lookups on rx.
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* Different parts have different size key caches. We handle
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* up to ATH_KEYMAX entries (could dynamically allocate state).
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*/
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#define ATH_KEYMAX 128 /* max key cache size we handle */
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#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */
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/* driver-specific node state */
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struct ath_node {
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struct ieee80211_node an_node; /* base class */
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u_int8_t an_tx_mgtrate; /* h/w rate for management/ctl frames */
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u_int8_t an_tx_mgtratesp;/* short preamble h/w rate for " " */
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u_int32_t an_avgrssi; /* average rssi over all rx frames */
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HAL_NODE_STATS an_halstats; /* rssi statistics used by hal */
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/* variable-length rate control state follows */
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};
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#define ATH_NODE(ni) ((struct ath_node *)(ni))
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#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni))
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#define ATH_RSSI_LPF_LEN 10
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#define ATH_RSSI_DUMMY_MARKER 0x127
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#define ATH_EP_MUL(x, mul) ((x) * (mul))
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#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER))
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#define ATH_LPF_RSSI(x, y, len) \
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((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
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#define ATH_RSSI_LPF(x, y) do { \
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if ((y) >= -20) \
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x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
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} while (0)
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struct ath_buf {
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STAILQ_ENTRY(ath_buf) bf_list;
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int bf_nseg;
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struct ath_desc *bf_desc; /* virtual addr of desc */
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bus_addr_t bf_daddr; /* physical addr of desc */
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bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */
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struct mbuf *bf_m; /* mbuf for buf */
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struct ieee80211_node *bf_node; /* pointer to the node */
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bus_size_t bf_mapsize;
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#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */
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bus_dma_segment_t bf_segs[ATH_MAX_SCATTER];
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};
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typedef STAILQ_HEAD(, ath_buf) ath_bufhead;
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/*
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* DMA state for tx/rx descriptors.
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*/
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struct ath_descdma {
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const char* dd_name;
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struct ath_desc *dd_desc; /* descriptors */
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bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */
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bus_addr_t dd_desc_len; /* size of dd_desc */
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bus_dma_segment_t dd_dseg;
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bus_dma_tag_t dd_dmat; /* bus DMA tag */
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bus_dmamap_t dd_dmamap; /* DMA map for descriptors */
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struct ath_buf *dd_bufptr; /* associated buffers */
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};
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/*
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* Data transmit queue state. One of these exists for each
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* hardware transmit queue. Packets sent to us from above
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* are assigned to queues based on their priority. Not all
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* devices support a complete set of hardware transmit queues.
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* For those devices the array sc_ac2q will map multiple
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* priorities to fewer hardware queues (typically all to one
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* hardware queue).
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*/
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struct ath_txq {
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u_int axq_qnum; /* hardware q number */
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u_int axq_depth; /* queue depth (stat only) */
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u_int axq_intrcnt; /* interrupt count */
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u_int32_t *axq_link; /* link ptr in last TX desc */
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STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */
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struct mtx axq_lock; /* lock on q and link */
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/*
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* State for patching up CTS when bursting.
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*/
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struct ath_buf *axq_linkbuf; /* va of last buffer */
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struct ath_desc *axq_lastdsWithCTS;
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/* first desc of last descriptor
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* that contains CTS
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*/
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struct ath_desc *axq_gatingds; /* final desc of the gating desc
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* that determines whether
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* lastdsWithCTS has been DMA'ed
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* or not
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*/
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};
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#define ATH_TXQ_LOCK_INIT(_sc, _tq) \
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mtx_init(&(_tq)->axq_lock, \
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device_get_nameunit((_sc)->sc_dev), "xmit q", MTX_DEF)
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#define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock)
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#define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock)
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#define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock)
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#define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED)
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#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
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STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \
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(_tq)->axq_depth++; \
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} while (0)
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#define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \
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STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \
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(_tq)->axq_depth--; \
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} while (0)
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struct ath_softc {
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struct arpcom sc_arp; /* interface common */
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struct ath_stats sc_stats; /* interface statistics */
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struct ieee80211com sc_ic; /* IEEE 802.11 common */
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int sc_regdomain;
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int sc_countrycode;
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int sc_debug;
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void (*sc_recv_mgmt)(struct ieee80211com *,
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struct mbuf *,
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struct ieee80211_node *,
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int, int, u_int32_t);
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int (*sc_newstate)(struct ieee80211com *,
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enum ieee80211_state, int);
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void (*sc_node_free)(struct ieee80211_node *);
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device_t sc_dev;
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bus_space_tag_t sc_st; /* bus space tag */
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bus_space_handle_t sc_sh; /* bus space handle */
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bus_dma_tag_t sc_dmat; /* bus DMA tag */
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struct mtx sc_mtx; /* master lock (recursive) */
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struct ath_hal *sc_ah; /* Atheros HAL */
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struct ath_ratectrl *sc_rc; /* tx rate control support */
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void (*sc_setdefantenna)(struct ath_softc *, u_int);
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unsigned int sc_invalid : 1, /* disable hardware accesses */
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sc_mrretry : 1, /* multi-rate retry support */
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sc_softled : 1, /* enable LED gpio status */
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sc_splitmic: 1, /* split TKIP MIC keys */
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sc_needmib : 1, /* enable MIB stats intr */
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sc_hasdiversity : 1,/* rx diversity available */
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sc_diversity : 1,/* enable rx diversity */
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sc_hasveol : 1, /* tx VEOL support */
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sc_hastpc : 1, /* per-packet TPC support */
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sc_ledstate: 1, /* LED on/off state */
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sc_blinking: 1, /* LED blink operation active */
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sc_mcastkey: 1, /* mcast key cache search */
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sc_hasclrkey:1; /* CLR key supported */
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/* rate tables */
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const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX];
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const HAL_RATE_TABLE *sc_currates; /* current rate table */
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enum ieee80211_phymode sc_curmode; /* current phy mode */
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u_int16_t sc_curtxpow; /* current tx power limit */
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HAL_CHANNEL sc_curchan; /* current h/w channel */
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u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */
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struct {
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u_int8_t ieeerate; /* IEEE rate */
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u_int8_t rxflags; /* radiotap rx flags */
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u_int8_t txflags; /* radiotap tx flags */
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u_int16_t ledon; /* softled on time */
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u_int16_t ledoff; /* softled off time */
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} sc_hwmap[32]; /* h/w rate ix mappings */
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u_int8_t sc_protrix; /* protection rate index */
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u_int sc_txantenna; /* tx antenna (fixed or auto) */
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HAL_INT sc_imask; /* interrupt mask copy */
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u_int sc_keymax; /* size of key cache */
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u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */
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struct ieee80211_node *sc_keyixmap[ATH_KEYMAX];/* key ix->node map */
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u_int sc_ledpin; /* GPIO pin for driving LED */
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u_int sc_ledon; /* pin setting for LED on */
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u_int sc_ledidle; /* idle polling interval */
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int sc_ledevent; /* time of last LED event */
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u_int8_t sc_rxrate; /* current rx rate for LED */
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u_int8_t sc_txrate; /* current tx rate for LED */
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u_int16_t sc_ledoff; /* off time for current blink */
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struct callout sc_ledtimer; /* led off timer */
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struct bpf_if *sc_drvbpf;
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union {
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struct ath_tx_radiotap_header th;
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u_int8_t pad[64];
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} u_tx_rt;
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int sc_tx_th_len;
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union {
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struct ath_rx_radiotap_header th;
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u_int8_t pad[64];
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} u_rx_rt;
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int sc_rx_th_len;
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struct task sc_fataltask; /* fatal int processing */
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struct ath_descdma sc_rxdma; /* RX descriptos */
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ath_bufhead sc_rxbuf; /* receive buffer */
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u_int32_t *sc_rxlink; /* link ptr in last RX desc */
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struct task sc_rxtask; /* rx int processing */
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struct task sc_rxorntask; /* rxorn int processing */
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u_int8_t sc_defant; /* current default antenna */
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u_int8_t sc_rxotherant; /* rx's on non-default antenna*/
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struct ath_descdma sc_txdma; /* TX descriptors */
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ath_bufhead sc_txbuf; /* transmit buffer */
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struct mtx sc_txbuflock; /* txbuf lock */
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int sc_tx_timer; /* transmit timeout */
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u_int sc_txqsetup; /* h/w queues setup */
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u_int sc_txintrperiod;/* tx interrupt batching */
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struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
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struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */
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struct task sc_txtask; /* tx int processing */
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struct ath_descdma sc_bdma; /* beacon descriptors */
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ath_bufhead sc_bbuf; /* beacon buffers */
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u_int sc_bhalq; /* HAL q for outgoing beacons */
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u_int sc_bmisscount; /* missed beacon transmits */
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u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */
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struct ath_txq *sc_cabq; /* tx q for cab frames */
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struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */
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struct task sc_bmisstask; /* bmiss int processing */
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struct task sc_bstucktask; /* stuck beacon processing */
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enum {
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OK, /* no change needed */
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UPDATE, /* update pending */
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COMMIT /* beacon sent, commit change */
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} sc_updateslot; /* slot time update fsm */
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struct callout sc_cal_ch; /* callout handle for cals */
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struct callout sc_scan_ch; /* callout handle for scan */
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};
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#define sc_if sc_arp.ac_if
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#define sc_tx_th u_tx_rt.th
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#define sc_rx_th u_rx_rt.th
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#define ATH_LOCK_INIT(_sc) \
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mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
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MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE)
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#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
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#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
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#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
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#define ATH_TXBUF_LOCK_INIT(_sc) \
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mtx_init(&(_sc)->sc_txbuflock, \
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device_get_nameunit((_sc)->sc_dev), "xmit buf q", MTX_DEF)
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#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock)
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#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock)
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#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock)
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#define ATH_TXBUF_LOCK_ASSERT(_sc) \
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mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED)
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int ath_attach(u_int16_t, struct ath_softc *);
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int ath_detach(struct ath_softc *);
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void ath_resume(struct ath_softc *);
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void ath_suspend(struct ath_softc *);
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void ath_shutdown(struct ath_softc *);
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void ath_intr(void *);
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/*
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* HAL definitions to comply with local coding convention.
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*/
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#define ath_hal_detach(_ah) \
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((*(_ah)->ah_detach)((_ah)))
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#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \
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((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
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#define ath_hal_getratetable(_ah, _mode) \
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((*(_ah)->ah_getRateTable)((_ah), (_mode)))
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#define ath_hal_getmac(_ah, _mac) \
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((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
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#define ath_hal_setmac(_ah, _mac) \
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((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
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#define ath_hal_intrset(_ah, _mask) \
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((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
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#define ath_hal_intrget(_ah) \
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((*(_ah)->ah_getInterrupts)((_ah)))
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#define ath_hal_intrpend(_ah) \
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((*(_ah)->ah_isInterruptPending)((_ah)))
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#define ath_hal_getisr(_ah, _pmask) \
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((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
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#define ath_hal_updatetxtriglevel(_ah, _inc) \
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((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
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#define ath_hal_setpower(_ah, _mode, _sleepduration) \
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((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE, (_sleepduration)))
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#define ath_hal_keycachesize(_ah) \
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((*(_ah)->ah_getKeyCacheSize)((_ah)))
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#define ath_hal_keyreset(_ah, _ix) \
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((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
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#define ath_hal_keyset(_ah, _ix, _pk, _mac) \
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((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
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#define ath_hal_keyisvalid(_ah, _ix) \
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(((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
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#define ath_hal_keysetmac(_ah, _ix, _mac) \
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((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
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#define ath_hal_getrxfilter(_ah) \
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((*(_ah)->ah_getRxFilter)((_ah)))
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#define ath_hal_setrxfilter(_ah, _filter) \
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((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
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#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \
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((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
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#define ath_hal_waitforbeacon(_ah, _bf) \
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((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
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#define ath_hal_putrxbuf(_ah, _bufaddr) \
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((*(_ah)->ah_setRxDP)((_ah), (_bufaddr)))
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#define ath_hal_gettsf32(_ah) \
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((*(_ah)->ah_getTsf32)((_ah)))
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#define ath_hal_gettsf64(_ah) \
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((*(_ah)->ah_getTsf64)((_ah)))
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#define ath_hal_resettsf(_ah) \
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((*(_ah)->ah_resetTsf)((_ah)))
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#define ath_hal_rxena(_ah) \
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((*(_ah)->ah_enableReceive)((_ah)))
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#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \
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((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
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#define ath_hal_gettxbuf(_ah, _q) \
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((*(_ah)->ah_getTxDP)((_ah), (_q)))
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#define ath_hal_numtxpending(_ah, _q) \
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((*(_ah)->ah_numTxPending)((_ah), (_q)))
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#define ath_hal_getrxbuf(_ah) \
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((*(_ah)->ah_getRxDP)((_ah)))
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#define ath_hal_txstart(_ah, _q) \
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((*(_ah)->ah_startTxDma)((_ah), (_q)))
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#define ath_hal_setchannel(_ah, _chan) \
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((*(_ah)->ah_setChannel)((_ah), (_chan)))
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#define ath_hal_calibrate(_ah, _chan) \
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((*(_ah)->ah_perCalibration)((_ah), (_chan)))
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#define ath_hal_setledstate(_ah, _state) \
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((*(_ah)->ah_setLedState)((_ah), (_state)))
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#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \
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((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod)))
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#define ath_hal_beaconreset(_ah) \
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((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
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#define ath_hal_beacontimers(_ah, _bs) \
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((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs)))
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#define ath_hal_setassocid(_ah, _bss, _associd) \
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((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd)))
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#define ath_hal_phydisable(_ah) \
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((*(_ah)->ah_phyDisable)((_ah)))
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#define ath_hal_setopmode(_ah) \
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((*(_ah)->ah_setPCUConfig)((_ah)))
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#define ath_hal_stoptxdma(_ah, _qnum) \
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((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
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#define ath_hal_stoppcurecv(_ah) \
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((*(_ah)->ah_stopPcuReceive)((_ah)))
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#define ath_hal_startpcurecv(_ah) \
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((*(_ah)->ah_startPcuReceive)((_ah)))
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#define ath_hal_stopdmarecv(_ah) \
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((*(_ah)->ah_stopDmaReceive)((_ah)))
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#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \
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((*(_ah)->ah_getDiagState)((_ah), (_id), \
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(_indata), (_insize), (_outdata), (_outsize)))
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#define ath_hal_setuptxqueue(_ah, _type, _irq) \
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((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
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#define ath_hal_resettxqueue(_ah, _q) \
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((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
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#define ath_hal_releasetxqueue(_ah, _q) \
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((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
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#define ath_hal_gettxqueueprops(_ah, _q, _qi) \
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((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi)))
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#define ath_hal_settxqueueprops(_ah, _q, _qi) \
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((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi)))
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#define ath_hal_getrfgain(_ah) \
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((*(_ah)->ah_getRfGain)((_ah)))
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#define ath_hal_getdefantenna(_ah) \
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((*(_ah)->ah_getDefAntenna)((_ah)))
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#define ath_hal_setdefantenna(_ah, _ant) \
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((*(_ah)->ah_setDefAntenna)((_ah), (_ant)))
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#define ath_hal_rxmonitor(_ah, _arg) \
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((*(_ah)->ah_rxMonitor)((_ah), (_arg)))
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#define ath_hal_mibevent(_ah, _stats) \
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((*(_ah)->ah_procMibEvent)((_ah), (_stats)))
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#define ath_hal_setslottime(_ah, _us) \
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((*(_ah)->ah_setSlotTime)((_ah), (_us)))
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#define ath_hal_getslottime(_ah) \
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((*(_ah)->ah_getSlotTime)((_ah)))
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#define ath_hal_setacktimeout(_ah, _us) \
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((*(_ah)->ah_setAckTimeout)((_ah), (_us)))
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#define ath_hal_getacktimeout(_ah) \
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((*(_ah)->ah_getAckTimeout)((_ah)))
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#define ath_hal_setctstimeout(_ah, _us) \
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((*(_ah)->ah_setCTSTimeout)((_ah), (_us)))
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#define ath_hal_getctstimeout(_ah) \
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((*(_ah)->ah_getCTSTimeout)((_ah)))
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#define ath_hal_getcapability(_ah, _cap, _param, _result) \
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((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
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#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \
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((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status)))
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#define ath_hal_ciphersupported(_ah, _cipher) \
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(ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK)
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#define ath_hal_getregdomain(_ah, _prd) \
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ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd))
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#define ath_hal_getcountrycode(_ah, _pcc) \
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(*(_pcc) = (_ah)->ah_countryCode)
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#define ath_hal_tkipsplit(_ah) \
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(ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK)
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#define ath_hal_hwphycounters(_ah) \
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(ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK)
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#define ath_hal_hasdiversity(_ah) \
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(ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK)
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#define ath_hal_getdiversity(_ah) \
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(ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK)
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#define ath_hal_setdiversity(_ah, _v) \
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ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL)
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#define ath_hal_getdiag(_ah, _pv) \
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(ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK)
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#define ath_hal_setdiag(_ah, _v) \
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ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL)
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#define ath_hal_getnumtxqueues(_ah, _pv) \
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(ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK)
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#define ath_hal_hasveol(_ah) \
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(ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK)
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|
#define ath_hal_hastxpowlimit(_ah) \
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(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK)
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#define ath_hal_settxpowlimit(_ah, _pow) \
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((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow)))
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|
#define ath_hal_gettxpowlimit(_ah, _ppow) \
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(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK)
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|
#define ath_hal_getmaxtxpow(_ah, _ppow) \
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(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK)
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|
#define ath_hal_gettpscale(_ah, _scale) \
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|
(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK)
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|
#define ath_hal_settpscale(_ah, _v) \
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ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL)
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|
#define ath_hal_hastpc(_ah) \
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|
(ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK)
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|
#define ath_hal_gettpc(_ah) \
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|
(ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK)
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|
#define ath_hal_settpc(_ah, _v) \
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ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL)
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|
#define ath_hal_hasbursting(_ah) \
|
|
(ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK)
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|
#ifdef notyet
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|
#define ath_hal_hasmcastkeysearch(_ah) \
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|
(ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK)
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|
#define ath_hal_getmcastkeysearch(_ah) \
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|
(ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK)
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|
#else
|
|
#define ath_hal_getmcastkeysearch(_ah) 0
|
|
#endif
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|
|
|
#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
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|
((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
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|
#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext) \
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((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext)))
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|
#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
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_txr0, _txtr0, _keyix, _ant, _flags, \
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|
_rtsrate, _rtsdura) \
|
|
((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
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|
(_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
|
|
(_flags), (_rtsrate), (_rtsdura)))
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|
#define ath_hal_setupxtxdesc(_ah, _ds, \
|
|
_txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
|
|
((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
|
|
(_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
|
|
#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \
|
|
((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0)))
|
|
#define ath_hal_txprocdesc(_ah, _ds) \
|
|
((*(_ah)->ah_procTxDesc)((_ah), (_ds)))
|
|
#define ath_hal_updateCTSForBursting(_ah, _ds, _prevds, _prevdsWithCTS, \
|
|
_gatingds, _txOpLimit, _ctsDuration) \
|
|
((*(_ah)->ah_updateCTSForBursting)((_ah), (_ds), (_prevds), \
|
|
(_prevdsWithCTS), (_gatingds), (_txOpLimit), (_ctsDuration)))
|
|
|
|
#define ath_hal_gpioCfgOutput(_ah, _gpio) \
|
|
((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio)))
|
|
#define ath_hal_gpioset(_ah, _gpio, _b) \
|
|
((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))
|
|
|
|
#endif /* _DEV_ATH_ATHVAR_H */
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